1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2018 Nexenta Systems, Inc. 14 * Copyright 2016 The MathWorks, Inc. All rights reserved. 15 * Copyright 2019 Joyent, Inc. 16 * Copyright 2019 Western Digital Corporation. 17 * Copyright 2021 Oxide Computer Company. 18 * Copyright 2022 OmniOS Community Edition (OmniOSce) Association. 19 */ 20 21 #ifndef _NVME_VAR_H 22 #define _NVME_VAR_H 23 24 #include <sys/ddi.h> 25 #include <sys/sunddi.h> 26 #include <sys/blkdev.h> 27 #include <sys/taskq_impl.h> 28 #include <sys/list.h> 29 30 /* 31 * NVMe driver state 32 */ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #define NVME_FMA_INIT 0x1 39 #define NVME_REGS_MAPPED 0x2 40 #define NVME_ADMIN_QUEUE 0x4 41 #define NVME_CTRL_LIMITS 0x8 42 #define NVME_INTERRUPTS 0x10 43 #define NVME_UFM_INIT 0x20 44 45 #define NVME_MIN_ADMIN_QUEUE_LEN 16 46 #define NVME_MIN_IO_QUEUE_LEN 16 47 #define NVME_DEFAULT_ADMIN_QUEUE_LEN 256 48 #define NVME_DEFAULT_IO_QUEUE_LEN 1024 49 #define NVME_DEFAULT_ASYNC_EVENT_LIMIT 10 50 #define NVME_MIN_ASYNC_EVENT_LIMIT 1 51 #define NVME_DEFAULT_MIN_BLOCK_SIZE 512 52 53 54 typedef struct nvme nvme_t; 55 typedef struct nvme_namespace nvme_namespace_t; 56 typedef struct nvme_minor_state nvme_minor_state_t; 57 typedef struct nvme_dma nvme_dma_t; 58 typedef struct nvme_cmd nvme_cmd_t; 59 typedef struct nvme_cq nvme_cq_t; 60 typedef struct nvme_qpair nvme_qpair_t; 61 typedef struct nvme_task_arg nvme_task_arg_t; 62 63 struct nvme_minor_state { 64 kmutex_t nm_mutex; 65 boolean_t nm_oexcl; 66 uint_t nm_ocnt; 67 }; 68 69 struct nvme_dma { 70 ddi_dma_handle_t nd_dmah; 71 ddi_acc_handle_t nd_acch; 72 ddi_dma_cookie_t nd_cookie; 73 uint_t nd_ncookie; 74 caddr_t nd_memp; 75 size_t nd_len; 76 boolean_t nd_cached; 77 }; 78 79 struct nvme_cmd { 80 struct list_node nc_list; 81 82 nvme_sqe_t nc_sqe; 83 nvme_cqe_t nc_cqe; 84 85 void (*nc_callback)(void *); 86 bd_xfer_t *nc_xfer; 87 boolean_t nc_completed; 88 boolean_t nc_dontpanic; 89 uint16_t nc_sqid; 90 91 nvme_dma_t *nc_dma; 92 nvme_dma_t *nc_prp; /* DMA for PRP lists */ 93 94 kmutex_t nc_mutex; 95 kcondvar_t nc_cv; 96 97 taskq_ent_t nc_tqent; 98 nvme_t *nc_nvme; 99 }; 100 101 struct nvme_cq { 102 size_t ncq_nentry; 103 uint16_t ncq_id; 104 105 nvme_dma_t *ncq_dma; 106 nvme_cqe_t *ncq_cq; 107 uint_t ncq_head; 108 uint_t ncq_tail; 109 uintptr_t ncq_hdbl; 110 int ncq_phase; 111 112 taskq_t *ncq_cmd_taskq; 113 114 kmutex_t ncq_mutex; 115 }; 116 117 struct nvme_qpair { 118 size_t nq_nentry; 119 120 /* submission fields */ 121 nvme_dma_t *nq_sqdma; 122 nvme_sqe_t *nq_sq; 123 uint_t nq_sqhead; 124 uint_t nq_sqtail; 125 uintptr_t nq_sqtdbl; 126 127 /* completion */ 128 nvme_cq_t *nq_cq; 129 130 /* shared structures for completion and submission */ 131 nvme_cmd_t **nq_cmd; /* active command array */ 132 uint16_t nq_next_cmd; /* next potential empty queue slot */ 133 uint_t nq_active_cmds; /* number of active cmds */ 134 135 kmutex_t nq_mutex; /* protects shared state */ 136 ksema_t nq_sema; /* semaphore to ensure q always has >= 1 empty slot */ 137 }; 138 139 struct nvme { 140 dev_info_t *n_dip; 141 int n_progress; 142 143 caddr_t n_regs; 144 ddi_acc_handle_t n_regh; 145 146 kmem_cache_t *n_cmd_cache; 147 kmem_cache_t *n_prp_cache; 148 149 size_t n_inth_sz; 150 ddi_intr_handle_t *n_inth; 151 int n_intr_cnt; 152 uint_t n_intr_pri; 153 int n_intr_cap; 154 int n_intr_type; 155 int n_intr_types; 156 157 char *n_product; 158 char *n_vendor; 159 160 nvme_version_t n_version; 161 boolean_t n_dead; 162 boolean_t n_strict_version; 163 boolean_t n_ignore_unknown_vendor_status; 164 uint32_t n_admin_queue_len; 165 uint32_t n_io_squeue_len; 166 uint32_t n_io_cqueue_len; 167 uint16_t n_async_event_limit; 168 uint_t n_min_block_size; 169 uint16_t n_abort_command_limit; 170 uint64_t n_max_data_transfer_size; 171 boolean_t n_write_cache_present; 172 boolean_t n_write_cache_enabled; 173 int n_error_log_len; 174 boolean_t n_lba_range_supported; 175 boolean_t n_auto_pst_supported; 176 boolean_t n_async_event_supported; 177 boolean_t n_progress_supported; 178 int n_submission_queues; 179 int n_completion_queues; 180 181 int n_nssr_supported; 182 int n_doorbell_stride; 183 int n_timeout; 184 int n_arbitration_mechanisms; 185 int n_cont_queues_reqd; 186 int n_max_queue_entries; 187 int n_pageshift; 188 int n_pagesize; 189 190 int n_namespace_count; 191 uint_t n_namespaces_attachable; 192 uint_t n_ioq_count; 193 uint_t n_cq_count; 194 195 nvme_identify_ctrl_t *n_idctl; 196 197 /* Pointer to the admin queue, which is always queue 0 in n_ioq. */ 198 nvme_qpair_t *n_adminq; 199 /* 200 * All command queues, including the admin queue. 201 * Its length is: n_ioq_count + 1. 202 */ 203 nvme_qpair_t **n_ioq; 204 nvme_cq_t **n_cq; 205 206 nvme_namespace_t *n_ns; 207 208 ddi_dma_attr_t n_queue_dma_attr; 209 ddi_dma_attr_t n_prp_dma_attr; 210 ddi_dma_attr_t n_sgl_dma_attr; 211 ddi_device_acc_attr_t n_reg_acc_attr; 212 ddi_iblock_cookie_t n_fm_ibc; 213 int n_fm_cap; 214 215 ksema_t n_abort_sema; 216 217 /* state for devctl minor node */ 218 nvme_minor_state_t n_minor; 219 220 /* errors detected by driver */ 221 uint32_t n_dma_bind_err; 222 uint32_t n_abort_failed; 223 uint32_t n_cmd_timeout; 224 uint32_t n_cmd_aborted; 225 uint32_t n_wrong_logpage; 226 uint32_t n_unknown_logpage; 227 uint32_t n_too_many_cookies; 228 229 /* errors detected by hardware */ 230 uint32_t n_data_xfr_err; 231 uint32_t n_internal_err; 232 uint32_t n_abort_rq_err; 233 uint32_t n_abort_sq_del; 234 uint32_t n_nvm_cap_exc; 235 uint32_t n_nvm_ns_notrdy; 236 uint32_t n_inv_cq_err; 237 uint32_t n_inv_qid_err; 238 uint32_t n_max_qsz_exc; 239 uint32_t n_inv_int_vect; 240 uint32_t n_inv_log_page; 241 uint32_t n_inv_format; 242 uint32_t n_inv_q_del; 243 uint32_t n_cnfl_attr; 244 uint32_t n_inv_prot; 245 uint32_t n_readonly; 246 247 /* errors reported by asynchronous events */ 248 uint32_t n_diagfail_event; 249 uint32_t n_persistent_event; 250 uint32_t n_transient_event; 251 uint32_t n_fw_load_event; 252 uint32_t n_reliability_event; 253 uint32_t n_temperature_event; 254 uint32_t n_spare_event; 255 uint32_t n_vendor_event; 256 uint32_t n_notice_event; 257 uint32_t n_unknown_event; 258 259 /* hot removal NDI event handling */ 260 ddi_eventcookie_t n_rm_cookie; 261 ddi_callback_id_t n_ev_rm_cb_id; 262 263 /* DDI UFM handle */ 264 ddi_ufm_handle_t *n_ufmh; 265 /* Cached Firmware Slot Information log page */ 266 nvme_fwslot_log_t *n_fwslot; 267 /* Lock protecting the cached firmware slot info */ 268 kmutex_t n_fwslot_mutex; 269 }; 270 271 struct nvme_namespace { 272 nvme_t *ns_nvme; 273 uint8_t ns_eui64[8]; 274 char ns_name[17]; 275 276 bd_handle_t ns_bd_hdl; 277 278 uint32_t ns_id; 279 size_t ns_block_count; 280 size_t ns_block_size; 281 size_t ns_best_block_size; 282 283 boolean_t ns_ignore; 284 285 nvme_identify_nsid_t *ns_idns; 286 287 /* state for attachment point minor node */ 288 nvme_minor_state_t ns_minor; 289 290 /* 291 * If a namespace has no EUI64, we create a devid in 292 * nvme_prepare_devid(). 293 */ 294 char *ns_devid; 295 }; 296 297 struct nvme_task_arg { 298 nvme_t *nt_nvme; 299 nvme_cmd_t *nt_cmd; 300 }; 301 302 #ifdef __cplusplus 303 } 304 #endif 305 306 #endif /* _NVME_VAR_H */ 307