1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2018 Nexenta Systems, Inc. 14 * Copyright 2016 Tegile Systems, Inc. All rights reserved. 15 * Copyright (c) 2016 The MathWorks, Inc. All rights reserved. 16 * Copyright 2018 Joyent, Inc. 17 */ 18 19 /* 20 * blkdev driver for NVMe compliant storage devices 21 * 22 * This driver was written to conform to version 1.2.1 of the NVMe 23 * specification. It may work with newer versions, but that is completely 24 * untested and disabled by default. 25 * 26 * The driver has only been tested on x86 systems and will not work on big- 27 * endian systems without changes to the code accessing registers and data 28 * structures used by the hardware. 29 * 30 * 31 * Interrupt Usage: 32 * 33 * The driver will use a single interrupt while configuring the device as the 34 * specification requires, but contrary to the specification it will try to use 35 * a single-message MSI(-X) or FIXED interrupt. Later in the attach process it 36 * will switch to multiple-message MSI(-X) if supported. The driver wants to 37 * have one interrupt vector per CPU, but it will work correctly if less are 38 * available. Interrupts can be shared by queues, the interrupt handler will 39 * iterate through the I/O queue array by steps of n_intr_cnt. Usually only 40 * the admin queue will share an interrupt with one I/O queue. The interrupt 41 * handler will retrieve completed commands from all queues sharing an interrupt 42 * vector and will post them to a taskq for completion processing. 43 * 44 * 45 * Command Processing: 46 * 47 * NVMe devices can have up to 65535 I/O queue pairs, with each queue holding up 48 * to 65536 I/O commands. The driver will configure one I/O queue pair per 49 * available interrupt vector, with the queue length usually much smaller than 50 * the maximum of 65536. If the hardware doesn't provide enough queues, fewer 51 * interrupt vectors will be used. 52 * 53 * Additionally the hardware provides a single special admin queue pair that can 54 * hold up to 4096 admin commands. 55 * 56 * From the hardware perspective both queues of a queue pair are independent, 57 * but they share some driver state: the command array (holding pointers to 58 * commands currently being processed by the hardware) and the active command 59 * counter. Access to a queue pair and the shared state is protected by 60 * nq_mutex. 61 * 62 * When a command is submitted to a queue pair the active command counter is 63 * incremented and a pointer to the command is stored in the command array. The 64 * array index is used as command identifier (CID) in the submission queue 65 * entry. Some commands may take a very long time to complete, and if the queue 66 * wraps around in that time a submission may find the next array slot to still 67 * be used by a long-running command. In this case the array is sequentially 68 * searched for the next free slot. The length of the command array is the same 69 * as the configured queue length. Queue overrun is prevented by the semaphore, 70 * so a command submission may block if the queue is full. 71 * 72 * 73 * Polled I/O Support: 74 * 75 * For kernel core dump support the driver can do polled I/O. As interrupts are 76 * turned off while dumping the driver will just submit a command in the regular 77 * way, and then repeatedly attempt a command retrieval until it gets the 78 * command back. 79 * 80 * 81 * Namespace Support: 82 * 83 * NVMe devices can have multiple namespaces, each being a independent data 84 * store. The driver supports multiple namespaces and creates a blkdev interface 85 * for each namespace found. Namespaces can have various attributes to support 86 * protection information. This driver does not support any of this and ignores 87 * namespaces that have these attributes. 88 * 89 * As of NVMe 1.1 namespaces can have an 64bit Extended Unique Identifier 90 * (EUI64). This driver uses the EUI64 if present to generate the devid and 91 * passes it to blkdev to use it in the device node names. As this is currently 92 * untested namespaces with EUI64 are ignored by default. 93 * 94 * We currently support only (2 << NVME_MINOR_INST_SHIFT) - 2 namespaces in a 95 * single controller. This is an artificial limit imposed by the driver to be 96 * able to address a reasonable number of controllers and namespaces using a 97 * 32bit minor node number. 98 * 99 * 100 * Minor nodes: 101 * 102 * For each NVMe device the driver exposes one minor node for the controller and 103 * one minor node for each namespace. The only operations supported by those 104 * minor nodes are open(9E), close(9E), and ioctl(9E). This serves as the 105 * interface for the nvmeadm(1M) utility. 106 * 107 * 108 * Blkdev Interface: 109 * 110 * This driver uses blkdev to do all the heavy lifting involved with presenting 111 * a disk device to the system. As a result, the processing of I/O requests is 112 * relatively simple as blkdev takes care of partitioning, boundary checks, DMA 113 * setup, and splitting of transfers into manageable chunks. 114 * 115 * I/O requests coming in from blkdev are turned into NVM commands and posted to 116 * an I/O queue. The queue is selected by taking the CPU id modulo the number of 117 * queues. There is currently no timeout handling of I/O commands. 118 * 119 * Blkdev also supports querying device/media information and generating a 120 * devid. The driver reports the best block size as determined by the namespace 121 * format back to blkdev as physical block size to support partition and block 122 * alignment. The devid is either based on the namespace EUI64, if present, or 123 * composed using the device vendor ID, model number, serial number, and the 124 * namespace ID. 125 * 126 * 127 * Error Handling: 128 * 129 * Error handling is currently limited to detecting fatal hardware errors, 130 * either by asynchronous events, or synchronously through command status or 131 * admin command timeouts. In case of severe errors the device is fenced off, 132 * all further requests will return EIO. FMA is then called to fault the device. 133 * 134 * The hardware has a limit for outstanding asynchronous event requests. Before 135 * this limit is known the driver assumes it is at least 1 and posts a single 136 * asynchronous request. Later when the limit is known more asynchronous event 137 * requests are posted to allow quicker reception of error information. When an 138 * asynchronous event is posted by the hardware the driver will parse the error 139 * status fields and log information or fault the device, depending on the 140 * severity of the asynchronous event. The asynchronous event request is then 141 * reused and posted to the admin queue again. 142 * 143 * On command completion the command status is checked for errors. In case of 144 * errors indicating a driver bug the driver panics. Almost all other error 145 * status values just cause EIO to be returned. 146 * 147 * Command timeouts are currently detected for all admin commands except 148 * asynchronous event requests. If a command times out and the hardware appears 149 * to be healthy the driver attempts to abort the command. The original command 150 * timeout is also applied to the abort command. If the abort times out too the 151 * driver assumes the device to be dead, fences it off, and calls FMA to retire 152 * it. In all other cases the aborted command should return immediately with a 153 * status indicating it was aborted, and the driver will wait indefinitely for 154 * that to happen. No timeout handling of normal I/O commands is presently done. 155 * 156 * Any command that times out due to the controller dropping dead will be put on 157 * nvme_lost_cmds list if it references DMA memory. This will prevent the DMA 158 * memory being reused by the system and later be written to by a "dead" NVMe 159 * controller. 160 * 161 * 162 * Locking: 163 * 164 * Each queue pair has its own nq_mutex, which must be held when accessing the 165 * associated queue registers or the shared state of the queue pair. Callers of 166 * nvme_unqueue_cmd() must make sure that nq_mutex is held, while 167 * nvme_submit_{admin,io}_cmd() and nvme_retrieve_cmd() take care of this 168 * themselves. 169 * 170 * Each command also has its own nc_mutex, which is associated with the 171 * condition variable nc_cv. It is only used on admin commands which are run 172 * synchronously. In that case it must be held across calls to 173 * nvme_submit_{admin,io}_cmd() and nvme_wait_cmd(), which is taken care of by 174 * nvme_admin_cmd(). It must also be held whenever the completion state of the 175 * command is changed or while a admin command timeout is handled. 176 * 177 * If both nc_mutex and nq_mutex must be held, nc_mutex must be acquired first. 178 * More than one nc_mutex may only be held when aborting commands. In this case, 179 * the nc_mutex of the command to be aborted must be held across the call to 180 * nvme_abort_cmd() to prevent the command from completing while the abort is in 181 * progress. 182 * 183 * Each minor node has its own nm_mutex, which protects the open count nm_ocnt 184 * and exclusive-open flag nm_oexcl. 185 * 186 * 187 * Quiesce / Fast Reboot: 188 * 189 * The driver currently does not support fast reboot. A quiesce(9E) entry point 190 * is still provided which is used to send a shutdown notification to the 191 * device. 192 * 193 * 194 * Driver Configuration: 195 * 196 * The following driver properties can be changed to control some aspects of the 197 * drivers operation: 198 * - strict-version: can be set to 0 to allow devices conforming to newer 199 * major versions to be used 200 * - ignore-unknown-vendor-status: can be set to 1 to not handle any vendor 201 * specific command status as a fatal error leading device faulting 202 * - admin-queue-len: the maximum length of the admin queue (16-4096) 203 * - io-queue-len: the maximum length of the I/O queues (16-65536) 204 * - async-event-limit: the maximum number of asynchronous event requests to be 205 * posted by the driver 206 * - volatile-write-cache-enable: can be set to 0 to disable the volatile write 207 * cache 208 * - min-phys-block-size: the minimum physical block size to report to blkdev, 209 * which is among other things the basis for ZFS vdev ashift 210 * 211 * 212 * TODO: 213 * - figure out sane default for I/O queue depth reported to blkdev 214 * - FMA handling of media errors 215 * - support for devices supporting very large I/O requests using chained PRPs 216 * - support for configuring hardware parameters like interrupt coalescing 217 * - support for media formatting and hard partitioning into namespaces 218 * - support for big-endian systems 219 * - support for fast reboot 220 * - support for firmware updates 221 * - support for NVMe Subsystem Reset (1.1) 222 * - support for Scatter/Gather lists (1.1) 223 * - support for Reservations (1.1) 224 * - support for power management 225 */ 226 227 #include <sys/byteorder.h> 228 #ifdef _BIG_ENDIAN 229 #error nvme driver needs porting for big-endian platforms 230 #endif 231 232 #include <sys/modctl.h> 233 #include <sys/conf.h> 234 #include <sys/devops.h> 235 #include <sys/ddi.h> 236 #include <sys/sunddi.h> 237 #include <sys/sunndi.h> 238 #include <sys/bitmap.h> 239 #include <sys/sysmacros.h> 240 #include <sys/param.h> 241 #include <sys/varargs.h> 242 #include <sys/cpuvar.h> 243 #include <sys/disp.h> 244 #include <sys/blkdev.h> 245 #include <sys/atomic.h> 246 #include <sys/archsystm.h> 247 #include <sys/sata/sata_hba.h> 248 #include <sys/stat.h> 249 #include <sys/policy.h> 250 #include <sys/list.h> 251 252 #include <sys/nvme.h> 253 254 #ifdef __x86 255 #include <sys/x86_archext.h> 256 #endif 257 258 #include "nvme_reg.h" 259 #include "nvme_var.h" 260 261 /* 262 * Assertions to make sure that we've properly captured various aspects of the 263 * packed structures and haven't broken them during updates. 264 */ 265 CTASSERT(sizeof (nvme_identify_ctrl_t) == 0x1000); 266 CTASSERT(offsetof(nvme_identify_ctrl_t, id_oacs) == 256); 267 CTASSERT(offsetof(nvme_identify_ctrl_t, id_sqes) == 512); 268 CTASSERT(offsetof(nvme_identify_ctrl_t, id_subnqn) == 768); 269 CTASSERT(offsetof(nvme_identify_ctrl_t, id_nvmof) == 1792); 270 CTASSERT(offsetof(nvme_identify_ctrl_t, id_psd) == 2048); 271 CTASSERT(offsetof(nvme_identify_ctrl_t, id_vs) == 3072); 272 273 CTASSERT(sizeof (nvme_identify_nsid_t) == 0x1000); 274 CTASSERT(offsetof(nvme_identify_nsid_t, id_fpi) == 32); 275 CTASSERT(offsetof(nvme_identify_nsid_t, id_nguid) == 104); 276 CTASSERT(offsetof(nvme_identify_nsid_t, id_lbaf) == 128); 277 CTASSERT(offsetof(nvme_identify_nsid_t, id_vs) == 384); 278 279 CTASSERT(sizeof (nvme_identify_primary_caps_t) == 0x1000); 280 CTASSERT(offsetof(nvme_identify_primary_caps_t, nipc_vqfrt) == 32); 281 CTASSERT(offsetof(nvme_identify_primary_caps_t, nipc_vifrt) == 64); 282 283 284 /* NVMe spec version supported */ 285 static const int nvme_version_major = 1; 286 287 /* tunable for admin command timeout in seconds, default is 1s */ 288 int nvme_admin_cmd_timeout = 1; 289 290 /* tunable for FORMAT NVM command timeout in seconds, default is 600s */ 291 int nvme_format_cmd_timeout = 600; 292 293 static int nvme_attach(dev_info_t *, ddi_attach_cmd_t); 294 static int nvme_detach(dev_info_t *, ddi_detach_cmd_t); 295 static int nvme_quiesce(dev_info_t *); 296 static int nvme_fm_errcb(dev_info_t *, ddi_fm_error_t *, const void *); 297 static int nvme_setup_interrupts(nvme_t *, int, int); 298 static void nvme_release_interrupts(nvme_t *); 299 static uint_t nvme_intr(caddr_t, caddr_t); 300 301 static void nvme_shutdown(nvme_t *, int, boolean_t); 302 static boolean_t nvme_reset(nvme_t *, boolean_t); 303 static int nvme_init(nvme_t *); 304 static nvme_cmd_t *nvme_alloc_cmd(nvme_t *, int); 305 static void nvme_free_cmd(nvme_cmd_t *); 306 static nvme_cmd_t *nvme_create_nvm_cmd(nvme_namespace_t *, uint8_t, 307 bd_xfer_t *); 308 static void nvme_admin_cmd(nvme_cmd_t *, int); 309 static void nvme_submit_admin_cmd(nvme_qpair_t *, nvme_cmd_t *); 310 static int nvme_submit_io_cmd(nvme_qpair_t *, nvme_cmd_t *); 311 static void nvme_submit_cmd_common(nvme_qpair_t *, nvme_cmd_t *); 312 static nvme_cmd_t *nvme_unqueue_cmd(nvme_t *, nvme_qpair_t *, int); 313 static nvme_cmd_t *nvme_retrieve_cmd(nvme_t *, nvme_qpair_t *); 314 static void nvme_wait_cmd(nvme_cmd_t *, uint_t); 315 static void nvme_wakeup_cmd(void *); 316 static void nvme_async_event_task(void *); 317 318 static int nvme_check_unknown_cmd_status(nvme_cmd_t *); 319 static int nvme_check_vendor_cmd_status(nvme_cmd_t *); 320 static int nvme_check_integrity_cmd_status(nvme_cmd_t *); 321 static int nvme_check_specific_cmd_status(nvme_cmd_t *); 322 static int nvme_check_generic_cmd_status(nvme_cmd_t *); 323 static inline int nvme_check_cmd_status(nvme_cmd_t *); 324 325 static int nvme_abort_cmd(nvme_cmd_t *, uint_t); 326 static void nvme_async_event(nvme_t *); 327 static int nvme_format_nvm(nvme_t *, uint32_t, uint8_t, boolean_t, uint8_t, 328 boolean_t, uint8_t); 329 static int nvme_get_logpage(nvme_t *, void **, size_t *, uint8_t, ...); 330 static int nvme_identify(nvme_t *, uint32_t, void **); 331 static int nvme_set_features(nvme_t *, uint32_t, uint8_t, uint32_t, 332 uint32_t *); 333 static int nvme_get_features(nvme_t *, uint32_t, uint8_t, uint32_t *, 334 void **, size_t *); 335 static int nvme_write_cache_set(nvme_t *, boolean_t); 336 static int nvme_set_nqueues(nvme_t *, uint16_t *); 337 338 static void nvme_free_dma(nvme_dma_t *); 339 static int nvme_zalloc_dma(nvme_t *, size_t, uint_t, ddi_dma_attr_t *, 340 nvme_dma_t **); 341 static int nvme_zalloc_queue_dma(nvme_t *, uint32_t, uint16_t, uint_t, 342 nvme_dma_t **); 343 static void nvme_free_qpair(nvme_qpair_t *); 344 static int nvme_alloc_qpair(nvme_t *, uint32_t, nvme_qpair_t **, int); 345 static int nvme_create_io_qpair(nvme_t *, nvme_qpair_t *, uint16_t); 346 347 static inline void nvme_put64(nvme_t *, uintptr_t, uint64_t); 348 static inline void nvme_put32(nvme_t *, uintptr_t, uint32_t); 349 static inline uint64_t nvme_get64(nvme_t *, uintptr_t); 350 static inline uint32_t nvme_get32(nvme_t *, uintptr_t); 351 352 static boolean_t nvme_check_regs_hdl(nvme_t *); 353 static boolean_t nvme_check_dma_hdl(nvme_dma_t *); 354 355 static int nvme_fill_prp(nvme_cmd_t *, bd_xfer_t *); 356 357 static void nvme_bd_xfer_done(void *); 358 static void nvme_bd_driveinfo(void *, bd_drive_t *); 359 static int nvme_bd_mediainfo(void *, bd_media_t *); 360 static int nvme_bd_cmd(nvme_namespace_t *, bd_xfer_t *, uint8_t); 361 static int nvme_bd_read(void *, bd_xfer_t *); 362 static int nvme_bd_write(void *, bd_xfer_t *); 363 static int nvme_bd_sync(void *, bd_xfer_t *); 364 static int nvme_bd_devid(void *, dev_info_t *, ddi_devid_t *); 365 366 static int nvme_prp_dma_constructor(void *, void *, int); 367 static void nvme_prp_dma_destructor(void *, void *); 368 369 static void nvme_prepare_devid(nvme_t *, uint32_t); 370 371 static int nvme_open(dev_t *, int, int, cred_t *); 372 static int nvme_close(dev_t, int, int, cred_t *); 373 static int nvme_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 374 375 #define NVME_MINOR_INST_SHIFT 9 376 #define NVME_MINOR(inst, nsid) (((inst) << NVME_MINOR_INST_SHIFT) | (nsid)) 377 #define NVME_MINOR_INST(minor) ((minor) >> NVME_MINOR_INST_SHIFT) 378 #define NVME_MINOR_NSID(minor) ((minor) & ((1 << NVME_MINOR_INST_SHIFT) - 1)) 379 #define NVME_MINOR_MAX (NVME_MINOR(1, 0) - 2) 380 381 static void *nvme_state; 382 static kmem_cache_t *nvme_cmd_cache; 383 384 /* 385 * DMA attributes for queue DMA memory 386 * 387 * Queue DMA memory must be page aligned. The maximum length of a queue is 388 * 65536 entries, and an entry can be 64 bytes long. 389 */ 390 static ddi_dma_attr_t nvme_queue_dma_attr = { 391 .dma_attr_version = DMA_ATTR_V0, 392 .dma_attr_addr_lo = 0, 393 .dma_attr_addr_hi = 0xffffffffffffffffULL, 394 .dma_attr_count_max = (UINT16_MAX + 1) * sizeof (nvme_sqe_t) - 1, 395 .dma_attr_align = 0x1000, 396 .dma_attr_burstsizes = 0x7ff, 397 .dma_attr_minxfer = 0x1000, 398 .dma_attr_maxxfer = (UINT16_MAX + 1) * sizeof (nvme_sqe_t), 399 .dma_attr_seg = 0xffffffffffffffffULL, 400 .dma_attr_sgllen = 1, 401 .dma_attr_granular = 1, 402 .dma_attr_flags = 0, 403 }; 404 405 /* 406 * DMA attributes for transfers using Physical Region Page (PRP) entries 407 * 408 * A PRP entry describes one page of DMA memory using the page size specified 409 * in the controller configuration's memory page size register (CC.MPS). It uses 410 * a 64bit base address aligned to this page size. There is no limitation on 411 * chaining PRPs together for arbitrarily large DMA transfers. 412 */ 413 static ddi_dma_attr_t nvme_prp_dma_attr = { 414 .dma_attr_version = DMA_ATTR_V0, 415 .dma_attr_addr_lo = 0, 416 .dma_attr_addr_hi = 0xffffffffffffffffULL, 417 .dma_attr_count_max = 0xfff, 418 .dma_attr_align = 0x1000, 419 .dma_attr_burstsizes = 0x7ff, 420 .dma_attr_minxfer = 0x1000, 421 .dma_attr_maxxfer = 0x1000, 422 .dma_attr_seg = 0xfff, 423 .dma_attr_sgllen = -1, 424 .dma_attr_granular = 1, 425 .dma_attr_flags = 0, 426 }; 427 428 /* 429 * DMA attributes for transfers using scatter/gather lists 430 * 431 * A SGL entry describes a chunk of DMA memory using a 64bit base address and a 432 * 32bit length field. SGL Segment and SGL Last Segment entries require the 433 * length to be a multiple of 16 bytes. 434 */ 435 static ddi_dma_attr_t nvme_sgl_dma_attr = { 436 .dma_attr_version = DMA_ATTR_V0, 437 .dma_attr_addr_lo = 0, 438 .dma_attr_addr_hi = 0xffffffffffffffffULL, 439 .dma_attr_count_max = 0xffffffffUL, 440 .dma_attr_align = 1, 441 .dma_attr_burstsizes = 0x7ff, 442 .dma_attr_minxfer = 0x10, 443 .dma_attr_maxxfer = 0xfffffffffULL, 444 .dma_attr_seg = 0xffffffffffffffffULL, 445 .dma_attr_sgllen = -1, 446 .dma_attr_granular = 0x10, 447 .dma_attr_flags = 0 448 }; 449 450 static ddi_device_acc_attr_t nvme_reg_acc_attr = { 451 .devacc_attr_version = DDI_DEVICE_ATTR_V0, 452 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, 453 .devacc_attr_dataorder = DDI_STRICTORDER_ACC 454 }; 455 456 static struct cb_ops nvme_cb_ops = { 457 .cb_open = nvme_open, 458 .cb_close = nvme_close, 459 .cb_strategy = nodev, 460 .cb_print = nodev, 461 .cb_dump = nodev, 462 .cb_read = nodev, 463 .cb_write = nodev, 464 .cb_ioctl = nvme_ioctl, 465 .cb_devmap = nodev, 466 .cb_mmap = nodev, 467 .cb_segmap = nodev, 468 .cb_chpoll = nochpoll, 469 .cb_prop_op = ddi_prop_op, 470 .cb_str = 0, 471 .cb_flag = D_NEW | D_MP, 472 .cb_rev = CB_REV, 473 .cb_aread = nodev, 474 .cb_awrite = nodev 475 }; 476 477 static struct dev_ops nvme_dev_ops = { 478 .devo_rev = DEVO_REV, 479 .devo_refcnt = 0, 480 .devo_getinfo = ddi_no_info, 481 .devo_identify = nulldev, 482 .devo_probe = nulldev, 483 .devo_attach = nvme_attach, 484 .devo_detach = nvme_detach, 485 .devo_reset = nodev, 486 .devo_cb_ops = &nvme_cb_ops, 487 .devo_bus_ops = NULL, 488 .devo_power = NULL, 489 .devo_quiesce = nvme_quiesce, 490 }; 491 492 static struct modldrv nvme_modldrv = { 493 .drv_modops = &mod_driverops, 494 .drv_linkinfo = "NVMe v1.1b", 495 .drv_dev_ops = &nvme_dev_ops 496 }; 497 498 static struct modlinkage nvme_modlinkage = { 499 .ml_rev = MODREV_1, 500 .ml_linkage = { &nvme_modldrv, NULL } 501 }; 502 503 static bd_ops_t nvme_bd_ops = { 504 .o_version = BD_OPS_VERSION_0, 505 .o_drive_info = nvme_bd_driveinfo, 506 .o_media_info = nvme_bd_mediainfo, 507 .o_devid_init = nvme_bd_devid, 508 .o_sync_cache = nvme_bd_sync, 509 .o_read = nvme_bd_read, 510 .o_write = nvme_bd_write, 511 }; 512 513 /* 514 * This list will hold commands that have timed out and couldn't be aborted. 515 * As we don't know what the hardware may still do with the DMA memory we can't 516 * free them, so we'll keep them forever on this list where we can easily look 517 * at them with mdb. 518 */ 519 static struct list nvme_lost_cmds; 520 static kmutex_t nvme_lc_mutex; 521 522 int 523 _init(void) 524 { 525 int error; 526 527 error = ddi_soft_state_init(&nvme_state, sizeof (nvme_t), 1); 528 if (error != DDI_SUCCESS) 529 return (error); 530 531 nvme_cmd_cache = kmem_cache_create("nvme_cmd_cache", 532 sizeof (nvme_cmd_t), 64, NULL, NULL, NULL, NULL, NULL, 0); 533 534 mutex_init(&nvme_lc_mutex, NULL, MUTEX_DRIVER, NULL); 535 list_create(&nvme_lost_cmds, sizeof (nvme_cmd_t), 536 offsetof(nvme_cmd_t, nc_list)); 537 538 bd_mod_init(&nvme_dev_ops); 539 540 error = mod_install(&nvme_modlinkage); 541 if (error != DDI_SUCCESS) { 542 ddi_soft_state_fini(&nvme_state); 543 mutex_destroy(&nvme_lc_mutex); 544 list_destroy(&nvme_lost_cmds); 545 bd_mod_fini(&nvme_dev_ops); 546 } 547 548 return (error); 549 } 550 551 int 552 _fini(void) 553 { 554 int error; 555 556 if (!list_is_empty(&nvme_lost_cmds)) 557 return (DDI_FAILURE); 558 559 error = mod_remove(&nvme_modlinkage); 560 if (error == DDI_SUCCESS) { 561 ddi_soft_state_fini(&nvme_state); 562 kmem_cache_destroy(nvme_cmd_cache); 563 mutex_destroy(&nvme_lc_mutex); 564 list_destroy(&nvme_lost_cmds); 565 bd_mod_fini(&nvme_dev_ops); 566 } 567 568 return (error); 569 } 570 571 int 572 _info(struct modinfo *modinfop) 573 { 574 return (mod_info(&nvme_modlinkage, modinfop)); 575 } 576 577 static inline void 578 nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val) 579 { 580 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0); 581 582 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 583 ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val); 584 } 585 586 static inline void 587 nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val) 588 { 589 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0); 590 591 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 592 ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val); 593 } 594 595 static inline uint64_t 596 nvme_get64(nvme_t *nvme, uintptr_t reg) 597 { 598 uint64_t val; 599 600 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0); 601 602 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 603 val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg)); 604 605 return (val); 606 } 607 608 static inline uint32_t 609 nvme_get32(nvme_t *nvme, uintptr_t reg) 610 { 611 uint32_t val; 612 613 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0); 614 615 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 616 val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg)); 617 618 return (val); 619 } 620 621 static boolean_t 622 nvme_check_regs_hdl(nvme_t *nvme) 623 { 624 ddi_fm_error_t error; 625 626 ddi_fm_acc_err_get(nvme->n_regh, &error, DDI_FME_VERSION); 627 628 if (error.fme_status != DDI_FM_OK) 629 return (B_TRUE); 630 631 return (B_FALSE); 632 } 633 634 static boolean_t 635 nvme_check_dma_hdl(nvme_dma_t *dma) 636 { 637 ddi_fm_error_t error; 638 639 if (dma == NULL) 640 return (B_FALSE); 641 642 ddi_fm_dma_err_get(dma->nd_dmah, &error, DDI_FME_VERSION); 643 644 if (error.fme_status != DDI_FM_OK) 645 return (B_TRUE); 646 647 return (B_FALSE); 648 } 649 650 static void 651 nvme_free_dma_common(nvme_dma_t *dma) 652 { 653 if (dma->nd_dmah != NULL) 654 (void) ddi_dma_unbind_handle(dma->nd_dmah); 655 if (dma->nd_acch != NULL) 656 ddi_dma_mem_free(&dma->nd_acch); 657 if (dma->nd_dmah != NULL) 658 ddi_dma_free_handle(&dma->nd_dmah); 659 } 660 661 static void 662 nvme_free_dma(nvme_dma_t *dma) 663 { 664 nvme_free_dma_common(dma); 665 kmem_free(dma, sizeof (*dma)); 666 } 667 668 /* ARGSUSED */ 669 static void 670 nvme_prp_dma_destructor(void *buf, void *private) 671 { 672 nvme_dma_t *dma = (nvme_dma_t *)buf; 673 674 nvme_free_dma_common(dma); 675 } 676 677 static int 678 nvme_alloc_dma_common(nvme_t *nvme, nvme_dma_t *dma, 679 size_t len, uint_t flags, ddi_dma_attr_t *dma_attr) 680 { 681 if (ddi_dma_alloc_handle(nvme->n_dip, dma_attr, DDI_DMA_SLEEP, NULL, 682 &dma->nd_dmah) != DDI_SUCCESS) { 683 /* 684 * Due to DDI_DMA_SLEEP this can't be DDI_DMA_NORESOURCES, and 685 * the only other possible error is DDI_DMA_BADATTR which 686 * indicates a driver bug which should cause a panic. 687 */ 688 dev_err(nvme->n_dip, CE_PANIC, 689 "!failed to get DMA handle, check DMA attributes"); 690 return (DDI_FAILURE); 691 } 692 693 /* 694 * ddi_dma_mem_alloc() can only fail when DDI_DMA_NOSLEEP is specified 695 * or the flags are conflicting, which isn't the case here. 696 */ 697 (void) ddi_dma_mem_alloc(dma->nd_dmah, len, &nvme->n_reg_acc_attr, 698 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &dma->nd_memp, 699 &dma->nd_len, &dma->nd_acch); 700 701 if (ddi_dma_addr_bind_handle(dma->nd_dmah, NULL, dma->nd_memp, 702 dma->nd_len, flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 703 &dma->nd_cookie, &dma->nd_ncookie) != DDI_DMA_MAPPED) { 704 dev_err(nvme->n_dip, CE_WARN, 705 "!failed to bind DMA memory"); 706 atomic_inc_32(&nvme->n_dma_bind_err); 707 nvme_free_dma_common(dma); 708 return (DDI_FAILURE); 709 } 710 711 return (DDI_SUCCESS); 712 } 713 714 static int 715 nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags, 716 ddi_dma_attr_t *dma_attr, nvme_dma_t **ret) 717 { 718 nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP); 719 720 if (nvme_alloc_dma_common(nvme, dma, len, flags, dma_attr) != 721 DDI_SUCCESS) { 722 *ret = NULL; 723 kmem_free(dma, sizeof (nvme_dma_t)); 724 return (DDI_FAILURE); 725 } 726 727 bzero(dma->nd_memp, dma->nd_len); 728 729 *ret = dma; 730 return (DDI_SUCCESS); 731 } 732 733 /* ARGSUSED */ 734 static int 735 nvme_prp_dma_constructor(void *buf, void *private, int flags) 736 { 737 nvme_dma_t *dma = (nvme_dma_t *)buf; 738 nvme_t *nvme = (nvme_t *)private; 739 740 dma->nd_dmah = NULL; 741 dma->nd_acch = NULL; 742 743 if (nvme_alloc_dma_common(nvme, dma, nvme->n_pagesize, 744 DDI_DMA_READ, &nvme->n_prp_dma_attr) != DDI_SUCCESS) { 745 return (-1); 746 } 747 748 ASSERT(dma->nd_ncookie == 1); 749 750 dma->nd_cached = B_TRUE; 751 752 return (0); 753 } 754 755 static int 756 nvme_zalloc_queue_dma(nvme_t *nvme, uint32_t nentry, uint16_t qe_len, 757 uint_t flags, nvme_dma_t **dma) 758 { 759 uint32_t len = nentry * qe_len; 760 ddi_dma_attr_t q_dma_attr = nvme->n_queue_dma_attr; 761 762 len = roundup(len, nvme->n_pagesize); 763 764 q_dma_attr.dma_attr_minxfer = len; 765 766 if (nvme_zalloc_dma(nvme, len, flags, &q_dma_attr, dma) 767 != DDI_SUCCESS) { 768 dev_err(nvme->n_dip, CE_WARN, 769 "!failed to get DMA memory for queue"); 770 goto fail; 771 } 772 773 if ((*dma)->nd_ncookie != 1) { 774 dev_err(nvme->n_dip, CE_WARN, 775 "!got too many cookies for queue DMA"); 776 goto fail; 777 } 778 779 return (DDI_SUCCESS); 780 781 fail: 782 if (*dma) { 783 nvme_free_dma(*dma); 784 *dma = NULL; 785 } 786 787 return (DDI_FAILURE); 788 } 789 790 static void 791 nvme_free_qpair(nvme_qpair_t *qp) 792 { 793 int i; 794 795 mutex_destroy(&qp->nq_mutex); 796 sema_destroy(&qp->nq_sema); 797 798 if (qp->nq_sqdma != NULL) 799 nvme_free_dma(qp->nq_sqdma); 800 if (qp->nq_cqdma != NULL) 801 nvme_free_dma(qp->nq_cqdma); 802 803 if (qp->nq_active_cmds > 0) 804 for (i = 0; i != qp->nq_nentry; i++) 805 if (qp->nq_cmd[i] != NULL) 806 nvme_free_cmd(qp->nq_cmd[i]); 807 808 if (qp->nq_cmd != NULL) 809 kmem_free(qp->nq_cmd, sizeof (nvme_cmd_t *) * qp->nq_nentry); 810 811 kmem_free(qp, sizeof (nvme_qpair_t)); 812 } 813 814 static int 815 nvme_alloc_qpair(nvme_t *nvme, uint32_t nentry, nvme_qpair_t **nqp, 816 int idx) 817 { 818 nvme_qpair_t *qp = kmem_zalloc(sizeof (*qp), KM_SLEEP); 819 820 mutex_init(&qp->nq_mutex, NULL, MUTEX_DRIVER, 821 DDI_INTR_PRI(nvme->n_intr_pri)); 822 sema_init(&qp->nq_sema, nentry, NULL, SEMA_DRIVER, NULL); 823 824 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_sqe_t), 825 DDI_DMA_WRITE, &qp->nq_sqdma) != DDI_SUCCESS) 826 goto fail; 827 828 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_cqe_t), 829 DDI_DMA_READ, &qp->nq_cqdma) != DDI_SUCCESS) 830 goto fail; 831 832 qp->nq_sq = (nvme_sqe_t *)qp->nq_sqdma->nd_memp; 833 qp->nq_cq = (nvme_cqe_t *)qp->nq_cqdma->nd_memp; 834 qp->nq_nentry = nentry; 835 836 qp->nq_sqtdbl = NVME_REG_SQTDBL(nvme, idx); 837 qp->nq_cqhdbl = NVME_REG_CQHDBL(nvme, idx); 838 839 qp->nq_cmd = kmem_zalloc(sizeof (nvme_cmd_t *) * nentry, KM_SLEEP); 840 qp->nq_next_cmd = 0; 841 842 *nqp = qp; 843 return (DDI_SUCCESS); 844 845 fail: 846 nvme_free_qpair(qp); 847 *nqp = NULL; 848 849 return (DDI_FAILURE); 850 } 851 852 static nvme_cmd_t * 853 nvme_alloc_cmd(nvme_t *nvme, int kmflag) 854 { 855 nvme_cmd_t *cmd = kmem_cache_alloc(nvme_cmd_cache, kmflag); 856 857 if (cmd == NULL) 858 return (cmd); 859 860 bzero(cmd, sizeof (nvme_cmd_t)); 861 862 cmd->nc_nvme = nvme; 863 864 mutex_init(&cmd->nc_mutex, NULL, MUTEX_DRIVER, 865 DDI_INTR_PRI(nvme->n_intr_pri)); 866 cv_init(&cmd->nc_cv, NULL, CV_DRIVER, NULL); 867 868 return (cmd); 869 } 870 871 static void 872 nvme_free_cmd(nvme_cmd_t *cmd) 873 { 874 /* Don't free commands on the lost commands list. */ 875 if (list_link_active(&cmd->nc_list)) 876 return; 877 878 if (cmd->nc_dma) { 879 if (cmd->nc_dma->nd_cached) 880 kmem_cache_free(cmd->nc_nvme->n_prp_cache, 881 cmd->nc_dma); 882 else 883 nvme_free_dma(cmd->nc_dma); 884 cmd->nc_dma = NULL; 885 } 886 887 cv_destroy(&cmd->nc_cv); 888 mutex_destroy(&cmd->nc_mutex); 889 890 kmem_cache_free(nvme_cmd_cache, cmd); 891 } 892 893 static void 894 nvme_submit_admin_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd) 895 { 896 sema_p(&qp->nq_sema); 897 nvme_submit_cmd_common(qp, cmd); 898 } 899 900 static int 901 nvme_submit_io_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd) 902 { 903 if (sema_tryp(&qp->nq_sema) == 0) 904 return (EAGAIN); 905 906 nvme_submit_cmd_common(qp, cmd); 907 return (0); 908 } 909 910 static void 911 nvme_submit_cmd_common(nvme_qpair_t *qp, nvme_cmd_t *cmd) 912 { 913 nvme_reg_sqtdbl_t tail = { 0 }; 914 915 mutex_enter(&qp->nq_mutex); 916 cmd->nc_completed = B_FALSE; 917 918 /* 919 * Try to insert the cmd into the active cmd array at the nq_next_cmd 920 * slot. If the slot is already occupied advance to the next slot and 921 * try again. This can happen for long running commands like async event 922 * requests. 923 */ 924 while (qp->nq_cmd[qp->nq_next_cmd] != NULL) 925 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry; 926 qp->nq_cmd[qp->nq_next_cmd] = cmd; 927 928 qp->nq_active_cmds++; 929 930 cmd->nc_sqe.sqe_cid = qp->nq_next_cmd; 931 bcopy(&cmd->nc_sqe, &qp->nq_sq[qp->nq_sqtail], sizeof (nvme_sqe_t)); 932 (void) ddi_dma_sync(qp->nq_sqdma->nd_dmah, 933 sizeof (nvme_sqe_t) * qp->nq_sqtail, 934 sizeof (nvme_sqe_t), DDI_DMA_SYNC_FORDEV); 935 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry; 936 937 tail.b.sqtdbl_sqt = qp->nq_sqtail = (qp->nq_sqtail + 1) % qp->nq_nentry; 938 nvme_put32(cmd->nc_nvme, qp->nq_sqtdbl, tail.r); 939 940 mutex_exit(&qp->nq_mutex); 941 } 942 943 static nvme_cmd_t * 944 nvme_unqueue_cmd(nvme_t *nvme, nvme_qpair_t *qp, int cid) 945 { 946 nvme_cmd_t *cmd; 947 948 ASSERT(mutex_owned(&qp->nq_mutex)); 949 ASSERT3S(cid, <, qp->nq_nentry); 950 951 cmd = qp->nq_cmd[cid]; 952 qp->nq_cmd[cid] = NULL; 953 ASSERT3U(qp->nq_active_cmds, >, 0); 954 qp->nq_active_cmds--; 955 sema_v(&qp->nq_sema); 956 957 ASSERT3P(cmd, !=, NULL); 958 ASSERT3P(cmd->nc_nvme, ==, nvme); 959 ASSERT3S(cmd->nc_sqe.sqe_cid, ==, cid); 960 961 return (cmd); 962 } 963 964 static nvme_cmd_t * 965 nvme_retrieve_cmd(nvme_t *nvme, nvme_qpair_t *qp) 966 { 967 nvme_reg_cqhdbl_t head = { 0 }; 968 969 nvme_cqe_t *cqe; 970 nvme_cmd_t *cmd; 971 972 (void) ddi_dma_sync(qp->nq_cqdma->nd_dmah, 0, 973 sizeof (nvme_cqe_t) * qp->nq_nentry, DDI_DMA_SYNC_FORKERNEL); 974 975 mutex_enter(&qp->nq_mutex); 976 cqe = &qp->nq_cq[qp->nq_cqhead]; 977 978 /* Check phase tag of CQE. Hardware inverts it for new entries. */ 979 if (cqe->cqe_sf.sf_p == qp->nq_phase) { 980 mutex_exit(&qp->nq_mutex); 981 return (NULL); 982 } 983 984 ASSERT(nvme->n_ioq[cqe->cqe_sqid] == qp); 985 986 cmd = nvme_unqueue_cmd(nvme, qp, cqe->cqe_cid); 987 988 ASSERT(cmd->nc_sqid == cqe->cqe_sqid); 989 bcopy(cqe, &cmd->nc_cqe, sizeof (nvme_cqe_t)); 990 991 qp->nq_sqhead = cqe->cqe_sqhd; 992 993 head.b.cqhdbl_cqh = qp->nq_cqhead = (qp->nq_cqhead + 1) % qp->nq_nentry; 994 995 /* Toggle phase on wrap-around. */ 996 if (qp->nq_cqhead == 0) 997 qp->nq_phase = qp->nq_phase ? 0 : 1; 998 999 nvme_put32(cmd->nc_nvme, qp->nq_cqhdbl, head.r); 1000 mutex_exit(&qp->nq_mutex); 1001 1002 return (cmd); 1003 } 1004 1005 static int 1006 nvme_check_unknown_cmd_status(nvme_cmd_t *cmd) 1007 { 1008 nvme_cqe_t *cqe = &cmd->nc_cqe; 1009 1010 dev_err(cmd->nc_nvme->n_dip, CE_WARN, 1011 "!unknown command status received: opc = %x, sqid = %d, cid = %d, " 1012 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc, 1013 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct, 1014 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m); 1015 1016 if (cmd->nc_xfer != NULL) 1017 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 1018 1019 if (cmd->nc_nvme->n_strict_version) { 1020 cmd->nc_nvme->n_dead = B_TRUE; 1021 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST); 1022 } 1023 1024 return (EIO); 1025 } 1026 1027 static int 1028 nvme_check_vendor_cmd_status(nvme_cmd_t *cmd) 1029 { 1030 nvme_cqe_t *cqe = &cmd->nc_cqe; 1031 1032 dev_err(cmd->nc_nvme->n_dip, CE_WARN, 1033 "!unknown command status received: opc = %x, sqid = %d, cid = %d, " 1034 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc, 1035 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct, 1036 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m); 1037 if (!cmd->nc_nvme->n_ignore_unknown_vendor_status) { 1038 cmd->nc_nvme->n_dead = B_TRUE; 1039 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST); 1040 } 1041 1042 return (EIO); 1043 } 1044 1045 static int 1046 nvme_check_integrity_cmd_status(nvme_cmd_t *cmd) 1047 { 1048 nvme_cqe_t *cqe = &cmd->nc_cqe; 1049 1050 switch (cqe->cqe_sf.sf_sc) { 1051 case NVME_CQE_SC_INT_NVM_WRITE: 1052 /* write fail */ 1053 /* TODO: post ereport */ 1054 if (cmd->nc_xfer != NULL) 1055 bd_error(cmd->nc_xfer, BD_ERR_MEDIA); 1056 return (EIO); 1057 1058 case NVME_CQE_SC_INT_NVM_READ: 1059 /* read fail */ 1060 /* TODO: post ereport */ 1061 if (cmd->nc_xfer != NULL) 1062 bd_error(cmd->nc_xfer, BD_ERR_MEDIA); 1063 return (EIO); 1064 1065 default: 1066 return (nvme_check_unknown_cmd_status(cmd)); 1067 } 1068 } 1069 1070 static int 1071 nvme_check_generic_cmd_status(nvme_cmd_t *cmd) 1072 { 1073 nvme_cqe_t *cqe = &cmd->nc_cqe; 1074 1075 switch (cqe->cqe_sf.sf_sc) { 1076 case NVME_CQE_SC_GEN_SUCCESS: 1077 return (0); 1078 1079 /* 1080 * Errors indicating a bug in the driver should cause a panic. 1081 */ 1082 case NVME_CQE_SC_GEN_INV_OPC: 1083 /* Invalid Command Opcode */ 1084 if (!cmd->nc_dontpanic) 1085 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, 1086 "programming error: invalid opcode in cmd %p", 1087 (void *)cmd); 1088 return (EINVAL); 1089 1090 case NVME_CQE_SC_GEN_INV_FLD: 1091 /* Invalid Field in Command */ 1092 if (!cmd->nc_dontpanic) 1093 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, 1094 "programming error: invalid field in cmd %p", 1095 (void *)cmd); 1096 return (EIO); 1097 1098 case NVME_CQE_SC_GEN_ID_CNFL: 1099 /* Command ID Conflict */ 1100 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: " 1101 "cmd ID conflict in cmd %p", (void *)cmd); 1102 return (0); 1103 1104 case NVME_CQE_SC_GEN_INV_NS: 1105 /* Invalid Namespace or Format */ 1106 if (!cmd->nc_dontpanic) 1107 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, 1108 "programming error: invalid NS/format in cmd %p", 1109 (void *)cmd); 1110 return (EINVAL); 1111 1112 case NVME_CQE_SC_GEN_NVM_LBA_RANGE: 1113 /* LBA Out Of Range */ 1114 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: " 1115 "LBA out of range in cmd %p", (void *)cmd); 1116 return (0); 1117 1118 /* 1119 * Non-fatal errors, handle gracefully. 1120 */ 1121 case NVME_CQE_SC_GEN_DATA_XFR_ERR: 1122 /* Data Transfer Error (DMA) */ 1123 /* TODO: post ereport */ 1124 atomic_inc_32(&cmd->nc_nvme->n_data_xfr_err); 1125 if (cmd->nc_xfer != NULL) 1126 bd_error(cmd->nc_xfer, BD_ERR_NTRDY); 1127 return (EIO); 1128 1129 case NVME_CQE_SC_GEN_INTERNAL_ERR: 1130 /* 1131 * Internal Error. The spec (v1.0, section 4.5.1.2) says 1132 * detailed error information is returned as async event, 1133 * so we pretty much ignore the error here and handle it 1134 * in the async event handler. 1135 */ 1136 atomic_inc_32(&cmd->nc_nvme->n_internal_err); 1137 if (cmd->nc_xfer != NULL) 1138 bd_error(cmd->nc_xfer, BD_ERR_NTRDY); 1139 return (EIO); 1140 1141 case NVME_CQE_SC_GEN_ABORT_REQUEST: 1142 /* 1143 * Command Abort Requested. This normally happens only when a 1144 * command times out. 1145 */ 1146 /* TODO: post ereport or change blkdev to handle this? */ 1147 atomic_inc_32(&cmd->nc_nvme->n_abort_rq_err); 1148 return (ECANCELED); 1149 1150 case NVME_CQE_SC_GEN_ABORT_PWRLOSS: 1151 /* Command Aborted due to Power Loss Notification */ 1152 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST); 1153 cmd->nc_nvme->n_dead = B_TRUE; 1154 return (EIO); 1155 1156 case NVME_CQE_SC_GEN_ABORT_SQ_DEL: 1157 /* Command Aborted due to SQ Deletion */ 1158 atomic_inc_32(&cmd->nc_nvme->n_abort_sq_del); 1159 return (EIO); 1160 1161 case NVME_CQE_SC_GEN_NVM_CAP_EXC: 1162 /* Capacity Exceeded */ 1163 atomic_inc_32(&cmd->nc_nvme->n_nvm_cap_exc); 1164 if (cmd->nc_xfer != NULL) 1165 bd_error(cmd->nc_xfer, BD_ERR_MEDIA); 1166 return (EIO); 1167 1168 case NVME_CQE_SC_GEN_NVM_NS_NOTRDY: 1169 /* Namespace Not Ready */ 1170 atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_notrdy); 1171 if (cmd->nc_xfer != NULL) 1172 bd_error(cmd->nc_xfer, BD_ERR_NTRDY); 1173 return (EIO); 1174 1175 default: 1176 return (nvme_check_unknown_cmd_status(cmd)); 1177 } 1178 } 1179 1180 static int 1181 nvme_check_specific_cmd_status(nvme_cmd_t *cmd) 1182 { 1183 nvme_cqe_t *cqe = &cmd->nc_cqe; 1184 1185 switch (cqe->cqe_sf.sf_sc) { 1186 case NVME_CQE_SC_SPC_INV_CQ: 1187 /* Completion Queue Invalid */ 1188 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE); 1189 atomic_inc_32(&cmd->nc_nvme->n_inv_cq_err); 1190 return (EINVAL); 1191 1192 case NVME_CQE_SC_SPC_INV_QID: 1193 /* Invalid Queue Identifier */ 1194 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE || 1195 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_SQUEUE || 1196 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE || 1197 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE); 1198 atomic_inc_32(&cmd->nc_nvme->n_inv_qid_err); 1199 return (EINVAL); 1200 1201 case NVME_CQE_SC_SPC_MAX_QSZ_EXC: 1202 /* Max Queue Size Exceeded */ 1203 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE || 1204 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE); 1205 atomic_inc_32(&cmd->nc_nvme->n_max_qsz_exc); 1206 return (EINVAL); 1207 1208 case NVME_CQE_SC_SPC_ABRT_CMD_EXC: 1209 /* Abort Command Limit Exceeded */ 1210 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT); 1211 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: " 1212 "abort command limit exceeded in cmd %p", (void *)cmd); 1213 return (0); 1214 1215 case NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC: 1216 /* Async Event Request Limit Exceeded */ 1217 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ASYNC_EVENT); 1218 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: " 1219 "async event request limit exceeded in cmd %p", 1220 (void *)cmd); 1221 return (0); 1222 1223 case NVME_CQE_SC_SPC_INV_INT_VECT: 1224 /* Invalid Interrupt Vector */ 1225 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE); 1226 atomic_inc_32(&cmd->nc_nvme->n_inv_int_vect); 1227 return (EINVAL); 1228 1229 case NVME_CQE_SC_SPC_INV_LOG_PAGE: 1230 /* Invalid Log Page */ 1231 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_GET_LOG_PAGE); 1232 atomic_inc_32(&cmd->nc_nvme->n_inv_log_page); 1233 return (EINVAL); 1234 1235 case NVME_CQE_SC_SPC_INV_FORMAT: 1236 /* Invalid Format */ 1237 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_FORMAT); 1238 atomic_inc_32(&cmd->nc_nvme->n_inv_format); 1239 if (cmd->nc_xfer != NULL) 1240 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 1241 return (EINVAL); 1242 1243 case NVME_CQE_SC_SPC_INV_Q_DEL: 1244 /* Invalid Queue Deletion */ 1245 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE); 1246 atomic_inc_32(&cmd->nc_nvme->n_inv_q_del); 1247 return (EINVAL); 1248 1249 case NVME_CQE_SC_SPC_NVM_CNFL_ATTR: 1250 /* Conflicting Attributes */ 1251 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_DSET_MGMT || 1252 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ || 1253 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE); 1254 atomic_inc_32(&cmd->nc_nvme->n_cnfl_attr); 1255 if (cmd->nc_xfer != NULL) 1256 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 1257 return (EINVAL); 1258 1259 case NVME_CQE_SC_SPC_NVM_INV_PROT: 1260 /* Invalid Protection Information */ 1261 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_COMPARE || 1262 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ || 1263 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE); 1264 atomic_inc_32(&cmd->nc_nvme->n_inv_prot); 1265 if (cmd->nc_xfer != NULL) 1266 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 1267 return (EINVAL); 1268 1269 case NVME_CQE_SC_SPC_NVM_READONLY: 1270 /* Write to Read Only Range */ 1271 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE); 1272 atomic_inc_32(&cmd->nc_nvme->n_readonly); 1273 if (cmd->nc_xfer != NULL) 1274 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ); 1275 return (EROFS); 1276 1277 default: 1278 return (nvme_check_unknown_cmd_status(cmd)); 1279 } 1280 } 1281 1282 static inline int 1283 nvme_check_cmd_status(nvme_cmd_t *cmd) 1284 { 1285 nvme_cqe_t *cqe = &cmd->nc_cqe; 1286 1287 /* 1288 * Take a shortcut if the controller is dead, or if 1289 * command status indicates no error. 1290 */ 1291 if (cmd->nc_nvme->n_dead) 1292 return (EIO); 1293 1294 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC && 1295 cqe->cqe_sf.sf_sc == NVME_CQE_SC_GEN_SUCCESS) 1296 return (0); 1297 1298 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC) 1299 return (nvme_check_generic_cmd_status(cmd)); 1300 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_SPECIFIC) 1301 return (nvme_check_specific_cmd_status(cmd)); 1302 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_INTEGRITY) 1303 return (nvme_check_integrity_cmd_status(cmd)); 1304 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_VENDOR) 1305 return (nvme_check_vendor_cmd_status(cmd)); 1306 1307 return (nvme_check_unknown_cmd_status(cmd)); 1308 } 1309 1310 static int 1311 nvme_abort_cmd(nvme_cmd_t *abort_cmd, uint_t sec) 1312 { 1313 nvme_t *nvme = abort_cmd->nc_nvme; 1314 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1315 nvme_abort_cmd_t ac = { 0 }; 1316 int ret = 0; 1317 1318 sema_p(&nvme->n_abort_sema); 1319 1320 ac.b.ac_cid = abort_cmd->nc_sqe.sqe_cid; 1321 ac.b.ac_sqid = abort_cmd->nc_sqid; 1322 1323 cmd->nc_sqid = 0; 1324 cmd->nc_sqe.sqe_opc = NVME_OPC_ABORT; 1325 cmd->nc_callback = nvme_wakeup_cmd; 1326 cmd->nc_sqe.sqe_cdw10 = ac.r; 1327 1328 /* 1329 * Send the ABORT to the hardware. The ABORT command will return _after_ 1330 * the aborted command has completed (aborted or otherwise), but since 1331 * we still hold the aborted command's mutex its callback hasn't been 1332 * processed yet. 1333 */ 1334 nvme_admin_cmd(cmd, sec); 1335 sema_v(&nvme->n_abort_sema); 1336 1337 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1338 dev_err(nvme->n_dip, CE_WARN, 1339 "!ABORT failed with sct = %x, sc = %x", 1340 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 1341 atomic_inc_32(&nvme->n_abort_failed); 1342 } else { 1343 dev_err(nvme->n_dip, CE_WARN, 1344 "!ABORT of command %d/%d %ssuccessful", 1345 abort_cmd->nc_sqe.sqe_cid, abort_cmd->nc_sqid, 1346 cmd->nc_cqe.cqe_dw0 & 1 ? "un" : ""); 1347 if ((cmd->nc_cqe.cqe_dw0 & 1) == 0) 1348 atomic_inc_32(&nvme->n_cmd_aborted); 1349 } 1350 1351 nvme_free_cmd(cmd); 1352 return (ret); 1353 } 1354 1355 /* 1356 * nvme_wait_cmd -- wait for command completion or timeout 1357 * 1358 * In case of a serious error or a timeout of the abort command the hardware 1359 * will be declared dead and FMA will be notified. 1360 */ 1361 static void 1362 nvme_wait_cmd(nvme_cmd_t *cmd, uint_t sec) 1363 { 1364 clock_t timeout = ddi_get_lbolt() + drv_usectohz(sec * MICROSEC); 1365 nvme_t *nvme = cmd->nc_nvme; 1366 nvme_reg_csts_t csts; 1367 nvme_qpair_t *qp; 1368 1369 ASSERT(mutex_owned(&cmd->nc_mutex)); 1370 1371 while (!cmd->nc_completed) { 1372 if (cv_timedwait(&cmd->nc_cv, &cmd->nc_mutex, timeout) == -1) 1373 break; 1374 } 1375 1376 if (cmd->nc_completed) 1377 return; 1378 1379 /* 1380 * The command timed out. 1381 * 1382 * Check controller for fatal status, any errors associated with the 1383 * register or DMA handle, or for a double timeout (abort command timed 1384 * out). If necessary log a warning and call FMA. 1385 */ 1386 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 1387 dev_err(nvme->n_dip, CE_WARN, "!command %d/%d timeout, " 1388 "OPC = %x, CFS = %d", cmd->nc_sqe.sqe_cid, cmd->nc_sqid, 1389 cmd->nc_sqe.sqe_opc, csts.b.csts_cfs); 1390 atomic_inc_32(&nvme->n_cmd_timeout); 1391 1392 if (csts.b.csts_cfs || 1393 nvme_check_regs_hdl(nvme) || 1394 nvme_check_dma_hdl(cmd->nc_dma) || 1395 cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT) { 1396 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 1397 nvme->n_dead = B_TRUE; 1398 } else if (nvme_abort_cmd(cmd, sec) == 0) { 1399 /* 1400 * If the abort succeeded the command should complete 1401 * immediately with an appropriate status. 1402 */ 1403 while (!cmd->nc_completed) 1404 cv_wait(&cmd->nc_cv, &cmd->nc_mutex); 1405 1406 return; 1407 } 1408 1409 qp = nvme->n_ioq[cmd->nc_sqid]; 1410 1411 mutex_enter(&qp->nq_mutex); 1412 (void) nvme_unqueue_cmd(nvme, qp, cmd->nc_sqe.sqe_cid); 1413 mutex_exit(&qp->nq_mutex); 1414 1415 /* 1416 * As we don't know what the presumed dead hardware might still do with 1417 * the DMA memory, we'll put the command on the lost commands list if it 1418 * has any DMA memory. 1419 */ 1420 if (cmd->nc_dma != NULL) { 1421 mutex_enter(&nvme_lc_mutex); 1422 list_insert_head(&nvme_lost_cmds, cmd); 1423 mutex_exit(&nvme_lc_mutex); 1424 } 1425 } 1426 1427 static void 1428 nvme_wakeup_cmd(void *arg) 1429 { 1430 nvme_cmd_t *cmd = arg; 1431 1432 mutex_enter(&cmd->nc_mutex); 1433 cmd->nc_completed = B_TRUE; 1434 cv_signal(&cmd->nc_cv); 1435 mutex_exit(&cmd->nc_mutex); 1436 } 1437 1438 static void 1439 nvme_async_event_task(void *arg) 1440 { 1441 nvme_cmd_t *cmd = arg; 1442 nvme_t *nvme = cmd->nc_nvme; 1443 nvme_error_log_entry_t *error_log = NULL; 1444 nvme_health_log_t *health_log = NULL; 1445 size_t logsize = 0; 1446 nvme_async_event_t event; 1447 1448 /* 1449 * Check for errors associated with the async request itself. The only 1450 * command-specific error is "async event limit exceeded", which 1451 * indicates a programming error in the driver and causes a panic in 1452 * nvme_check_cmd_status(). 1453 * 1454 * Other possible errors are various scenarios where the async request 1455 * was aborted, or internal errors in the device. Internal errors are 1456 * reported to FMA, the command aborts need no special handling here. 1457 * 1458 * And finally, at least qemu nvme does not support async events, 1459 * and will return NVME_CQE_SC_GEN_INV_OPC | DNR. If so, we 1460 * will avoid posting async events. 1461 */ 1462 1463 if (nvme_check_cmd_status(cmd) != 0) { 1464 dev_err(cmd->nc_nvme->n_dip, CE_WARN, 1465 "!async event request returned failure, sct = %x, " 1466 "sc = %x, dnr = %d, m = %d", cmd->nc_cqe.cqe_sf.sf_sct, 1467 cmd->nc_cqe.cqe_sf.sf_sc, cmd->nc_cqe.cqe_sf.sf_dnr, 1468 cmd->nc_cqe.cqe_sf.sf_m); 1469 1470 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC && 1471 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INTERNAL_ERR) { 1472 cmd->nc_nvme->n_dead = B_TRUE; 1473 ddi_fm_service_impact(cmd->nc_nvme->n_dip, 1474 DDI_SERVICE_LOST); 1475 } 1476 1477 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC && 1478 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_OPC && 1479 cmd->nc_cqe.cqe_sf.sf_dnr == 1) { 1480 nvme->n_async_event_supported = B_FALSE; 1481 } 1482 1483 nvme_free_cmd(cmd); 1484 return; 1485 } 1486 1487 1488 event.r = cmd->nc_cqe.cqe_dw0; 1489 1490 /* Clear CQE and re-submit the async request. */ 1491 bzero(&cmd->nc_cqe, sizeof (nvme_cqe_t)); 1492 nvme_submit_admin_cmd(nvme->n_adminq, cmd); 1493 1494 switch (event.b.ae_type) { 1495 case NVME_ASYNC_TYPE_ERROR: 1496 if (event.b.ae_logpage == NVME_LOGPAGE_ERROR) { 1497 (void) nvme_get_logpage(nvme, (void **)&error_log, 1498 &logsize, event.b.ae_logpage); 1499 } else { 1500 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in " 1501 "async event reply: %d", event.b.ae_logpage); 1502 atomic_inc_32(&nvme->n_wrong_logpage); 1503 } 1504 1505 switch (event.b.ae_info) { 1506 case NVME_ASYNC_ERROR_INV_SQ: 1507 dev_err(nvme->n_dip, CE_PANIC, "programming error: " 1508 "invalid submission queue"); 1509 return; 1510 1511 case NVME_ASYNC_ERROR_INV_DBL: 1512 dev_err(nvme->n_dip, CE_PANIC, "programming error: " 1513 "invalid doorbell write value"); 1514 return; 1515 1516 case NVME_ASYNC_ERROR_DIAGFAIL: 1517 dev_err(nvme->n_dip, CE_WARN, "!diagnostic failure"); 1518 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 1519 nvme->n_dead = B_TRUE; 1520 atomic_inc_32(&nvme->n_diagfail_event); 1521 break; 1522 1523 case NVME_ASYNC_ERROR_PERSISTENT: 1524 dev_err(nvme->n_dip, CE_WARN, "!persistent internal " 1525 "device error"); 1526 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 1527 nvme->n_dead = B_TRUE; 1528 atomic_inc_32(&nvme->n_persistent_event); 1529 break; 1530 1531 case NVME_ASYNC_ERROR_TRANSIENT: 1532 dev_err(nvme->n_dip, CE_WARN, "!transient internal " 1533 "device error"); 1534 /* TODO: send ereport */ 1535 atomic_inc_32(&nvme->n_transient_event); 1536 break; 1537 1538 case NVME_ASYNC_ERROR_FW_LOAD: 1539 dev_err(nvme->n_dip, CE_WARN, 1540 "!firmware image load error"); 1541 atomic_inc_32(&nvme->n_fw_load_event); 1542 break; 1543 } 1544 break; 1545 1546 case NVME_ASYNC_TYPE_HEALTH: 1547 if (event.b.ae_logpage == NVME_LOGPAGE_HEALTH) { 1548 (void) nvme_get_logpage(nvme, (void **)&health_log, 1549 &logsize, event.b.ae_logpage, -1); 1550 } else { 1551 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in " 1552 "async event reply: %d", event.b.ae_logpage); 1553 atomic_inc_32(&nvme->n_wrong_logpage); 1554 } 1555 1556 switch (event.b.ae_info) { 1557 case NVME_ASYNC_HEALTH_RELIABILITY: 1558 dev_err(nvme->n_dip, CE_WARN, 1559 "!device reliability compromised"); 1560 /* TODO: send ereport */ 1561 atomic_inc_32(&nvme->n_reliability_event); 1562 break; 1563 1564 case NVME_ASYNC_HEALTH_TEMPERATURE: 1565 dev_err(nvme->n_dip, CE_WARN, 1566 "!temperature above threshold"); 1567 /* TODO: send ereport */ 1568 atomic_inc_32(&nvme->n_temperature_event); 1569 break; 1570 1571 case NVME_ASYNC_HEALTH_SPARE: 1572 dev_err(nvme->n_dip, CE_WARN, 1573 "!spare space below threshold"); 1574 /* TODO: send ereport */ 1575 atomic_inc_32(&nvme->n_spare_event); 1576 break; 1577 } 1578 break; 1579 1580 case NVME_ASYNC_TYPE_VENDOR: 1581 dev_err(nvme->n_dip, CE_WARN, "!vendor specific async event " 1582 "received, info = %x, logpage = %x", event.b.ae_info, 1583 event.b.ae_logpage); 1584 atomic_inc_32(&nvme->n_vendor_event); 1585 break; 1586 1587 default: 1588 dev_err(nvme->n_dip, CE_WARN, "!unknown async event received, " 1589 "type = %x, info = %x, logpage = %x", event.b.ae_type, 1590 event.b.ae_info, event.b.ae_logpage); 1591 atomic_inc_32(&nvme->n_unknown_event); 1592 break; 1593 } 1594 1595 if (error_log) 1596 kmem_free(error_log, logsize); 1597 1598 if (health_log) 1599 kmem_free(health_log, logsize); 1600 } 1601 1602 static void 1603 nvme_admin_cmd(nvme_cmd_t *cmd, int sec) 1604 { 1605 mutex_enter(&cmd->nc_mutex); 1606 nvme_submit_admin_cmd(cmd->nc_nvme->n_adminq, cmd); 1607 nvme_wait_cmd(cmd, sec); 1608 mutex_exit(&cmd->nc_mutex); 1609 } 1610 1611 static void 1612 nvme_async_event(nvme_t *nvme) 1613 { 1614 nvme_cmd_t *cmd; 1615 1616 cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1617 cmd->nc_sqid = 0; 1618 cmd->nc_sqe.sqe_opc = NVME_OPC_ASYNC_EVENT; 1619 cmd->nc_callback = nvme_async_event_task; 1620 cmd->nc_dontpanic = B_TRUE; 1621 1622 nvme_submit_admin_cmd(nvme->n_adminq, cmd); 1623 } 1624 1625 static int 1626 nvme_format_nvm(nvme_t *nvme, uint32_t nsid, uint8_t lbaf, boolean_t ms, 1627 uint8_t pi, boolean_t pil, uint8_t ses) 1628 { 1629 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1630 nvme_format_nvm_t format_nvm = { 0 }; 1631 int ret; 1632 1633 format_nvm.b.fm_lbaf = lbaf & 0xf; 1634 format_nvm.b.fm_ms = ms ? 1 : 0; 1635 format_nvm.b.fm_pi = pi & 0x7; 1636 format_nvm.b.fm_pil = pil ? 1 : 0; 1637 format_nvm.b.fm_ses = ses & 0x7; 1638 1639 cmd->nc_sqid = 0; 1640 cmd->nc_callback = nvme_wakeup_cmd; 1641 cmd->nc_sqe.sqe_nsid = nsid; 1642 cmd->nc_sqe.sqe_opc = NVME_OPC_NVM_FORMAT; 1643 cmd->nc_sqe.sqe_cdw10 = format_nvm.r; 1644 1645 /* 1646 * Some devices like Samsung SM951 don't allow formatting of all 1647 * namespaces in one command. Handle that gracefully. 1648 */ 1649 if (nsid == (uint32_t)-1) 1650 cmd->nc_dontpanic = B_TRUE; 1651 1652 nvme_admin_cmd(cmd, nvme_format_cmd_timeout); 1653 1654 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1655 dev_err(nvme->n_dip, CE_WARN, 1656 "!FORMAT failed with sct = %x, sc = %x", 1657 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 1658 } 1659 1660 nvme_free_cmd(cmd); 1661 return (ret); 1662 } 1663 1664 static int 1665 nvme_get_logpage(nvme_t *nvme, void **buf, size_t *bufsize, uint8_t logpage, 1666 ...) 1667 { 1668 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1669 nvme_getlogpage_t getlogpage = { 0 }; 1670 va_list ap; 1671 int ret; 1672 1673 va_start(ap, logpage); 1674 1675 cmd->nc_sqid = 0; 1676 cmd->nc_callback = nvme_wakeup_cmd; 1677 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_LOG_PAGE; 1678 1679 getlogpage.b.lp_lid = logpage; 1680 1681 switch (logpage) { 1682 case NVME_LOGPAGE_ERROR: 1683 cmd->nc_sqe.sqe_nsid = (uint32_t)-1; 1684 /* 1685 * The GET LOG PAGE command can use at most 2 pages to return 1686 * data, PRP lists are not supported. 1687 */ 1688 *bufsize = MIN(2 * nvme->n_pagesize, 1689 nvme->n_error_log_len * sizeof (nvme_error_log_entry_t)); 1690 break; 1691 1692 case NVME_LOGPAGE_HEALTH: 1693 cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t); 1694 *bufsize = sizeof (nvme_health_log_t); 1695 break; 1696 1697 case NVME_LOGPAGE_FWSLOT: 1698 cmd->nc_sqe.sqe_nsid = (uint32_t)-1; 1699 *bufsize = sizeof (nvme_fwslot_log_t); 1700 break; 1701 1702 default: 1703 dev_err(nvme->n_dip, CE_WARN, "!unknown log page requested: %d", 1704 logpage); 1705 atomic_inc_32(&nvme->n_unknown_logpage); 1706 ret = EINVAL; 1707 goto fail; 1708 } 1709 1710 va_end(ap); 1711 1712 getlogpage.b.lp_numd = *bufsize / sizeof (uint32_t) - 1; 1713 1714 cmd->nc_sqe.sqe_cdw10 = getlogpage.r; 1715 1716 if (nvme_zalloc_dma(nvme, getlogpage.b.lp_numd * sizeof (uint32_t), 1717 DDI_DMA_READ, &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) { 1718 dev_err(nvme->n_dip, CE_WARN, 1719 "!nvme_zalloc_dma failed for GET LOG PAGE"); 1720 ret = ENOMEM; 1721 goto fail; 1722 } 1723 1724 if (cmd->nc_dma->nd_ncookie > 2) { 1725 dev_err(nvme->n_dip, CE_WARN, 1726 "!too many DMA cookies for GET LOG PAGE"); 1727 atomic_inc_32(&nvme->n_too_many_cookies); 1728 ret = ENOMEM; 1729 goto fail; 1730 } 1731 1732 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress; 1733 if (cmd->nc_dma->nd_ncookie > 1) { 1734 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah, 1735 &cmd->nc_dma->nd_cookie); 1736 cmd->nc_sqe.sqe_dptr.d_prp[1] = 1737 cmd->nc_dma->nd_cookie.dmac_laddress; 1738 } 1739 1740 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 1741 1742 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1743 dev_err(nvme->n_dip, CE_WARN, 1744 "!GET LOG PAGE failed with sct = %x, sc = %x", 1745 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 1746 goto fail; 1747 } 1748 1749 *buf = kmem_alloc(*bufsize, KM_SLEEP); 1750 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize); 1751 1752 fail: 1753 nvme_free_cmd(cmd); 1754 1755 return (ret); 1756 } 1757 1758 static int 1759 nvme_identify(nvme_t *nvme, uint32_t nsid, void **buf) 1760 { 1761 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1762 int ret; 1763 1764 if (buf == NULL) 1765 return (EINVAL); 1766 1767 cmd->nc_sqid = 0; 1768 cmd->nc_callback = nvme_wakeup_cmd; 1769 cmd->nc_sqe.sqe_opc = NVME_OPC_IDENTIFY; 1770 cmd->nc_sqe.sqe_nsid = nsid; 1771 cmd->nc_sqe.sqe_cdw10 = nsid ? NVME_IDENTIFY_NSID : NVME_IDENTIFY_CTRL; 1772 1773 if (nvme_zalloc_dma(nvme, NVME_IDENTIFY_BUFSIZE, DDI_DMA_READ, 1774 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) { 1775 dev_err(nvme->n_dip, CE_WARN, 1776 "!nvme_zalloc_dma failed for IDENTIFY"); 1777 ret = ENOMEM; 1778 goto fail; 1779 } 1780 1781 if (cmd->nc_dma->nd_ncookie > 2) { 1782 dev_err(nvme->n_dip, CE_WARN, 1783 "!too many DMA cookies for IDENTIFY"); 1784 atomic_inc_32(&nvme->n_too_many_cookies); 1785 ret = ENOMEM; 1786 goto fail; 1787 } 1788 1789 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress; 1790 if (cmd->nc_dma->nd_ncookie > 1) { 1791 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah, 1792 &cmd->nc_dma->nd_cookie); 1793 cmd->nc_sqe.sqe_dptr.d_prp[1] = 1794 cmd->nc_dma->nd_cookie.dmac_laddress; 1795 } 1796 1797 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 1798 1799 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1800 dev_err(nvme->n_dip, CE_WARN, 1801 "!IDENTIFY failed with sct = %x, sc = %x", 1802 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 1803 goto fail; 1804 } 1805 1806 *buf = kmem_alloc(NVME_IDENTIFY_BUFSIZE, KM_SLEEP); 1807 bcopy(cmd->nc_dma->nd_memp, *buf, NVME_IDENTIFY_BUFSIZE); 1808 1809 fail: 1810 nvme_free_cmd(cmd); 1811 1812 return (ret); 1813 } 1814 1815 static int 1816 nvme_set_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t val, 1817 uint32_t *res) 1818 { 1819 _NOTE(ARGUNUSED(nsid)); 1820 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1821 int ret = EINVAL; 1822 1823 ASSERT(res != NULL); 1824 1825 cmd->nc_sqid = 0; 1826 cmd->nc_callback = nvme_wakeup_cmd; 1827 cmd->nc_sqe.sqe_opc = NVME_OPC_SET_FEATURES; 1828 cmd->nc_sqe.sqe_cdw10 = feature; 1829 cmd->nc_sqe.sqe_cdw11 = val; 1830 1831 switch (feature) { 1832 case NVME_FEAT_WRITE_CACHE: 1833 if (!nvme->n_write_cache_present) 1834 goto fail; 1835 break; 1836 1837 case NVME_FEAT_NQUEUES: 1838 break; 1839 1840 default: 1841 goto fail; 1842 } 1843 1844 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 1845 1846 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1847 dev_err(nvme->n_dip, CE_WARN, 1848 "!SET FEATURES %d failed with sct = %x, sc = %x", 1849 feature, cmd->nc_cqe.cqe_sf.sf_sct, 1850 cmd->nc_cqe.cqe_sf.sf_sc); 1851 goto fail; 1852 } 1853 1854 *res = cmd->nc_cqe.cqe_dw0; 1855 1856 fail: 1857 nvme_free_cmd(cmd); 1858 return (ret); 1859 } 1860 1861 static int 1862 nvme_get_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t *res, 1863 void **buf, size_t *bufsize) 1864 { 1865 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 1866 int ret = EINVAL; 1867 1868 ASSERT(res != NULL); 1869 1870 if (bufsize != NULL) 1871 *bufsize = 0; 1872 1873 cmd->nc_sqid = 0; 1874 cmd->nc_callback = nvme_wakeup_cmd; 1875 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_FEATURES; 1876 cmd->nc_sqe.sqe_cdw10 = feature; 1877 cmd->nc_sqe.sqe_cdw11 = *res; 1878 1879 /* 1880 * For some of the optional features there doesn't seem to be a method 1881 * of detecting whether it is supported other than using it. This will 1882 * cause "Invalid Field in Command" error, which is normally considered 1883 * a programming error. Set the nc_dontpanic flag to override the panic 1884 * in nvme_check_generic_cmd_status(). 1885 */ 1886 switch (feature) { 1887 case NVME_FEAT_ARBITRATION: 1888 case NVME_FEAT_POWER_MGMT: 1889 case NVME_FEAT_TEMPERATURE: 1890 case NVME_FEAT_ERROR: 1891 case NVME_FEAT_NQUEUES: 1892 case NVME_FEAT_INTR_COAL: 1893 case NVME_FEAT_INTR_VECT: 1894 case NVME_FEAT_WRITE_ATOM: 1895 case NVME_FEAT_ASYNC_EVENT: 1896 break; 1897 1898 case NVME_FEAT_WRITE_CACHE: 1899 if (!nvme->n_write_cache_present) 1900 goto fail; 1901 break; 1902 1903 case NVME_FEAT_LBA_RANGE: 1904 if (!nvme->n_lba_range_supported) 1905 goto fail; 1906 1907 cmd->nc_dontpanic = B_TRUE; 1908 cmd->nc_sqe.sqe_nsid = nsid; 1909 ASSERT(bufsize != NULL); 1910 *bufsize = NVME_LBA_RANGE_BUFSIZE; 1911 break; 1912 1913 case NVME_FEAT_AUTO_PST: 1914 if (!nvme->n_auto_pst_supported) 1915 goto fail; 1916 1917 ASSERT(bufsize != NULL); 1918 *bufsize = NVME_AUTO_PST_BUFSIZE; 1919 break; 1920 1921 case NVME_FEAT_PROGRESS: 1922 if (!nvme->n_progress_supported) 1923 goto fail; 1924 1925 cmd->nc_dontpanic = B_TRUE; 1926 break; 1927 1928 default: 1929 goto fail; 1930 } 1931 1932 if (bufsize != NULL && *bufsize != 0) { 1933 if (nvme_zalloc_dma(nvme, *bufsize, DDI_DMA_READ, 1934 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) { 1935 dev_err(nvme->n_dip, CE_WARN, 1936 "!nvme_zalloc_dma failed for GET FEATURES"); 1937 ret = ENOMEM; 1938 goto fail; 1939 } 1940 1941 if (cmd->nc_dma->nd_ncookie > 2) { 1942 dev_err(nvme->n_dip, CE_WARN, 1943 "!too many DMA cookies for GET FEATURES"); 1944 atomic_inc_32(&nvme->n_too_many_cookies); 1945 ret = ENOMEM; 1946 goto fail; 1947 } 1948 1949 cmd->nc_sqe.sqe_dptr.d_prp[0] = 1950 cmd->nc_dma->nd_cookie.dmac_laddress; 1951 if (cmd->nc_dma->nd_ncookie > 1) { 1952 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah, 1953 &cmd->nc_dma->nd_cookie); 1954 cmd->nc_sqe.sqe_dptr.d_prp[1] = 1955 cmd->nc_dma->nd_cookie.dmac_laddress; 1956 } 1957 } 1958 1959 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 1960 1961 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 1962 boolean_t known = B_TRUE; 1963 1964 /* Check if this is unsupported optional feature */ 1965 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC && 1966 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INV_FLD) { 1967 switch (feature) { 1968 case NVME_FEAT_LBA_RANGE: 1969 nvme->n_lba_range_supported = B_FALSE; 1970 break; 1971 case NVME_FEAT_PROGRESS: 1972 nvme->n_progress_supported = B_FALSE; 1973 break; 1974 default: 1975 known = B_FALSE; 1976 break; 1977 } 1978 } else { 1979 known = B_FALSE; 1980 } 1981 1982 /* Report the error otherwise */ 1983 if (!known) { 1984 dev_err(nvme->n_dip, CE_WARN, 1985 "!GET FEATURES %d failed with sct = %x, sc = %x", 1986 feature, cmd->nc_cqe.cqe_sf.sf_sct, 1987 cmd->nc_cqe.cqe_sf.sf_sc); 1988 } 1989 1990 goto fail; 1991 } 1992 1993 if (bufsize != NULL && *bufsize != 0) { 1994 ASSERT(buf != NULL); 1995 *buf = kmem_alloc(*bufsize, KM_SLEEP); 1996 bcopy(cmd->nc_dma->nd_memp, *buf, *bufsize); 1997 } 1998 1999 *res = cmd->nc_cqe.cqe_dw0; 2000 2001 fail: 2002 nvme_free_cmd(cmd); 2003 return (ret); 2004 } 2005 2006 static int 2007 nvme_write_cache_set(nvme_t *nvme, boolean_t enable) 2008 { 2009 nvme_write_cache_t nwc = { 0 }; 2010 2011 if (enable) 2012 nwc.b.wc_wce = 1; 2013 2014 return (nvme_set_features(nvme, 0, NVME_FEAT_WRITE_CACHE, nwc.r, 2015 &nwc.r)); 2016 } 2017 2018 static int 2019 nvme_set_nqueues(nvme_t *nvme, uint16_t *nqueues) 2020 { 2021 nvme_nqueues_t nq = { 0 }; 2022 int ret; 2023 2024 nq.b.nq_nsq = nq.b.nq_ncq = *nqueues - 1; 2025 2026 ret = nvme_set_features(nvme, 0, NVME_FEAT_NQUEUES, nq.r, &nq.r); 2027 2028 if (ret == 0) { 2029 /* 2030 * Always use the same number of submission and completion 2031 * queues, and never use more than the requested number of 2032 * queues. 2033 */ 2034 *nqueues = MIN(*nqueues, MIN(nq.b.nq_nsq, nq.b.nq_ncq) + 1); 2035 } 2036 2037 return (ret); 2038 } 2039 2040 static int 2041 nvme_create_io_qpair(nvme_t *nvme, nvme_qpair_t *qp, uint16_t idx) 2042 { 2043 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 2044 nvme_create_queue_dw10_t dw10 = { 0 }; 2045 nvme_create_cq_dw11_t c_dw11 = { 0 }; 2046 nvme_create_sq_dw11_t s_dw11 = { 0 }; 2047 int ret; 2048 2049 dw10.b.q_qid = idx; 2050 dw10.b.q_qsize = qp->nq_nentry - 1; 2051 2052 c_dw11.b.cq_pc = 1; 2053 c_dw11.b.cq_ien = 1; 2054 c_dw11.b.cq_iv = idx % nvme->n_intr_cnt; 2055 2056 cmd->nc_sqid = 0; 2057 cmd->nc_callback = nvme_wakeup_cmd; 2058 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_CQUEUE; 2059 cmd->nc_sqe.sqe_cdw10 = dw10.r; 2060 cmd->nc_sqe.sqe_cdw11 = c_dw11.r; 2061 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_cqdma->nd_cookie.dmac_laddress; 2062 2063 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 2064 2065 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 2066 dev_err(nvme->n_dip, CE_WARN, 2067 "!CREATE CQUEUE failed with sct = %x, sc = %x", 2068 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 2069 goto fail; 2070 } 2071 2072 nvme_free_cmd(cmd); 2073 2074 s_dw11.b.sq_pc = 1; 2075 s_dw11.b.sq_cqid = idx; 2076 2077 cmd = nvme_alloc_cmd(nvme, KM_SLEEP); 2078 cmd->nc_sqid = 0; 2079 cmd->nc_callback = nvme_wakeup_cmd; 2080 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_SQUEUE; 2081 cmd->nc_sqe.sqe_cdw10 = dw10.r; 2082 cmd->nc_sqe.sqe_cdw11 = s_dw11.r; 2083 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_sqdma->nd_cookie.dmac_laddress; 2084 2085 nvme_admin_cmd(cmd, nvme_admin_cmd_timeout); 2086 2087 if ((ret = nvme_check_cmd_status(cmd)) != 0) { 2088 dev_err(nvme->n_dip, CE_WARN, 2089 "!CREATE SQUEUE failed with sct = %x, sc = %x", 2090 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc); 2091 goto fail; 2092 } 2093 2094 fail: 2095 nvme_free_cmd(cmd); 2096 2097 return (ret); 2098 } 2099 2100 static boolean_t 2101 nvme_reset(nvme_t *nvme, boolean_t quiesce) 2102 { 2103 nvme_reg_csts_t csts; 2104 int i; 2105 2106 nvme_put32(nvme, NVME_REG_CC, 0); 2107 2108 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2109 if (csts.b.csts_rdy == 1) { 2110 nvme_put32(nvme, NVME_REG_CC, 0); 2111 for (i = 0; i != nvme->n_timeout * 10; i++) { 2112 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2113 if (csts.b.csts_rdy == 0) 2114 break; 2115 2116 if (quiesce) 2117 drv_usecwait(50000); 2118 else 2119 delay(drv_usectohz(50000)); 2120 } 2121 } 2122 2123 nvme_put32(nvme, NVME_REG_AQA, 0); 2124 nvme_put32(nvme, NVME_REG_ASQ, 0); 2125 nvme_put32(nvme, NVME_REG_ACQ, 0); 2126 2127 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2128 return (csts.b.csts_rdy == 0 ? B_TRUE : B_FALSE); 2129 } 2130 2131 static void 2132 nvme_shutdown(nvme_t *nvme, int mode, boolean_t quiesce) 2133 { 2134 nvme_reg_cc_t cc; 2135 nvme_reg_csts_t csts; 2136 int i; 2137 2138 ASSERT(mode == NVME_CC_SHN_NORMAL || mode == NVME_CC_SHN_ABRUPT); 2139 2140 cc.r = nvme_get32(nvme, NVME_REG_CC); 2141 cc.b.cc_shn = mode & 0x3; 2142 nvme_put32(nvme, NVME_REG_CC, cc.r); 2143 2144 for (i = 0; i != 10; i++) { 2145 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2146 if (csts.b.csts_shst == NVME_CSTS_SHN_COMPLETE) 2147 break; 2148 2149 if (quiesce) 2150 drv_usecwait(100000); 2151 else 2152 delay(drv_usectohz(100000)); 2153 } 2154 } 2155 2156 2157 static void 2158 nvme_prepare_devid(nvme_t *nvme, uint32_t nsid) 2159 { 2160 /* 2161 * Section 7.7 of the spec describes how to get a unique ID for 2162 * the controller: the vendor ID, the model name and the serial 2163 * number shall be unique when combined. 2164 * 2165 * If a namespace has no EUI64 we use the above and add the hex 2166 * namespace ID to get a unique ID for the namespace. 2167 */ 2168 char model[sizeof (nvme->n_idctl->id_model) + 1]; 2169 char serial[sizeof (nvme->n_idctl->id_serial) + 1]; 2170 2171 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model)); 2172 bcopy(nvme->n_idctl->id_serial, serial, 2173 sizeof (nvme->n_idctl->id_serial)); 2174 2175 model[sizeof (nvme->n_idctl->id_model)] = '\0'; 2176 serial[sizeof (nvme->n_idctl->id_serial)] = '\0'; 2177 2178 nvme->n_ns[nsid - 1].ns_devid = kmem_asprintf("%4X-%s-%s-%X", 2179 nvme->n_idctl->id_vid, model, serial, nsid); 2180 } 2181 2182 static int 2183 nvme_init_ns(nvme_t *nvme, int nsid) 2184 { 2185 nvme_namespace_t *ns = &nvme->n_ns[nsid - 1]; 2186 nvme_identify_nsid_t *idns; 2187 int last_rp; 2188 2189 ns->ns_nvme = nvme; 2190 2191 if (nvme_identify(nvme, nsid, (void **)&idns) != 0) { 2192 dev_err(nvme->n_dip, CE_WARN, 2193 "!failed to identify namespace %d", nsid); 2194 return (DDI_FAILURE); 2195 } 2196 2197 ns->ns_idns = idns; 2198 ns->ns_id = nsid; 2199 ns->ns_block_count = idns->id_nsize; 2200 ns->ns_block_size = 2201 1 << idns->id_lbaf[idns->id_flbas.lba_format].lbaf_lbads; 2202 ns->ns_best_block_size = ns->ns_block_size; 2203 2204 /* 2205 * Get the EUI64 if present. Use it for devid and device node names. 2206 */ 2207 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1)) 2208 bcopy(idns->id_eui64, ns->ns_eui64, sizeof (ns->ns_eui64)); 2209 2210 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 2211 if (*(uint64_t *)ns->ns_eui64 != 0) { 2212 uint8_t *eui64 = ns->ns_eui64; 2213 2214 (void) snprintf(ns->ns_name, sizeof (ns->ns_name), 2215 "%02x%02x%02x%02x%02x%02x%02x%02x", 2216 eui64[0], eui64[1], eui64[2], eui64[3], 2217 eui64[4], eui64[5], eui64[6], eui64[7]); 2218 } else { 2219 (void) snprintf(ns->ns_name, sizeof (ns->ns_name), "%d", 2220 ns->ns_id); 2221 2222 nvme_prepare_devid(nvme, ns->ns_id); 2223 } 2224 2225 /* 2226 * Find the LBA format with no metadata and the best relative 2227 * performance. A value of 3 means "degraded", 0 is best. 2228 */ 2229 last_rp = 3; 2230 for (int j = 0; j <= idns->id_nlbaf; j++) { 2231 if (idns->id_lbaf[j].lbaf_lbads == 0) 2232 break; 2233 if (idns->id_lbaf[j].lbaf_ms != 0) 2234 continue; 2235 if (idns->id_lbaf[j].lbaf_rp >= last_rp) 2236 continue; 2237 last_rp = idns->id_lbaf[j].lbaf_rp; 2238 ns->ns_best_block_size = 2239 1 << idns->id_lbaf[j].lbaf_lbads; 2240 } 2241 2242 if (ns->ns_best_block_size < nvme->n_min_block_size) 2243 ns->ns_best_block_size = nvme->n_min_block_size; 2244 2245 /* 2246 * We currently don't support namespaces that use either: 2247 * - protection information 2248 * - illegal block size (< 512) 2249 */ 2250 if (idns->id_dps.dp_pinfo) { 2251 dev_err(nvme->n_dip, CE_WARN, 2252 "!ignoring namespace %d, unsupported feature: " 2253 "pinfo = %d", nsid, idns->id_dps.dp_pinfo); 2254 ns->ns_ignore = B_TRUE; 2255 } else if (ns->ns_block_size < 512) { 2256 dev_err(nvme->n_dip, CE_WARN, 2257 "!ignoring namespace %d, unsupported block size %"PRIu64, 2258 nsid, (uint64_t)ns->ns_block_size); 2259 ns->ns_ignore = B_TRUE; 2260 } else { 2261 ns->ns_ignore = B_FALSE; 2262 } 2263 2264 return (DDI_SUCCESS); 2265 } 2266 2267 static int 2268 nvme_init(nvme_t *nvme) 2269 { 2270 nvme_reg_cc_t cc = { 0 }; 2271 nvme_reg_aqa_t aqa = { 0 }; 2272 nvme_reg_asq_t asq = { 0 }; 2273 nvme_reg_acq_t acq = { 0 }; 2274 nvme_reg_cap_t cap; 2275 nvme_reg_vs_t vs; 2276 nvme_reg_csts_t csts; 2277 int i = 0; 2278 uint16_t nqueues; 2279 char model[sizeof (nvme->n_idctl->id_model) + 1]; 2280 char *vendor, *product; 2281 2282 /* Check controller version */ 2283 vs.r = nvme_get32(nvme, NVME_REG_VS); 2284 nvme->n_version.v_major = vs.b.vs_mjr; 2285 nvme->n_version.v_minor = vs.b.vs_mnr; 2286 dev_err(nvme->n_dip, CE_CONT, "?NVMe spec version %d.%d", 2287 nvme->n_version.v_major, nvme->n_version.v_minor); 2288 2289 if (nvme->n_version.v_major > nvme_version_major) { 2290 dev_err(nvme->n_dip, CE_WARN, "!no support for version > %d.x", 2291 nvme_version_major); 2292 if (nvme->n_strict_version) 2293 goto fail; 2294 } 2295 2296 /* retrieve controller configuration */ 2297 cap.r = nvme_get64(nvme, NVME_REG_CAP); 2298 2299 if ((cap.b.cap_css & NVME_CAP_CSS_NVM) == 0) { 2300 dev_err(nvme->n_dip, CE_WARN, 2301 "!NVM command set not supported by hardware"); 2302 goto fail; 2303 } 2304 2305 nvme->n_nssr_supported = cap.b.cap_nssrs; 2306 nvme->n_doorbell_stride = 4 << cap.b.cap_dstrd; 2307 nvme->n_timeout = cap.b.cap_to; 2308 nvme->n_arbitration_mechanisms = cap.b.cap_ams; 2309 nvme->n_cont_queues_reqd = cap.b.cap_cqr; 2310 nvme->n_max_queue_entries = cap.b.cap_mqes + 1; 2311 2312 /* 2313 * The MPSMIN and MPSMAX fields in the CAP register use 0 to specify 2314 * the base page size of 4k (1<<12), so add 12 here to get the real 2315 * page size value. 2316 */ 2317 nvme->n_pageshift = MIN(MAX(cap.b.cap_mpsmin + 12, PAGESHIFT), 2318 cap.b.cap_mpsmax + 12); 2319 nvme->n_pagesize = 1UL << (nvme->n_pageshift); 2320 2321 /* 2322 * Set up Queue DMA to transfer at least 1 page-aligned page at a time. 2323 */ 2324 nvme->n_queue_dma_attr.dma_attr_align = nvme->n_pagesize; 2325 nvme->n_queue_dma_attr.dma_attr_minxfer = nvme->n_pagesize; 2326 2327 /* 2328 * Set up PRP DMA to transfer 1 page-aligned page at a time. 2329 * Maxxfer may be increased after we identified the controller limits. 2330 */ 2331 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_pagesize; 2332 nvme->n_prp_dma_attr.dma_attr_minxfer = nvme->n_pagesize; 2333 nvme->n_prp_dma_attr.dma_attr_align = nvme->n_pagesize; 2334 nvme->n_prp_dma_attr.dma_attr_seg = nvme->n_pagesize - 1; 2335 2336 /* 2337 * Reset controller if it's still in ready state. 2338 */ 2339 if (nvme_reset(nvme, B_FALSE) == B_FALSE) { 2340 dev_err(nvme->n_dip, CE_WARN, "!unable to reset controller"); 2341 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 2342 nvme->n_dead = B_TRUE; 2343 goto fail; 2344 } 2345 2346 /* 2347 * Create the admin queue pair. 2348 */ 2349 if (nvme_alloc_qpair(nvme, nvme->n_admin_queue_len, &nvme->n_adminq, 0) 2350 != DDI_SUCCESS) { 2351 dev_err(nvme->n_dip, CE_WARN, 2352 "!unable to allocate admin qpair"); 2353 goto fail; 2354 } 2355 nvme->n_ioq = kmem_alloc(sizeof (nvme_qpair_t *), KM_SLEEP); 2356 nvme->n_ioq[0] = nvme->n_adminq; 2357 2358 nvme->n_progress |= NVME_ADMIN_QUEUE; 2359 2360 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, 2361 "admin-queue-len", nvme->n_admin_queue_len); 2362 2363 aqa.b.aqa_asqs = aqa.b.aqa_acqs = nvme->n_admin_queue_len - 1; 2364 asq = nvme->n_adminq->nq_sqdma->nd_cookie.dmac_laddress; 2365 acq = nvme->n_adminq->nq_cqdma->nd_cookie.dmac_laddress; 2366 2367 ASSERT((asq & (nvme->n_pagesize - 1)) == 0); 2368 ASSERT((acq & (nvme->n_pagesize - 1)) == 0); 2369 2370 nvme_put32(nvme, NVME_REG_AQA, aqa.r); 2371 nvme_put64(nvme, NVME_REG_ASQ, asq); 2372 nvme_put64(nvme, NVME_REG_ACQ, acq); 2373 2374 cc.b.cc_ams = 0; /* use Round-Robin arbitration */ 2375 cc.b.cc_css = 0; /* use NVM command set */ 2376 cc.b.cc_mps = nvme->n_pageshift - 12; 2377 cc.b.cc_shn = 0; /* no shutdown in progress */ 2378 cc.b.cc_en = 1; /* enable controller */ 2379 cc.b.cc_iosqes = 6; /* submission queue entry is 2^6 bytes long */ 2380 cc.b.cc_iocqes = 4; /* completion queue entry is 2^4 bytes long */ 2381 2382 nvme_put32(nvme, NVME_REG_CC, cc.r); 2383 2384 /* 2385 * Wait for the controller to become ready. 2386 */ 2387 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2388 if (csts.b.csts_rdy == 0) { 2389 for (i = 0; i != nvme->n_timeout * 10; i++) { 2390 delay(drv_usectohz(50000)); 2391 csts.r = nvme_get32(nvme, NVME_REG_CSTS); 2392 2393 if (csts.b.csts_cfs == 1) { 2394 dev_err(nvme->n_dip, CE_WARN, 2395 "!controller fatal status at init"); 2396 ddi_fm_service_impact(nvme->n_dip, 2397 DDI_SERVICE_LOST); 2398 nvme->n_dead = B_TRUE; 2399 goto fail; 2400 } 2401 2402 if (csts.b.csts_rdy == 1) 2403 break; 2404 } 2405 } 2406 2407 if (csts.b.csts_rdy == 0) { 2408 dev_err(nvme->n_dip, CE_WARN, "!controller not ready"); 2409 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST); 2410 nvme->n_dead = B_TRUE; 2411 goto fail; 2412 } 2413 2414 /* 2415 * Assume an abort command limit of 1. We'll destroy and re-init 2416 * that later when we know the true abort command limit. 2417 */ 2418 sema_init(&nvme->n_abort_sema, 1, NULL, SEMA_DRIVER, NULL); 2419 2420 /* 2421 * Setup initial interrupt for admin queue. 2422 */ 2423 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 1) 2424 != DDI_SUCCESS) && 2425 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 1) 2426 != DDI_SUCCESS) && 2427 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_FIXED, 1) 2428 != DDI_SUCCESS)) { 2429 dev_err(nvme->n_dip, CE_WARN, 2430 "!failed to setup initial interrupt"); 2431 goto fail; 2432 } 2433 2434 /* 2435 * Post an asynchronous event command to catch errors. 2436 * We assume the asynchronous events are supported as required by 2437 * specification (Figure 40 in section 5 of NVMe 1.2). 2438 * However, since at least qemu does not follow the specification, 2439 * we need a mechanism to protect ourselves. 2440 */ 2441 nvme->n_async_event_supported = B_TRUE; 2442 nvme_async_event(nvme); 2443 2444 /* 2445 * Identify Controller 2446 */ 2447 if (nvme_identify(nvme, 0, (void **)&nvme->n_idctl) != 0) { 2448 dev_err(nvme->n_dip, CE_WARN, 2449 "!failed to identify controller"); 2450 goto fail; 2451 } 2452 2453 /* 2454 * Get Vendor & Product ID 2455 */ 2456 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model)); 2457 model[sizeof (nvme->n_idctl->id_model)] = '\0'; 2458 sata_split_model(model, &vendor, &product); 2459 2460 if (vendor == NULL) 2461 nvme->n_vendor = strdup("NVMe"); 2462 else 2463 nvme->n_vendor = strdup(vendor); 2464 2465 nvme->n_product = strdup(product); 2466 2467 /* 2468 * Get controller limits. 2469 */ 2470 nvme->n_async_event_limit = MAX(NVME_MIN_ASYNC_EVENT_LIMIT, 2471 MIN(nvme->n_admin_queue_len / 10, 2472 MIN(nvme->n_idctl->id_aerl + 1, nvme->n_async_event_limit))); 2473 2474 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, 2475 "async-event-limit", nvme->n_async_event_limit); 2476 2477 nvme->n_abort_command_limit = nvme->n_idctl->id_acl + 1; 2478 2479 /* 2480 * Reinitialize the semaphore with the true abort command limit 2481 * supported by the hardware. It's not necessary to disable interrupts 2482 * as only command aborts use the semaphore, and no commands are 2483 * executed or aborted while we're here. 2484 */ 2485 sema_destroy(&nvme->n_abort_sema); 2486 sema_init(&nvme->n_abort_sema, nvme->n_abort_command_limit - 1, NULL, 2487 SEMA_DRIVER, NULL); 2488 2489 nvme->n_progress |= NVME_CTRL_LIMITS; 2490 2491 if (nvme->n_idctl->id_mdts == 0) 2492 nvme->n_max_data_transfer_size = nvme->n_pagesize * 65536; 2493 else 2494 nvme->n_max_data_transfer_size = 2495 1ull << (nvme->n_pageshift + nvme->n_idctl->id_mdts); 2496 2497 nvme->n_error_log_len = nvme->n_idctl->id_elpe + 1; 2498 2499 /* 2500 * Limit n_max_data_transfer_size to what we can handle in one PRP. 2501 * Chained PRPs are currently unsupported. 2502 * 2503 * This is a no-op on hardware which doesn't support a transfer size 2504 * big enough to require chained PRPs. 2505 */ 2506 nvme->n_max_data_transfer_size = MIN(nvme->n_max_data_transfer_size, 2507 (nvme->n_pagesize / sizeof (uint64_t) * nvme->n_pagesize)); 2508 2509 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_max_data_transfer_size; 2510 2511 /* 2512 * Make sure the minimum/maximum queue entry sizes are not 2513 * larger/smaller than the default. 2514 */ 2515 2516 if (((1 << nvme->n_idctl->id_sqes.qes_min) > sizeof (nvme_sqe_t)) || 2517 ((1 << nvme->n_idctl->id_sqes.qes_max) < sizeof (nvme_sqe_t)) || 2518 ((1 << nvme->n_idctl->id_cqes.qes_min) > sizeof (nvme_cqe_t)) || 2519 ((1 << nvme->n_idctl->id_cqes.qes_max) < sizeof (nvme_cqe_t))) 2520 goto fail; 2521 2522 /* 2523 * Check for the presence of a Volatile Write Cache. If present, 2524 * enable or disable based on the value of the property 2525 * volatile-write-cache-enable (default is enabled). 2526 */ 2527 nvme->n_write_cache_present = 2528 nvme->n_idctl->id_vwc.vwc_present == 0 ? B_FALSE : B_TRUE; 2529 2530 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, 2531 "volatile-write-cache-present", 2532 nvme->n_write_cache_present ? 1 : 0); 2533 2534 if (!nvme->n_write_cache_present) { 2535 nvme->n_write_cache_enabled = B_FALSE; 2536 } else if (nvme_write_cache_set(nvme, nvme->n_write_cache_enabled) 2537 != 0) { 2538 dev_err(nvme->n_dip, CE_WARN, 2539 "!failed to %sable volatile write cache", 2540 nvme->n_write_cache_enabled ? "en" : "dis"); 2541 /* 2542 * Assume the cache is (still) enabled. 2543 */ 2544 nvme->n_write_cache_enabled = B_TRUE; 2545 } 2546 2547 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, 2548 "volatile-write-cache-enable", 2549 nvme->n_write_cache_enabled ? 1 : 0); 2550 2551 /* 2552 * Assume LBA Range Type feature is supported. If it isn't this 2553 * will be set to B_FALSE by nvme_get_features(). 2554 */ 2555 nvme->n_lba_range_supported = B_TRUE; 2556 2557 /* 2558 * Check support for Autonomous Power State Transition. 2559 */ 2560 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1)) 2561 nvme->n_auto_pst_supported = 2562 nvme->n_idctl->id_apsta.ap_sup == 0 ? B_FALSE : B_TRUE; 2563 2564 /* 2565 * Assume Software Progress Marker feature is supported. If it isn't 2566 * this will be set to B_FALSE by nvme_get_features(). 2567 */ 2568 nvme->n_progress_supported = B_TRUE; 2569 2570 /* 2571 * Identify Namespaces 2572 */ 2573 nvme->n_namespace_count = nvme->n_idctl->id_nn; 2574 2575 if (nvme->n_namespace_count == 0) { 2576 dev_err(nvme->n_dip, CE_WARN, 2577 "!controllers without namespaces are not supported"); 2578 goto fail; 2579 } 2580 2581 if (nvme->n_namespace_count > NVME_MINOR_MAX) { 2582 dev_err(nvme->n_dip, CE_WARN, 2583 "!too many namespaces: %d, limiting to %d\n", 2584 nvme->n_namespace_count, NVME_MINOR_MAX); 2585 nvme->n_namespace_count = NVME_MINOR_MAX; 2586 } 2587 2588 nvme->n_ns = kmem_zalloc(sizeof (nvme_namespace_t) * 2589 nvme->n_namespace_count, KM_SLEEP); 2590 2591 for (i = 0; i != nvme->n_namespace_count; i++) { 2592 mutex_init(&nvme->n_ns[i].ns_minor.nm_mutex, NULL, MUTEX_DRIVER, 2593 NULL); 2594 if (nvme_init_ns(nvme, i + 1) != DDI_SUCCESS) 2595 goto fail; 2596 } 2597 2598 /* 2599 * Try to set up MSI/MSI-X interrupts. 2600 */ 2601 if ((nvme->n_intr_types & (DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX)) 2602 != 0) { 2603 nvme_release_interrupts(nvme); 2604 2605 nqueues = MIN(UINT16_MAX, ncpus); 2606 2607 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 2608 nqueues) != DDI_SUCCESS) && 2609 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 2610 nqueues) != DDI_SUCCESS)) { 2611 dev_err(nvme->n_dip, CE_WARN, 2612 "!failed to setup MSI/MSI-X interrupts"); 2613 goto fail; 2614 } 2615 } 2616 2617 nqueues = nvme->n_intr_cnt; 2618 2619 /* 2620 * Create I/O queue pairs. 2621 */ 2622 2623 if (nvme_set_nqueues(nvme, &nqueues) != 0) { 2624 dev_err(nvme->n_dip, CE_WARN, 2625 "!failed to set number of I/O queues to %d", 2626 nvme->n_intr_cnt); 2627 goto fail; 2628 } 2629 2630 /* 2631 * Reallocate I/O queue array 2632 */ 2633 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *)); 2634 nvme->n_ioq = kmem_zalloc(sizeof (nvme_qpair_t *) * 2635 (nqueues + 1), KM_SLEEP); 2636 nvme->n_ioq[0] = nvme->n_adminq; 2637 2638 nvme->n_ioq_count = nqueues; 2639 2640 /* 2641 * If we got less queues than we asked for we might as well give 2642 * some of the interrupt vectors back to the system. 2643 */ 2644 if (nvme->n_ioq_count < nvme->n_intr_cnt) { 2645 nvme_release_interrupts(nvme); 2646 2647 if (nvme_setup_interrupts(nvme, nvme->n_intr_type, 2648 nvme->n_ioq_count) != DDI_SUCCESS) { 2649 dev_err(nvme->n_dip, CE_WARN, 2650 "!failed to reduce number of interrupts"); 2651 goto fail; 2652 } 2653 } 2654 2655 /* 2656 * Alloc & register I/O queue pairs 2657 */ 2658 nvme->n_io_queue_len = 2659 MIN(nvme->n_io_queue_len, nvme->n_max_queue_entries); 2660 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, "io-queue-len", 2661 nvme->n_io_queue_len); 2662 2663 for (i = 1; i != nvme->n_ioq_count + 1; i++) { 2664 if (nvme_alloc_qpair(nvme, nvme->n_io_queue_len, 2665 &nvme->n_ioq[i], i) != DDI_SUCCESS) { 2666 dev_err(nvme->n_dip, CE_WARN, 2667 "!unable to allocate I/O qpair %d", i); 2668 goto fail; 2669 } 2670 2671 if (nvme_create_io_qpair(nvme, nvme->n_ioq[i], i) != 0) { 2672 dev_err(nvme->n_dip, CE_WARN, 2673 "!unable to create I/O qpair %d", i); 2674 goto fail; 2675 } 2676 } 2677 2678 /* 2679 * Post more asynchronous events commands to reduce event reporting 2680 * latency as suggested by the spec. 2681 */ 2682 if (nvme->n_async_event_supported) { 2683 for (i = 1; i != nvme->n_async_event_limit; i++) 2684 nvme_async_event(nvme); 2685 } 2686 2687 return (DDI_SUCCESS); 2688 2689 fail: 2690 (void) nvme_reset(nvme, B_FALSE); 2691 return (DDI_FAILURE); 2692 } 2693 2694 static uint_t 2695 nvme_intr(caddr_t arg1, caddr_t arg2) 2696 { 2697 /*LINTED: E_PTR_BAD_CAST_ALIGN*/ 2698 nvme_t *nvme = (nvme_t *)arg1; 2699 int inum = (int)(uintptr_t)arg2; 2700 int ccnt = 0; 2701 int qnum; 2702 nvme_cmd_t *cmd; 2703 2704 if (inum >= nvme->n_intr_cnt) 2705 return (DDI_INTR_UNCLAIMED); 2706 2707 if (nvme->n_dead) 2708 return (nvme->n_intr_type == DDI_INTR_TYPE_FIXED ? 2709 DDI_INTR_UNCLAIMED : DDI_INTR_CLAIMED); 2710 2711 /* 2712 * The interrupt vector a queue uses is calculated as queue_idx % 2713 * intr_cnt in nvme_create_io_qpair(). Iterate through the queue array 2714 * in steps of n_intr_cnt to process all queues using this vector. 2715 */ 2716 for (qnum = inum; 2717 qnum < nvme->n_ioq_count + 1 && nvme->n_ioq[qnum] != NULL; 2718 qnum += nvme->n_intr_cnt) { 2719 while ((cmd = nvme_retrieve_cmd(nvme, nvme->n_ioq[qnum]))) { 2720 taskq_dispatch_ent((taskq_t *)cmd->nc_nvme->n_cmd_taskq, 2721 cmd->nc_callback, cmd, TQ_NOSLEEP, &cmd->nc_tqent); 2722 ccnt++; 2723 } 2724 } 2725 2726 return (ccnt > 0 ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 2727 } 2728 2729 static void 2730 nvme_release_interrupts(nvme_t *nvme) 2731 { 2732 int i; 2733 2734 for (i = 0; i < nvme->n_intr_cnt; i++) { 2735 if (nvme->n_inth[i] == NULL) 2736 break; 2737 2738 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK) 2739 (void) ddi_intr_block_disable(&nvme->n_inth[i], 1); 2740 else 2741 (void) ddi_intr_disable(nvme->n_inth[i]); 2742 2743 (void) ddi_intr_remove_handler(nvme->n_inth[i]); 2744 (void) ddi_intr_free(nvme->n_inth[i]); 2745 } 2746 2747 kmem_free(nvme->n_inth, nvme->n_inth_sz); 2748 nvme->n_inth = NULL; 2749 nvme->n_inth_sz = 0; 2750 2751 nvme->n_progress &= ~NVME_INTERRUPTS; 2752 } 2753 2754 static int 2755 nvme_setup_interrupts(nvme_t *nvme, int intr_type, int nqpairs) 2756 { 2757 int nintrs, navail, count; 2758 int ret; 2759 int i; 2760 2761 if (nvme->n_intr_types == 0) { 2762 ret = ddi_intr_get_supported_types(nvme->n_dip, 2763 &nvme->n_intr_types); 2764 if (ret != DDI_SUCCESS) { 2765 dev_err(nvme->n_dip, CE_WARN, 2766 "!%s: ddi_intr_get_supported types failed", 2767 __func__); 2768 return (ret); 2769 } 2770 #ifdef __x86 2771 if (get_hwenv() == HW_VMWARE) 2772 nvme->n_intr_types &= ~DDI_INTR_TYPE_MSIX; 2773 #endif 2774 } 2775 2776 if ((nvme->n_intr_types & intr_type) == 0) 2777 return (DDI_FAILURE); 2778 2779 ret = ddi_intr_get_nintrs(nvme->n_dip, intr_type, &nintrs); 2780 if (ret != DDI_SUCCESS) { 2781 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_nintrs failed", 2782 __func__); 2783 return (ret); 2784 } 2785 2786 ret = ddi_intr_get_navail(nvme->n_dip, intr_type, &navail); 2787 if (ret != DDI_SUCCESS) { 2788 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_navail failed", 2789 __func__); 2790 return (ret); 2791 } 2792 2793 /* We want at most one interrupt per queue pair. */ 2794 if (navail > nqpairs) 2795 navail = nqpairs; 2796 2797 nvme->n_inth_sz = sizeof (ddi_intr_handle_t) * navail; 2798 nvme->n_inth = kmem_zalloc(nvme->n_inth_sz, KM_SLEEP); 2799 2800 ret = ddi_intr_alloc(nvme->n_dip, nvme->n_inth, intr_type, 0, navail, 2801 &count, 0); 2802 if (ret != DDI_SUCCESS) { 2803 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_alloc failed", 2804 __func__); 2805 goto fail; 2806 } 2807 2808 nvme->n_intr_cnt = count; 2809 2810 ret = ddi_intr_get_pri(nvme->n_inth[0], &nvme->n_intr_pri); 2811 if (ret != DDI_SUCCESS) { 2812 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_pri failed", 2813 __func__); 2814 goto fail; 2815 } 2816 2817 for (i = 0; i < count; i++) { 2818 ret = ddi_intr_add_handler(nvme->n_inth[i], nvme_intr, 2819 (void *)nvme, (void *)(uintptr_t)i); 2820 if (ret != DDI_SUCCESS) { 2821 dev_err(nvme->n_dip, CE_WARN, 2822 "!%s: ddi_intr_add_handler failed", __func__); 2823 goto fail; 2824 } 2825 } 2826 2827 (void) ddi_intr_get_cap(nvme->n_inth[0], &nvme->n_intr_cap); 2828 2829 for (i = 0; i < count; i++) { 2830 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK) 2831 ret = ddi_intr_block_enable(&nvme->n_inth[i], 1); 2832 else 2833 ret = ddi_intr_enable(nvme->n_inth[i]); 2834 2835 if (ret != DDI_SUCCESS) { 2836 dev_err(nvme->n_dip, CE_WARN, 2837 "!%s: enabling interrupt %d failed", __func__, i); 2838 goto fail; 2839 } 2840 } 2841 2842 nvme->n_intr_type = intr_type; 2843 2844 nvme->n_progress |= NVME_INTERRUPTS; 2845 2846 return (DDI_SUCCESS); 2847 2848 fail: 2849 nvme_release_interrupts(nvme); 2850 2851 return (ret); 2852 } 2853 2854 static int 2855 nvme_fm_errcb(dev_info_t *dip, ddi_fm_error_t *fm_error, const void *arg) 2856 { 2857 _NOTE(ARGUNUSED(arg)); 2858 2859 pci_ereport_post(dip, fm_error, NULL); 2860 return (fm_error->fme_status); 2861 } 2862 2863 static int 2864 nvme_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 2865 { 2866 nvme_t *nvme; 2867 int instance; 2868 int nregs; 2869 off_t regsize; 2870 int i; 2871 char name[32]; 2872 2873 if (cmd != DDI_ATTACH) 2874 return (DDI_FAILURE); 2875 2876 instance = ddi_get_instance(dip); 2877 2878 if (ddi_soft_state_zalloc(nvme_state, instance) != DDI_SUCCESS) 2879 return (DDI_FAILURE); 2880 2881 nvme = ddi_get_soft_state(nvme_state, instance); 2882 ddi_set_driver_private(dip, nvme); 2883 nvme->n_dip = dip; 2884 2885 mutex_init(&nvme->n_minor.nm_mutex, NULL, MUTEX_DRIVER, NULL); 2886 2887 nvme->n_strict_version = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2888 DDI_PROP_DONTPASS, "strict-version", 1) == 1 ? B_TRUE : B_FALSE; 2889 nvme->n_ignore_unknown_vendor_status = ddi_prop_get_int(DDI_DEV_T_ANY, 2890 dip, DDI_PROP_DONTPASS, "ignore-unknown-vendor-status", 0) == 1 ? 2891 B_TRUE : B_FALSE; 2892 nvme->n_admin_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2893 DDI_PROP_DONTPASS, "admin-queue-len", NVME_DEFAULT_ADMIN_QUEUE_LEN); 2894 nvme->n_io_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2895 DDI_PROP_DONTPASS, "io-queue-len", NVME_DEFAULT_IO_QUEUE_LEN); 2896 nvme->n_async_event_limit = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2897 DDI_PROP_DONTPASS, "async-event-limit", 2898 NVME_DEFAULT_ASYNC_EVENT_LIMIT); 2899 nvme->n_write_cache_enabled = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2900 DDI_PROP_DONTPASS, "volatile-write-cache-enable", 1) != 0 ? 2901 B_TRUE : B_FALSE; 2902 nvme->n_min_block_size = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 2903 DDI_PROP_DONTPASS, "min-phys-block-size", 2904 NVME_DEFAULT_MIN_BLOCK_SIZE); 2905 2906 if (!ISP2(nvme->n_min_block_size) || 2907 (nvme->n_min_block_size < NVME_DEFAULT_MIN_BLOCK_SIZE)) { 2908 dev_err(dip, CE_WARN, "!min-phys-block-size %s, " 2909 "using default %d", ISP2(nvme->n_min_block_size) ? 2910 "too low" : "not a power of 2", 2911 NVME_DEFAULT_MIN_BLOCK_SIZE); 2912 nvme->n_min_block_size = NVME_DEFAULT_MIN_BLOCK_SIZE; 2913 } 2914 2915 if (nvme->n_admin_queue_len < NVME_MIN_ADMIN_QUEUE_LEN) 2916 nvme->n_admin_queue_len = NVME_MIN_ADMIN_QUEUE_LEN; 2917 else if (nvme->n_admin_queue_len > NVME_MAX_ADMIN_QUEUE_LEN) 2918 nvme->n_admin_queue_len = NVME_MAX_ADMIN_QUEUE_LEN; 2919 2920 if (nvme->n_io_queue_len < NVME_MIN_IO_QUEUE_LEN) 2921 nvme->n_io_queue_len = NVME_MIN_IO_QUEUE_LEN; 2922 2923 if (nvme->n_async_event_limit < 1) 2924 nvme->n_async_event_limit = NVME_DEFAULT_ASYNC_EVENT_LIMIT; 2925 2926 nvme->n_reg_acc_attr = nvme_reg_acc_attr; 2927 nvme->n_queue_dma_attr = nvme_queue_dma_attr; 2928 nvme->n_prp_dma_attr = nvme_prp_dma_attr; 2929 nvme->n_sgl_dma_attr = nvme_sgl_dma_attr; 2930 2931 /* 2932 * Setup FMA support. 2933 */ 2934 nvme->n_fm_cap = ddi_getprop(DDI_DEV_T_ANY, dip, 2935 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 2936 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 2937 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 2938 2939 ddi_fm_init(dip, &nvme->n_fm_cap, &nvme->n_fm_ibc); 2940 2941 if (nvme->n_fm_cap) { 2942 if (nvme->n_fm_cap & DDI_FM_ACCCHK_CAPABLE) 2943 nvme->n_reg_acc_attr.devacc_attr_access = 2944 DDI_FLAGERR_ACC; 2945 2946 if (nvme->n_fm_cap & DDI_FM_DMACHK_CAPABLE) { 2947 nvme->n_prp_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 2948 nvme->n_sgl_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 2949 } 2950 2951 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) || 2952 DDI_FM_ERRCB_CAP(nvme->n_fm_cap)) 2953 pci_ereport_setup(dip); 2954 2955 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap)) 2956 ddi_fm_handler_register(dip, nvme_fm_errcb, 2957 (void *)nvme); 2958 } 2959 2960 nvme->n_progress |= NVME_FMA_INIT; 2961 2962 /* 2963 * The spec defines several register sets. Only the controller 2964 * registers (set 1) are currently used. 2965 */ 2966 if (ddi_dev_nregs(dip, &nregs) == DDI_FAILURE || 2967 nregs < 2 || 2968 ddi_dev_regsize(dip, 1, ®size) == DDI_FAILURE) 2969 goto fail; 2970 2971 if (ddi_regs_map_setup(dip, 1, &nvme->n_regs, 0, regsize, 2972 &nvme->n_reg_acc_attr, &nvme->n_regh) != DDI_SUCCESS) { 2973 dev_err(dip, CE_WARN, "!failed to map regset 1"); 2974 goto fail; 2975 } 2976 2977 nvme->n_progress |= NVME_REGS_MAPPED; 2978 2979 /* 2980 * Create taskq for command completion. 2981 */ 2982 (void) snprintf(name, sizeof (name), "%s%d_cmd_taskq", 2983 ddi_driver_name(dip), ddi_get_instance(dip)); 2984 nvme->n_cmd_taskq = ddi_taskq_create(dip, name, MIN(UINT16_MAX, ncpus), 2985 TASKQ_DEFAULTPRI, 0); 2986 if (nvme->n_cmd_taskq == NULL) { 2987 dev_err(dip, CE_WARN, "!failed to create cmd taskq"); 2988 goto fail; 2989 } 2990 2991 /* 2992 * Create PRP DMA cache 2993 */ 2994 (void) snprintf(name, sizeof (name), "%s%d_prp_cache", 2995 ddi_driver_name(dip), ddi_get_instance(dip)); 2996 nvme->n_prp_cache = kmem_cache_create(name, sizeof (nvme_dma_t), 2997 0, nvme_prp_dma_constructor, nvme_prp_dma_destructor, 2998 NULL, (void *)nvme, NULL, 0); 2999 3000 if (nvme_init(nvme) != DDI_SUCCESS) 3001 goto fail; 3002 3003 /* 3004 * Attach the blkdev driver for each namespace. 3005 */ 3006 for (i = 0; i != nvme->n_namespace_count; i++) { 3007 if (ddi_create_minor_node(nvme->n_dip, nvme->n_ns[i].ns_name, 3008 S_IFCHR, NVME_MINOR(ddi_get_instance(nvme->n_dip), i + 1), 3009 DDI_NT_NVME_ATTACHMENT_POINT, 0) != DDI_SUCCESS) { 3010 dev_err(dip, CE_WARN, 3011 "!failed to create minor node for namespace %d", i); 3012 goto fail; 3013 } 3014 3015 if (nvme->n_ns[i].ns_ignore) 3016 continue; 3017 3018 nvme->n_ns[i].ns_bd_hdl = bd_alloc_handle(&nvme->n_ns[i], 3019 &nvme_bd_ops, &nvme->n_prp_dma_attr, KM_SLEEP); 3020 3021 if (nvme->n_ns[i].ns_bd_hdl == NULL) { 3022 dev_err(dip, CE_WARN, 3023 "!failed to get blkdev handle for namespace %d", i); 3024 goto fail; 3025 } 3026 3027 if (bd_attach_handle(dip, nvme->n_ns[i].ns_bd_hdl) 3028 != DDI_SUCCESS) { 3029 dev_err(dip, CE_WARN, 3030 "!failed to attach blkdev handle for namespace %d", 3031 i); 3032 goto fail; 3033 } 3034 } 3035 3036 if (ddi_create_minor_node(dip, "devctl", S_IFCHR, 3037 NVME_MINOR(ddi_get_instance(dip), 0), DDI_NT_NVME_NEXUS, 0) 3038 != DDI_SUCCESS) { 3039 dev_err(dip, CE_WARN, "nvme_attach: " 3040 "cannot create devctl minor node"); 3041 goto fail; 3042 } 3043 3044 return (DDI_SUCCESS); 3045 3046 fail: 3047 /* attach successful anyway so that FMA can retire the device */ 3048 if (nvme->n_dead) 3049 return (DDI_SUCCESS); 3050 3051 (void) nvme_detach(dip, DDI_DETACH); 3052 3053 return (DDI_FAILURE); 3054 } 3055 3056 static int 3057 nvme_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 3058 { 3059 int instance, i; 3060 nvme_t *nvme; 3061 3062 if (cmd != DDI_DETACH) 3063 return (DDI_FAILURE); 3064 3065 instance = ddi_get_instance(dip); 3066 3067 nvme = ddi_get_soft_state(nvme_state, instance); 3068 3069 if (nvme == NULL) 3070 return (DDI_FAILURE); 3071 3072 ddi_remove_minor_node(dip, "devctl"); 3073 mutex_destroy(&nvme->n_minor.nm_mutex); 3074 3075 if (nvme->n_ns) { 3076 for (i = 0; i != nvme->n_namespace_count; i++) { 3077 ddi_remove_minor_node(dip, nvme->n_ns[i].ns_name); 3078 mutex_destroy(&nvme->n_ns[i].ns_minor.nm_mutex); 3079 3080 if (nvme->n_ns[i].ns_bd_hdl) { 3081 (void) bd_detach_handle( 3082 nvme->n_ns[i].ns_bd_hdl); 3083 bd_free_handle(nvme->n_ns[i].ns_bd_hdl); 3084 } 3085 3086 if (nvme->n_ns[i].ns_idns) 3087 kmem_free(nvme->n_ns[i].ns_idns, 3088 sizeof (nvme_identify_nsid_t)); 3089 if (nvme->n_ns[i].ns_devid) 3090 strfree(nvme->n_ns[i].ns_devid); 3091 } 3092 3093 kmem_free(nvme->n_ns, sizeof (nvme_namespace_t) * 3094 nvme->n_namespace_count); 3095 } 3096 3097 if (nvme->n_progress & NVME_INTERRUPTS) 3098 nvme_release_interrupts(nvme); 3099 3100 if (nvme->n_cmd_taskq) 3101 ddi_taskq_wait(nvme->n_cmd_taskq); 3102 3103 if (nvme->n_ioq_count > 0) { 3104 for (i = 1; i != nvme->n_ioq_count + 1; i++) { 3105 if (nvme->n_ioq[i] != NULL) { 3106 /* TODO: send destroy queue commands */ 3107 nvme_free_qpair(nvme->n_ioq[i]); 3108 } 3109 } 3110 3111 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *) * 3112 (nvme->n_ioq_count + 1)); 3113 } 3114 3115 if (nvme->n_prp_cache != NULL) { 3116 kmem_cache_destroy(nvme->n_prp_cache); 3117 } 3118 3119 if (nvme->n_progress & NVME_REGS_MAPPED) { 3120 nvme_shutdown(nvme, NVME_CC_SHN_NORMAL, B_FALSE); 3121 (void) nvme_reset(nvme, B_FALSE); 3122 } 3123 3124 if (nvme->n_cmd_taskq) 3125 ddi_taskq_destroy(nvme->n_cmd_taskq); 3126 3127 if (nvme->n_progress & NVME_CTRL_LIMITS) 3128 sema_destroy(&nvme->n_abort_sema); 3129 3130 if (nvme->n_progress & NVME_ADMIN_QUEUE) 3131 nvme_free_qpair(nvme->n_adminq); 3132 3133 if (nvme->n_idctl) 3134 kmem_free(nvme->n_idctl, NVME_IDENTIFY_BUFSIZE); 3135 3136 if (nvme->n_progress & NVME_REGS_MAPPED) 3137 ddi_regs_map_free(&nvme->n_regh); 3138 3139 if (nvme->n_progress & NVME_FMA_INIT) { 3140 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap)) 3141 ddi_fm_handler_unregister(nvme->n_dip); 3142 3143 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) || 3144 DDI_FM_ERRCB_CAP(nvme->n_fm_cap)) 3145 pci_ereport_teardown(nvme->n_dip); 3146 3147 ddi_fm_fini(nvme->n_dip); 3148 } 3149 3150 if (nvme->n_vendor != NULL) 3151 strfree(nvme->n_vendor); 3152 3153 if (nvme->n_product != NULL) 3154 strfree(nvme->n_product); 3155 3156 ddi_soft_state_free(nvme_state, instance); 3157 3158 return (DDI_SUCCESS); 3159 } 3160 3161 static int 3162 nvme_quiesce(dev_info_t *dip) 3163 { 3164 int instance; 3165 nvme_t *nvme; 3166 3167 instance = ddi_get_instance(dip); 3168 3169 nvme = ddi_get_soft_state(nvme_state, instance); 3170 3171 if (nvme == NULL) 3172 return (DDI_FAILURE); 3173 3174 nvme_shutdown(nvme, NVME_CC_SHN_ABRUPT, B_TRUE); 3175 3176 (void) nvme_reset(nvme, B_TRUE); 3177 3178 return (DDI_FAILURE); 3179 } 3180 3181 static int 3182 nvme_fill_prp(nvme_cmd_t *cmd, bd_xfer_t *xfer) 3183 { 3184 nvme_t *nvme = cmd->nc_nvme; 3185 int nprp_page, nprp; 3186 uint64_t *prp; 3187 3188 if (xfer->x_ndmac == 0) 3189 return (DDI_FAILURE); 3190 3191 cmd->nc_sqe.sqe_dptr.d_prp[0] = xfer->x_dmac.dmac_laddress; 3192 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac); 3193 3194 if (xfer->x_ndmac == 1) { 3195 cmd->nc_sqe.sqe_dptr.d_prp[1] = 0; 3196 return (DDI_SUCCESS); 3197 } else if (xfer->x_ndmac == 2) { 3198 cmd->nc_sqe.sqe_dptr.d_prp[1] = xfer->x_dmac.dmac_laddress; 3199 return (DDI_SUCCESS); 3200 } 3201 3202 xfer->x_ndmac--; 3203 3204 nprp_page = nvme->n_pagesize / sizeof (uint64_t) - 1; 3205 ASSERT(nprp_page > 0); 3206 nprp = (xfer->x_ndmac + nprp_page - 1) / nprp_page; 3207 3208 /* 3209 * We currently don't support chained PRPs and set up our DMA 3210 * attributes to reflect that. If we still get an I/O request 3211 * that needs a chained PRP something is very wrong. 3212 */ 3213 VERIFY(nprp == 1); 3214 3215 cmd->nc_dma = kmem_cache_alloc(nvme->n_prp_cache, KM_SLEEP); 3216 bzero(cmd->nc_dma->nd_memp, cmd->nc_dma->nd_len); 3217 3218 cmd->nc_sqe.sqe_dptr.d_prp[1] = cmd->nc_dma->nd_cookie.dmac_laddress; 3219 3220 /*LINTED: E_PTR_BAD_CAST_ALIGN*/ 3221 for (prp = (uint64_t *)cmd->nc_dma->nd_memp; 3222 xfer->x_ndmac > 0; 3223 prp++, xfer->x_ndmac--) { 3224 *prp = xfer->x_dmac.dmac_laddress; 3225 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac); 3226 } 3227 3228 (void) ddi_dma_sync(cmd->nc_dma->nd_dmah, 0, cmd->nc_dma->nd_len, 3229 DDI_DMA_SYNC_FORDEV); 3230 return (DDI_SUCCESS); 3231 } 3232 3233 static nvme_cmd_t * 3234 nvme_create_nvm_cmd(nvme_namespace_t *ns, uint8_t opc, bd_xfer_t *xfer) 3235 { 3236 nvme_t *nvme = ns->ns_nvme; 3237 nvme_cmd_t *cmd; 3238 3239 /* 3240 * Blkdev only sets BD_XFER_POLL when dumping, so don't sleep. 3241 */ 3242 cmd = nvme_alloc_cmd(nvme, (xfer->x_flags & BD_XFER_POLL) ? 3243 KM_NOSLEEP : KM_SLEEP); 3244 3245 if (cmd == NULL) 3246 return (NULL); 3247 3248 cmd->nc_sqe.sqe_opc = opc; 3249 cmd->nc_callback = nvme_bd_xfer_done; 3250 cmd->nc_xfer = xfer; 3251 3252 switch (opc) { 3253 case NVME_OPC_NVM_WRITE: 3254 case NVME_OPC_NVM_READ: 3255 VERIFY(xfer->x_nblks <= 0x10000); 3256 3257 cmd->nc_sqe.sqe_nsid = ns->ns_id; 3258 3259 cmd->nc_sqe.sqe_cdw10 = xfer->x_blkno & 0xffffffffu; 3260 cmd->nc_sqe.sqe_cdw11 = (xfer->x_blkno >> 32); 3261 cmd->nc_sqe.sqe_cdw12 = (uint16_t)(xfer->x_nblks - 1); 3262 3263 if (nvme_fill_prp(cmd, xfer) != DDI_SUCCESS) 3264 goto fail; 3265 break; 3266 3267 case NVME_OPC_NVM_FLUSH: 3268 cmd->nc_sqe.sqe_nsid = ns->ns_id; 3269 break; 3270 3271 default: 3272 goto fail; 3273 } 3274 3275 return (cmd); 3276 3277 fail: 3278 nvme_free_cmd(cmd); 3279 return (NULL); 3280 } 3281 3282 static void 3283 nvme_bd_xfer_done(void *arg) 3284 { 3285 nvme_cmd_t *cmd = arg; 3286 bd_xfer_t *xfer = cmd->nc_xfer; 3287 int error = 0; 3288 3289 error = nvme_check_cmd_status(cmd); 3290 nvme_free_cmd(cmd); 3291 3292 bd_xfer_done(xfer, error); 3293 } 3294 3295 static void 3296 nvme_bd_driveinfo(void *arg, bd_drive_t *drive) 3297 { 3298 nvme_namespace_t *ns = arg; 3299 nvme_t *nvme = ns->ns_nvme; 3300 3301 /* 3302 * blkdev maintains one queue size per instance (namespace), 3303 * but all namespace share the I/O queues. 3304 * TODO: need to figure out a sane default, or use per-NS I/O queues, 3305 * or change blkdev to handle EAGAIN 3306 */ 3307 drive->d_qsize = nvme->n_ioq_count * nvme->n_io_queue_len 3308 / nvme->n_namespace_count; 3309 3310 /* 3311 * d_maxxfer is not set, which means the value is taken from the DMA 3312 * attributes specified to bd_alloc_handle. 3313 */ 3314 3315 drive->d_removable = B_FALSE; 3316 drive->d_hotpluggable = B_FALSE; 3317 3318 bcopy(ns->ns_eui64, drive->d_eui64, sizeof (drive->d_eui64)); 3319 drive->d_target = ns->ns_id; 3320 drive->d_lun = 0; 3321 3322 drive->d_model = nvme->n_idctl->id_model; 3323 drive->d_model_len = sizeof (nvme->n_idctl->id_model); 3324 drive->d_vendor = nvme->n_vendor; 3325 drive->d_vendor_len = strlen(nvme->n_vendor); 3326 drive->d_product = nvme->n_product; 3327 drive->d_product_len = strlen(nvme->n_product); 3328 drive->d_serial = nvme->n_idctl->id_serial; 3329 drive->d_serial_len = sizeof (nvme->n_idctl->id_serial); 3330 drive->d_revision = nvme->n_idctl->id_fwrev; 3331 drive->d_revision_len = sizeof (nvme->n_idctl->id_fwrev); 3332 } 3333 3334 static int 3335 nvme_bd_mediainfo(void *arg, bd_media_t *media) 3336 { 3337 nvme_namespace_t *ns = arg; 3338 3339 media->m_nblks = ns->ns_block_count; 3340 media->m_blksize = ns->ns_block_size; 3341 media->m_readonly = B_FALSE; 3342 media->m_solidstate = B_TRUE; 3343 3344 media->m_pblksize = ns->ns_best_block_size; 3345 3346 return (0); 3347 } 3348 3349 static int 3350 nvme_bd_cmd(nvme_namespace_t *ns, bd_xfer_t *xfer, uint8_t opc) 3351 { 3352 nvme_t *nvme = ns->ns_nvme; 3353 nvme_cmd_t *cmd; 3354 nvme_qpair_t *ioq; 3355 boolean_t poll; 3356 int ret; 3357 3358 if (nvme->n_dead) 3359 return (EIO); 3360 3361 cmd = nvme_create_nvm_cmd(ns, opc, xfer); 3362 if (cmd == NULL) 3363 return (ENOMEM); 3364 3365 cmd->nc_sqid = (CPU->cpu_id % nvme->n_ioq_count) + 1; 3366 ASSERT(cmd->nc_sqid <= nvme->n_ioq_count); 3367 ioq = nvme->n_ioq[cmd->nc_sqid]; 3368 3369 /* 3370 * Get the polling flag before submitting the command. The command may 3371 * complete immediately after it was submitted, which means we must 3372 * treat both cmd and xfer as if they have been freed already. 3373 */ 3374 poll = (xfer->x_flags & BD_XFER_POLL) != 0; 3375 3376 ret = nvme_submit_io_cmd(ioq, cmd); 3377 3378 if (ret != 0) 3379 return (ret); 3380 3381 if (!poll) 3382 return (0); 3383 3384 do { 3385 cmd = nvme_retrieve_cmd(nvme, ioq); 3386 if (cmd != NULL) 3387 nvme_bd_xfer_done(cmd); 3388 else 3389 drv_usecwait(10); 3390 } while (ioq->nq_active_cmds != 0); 3391 3392 return (0); 3393 } 3394 3395 static int 3396 nvme_bd_read(void *arg, bd_xfer_t *xfer) 3397 { 3398 nvme_namespace_t *ns = arg; 3399 3400 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_READ)); 3401 } 3402 3403 static int 3404 nvme_bd_write(void *arg, bd_xfer_t *xfer) 3405 { 3406 nvme_namespace_t *ns = arg; 3407 3408 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_WRITE)); 3409 } 3410 3411 static int 3412 nvme_bd_sync(void *arg, bd_xfer_t *xfer) 3413 { 3414 nvme_namespace_t *ns = arg; 3415 3416 if (ns->ns_nvme->n_dead) 3417 return (EIO); 3418 3419 /* 3420 * If the volatile write cache is not present or not enabled the FLUSH 3421 * command is a no-op, so we can take a shortcut here. 3422 */ 3423 if (!ns->ns_nvme->n_write_cache_present) { 3424 bd_xfer_done(xfer, ENOTSUP); 3425 return (0); 3426 } 3427 3428 if (!ns->ns_nvme->n_write_cache_enabled) { 3429 bd_xfer_done(xfer, 0); 3430 return (0); 3431 } 3432 3433 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_FLUSH)); 3434 } 3435 3436 static int 3437 nvme_bd_devid(void *arg, dev_info_t *devinfo, ddi_devid_t *devid) 3438 { 3439 nvme_namespace_t *ns = arg; 3440 3441 /*LINTED: E_BAD_PTR_CAST_ALIGN*/ 3442 if (*(uint64_t *)ns->ns_eui64 != 0) { 3443 return (ddi_devid_init(devinfo, DEVID_SCSI3_WWN, 3444 sizeof (ns->ns_eui64), ns->ns_eui64, devid)); 3445 } else { 3446 return (ddi_devid_init(devinfo, DEVID_ENCAP, 3447 strlen(ns->ns_devid), ns->ns_devid, devid)); 3448 } 3449 } 3450 3451 static int 3452 nvme_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 3453 { 3454 #ifndef __lock_lint 3455 _NOTE(ARGUNUSED(cred_p)); 3456 #endif 3457 minor_t minor = getminor(*devp); 3458 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor)); 3459 int nsid = NVME_MINOR_NSID(minor); 3460 nvme_minor_state_t *nm; 3461 int rv = 0; 3462 3463 if (otyp != OTYP_CHR) 3464 return (EINVAL); 3465 3466 if (nvme == NULL) 3467 return (ENXIO); 3468 3469 if (nsid > nvme->n_namespace_count) 3470 return (ENXIO); 3471 3472 if (nvme->n_dead) 3473 return (EIO); 3474 3475 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor; 3476 3477 mutex_enter(&nm->nm_mutex); 3478 if (nm->nm_oexcl) { 3479 rv = EBUSY; 3480 goto out; 3481 } 3482 3483 if (flag & FEXCL) { 3484 if (nm->nm_ocnt != 0) { 3485 rv = EBUSY; 3486 goto out; 3487 } 3488 nm->nm_oexcl = B_TRUE; 3489 } 3490 3491 nm->nm_ocnt++; 3492 3493 out: 3494 mutex_exit(&nm->nm_mutex); 3495 return (rv); 3496 3497 } 3498 3499 static int 3500 nvme_close(dev_t dev, int flag, int otyp, cred_t *cred_p) 3501 { 3502 #ifndef __lock_lint 3503 _NOTE(ARGUNUSED(cred_p)); 3504 _NOTE(ARGUNUSED(flag)); 3505 #endif 3506 minor_t minor = getminor(dev); 3507 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor)); 3508 int nsid = NVME_MINOR_NSID(minor); 3509 nvme_minor_state_t *nm; 3510 3511 if (otyp != OTYP_CHR) 3512 return (ENXIO); 3513 3514 if (nvme == NULL) 3515 return (ENXIO); 3516 3517 if (nsid > nvme->n_namespace_count) 3518 return (ENXIO); 3519 3520 nm = nsid == 0 ? &nvme->n_minor : &nvme->n_ns[nsid - 1].ns_minor; 3521 3522 mutex_enter(&nm->nm_mutex); 3523 if (nm->nm_oexcl) 3524 nm->nm_oexcl = B_FALSE; 3525 3526 ASSERT(nm->nm_ocnt > 0); 3527 nm->nm_ocnt--; 3528 mutex_exit(&nm->nm_mutex); 3529 3530 return (0); 3531 } 3532 3533 static int 3534 nvme_ioctl_identify(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3535 cred_t *cred_p) 3536 { 3537 _NOTE(ARGUNUSED(cred_p)); 3538 int rv = 0; 3539 void *idctl; 3540 3541 if ((mode & FREAD) == 0) 3542 return (EPERM); 3543 3544 if (nioc->n_len < NVME_IDENTIFY_BUFSIZE) 3545 return (EINVAL); 3546 3547 if ((rv = nvme_identify(nvme, nsid, (void **)&idctl)) != 0) 3548 return (rv); 3549 3550 if (ddi_copyout(idctl, (void *)nioc->n_buf, NVME_IDENTIFY_BUFSIZE, mode) 3551 != 0) 3552 rv = EFAULT; 3553 3554 kmem_free(idctl, NVME_IDENTIFY_BUFSIZE); 3555 3556 return (rv); 3557 } 3558 3559 static int 3560 nvme_ioctl_capabilities(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, 3561 int mode, cred_t *cred_p) 3562 { 3563 _NOTE(ARGUNUSED(nsid, cred_p)); 3564 int rv = 0; 3565 nvme_reg_cap_t cap = { 0 }; 3566 nvme_capabilities_t nc; 3567 3568 if ((mode & FREAD) == 0) 3569 return (EPERM); 3570 3571 if (nioc->n_len < sizeof (nc)) 3572 return (EINVAL); 3573 3574 cap.r = nvme_get64(nvme, NVME_REG_CAP); 3575 3576 /* 3577 * The MPSMIN and MPSMAX fields in the CAP register use 0 to 3578 * specify the base page size of 4k (1<<12), so add 12 here to 3579 * get the real page size value. 3580 */ 3581 nc.mpsmax = 1 << (12 + cap.b.cap_mpsmax); 3582 nc.mpsmin = 1 << (12 + cap.b.cap_mpsmin); 3583 3584 if (ddi_copyout(&nc, (void *)nioc->n_buf, sizeof (nc), mode) != 0) 3585 rv = EFAULT; 3586 3587 return (rv); 3588 } 3589 3590 static int 3591 nvme_ioctl_get_logpage(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, 3592 int mode, cred_t *cred_p) 3593 { 3594 _NOTE(ARGUNUSED(cred_p)); 3595 void *log = NULL; 3596 size_t bufsize = 0; 3597 int rv = 0; 3598 3599 if ((mode & FREAD) == 0) 3600 return (EPERM); 3601 3602 switch (nioc->n_arg) { 3603 case NVME_LOGPAGE_ERROR: 3604 if (nsid != 0) 3605 return (EINVAL); 3606 break; 3607 case NVME_LOGPAGE_HEALTH: 3608 if (nsid != 0 && nvme->n_idctl->id_lpa.lp_smart == 0) 3609 return (EINVAL); 3610 3611 if (nsid == 0) 3612 nsid = (uint32_t)-1; 3613 3614 break; 3615 case NVME_LOGPAGE_FWSLOT: 3616 if (nsid != 0) 3617 return (EINVAL); 3618 break; 3619 default: 3620 return (EINVAL); 3621 } 3622 3623 if (nvme_get_logpage(nvme, &log, &bufsize, nioc->n_arg, nsid) 3624 != DDI_SUCCESS) 3625 return (EIO); 3626 3627 if (nioc->n_len < bufsize) { 3628 kmem_free(log, bufsize); 3629 return (EINVAL); 3630 } 3631 3632 if (ddi_copyout(log, (void *)nioc->n_buf, bufsize, mode) != 0) 3633 rv = EFAULT; 3634 3635 nioc->n_len = bufsize; 3636 kmem_free(log, bufsize); 3637 3638 return (rv); 3639 } 3640 3641 static int 3642 nvme_ioctl_get_features(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, 3643 int mode, cred_t *cred_p) 3644 { 3645 _NOTE(ARGUNUSED(cred_p)); 3646 void *buf = NULL; 3647 size_t bufsize = 0; 3648 uint32_t res = 0; 3649 uint8_t feature; 3650 int rv = 0; 3651 3652 if ((mode & FREAD) == 0) 3653 return (EPERM); 3654 3655 if ((nioc->n_arg >> 32) > 0xff) 3656 return (EINVAL); 3657 3658 feature = (uint8_t)(nioc->n_arg >> 32); 3659 3660 switch (feature) { 3661 case NVME_FEAT_ARBITRATION: 3662 case NVME_FEAT_POWER_MGMT: 3663 case NVME_FEAT_TEMPERATURE: 3664 case NVME_FEAT_ERROR: 3665 case NVME_FEAT_NQUEUES: 3666 case NVME_FEAT_INTR_COAL: 3667 case NVME_FEAT_WRITE_ATOM: 3668 case NVME_FEAT_ASYNC_EVENT: 3669 case NVME_FEAT_PROGRESS: 3670 if (nsid != 0) 3671 return (EINVAL); 3672 break; 3673 3674 case NVME_FEAT_INTR_VECT: 3675 if (nsid != 0) 3676 return (EINVAL); 3677 3678 res = nioc->n_arg & 0xffffffffUL; 3679 if (res >= nvme->n_intr_cnt) 3680 return (EINVAL); 3681 break; 3682 3683 case NVME_FEAT_LBA_RANGE: 3684 if (nvme->n_lba_range_supported == B_FALSE) 3685 return (EINVAL); 3686 3687 if (nsid == 0 || 3688 nsid > nvme->n_namespace_count) 3689 return (EINVAL); 3690 3691 break; 3692 3693 case NVME_FEAT_WRITE_CACHE: 3694 if (nsid != 0) 3695 return (EINVAL); 3696 3697 if (!nvme->n_write_cache_present) 3698 return (EINVAL); 3699 3700 break; 3701 3702 case NVME_FEAT_AUTO_PST: 3703 if (nsid != 0) 3704 return (EINVAL); 3705 3706 if (!nvme->n_auto_pst_supported) 3707 return (EINVAL); 3708 3709 break; 3710 3711 default: 3712 return (EINVAL); 3713 } 3714 3715 rv = nvme_get_features(nvme, nsid, feature, &res, &buf, &bufsize); 3716 if (rv != 0) 3717 return (rv); 3718 3719 if (nioc->n_len < bufsize) { 3720 kmem_free(buf, bufsize); 3721 return (EINVAL); 3722 } 3723 3724 if (buf && ddi_copyout(buf, (void*)nioc->n_buf, bufsize, mode) != 0) 3725 rv = EFAULT; 3726 3727 kmem_free(buf, bufsize); 3728 nioc->n_arg = res; 3729 nioc->n_len = bufsize; 3730 3731 return (rv); 3732 } 3733 3734 static int 3735 nvme_ioctl_intr_cnt(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3736 cred_t *cred_p) 3737 { 3738 _NOTE(ARGUNUSED(nsid, mode, cred_p)); 3739 3740 if ((mode & FREAD) == 0) 3741 return (EPERM); 3742 3743 nioc->n_arg = nvme->n_intr_cnt; 3744 return (0); 3745 } 3746 3747 static int 3748 nvme_ioctl_version(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3749 cred_t *cred_p) 3750 { 3751 _NOTE(ARGUNUSED(nsid, cred_p)); 3752 int rv = 0; 3753 3754 if ((mode & FREAD) == 0) 3755 return (EPERM); 3756 3757 if (nioc->n_len < sizeof (nvme->n_version)) 3758 return (ENOMEM); 3759 3760 if (ddi_copyout(&nvme->n_version, (void *)nioc->n_buf, 3761 sizeof (nvme->n_version), mode) != 0) 3762 rv = EFAULT; 3763 3764 return (rv); 3765 } 3766 3767 static int 3768 nvme_ioctl_format(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3769 cred_t *cred_p) 3770 { 3771 _NOTE(ARGUNUSED(mode)); 3772 nvme_format_nvm_t frmt = { 0 }; 3773 int c_nsid = nsid != 0 ? nsid - 1 : 0; 3774 3775 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0) 3776 return (EPERM); 3777 3778 frmt.r = nioc->n_arg & 0xffffffff; 3779 3780 /* 3781 * Check whether the FORMAT NVM command is supported. 3782 */ 3783 if (nvme->n_idctl->id_oacs.oa_format == 0) 3784 return (EINVAL); 3785 3786 /* 3787 * Don't allow format or secure erase of individual namespace if that 3788 * would cause a format or secure erase of all namespaces. 3789 */ 3790 if (nsid != 0 && nvme->n_idctl->id_fna.fn_format != 0) 3791 return (EINVAL); 3792 3793 if (nsid != 0 && frmt.b.fm_ses != NVME_FRMT_SES_NONE && 3794 nvme->n_idctl->id_fna.fn_sec_erase != 0) 3795 return (EINVAL); 3796 3797 /* 3798 * Don't allow formatting with Protection Information. 3799 */ 3800 if (frmt.b.fm_pi != 0 || frmt.b.fm_pil != 0 || frmt.b.fm_ms != 0) 3801 return (EINVAL); 3802 3803 /* 3804 * Don't allow formatting using an illegal LBA format, or any LBA format 3805 * that uses metadata. 3806 */ 3807 if (frmt.b.fm_lbaf > nvme->n_ns[c_nsid].ns_idns->id_nlbaf || 3808 nvme->n_ns[c_nsid].ns_idns->id_lbaf[frmt.b.fm_lbaf].lbaf_ms != 0) 3809 return (EINVAL); 3810 3811 /* 3812 * Don't allow formatting using an illegal Secure Erase setting. 3813 */ 3814 if (frmt.b.fm_ses > NVME_FRMT_MAX_SES || 3815 (frmt.b.fm_ses == NVME_FRMT_SES_CRYPTO && 3816 nvme->n_idctl->id_fna.fn_crypt_erase == 0)) 3817 return (EINVAL); 3818 3819 if (nsid == 0) 3820 nsid = (uint32_t)-1; 3821 3822 return (nvme_format_nvm(nvme, nsid, frmt.b.fm_lbaf, B_FALSE, 0, B_FALSE, 3823 frmt.b.fm_ses)); 3824 } 3825 3826 static int 3827 nvme_ioctl_detach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3828 cred_t *cred_p) 3829 { 3830 _NOTE(ARGUNUSED(nioc, mode)); 3831 int rv = 0; 3832 3833 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0) 3834 return (EPERM); 3835 3836 if (nsid == 0) 3837 return (EINVAL); 3838 3839 rv = bd_detach_handle(nvme->n_ns[nsid - 1].ns_bd_hdl); 3840 if (rv != DDI_SUCCESS) 3841 rv = EBUSY; 3842 3843 return (rv); 3844 } 3845 3846 static int 3847 nvme_ioctl_attach(nvme_t *nvme, int nsid, nvme_ioctl_t *nioc, int mode, 3848 cred_t *cred_p) 3849 { 3850 _NOTE(ARGUNUSED(nioc, mode)); 3851 nvme_identify_nsid_t *idns; 3852 int rv = 0; 3853 3854 if ((mode & FWRITE) == 0 || secpolicy_sys_config(cred_p, B_FALSE) != 0) 3855 return (EPERM); 3856 3857 if (nsid == 0) 3858 return (EINVAL); 3859 3860 /* 3861 * Identify namespace again, free old identify data. 3862 */ 3863 idns = nvme->n_ns[nsid - 1].ns_idns; 3864 if (nvme_init_ns(nvme, nsid) != DDI_SUCCESS) 3865 return (EIO); 3866 3867 kmem_free(idns, sizeof (nvme_identify_nsid_t)); 3868 3869 rv = bd_attach_handle(nvme->n_dip, nvme->n_ns[nsid - 1].ns_bd_hdl); 3870 if (rv != DDI_SUCCESS) 3871 rv = EBUSY; 3872 3873 return (rv); 3874 } 3875 3876 static int 3877 nvme_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred_p, 3878 int *rval_p) 3879 { 3880 #ifndef __lock_lint 3881 _NOTE(ARGUNUSED(rval_p)); 3882 #endif 3883 minor_t minor = getminor(dev); 3884 nvme_t *nvme = ddi_get_soft_state(nvme_state, NVME_MINOR_INST(minor)); 3885 int nsid = NVME_MINOR_NSID(minor); 3886 int rv = 0; 3887 nvme_ioctl_t nioc; 3888 3889 int (*nvme_ioctl[])(nvme_t *, int, nvme_ioctl_t *, int, cred_t *) = { 3890 NULL, 3891 nvme_ioctl_identify, 3892 nvme_ioctl_identify, 3893 nvme_ioctl_capabilities, 3894 nvme_ioctl_get_logpage, 3895 nvme_ioctl_get_features, 3896 nvme_ioctl_intr_cnt, 3897 nvme_ioctl_version, 3898 nvme_ioctl_format, 3899 nvme_ioctl_detach, 3900 nvme_ioctl_attach 3901 }; 3902 3903 if (nvme == NULL) 3904 return (ENXIO); 3905 3906 if (nsid > nvme->n_namespace_count) 3907 return (ENXIO); 3908 3909 if (IS_DEVCTL(cmd)) 3910 return (ndi_devctl_ioctl(nvme->n_dip, cmd, arg, mode, 0)); 3911 3912 #ifdef _MULTI_DATAMODEL 3913 switch (ddi_model_convert_from(mode & FMODELS)) { 3914 case DDI_MODEL_ILP32: { 3915 nvme_ioctl32_t nioc32; 3916 if (ddi_copyin((void*)arg, &nioc32, sizeof (nvme_ioctl32_t), 3917 mode) != 0) 3918 return (EFAULT); 3919 nioc.n_len = nioc32.n_len; 3920 nioc.n_buf = nioc32.n_buf; 3921 nioc.n_arg = nioc32.n_arg; 3922 break; 3923 } 3924 case DDI_MODEL_NONE: 3925 #endif 3926 if (ddi_copyin((void*)arg, &nioc, sizeof (nvme_ioctl_t), mode) 3927 != 0) 3928 return (EFAULT); 3929 #ifdef _MULTI_DATAMODEL 3930 break; 3931 } 3932 #endif 3933 3934 if (nvme->n_dead && cmd != NVME_IOC_DETACH) 3935 return (EIO); 3936 3937 3938 if (cmd == NVME_IOC_IDENTIFY_CTRL) { 3939 /* 3940 * This makes NVME_IOC_IDENTIFY_CTRL work the same on devctl and 3941 * attachment point nodes. 3942 */ 3943 nsid = 0; 3944 } else if (cmd == NVME_IOC_IDENTIFY_NSID && nsid == 0) { 3945 /* 3946 * This makes NVME_IOC_IDENTIFY_NSID work on a devctl node, it 3947 * will always return identify data for namespace 1. 3948 */ 3949 nsid = 1; 3950 } 3951 3952 if (IS_NVME_IOC(cmd) && nvme_ioctl[NVME_IOC_CMD(cmd)] != NULL) 3953 rv = nvme_ioctl[NVME_IOC_CMD(cmd)](nvme, nsid, &nioc, mode, 3954 cred_p); 3955 else 3956 rv = EINVAL; 3957 3958 #ifdef _MULTI_DATAMODEL 3959 switch (ddi_model_convert_from(mode & FMODELS)) { 3960 case DDI_MODEL_ILP32: { 3961 nvme_ioctl32_t nioc32; 3962 3963 nioc32.n_len = (size32_t)nioc.n_len; 3964 nioc32.n_buf = (uintptr32_t)nioc.n_buf; 3965 nioc32.n_arg = nioc.n_arg; 3966 3967 if (ddi_copyout(&nioc32, (void *)arg, sizeof (nvme_ioctl32_t), 3968 mode) != 0) 3969 return (EFAULT); 3970 break; 3971 } 3972 case DDI_MODEL_NONE: 3973 #endif 3974 if (ddi_copyout(&nioc, (void *)arg, sizeof (nvme_ioctl_t), mode) 3975 != 0) 3976 return (EFAULT); 3977 #ifdef _MULTI_DATAMODEL 3978 break; 3979 } 3980 #endif 3981 3982 return (rv); 3983 } 3984