1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 NetXen, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #include <sys/types.h> 26 #include <sys/conf.h> 27 #include <sys/debug.h> 28 #include <sys/stropts.h> 29 #include <sys/stream.h> 30 #include <sys/strlog.h> 31 #include <sys/kmem.h> 32 #include <sys/stat.h> 33 #include <sys/kstat.h> 34 #include <sys/vtrace.h> 35 #include <sys/dlpi.h> 36 #include <sys/strsun.h> 37 #include <sys/ethernet.h> 38 #include <sys/modctl.h> 39 #include <sys/errno.h> 40 #include <sys/dditypes.h> 41 #include <sys/ddi.h> 42 #include <sys/sunddi.h> 43 #include <sys/sysmacros.h> 44 #include <sys/pci.h> 45 46 #include "unm_nic.h" 47 #include "unm_nic_hw.h" 48 #include "nic_cmn.h" 49 #include "unm_nic_ioctl.h" 50 #include "nic_phan_reg.h" 51 52 struct crb_addr_pair { 53 long addr, data; 54 }; 55 56 #define MAX_CRB_XFORM 60 57 #define ADDR_ERROR ((unsigned long)0xffffffff) 58 59 #define crb_addr_transform(name) \ 60 crb_addr_xform[UNM_HW_PX_MAP_CRB_##name] = \ 61 UNM_HW_CRB_HUB_AGT_ADR_##name << 20 62 63 static unsigned int crb_addr_xform[MAX_CRB_XFORM]; 64 65 static void 66 crb_addr_transform_setup(void) 67 { 68 crb_addr_transform(XDMA); 69 crb_addr_transform(TIMR); 70 crb_addr_transform(SRE); 71 crb_addr_transform(SQN3); 72 crb_addr_transform(SQN2); 73 crb_addr_transform(SQN1); 74 crb_addr_transform(SQN0); 75 crb_addr_transform(SQS3); 76 crb_addr_transform(SQS2); 77 crb_addr_transform(SQS1); 78 crb_addr_transform(SQS0); 79 crb_addr_transform(RPMX7); 80 crb_addr_transform(RPMX6); 81 crb_addr_transform(RPMX5); 82 crb_addr_transform(RPMX4); 83 crb_addr_transform(RPMX3); 84 crb_addr_transform(RPMX2); 85 crb_addr_transform(RPMX1); 86 crb_addr_transform(RPMX0); 87 crb_addr_transform(ROMUSB); 88 crb_addr_transform(SN); 89 crb_addr_transform(QMN); 90 crb_addr_transform(QMS); 91 crb_addr_transform(PGNI); 92 crb_addr_transform(PGND); 93 crb_addr_transform(PGN3); 94 crb_addr_transform(PGN2); 95 crb_addr_transform(PGN1); 96 crb_addr_transform(PGN0); 97 crb_addr_transform(PGSI); 98 crb_addr_transform(PGSD); 99 crb_addr_transform(PGS3); 100 crb_addr_transform(PGS2); 101 crb_addr_transform(PGS1); 102 crb_addr_transform(PGS0); 103 crb_addr_transform(PS); 104 crb_addr_transform(PH); 105 crb_addr_transform(NIU); 106 crb_addr_transform(I2Q); 107 crb_addr_transform(EG); 108 crb_addr_transform(MN); 109 crb_addr_transform(MS); 110 crb_addr_transform(CAS2); 111 crb_addr_transform(CAS1); 112 crb_addr_transform(CAS0); 113 crb_addr_transform(CAM); 114 crb_addr_transform(C2C1); 115 crb_addr_transform(C2C0); 116 crb_addr_transform(SMB); 117 crb_addr_transform(OCM0); 118 119 /* 120 * Used only in P3 just define it for P2 also. 121 */ 122 crb_addr_transform(I2C0); 123 } 124 125 /* 126 * decode_crb_addr(0 - utility to translate from internal Phantom CRB address 127 * to external PCI CRB address. 128 */ 129 static unsigned long 130 decode_crb_addr(unsigned long addr) 131 { 132 int i; 133 unsigned long base_addr, offset, pci_base; 134 135 crb_addr_transform_setup(); 136 137 pci_base = ADDR_ERROR; 138 base_addr = addr & 0xfff00000; 139 offset = addr & 0x000fffff; 140 141 for (i = 0; i < MAX_CRB_XFORM; i++) { 142 if (crb_addr_xform[i] == base_addr) { 143 pci_base = i << 20; 144 break; 145 } 146 } 147 148 if (pci_base == ADDR_ERROR) { 149 return (pci_base); 150 } else { 151 return (pci_base + offset); 152 } 153 } 154 155 static long rom_max_timeout = 100; 156 static long rom_lock_timeout = 10000; 157 158 static int 159 rom_lock(unm_adapter *adapter) 160 { 161 uint32_t done = 0; 162 long timeout = 0; 163 164 while (!done) { 165 /* acquire semaphore2 from PCI HW block */ 166 unm_nic_read_w0(adapter, UNM_PCIE_REG(PCIE_SEM2_LOCK), &done); 167 if (done == 1) 168 break; 169 if (timeout >= rom_lock_timeout) { 170 cmn_err(CE_WARN, "%s%d rom_lock timed out %d %ld\n", 171 adapter->name, adapter->instance, done, timeout); 172 return (-1); 173 } 174 timeout++; 175 } 176 unm_nic_reg_write(adapter, UNM_ROM_LOCK_ID, ROM_LOCK_DRIVER); 177 return (0); 178 } 179 180 static void 181 rom_unlock(unm_adapter *adapter) 182 { 183 uint32_t val; 184 185 /* release semaphore2 */ 186 unm_nic_read_w0(adapter, UNM_PCIE_REG(PCIE_SEM2_UNLOCK), &val); 187 } 188 189 static int 190 wait_rom_done(unm_adapter *adapter) 191 { 192 long timeout = 0; 193 long done = 0; 194 195 while (done == 0) { 196 unm_nic_reg_read(adapter, UNM_ROMUSB_GLB_STATUS, &done); 197 done &= 2; 198 timeout++; 199 if (timeout >= rom_max_timeout) { 200 cmn_err(CE_WARN, 201 "Timeout reached waiting for rom done"); 202 return (-1); 203 } 204 } 205 return (0); 206 } 207 208 static int 209 do_rom_fast_read(unm_adapter *adapter, int addr, int *valp) 210 { 211 unm_nic_reg_write(adapter, UNM_ROMUSB_ROM_ADDRESS, addr); 212 unm_nic_reg_write(adapter, UNM_ROMUSB_ROM_ABYTE_CNT, 3); 213 drv_usecwait(100); /* prevent bursting on CRB */ 214 unm_nic_reg_write(adapter, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 215 unm_nic_reg_write(adapter, UNM_ROMUSB_ROM_INSTR_OPCODE, 0xb); 216 if (wait_rom_done(adapter) != DDI_SUCCESS) { 217 cmn_err(CE_WARN, "Error waiting for rom done\n"); 218 return (-1); 219 } 220 221 // reset abyte_cnt and dummy_byte_cnt 222 unm_nic_reg_write(adapter, UNM_ROMUSB_ROM_ABYTE_CNT, 0); 223 drv_usecwait(100); /* prevent bursting on CRB */ 224 unm_nic_reg_write(adapter, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 225 226 unm_nic_reg_read(adapter, UNM_ROMUSB_ROM_RDATA, valp); 227 return (0); 228 } 229 230 int 231 rom_fast_read(struct unm_adapter_s *adapter, int addr, int *valp) 232 { 233 int ret; 234 235 if (rom_lock(adapter) != 0) { 236 cmn_err(CE_WARN, "%s(%d)rom_lock failed\n", 237 __FUNCTION__, __LINE__); 238 return (-1); 239 } 240 241 ret = do_rom_fast_read(adapter, addr, valp); 242 if (ret != 0) { 243 cmn_err(CE_WARN, "%s do_rom_fast_read returned: %d\n", 244 __FUNCTION__, __LINE__); 245 return (-1); 246 } 247 rom_unlock(adapter); 248 return (ret); 249 } 250 251 int 252 pinit_from_rom(struct unm_adapter_s *adapter, int verbose) 253 { 254 int addr, val, status, i, init_delay = 0, n; 255 struct crb_addr_pair *buf; 256 unsigned long off; 257 unsigned int offset; 258 259 status = unm_nic_get_board_info(adapter); 260 if (status) 261 cmn_err(CE_WARN, "%s: pinit_from_rom: Error getting brdinfo\n", 262 unm_nic_driver_name); 263 264 UNM_CRB_WRITELIT_ADAPTER(UNM_ROMUSB_GLB_SW_RESET, 0xffffffff, adapter); 265 266 if (verbose) { 267 int val; 268 if (rom_fast_read(adapter, 0x4008, &val) == 0) 269 cmn_err(CE_WARN, "P2 ROM board type: 0x%08x\n", val); 270 else 271 cmn_err(CE_WARN, "Could not read board type\n"); 272 if (rom_fast_read(adapter, 0x400c, &val) == 0) 273 cmn_err(CE_WARN, "ROM board num: 0x%08x\n", val); 274 else 275 cmn_err(CE_WARN, "Could not read board number\n"); 276 if (rom_fast_read(adapter, 0x4010, &val) == 0) 277 cmn_err(CE_WARN, "ROM chip num: 0x%08x\n", val); 278 else 279 cmn_err(CE_WARN, "Could not read chip number\n"); 280 } 281 282 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 283 if (rom_fast_read(adapter, 0, &n) != 0 || 284 (unsigned int)n != 0xcafecafe || 285 rom_fast_read(adapter, 4, &n) != 0) { 286 cmn_err(CE_WARN, "%s: ERROR Reading crb_init area: " 287 "n: %08x\n", unm_nic_driver_name, n); 288 return (-1); 289 } 290 291 offset = n & 0xffffU; 292 n = (n >> 16) & 0xffffU; 293 } else { 294 if (rom_fast_read(adapter, 0, &n) != 0 || 295 !(n & 0x80000000)) { 296 cmn_err(CE_WARN, "%s: ERROR Reading crb_init area: " 297 "n: %08x\n", unm_nic_driver_name, n); 298 return (-1); 299 } 300 offset = 1; 301 n &= ~0x80000000; 302 } 303 304 if (n >= 1024) { 305 cmn_err(CE_WARN, "%s: %s:n=0x%x Card flash not initialized\n", 306 unm_nic_driver_name, __FUNCTION__, n); 307 return (-1); 308 } 309 310 if (verbose) 311 cmn_err(CE_WARN, "%s: %d CRB init values found in ROM.\n", 312 unm_nic_driver_name, n); 313 314 buf = kmem_zalloc(n * sizeof (struct crb_addr_pair), KM_SLEEP); 315 if (buf == NULL) { 316 cmn_err(CE_WARN, "%s: pinit_from_rom: Unable to get memory\n", 317 unm_nic_driver_name); 318 return (-1); 319 } 320 321 for (i = 0; i < n; i++) { 322 if (rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 || 323 rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) { 324 kmem_free(buf, n * sizeof (struct crb_addr_pair)); 325 return (-1); 326 } 327 328 buf[i].addr = addr; 329 buf[i].data = val; 330 331 if (verbose) 332 cmn_err(CE_WARN, "%s: PCI: 0x%08x == 0x%08x\n", 333 unm_nic_driver_name, 334 (unsigned int)decode_crb_addr( 335 (unsigned long)addr), val); 336 } 337 338 for (i = 0; i < n; i++) { 339 off = decode_crb_addr((unsigned long)buf[i].addr) + 340 UNM_PCI_CRBSPACE; 341 /* skipping cold reboot MAGIC */ 342 if (off == UNM_CAM_RAM(0x1fc)) { 343 continue; 344 } 345 346 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 347 /* do not reset PCI */ 348 if (off == (ROMUSB_GLB + 0xbc)) { 349 continue; 350 } 351 if (off == (ROMUSB_GLB + 0xc8)) /* core clock */ 352 continue; 353 if (off == (ROMUSB_GLB + 0x24)) /* MN clock */ 354 continue; 355 if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */ 356 continue; 357 if (off == (UNM_CRB_PEG_NET_1 + 0x18)) { 358 buf[i].data = 0x1020; 359 } 360 /* skip the function enable register */ 361 if (off == UNM_PCIE_REG(PCIE_SETUP_FUNCTION)) { 362 continue; 363 } 364 if (off == UNM_PCIE_REG(PCIE_SETUP_FUNCTION2)) { 365 continue; 366 } 367 368 if ((off & 0x0ff00000) == UNM_CRB_SMB) { 369 continue; 370 } 371 372 } 373 374 if (off == ADDR_ERROR) { 375 cmn_err(CE_WARN, "%s: Err: Unknown addr: 0x%08lx\n", 376 unm_nic_driver_name, buf[i].addr); 377 continue; 378 } 379 380 /* After writing this register, HW needs time for CRB */ 381 /* to quiet down (else crb_window returns 0xffffffff) */ 382 if (off == UNM_ROMUSB_GLB_SW_RESET) { 383 init_delay = 1; 384 385 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 386 /* hold xdma in reset also */ 387 buf[i].data = 0x8000ff; 388 } 389 } 390 391 adapter->unm_nic_hw_write_wx(adapter, off, &buf[i].data, 4); 392 393 if (init_delay == 1) { 394 nx_msleep(1000); /* Sleep 1000 msecs */ 395 init_delay = 0; 396 } 397 398 nx_msleep(1); /* Sleep 1 msec */ 399 } 400 401 kmem_free(buf, n * sizeof (struct crb_addr_pair)); 402 403 // disable_peg_cache_all 404 // unreset_net_cache 405 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 406 val = UNM_CRB_READ_VAL_ADAPTER(UNM_ROMUSB_GLB_SW_RESET, 407 adapter); 408 UNM_CRB_WRITELIT_ADAPTER(UNM_ROMUSB_GLB_SW_RESET, 409 (val & 0xffffff0f), adapter); 410 } 411 412 // p2dn replyCount 413 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_D+0xec, 0x1e, adapter); 414 // disable_peg_cache 0 415 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_D+0x4c, 8, adapter); 416 // disable_peg_cache 1 417 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_I+0x4c, 8, adapter); 418 419 // peg_clr_all 420 // peg_clr 0 421 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_0+0x8, 0, adapter); 422 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_0+0xc, 0, adapter); 423 // peg_clr 1 424 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_1+0x8, 0, adapter); 425 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_1+0xc, 0, adapter); 426 // peg_clr 2 427 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_2+0x8, 0, adapter); 428 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_2+0xc, 0, adapter); 429 // peg_clr 3 430 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_3+0x8, 0, adapter); 431 UNM_CRB_WRITELIT_ADAPTER(UNM_CRB_PEG_NET_3+0xc, 0, adapter); 432 433 return (0); 434 } 435 436 int 437 phantom_init(struct unm_adapter_s *adapter, int pegtune_val) 438 { 439 u32 val = 0; 440 int retries = 120; 441 442 if (!pegtune_val) { 443 do { 444 val = adapter->unm_nic_pci_read_normalize(adapter, 445 CRB_CMDPEG_STATE); 446 447 if ((val == PHAN_INITIALIZE_COMPLETE) || 448 (val == PHAN_INITIALIZE_ACK)) 449 return (DDI_SUCCESS); 450 451 /* 500 msec wait */ 452 drv_usecwait(500000); 453 } while (--retries > 0); 454 455 if (!retries) { 456 val = adapter->unm_nic_pci_read_normalize(adapter, 457 UNM_ROMUSB_GLB_PEGTUNE_DONE); 458 cmn_err(CE_WARN, "WARNING: Initial boot wait loop" 459 "failed...state:%d\n", val); 460 return (DDI_FAILURE); 461 } 462 } 463 464 return (DDI_SUCCESS); 465 } 466 467 int 468 load_from_flash(struct unm_adapter_s *adapter) 469 { 470 int i; 471 long data, size = 0; 472 long flashaddr = BOOTLD_START, memaddr = BOOTLD_START; 473 474 size = (IMAGE_START - BOOTLD_START)/4; 475 476 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 477 data = 1; 478 adapter->unm_nic_hw_write_wx(adapter, UNM_ROMUSB_GLB_CAS_RST, 479 &data, 4); 480 } 481 482 for (i = 0; i < size; i++) { 483 if (rom_fast_read(adapter, flashaddr, (int *)&data) != 0) { 484 cmn_err(CE_WARN, "Error in rom_fast_read: " 485 "Will skip loading flash image\n"); 486 return (DDI_FAILURE); 487 } 488 489 adapter->unm_nic_pci_mem_write(adapter, memaddr, &data, 4); 490 flashaddr += 4; 491 memaddr += 4; 492 } 493 494 drv_usecwait(100); 495 UNM_READ_LOCK(&adapter->adapter_lock); 496 497 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 498 data = 0x80001d; 499 adapter->unm_nic_hw_write_wx(adapter, UNM_ROMUSB_GLB_SW_RESET, 500 &data, 4); 501 } else { 502 data = 0x3fff; 503 adapter->unm_nic_hw_write_wx(adapter, 504 UNM_ROMUSB_GLB_CHIP_CLK_CTRL, &data, 4); 505 data = 0; 506 adapter->unm_nic_hw_write_wx(adapter, UNM_ROMUSB_GLB_CAS_RST, 507 &data, 4); 508 } 509 510 UNM_READ_UNLOCK(&adapter->adapter_lock); 511 return (DDI_SUCCESS); 512 } 513