1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 NetXen, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef __UNM_BRDINFO_H 26 #define __UNM_BRDINFO_H 27 28 /* The version of the main data structure */ 29 #define UNM_BDINFO_VERSION 1 30 31 /* Magic number to let user know flash is programmed */ 32 #define UNM_BDINFO_MAGIC 0x12345678 33 34 #define P2_CHIP 2 35 #define P3_CHIP 3 36 #define NX_P2_C0 0x24 37 #define NX_P2_C1 0x25 38 #define NX_P3_A0 0x30 39 #define NX_P3_A2 0x32 40 #define NX_P3_B0 0x40 41 #define NX_P3_B1 0x41 42 #define NX_P3_B2 0x42 43 44 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1) 45 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0) 46 47 typedef enum { 48 UNM_BRDTYPE_P1_BD = 0x0000, 49 UNM_BRDTYPE_P1_SB = 0x0001, 50 UNM_BRDTYPE_P1_SMAX = 0x0002, 51 UNM_BRDTYPE_P1_SOCK = 0x0003, 52 53 UNM_BRDTYPE_P2_SOCK_31 = 0x0008, 54 UNM_BRDTYPE_P2_SOCK_35 = 0x0009, 55 UNM_BRDTYPE_P2_SB35_4G = 0x000a, 56 UNM_BRDTYPE_P2_SB31_10G = 0x000b, 57 UNM_BRDTYPE_P2_SB31_2G = 0x000c, 58 59 UNM_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, 60 UNM_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, 61 UNM_BRDTYPE_P2_SB31_10G_CX4 = 0x000f, 62 63 /* Reference quad gig */ 64 UNM_BRDTYPE_P3_REF_QG = 0x0021, 65 UNM_BRDTYPE_P3_HMEZ = 0x0022, 66 /* Dual CX4 - Low Profile - Red card */ 67 UNM_BRDTYPE_P3_10G_CX4_LP = 0x0023, 68 UNM_BRDTYPE_P3_4_GB = 0x0024, 69 UNM_BRDTYPE_P3_IMEZ = 0x0025, 70 UNM_BRDTYPE_P3_10G_SFP_PLUS = 0x0026, 71 UNM_BRDTYPE_P3_10000_BASE_T = 0x0027, 72 UNM_BRDTYPE_P3_XG_LOM = 0x0028, 73 74 UNM_BRDTYPE_P3_4_GB_MM = 0x0029, 75 UNM_BRDTYPE_P3_10G_CX4 = 0x0031, /* Reference CX4 */ 76 UNM_BRDTYPE_P3_10G_XFP = 0x0032, /* Reference XFP */ 77 78 UNM_BRDTYPE_P3_10G_TRP = 0x0080, 79 80 } unm_brdtype_t; 81 82 typedef enum { 83 NX_UNKNOWN_TYPE_ROMIMAGE = 0, 84 NX_P2_MN_TYPE_ROMIMAGE = 1, 85 NX_P3_CT_TYPE_ROMIMAGE, 86 NX_P3_MN_TYPE_ROMIMAGE, 87 NX_P3_MS_TYPE_ROMIMAGE, 88 NX_UNKNOWN_TYPE_ROMIMAGE_LAST, 89 } nx_fw_type_t; 90 91 /* board type specific information */ 92 typedef struct { 93 unm_brdtype_t brdtype; /* type of board */ 94 long ports; /* max no of physical ports */ 95 nx_fw_type_t fwtype; /* The FW Associated with board type */ 96 char *short_name; 97 } unm_brdinfo_t; 98 99 #define NUM_SUPPORTED_BOARDS (sizeof (unm_boards)/sizeof (unm_brdinfo_t)) 100 101 #define GET_BRD_NAME_BY_TYPE(type, name) \ 102 { \ 103 int i, found = 0; \ 104 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { \ 105 if (unm_boards[i].brdtype == type) { \ 106 name = unm_boards[i].short_name; \ 107 found = 1; \ 108 break; \ 109 } \ 110 } \ 111 if (!found) \ 112 name = "Unknown"; \ 113 } 114 115 typedef struct { 116 __uint32_t header_version; 117 118 __uint32_t board_mfg; 119 __uint32_t board_type; 120 __uint32_t board_num; 121 __uint32_t chip_id; 122 __uint32_t chip_minor; 123 __uint32_t chip_major; 124 __uint32_t chip_pkg; 125 __uint32_t chip_lot; 126 127 128 __uint32_t port_mask; /* available niu ports */ 129 __uint32_t peg_mask; /* available pegs */ 130 __uint32_t icache_ok; /* can we run with icache? */ 131 __uint32_t dcache_ok; /* can we run with dcache? */ 132 __uint32_t casper_ok; 133 134 /* unm_eth_addr_t mac_address[MAX_PORTS]; */ 135 __uint32_t mac_addr_lo_0; 136 __uint32_t mac_addr_lo_1; 137 __uint32_t mac_addr_lo_2; 138 __uint32_t mac_addr_lo_3; 139 140 /* MN-related config */ 141 __uint32_t mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */ 142 __uint32_t mn_sync_shift_cclk; 143 __uint32_t mn_sync_shift_mclk; 144 __uint32_t mn_wb_en; 145 __uint32_t mn_crystal_freq; /* in MHz */ 146 __uint32_t mn_speed; /* in MHz */ 147 __uint32_t mn_org; 148 __uint32_t mn_depth; 149 __uint32_t mn_ranks_0; /* ranks per slot */ 150 __uint32_t mn_ranks_1; /* ranks per slot */ 151 __uint32_t mn_rd_latency_0; 152 __uint32_t mn_rd_latency_1; 153 __uint32_t mn_rd_latency_2; 154 __uint32_t mn_rd_latency_3; 155 __uint32_t mn_rd_latency_4; 156 __uint32_t mn_rd_latency_5; 157 __uint32_t mn_rd_latency_6; 158 __uint32_t mn_rd_latency_7; 159 __uint32_t mn_rd_latency_8; 160 __uint32_t mn_dll_val[18]; 161 __uint32_t mn_mode_reg; /* See MIU DDR Mode Register */ 162 __uint32_t mn_ext_mode_reg; /* See MIU DDR Extended Mode Register */ 163 __uint32_t mn_timing_0; /* See MIU Memory Control Timing Rgister */ 164 __uint32_t mn_timing_1; /* See MIU Extended Memory Ctrl Timing Register */ 165 __uint32_t mn_timing_2; /* See MIU Extended Memory Ctrl Timing2 Register */ 166 167 /* SN-related config */ 168 __uint32_t sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */ 169 __uint32_t sn_pt_mode; /* pass through mode */ 170 __uint32_t sn_ecc_en; 171 __uint32_t sn_wb_en; 172 __uint32_t sn_crystal_freq; 173 __uint32_t sn_speed; 174 __uint32_t sn_org; 175 __uint32_t sn_depth; 176 __uint32_t sn_dll_tap; 177 __uint32_t sn_rd_latency; 178 179 __uint32_t mac_addr_hi_0; 180 __uint32_t mac_addr_hi_1; 181 __uint32_t mac_addr_hi_2; 182 __uint32_t mac_addr_hi_3; 183 184 __uint32_t magic; /* indicates flash has been initialized */ 185 186 __uint32_t mn_rdimm; 187 __uint32_t mn_dll_override; 188 __uint32_t coreclock_speed; 189 } unm_board_info_t; 190 191 #define FLASH_NUM_PORTS 4 192 193 typedef struct { 194 __uint32_t flash_addr[32]; 195 } unm_flash_mac_addr_t; 196 197 /* flash user area */ 198 typedef struct { 199 __uint8_t flash_md5[16]; 200 __uint8_t crbinit_md5[16]; 201 __uint8_t brdcfg_md5[16]; 202 /* bootloader */ 203 __uint32_t bootld_version; 204 __uint32_t bootld_size; 205 __uint8_t bootld_md5[16]; 206 /* image */ 207 __uint32_t image_version; 208 __uint32_t image_size; 209 __uint8_t image_md5[16]; 210 /* primary image status */ 211 __uint32_t primary_status; 212 __uint32_t secondary_present; 213 214 /* MAC address , 4 ports */ 215 unm_flash_mac_addr_t mac_addr[FLASH_NUM_PORTS]; 216 217 /* Any user defined data */ 218 } unm_old_user_info_t; 219 220 #define FLASH_NUM_MAC_PER_PORT 32 221 typedef struct { 222 __uint8_t flash_md5[16 * 64]; 223 // __uint8_t crbinit_md5[16]; 224 // __uint8_t brdcfg_md5[16]; 225 /* bootloader */ 226 __uint32_t bootld_version; 227 __uint32_t bootld_size; 228 // __uint8_t bootld_md5[16]; 229 /* image */ 230 __uint32_t image_version; 231 __uint32_t image_size; 232 // U8 image_md5[16]; 233 /* primary image status */ 234 __uint32_t primary_status; 235 __uint32_t secondary_present; 236 237 /* MAC address , 4 ports, 32 address per port */ 238 __uint64_t mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT]; 239 __uint32_t sub_sys_id; 240 __uint8_t serial_num[32]; 241 __uint32_t bios_version; 242 __uint32_t pxe_enable; /* bitmask, per port */ 243 __uint32_t vlan_tag[FLASH_NUM_PORTS]; 244 245 /* Any user defined data */ 246 } unm_user_info_t; 247 248 /* Flash memory map */ 249 typedef enum { 250 CRBINIT_START = 0, /* Crbinit section */ 251 BRDCFG_START = 0x4000, /* board config */ 252 INITCODE_START = 0x6000, /* pegtune code */ 253 BOOTLD_START = 0x10000, /* bootld */ 254 BOOTLD1_START = 0x14000, /* Start of booloader 1 */ 255 IMAGE_START = 0x43000, /* compressed image */ 256 SECONDARY_START = 0x200000, /* backup images */ 257 PXE_FIRST_STAGE_INTEL = 0x3C0000, /* Intel First Stage info */ 258 PXE_FIRST_STAGE_PPC = 0x3C4000, /* PPC First Stage info */ 259 PXE_SECOND_STAGE_INTEL = 0x3B0000, /* Intel Second Stage info */ 260 PXE_SECOND_STAGE_PPC = 0x3A0000, /* Intel Second Stage info */ 261 // LICENSE_TIME_START = 0x3C0000, /* license expiry time info */ 262 PXE_START = 0x3D0000, /* PXE image area */ 263 DEFAULT_DATA_START = 0x3e0000, /* where we place default factory data */ 264 /* User defined region for new boards */ 265 USER_START = 0x3E8000, 266 VPD_START = 0x3E8C00, /* Vendor private data */ 267 LICENSE_START = 0x3E9000, /* Firmware License */ 268 FIXED_START = 0x3F0000 /* backup of crbinit */ 269 } unm_flash_map_t; 270 271 #define USER_START_OLD PXE_START /* for backward compatibility */ 272 273 #endif /* !__UNM_BRDINFO_H */ 274