1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 NetXen, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Data types and structure for HAL - NIC interface. 27 * 28 */ 29 30 #ifndef _NXHAL_NIC_INTERFACE_H_ 31 #define _NXHAL_NIC_INTERFACE_H_ 32 33 /* 34 * Simple Types 35 */ 36 37 typedef U32 nx_reg_addr_t; 38 39 /* 40 * Root crb-based firmware commands 41 */ 42 43 /* 44 * CRB Root Command 45 * A single set of crbs is used across all physical/virtual 46 * functions for capability queries, initialization, and 47 * context creation/destruction. 48 * 49 * There are 4 CRBS: 50 * Command/Response CRB 51 * Argument1 CRB 52 * Argument2 CRB 53 * Argument3 CRB 54 * Signature CRB 55 * 56 * The cmd/rsp crb is always intiated by the host via 57 * a command code and always responded by the card with 58 * a response code. The cmd and rsp codes are disjoint. 59 * The sequence of use is always CMD, RSP, CLEAR CMD. 60 * 61 * The arguments are for passing in command specific 62 * and response specific parameters/data. 63 * 64 * The signature is composed of a magic value, the 65 * pci function id, and a command sequence id: 66 * [7:0] = pci function 67 * [15:8] = version 68 * [31:16] = magic of 0xcafe 69 * 70 * The pci function allows the card to take correct 71 * action for the given particular commands. 72 * The firmware will attempt to detect 73 * an errant driver that has died while holding 74 * the root crb hardware lock. Such an error condition 75 * shows up as the cmd/rsp crb stuck in a non-clear state. 76 * 77 * Interface Sequence: 78 * Host always makes requests and firmware always responds. 79 * Note that data field is always set prior to command field. 80 * 81 * [READ] CMD/RSP CRB ARGUMENT FIELD 82 * Host grab lock 83 * Host -> CMD optional parameter 84 * FW <- (Good) RSP-OK DATA 85 * FW <- (Fail) RSP-FAIL optional failure code 86 * Host -> CLEAR 87 * Host release lock 88 * 89 * [WRITE] CMD/RSP CRB ARGUMENT FIELD 90 * Host grab lock 91 * Host -> CMD DATA 92 * FW <- (Good) RSP-OK optional write status 93 * FW <- (Write) RSP-FAIL optional failure code 94 * Host -> CLEAR 95 * Host release lock 96 */ 97 98 99 /* 100 * CMD/RSP 101 */ 102 103 #define NX_CDRP_SIGNATURE_TO_PCIFN(sign) ((sign) & 0xff) 104 #define NX_CDRP_SIGNATURE_TO_VERSION(sign) (((sign)>>8) & 0xff) 105 #define NX_CDRP_SIGNATURE_TO_MAGIC(sign) (((sign)>>16) & 0xffff) 106 #define NX_CDRP_SIGNATURE_VALID(sign) \ 107 (NX_CDRP_SIGNATURE_TO_MAGIC(sign) == 0xcafe && \ 108 NX_CDRP_SIGNATURE_TO_PCIFN(sign) < 8) 109 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \ 110 (((pcifn) & 0xff) | \ 111 (((version) & 0xff) << 8) | \ 112 ((u32)0xcafe << 16)) 113 114 #define NX_CDRP_CLEAR 0x00000000 115 #define NX_CDRP_CMD_BIT 0x80000000 116 117 /* 118 * All responses must have the NX_CDRP_CMD_BIT cleared 119 * in the crb NX_CDRP_CRB_OFFSET. 120 */ 121 122 #define NX_CDRP_FORM_RSP(rsp) (rsp) 123 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0) 124 125 #define NX_CDRP_RSP_OK 0x00000001 126 #define NX_CDRP_RSP_FAIL 0x00000002 127 #define NX_CDRP_RSP_TIMEOUT 0x00000003 128 129 /* 130 * All commands must have the NX_CDRP_CMD_BIT set in 131 * the crb NX_CDRP_CRB_OFFSET. 132 * The macros below do not have it explicitly set to 133 * allow their use in lookup tables 134 */ 135 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd)) 136 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0) 137 138 /* [CMD] Capability Vector [RSP] Capability Vector */ 139 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 140 141 /* [CMD] - [RSP] Query Value */ 142 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 143 144 /* [CMD] - [RSP] Query Value */ 145 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 146 147 /* [CMD] - [RSP] Query Value */ 148 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 149 150 /* [CMD] - [RSP] Query Value */ 151 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 152 153 /* [CMD] - [RSP] Query Value */ 154 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 155 156 /* [CMD] Rx Config DMA Addr [RSP] rcode */ 157 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007 158 159 /* [CMD] Rx Context Handle, Reset Kind [RSP] rcode */ 160 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008 161 162 /* [CMD] Tx Config DMA Addr [RSP] rcode */ 163 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009 164 165 /* [CMD] Tx Context Handle, Reset Kind [RSP] rcode */ 166 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a 167 168 /* [CMD] Stat setup dma addr - [RSP] Handle, rcode */ 169 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e 170 171 /* [CMD] Handle - [RSP] rcode */ 172 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f 173 174 /* [CMD] Handle - [RSP] rcode */ 175 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010 176 177 /* [CMD] - [RSP] rcode */ 178 #define NX_CDRP_CMD_GEN_INT 0x00000011 179 180 /* [CMD] MTU - [RSP] rcode */ 181 #define NX_CDRP_CMD_SET_MTU 0x00000012 182 183 #define NX_CDRP_CMD_MAX 0x00000013 184 185 /* 186 * Capabilities 187 */ 188 189 #define NX_CAP_BIT(class, bit) (1 << bit) 190 191 /* Class 0 (i.e. ARGS 1) */ 192 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0) 193 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1) 194 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2) 195 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3) 196 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4) 197 #define NX_CAP0_LRO NX_CAP_BIT(0, 5) 198 #define NX_CAP0_LSO NX_CAP_BIT(0, 6) 199 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7) 200 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8) 201 202 /* Class 1 (i.e. ARGS 2) */ 203 #define NX_CAP1_NIC NX_CAP_BIT(1, 0) 204 #define NX_CAP1_PXE NX_CAP_BIT(1, 1) 205 #define NX_CAP1_CHIMNEY NX_CAP_BIT(1, 2) 206 #define NX_CAP1_LSA NX_CAP_BIT(1, 3) 207 #define NX_CAP1_RDMA NX_CAP_BIT(1, 4) 208 #define NX_CAP1_ISCSI NX_CAP_BIT(1, 5) 209 #define NX_CAP1_FCOE NX_CAP_BIT(1, 6) 210 211 /* Class 2 (i.e. ARGS 3) */ 212 213 /* 214 * Rules 215 */ 216 217 typedef U32 nx_rx_rule_type_t; 218 219 #define NX_RX_RULETYPE_DEFAULT 0 220 #define NX_RX_RULETYPE_MAC 1 221 #define NX_RX_RULETYPE_MAC_VLAN 2 222 #define NX_RX_RULETYPE_MAC_RSS 3 223 #define NX_RX_RULETYPE_MAC_VLAN_RSS 4 224 #define NX_RX_RULETYPE_MAX 5 225 226 typedef U32 nx_rx_rule_cmd_t; 227 228 #define NX_RX_RULECMD_ADD 0 229 #define NX_RX_RULECMD_REMOVE 1 230 #define NX_RX_RULECMD_MAX 2 231 232 typedef struct nx_rx_rule_arg_s { 233 union { 234 struct { 235 char mac[6]; 236 } m; 237 struct { 238 char mac[6]; 239 char vlan; 240 } mv; 241 struct { 242 char mac[6]; 243 } mr; 244 struct { 245 char mac[6]; 246 char vlan; 247 } mvr; 248 } s1; 249 /* will be union of all the different args for rules */ 250 U64 data; 251 } nx_rx_rule_arg_t; 252 253 typedef struct nx_rx_rule_s { 254 U32 id; 255 U32 active; 256 nx_rx_rule_arg_t arg; 257 nx_rx_rule_type_t type; 258 } nx_rx_rule_t; 259 260 /* MSG - REQUIRES TX CONTEXT */ 261 262 /* 263 * The rules can be added/deleted from both the 264 * host and card sides so rq/rsp are similar. 265 */ 266 typedef struct nx_hostmsg_rx_rule_s { 267 nx_rx_rule_cmd_t cmd; 268 nx_rx_rule_t rule; 269 } nx_hostmsg_rx_rule_t; 270 271 typedef struct nx_cardmsg_rx_rule_s { 272 nx_rcode_t rcode; 273 nx_rx_rule_cmd_t cmd; 274 nx_rx_rule_t rule; 275 } nx_cardmsg_rx_rule_t; 276 277 278 /* 279 * Common to Rx/Tx contexts 280 */ 281 282 /* 283 * Context states 284 */ 285 286 typedef U32 nx_host_ctx_state_t; 287 288 #define NX_HOST_CTX_STATE_FREED 0 /* Invalid state */ 289 #define NX_HOST_CTX_STATE_ALLOCATED 1 /* Not committed */ 290 /* The following states imply FW is aware of context */ 291 #define NX_HOST_CTX_STATE_ACTIVE 2 292 #define NX_HOST_CTX_STATE_DISABLED 3 293 #define NX_HOST_CTX_STATE_QUIESCED 4 294 #define NX_HOST_CTX_STATE_MAX 5 295 296 /* 297 * Interrupt mask crb use must be set identically on the Tx 298 * and Rx context configs across a pci function 299 */ 300 301 /* Rx and Tx have unique interrupt/crb */ 302 #define NX_HOST_INT_CRB_MODE_UNIQUE 0 303 /* Rx and Tx share a common interrupt/crb */ 304 #define NX_HOST_INT_CRB_MODE_SHARED 1 /* <= LEGACY */ 305 /* Rx does not use a crb */ 306 #define NX_HOST_INT_CRB_MODE_NORX 2 307 /* Tx does not use a crb */ 308 #define NX_HOST_INT_CRB_MODE_NOTX 3 309 /* Neither Rx nor Tx use a crb */ 310 #define NX_HOST_INT_CRB_MODE_NORXTX 4 311 312 /* 313 * Destroy Rx/Tx 314 */ 315 316 #define NX_DESTROY_CTX_RESET 0 317 #define NX_DESTROY_CTX_D3_RESET 1 318 #define NX_DESTROY_CTX_MAX 2 319 320 321 /* 322 * Tx 323 */ 324 325 /* 326 * Components of the host-request for Tx context creation. 327 * CRB - DOES NOT REQUIRE Rx/TX CONTEXT 328 */ 329 330 typedef struct nx_hostrq_cds_ring_s { 331 U64 host_phys_addr; /* Ring base addr */ 332 U32 ring_size; /* Ring entries */ 333 U32 rsvd; /* Padding */ 334 } nx_hostrq_cds_ring_t; 335 336 typedef struct nx_hostrq_tx_ctx_s { 337 U64 host_rsp_dma_addr; /* Response dma'd here */ 338 U64 cmd_cons_dma_addr; /* */ 339 U64 dummy_dma_addr; /* */ 340 U32 capabilities[4]; /* Flag bit vector */ 341 U32 host_int_crb_mode; /* Interrupt crb usage */ 342 U32 rsvd1; /* Padding */ 343 U16 rsvd2; /* Padding */ 344 U16 interrupt_ctl; 345 U16 msi_index; 346 U16 rsvd3; /* Padding */ 347 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */ 348 U8 reserved[128]; /* future expansion */ 349 } nx_hostrq_tx_ctx_t; 350 351 typedef struct nx_cardrsp_cds_ring_s { 352 U32 host_producer_crb; /* Crb to use */ 353 U32 interrupt_crb; /* Crb to use */ 354 } nx_cardrsp_cds_ring_t; 355 356 typedef struct nx_cardrsp_tx_ctx_s { 357 U32 host_ctx_state; /* Starting state */ 358 U16 context_id; /* Handle for context */ 359 U8 phys_port; /* Physical id of port */ 360 U8 virt_port; /* Virtual/Logical id of port */ 361 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */ 362 U8 reserved[128]; /* future expansion */ 363 } nx_cardrsp_tx_ctx_t; 364 365 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) \ 366 (sizeof (HOSTRQ_TX)) 367 368 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) \ 369 (sizeof (CARDRSP_TX)) 370 371 /* 372 * Rx 373 */ 374 375 /* 376 * RDS ring mapping to producer crbs 377 */ 378 379 /* Each ring has a unique crb */ 380 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0 /* <= LEGACY */ 381 382 /* 383 * All configured RDS Rings share common crb: 384 * 1 Ring - same as unique 385 * 2 Rings - 16, 16 386 * 3 Rings - 10, 10, 10 387 */ 388 #define NX_HOST_RDS_CRB_MODE_SHARED 1 389 390 /* 391 * Bit usage is specified per-ring using the 392 * ring's size. Sum of bit lengths must be <= 32. 393 * Packing is [Ring N] ... [Ring 1][Ring 0] 394 */ 395 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2 396 #define NX_HOST_RDS_CRB_MODE_MAX 3 397 398 399 /* 400 * RDS Ting Types 401 */ 402 403 #define NX_RDS_RING_TYPE_NORMAL 0 404 #define NX_RDS_RING_TYPE_JUMBO 1 405 #define NX_RDS_RING_TYPE_LRO 2 406 #define NX_RDS_RING_TYPE_MAX 3 407 408 /* 409 * Components of the host-request for Rx context creation. 410 * CRB - DOES NOT REQUIRE Rx/TX CONTEXT 411 */ 412 413 typedef struct nx_hostrq_sds_ring_s { 414 U64 host_phys_addr; /* Ring base addr */ 415 U32 ring_size; /* Ring entries */ 416 U16 msi_index; 417 U16 rsvd; /* Padding */ 418 } nx_hostrq_sds_ring_t; 419 420 typedef struct nx_hostrq_rds_ring_s { 421 U64 host_phys_addr; /* Ring base addr */ 422 U64 buff_size; /* Packet buffer size */ 423 U32 ring_size; /* Ring entries */ 424 U32 ring_kind; /* Class of ring */ 425 } nx_hostrq_rds_ring_t; 426 427 typedef struct nx_hostrq_rx_ctx_s { 428 U64 host_rsp_dma_addr; /* Response dma'd here */ 429 U32 capabilities[4]; /* Flag bit vector */ 430 U32 host_int_crb_mode; /* Interrupt crb usage */ 431 U32 host_rds_crb_mode; /* RDS crb usage */ 432 /* These ring offsets are relative to data[0] below */ 433 U32 rds_ring_offset; /* Offset to RDS config */ 434 U32 sds_ring_offset; /* Offset to SDS config */ 435 U16 num_rds_rings; /* Count of RDS rings */ 436 U16 num_sds_rings; /* Count of SDS rings */ 437 U16 rsvd1; /* Padding */ 438 U16 rsvd2; /* Padding */ 439 U8 reserved[128]; /* reserve space for future expansion */ 440 /* 441 * MUST BE 64-bit aligned. 442 * The following is packed: 443 * - N hostrq_rds_rings 444 * - N hostrq_sds_rings 445 */ 446 char data[]; 447 } nx_hostrq_rx_ctx_t; 448 449 typedef struct nx_cardrsp_rds_ring_s { 450 U32 host_producer_crb; /* Crb to use */ 451 U32 rsvd1; /* Padding */ 452 } nx_cardrsp_rds_ring_t; 453 454 typedef struct nx_cardrsp_sds_ring_s { 455 U32 host_consumer_crb; /* Crb to use */ 456 U32 interrupt_crb; /* Crb to use */ 457 } nx_cardrsp_sds_ring_t; 458 459 typedef struct nx_cardrsp_rx_ctx_s { 460 /* These ring offsets are relative to data[0] below */ 461 U32 rds_ring_offset; /* Offset to RDS config */ 462 U32 sds_ring_offset; /* Offset to SDS config */ 463 U32 host_ctx_state; /* Starting State */ 464 U32 num_fn_per_port; /* How many PCI fn share the port */ 465 U16 num_rds_rings; /* Count of RDS rings */ 466 U16 num_sds_rings; /* Count of SDS rings */ 467 U16 context_id; /* Handle for context */ 468 U8 phys_port; /* Physical id of port */ 469 U8 virt_port; /* Virtual/Logical id of port */ 470 U8 reserved[128]; /* save space for future expansion */ 471 /* 472 * MUST BE 64-bit aligned. 473 * The following is packed: 474 * - N cardrsp_rds_rings 475 * - N cardrs_sds_rings 476 */ 477 char data[]; 478 } nx_cardrsp_rx_ctx_t; 479 480 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 481 (sizeof (HOSTRQ_RX) + \ 482 (rds_rings)*(sizeof (nx_hostrq_rds_ring_t)) + \ 483 (sds_rings)*(sizeof (nx_hostrq_sds_ring_t))) 484 485 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ 486 (sizeof (CARDRSP_RX) + \ 487 (rds_rings)*(sizeof (nx_cardrsp_rds_ring_t)) + \ 488 (sds_rings)*(sizeof (nx_cardrsp_sds_ring_t))) 489 490 491 /* 492 * Statistics 493 */ 494 495 /* 496 * The model of statistics update to use 497 */ 498 499 #define NX_STATISTICS_MODE_INVALID 0 500 501 /* 502 * Permanent setup; Updates are only sent on explicit request 503 * NX_CDRP_CMD_GET_STATISTICS) 504 */ 505 #define NX_STATISTICS_MODE_PULL 1 506 507 /* 508 * Permanent setup; Updates are sent automatically and on 509 * explicit request (NX_CDRP_CMD_GET_STATISTICS) 510 */ 511 #define NX_STATISTICS_MODE_PUSH 2 512 513 /* One time stat update. */ 514 #define NX_STATISTICS_MODE_SINGLE_SHOT 3 515 516 #define NX_STATISTICS_MODE_MAX 4 517 518 /* 519 * What set of stats 520 */ 521 #define NX_STATISTICS_TYPE_INVALID 0 522 #define NX_STATISTICS_TYPE_NIC_RX_CORE 1 523 #define NX_STATISTICS_TYPE_NIC_TX_CORE 2 524 #define NX_STATISTICS_TYPE_NIC_RX_ALL 3 525 #define NX_STATISTICS_TYPE_NIC_TX_ALL 4 526 #define NX_STATISTICS_TYPE_MAX 5 527 528 529 /* 530 * Request to setup statistics gathering. 531 * CRB - DOES NOT REQUIRE Rx/TX CONTEXT 532 */ 533 534 typedef struct nx_hostrq_stat_setup_s { 535 U64 host_stat_buffer; /* Where to dma stats */ 536 U32 host_stat_size; /* Size of stat buffer */ 537 U16 context_id; /* Which context */ 538 U16 stat_type; /* What class of stats */ 539 U16 stat_mode; /* When to update */ 540 U16 stat_interval; /* Frequency of update */ 541 } nx_hostrq_stat_setup_t; 542 543 544 545 #endif /* _NXHAL_NIC_INTERFACE_H_ */ 546