1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 NetXen, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef NIC_PHAN_REG_H 26 #define NIC_PHAN_REG_H 27 28 #define NIC_CRB_BASE UNM_CAM_RAM(0x200) 29 #define NIC_CRB_BASE_2 UNM_CAM_RAM(0x700) 30 #define UNM_NIC_REG(X) (NIC_CRB_BASE+(X)) 31 #define UNM_NIC_REG_2(X) (NIC_CRB_BASE_2+(X)) 32 33 #define CRB_CUT_THRU_PAGE_SIZE UNM_CAM_RAM(0x170) 34 35 #define CRB_CMD_PRODUCER_OFFSET UNM_NIC_REG(0x08) 36 #define CRB_CMD_CONSUMER_OFFSET UNM_NIC_REG(0x0c) 37 /* C0 EPG BUG */ 38 #define CRB_PAUSE_ADDR_LO UNM_NIC_REG(0x10) 39 #define CRB_PAUSE_ADDR_HI UNM_NIC_REG(0x14) 40 #define NX_CDRP_CRB_OFFSET UNM_NIC_REG(0x18) 41 #define NX_ARG1_CRB_OFFSET UNM_NIC_REG(0x1c) 42 #define NX_ARG2_CRB_OFFSET UNM_NIC_REG(0x20) 43 #define NX_ARG3_CRB_OFFSET UNM_NIC_REG(0x24) 44 #define NX_SIGN_CRB_OFFSET UNM_NIC_REG(0x28) 45 #define CRB_CMDPEG_CMDRING UNM_NIC_REG(0x38) 46 #define CRB_HOST_DUMMY_BUF_ADDR_HI UNM_NIC_REG(0x3c) 47 #define CRB_HOST_DUMMY_BUF_ADDR_LO UNM_NIC_REG(0x40) 48 #define CRB_CMDPEG_STATE UNM_NIC_REG(0x50) 49 /* interrupt coalescing */ 50 #define CRB_GLOBAL_INT_COAL UNM_NIC_REG(0x64) 51 #define CRB_INT_COAL_MODE UNM_NIC_REG(0x68) 52 #define CRB_MAX_RCV_BUFS UNM_NIC_REG(0x6c) 53 #define CRB_TX_INT_THRESHOLD UNM_NIC_REG(0x70) 54 #define CRB_RX_PKT_TIMER UNM_NIC_REG(0x74) 55 #define CRB_TX_PKT_TIMER UNM_NIC_REG(0x78) 56 #define CRB_RX_PKT_CNT UNM_NIC_REG(0x7c) 57 #define CRB_RX_TMR_CNT UNM_NIC_REG(0x80) 58 #define CRB_RCV_INTR_COUNT UNM_NIC_REG(0x84) 59 /* XG Link status */ 60 #define CRB_XG_STATE UNM_NIC_REG(0x94) 61 /* XG PF Link status */ 62 #define CRB_XG_STATE_P3 UNM_NIC_REG(0x98) 63 /* Debug -performance */ 64 #define CRB_TX_STATE UNM_NIC_REG(0xac) 65 #define CRB_TX_COUNT UNM_NIC_REG(0xb0) 66 #define CRB_RX_STATE UNM_NIC_REG(0xb4) 67 #define CRB_RX_PERF_DEBUG_1 UNM_NIC_REG(0xb8) 68 /* LRO On/OFF */ 69 #define CRB_RX_LRO_CONTROL UNM_NIC_REG(0xbc) 70 /* Multiport Mode */ 71 #define CRB_MPORT_MODE UNM_NIC_REG(0xc4) 72 #define CRB_INT_VECTOR UNM_NIC_REG(0xd4) 73 #define CRB_PF_LINK_SPEED_1 UNM_NIC_REG(0xe8) 74 #define CRB_PF_LINK_SPEED_2 UNM_NIC_REG(0xec) 75 #define CRB_HOST_DUMMY_BUF UNM_NIC_REG(0xfc) 76 77 #define CRB_SCRATCHPAD_TEST UNM_NIC_REG(0x280) 78 79 #define CRB_RCVPEG_STATE UNM_NIC_REG(0x13c) 80 81 /* 12 registers to store MAC addresses for 8 PCI functions */ 82 #define CRB_MAC_BLOCK_START UNM_CAM_RAM(0x1c0) 83 84 #define CRB_CMD_PRODUCER_OFFSET_1 UNM_NIC_REG(0x1ac) 85 #define CRB_CMD_CONSUMER_OFFSET_1 UNM_NIC_REG(0x1b0) 86 #define CRB_TEMP_STATE UNM_NIC_REG(0x1b4) 87 #define CRB_CMD_PRODUCER_OFFSET_2 UNM_NIC_REG(0x1b8) 88 #define CRB_CMD_CONSUMER_OFFSET_2 UNM_NIC_REG(0x1bc) 89 90 #define CRB_CMD_PRODUCER_OFFSET_3 UNM_NIC_REG(0x1d0) 91 #define CRB_CMD_CONSUMER_OFFSET_3 UNM_NIC_REG(0x1d4) 92 /* sw int status/mask registers */ 93 #define CRB_SW_INT_MASK_OFFSET_0 0x1d8 94 #define CRB_SW_INT_MASK_OFFSET_1 0x1e0 95 #define CRB_SW_INT_MASK_OFFSET_2 0x1e4 96 #define CRB_SW_INT_MASK_OFFSET_3 0x1e8 97 #define CRB_SW_INT_MASK_OFFSET_4 0x450 98 #define CRB_SW_INT_MASK_OFFSET_5 0x454 99 #define CRB_SW_INT_MASK_OFFSET_6 0x458 100 #define CRB_SW_INT_MASK_OFFSET_7 0x45c 101 #define CRB_SW_INT_MASK_0 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_0) 102 #define CRB_SW_INT_MASK_1 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_1) 103 #define CRB_SW_INT_MASK_2 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_2) 104 #define CRB_SW_INT_MASK_3 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_3) 105 #define CRB_SW_INT_MASK_4 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_4) 106 #define CRB_SW_INT_MASK_5 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_5) 107 #define CRB_SW_INT_MASK_6 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_6) 108 #define CRB_SW_INT_MASK_7 UNM_NIC_REG(CRB_SW_INT_MASK_OFFSET_7) 109 110 #define CRB_NIC_DEBUG_STRUCT_BASE UNM_NIC_REG(0x288) 111 112 /* 113 * capabilities register, can be used to selectively enable/disable features 114 * for backward compability 115 */ 116 #define CRB_NIC_CAPABILITIES_HOST UNM_NIC_REG(0x1a8) 117 #define CRB_NIC_MSI_MODE_HOST UNM_NIC_REG(0x270) 118 #define INTR_SCHEME_PERPORT 0x1 119 #define MSI_MODE_MULTIFUNC 0x1 120 121 #define CRB_EPG_QUEUE_BUSY_COUNT UNM_NIC_REG(0x200) 122 123 #define CRB_V2P_0 UNM_NIC_REG(0x290) 124 #define CRB_V2P_1 UNM_NIC_REG(0x294) 125 #define CRB_V2P_2 UNM_NIC_REG(0x298) 126 #define CRB_V2P_3 UNM_NIC_REG(0x29c) 127 #define CRB_V2P(port) (CRB_V2P_0+((port)*4)) 128 #define CRB_DRIVER_VERSION UNM_NIC_REG(0x2a0) 129 130 #define CRB_CNT_DBG1 UNM_NIC_REG(0x2a4) 131 #define CRB_CNT_DBG2 UNM_NIC_REG(0x2a8) 132 #define CRB_CNT_DBG3 UNM_NIC_REG(0x2ac) 133 134 /* 135 * Driver must set the version number register as follows: 136 * (major << 16) | (minor << 8) | (subminor) 137 */ 138 139 /* last -> 0x2a0 */ 140 141 /* Upper 16 bits of CRB_TEMP_STATE:temperature value. Lower 16 bits: state */ 142 #define nx_get_temp_val(x) ((x) >> 16) 143 #define nx_get_temp_state(x) ((x) & 0xffff) 144 #define nx_encode_temp(val, state) (((val) << 16) | (state)) 145 146 #define lower32(x) ((__uint32_t)((x) & 0xffffffff)) 147 #define upper32(x) ((__uint32_t)(((unsigned long long)(x) >> 32) & \ 148 0xffffffff)) 149 150 /* 151 * Temperature control. 152 */ 153 enum { 154 NX_TEMP_NORMAL = 0x1, /* Normal operating range */ 155 NX_TEMP_WARN, /* Sound alert, temperature getting high */ 156 NX_TEMP_PANIC /* Fatal error, hardware has shut down. */ 157 }; 158 159 #define D3_CRB_REG_FUN2 (UNM_PCIX_PS_REG(0x2084)) 160 #define D3_CRB_REG_FUN3 (UNM_PCIX_PS_REG(0x3084)) 161 #endif /* NIC_PHAN_REG_H */ 162