1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_NGE_CHIP_H 28 #define _SYS_NGE_CHIP_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include "nge.h" 35 36 #define VENDOR_ID_NVIDIA 0x10de 37 38 #define DEVICE_ID_MCP04_37 0x37 39 #define DEVICE_ID_MCP04_38 0x38 40 #define DEVICE_ID_CK804_56 0x56 41 #define DEVICE_ID_CK804_57 0x57 42 #define DEVICE_ID_MCP51_269 0x269 43 #define DEVICE_ID_MCP51_268 0x268 44 #define DEVICE_ID_MCP55_373 0x373 45 #define DEVICE_ID_MCP55_372 0x372 46 #define DEVICE_ID_MCP61_3EE 0x3ee 47 #define DEVICE_ID_MCP61_3EF 0x3ef 48 #define DEVICE_ID_NF3_E6 0xe6 49 #define DEVICE_ID_NF3_DF 0xdf 50 51 /* Private PCI configuration register for bus config of ck804/mcp55 */ 52 #define PCI_CONF_HT_INTERNAL 0x4c 53 54 typedef union _nge_interbus_conf { 55 uint32_t conf_val; 56 struct { 57 uint32_t unit_id:5; 58 uint32_t resv5_23:19; 59 uint32_t aux_val:3; 60 uint32_t resv27:1; 61 uint32_t msi_off:1; 62 uint32_t msix_off:1; /* mcp55 only */ 63 uint32_t resv30_31:2; 64 } conf_bits; 65 } nge_interbus_conf; 66 67 /* Private PCI configuration register for MSI mask of mcp55 */ 68 #define PCI_CONF_HT_MSI_MASK 0x60 69 70 typedef union _nge_msi_mask_conf { 71 uint32_t msi_mask_conf_val; 72 struct { 73 uint32_t vec0_off:1; 74 uint32_t vec1_off:1; 75 uint32_t vec2_off:1; 76 uint32_t vec3_off:1; 77 uint32_t vec4_off:1; 78 uint32_t vec5_off:1; 79 uint32_t vec6_off:1; 80 uint32_t vec7_off:1; 81 uint32_t resv8_31:24; 82 } msi_mask_bits; 83 } nge_msi_mask_conf; 84 85 /* Private PCI configuration register for MSI map capability of mcp55 */ 86 #define PCI_CONF_HT_MSI_MAP_CAP 0x6c 87 88 typedef union _nge_msi_map_cap_conf { 89 uint32_t msi_map_cap_conf_val; 90 struct { 91 uint32_t cap_id:8; 92 uint32_t next_ptr:8; 93 uint32_t map_en:1; 94 uint32_t map_fixed:1; 95 uint32_t resv18_26:9; 96 uint32_t cap_type:5; 97 } map_cap_conf_bits; 98 } nge_msi_map_cap_conf; 99 100 /* 101 * Master interrupt 102 */ 103 #define NGE_INTR_SRC 0x000 104 #define INTR_SRC_ALL 0x00007fff 105 typedef union _nge_intr_src { 106 uint32_t intr_val; 107 struct { 108 uint32_t reint:1; 109 uint32_t rcint:1; 110 uint32_t miss:1; 111 uint32_t teint:1; 112 uint32_t tcint:1; 113 uint32_t stint:1; 114 uint32_t mint:1; 115 uint32_t rfint:1; 116 uint32_t tfint:1; 117 uint32_t feint:1; 118 uint32_t resv10:1; 119 uint32_t resv11:1; 120 uint32_t resv12:1; 121 uint32_t resv13:1; 122 uint32_t phyint:1; 123 uint32_t resv15_31:17; 124 } int_bits; 125 } nge_intr_src; 126 127 /* 128 * Master interrupt Mask 129 */ 130 #define NGE_INTR_MASK 0x004 131 #define NGE_INTR_ALL_EN 0x00007fff 132 typedef union _nge_intr_mask { 133 uint32_t mask_val; 134 struct { 135 uint32_t reint:1; 136 uint32_t rcint:1; 137 uint32_t miss:1; 138 uint32_t teint:1; 139 uint32_t tcint:1; 140 uint32_t stint:1; 141 uint32_t mint:1; 142 uint32_t rfint:1; 143 uint32_t tfint:1; 144 uint32_t feint:1; 145 uint32_t resv10:1; 146 uint32_t resv11:1; 147 uint32_t resv12:1; 148 uint32_t resv13:1; 149 uint32_t phyint:1; 150 uint32_t resv15_31:17; 151 } mask_bits; 152 } nge_intr_mask; 153 154 /* 155 * Software timer control register 156 */ 157 #define NGE_SWTR_CNTL 0x008 158 typedef union _nge_swtr_cntl { 159 uint8_t ctrl_val; 160 struct { 161 uint8_t stren:1; 162 uint8_t sten:1; 163 uint8_t resv2_7:6; 164 } cntl_bits; 165 } nge_swtr_cntl; 166 167 /* 168 * Software Timer Interval 169 */ 170 #define NGE_SWTR_ITC 0x00c 171 172 /* Default timer interval, 97 would mean 1 ms */ 173 #define SWTR_ITC 0x8 174 typedef union _nge_itc { 175 uint32_t itc_val; 176 struct { 177 uint32_t sw_intv:16; 178 uint32_t sw_cur_val:16; 179 } itc_bits; 180 } nge_itc; 181 182 /* 183 * Fatal error register 184 */ 185 #define NGE_REG010 0x010 186 typedef union _nge_reg010 { 187 uint32_t reg010_val; 188 struct { 189 uint32_t resv0:1; 190 uint32_t resv1:1; 191 uint32_t resv2:1; 192 uint32_t resv3:1; 193 uint32_t resv4:1; 194 uint32_t resv5:1; 195 uint32_t resv6:1; 196 uint32_t resv7:1; 197 uint32_t resv8:1; 198 uint32_t resv9:1; 199 uint32_t resv10:1; 200 uint32_t resv11_31:21; 201 } reg010_bits; 202 } nge_reg010; 203 204 /* 205 * MSI vector map register 0 206 */ 207 #define NGE_MSI_MAP0 0x020 208 typedef union _nge_msi_map0_vec { 209 uint32_t msi_map0_val; 210 struct { 211 uint32_t reint_vec:4; 212 uint32_t rcint_vec:4; 213 uint32_t miss_vec:4; 214 uint32_t teint_vec:4; 215 uint32_t tcint_vec:4; 216 uint32_t stint_vec:4; 217 uint32_t mint_vec:4; 218 uint32_t rfint_vec:4; 219 } vecs_bits; 220 } nge_msi_map0_vec; 221 222 /* 223 * MSI vector map register 1 224 */ 225 #define NGE_MSI_MAP1 0x024 226 typedef union _nge_msi_map1_vec { 227 uint32_t msi_map1_val; 228 struct { 229 uint32_t tfint_vec:4; 230 uint32_t feint_vec:4; 231 uint32_t resv8_11:4; 232 uint32_t resv12_15:4; 233 uint32_t resv16_19:4; 234 uint32_t resv20_23:4; 235 uint32_t resv24_31:8; 236 } vecs_bits; 237 } nge_msi_map1_vec; 238 239 240 /* 241 * MSI vector map register 2 242 */ 243 #define NGE_MSI_MAP2 0x028 244 245 /* 246 * MSI vector map register 2 247 */ 248 #define NGE_MSI_MAP3 0x02c 249 250 /* 251 * MSI mask register for mcp55 252 */ 253 #define NGE_MSI_MASK 0x30 254 typedef union _nge_msi_mask { 255 uint32_t msi_mask_val; 256 struct { 257 uint32_t vec0:1; 258 uint32_t vec1:1; 259 uint32_t vec2:1; 260 uint32_t vec3:1; 261 uint32_t vec4:1; 262 uint32_t vec5:1; 263 uint32_t vec6:1; 264 uint32_t vec7:1; 265 uint32_t resv8_31:24; 266 }msi_msk_bits; 267 }nge_msi_mask; 268 269 /* 270 * Software misc register for mcp51 271 */ 272 #define NGE_SOFT_MISC 0x034 273 typedef union _nge_soft_misc { 274 uint32_t misc_val; 275 struct { 276 uint32_t rx_clk_vx_rst:1; 277 uint32_t tx_clk_vx_rst:1; 278 uint32_t clk12m_vx_rst:1; 279 uint32_t fpci_clk_vx_rst:1; 280 uint32_t rx_clk_vc_rst:1; 281 uint32_t tx_clk_vc_rst:1; 282 uint32_t fs_clk_vc_rst:1; 283 uint32_t rst_ex_m2pintf:1; 284 uint32_t resv8_31:24; 285 } misc_bits; 286 } nge_soft_misc; 287 288 /* 289 * DMA configuration 290 */ 291 #define NGE_DMA_CFG 0x040 292 typedef union _nge_dma_cfg { 293 uint32_t cfg_val; 294 struct { 295 uint32_t tx_start_pri:3; 296 uint32_t tx_start_pri_flag:1; 297 uint32_t tx_prd_rpri:3; 298 uint32_t tx_prd_rpri_flag:1; 299 uint32_t tx_prd_wpri:3; 300 uint32_t tx_prd_wpri_flag:1; 301 uint32_t rx_start_pri:3; 302 uint32_t rx_start_pri_flag:1; 303 uint32_t rx_prd_rpri:3; 304 uint32_t rx_prd_rpri_flag:1; 305 uint32_t rx_prd_wpri:3; 306 uint32_t rx_prd_wpri_flag:1; 307 uint32_t dma_max_pri:3; 308 uint32_t dma_wrr_disable:1; 309 uint32_t dma_pri_disable:1; 310 } cfg_bits; 311 } nge_dma_cfg; 312 313 /* 314 * Request DMA configuration 315 */ 316 #define NGE_DMA_RCFG 0x044 317 typedef union _nge_dma_rcfg { 318 uint32_t dma_rcfg_val; 319 struct { 320 uint32_t tx_prd_coh_state:2; 321 uint32_t tx_data_coh_state:2; 322 uint32_t rx_prd_coh_state:2; 323 uint32_t rx_data_coh_state:2; 324 uint32_t max_roffset:5; 325 uint32_t resv13_31:19; 326 } rcfg_bis; 327 } nge_dma_rcfg; 328 329 /* 330 * Hot DMA configuration 331 */ 332 #define NGE_DMA_HOT_CFG 0x048 333 typedef union _nge_dma_hcfg { 334 uint32_t dma_hcfg_val; 335 struct { 336 uint32_t resv0_3:4; 337 uint32_t noti_wstart_pri:3; 338 uint32_t noti_wstart_pri_flag:1; 339 uint32_t cmd_rstart_pri:3; 340 uint32_t cmd_rstart_pri_flag:1; 341 uint32_t cmd_wstart_pri:3; 342 uint32_t cmd_wstart_pri_flag:1; 343 uint32_t resv16_31:16; 344 } hcfg_bits; 345 } nge_dma_hcfg; 346 347 /* 348 * PMU control register 0 for mcp51 349 */ 350 #define NGE_PMU_CNTL0 0x060 351 #define NGE_PMU_CORE_SPD10_BUSY 0x8 352 #define NGE_PMU_CORE_SPD10_IDLE 0xB 353 #define NGE_PMU_CORE_SPD100_BUSY 0x4 354 #define NGE_PMU_CORE_SPD100_IDLE 0x7 355 #define NGE_PMU_CORE_SPD1000_BUSY 0x0 356 #define NGE_PMU_CORE_SPD1000_IDLE 0x3 357 358 typedef union _nge_pmu_cntl0 { 359 uint32_t cntl0_val; 360 struct { 361 uint32_t core_spd10_fp:4; 362 uint32_t core_spd10_idle:4; 363 uint32_t core_spd100_fp:4; 364 uint32_t core_spd100_idle:4; 365 uint32_t core_spd1000_fp:4; 366 uint32_t core_spd1000_idle:4; 367 uint32_t core_sts_cur:8; 368 } cntl0_bits; 369 } nge_pmu_cntl0; 370 371 /* 372 * PMU control register 1 for mcp51 373 */ 374 #define NGE_PMU_CNTL1 0x064 375 typedef union _nge_pmu_cntl1 { 376 uint32_t cntl1_val; 377 struct { 378 uint32_t dev_fp:4; 379 uint32_t dev_idle:4; 380 uint32_t resv8_27:20; 381 uint32_t dev_sts_cur:4; 382 } cntl1_bits; 383 } nge_pmu_cntl1; 384 385 /* 386 * PMU control register 2 for mcp51 387 */ 388 #define NGE_PMU_CNTL2 0x068 389 typedef union _nge_pmu_cntl2 { 390 uint32_t cntl2_val; 391 struct { 392 uint32_t core_override:4; 393 uint32_t resv4_7:4; 394 uint32_t dev_override:4; 395 uint32_t resv12_15:4; 396 uint32_t core_override_en:1; 397 uint32_t dev_override_en:1; 398 uint32_t core_enable:1; 399 uint32_t dev_enable:1; 400 uint32_t rx_wake_dis:1; 401 uint32_t cidle_timer:1; 402 uint32_t didle_timer:1; 403 uint32_t resv23_31:9; 404 } cntl2_bits; 405 } nge_pmu_cntl2; 406 407 /* 408 * PMU core idle limit register for mcp51 409 */ 410 #define NGE_PMU_CIDLE_LIMIT 0x06c 411 #define NGE_PMU_CIDLE_LIMIT_DEF 0xffff 412 413 /* 414 * PMU device idle limit register for mcp51 415 */ 416 #define NGE_PMU_DIDLE_LIMIT 0x070 417 #define NGE_PMU_DIDLE_LIMIT_DEF 0xffff 418 419 /* 420 * PMU core idle count value register for mcp51 421 */ 422 #define NGE_PMU_CIDLE_COUNT 0x074 423 #define NGE_PMU_CIDEL_COUNT_DEF 0xffff 424 425 /* 426 * PMU device idle count value register for mcp51 427 */ 428 #define NGE_PMU_DIDLE_COUNT 0x078 429 #define NGE_PMU_DIDEL_COUNT_DEF 0xffff 430 431 /* 432 * Transmit control 433 */ 434 #define NGE_TX_CNTL 0x080 435 typedef union _nge_tx_cntl { 436 uint32_t cntl_val; 437 struct { 438 uint32_t paen:1; /* only for mcp55, otherwise reserve */ 439 uint32_t resv1:1; 440 uint32_t retry_en:1; 441 uint32_t pad_en:1; 442 uint32_t fappend_en:1; 443 uint32_t two_def_en:1; 444 uint32_t resv6_7:2; 445 uint32_t max_retry:4; 446 uint32_t burst_en:1; 447 uint32_t resv13_15:3; 448 uint32_t retry_emask:1; 449 uint32_t exdef_mask:1; 450 uint32_t def_mask:1; 451 uint32_t lcar_mask:1; 452 uint32_t tlcol_mask:1; 453 uint32_t uflo_err_mask:1; 454 uint32_t resv22_23:2; 455 uint32_t jam_seq_en:1; 456 uint32_t resv25_31:7; 457 } cntl_bits; 458 } nge_tx_cntl; 459 460 /* 461 * Transmit enable 462 * Note: for ck804 or mcp51, this is 8-bit register; 463 * for mcp55, it is a 32-bit register. 464 */ 465 #define NGE_TX_EN 0x084 466 typedef union _nge_tx_en { 467 uint8_t val; 468 struct { 469 uint8_t tx_en:1; 470 uint8_t resv1_7:7; 471 } bits; 472 } nge_tx_en; 473 474 /* 475 * Transmit status 476 */ 477 #define NGE_TX_STA 0x088 478 typedef union _nge_tx_sta { 479 uint32_t sta_val; 480 struct { 481 uint32_t tx_chan_sta:1; 482 uint32_t resv1_15:15; 483 uint32_t retry_err:1; 484 uint32_t exdef:1; 485 uint32_t def:1; 486 uint32_t lcar:1; 487 uint32_t tlcol:1; 488 uint32_t uflo:1; 489 uint32_t resv22_31:10; 490 } sta_bits; 491 } nge_tx_sta; 492 493 /* 494 * Receive control 495 */ 496 #define NGE_RX_CNTL0 0x08c 497 typedef union _nge_rx_cntrl0 { 498 uint32_t cntl_val; 499 struct { 500 uint32_t resv0:1; 501 uint32_t padsen:1; 502 uint32_t fcsren:1; 503 uint32_t paen:1; 504 uint32_t lben:1; 505 uint32_t afen:1; 506 uint32_t runten:1; 507 uint32_t brdis:1; 508 uint32_t rdfen:1; 509 uint32_t slfb:1; 510 uint32_t resv10_15:6; 511 uint32_t runtm:1; 512 uint32_t rlcolm:1; 513 uint32_t maxerm:1; 514 uint32_t lferm:1; 515 uint32_t crcm:1; 516 uint32_t ofolm:1; 517 uint32_t framerm:1; 518 uint32_t resv23_31:9; 519 } cntl_bits; 520 } nge_rx_cntrl0; 521 522 /* 523 * Maximum receive Frame size 524 */ 525 #define NGE_RX_CNTL1 0x090 526 typedef union _nge_rx_cntl1 { 527 uint32_t cntl_val; 528 struct { 529 uint32_t length:14; 530 uint32_t resv14_31:18; 531 } cntl_bits; 532 } nge_rx_cntl1; 533 534 /* 535 * Receive enable register 536 * Note: for ck804 and mcp51, this is a 8-bit register; 537 * for mcp55, it is a 32-bit register. 538 */ 539 #define NGE_RX_EN 0x094 540 typedef union _nge_rx_en { 541 uint8_t val; 542 struct { 543 uint8_t rx_en:1; 544 uint8_t resv1_7:7; 545 } bits; 546 } nge_rx_en; 547 548 /* 549 * Receive status register 550 */ 551 #define NGE_RX_STA 0x098 552 typedef union _nge_rx_sta { 553 uint32_t sta_val; 554 struct { 555 uint32_t rx_chan_sta:1; 556 uint32_t resv1_15:15; 557 uint32_t runt_sta:1; 558 uint32_t rlcol_sta:1; 559 uint32_t mlen_err:1; 560 uint32_t lf_err:1; 561 uint32_t crc_err:1; 562 uint32_t ofol_err:1; 563 uint32_t fram_err:1; 564 uint32_t resv23_31:9; 565 } sta_bits; 566 } nge_rx_sta; 567 568 /* 569 * Backoff Control 570 */ 571 #define NGE_BKOFF_CNTL 0x09c 572 #define BKOFF_RSEED 0x8 573 #define BKOFF_SLIM_GMII 0x3ff 574 #define BKOFF_SLIM_MII 0x7f 575 typedef union _nge_bkoff_cntl { 576 uint32_t cntl_val; 577 struct { 578 uint32_t rseed:8; 579 uint32_t sltm:10; 580 uint32_t resv18_30:13; 581 uint32_t leg_bk_en:1; 582 } bkoff_bits; 583 } nge_bkoff_cntl; 584 585 /* 586 * Transmit defferral timing 587 */ 588 #define NGE_TX_DEF 0x0a0 589 #define TX_TIFG_MII 0x15 590 #define TX_IFG_RGMII_1000_FD 0x14 591 #define TX_IFG_RGMII_OTHER 0x16 592 #define TX_IFG2_MII 0x5 593 #define TX_IFG2_RGMII_10_100 0x7 594 #define TX_IFG2_RGMII_1000 0x5 595 #define TX_IFG2_DEFAULT 0X0 596 #define TX_IFG1_DEFAULT 0xf 597 typedef union _nge_tx_def { 598 uint32_t def_val; 599 struct { 600 uint32_t ifg1_def:8; 601 uint32_t ifg2_def:8; 602 uint32_t if_def:8; 603 uint32_t resv24_31:8; 604 } def_bits; 605 } nge_tx_def; 606 607 /* 608 * Receive defferral timing 609 */ 610 #define NGE_RX_DEf 0x0a4 611 #define RX_DEF_DEFAULT 0x16 612 typedef union _nge_rx_def { 613 uint8_t def_val; 614 struct { 615 uint8_t rifg; 616 } def_bits; 617 } nge_rx_def; 618 619 /* 620 * Low 32 bit unicast address 621 */ 622 #define NGE_UNI_ADDR0 0x0a8 623 union { 624 uint32_t addr_val; 625 struct { 626 uint32_t addr; 627 } addr_bits; 628 } nge_uni_addr0; 629 630 /* 631 * High 32 bit unicast address 632 */ 633 #define NGE_UNI_ADDR1 0x0ac 634 typedef union _nge_uni_addr1 { 635 uint32_t addr_val; 636 struct { 637 uint32_t addr:16; 638 uint32_t resv16_31:16; 639 } addr_bits; 640 } nge_uni_addr1; 641 642 #define LOW_24BITS_MASK 0xffffffULL 643 #define REVERSE_MAC_ELITE 0x211900ULL 644 #define REVERSE_MAC_GIGABYTE 0xe61600ULL 645 #define REVERSE_MAC_ASUS 0x601d00ULL 646 647 /* 648 * Low 32 bit multicast address 649 */ 650 #define NGE_MUL_ADDR0 0x0b0 651 union { 652 uint32_t addr_val; 653 struct { 654 uint32_t addr; 655 }addr_bits; 656 }nge_mul_addr0; 657 658 /* 659 * High 32 bit multicast address 660 */ 661 #define NGE_MUL_ADDR1 0x0b4 662 typedef union _nge_mul_addr1 { 663 uint32_t addr_val; 664 struct { 665 uint32_t addr:16; 666 uint32_t resv16_31:16; 667 }addr_bits; 668 }nge_mul_addr1; 669 670 /* 671 * Low 32 bit multicast mask 672 */ 673 #define NGE_MUL_MASK 0x0b8 674 union { 675 uint32_t mask_val; 676 struct { 677 uint32_t mask; 678 } mask_bits; 679 } nge_mul_mask0; 680 681 /* 682 * High 32 bit multicast mask 683 */ 684 #define NGE_MUL_MASK1 0x0bc 685 union { 686 uint32_t mask_val; 687 struct { 688 uint32_t mask:16; 689 uint32_t resv16_31:16; 690 } mask_bits; 691 } nge_mul_mask1; 692 693 /* 694 * Mac-to Phy Interface 695 */ 696 #define NGE_MAC2PHY 0x0c0 697 #define low_speed 0x0 698 #define fast_speed 0x1 699 #define giga_speed 0x2 700 #define err_speed 0x4 701 #define MII_IN 0x0 702 #define RGMII_IN 0x1 703 #define ERR_IN1 0x3 704 #define ERR_IN2 0x4 705 typedef union _nge_mac2phy { 706 uint32_t m2p_val; 707 struct { 708 uint32_t speed:2; 709 uint32_t resv2_7:6; 710 uint32_t hdup_en:1; 711 uint32_t resv9:1; 712 uint32_t phyintr:1; /* for mcp55 only */ 713 uint32_t phyintrlvl:1; /* for mcp55 only */ 714 uint32_t resv12_27:16; 715 uint32_t in_type:2; 716 uint32_t resv30_31:2; 717 } m2p_bits; 718 } nge_mac2phy; 719 720 /* 721 * Transmit Descriptor Ring address 722 */ 723 #define NGE_TX_DADR 0x100 724 typedef union _nge_tx_addr { 725 uint32_t addr_val; 726 struct { 727 uint32_t resv0_2:3; 728 uint32_t addr:29; 729 } addr_bits; 730 } nge_tx_addr; 731 732 /* 733 * Receive Descriptor Ring address 734 */ 735 #define NGE_RX_DADR 0x104 736 typedef union _nge_rx_addr { 737 uint32_t addr_val; 738 struct { 739 uint32_t resv0_2:3; 740 uint32_t addr:29; 741 } addr_bits; 742 } nge_rx_addr; 743 744 /* 745 * Rx/tx descriptor ring leng 746 * Note: for mcp55, tdlen/rdlen are 14 bit. 747 */ 748 #define NGE_RXTX_DLEN 0x108 749 typedef union _nge_rxtx_dlen { 750 uint32_t dlen_val; 751 struct { 752 uint32_t tdlen:14; 753 uint32_t resv14_15:2; 754 uint32_t rdlen:14; 755 uint32_t resv30_31:2; 756 } dlen_bits; 757 } nge_rxtx_dlen; 758 759 /* 760 * Transmit polling register 761 */ 762 #define NGE_TX_POLL 0x10c 763 #define TX_POLL_INTV_1G 10 764 #define TX_POLL_INTV_100M 100 765 #define TX_POLL_INTV_10M 1000 766 767 typedef union _nge_tx_poll { 768 uint32_t poll_val; 769 struct { 770 uint32_t tpi:16; 771 uint32_t tpen:1; 772 uint32_t resv17_31:15; 773 } poll_bits; 774 } nge_tx_poll; 775 776 /* 777 * Receive polling register 778 */ 779 #define NGE_RX_POLL 0x110 780 #define RX_POLL_INTV_1G 10 781 #define RX_POLL_INTV_100M 100 782 #define RX_POLL_INTV_10M 1000 783 typedef union _nge_rx_poll { 784 uint32_t poll_val; 785 struct { 786 uint32_t rpi:16; 787 uint32_t rpen:1; 788 uint32_t resv17_31:15; 789 } poll_bits; 790 } nge_rx_poll; 791 792 /* 793 * Transmit polling count 794 */ 795 #define NGE_TX_PCNT 0x114 796 union { 797 uint32_t cnt_val; 798 struct { 799 uint32_t pcnt:32; 800 } cnt_bits; 801 } nge_tx_pcnt; 802 803 /* 804 * Receive polling count 805 */ 806 #define NGE_RX_PCNT 0x118 807 union { 808 uint32_t cnt_val; 809 struct { 810 uint32_t pcnt:32; 811 } cnt_bits; 812 } nge_rx_pcnt; 813 814 815 /* 816 * Current tx's descriptor address 817 */ 818 #define NGE_TX_CUR_DADR 0x11c 819 union { 820 uint32_t addr_val; 821 struct { 822 uint32_t resv0_2:3; 823 uint32_t addr:29; 824 } addr_bits; 825 } nge_tx_cur_addr; 826 827 /* 828 * Current rx's descriptor address 829 */ 830 #define NGE_RX_CUR_DADR 0x120 831 union { 832 uint32_t addr_val; 833 struct { 834 uint32_t resv0_2:3; 835 uint32_t addr:29; 836 } addr_bits; 837 } nge_rx_cur_addr; 838 839 /* 840 * Current tx's data buffer address 841 */ 842 #define NGE_TX_CUR_PRD0 0x124 843 union { 844 uint32_t prd0_val; 845 struct { 846 uint32_t prd0:32; 847 } prd0_bits; 848 } nge_tx_cur_prd0; 849 850 /* 851 * Current tx's data buffer status 852 */ 853 #define NGE_TX_CUR_PRD1 0x128 854 union { 855 uint32_t prd1_val; 856 struct { 857 uint32_t rebytes:16; 858 uint32_t status:16; 859 } prd1_bits; 860 } nge_tx_cur_prd1; 861 862 /* 863 * Current rx's data buffer address 864 */ 865 #define NGE_RX_CUR_PRD0 0x12c 866 union { 867 uint32_t prd0_val; 868 struct { 869 uint32_t prd0:32; 870 }prd0_bits; 871 }nge_rx_cur_prd0; 872 873 /* 874 * Current rx's data buffer status 875 */ 876 #define NGE_RX_CUR_PRD1 0x130 877 878 /* 879 * Next tx's descriptor address 880 */ 881 #define NGE_TX_NXT_DADR 0x134 882 union { 883 uint32_t dadr_val; 884 struct { 885 uint32_t addr:32; 886 }addr_bits; 887 }nge_tx_nxt_dadr; 888 889 /* 890 * Next rx's descriptor address 891 */ 892 #define NGE_RX_NXT_DADR 0x138 893 union { 894 uint32_t dadr_val; 895 struct { 896 uint32_t addr:32; 897 } addr_bits; 898 } nge_rx_nxt_dadr; 899 900 /* 901 * Transmit fifo watermark 902 */ 903 #define NGE_TX_FIFO_WM 0x13c 904 #define TX_FIFO_TBFW 0 905 #define TX_FIFO_NOB_WM_MII 1 906 #define TX_FIFO_NOB_WM_GMII 8 907 #define TX_FIFO_DATA_LWM 0x20 908 #define TX_FIFO_PRD_LWM 0x8 909 #define TX_FIFO_PRD_HWM 0x38 910 typedef union _nge_tx_fifo_wm { 911 uint32_t wm_val; 912 struct { 913 uint32_t data_lwm:9; 914 uint32_t resv8_11:3; 915 uint32_t prd_lwm:6; 916 uint32_t uprd_hwm:6; 917 uint32_t nbfb_wm:4; 918 uint32_t fb_wm:4; 919 } wm_bits; 920 } nge_tx_fifo_wm; 921 922 /* 923 * Receive fifo watermark 924 */ 925 #define NGE_RX_FIFO_WM 0x140 926 typedef union _nge_rx_fifo_wm { 927 uint32_t wm_val; 928 struct { 929 uint32_t data_hwm:9; 930 uint32_t resv9_11:3; 931 uint32_t prd_lwm:4; 932 uint32_t resv16_17:2; 933 uint32_t prd_hwm:4; 934 uint32_t resv22_31:10; 935 } wm_bits; 936 } nge_rx_fifo_wm; 937 938 /* 939 * Chip mode control 940 */ 941 #define NGE_MODE_CNTL 0x144 942 #define DESC_MCP1 0x0 943 #define DESC_OFFLOAD 0x1 944 #define DESC_HOT 0x2 945 #define DESC_RESV 0x3 946 #define MACHINE_BUSY 0x0 947 #define MACHINE_IDLE 0x1 948 typedef union _nge_mode_cntl { 949 uint32_t mode_val; 950 struct { 951 uint32_t txdm:1; 952 uint32_t rxdm:1; 953 uint32_t dma_dis:1; 954 uint32_t dma_status:1; 955 uint32_t bm_reset:1; 956 uint32_t resv5:1; 957 uint32_t vlan_strip:1; /* mcp55 chip only */ 958 uint32_t vlan_ins:1; /* mcp55 chip only */ 959 uint32_t desc_type:2; 960 uint32_t rx_sum_en:1; 961 uint32_t tx_prd_cu_en:1; 962 uint32_t w64_dis:1; 963 uint32_t tx_rcom_en:1; 964 uint32_t rx_filter_en:1; 965 uint32_t resv15:1; 966 uint32_t resv16:1; /* ck804 and mcp51 only */ 967 uint32_t resv17:1; /* ck804 and mcp51 only */ 968 uint32_t resv18:1; /* ck804 and mcp51 only */ 969 uint32_t resv19_21:3; 970 uint32_t tx_fetch_prd:1; /* mcp51/mcp55 only */ 971 uint32_t rx_fetch_prd:1; /* mcp51/mcp55 only */ 972 uint32_t resv24_29:6; 973 uint32_t rx_status:1; 974 uint32_t tx_status:1; 975 } mode_bits; 976 } nge_mode_cntl; 977 978 #define NGE_TX_DADR_HI 0x148 979 #define NGE_RX_DADR_HI 0x14c 980 981 /* 982 * Mii interrupt register 983 * Note: for mcp55, this is a 32-bit register. 984 */ 985 #define NGE_MINTR_SRC 0x180 986 typedef union _nge_mintr_src { 987 uint8_t src_val; 988 struct { 989 uint8_t mrei:1; 990 uint8_t mcc2:1; 991 uint8_t mcc1:1; 992 uint8_t mapi:1; 993 uint8_t mpdi:1; 994 uint8_t resv5_7:3; 995 } src_bits; 996 } nge_mintr_src; 997 998 /* 999 * Mii interrupt mask 1000 * Note: for mcp55, this is a 32-bit register. 1001 */ 1002 #define NGE_MINTR_MASK 0x184 1003 typedef union _nge_mintr_mask { 1004 uint8_t mask_val; 1005 struct { 1006 uint8_t mrei:1; 1007 uint8_t mcc2:1; 1008 uint8_t mcc1:1; 1009 uint8_t mapi:1; 1010 uint8_t mpdi:1; 1011 uint8_t resv5_7:3; 1012 } mask_bits; 1013 } nge_mintr_mask; 1014 1015 /* 1016 * Mii control and status 1017 */ 1018 #define NGE_MII_CS 0x188 1019 #define MII_POLL_INTV 0x4 1020 typedef union _nge_mii_cs { 1021 uint32_t cs_val; 1022 struct { 1023 uint32_t excap:1; 1024 uint32_t jab_dec:1; 1025 uint32_t lk_up:1; 1026 uint32_t ana_cap:1; 1027 uint32_t rfault:1; 1028 uint32_t auto_neg:1; 1029 uint32_t mfps:1; 1030 uint32_t resv7:1; 1031 uint32_t exst:1; 1032 uint32_t hdup_100m_t2:1; 1033 uint32_t fdup_100m_t2:1; 1034 uint32_t hdup_10m:1; 1035 uint32_t fdup_10m:1; 1036 uint32_t hdup_100m_x:1; 1037 uint32_t fdup_100m_x:1; 1038 uint32_t cap_100m_t4:1; 1039 uint32_t ap_intv:4; 1040 uint32_t ap_en:1; 1041 uint32_t resv21_23:3; 1042 uint32_t ap_paddr:5; 1043 uint32_t resv29_31:3; 1044 } cs_bits; 1045 } nge_mii_cs; 1046 1047 /* 1048 * Mii Clock timer register 1049 */ 1050 #define NGE_MII_TM 0x18c 1051 typedef union _nge_mii_tm { 1052 uint16_t tm_val; 1053 struct { 1054 uint16_t timer_interv:8; 1055 uint16_t timer_en:1; 1056 uint16_t resv9_14:6; 1057 uint16_t timer_status:1; 1058 } tm_bits; 1059 } nge_mii_tm; 1060 1061 /* 1062 * Mdio address 1063 */ 1064 #define NGE_MDIO_ADR 0x190 1065 typedef union _nge_mdio_adr { 1066 uint16_t adr_val; 1067 struct { 1068 uint16_t phy_reg:5; 1069 uint16_t phy_adr:5; 1070 uint16_t mdio_rw:1; 1071 uint16_t resv11_14:4; 1072 uint16_t mdio_clc:1; 1073 } adr_bits; 1074 } nge_mdio_adr; 1075 1076 /* 1077 * Mdio data 1078 */ 1079 #define NGE_MDIO_DATA 0x194 1080 1081 /* 1082 * Power Management and Control 1083 */ 1084 #define NGE_PM_CNTL 0x200 1085 typedef union _nge_pm_cntl { 1086 uint32_t cntl_val; 1087 struct { 1088 /* 1089 * mp_en: Magic Packet Enable 1090 * pm_en: Pattern Match Enable 1091 * lc_en: Link Change Enable 1092 */ 1093 uint32_t mp_en_d0:1; 1094 uint32_t pm_en_d0:1; 1095 uint32_t lc_en_d0:1; 1096 uint32_t resv3:1; 1097 uint32_t mp_en_d1:1; 1098 uint32_t pm_en_d1:1; 1099 uint32_t lc_en_d1:1; 1100 uint32_t resv7:1; 1101 uint32_t mp_en_d2:1; 1102 uint32_t pm_en_d2:1; 1103 uint32_t lc_en_d2:1; 1104 uint32_t resv11:1; 1105 uint32_t mp_en_d3:1; 1106 uint32_t pm_en_d3:1; 1107 uint32_t lc_en_d3:1; 1108 uint32_t resv15:1; 1109 uint32_t pat_match_en:5; 1110 uint32_t resv21_23:3; 1111 uint32_t pat_match_stat:5; 1112 uint32_t magic_status:1; 1113 uint32_t netman_status:1; 1114 uint32_t resv31:1; 1115 } cntl_bits; 1116 } nge_pm_cntl; 1117 1118 #define NGE_MPT_CRC0 0x204 1119 #define NGE_PMC_MK00 0x208 1120 #define NGE_PMC_MK01 0x20C 1121 #define NGE_PMC_MK02 0x210 1122 #define NGE_PMC_MK03 0x214 1123 #define NGE_MPT_CRC1 0x218 1124 #define NGE_PMC_MK10 0x21c 1125 #define NGE_PMC_MK11 0x220 1126 #define NGE_PMC_MK12 0x224 1127 #define NGE_PMC_MK13 0x228 1128 #define NGE_MPT_CRC2 0x22c 1129 #define NGE_PMC_MK20 0x230 1130 #define NGE_PMC_MK21 0x234 1131 #define NGE_PMC_MK22 0x238 1132 #define NGE_PMC_MK23 0x23c 1133 #define NGE_MPT_CRC3 0x240 1134 #define NGE_PMC_MK30 0x244 1135 #define NGE_PMC_MK31 0x248 1136 #define NGE_PMC_MK32 0x24c 1137 #define NGE_PMC_MK33 0x250 1138 #define NGE_MPT_CRC4 0x254 1139 #define NGE_PMC_MK40 0x258 1140 #define NGE_PMC_MK41 0x25c 1141 #define NGE_PMC_MK42 0x260 1142 #define NGE_PMC_MK43 0x264 1143 #define NGE_PMC_ALIAS 0x268 1144 #define NGE_PMCSR_ALIAS 0x26c 1145 1146 /* 1147 * Seeprom control 1148 */ 1149 #define NGE_EP_CNTL 0x500 1150 #define EEPROM_CLKDIV 249 1151 #define EEPROM_WAITCLK 0x7 1152 typedef union _nge_cp_cntl { 1153 uint32_t cntl_val; 1154 struct { 1155 uint32_t clkdiv:8; 1156 uint32_t rom_size:3; 1157 uint32_t resv11:1; 1158 uint32_t word_wid:1; 1159 uint32_t resv13_15:3; 1160 uint32_t wait_slots:4; 1161 uint32_t resv20_31:12; 1162 } cntl_bits; 1163 } nge_cp_cntl; 1164 1165 /* 1166 * Seeprom cmd control 1167 */ 1168 #define NGE_EP_CMD 0x504 1169 #define SEEPROM_CMD_READ 0x0 1170 #define SEEPROM_CMD_WRITE_ENABLE 0x1 1171 #define SEEPROM_CMD_ERASE 0x2 1172 #define SEEPROM_CMD_WRITE 0x3 1173 #define SEEPROM_CMD_ERALSE_ALL 0x4 1174 #define SEEPROM_CMD_WRITE_ALL 0x5 1175 #define SEEPROM_CMD_WRITE_DIS 0x6 1176 #define SEEPROM_READY 0x1 1177 typedef union _nge_ep_cmd { 1178 uint32_t cmd_val; 1179 struct { 1180 uint32_t addr:16; 1181 uint32_t cmd:3; 1182 uint32_t resv19_30:12; 1183 uint32_t sts:1; 1184 } cmd_bits; 1185 } nge_ep_cmd; 1186 1187 /* 1188 * Seeprom data register 1189 */ 1190 #define NGE_EP_DATA 0x508 1191 typedef union _nge_ep_data { 1192 uint32_t data_val; 1193 struct { 1194 uint32_t data:16; 1195 uint32_t resv16_31:16; 1196 } data_bits; 1197 } nge_ep_data; 1198 1199 /* 1200 * Power management control 2nd register (since MCP51) 1201 */ 1202 #define NGE_PM_CNTL2 0x600 1203 typedef union _nge_pm_cntl2 { 1204 uint32_t cntl_val; 1205 struct { 1206 uint32_t phy_coma_set:1; 1207 uint32_t phy_coma_status:1; 1208 uint32_t resv2_3:2; 1209 uint32_t resv4:1; 1210 uint32_t resv5_7:3; 1211 uint32_t resv8_11:4; 1212 uint32_t resv12_15:4; 1213 uint32_t pmt5_en:1; 1214 uint32_t pmt6_en:1; 1215 uint32_t pmt7_en:1; 1216 uint32_t resv19_23:5; 1217 uint32_t pmt5_status:1; 1218 uint32_t pmt6_status:1; 1219 uint32_t pmt7_status:1; 1220 uint32_t resv27_31:5; 1221 } cntl_bits; 1222 } nge_pm_cntl2; 1223 1224 1225 /* 1226 * ASF RAM 0x800-0xfff 1227 */ 1228 1229 /* 1230 * Hardware-defined Statistics Block Offsets 1231 * 1232 * These are given in the manual as addresses in NIC memory, starting 1233 * from the NIC statistics area base address of 0x2000; 1234 */ 1235 1236 #define KS_BASE 0x0280 1237 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint32_t)) 1238 1239 typedef enum { 1240 KS_ifHOutOctets = KS_ADDR(0x0280), 1241 KS_ifHOutZeroRetranCount, 1242 KS_ifHOutOneRetranCount, 1243 KS_ifHOutMoreRetranCount, 1244 KS_ifHOutColCount, 1245 KS_ifHOutFifoovCount, 1246 KS_ifHOutLOCCount, 1247 KS_ifHOutExDecCount, 1248 KS_ifHOutRetryCount, 1249 1250 KS_ifHInFrameErrCount, 1251 KS_ifHInExtraOctErrCount, 1252 KS_ifHInLColErrCount, 1253 KS_ifHInRuntCount, 1254 KS_ifHInOversizeErrCount, 1255 KS_ifHInFovErrCount, 1256 KS_ifHInFCSErrCount, 1257 KS_ifHInAlignErrCount, 1258 KS_ifHInLenErrCount, 1259 KS_ifHInUniPktsCount, 1260 KS_ifHInBroadPksCount, 1261 KS_ifHInMulPksCount, 1262 KS_STATS_SIZE = KS_ADDR(0x2d0) 1263 1264 } nge_stats_offset_t; 1265 1266 /* 1267 * Hardware-defined Statistics Block 1268 * 1269 * Another view of the statistic block, as a array and a structure ... 1270 */ 1271 1272 typedef union { 1273 uint64_t a[KS_STATS_SIZE]; 1274 struct { 1275 uint64_t OutOctets; 1276 uint64_t OutZeroRetranCount; 1277 uint64_t OutOneRetranCount; 1278 uint64_t OutMoreRetranCount; 1279 uint64_t OutColCount; 1280 uint64_t OutFifoovCount; 1281 uint64_t OutLOCCount; 1282 uint64_t OutExDecCount; 1283 uint64_t OutRetryCount; 1284 1285 uint64_t InFrameErrCount; 1286 uint64_t InExtraOctErrCount; 1287 uint64_t InLColErrCount; 1288 uint64_t InRuntCount; 1289 uint64_t InOversizeErrCount; 1290 uint64_t InFovErrCount; 1291 uint64_t InFCSErrCount; 1292 uint64_t InAlignErrCount; 1293 uint64_t InLenErrCount; 1294 uint64_t InUniPktsCount; 1295 uint64_t InBroadPksCount; 1296 uint64_t InMulPksCount; 1297 } s; 1298 } nge_hw_statistics_t; 1299 1300 /* 1301 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1302 */ 1303 1304 #define NGE_PHY_NUMBER 32 1305 #define MII_LP_ASYM_PAUSE 0x0800 1306 #define MII_LP_PAUSE 0x0400 1307 1308 #define MII_100BASE_T4 0x0200 1309 #define MII_100BASET_FD 0x0100 1310 #define MII_100BASET_HD 0x0080 1311 #define MII_10BASET_FD 0x0040 1312 #define MII_10BASET_HD 0x0020 1313 1314 #define MII_ID_MARVELL 0x5043 1315 #define MII_ID_CICADA 0x03f1 1316 #define MII_IDL_MASK 0xfc00 1317 #define MII_AN_LPNXTPG 8 1318 1319 1320 #define MII_IEEE_EXT_STATUS 15 1321 1322 /* 1323 * New bits in the MII_CONTROL register 1324 */ 1325 #define MII_CONTROL_1000MB 0x0040 1326 1327 /* 1328 * New bits in the MII_AN_ADVERT register 1329 */ 1330 #define MII_ABILITY_ASYM_PAUSE 0x0800 1331 #define MII_ABILITY_PAUSE 0x0400 1332 1333 /* 1334 * Values for the <selector> field of the MII_AN_ADVERT register 1335 */ 1336 #define MII_AN_SELECTOR_8023 0x0001 1337 1338 /* 1339 * Bits in the MII_1000BASE_T_CONTROL register 1340 * 1341 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1342 * (otherwise, roles are automatically negotiated). When this bit is set, 1343 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1344 */ 1345 #define MII_1000BASE_T_CONTROL 9 1346 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1347 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1348 #define MII_1000BT_CTL_ADV_FDX 0x0200 1349 #define MII_1000BT_CTL_ADV_HDX 0x0100 1350 1351 /* 1352 * Bits in the MII_1000BASE_T_STATUS register 1353 */ 1354 #define MII_1000BASE_T_STATUS 10 1355 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1356 #define MII_1000BT_STAT_MASTER_MODE 0x4000 1357 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1358 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1359 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1360 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1361 1362 #define MII_CICADA_BYPASS_CONTROL MII_VENDOR(2) 1363 #define CICADA_125MHZ_CLOCK_ENABLE 0x0001 1364 1365 #define MII_CICADA_10BASET_CONTROL MII_VENDOR(6) 1366 #define MII_CICADA_DISABLE_ECHO_MODE 0x2000 1367 1368 #define MII_CICADA_EXT_CONTROL MII_VENDOR(7) 1369 #define MII_CICADA_MODE_SELECT_BITS 0xf000 1370 #define MII_CICADA_MODE_SELECT_RGMII 0x1000 1371 #define MII_CICADA_POWER_SUPPLY_BITS 0x0e00 1372 #define MII_CICADA_POWER_SUPPLY_3_3V 0x0000 1373 #define MII_CICADA_POWER_SUPPLY_2_5V 0x0200 1374 1375 #define MII_CICADA_AUXCTRL_STATUS MII_VENDOR(12) 1376 #define MII_CICADA_PIN_PRORITY_SETTING 0x0004 1377 #define MII_CICADA_PIN_PRORITY_DEFAULT 0x0000 1378 1379 1380 #define NGE_REG_SIZE 0xfff 1381 #define NGE_MII_SIZE 0x20 1382 #define NGE_SEEROM_SIZE 0x800 1383 /* 1384 * Legacy rx's bd which does not support 1385 * any hardware offload 1386 */ 1387 typedef struct _legacy_rx_bd { 1388 uint32_t host_buf_addr; 1389 union { 1390 uint32_t cntl_val; 1391 struct { 1392 uint32_t bcnt:16; 1393 uint32_t end:1; 1394 uint32_t miss:1; 1395 uint32_t extra:1; 1396 uint32_t inten:1; 1397 uint32_t bam:1; 1398 uint32_t mam:1; 1399 uint32_t pam:1; 1400 uint32_t runt:1; 1401 uint32_t lcol:1; 1402 uint32_t max:1; 1403 uint32_t lfer:1; 1404 uint32_t crc:1; 1405 uint32_t ofol:1; 1406 uint32_t fram:1; 1407 uint32_t err:1; 1408 uint32_t own:1; 1409 } cntl_bits; 1410 } cntl_status; 1411 } legacy_rx_bd, *plegacy_rx_bd; 1412 1413 /* 1414 * Stand offload rx's bd which supports hareware checksum 1415 * for tcp/ip 1416 */ 1417 #define CK8G_NO_HSUM 0x0 1418 #define CK8G_TCP_SUM_ERR 0x1 1419 #define CK8G_UDP_SUM_ERR 0x2 1420 #define CK8G_IP_HSUM_ERR 0x3 1421 #define CK8G_IP_HSUM 0x4 1422 #define CK8G_TCP_SUM 0x5 1423 #define CK8G_UDP_SUM 0x6 1424 #define CK8G_RESV 0x7 1425 typedef struct _sum_rx_bd { 1426 uint32_t host_buf_addr; 1427 union { 1428 uint32_t cntl_val; 1429 struct { 1430 uint32_t bcnt:14; 1431 uint32_t resv14_29:16; 1432 uint32_t inten:1; 1433 uint32_t own:1; 1434 } control_bits; 1435 struct { 1436 uint32_t bcnt:14; 1437 uint32_t resv14:1; 1438 uint32_t bam:1; 1439 uint32_t mam:1; 1440 uint32_t pam:1; 1441 uint32_t runt:1; 1442 uint32_t lcol:1; 1443 uint32_t max:1; 1444 uint32_t lfer:1; 1445 uint32_t crc:1; 1446 uint32_t ofol:1; 1447 uint32_t fram:1; 1448 uint32_t extra:1; 1449 uint32_t l3_l4_sum:3; 1450 uint32_t rend:1; 1451 uint32_t err:1; 1452 uint32_t own:1; 1453 } status_bits; 1454 } cntl_status; 1455 } sum_rx_bd, *psum_rx_bd; 1456 /* 1457 * Hot offload rx's bd which support 64bit access and 1458 * full-tcp hardware offload 1459 */ 1460 typedef struct _hot_rx_bd { 1461 uint32_t host_buf_addr_hi; 1462 uint32_t host_buf_addr_lo; 1463 uint32_t sw_tag; 1464 union { 1465 uint32_t cntl_val; 1466 struct { 1467 uint32_t bcnt:14; 1468 uint32_t resv14_29:16; 1469 uint32_t inten:1; 1470 uint32_t own:1; 1471 } control_bits; 1472 1473 struct { 1474 uint32_t bcnt:14; 1475 uint32_t ctmach_rd:1; 1476 uint32_t bam:1; 1477 uint32_t mam:1; 1478 uint32_t pam:1; 1479 uint32_t runt:1; 1480 uint32_t lcol:1; 1481 uint32_t max:1; 1482 uint32_t lfer:1; 1483 uint32_t crc:1; 1484 uint32_t ofol:1; 1485 uint32_t fram:1; 1486 uint32_t extra:1; 1487 uint32_t l3_l4_sum:3; 1488 uint32_t rend:1; 1489 uint32_t err:1; 1490 uint32_t own:1; 1491 } status_bits_legacy; 1492 } cntl_status; 1493 } hot_rx_bd, *phot_rx_bd; 1494 1495 /* 1496 * Legacy tx's bd which does not support 1497 * any hardware offload 1498 */ 1499 typedef struct _legacy_tx_bd { 1500 uint32_t host_buf_addr; 1501 union { 1502 uint32_t cntl_val; 1503 struct { 1504 uint32_t bcnt:16; 1505 uint32_t end:1; 1506 uint32_t resv17_23:7; 1507 uint32_t inten:1; 1508 uint32_t resv25_30:6; 1509 uint32_t own:1; 1510 } control_bits; 1511 1512 struct { 1513 uint32_t bcnt:16; 1514 uint32_t end:1; 1515 uint32_t rtry:1; 1516 uint32_t trc:4; 1517 uint32_t inten:1; 1518 uint32_t exdef:1; 1519 uint32_t def:1; 1520 uint32_t lcar:1; 1521 uint32_t lcol:1; 1522 uint32_t uflo:1; 1523 uint32_t err:1; 1524 uint32_t own:1; 1525 } status_bits; 1526 } cntl_status; 1527 } legacy_tx_bd, *plegacy_tx_bd; 1528 1529 /* 1530 * Stand offload tx's bd which supports hareware checksum 1531 * for tcp/ip 1532 */ 1533 typedef struct _sum_tx_bd { 1534 uint32_t host_buf_addr; 1535 union { 1536 uint32_t cntl_val; 1537 struct { 1538 uint32_t bcnt:14; 1539 uint32_t resv14_25:12; 1540 uint32_t tcp_hsum:1; 1541 uint32_t ip_hsum:1; 1542 uint32_t segen:1; 1543 uint32_t end:1; 1544 uint32_t inten:1; 1545 uint32_t own:1; 1546 } control_sum_bits; 1547 1548 struct { 1549 uint32_t bcnt:14; 1550 uint32_t mss:14; 1551 uint32_t segen:1; 1552 uint32_t end:1; 1553 uint32_t inten:1; 1554 uint32_t own:1; 1555 } control_tso_bits; 1556 1557 struct { 1558 uint32_t bcnt:14; 1559 uint32_t resv14_17:4; 1560 uint32_t rtry:1; 1561 uint32_t trc:4; 1562 uint32_t inten:1; 1563 uint32_t exdef:1; 1564 uint32_t def:1; 1565 uint32_t lcar:1; 1566 uint32_t lcol:1; 1567 uint32_t uflo:1; 1568 uint32_t end:1; 1569 uint32_t err:1; 1570 uint32_t own:1; 1571 } status_bits; 1572 } control_status; 1573 } sum_tx_bd, *psum_tx_bd; 1574 1575 /* 1576 * Hot offload tx's bd which support 64bit access and 1577 * full-tcp hardware offload 1578 */ 1579 1580 typedef struct _hot_tx_bd { 1581 uint32_t host_buf_addr_hi; 1582 uint32_t host_buf_addr_lo; 1583 union { 1584 uint32_t parm_val; 1585 struct { 1586 uint32_t resv0_15:16; 1587 uint32_t resv16:1; 1588 uint32_t resv17:1; 1589 uint32_t resv18_31:14; 1590 } parm_bits; 1591 } hot_parms; 1592 1593 union { 1594 uint32_t cntl_val; 1595 struct { 1596 uint32_t bcnt:14; 1597 uint32_t resv14_25:12; 1598 uint32_t tcp_hsum:1; 1599 uint32_t ip_hsum:1; 1600 uint32_t segen:1; 1601 uint32_t end:1; 1602 uint32_t inten:1; 1603 uint32_t own:1; 1604 } control_sum_bits; 1605 1606 struct { 1607 uint32_t bcnt:14; 1608 uint32_t mss:14; 1609 uint32_t segen:1; 1610 uint32_t end:1; 1611 uint32_t inten:1; 1612 uint32_t own:1; 1613 } control_tso_bits; 1614 1615 struct { 1616 uint32_t bcnt:14; 1617 uint32_t resv14_17:4; 1618 uint32_t rtry:1; 1619 uint32_t trc:4; 1620 uint32_t inten:1; 1621 uint32_t exdef:1; 1622 uint32_t def:1; 1623 uint32_t lcar:1; 1624 uint32_t lcol:1; 1625 uint32_t uflo:1; 1626 uint32_t end:1; 1627 uint32_t err:1; 1628 uint32_t own:1; 1629 } status_bits; 1630 } control_status; 1631 } hot_tx_bd, *phot_tx_bd; 1632 1633 #ifdef __cplusplus 1634 } 1635 #endif 1636 1637 #endif /* _SYS_NGE_CHIP_H */ 1638