1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2018, Joyent, Inc. 29 */ 30 31 #include "nge.h" 32 static uint32_t nge_watchdog_count = 1 << 5; 33 static uint32_t nge_watchdog_check = 1 << 3; 34 extern boolean_t nge_enable_msi; 35 static void nge_sync_mac_modes(nge_t *); 36 37 #undef NGE_DBG 38 #define NGE_DBG NGE_DBG_CHIP 39 40 /* 41 * Operating register get/set access routines 42 */ 43 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno); 44 #pragma inline(nge_reg_get8) 45 46 uint8_t 47 nge_reg_get8(nge_t *ngep, nge_regno_t regno) 48 { 49 NGE_TRACE(("nge_reg_get8($%p, 0x%lx)", (void *)ngep, regno)); 50 51 return (ddi_get8(ngep->io_handle, PIO_ADDR(ngep, regno))); 52 } 53 54 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data); 55 #pragma inline(nge_reg_put8) 56 57 void 58 nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data) 59 { 60 NGE_TRACE(("nge_reg_put8($%p, 0x%lx, 0x%x)", 61 (void *)ngep, regno, data)); 62 ddi_put8(ngep->io_handle, PIO_ADDR(ngep, regno), data); 63 64 } 65 66 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno); 67 #pragma inline(nge_reg_get16) 68 69 uint16_t 70 nge_reg_get16(nge_t *ngep, nge_regno_t regno) 71 { 72 NGE_TRACE(("nge_reg_get16($%p, 0x%lx)", (void *)ngep, regno)); 73 return (ddi_get16(ngep->io_handle, PIO_ADDR(ngep, regno))); 74 } 75 76 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 77 #pragma inline(nge_reg_put16) 78 79 void 80 nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data) 81 { 82 NGE_TRACE(("nge_reg_put16($%p, 0x%lx, 0x%x)", 83 (void *)ngep, regno, data)); 84 ddi_put16(ngep->io_handle, PIO_ADDR(ngep, regno), data); 85 86 } 87 88 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno); 89 #pragma inline(nge_reg_get32) 90 91 uint32_t 92 nge_reg_get32(nge_t *ngep, nge_regno_t regno) 93 { 94 NGE_TRACE(("nge_reg_get32($%p, 0x%lx)", (void *)ngep, regno)); 95 return (ddi_get32(ngep->io_handle, PIO_ADDR(ngep, regno))); 96 } 97 98 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data); 99 #pragma inline(nge_reg_put32) 100 101 void 102 nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data) 103 { 104 NGE_TRACE(("nge_reg_put32($%p, 0x%lx, 0x%x)", 105 (void *)ngep, regno, data)); 106 ddi_put32(ngep->io_handle, PIO_ADDR(ngep, regno), data); 107 108 } 109 110 111 static int nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 112 #pragma no_inline(nge_chip_peek_cfg) 113 114 static int 115 nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 116 { 117 int err; 118 uint64_t regval; 119 uint64_t regno; 120 121 NGE_TRACE(("nge_chip_peek_cfg($%p, $%p)", 122 (void *)ngep, (void *)ppd)); 123 124 err = DDI_SUCCESS; 125 regno = ppd->pp_acc_offset; 126 127 switch (ppd->pp_acc_size) { 128 case 1: 129 regval = pci_config_get8(ngep->cfg_handle, regno); 130 break; 131 132 case 2: 133 regval = pci_config_get16(ngep->cfg_handle, regno); 134 break; 135 136 case 4: 137 regval = pci_config_get32(ngep->cfg_handle, regno); 138 break; 139 140 case 8: 141 regval = pci_config_get64(ngep->cfg_handle, regno); 142 break; 143 } 144 ppd->pp_acc_data = regval; 145 return (err); 146 } 147 148 static int nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 149 150 static int 151 nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 152 { 153 int err; 154 uint64_t regval; 155 uint64_t regno; 156 157 NGE_TRACE(("nge_chip_poke_cfg($%p, $%p)", 158 (void *)ngep, (void *)ppd)); 159 160 err = DDI_SUCCESS; 161 regno = ppd->pp_acc_offset; 162 regval = ppd->pp_acc_data; 163 164 switch (ppd->pp_acc_size) { 165 case 1: 166 pci_config_put8(ngep->cfg_handle, regno, regval); 167 break; 168 169 case 2: 170 pci_config_put16(ngep->cfg_handle, regno, regval); 171 break; 172 173 case 4: 174 pci_config_put32(ngep->cfg_handle, regno, regval); 175 break; 176 177 case 8: 178 pci_config_put64(ngep->cfg_handle, regno, regval); 179 break; 180 } 181 182 return (err); 183 184 } 185 186 static int nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd); 187 188 static int 189 nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd) 190 { 191 int err; 192 uint64_t regval; 193 void *regaddr; 194 195 NGE_TRACE(("nge_chip_peek_reg($%p, $%p)", 196 (void *)ngep, (void *)ppd)); 197 198 err = DDI_SUCCESS; 199 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 200 201 switch (ppd->pp_acc_size) { 202 case 1: 203 regval = ddi_get8(ngep->io_handle, regaddr); 204 break; 205 206 case 2: 207 regval = ddi_get16(ngep->io_handle, regaddr); 208 break; 209 210 case 4: 211 regval = ddi_get32(ngep->io_handle, regaddr); 212 break; 213 214 case 8: 215 regval = ddi_get64(ngep->io_handle, regaddr); 216 break; 217 218 default: 219 regval = 0x0ull; 220 break; 221 } 222 ppd->pp_acc_data = regval; 223 return (err); 224 } 225 226 static int nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd); 227 228 static int 229 nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd) 230 { 231 int err; 232 uint64_t regval; 233 void *regaddr; 234 235 NGE_TRACE(("nge_chip_poke_reg($%p, $%p)", 236 (void *)ngep, (void *)ppd)); 237 238 err = DDI_SUCCESS; 239 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 240 regval = ppd->pp_acc_data; 241 242 switch (ppd->pp_acc_size) { 243 case 1: 244 ddi_put8(ngep->io_handle, regaddr, regval); 245 break; 246 247 case 2: 248 ddi_put16(ngep->io_handle, regaddr, regval); 249 break; 250 251 case 4: 252 ddi_put32(ngep->io_handle, regaddr, regval); 253 break; 254 255 case 8: 256 ddi_put64(ngep->io_handle, regaddr, regval); 257 break; 258 } 259 return (err); 260 } 261 262 static int nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd); 263 #pragma no_inline(nge_chip_peek_mii) 264 265 static int 266 nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd) 267 { 268 int err; 269 270 err = DDI_SUCCESS; 271 ppd->pp_acc_data = nge_mii_get16(ngep, ppd->pp_acc_offset/2); 272 return (err); 273 } 274 275 static int nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd); 276 #pragma no_inline(nge_chip_poke_mii) 277 278 static int 279 nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd) 280 { 281 int err; 282 err = DDI_SUCCESS; 283 nge_mii_put16(ngep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 284 return (err); 285 } 286 287 /* 288 * Basic SEEPROM get/set access routine 289 * 290 * This uses the chip's SEEPROM auto-access method, controlled by the 291 * Serial EEPROM Address/Data Registers at 0x504h, so the CPU 292 * doesn't have to fiddle with the individual bits. 293 * 294 * The caller should hold <genlock> and *also* have already acquired 295 * the right to access the SEEPROM. 296 * 297 * Return value: 298 * 0 on success, 299 * ENODATA on access timeout (maybe retryable: device may just be busy) 300 * EPROTO on other h/w or s/w errors. 301 * 302 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 303 * from a (successful) SEEPROM_ACCESS_READ. 304 */ 305 306 static int 307 nge_seeprom_access(nge_t *ngep, uint32_t cmd, nge_regno_t addr, uint16_t *dp) 308 { 309 uint32_t tries; 310 nge_ep_cmd cmd_reg; 311 nge_ep_data data_reg; 312 313 NGE_TRACE(("nge_seeprom_access($%p, %d, %x, $%p)", 314 (void *)ngep, cmd, addr, (void *)dp)); 315 316 ASSERT(mutex_owned(ngep->genlock)); 317 318 /* 319 * Check there's no command in progress. 320 * 321 * Note: this *shouldn't* ever find that there is a command 322 * in progress, because we already hold the <genlock> mutex. 323 * Also, to ensure we don't have a conflict with the chip's 324 * internal firmware or a process accessing the same (shared) 325 * So this is just a final consistency check: we shouldn't 326 * see EITHER the START bit (command started but not complete) 327 * OR the COMPLETE bit (command completed but not cleared). 328 */ 329 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 330 for (tries = 0; tries < 30; tries++) { 331 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 332 break; 333 drv_usecwait(10); 334 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 335 } 336 337 /* 338 * This should not happen. If so, we have to restart eeprom 339 * state machine 340 */ 341 if (tries == 30) { 342 cmd_reg.cmd_bits.sts = SEEPROM_READY; 343 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 344 drv_usecwait(10); 345 /* 346 * Polling the status bit to make assure the eeprom is ready 347 */ 348 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 349 for (tries = 0; tries < 30; tries++) { 350 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 351 break; 352 drv_usecwait(10); 353 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 354 } 355 } 356 357 /* 358 * Assemble the command ... 359 */ 360 cmd_reg.cmd_bits.addr = (uint32_t)addr; 361 cmd_reg.cmd_bits.cmd = cmd; 362 cmd_reg.cmd_bits.sts = 0; 363 364 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 365 366 /* 367 * Polling whether the access is successful. 368 * 369 */ 370 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 371 for (tries = 0; tries < 30; tries++) { 372 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 373 break; 374 drv_usecwait(10); 375 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 376 } 377 378 if (tries == 30) { 379 nge_report(ngep, NGE_HW_ROM); 380 return (DDI_FAILURE); 381 } 382 switch (cmd) { 383 default: 384 case SEEPROM_CMD_WRITE_ENABLE: 385 case SEEPROM_CMD_ERASE: 386 case SEEPROM_CMD_ERALSE_ALL: 387 case SEEPROM_CMD_WRITE_DIS: 388 break; 389 390 case SEEPROM_CMD_READ: 391 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 392 *dp = data_reg.data_bits.data; 393 break; 394 395 case SEEPROM_CMD_WRITE: 396 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 397 data_reg.data_bits.data = *dp; 398 nge_reg_put32(ngep, NGE_EP_DATA, data_reg.data_val); 399 break; 400 } 401 402 return (DDI_SUCCESS); 403 } 404 405 406 static int 407 nge_chip_peek_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 408 { 409 uint16_t data; 410 int err; 411 412 err = nge_seeprom_access(ngep, SEEPROM_CMD_READ, 413 ppd->pp_acc_offset, &data); 414 ppd->pp_acc_data = data; 415 return (err); 416 } 417 418 static int 419 nge_chip_poke_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 420 { 421 uint16_t data; 422 int err; 423 424 data = ppd->pp_acc_data; 425 err = nge_seeprom_access(ngep, SEEPROM_CMD_WRITE, 426 ppd->pp_acc_offset, &data); 427 return (err); 428 } 429 430 void 431 nge_init_dev_spec_param(nge_t *ngep) 432 { 433 nge_dev_spec_param_t *dev_param_p; 434 chip_info_t *infop; 435 436 dev_param_p = &ngep->dev_spec_param; 437 infop = (chip_info_t *)&ngep->chipinfo; 438 439 switch (infop->device) { 440 case DEVICE_ID_NF3_E6: 441 case DEVICE_ID_NF3_DF: 442 case DEVICE_ID_MCP04_37: 443 case DEVICE_ID_MCP04_38: 444 dev_param_p->msi = B_FALSE; 445 dev_param_p->msi_x = B_FALSE; 446 dev_param_p->vlan = B_FALSE; 447 dev_param_p->advanced_pm = B_FALSE; 448 dev_param_p->mac_addr_order = B_FALSE; 449 dev_param_p->tx_pause_frame = B_FALSE; 450 dev_param_p->rx_pause_frame = B_FALSE; 451 dev_param_p->jumbo = B_FALSE; 452 dev_param_p->tx_rx_64byte = B_FALSE; 453 dev_param_p->rx_hw_checksum = B_FALSE; 454 dev_param_p->tx_hw_checksum = 0; 455 dev_param_p->desc_type = DESC_OFFLOAD; 456 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 457 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 458 dev_param_p->nge_split = NGE_SPLIT_32; 459 break; 460 461 case DEVICE_ID_CK804_56: 462 case DEVICE_ID_CK804_57: 463 dev_param_p->msi = B_TRUE; 464 dev_param_p->msi_x = B_TRUE; 465 dev_param_p->vlan = B_FALSE; 466 dev_param_p->advanced_pm = B_FALSE; 467 dev_param_p->mac_addr_order = B_FALSE; 468 dev_param_p->tx_pause_frame = B_FALSE; 469 dev_param_p->rx_pause_frame = B_TRUE; 470 dev_param_p->jumbo = B_TRUE; 471 dev_param_p->tx_rx_64byte = B_FALSE; 472 dev_param_p->rx_hw_checksum = B_TRUE; 473 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 474 dev_param_p->desc_type = DESC_HOT; 475 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 476 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 477 dev_param_p->nge_split = NGE_SPLIT_96; 478 break; 479 480 case DEVICE_ID_MCP51_268: 481 case DEVICE_ID_MCP51_269: 482 dev_param_p->msi = B_FALSE; 483 dev_param_p->msi_x = B_FALSE; 484 dev_param_p->vlan = B_FALSE; 485 dev_param_p->advanced_pm = B_TRUE; 486 dev_param_p->mac_addr_order = B_FALSE; 487 dev_param_p->tx_pause_frame = B_FALSE; 488 dev_param_p->rx_pause_frame = B_FALSE; 489 dev_param_p->jumbo = B_FALSE; 490 dev_param_p->tx_rx_64byte = B_TRUE; 491 dev_param_p->rx_hw_checksum = B_FALSE; 492 dev_param_p->tx_hw_checksum = 0; 493 dev_param_p->desc_type = DESC_OFFLOAD; 494 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 495 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 496 dev_param_p->nge_split = NGE_SPLIT_32; 497 break; 498 499 case DEVICE_ID_MCP55_372: 500 case DEVICE_ID_MCP55_373: 501 dev_param_p->msi = B_TRUE; 502 dev_param_p->msi_x = B_TRUE; 503 dev_param_p->vlan = B_TRUE; 504 dev_param_p->advanced_pm = B_TRUE; 505 dev_param_p->mac_addr_order = B_FALSE; 506 dev_param_p->tx_pause_frame = B_TRUE; 507 dev_param_p->rx_pause_frame = B_TRUE; 508 dev_param_p->jumbo = B_TRUE; 509 dev_param_p->tx_rx_64byte = B_TRUE; 510 dev_param_p->rx_hw_checksum = B_TRUE; 511 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 512 dev_param_p->desc_type = DESC_HOT; 513 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 514 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 515 dev_param_p->nge_split = NGE_SPLIT_96; 516 break; 517 518 case DEVICE_ID_MCP61_3EE: 519 case DEVICE_ID_MCP61_3EF: 520 dev_param_p->msi = B_FALSE; 521 dev_param_p->msi_x = B_FALSE; 522 dev_param_p->vlan = B_FALSE; 523 dev_param_p->advanced_pm = B_TRUE; 524 dev_param_p->mac_addr_order = B_TRUE; 525 dev_param_p->tx_pause_frame = B_FALSE; 526 dev_param_p->rx_pause_frame = B_FALSE; 527 dev_param_p->jumbo = B_FALSE; 528 dev_param_p->tx_rx_64byte = B_TRUE; 529 dev_param_p->rx_hw_checksum = B_FALSE; 530 dev_param_p->tx_hw_checksum = 0; 531 dev_param_p->desc_type = DESC_OFFLOAD; 532 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 533 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 534 dev_param_p->nge_split = NGE_SPLIT_32; 535 break; 536 537 case DEVICE_ID_MCP77_760: 538 case DEVICE_ID_MCP79_AB0: 539 dev_param_p->msi = B_FALSE; 540 dev_param_p->msi_x = B_FALSE; 541 dev_param_p->vlan = B_FALSE; 542 dev_param_p->advanced_pm = B_TRUE; 543 dev_param_p->mac_addr_order = B_TRUE; 544 dev_param_p->tx_pause_frame = B_FALSE; 545 dev_param_p->rx_pause_frame = B_FALSE; 546 dev_param_p->jumbo = B_FALSE; 547 dev_param_p->tx_rx_64byte = B_TRUE; 548 dev_param_p->rx_hw_checksum = B_FALSE; 549 dev_param_p->tx_hw_checksum = 0; 550 dev_param_p->desc_type = DESC_HOT; 551 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 552 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 553 dev_param_p->nge_split = NGE_SPLIT_32; 554 break; 555 556 default: 557 dev_param_p->msi = B_FALSE; 558 dev_param_p->msi_x = B_FALSE; 559 dev_param_p->vlan = B_FALSE; 560 dev_param_p->advanced_pm = B_FALSE; 561 dev_param_p->mac_addr_order = B_FALSE; 562 dev_param_p->tx_pause_frame = B_FALSE; 563 dev_param_p->rx_pause_frame = B_FALSE; 564 dev_param_p->jumbo = B_FALSE; 565 dev_param_p->tx_rx_64byte = B_FALSE; 566 dev_param_p->rx_hw_checksum = B_FALSE; 567 dev_param_p->tx_hw_checksum = 0; 568 dev_param_p->desc_type = DESC_OFFLOAD; 569 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 570 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 571 dev_param_p->nge_split = NGE_SPLIT_32; 572 return; 573 } 574 } 575 /* 576 * Perform first-stage chip (re-)initialisation, using only config-space 577 * accesses: 578 * 579 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 580 * returning the data in the structure pointed to by <infop>. 581 */ 582 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset); 583 #pragma no_inline(nge_chip_cfg_init) 584 585 void 586 nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset) 587 { 588 uint16_t command; 589 ddi_acc_handle_t handle; 590 nge_interbus_conf interbus_conf; 591 nge_msi_mask_conf msi_mask_conf; 592 nge_msi_map_cap_conf cap_conf; 593 594 NGE_TRACE(("nge_chip_cfg_init($%p, $%p, %d)", 595 (void *)ngep, (void *)infop, reset)); 596 597 /* 598 * save PCI cache line size and subsystem vendor ID 599 * 600 * Read all the config-space registers that characterise the 601 * chip, specifically vendor/device/revision/subsystem vendor 602 * and subsystem device id. We expect (but don't check) that 603 */ 604 handle = ngep->cfg_handle; 605 /* reading the vendor information once */ 606 if (reset == B_FALSE) { 607 infop->command = pci_config_get16(handle, 608 PCI_CONF_COMM); 609 infop->vendor = pci_config_get16(handle, 610 PCI_CONF_VENID); 611 infop->device = pci_config_get16(handle, 612 PCI_CONF_DEVID); 613 infop->subven = pci_config_get16(handle, 614 PCI_CONF_SUBVENID); 615 infop->subdev = pci_config_get16(handle, 616 PCI_CONF_SUBSYSID); 617 infop->class_code = pci_config_get8(handle, 618 PCI_CONF_BASCLASS); 619 infop->revision = pci_config_get8(handle, 620 PCI_CONF_REVID); 621 infop->clsize = pci_config_get8(handle, 622 PCI_CONF_CACHE_LINESZ); 623 infop->latency = pci_config_get8(handle, 624 PCI_CONF_LATENCY_TIMER); 625 } 626 if (nge_enable_msi) { 627 /* Disable the hidden for MSI support */ 628 interbus_conf.conf_val = pci_config_get32(handle, 629 PCI_CONF_HT_INTERNAL); 630 if ((infop->device == DEVICE_ID_MCP55_373) || 631 (infop->device == DEVICE_ID_MCP55_372)) 632 interbus_conf.conf_bits.msix_off = NGE_SET; 633 interbus_conf.conf_bits.msi_off = NGE_CLEAR; 634 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 635 interbus_conf.conf_val); 636 637 if ((infop->device == DEVICE_ID_MCP55_373) || 638 (infop->device == DEVICE_ID_MCP55_372)) { 639 640 /* Disable the vector off for mcp55 */ 641 msi_mask_conf.msi_mask_conf_val = 642 pci_config_get32(handle, PCI_CONF_HT_MSI_MASK); 643 msi_mask_conf.msi_mask_bits.vec0_off = NGE_CLEAR; 644 msi_mask_conf.msi_mask_bits.vec1_off = NGE_CLEAR; 645 msi_mask_conf.msi_mask_bits.vec2_off = NGE_CLEAR; 646 msi_mask_conf.msi_mask_bits.vec3_off = NGE_CLEAR; 647 msi_mask_conf.msi_mask_bits.vec4_off = NGE_CLEAR; 648 msi_mask_conf.msi_mask_bits.vec5_off = NGE_CLEAR; 649 msi_mask_conf.msi_mask_bits.vec6_off = NGE_CLEAR; 650 msi_mask_conf.msi_mask_bits.vec7_off = NGE_CLEAR; 651 pci_config_put32(handle, PCI_CONF_HT_MSI_MASK, 652 msi_mask_conf.msi_mask_conf_val); 653 654 /* Enable the MSI mapping */ 655 cap_conf.msi_map_cap_conf_val = 656 pci_config_get32(handle, PCI_CONF_HT_MSI_MAP_CAP); 657 cap_conf.map_cap_conf_bits.map_en = NGE_SET; 658 pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP, 659 cap_conf.msi_map_cap_conf_val); 660 } 661 } else { 662 interbus_conf.conf_val = pci_config_get32(handle, 663 PCI_CONF_HT_INTERNAL); 664 interbus_conf.conf_bits.msi_off = NGE_SET; 665 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 666 interbus_conf.conf_val); 667 } 668 command = infop->command | PCI_COMM_MAE; 669 command &= ~PCI_COMM_MEMWR_INVAL; 670 command |= PCI_COMM_ME; 671 pci_config_put16(handle, PCI_CONF_COMM, command); 672 pci_config_put16(handle, PCI_CONF_STAT, ~0); 673 674 } 675 676 int 677 nge_chip_stop(nge_t *ngep, boolean_t fault) 678 { 679 int err; 680 uint32_t reg_val; 681 uint32_t tries; 682 nge_mintr_src mintr_src; 683 nge_mii_cs mii_cs; 684 nge_rx_poll rx_poll; 685 nge_tx_poll tx_poll; 686 nge_rx_en rx_en; 687 nge_tx_en tx_en; 688 nge_tx_sta tx_sta; 689 nge_rx_sta rx_sta; 690 nge_mode_cntl mode; 691 nge_pmu_cntl2 pmu_cntl2; 692 693 NGE_TRACE(("nge_chip_stop($%p, %d)", (void *)ngep, fault)); 694 695 err = DDI_SUCCESS; 696 697 /* Clear any pending PHY interrupt */ 698 mintr_src.src_val = nge_reg_get8(ngep, NGE_MINTR_SRC); 699 nge_reg_put8(ngep, NGE_MINTR_SRC, mintr_src.src_val); 700 701 /* Mask all interrupts */ 702 reg_val = nge_reg_get32(ngep, NGE_INTR_MASK); 703 reg_val &= ~NGE_INTR_ALL_EN; 704 nge_reg_put32(ngep, NGE_INTR_MASK, reg_val); 705 706 /* Disable auto-polling of phy */ 707 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 708 mii_cs.cs_bits.ap_en = NGE_CLEAR; 709 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 710 711 /* Reset buffer management & DMA */ 712 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 713 mode.mode_bits.dma_dis = NGE_SET; 714 mode.mode_bits.desc_type = ngep->desc_mode; 715 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 716 717 for (tries = 0; tries < 10000; tries++) { 718 drv_usecwait(10); 719 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 720 if (mode.mode_bits.dma_status == NGE_SET) 721 break; 722 } 723 if (tries == 10000) { 724 ngep->nge_chip_state = NGE_CHIP_ERROR; 725 return (DDI_FAILURE); 726 } 727 728 /* Disable rx's machine */ 729 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 730 rx_en.bits.rx_en = NGE_CLEAR; 731 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 732 733 /* Disable tx's machine */ 734 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 735 tx_en.bits.tx_en = NGE_CLEAR; 736 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 737 738 /* 739 * Clean the status of tx's state machine 740 * and Make assure the tx's channel is idle 741 */ 742 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 743 for (tries = 0; tries < 1000; tries++) { 744 if (tx_sta.sta_bits.tx_chan_sta == NGE_CLEAR) 745 break; 746 drv_usecwait(10); 747 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 748 } 749 if (tries == 1000) { 750 ngep->nge_chip_state = NGE_CHIP_ERROR; 751 return (DDI_FAILURE); 752 } 753 nge_reg_put32(ngep, NGE_TX_STA, tx_sta.sta_val); 754 755 /* 756 * Clean the status of rx's state machine 757 * and Make assure the tx's channel is idle 758 */ 759 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 760 for (tries = 0; tries < 1000; tries++) { 761 if (rx_sta.sta_bits.rx_chan_sta == NGE_CLEAR) 762 break; 763 drv_usecwait(10); 764 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 765 } 766 if (tries == 1000) { 767 ngep->nge_chip_state = NGE_CHIP_ERROR; 768 return (DDI_FAILURE); 769 } 770 nge_reg_put32(ngep, NGE_RX_STA, rx_sta.sta_val); 771 772 /* Disable auto-poll of rx's state machine */ 773 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 774 rx_poll.poll_bits.rpen = NGE_CLEAR; 775 rx_poll.poll_bits.rpi = NGE_CLEAR; 776 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 777 778 /* Disable auto-polling of tx's state machine */ 779 tx_poll.poll_val = nge_reg_get32(ngep, NGE_TX_POLL); 780 tx_poll.poll_bits.tpen = NGE_CLEAR; 781 tx_poll.poll_bits.tpi = NGE_CLEAR; 782 nge_reg_put32(ngep, NGE_TX_POLL, tx_poll.poll_val); 783 784 /* Restore buffer management */ 785 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 786 mode.mode_bits.bm_reset = NGE_SET; 787 mode.mode_bits.tx_rcom_en = NGE_SET; 788 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 789 790 if (ngep->dev_spec_param.advanced_pm) { 791 792 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 0); 793 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 0); 794 795 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 796 pmu_cntl2.cntl2_bits.cidle_timer = NGE_CLEAR; 797 pmu_cntl2.cntl2_bits.didle_timer = NGE_CLEAR; 798 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 799 } 800 if (fault) 801 ngep->nge_chip_state = NGE_CHIP_FAULT; 802 else 803 ngep->nge_chip_state = NGE_CHIP_STOPPED; 804 805 return (err); 806 } 807 808 static void 809 nge_rx_setup(nge_t *ngep) 810 { 811 uint64_t desc_addr; 812 nge_rxtx_dlen dlen; 813 nge_rx_poll rx_poll; 814 815 /* 816 * Filling the address and length of rx's descriptors 817 */ 818 desc_addr = ngep->recv->desc.cookie.dmac_laddress; 819 nge_reg_put32(ngep, NGE_RX_DADR, desc_addr); 820 nge_reg_put32(ngep, NGE_RX_DADR_HI, desc_addr >> 32); 821 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 822 dlen.dlen_bits.rdlen = ngep->recv->desc.nslots - 1; 823 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 824 825 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 826 rx_poll.poll_bits.rpi = RX_POLL_INTV_1G; 827 rx_poll.poll_bits.rpen = NGE_SET; 828 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 829 } 830 831 static void 832 nge_tx_setup(nge_t *ngep) 833 { 834 uint64_t desc_addr; 835 nge_rxtx_dlen dlen; 836 837 /* 838 * Filling the address and length of tx's descriptors 839 */ 840 desc_addr = ngep->send->desc.cookie.dmac_laddress; 841 nge_reg_put32(ngep, NGE_TX_DADR, desc_addr); 842 nge_reg_put32(ngep, NGE_TX_DADR_HI, desc_addr >> 32); 843 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 844 dlen.dlen_bits.tdlen = ngep->send->desc.nslots - 1; 845 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 846 } 847 848 static int 849 nge_buff_setup(nge_t *ngep) 850 { 851 nge_mode_cntl mode_cntl; 852 nge_dev_spec_param_t *dev_param_p; 853 854 dev_param_p = &ngep->dev_spec_param; 855 856 /* 857 * Configure Rx&Tx's buffer 858 */ 859 nge_rx_setup(ngep); 860 nge_tx_setup(ngep); 861 862 /* 863 * Configure buffer attribute 864 */ 865 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 866 867 /* 868 * Enable Dma access request 869 */ 870 mode_cntl.mode_bits.dma_dis = NGE_CLEAR; 871 872 /* 873 * Enbale Buffer management 874 */ 875 mode_cntl.mode_bits.bm_reset = NGE_CLEAR; 876 877 /* 878 * Support Standoffload Descriptor 879 */ 880 mode_cntl.mode_bits.desc_type = ngep->desc_mode; 881 882 /* 883 * Support receive hardware checksum 884 */ 885 if (dev_param_p->rx_hw_checksum) { 886 mode_cntl.mode_bits.rx_sum_en = NGE_SET; 887 } else 888 mode_cntl.mode_bits.rx_sum_en = NGE_CLEAR; 889 890 /* 891 * Disable Tx PRD coarse update 892 */ 893 mode_cntl.mode_bits.tx_prd_cu_en = NGE_CLEAR; 894 895 /* 896 * Disable 64-byte access 897 */ 898 mode_cntl.mode_bits.w64_dis = NGE_SET; 899 900 /* 901 * Skip Rx Error Frame is not supported and if 902 * enable it, jumbo frame does not work any more. 903 */ 904 mode_cntl.mode_bits.rx_filter_en = NGE_CLEAR; 905 906 /* 907 * Can not support hot mode now 908 */ 909 mode_cntl.mode_bits.resv15 = NGE_CLEAR; 910 911 if (dev_param_p->vlan) { 912 /* Disable the vlan strip for devices which support vlan */ 913 mode_cntl.mode_bits.vlan_strip = NGE_CLEAR; 914 915 /* Disable the vlan insert for devices which supprot vlan */ 916 mode_cntl.mode_bits.vlan_ins = NGE_CLEAR; 917 } 918 919 if (dev_param_p->tx_rx_64byte) { 920 921 /* Set the maximum TX PRD fetch size to 64 bytes */ 922 mode_cntl.mode_bits.tx_fetch_prd = NGE_SET; 923 924 /* Set the maximum RX PRD fetch size to 64 bytes */ 925 mode_cntl.mode_bits.rx_fetch_prd = NGE_SET; 926 } 927 /* 928 * Upload Rx data as it arrives, rather than waiting for full frame 929 */ 930 mode_cntl.mode_bits.resv16 = NGE_CLEAR; 931 932 /* 933 * Normal HOT table accesses 934 */ 935 mode_cntl.mode_bits.resv17 = NGE_CLEAR; 936 937 /* 938 * Normal HOT buffer requesting 939 */ 940 mode_cntl.mode_bits.resv18 = NGE_CLEAR; 941 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 942 943 /* 944 * Signal controller to check for new Rx descriptors 945 */ 946 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 947 mode_cntl.mode_bits.rxdm = NGE_SET; 948 mode_cntl.mode_bits.tx_rcom_en = NGE_SET; 949 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 950 951 952 return (DDI_SUCCESS); 953 } 954 955 /* 956 * When chipset resets, the chipset can not restore the orignial 957 * mac address to the mac address registers. 958 * 959 * When the driver is dettached, the function will write the orignial 960 * mac address to the mac address registers. 961 */ 962 963 void 964 nge_restore_mac_addr(nge_t *ngep) 965 { 966 uint32_t mac_addr; 967 968 mac_addr = (uint32_t)ngep->chipinfo.hw_mac_addr; 969 nge_reg_put32(ngep, NGE_UNI_ADDR0, mac_addr); 970 mac_addr = (uint32_t)(ngep->chipinfo.hw_mac_addr >> 32); 971 nge_reg_put32(ngep, NGE_UNI_ADDR1, mac_addr); 972 } 973 974 int 975 nge_chip_reset(nge_t *ngep) 976 { 977 int err; 978 uint8_t i; 979 uint32_t regno; 980 uint64_t mac = 0; 981 nge_uni_addr1 uaddr1; 982 nge_cp_cntl ee_cntl; 983 nge_soft_misc soft_misc; 984 nge_pmu_cntl0 pmu_cntl0; 985 nge_pmu_cntl2 pmu_cntl2; 986 nge_pm_cntl2 pm_cntl2; 987 const nge_ksindex_t *ksip; 988 989 NGE_TRACE(("nge_chip_reset($%p)", (void *)ngep)); 990 991 /* 992 * Clear the statistics by reading the statistics register 993 */ 994 for (ksip = nge_statistics; ksip->name != NULL; ++ksip) { 995 regno = KS_BASE + ksip->index * sizeof (uint32_t); 996 (void) nge_reg_get32(ngep, regno); 997 } 998 999 /* 1000 * Setup seeprom control 1001 */ 1002 ee_cntl.cntl_val = nge_reg_get32(ngep, NGE_EP_CNTL); 1003 ee_cntl.cntl_bits.clkdiv = EEPROM_CLKDIV; 1004 ee_cntl.cntl_bits.rom_size = EEPROM_32K; 1005 ee_cntl.cntl_bits.word_wid = ACCESS_16BIT; 1006 ee_cntl.cntl_bits.wait_slots = EEPROM_WAITCLK; 1007 nge_reg_put32(ngep, NGE_EP_CNTL, ee_cntl.cntl_val); 1008 1009 /* 1010 * Reading the unicast mac address table 1011 */ 1012 if (ngep->nge_chip_state == NGE_CHIP_INITIAL) { 1013 uaddr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 1014 mac = uaddr1.addr_bits.addr; 1015 mac <<= 32; 1016 mac |= nge_reg_get32(ngep, NGE_UNI_ADDR0); 1017 ngep->chipinfo.hw_mac_addr = mac; 1018 if (ngep->dev_spec_param.mac_addr_order) { 1019 for (i = 0; i < ETHERADDRL; i++) { 1020 ngep->chipinfo.vendor_addr.addr[i] = 1021 (uchar_t)mac; 1022 ngep->cur_uni_addr.addr[i] = 1023 (uchar_t)mac; 1024 mac >>= 8; 1025 } 1026 } else { 1027 for (i = ETHERADDRL; i-- != 0; ) { 1028 ngep->chipinfo.vendor_addr.addr[i] = 1029 (uchar_t)mac; 1030 ngep->cur_uni_addr.addr[i] = 1031 (uchar_t)mac; 1032 mac >>= 8; 1033 } 1034 } 1035 ngep->chipinfo.vendor_addr.set = 1; 1036 } 1037 pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ, 1038 ngep->chipinfo.clsize); 1039 pci_config_put8(ngep->cfg_handle, PCI_CONF_LATENCY_TIMER, 1040 ngep->chipinfo.latency); 1041 1042 1043 if (ngep->dev_spec_param.advanced_pm) { 1044 1045 /* Program software misc register */ 1046 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1047 soft_misc.misc_bits.rx_clk_vx_rst = NGE_SET; 1048 soft_misc.misc_bits.tx_clk_vx_rst = NGE_SET; 1049 soft_misc.misc_bits.clk12m_vx_rst = NGE_SET; 1050 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_SET; 1051 soft_misc.misc_bits.rx_clk_vc_rst = NGE_SET; 1052 soft_misc.misc_bits.tx_clk_vc_rst = NGE_SET; 1053 soft_misc.misc_bits.fs_clk_vc_rst = NGE_SET; 1054 soft_misc.misc_bits.rst_ex_m2pintf = NGE_SET; 1055 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1056 1057 /* wait for 32 us */ 1058 drv_usecwait(32); 1059 1060 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1061 soft_misc.misc_bits.rx_clk_vx_rst = NGE_CLEAR; 1062 soft_misc.misc_bits.tx_clk_vx_rst = NGE_CLEAR; 1063 soft_misc.misc_bits.clk12m_vx_rst = NGE_CLEAR; 1064 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_CLEAR; 1065 soft_misc.misc_bits.rx_clk_vc_rst = NGE_CLEAR; 1066 soft_misc.misc_bits.tx_clk_vc_rst = NGE_CLEAR; 1067 soft_misc.misc_bits.fs_clk_vc_rst = NGE_CLEAR; 1068 soft_misc.misc_bits.rst_ex_m2pintf = NGE_CLEAR; 1069 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1070 1071 /* Program PMU registers */ 1072 pmu_cntl0.cntl0_val = nge_reg_get32(ngep, NGE_PMU_CNTL0); 1073 pmu_cntl0.cntl0_bits.core_spd10_fp = 1074 NGE_PMU_CORE_SPD10_BUSY; 1075 pmu_cntl0.cntl0_bits.core_spd10_idle = 1076 NGE_PMU_CORE_SPD10_IDLE; 1077 pmu_cntl0.cntl0_bits.core_spd100_fp = 1078 NGE_PMU_CORE_SPD100_BUSY; 1079 pmu_cntl0.cntl0_bits.core_spd100_idle = 1080 NGE_PMU_CORE_SPD100_IDLE; 1081 pmu_cntl0.cntl0_bits.core_spd1000_fp = 1082 NGE_PMU_CORE_SPD1000_BUSY; 1083 pmu_cntl0.cntl0_bits.core_spd1000_idle = 1084 NGE_PMU_CORE_SPD100_IDLE; 1085 pmu_cntl0.cntl0_bits.core_spd10_idle = 1086 NGE_PMU_CORE_SPD10_IDLE; 1087 nge_reg_put32(ngep, NGE_PMU_CNTL0, pmu_cntl0.cntl0_val); 1088 1089 /* Set the core idle limit value */ 1090 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 1091 NGE_PMU_CIDLE_LIMIT_DEF); 1092 1093 /* Set the device idle limit value */ 1094 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 1095 NGE_PMU_DIDLE_LIMIT_DEF); 1096 1097 /* Enable the core/device idle timer in PMU control 2 */ 1098 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 1099 pmu_cntl2.cntl2_bits.cidle_timer = NGE_SET; 1100 pmu_cntl2.cntl2_bits.didle_timer = NGE_SET; 1101 pmu_cntl2.cntl2_bits.core_enable = NGE_SET; 1102 pmu_cntl2.cntl2_bits.dev_enable = NGE_SET; 1103 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 1104 } 1105 /* 1106 * Stop the chipset and clear buffer management 1107 */ 1108 err = nge_chip_stop(ngep, B_FALSE); 1109 if (err == DDI_FAILURE) 1110 return (err); 1111 /* 1112 * Clear the power state bits for phy since interface no longer 1113 * works after rebooting from Windows on a multi-boot machine 1114 */ 1115 if (ngep->chipinfo.device == DEVICE_ID_MCP51_268 || 1116 ngep->chipinfo.device == DEVICE_ID_MCP51_269 || 1117 ngep->chipinfo.device == DEVICE_ID_MCP55_372 || 1118 ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1119 ngep->chipinfo.device == DEVICE_ID_MCP61_3EE || 1120 ngep->chipinfo.device == DEVICE_ID_MCP61_3EF || 1121 ngep->chipinfo.device == DEVICE_ID_MCP77_760 || 1122 ngep->chipinfo.device == DEVICE_ID_MCP79_AB0) { 1123 1124 pm_cntl2.cntl_val = nge_reg_get32(ngep, NGE_PM_CNTL2); 1125 /* bring phy out of coma mode */ 1126 pm_cntl2.cntl_bits.phy_coma_set = NGE_CLEAR; 1127 /* disable auto reset coma bits */ 1128 pm_cntl2.cntl_bits.resv4 = NGE_CLEAR; 1129 /* restore power to gated clocks */ 1130 pm_cntl2.cntl_bits.resv8_11 = NGE_CLEAR; 1131 nge_reg_put32(ngep, NGE_PM_CNTL2, pm_cntl2.cntl_val); 1132 } 1133 1134 ngep->nge_chip_state = NGE_CHIP_RESET; 1135 return (DDI_SUCCESS); 1136 } 1137 1138 int 1139 nge_chip_start(nge_t *ngep) 1140 { 1141 int err; 1142 nge_itc itc; 1143 nge_tx_cntl tx_cntl; 1144 nge_rx_cntrl0 rx_cntl0; 1145 nge_rx_cntl1 rx_cntl1; 1146 nge_tx_en tx_en; 1147 nge_rx_en rx_en; 1148 nge_mii_cs mii_cs; 1149 nge_swtr_cntl swtr_cntl; 1150 nge_rx_fifo_wm rx_fifo; 1151 nge_intr_mask intr_mask; 1152 nge_mintr_mask mintr_mask; 1153 nge_dev_spec_param_t *dev_param_p; 1154 1155 NGE_TRACE(("nge_chip_start($%p)", (void *)ngep)); 1156 1157 /* 1158 * Setup buffer management 1159 */ 1160 err = nge_buff_setup(ngep); 1161 if (err == DDI_FAILURE) 1162 return (err); 1163 1164 dev_param_p = &ngep->dev_spec_param; 1165 1166 /* 1167 * Enable polling attribute 1168 */ 1169 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 1170 mii_cs.cs_bits.ap_paddr = ngep->phy_xmii_addr; 1171 mii_cs.cs_bits.ap_en = NGE_SET; 1172 mii_cs.cs_bits.ap_intv = MII_POLL_INTV; 1173 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 1174 1175 /* 1176 * Setup link 1177 */ 1178 (*ngep->physops->phys_update)(ngep); 1179 1180 /* 1181 * Configure the tx's parameters 1182 */ 1183 tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL); 1184 if (dev_param_p->tx_pause_frame) 1185 tx_cntl.cntl_bits.paen = NGE_SET; 1186 else 1187 tx_cntl.cntl_bits.paen = NGE_CLEAR; 1188 tx_cntl.cntl_bits.retry_en = NGE_SET; 1189 tx_cntl.cntl_bits.pad_en = NGE_SET; 1190 tx_cntl.cntl_bits.fappend_en = NGE_SET; 1191 tx_cntl.cntl_bits.two_def_en = NGE_SET; 1192 tx_cntl.cntl_bits.max_retry = 15; 1193 tx_cntl.cntl_bits.burst_en = NGE_CLEAR; 1194 tx_cntl.cntl_bits.uflo_err_mask = NGE_CLEAR; 1195 tx_cntl.cntl_bits.tlcol_mask = NGE_CLEAR; 1196 tx_cntl.cntl_bits.lcar_mask = NGE_CLEAR; 1197 tx_cntl.cntl_bits.def_mask = NGE_CLEAR; 1198 tx_cntl.cntl_bits.exdef_mask = NGE_SET; 1199 tx_cntl.cntl_bits.lcar_mask = NGE_SET; 1200 tx_cntl.cntl_bits.tlcol_mask = NGE_SET; 1201 tx_cntl.cntl_bits.uflo_err_mask = NGE_SET; 1202 tx_cntl.cntl_bits.jam_seq_en = NGE_CLEAR; 1203 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val); 1204 1205 1206 /* 1207 * Configure the parameters of Rx's state machine 1208 * Enabe the parameters: 1209 * 1). Pad Strip 1210 * 2). FCS Relay 1211 * 3). Pause 1212 * 4). Address filter 1213 * 5). Runt Packet receive 1214 * 6). Broadcast 1215 * 7). Receive Deferral 1216 * 1217 * Disable the following parameters for decreasing 1218 * the number of interrupts: 1219 * 1). Runt Inerrupt. 1220 * 2). Rx's Late Collision interrupt. 1221 * 3). Rx's Max length Error Interrupt. 1222 * 4). Rx's Length Field error Interrupt. 1223 * 5). Rx's FCS error interrupt. 1224 * 6). Rx's overflow error interrupt. 1225 * 7). Rx's Frame alignment error interrupt. 1226 */ 1227 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1228 rx_cntl0.cntl_bits.padsen = NGE_CLEAR; 1229 rx_cntl0.cntl_bits.fcsren = NGE_CLEAR; 1230 if (dev_param_p->rx_pause_frame) 1231 rx_cntl0.cntl_bits.paen = NGE_SET; 1232 else 1233 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1234 rx_cntl0.cntl_bits.lben = NGE_CLEAR; 1235 rx_cntl0.cntl_bits.afen = NGE_SET; 1236 rx_cntl0.cntl_bits.runten = NGE_CLEAR; 1237 rx_cntl0.cntl_bits.brdis = NGE_CLEAR; 1238 rx_cntl0.cntl_bits.rdfen = NGE_CLEAR; 1239 rx_cntl0.cntl_bits.runtm = NGE_CLEAR; 1240 rx_cntl0.cntl_bits.slfb = NGE_CLEAR; 1241 rx_cntl0.cntl_bits.rlcolm = NGE_CLEAR; 1242 rx_cntl0.cntl_bits.maxerm = NGE_CLEAR; 1243 rx_cntl0.cntl_bits.lferm = NGE_CLEAR; 1244 rx_cntl0.cntl_bits.crcm = NGE_CLEAR; 1245 rx_cntl0.cntl_bits.ofolm = NGE_CLEAR; 1246 rx_cntl0.cntl_bits.framerm = NGE_CLEAR; 1247 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1248 1249 /* 1250 * Configure the watermark for the rx's statemachine 1251 */ 1252 rx_fifo.wm_val = nge_reg_get32(ngep, NGE_RX_FIFO_WM); 1253 rx_fifo.wm_bits.data_hwm = ngep->rx_datahwm; 1254 rx_fifo.wm_bits.prd_lwm = ngep->rx_prdlwm; 1255 rx_fifo.wm_bits.prd_hwm = ngep->rx_prdhwm; 1256 nge_reg_put32(ngep, NGE_RX_FIFO_WM, rx_fifo.wm_val); 1257 1258 /* 1259 * Configure the deffer time slot for rx's state machine 1260 */ 1261 nge_reg_put8(ngep, NGE_RX_DEf, ngep->rx_def); 1262 1263 /* 1264 * Configure the length of rx's packet 1265 */ 1266 rx_cntl1.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL1); 1267 rx_cntl1.cntl_bits.length = ngep->max_sdu; 1268 nge_reg_put32(ngep, NGE_RX_CNTL1, rx_cntl1.cntl_val); 1269 /* 1270 * Enable Tx's state machine 1271 */ 1272 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 1273 tx_en.bits.tx_en = NGE_SET; 1274 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 1275 1276 /* 1277 * Enable Rx's state machine 1278 */ 1279 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 1280 rx_en.bits.rx_en = NGE_SET; 1281 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 1282 1283 itc.itc_val = nge_reg_get32(ngep, NGE_SWTR_ITC); 1284 itc.itc_bits.sw_intv = ngep->sw_intr_intv; 1285 nge_reg_put32(ngep, NGE_SWTR_ITC, itc.itc_val); 1286 1287 swtr_cntl.ctrl_val = nge_reg_get8(ngep, NGE_SWTR_CNTL); 1288 swtr_cntl.cntl_bits.sten = NGE_SET; 1289 swtr_cntl.cntl_bits.stren = NGE_SET; 1290 nge_reg_put32(ngep, NGE_SWTR_CNTL, swtr_cntl.ctrl_val); 1291 1292 /* 1293 * Disable all mii read/write operation Interrupt 1294 */ 1295 mintr_mask.mask_val = nge_reg_get8(ngep, NGE_MINTR_MASK); 1296 mintr_mask.mask_bits.mrei = NGE_CLEAR; 1297 mintr_mask.mask_bits.mcc2 = NGE_CLEAR; 1298 mintr_mask.mask_bits.mcc1 = NGE_CLEAR; 1299 mintr_mask.mask_bits.mapi = NGE_SET; 1300 mintr_mask.mask_bits.mpdi = NGE_SET; 1301 nge_reg_put8(ngep, NGE_MINTR_MASK, mintr_mask.mask_val); 1302 1303 /* 1304 * Enable all interrupt event 1305 */ 1306 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1307 intr_mask.mask_bits.reint = NGE_SET; 1308 intr_mask.mask_bits.rcint = NGE_SET; 1309 intr_mask.mask_bits.miss = NGE_SET; 1310 intr_mask.mask_bits.teint = NGE_SET; 1311 intr_mask.mask_bits.tcint = NGE_CLEAR; 1312 intr_mask.mask_bits.stint = NGE_CLEAR; 1313 intr_mask.mask_bits.mint = NGE_CLEAR; 1314 intr_mask.mask_bits.rfint = NGE_CLEAR; 1315 intr_mask.mask_bits.tfint = NGE_SET; 1316 intr_mask.mask_bits.feint = NGE_SET; 1317 intr_mask.mask_bits.resv10 = NGE_CLEAR; 1318 intr_mask.mask_bits.resv11 = NGE_CLEAR; 1319 intr_mask.mask_bits.resv12 = NGE_CLEAR; 1320 intr_mask.mask_bits.resv13 = NGE_CLEAR; 1321 intr_mask.mask_bits.phyint = NGE_CLEAR; 1322 ngep->intr_masks = intr_mask.mask_val; 1323 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1324 ngep->nge_chip_state = NGE_CHIP_RUNNING; 1325 return (DDI_SUCCESS); 1326 } 1327 1328 /* 1329 * nge_chip_sync() -- program the chip with the unicast MAC address, 1330 * the multicast hash table, the required level of promiscuity. 1331 */ 1332 void 1333 nge_chip_sync(nge_t *ngep) 1334 { 1335 uint8_t i; 1336 uint64_t macaddr; 1337 uint64_t mul_addr; 1338 uint64_t mul_mask; 1339 nge_rx_cntrl0 rx_cntl; 1340 nge_uni_addr1 uni_adr1; 1341 1342 NGE_TRACE(("nge_chip_sync($%p)", (void *)ngep)); 1343 1344 macaddr = 0x0ull; 1345 mul_addr = 0x0ull; 1346 mul_mask = 0x0ull; 1347 rx_cntl.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1348 1349 if (ngep->promisc) { 1350 rx_cntl.cntl_bits.afen = NGE_CLEAR; 1351 rx_cntl.cntl_bits.brdis = NGE_SET; 1352 } else { 1353 rx_cntl.cntl_bits.afen = NGE_SET; 1354 rx_cntl.cntl_bits.brdis = NGE_CLEAR; 1355 } 1356 1357 /* 1358 * Transform the MAC address from host to chip format, the unicast 1359 * MAC address(es) ... 1360 */ 1361 for (i = ETHERADDRL, macaddr = 0ull; i != 0; --i) { 1362 macaddr |= ngep->cur_uni_addr.addr[i-1]; 1363 macaddr <<= (i > 1) ? 8 : 0; 1364 } 1365 1366 nge_reg_put32(ngep, NGE_UNI_ADDR0, (uint32_t)macaddr); 1367 macaddr = macaddr >>32; 1368 uni_adr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 1369 uni_adr1.addr_bits.addr = (uint16_t)macaddr; 1370 uni_adr1.addr_bits.resv16_31 = (uint16_t)0; 1371 nge_reg_put32(ngep, NGE_UNI_ADDR1, uni_adr1.addr_val); 1372 1373 /* 1374 * Reprogram the multicast address table ... 1375 */ 1376 for (i = ETHERADDRL, mul_addr = 0ull; i != 0; --i) { 1377 mul_addr |= ngep->cur_mul_addr.addr[i-1]; 1378 mul_addr <<= (i > 1) ? 8 : 0; 1379 mul_mask |= ngep->cur_mul_mask.addr[i-1]; 1380 mul_mask <<= (i > 1) ? 8 : 0; 1381 } 1382 nge_reg_put32(ngep, NGE_MUL_ADDR0, (uint32_t)mul_addr); 1383 mul_addr >>= 32; 1384 nge_reg_put32(ngep, NGE_MUL_ADDR1, mul_addr); 1385 nge_reg_put32(ngep, NGE_MUL_MASK, (uint32_t)mul_mask); 1386 mul_mask >>= 32; 1387 nge_reg_put32(ngep, NGE_MUL_MASK1, mul_mask); 1388 /* 1389 * Set or clear the PROMISCUOUS mode bit 1390 */ 1391 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl.cntl_val); 1392 /* 1393 * For internal PHY loopback, the link will 1394 * not be up, so it need to sync mac modes directly. 1395 */ 1396 if (ngep->param_loop_mode == NGE_LOOP_INTERNAL_PHY) 1397 nge_sync_mac_modes(ngep); 1398 } 1399 1400 static void 1401 nge_chip_err(nge_t *ngep) 1402 { 1403 nge_reg010 reg010_ins; 1404 nge_sw_statistics_t *psw_stat; 1405 nge_intr_mask intr_mask; 1406 1407 NGE_TRACE(("nge_chip_err($%p)", (void *)ngep)); 1408 1409 psw_stat = (nge_sw_statistics_t *)&ngep->statistics.sw_statistics; 1410 reg010_ins.reg010_val = nge_reg_get32(ngep, NGE_REG010); 1411 if (reg010_ins.reg010_bits.resv0) 1412 psw_stat->fe_err.tso_err_mss ++; 1413 1414 if (reg010_ins.reg010_bits.resv1) 1415 psw_stat->fe_err.tso_dis ++; 1416 1417 if (reg010_ins.reg010_bits.resv2) 1418 psw_stat->fe_err.tso_err_nosum ++; 1419 1420 if (reg010_ins.reg010_bits.resv3) 1421 psw_stat->fe_err.tso_err_hov ++; 1422 1423 if (reg010_ins.reg010_bits.resv4) 1424 psw_stat->fe_err.tso_err_huf ++; 1425 1426 if (reg010_ins.reg010_bits.resv5) 1427 psw_stat->fe_err.tso_err_l2 ++; 1428 1429 if (reg010_ins.reg010_bits.resv6) 1430 psw_stat->fe_err.tso_err_ip ++; 1431 1432 if (reg010_ins.reg010_bits.resv7) 1433 psw_stat->fe_err.tso_err_l4 ++; 1434 1435 if (reg010_ins.reg010_bits.resv8) 1436 psw_stat->fe_err.tso_err_tcp ++; 1437 1438 if (reg010_ins.reg010_bits.resv9) 1439 psw_stat->fe_err.hsum_err_ip ++; 1440 1441 if (reg010_ins.reg010_bits.resv10) 1442 psw_stat->fe_err.hsum_err_l4 ++; 1443 1444 if (reg010_ins.reg010_val != 0) { 1445 1446 /* 1447 * Fatal error is triggered by malformed driver commands. 1448 * Disable unless debugging. 1449 */ 1450 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1451 intr_mask.mask_bits.feint = NGE_CLEAR; 1452 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1453 ngep->intr_masks = intr_mask.mask_val; 1454 1455 } 1456 } 1457 1458 static void 1459 nge_sync_mac_modes(nge_t *ngep) 1460 { 1461 nge_tx_def tx_def; 1462 nge_tx_fifo_wm tx_fifo; 1463 nge_bkoff_cntl bk_cntl; 1464 nge_mac2phy m2p; 1465 nge_rx_cntrl0 rx_cntl0; 1466 nge_tx_cntl tx_cntl; 1467 nge_dev_spec_param_t *dev_param_p; 1468 1469 dev_param_p = &ngep->dev_spec_param; 1470 1471 tx_def.def_val = nge_reg_get32(ngep, NGE_TX_DEF); 1472 m2p.m2p_val = nge_reg_get32(ngep, NGE_MAC2PHY); 1473 tx_fifo.wm_val = nge_reg_get32(ngep, NGE_TX_FIFO_WM); 1474 bk_cntl.cntl_val = nge_reg_get32(ngep, NGE_BKOFF_CNTL); 1475 bk_cntl.bkoff_bits.rseed = BKOFF_RSEED; 1476 switch (ngep->param_link_speed) { 1477 case 10: 1478 m2p.m2p_bits.speed = low_speed; 1479 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1480 if (ngep->phy_mode == RGMII_IN) { 1481 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1482 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1483 } else { 1484 tx_def.def_bits.if_def = TX_TIFG_MII; 1485 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1486 } 1487 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1488 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1489 break; 1490 1491 case 100: 1492 m2p.m2p_bits.speed = fast_speed; 1493 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1494 if (ngep->phy_mode == RGMII_IN) { 1495 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1496 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1497 } else { 1498 tx_def.def_bits.if_def = TX_TIFG_MII; 1499 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1500 } 1501 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1502 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1503 break; 1504 1505 case 1000: 1506 m2p.m2p_bits.speed = giga_speed; 1507 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1508 if (ngep->param_link_duplex == LINK_DUPLEX_FULL) { 1509 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1510 tx_def.def_bits.if_def = TX_IFG_RGMII_1000_FD; 1511 } else { 1512 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1513 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1514 } 1515 1516 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_GMII; 1517 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_GMII; 1518 break; 1519 } 1520 1521 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1522 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 1523 m2p.m2p_bits.phyintr = NGE_CLEAR; 1524 m2p.m2p_bits.phyintrlvl = NGE_CLEAR; 1525 } 1526 if (ngep->param_link_duplex == LINK_DUPLEX_HALF) { 1527 m2p.m2p_bits.hdup_en = NGE_SET; 1528 } 1529 else 1530 m2p.m2p_bits.hdup_en = NGE_CLEAR; 1531 nge_reg_put32(ngep, NGE_MAC2PHY, m2p.m2p_val); 1532 nge_reg_put32(ngep, NGE_TX_DEF, tx_def.def_val); 1533 1534 tx_fifo.wm_bits.data_lwm = TX_FIFO_DATA_LWM; 1535 tx_fifo.wm_bits.prd_lwm = TX_FIFO_PRD_LWM; 1536 tx_fifo.wm_bits.uprd_hwm = TX_FIFO_PRD_HWM; 1537 tx_fifo.wm_bits.fb_wm = TX_FIFO_TBFW; 1538 nge_reg_put32(ngep, NGE_TX_FIFO_WM, tx_fifo.wm_val); 1539 1540 nge_reg_put32(ngep, NGE_BKOFF_CNTL, bk_cntl.cntl_val); 1541 1542 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1543 if (ngep->param_link_rx_pause && dev_param_p->rx_pause_frame) { 1544 if (rx_cntl0.cntl_bits.paen == NGE_CLEAR) { 1545 rx_cntl0.cntl_bits.paen = NGE_SET; 1546 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1547 } 1548 } else { 1549 if (rx_cntl0.cntl_bits.paen == NGE_SET) { 1550 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1551 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1552 } 1553 } 1554 1555 tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL); 1556 if (ngep->param_link_tx_pause && dev_param_p->tx_pause_frame) { 1557 if (tx_cntl.cntl_bits.paen == NGE_CLEAR) { 1558 tx_cntl.cntl_bits.paen = NGE_SET; 1559 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val); 1560 } 1561 } else { 1562 if (tx_cntl.cntl_bits.paen == NGE_SET) { 1563 tx_cntl.cntl_bits.paen = NGE_CLEAR; 1564 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val); 1565 } 1566 } 1567 } 1568 1569 /* 1570 * Handler for hardware link state change. 1571 * 1572 * When this routine is called, the hardware link state has changed 1573 * and the new state is reflected in the param_* variables. Here 1574 * we must update the softstate, reprogram the MAC to match, and 1575 * record the change in the log and/or on the console. 1576 */ 1577 static void 1578 nge_factotum_link_handler(nge_t *ngep) 1579 { 1580 /* 1581 * Update the s/w link_state 1582 */ 1583 if (ngep->param_link_up) 1584 ngep->link_state = LINK_STATE_UP; 1585 else 1586 ngep->link_state = LINK_STATE_DOWN; 1587 1588 /* 1589 * Reprogram the MAC modes to match 1590 */ 1591 nge_sync_mac_modes(ngep); 1592 } 1593 1594 static boolean_t 1595 nge_factotum_link_check(nge_t *ngep) 1596 { 1597 boolean_t lchg; 1598 boolean_t check; 1599 1600 ASSERT(mutex_owned(ngep->genlock)); 1601 1602 (*ngep->physops->phys_check)(ngep); 1603 switch (ngep->link_state) { 1604 case LINK_STATE_UP: 1605 lchg = (ngep->param_link_up == B_FALSE); 1606 check = (ngep->param_link_up == B_FALSE); 1607 break; 1608 1609 case LINK_STATE_DOWN: 1610 lchg = (ngep->param_link_up == B_TRUE); 1611 check = (ngep->param_link_up == B_TRUE); 1612 break; 1613 1614 default: 1615 check = B_TRUE; 1616 break; 1617 } 1618 1619 /* 1620 * If <check> is false, we're sure the link hasn't changed. 1621 * If true, however, it's not yet definitive; we have to call 1622 * nge_phys_check() to determine whether the link has settled 1623 * into a new state yet ... and if it has, then call the link 1624 * state change handler.But when the chip is 5700 in Dell 6650 1625 * ,even if check is false, the link may have changed.So we 1626 * have to call nge_phys_check() to determine the link state. 1627 */ 1628 if (check) 1629 nge_factotum_link_handler(ngep); 1630 1631 return (lchg); 1632 } 1633 1634 /* 1635 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1636 */ 1637 static boolean_t nge_factotum_stall_check(nge_t *ngep); 1638 1639 static boolean_t 1640 nge_factotum_stall_check(nge_t *ngep) 1641 { 1642 uint32_t dogval; 1643 send_ring_t *srp; 1644 srp = ngep->send; 1645 /* 1646 * Specific check for Tx stall ... 1647 * 1648 * The 'watchdog' counter is incremented whenever a packet 1649 * is queued, reset to 1 when some (but not all) buffers 1650 * are reclaimed, reset to 0 (disabled) when all buffers 1651 * are reclaimed, and shifted left here. If it exceeds the 1652 * threshold value, the chip is assumed to have stalled and 1653 * is put into the ERROR state. The factotum will then reset 1654 * it on the next pass. 1655 * 1656 * All of which should ensure that we don't get into a state 1657 * where packets are left pending indefinitely! 1658 */ 1659 if (ngep->watchdog == 0 && 1660 srp->tx_free < srp->desc.nslots) 1661 ngep->watchdog = 1; 1662 dogval = nge_atomic_shl32(&ngep->watchdog, 1); 1663 if (dogval >= nge_watchdog_check) 1664 nge_tx_recycle(ngep, B_FALSE); 1665 if (dogval < nge_watchdog_count) 1666 return (B_FALSE); 1667 else { 1668 ngep->statistics.sw_statistics.tx_stall++; 1669 return (B_TRUE); 1670 } 1671 } 1672 1673 1674 /* 1675 * The factotum is woken up when there's something to do that we'd rather 1676 * not do from inside a hardware interrupt handler or high-level cyclic. 1677 * Its two main tasks are: 1678 * reset & restart the chip after an error 1679 * check the link status whenever necessary 1680 */ 1681 /* ARGSUSED */ 1682 uint_t 1683 nge_chip_factotum(caddr_t args1, caddr_t args2) 1684 { 1685 uint_t result; 1686 nge_t *ngep; 1687 boolean_t err; 1688 boolean_t linkchg; 1689 1690 ngep = (nge_t *)args1; 1691 1692 NGE_TRACE(("nge_chip_factotum($%p)", (void *)ngep)); 1693 1694 mutex_enter(ngep->softlock); 1695 if (ngep->factotum_flag == 0) { 1696 mutex_exit(ngep->softlock); 1697 return (DDI_INTR_UNCLAIMED); 1698 } 1699 ngep->factotum_flag = 0; 1700 mutex_exit(ngep->softlock); 1701 err = B_FALSE; 1702 linkchg = B_FALSE; 1703 result = DDI_INTR_CLAIMED; 1704 1705 mutex_enter(ngep->genlock); 1706 switch (ngep->nge_chip_state) { 1707 default: 1708 break; 1709 1710 case NGE_CHIP_RUNNING: 1711 linkchg = nge_factotum_link_check(ngep); 1712 err = nge_factotum_stall_check(ngep); 1713 break; 1714 1715 case NGE_CHIP_FAULT: 1716 (void) nge_restart(ngep); 1717 NGE_REPORT((ngep, "automatic recovery activated")); 1718 break; 1719 } 1720 1721 if (err) 1722 (void) nge_chip_stop(ngep, B_TRUE); 1723 mutex_exit(ngep->genlock); 1724 1725 /* 1726 * If the link state changed, tell the world about it (if 1727 * this version of MAC supports link state notification). 1728 * Note: can't do this while still holding the mutex. 1729 */ 1730 if (linkchg) 1731 mac_link_update(ngep->mh, ngep->link_state); 1732 1733 return (result); 1734 1735 } 1736 1737 static void 1738 nge_intr_handle(nge_t *ngep, nge_intr_src *pintr_src) 1739 { 1740 boolean_t brx; 1741 boolean_t btx; 1742 nge_mintr_src mintr_src; 1743 1744 brx = B_FALSE; 1745 btx = B_FALSE; 1746 ngep->statistics.sw_statistics.intr_count++; 1747 ngep->statistics.sw_statistics.intr_lval = pintr_src->intr_val; 1748 brx = (pintr_src->int_bits.reint | pintr_src->int_bits.miss 1749 | pintr_src->int_bits.rcint | pintr_src->int_bits.stint) 1750 != 0 ? B_TRUE : B_FALSE; 1751 if (pintr_src->int_bits.reint) 1752 ngep->statistics.sw_statistics.rx_err++; 1753 if (pintr_src->int_bits.miss) 1754 ngep->statistics.sw_statistics.rx_nobuffer++; 1755 1756 btx = (pintr_src->int_bits.teint | pintr_src->int_bits.tfint) 1757 != 0 ? B_TRUE : B_FALSE; 1758 if (btx) 1759 nge_tx_recycle(ngep, B_TRUE); 1760 if (brx) 1761 nge_receive(ngep); 1762 if (pintr_src->int_bits.teint) 1763 ngep->statistics.sw_statistics.tx_stop_err++; 1764 if (ngep->intr_moderation && brx) { 1765 if (ngep->poll) { 1766 if (ngep->recv_count < ngep->param_rx_intr_hwater) { 1767 ngep->quiet_time++; 1768 if (ngep->quiet_time == 1769 ngep->param_poll_quiet_time) { 1770 ngep->poll = B_FALSE; 1771 ngep->quiet_time = 0; 1772 } 1773 } else 1774 ngep->quiet_time = 0; 1775 } else { 1776 if (ngep->recv_count > ngep->param_rx_intr_lwater) { 1777 ngep->busy_time++; 1778 if (ngep->busy_time == 1779 ngep->param_poll_busy_time) { 1780 ngep->poll = B_TRUE; 1781 ngep->busy_time = 0; 1782 } 1783 } else 1784 ngep->busy_time = 0; 1785 } 1786 } 1787 ngep->recv_count = 0; 1788 if (pintr_src->int_bits.feint) 1789 nge_chip_err(ngep); 1790 /* link interrupt, check the link state */ 1791 if (pintr_src->int_bits.mint) { 1792 mintr_src.src_val = nge_reg_get32(ngep, NGE_MINTR_SRC); 1793 nge_reg_put32(ngep, NGE_MINTR_SRC, mintr_src.src_val); 1794 nge_wake_factotum(ngep); 1795 } 1796 } 1797 1798 /* 1799 * nge_chip_intr() -- handle chip interrupts 1800 */ 1801 /* ARGSUSED */ 1802 uint_t 1803 nge_chip_intr(caddr_t arg1, caddr_t arg2) 1804 { 1805 nge_t *ngep = (nge_t *)arg1; 1806 nge_intr_src intr_src; 1807 nge_intr_mask intr_mask; 1808 1809 mutex_enter(ngep->genlock); 1810 1811 if (ngep->suspended) { 1812 mutex_exit(ngep->genlock); 1813 return (DDI_INTR_UNCLAIMED); 1814 } 1815 1816 /* 1817 * Check whether chip's says it's asserting #INTA; 1818 * if not, don't process or claim the interrupt. 1819 */ 1820 intr_src.intr_val = nge_reg_get32(ngep, NGE_INTR_SRC); 1821 if (intr_src.intr_val == 0) { 1822 mutex_exit(ngep->genlock); 1823 return (DDI_INTR_UNCLAIMED); 1824 } 1825 /* 1826 * Ack the interrupt 1827 */ 1828 nge_reg_put32(ngep, NGE_INTR_SRC, intr_src.intr_val); 1829 1830 if (ngep->nge_chip_state != NGE_CHIP_RUNNING) { 1831 mutex_exit(ngep->genlock); 1832 return (DDI_INTR_CLAIMED); 1833 } 1834 nge_intr_handle(ngep, &intr_src); 1835 if (ngep->poll && !ngep->ch_intr_mode) { 1836 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1837 intr_mask.mask_bits.stint = NGE_SET; 1838 intr_mask.mask_bits.rcint = NGE_CLEAR; 1839 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1840 ngep->ch_intr_mode = B_TRUE; 1841 } else if ((ngep->ch_intr_mode) && (!ngep->poll)) { 1842 nge_reg_put32(ngep, NGE_INTR_MASK, ngep->intr_masks); 1843 ngep->ch_intr_mode = B_FALSE; 1844 } 1845 mutex_exit(ngep->genlock); 1846 return (DDI_INTR_CLAIMED); 1847 } 1848 1849 static enum ioc_reply 1850 nge_pp_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1851 { 1852 int err; 1853 uint64_t sizemask; 1854 uint64_t mem_va; 1855 uint64_t maxoff; 1856 boolean_t peek; 1857 nge_peekpoke_t *ppd; 1858 int (*ppfn)(nge_t *ngep, nge_peekpoke_t *ppd); 1859 1860 switch (cmd) { 1861 default: 1862 return (IOC_INVAL); 1863 1864 case NGE_PEEK: 1865 peek = B_TRUE; 1866 break; 1867 1868 case NGE_POKE: 1869 peek = B_FALSE; 1870 break; 1871 } 1872 1873 /* 1874 * Validate format of ioctl 1875 */ 1876 if (iocp->ioc_count != sizeof (nge_peekpoke_t)) 1877 return (IOC_INVAL); 1878 if (mp->b_cont == NULL) 1879 return (IOC_INVAL); 1880 ppd = (nge_peekpoke_t *)mp->b_cont->b_rptr; 1881 1882 /* 1883 * Validate request parameters 1884 */ 1885 switch (ppd->pp_acc_space) { 1886 default: 1887 return (IOC_INVAL); 1888 1889 case NGE_PP_SPACE_CFG: 1890 /* 1891 * Config space 1892 */ 1893 sizemask = 8|4|2|1; 1894 mem_va = 0; 1895 maxoff = PCI_CONF_HDR_SIZE; 1896 ppfn = peek ? nge_chip_peek_cfg : nge_chip_poke_cfg; 1897 break; 1898 1899 case NGE_PP_SPACE_REG: 1900 /* 1901 * Memory-mapped I/O space 1902 */ 1903 sizemask = 8|4|2|1; 1904 mem_va = 0; 1905 maxoff = NGE_REG_SIZE; 1906 ppfn = peek ? nge_chip_peek_reg : nge_chip_poke_reg; 1907 break; 1908 1909 case NGE_PP_SPACE_MII: 1910 sizemask = 4|2|1; 1911 mem_va = 0; 1912 maxoff = NGE_MII_SIZE; 1913 ppfn = peek ? nge_chip_peek_mii : nge_chip_poke_mii; 1914 break; 1915 1916 case NGE_PP_SPACE_SEEPROM: 1917 sizemask = 4|2|1; 1918 mem_va = 0; 1919 maxoff = NGE_SEEROM_SIZE; 1920 ppfn = peek ? nge_chip_peek_seeprom : nge_chip_poke_seeprom; 1921 break; 1922 } 1923 1924 switch (ppd->pp_acc_size) { 1925 default: 1926 return (IOC_INVAL); 1927 1928 case 8: 1929 case 4: 1930 case 2: 1931 case 1: 1932 if ((ppd->pp_acc_size & sizemask) == 0) 1933 return (IOC_INVAL); 1934 break; 1935 } 1936 1937 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1938 return (IOC_INVAL); 1939 1940 if (ppd->pp_acc_offset >= maxoff) 1941 return (IOC_INVAL); 1942 1943 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1944 return (IOC_INVAL); 1945 1946 /* 1947 * All OK - go do it! 1948 */ 1949 ppd->pp_acc_offset += mem_va; 1950 if (ppfn) 1951 err = (*ppfn)(ngep, ppd); 1952 if (err != DDI_SUCCESS) 1953 return (IOC_INVAL); 1954 return (peek ? IOC_REPLY : IOC_ACK); 1955 } 1956 1957 static enum ioc_reply nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, 1958 struct iocblk *iocp); 1959 #pragma no_inline(nge_diag_ioctl) 1960 1961 static enum ioc_reply 1962 nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1963 { 1964 ASSERT(mutex_owned(ngep->genlock)); 1965 1966 switch (cmd) { 1967 default: 1968 nge_error(ngep, "nge_diag_ioctl: invalid cmd 0x%x", cmd); 1969 return (IOC_INVAL); 1970 1971 case NGE_DIAG: 1972 return (IOC_ACK); 1973 1974 case NGE_PEEK: 1975 case NGE_POKE: 1976 return (nge_pp_ioctl(ngep, cmd, mp, iocp)); 1977 1978 case NGE_PHY_RESET: 1979 return (IOC_RESTART_ACK); 1980 1981 case NGE_SOFT_RESET: 1982 case NGE_HARD_RESET: 1983 return (IOC_ACK); 1984 } 1985 1986 /* NOTREACHED */ 1987 } 1988 1989 enum ioc_reply 1990 nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp) 1991 { 1992 int cmd; 1993 1994 ASSERT(mutex_owned(ngep->genlock)); 1995 1996 cmd = iocp->ioc_cmd; 1997 1998 switch (cmd) { 1999 default: 2000 return (IOC_INVAL); 2001 2002 case NGE_DIAG: 2003 case NGE_PEEK: 2004 case NGE_POKE: 2005 case NGE_PHY_RESET: 2006 case NGE_SOFT_RESET: 2007 case NGE_HARD_RESET: 2008 #if NGE_DEBUGGING 2009 return (nge_diag_ioctl(ngep, cmd, mp, iocp)); 2010 #else 2011 return (IOC_INVAL); 2012 #endif 2013 2014 case NGE_MII_READ: 2015 case NGE_MII_WRITE: 2016 return (IOC_INVAL); 2017 2018 #if NGE_SEE_IO32 2019 case NGE_SEE_READ: 2020 case NGE_SEE_WRITE: 2021 return (IOC_INVAL); 2022 #endif 2023 2024 #if NGE_FLASH_IO32 2025 case NGE_FLASH_READ: 2026 case NGE_FLASH_WRITE: 2027 return (IOC_INVAL); 2028 #endif 2029 } 2030 } 2031