1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "nge.h" 28 static uint32_t nge_watchdog_count = 1 << 29; 29 extern boolean_t nge_enable_msi; 30 static void nge_sync_mac_modes(nge_t *); 31 32 #undef NGE_DBG 33 #define NGE_DBG NGE_DBG_CHIP 34 35 /* 36 * Operating register get/set access routines 37 */ 38 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno); 39 #pragma inline(nge_reg_get8) 40 41 uint8_t 42 nge_reg_get8(nge_t *ngep, nge_regno_t regno) 43 { 44 NGE_TRACE(("nge_reg_get8($%p, 0x%lx)", (void *)ngep, regno)); 45 46 return (ddi_get8(ngep->io_handle, PIO_ADDR(ngep, regno))); 47 } 48 49 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data); 50 #pragma inline(nge_reg_put8) 51 52 void 53 nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data) 54 { 55 NGE_TRACE(("nge_reg_put8($%p, 0x%lx, 0x%x)", 56 (void *)ngep, regno, data)); 57 ddi_put8(ngep->io_handle, PIO_ADDR(ngep, regno), data); 58 59 } 60 61 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno); 62 #pragma inline(nge_reg_get16) 63 64 uint16_t 65 nge_reg_get16(nge_t *ngep, nge_regno_t regno) 66 { 67 NGE_TRACE(("nge_reg_get16($%p, 0x%lx)", (void *)ngep, regno)); 68 return (ddi_get16(ngep->io_handle, PIO_ADDR(ngep, regno))); 69 } 70 71 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 72 #pragma inline(nge_reg_put16) 73 74 void 75 nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data) 76 { 77 NGE_TRACE(("nge_reg_put16($%p, 0x%lx, 0x%x)", 78 (void *)ngep, regno, data)); 79 ddi_put16(ngep->io_handle, PIO_ADDR(ngep, regno), data); 80 81 } 82 83 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno); 84 #pragma inline(nge_reg_get32) 85 86 uint32_t 87 nge_reg_get32(nge_t *ngep, nge_regno_t regno) 88 { 89 NGE_TRACE(("nge_reg_get32($%p, 0x%lx)", (void *)ngep, regno)); 90 return (ddi_get32(ngep->io_handle, PIO_ADDR(ngep, regno))); 91 } 92 93 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data); 94 #pragma inline(nge_reg_put32) 95 96 void 97 nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data) 98 { 99 NGE_TRACE(("nge_reg_put32($%p, 0x%lx, 0x%x)", 100 (void *)ngep, regno, data)); 101 ddi_put32(ngep->io_handle, PIO_ADDR(ngep, regno), data); 102 103 } 104 105 106 static int nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 107 #pragma no_inline(nge_chip_peek_cfg) 108 109 static int 110 nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 111 { 112 int err; 113 uint64_t regval; 114 uint64_t regno; 115 116 NGE_TRACE(("nge_chip_peek_cfg($%p, $%p)", 117 (void *)ngep, (void *)ppd)); 118 119 err = DDI_SUCCESS; 120 regno = ppd->pp_acc_offset; 121 122 switch (ppd->pp_acc_size) { 123 case 1: 124 regval = pci_config_get8(ngep->cfg_handle, regno); 125 break; 126 127 case 2: 128 regval = pci_config_get16(ngep->cfg_handle, regno); 129 break; 130 131 case 4: 132 regval = pci_config_get32(ngep->cfg_handle, regno); 133 break; 134 135 case 8: 136 regval = pci_config_get64(ngep->cfg_handle, regno); 137 break; 138 } 139 ppd->pp_acc_data = regval; 140 return (err); 141 } 142 143 static int nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 144 145 static int 146 nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 147 { 148 int err; 149 uint64_t regval; 150 uint64_t regno; 151 152 NGE_TRACE(("nge_chip_poke_cfg($%p, $%p)", 153 (void *)ngep, (void *)ppd)); 154 155 err = DDI_SUCCESS; 156 regno = ppd->pp_acc_offset; 157 regval = ppd->pp_acc_data; 158 159 switch (ppd->pp_acc_size) { 160 case 1: 161 pci_config_put8(ngep->cfg_handle, regno, regval); 162 break; 163 164 case 2: 165 pci_config_put16(ngep->cfg_handle, regno, regval); 166 break; 167 168 case 4: 169 pci_config_put32(ngep->cfg_handle, regno, regval); 170 break; 171 172 case 8: 173 pci_config_put64(ngep->cfg_handle, regno, regval); 174 break; 175 } 176 177 return (err); 178 179 } 180 181 static int nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd); 182 183 static int 184 nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd) 185 { 186 int err; 187 uint64_t regval; 188 void *regaddr; 189 190 NGE_TRACE(("nge_chip_peek_reg($%p, $%p)", 191 (void *)ngep, (void *)ppd)); 192 193 err = DDI_SUCCESS; 194 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 195 196 switch (ppd->pp_acc_size) { 197 case 1: 198 regval = ddi_get8(ngep->io_handle, regaddr); 199 break; 200 201 case 2: 202 regval = ddi_get16(ngep->io_handle, regaddr); 203 break; 204 205 case 4: 206 regval = ddi_get32(ngep->io_handle, regaddr); 207 break; 208 209 case 8: 210 regval = ddi_get64(ngep->io_handle, regaddr); 211 break; 212 213 default: 214 regval = 0x0ull; 215 break; 216 } 217 ppd->pp_acc_data = regval; 218 return (err); 219 } 220 221 static int nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd); 222 223 static int 224 nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd) 225 { 226 int err; 227 uint64_t regval; 228 void *regaddr; 229 230 NGE_TRACE(("nge_chip_poke_reg($%p, $%p)", 231 (void *)ngep, (void *)ppd)); 232 233 err = DDI_SUCCESS; 234 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 235 regval = ppd->pp_acc_data; 236 237 switch (ppd->pp_acc_size) { 238 case 1: 239 ddi_put8(ngep->io_handle, regaddr, regval); 240 break; 241 242 case 2: 243 ddi_put16(ngep->io_handle, regaddr, regval); 244 break; 245 246 case 4: 247 ddi_put32(ngep->io_handle, regaddr, regval); 248 break; 249 250 case 8: 251 ddi_put64(ngep->io_handle, regaddr, regval); 252 break; 253 } 254 return (err); 255 } 256 257 static int nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd); 258 #pragma no_inline(nge_chip_peek_mii) 259 260 static int 261 nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd) 262 { 263 int err; 264 265 err = DDI_SUCCESS; 266 ppd->pp_acc_data = nge_mii_get16(ngep, ppd->pp_acc_offset/2); 267 return (err); 268 } 269 270 static int nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd); 271 #pragma no_inline(nge_chip_poke_mii) 272 273 static int 274 nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd) 275 { 276 int err; 277 err = DDI_SUCCESS; 278 nge_mii_put16(ngep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 279 return (err); 280 } 281 282 /* 283 * Basic SEEPROM get/set access routine 284 * 285 * This uses the chip's SEEPROM auto-access method, controlled by the 286 * Serial EEPROM Address/Data Registers at 0x504h, so the CPU 287 * doesn't have to fiddle with the individual bits. 288 * 289 * The caller should hold <genlock> and *also* have already acquired 290 * the right to access the SEEPROM. 291 * 292 * Return value: 293 * 0 on success, 294 * ENODATA on access timeout (maybe retryable: device may just be busy) 295 * EPROTO on other h/w or s/w errors. 296 * 297 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 298 * from a (successful) SEEPROM_ACCESS_READ. 299 */ 300 301 static int 302 nge_seeprom_access(nge_t *ngep, uint32_t cmd, nge_regno_t addr, uint16_t *dp) 303 { 304 uint32_t tries; 305 nge_ep_cmd cmd_reg; 306 nge_ep_data data_reg; 307 308 NGE_TRACE(("nge_seeprom_access($%p, %d, %x, $%p)", 309 (void *)ngep, cmd, addr, (void *)dp)); 310 311 ASSERT(mutex_owned(ngep->genlock)); 312 313 /* 314 * Check there's no command in progress. 315 * 316 * Note: this *shouldn't* ever find that there is a command 317 * in progress, because we already hold the <genlock> mutex. 318 * Also, to ensure we don't have a conflict with the chip's 319 * internal firmware or a process accessing the same (shared) 320 * So this is just a final consistency check: we shouldn't 321 * see EITHER the START bit (command started but not complete) 322 * OR the COMPLETE bit (command completed but not cleared). 323 */ 324 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 325 for (tries = 0; tries < 30; tries++) { 326 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 327 break; 328 drv_usecwait(10); 329 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 330 } 331 332 /* 333 * This should not happen. If so, we have to restart eeprom 334 * state machine 335 */ 336 if (tries == 30) { 337 cmd_reg.cmd_bits.sts = SEEPROM_READY; 338 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 339 drv_usecwait(10); 340 /* 341 * Polling the status bit to make assure the eeprom is ready 342 */ 343 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 344 for (tries = 0; tries < 30; tries++) { 345 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 346 break; 347 drv_usecwait(10); 348 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 349 } 350 } 351 352 /* 353 * Assemble the command ... 354 */ 355 cmd_reg.cmd_bits.addr = (uint32_t)addr; 356 cmd_reg.cmd_bits.cmd = cmd; 357 cmd_reg.cmd_bits.sts = 0; 358 359 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 360 361 /* 362 * Polling whether the access is successful. 363 * 364 */ 365 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 366 for (tries = 0; tries < 30; tries++) { 367 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 368 break; 369 drv_usecwait(10); 370 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 371 } 372 373 if (tries == 30) { 374 nge_report(ngep, NGE_HW_ROM); 375 return (DDI_FAILURE); 376 } 377 switch (cmd) { 378 default: 379 case SEEPROM_CMD_WRITE_ENABLE: 380 case SEEPROM_CMD_ERASE: 381 case SEEPROM_CMD_ERALSE_ALL: 382 case SEEPROM_CMD_WRITE_DIS: 383 break; 384 385 case SEEPROM_CMD_READ: 386 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 387 *dp = data_reg.data_bits.data; 388 break; 389 390 case SEEPROM_CMD_WRITE: 391 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 392 data_reg.data_bits.data = *dp; 393 nge_reg_put32(ngep, NGE_EP_DATA, data_reg.data_val); 394 break; 395 } 396 397 return (DDI_SUCCESS); 398 } 399 400 401 static int 402 nge_chip_peek_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 403 { 404 uint16_t data; 405 int err; 406 407 err = nge_seeprom_access(ngep, SEEPROM_CMD_READ, 408 ppd->pp_acc_offset, &data); 409 ppd->pp_acc_data = data; 410 return (err); 411 } 412 413 static int 414 nge_chip_poke_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 415 { 416 uint16_t data; 417 int err; 418 419 data = ppd->pp_acc_data; 420 err = nge_seeprom_access(ngep, SEEPROM_CMD_WRITE, 421 ppd->pp_acc_offset, &data); 422 return (err); 423 } 424 425 void 426 nge_init_dev_spec_param(nge_t *ngep) 427 { 428 nge_dev_spec_param_t *dev_param_p; 429 chip_info_t *infop; 430 431 dev_param_p = &ngep->dev_spec_param; 432 infop = (chip_info_t *)&ngep->chipinfo; 433 434 switch (infop->device) { 435 case DEVICE_ID_NF3_E6: 436 case DEVICE_ID_NF3_DF: 437 case DEVICE_ID_MCP04_37: 438 case DEVICE_ID_MCP04_38: 439 dev_param_p->msi = B_FALSE; 440 dev_param_p->msi_x = B_FALSE; 441 dev_param_p->vlan = B_FALSE; 442 dev_param_p->advanced_pm = B_FALSE; 443 dev_param_p->mac_addr_order = B_FALSE; 444 dev_param_p->tx_pause_frame = B_FALSE; 445 dev_param_p->rx_pause_frame = B_FALSE; 446 dev_param_p->jumbo = B_FALSE; 447 dev_param_p->tx_rx_64byte = B_FALSE; 448 dev_param_p->rx_hw_checksum = B_FALSE; 449 dev_param_p->tx_hw_checksum = 0; 450 dev_param_p->desc_type = DESC_OFFLOAD; 451 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 452 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 453 dev_param_p->nge_split = NGE_SPLIT_32; 454 break; 455 456 case DEVICE_ID_CK804_56: 457 case DEVICE_ID_CK804_57: 458 dev_param_p->msi = B_TRUE; 459 dev_param_p->msi_x = B_TRUE; 460 dev_param_p->vlan = B_FALSE; 461 dev_param_p->advanced_pm = B_FALSE; 462 dev_param_p->mac_addr_order = B_FALSE; 463 dev_param_p->tx_pause_frame = B_FALSE; 464 dev_param_p->rx_pause_frame = B_TRUE; 465 dev_param_p->jumbo = B_TRUE; 466 dev_param_p->tx_rx_64byte = B_FALSE; 467 dev_param_p->rx_hw_checksum = B_TRUE; 468 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 469 dev_param_p->desc_type = DESC_HOT; 470 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 471 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 472 dev_param_p->nge_split = NGE_SPLIT_96; 473 break; 474 475 case DEVICE_ID_MCP51_268: 476 case DEVICE_ID_MCP51_269: 477 dev_param_p->msi = B_FALSE; 478 dev_param_p->msi_x = B_FALSE; 479 dev_param_p->vlan = B_FALSE; 480 dev_param_p->advanced_pm = B_TRUE; 481 dev_param_p->mac_addr_order = B_FALSE; 482 dev_param_p->tx_pause_frame = B_FALSE; 483 dev_param_p->rx_pause_frame = B_FALSE; 484 dev_param_p->jumbo = B_FALSE; 485 dev_param_p->tx_rx_64byte = B_TRUE; 486 dev_param_p->rx_hw_checksum = B_FALSE; 487 dev_param_p->tx_hw_checksum = 0; 488 dev_param_p->desc_type = DESC_OFFLOAD; 489 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 490 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 491 dev_param_p->nge_split = NGE_SPLIT_32; 492 break; 493 494 case DEVICE_ID_MCP55_372: 495 case DEVICE_ID_MCP55_373: 496 dev_param_p->msi = B_TRUE; 497 dev_param_p->msi_x = B_TRUE; 498 dev_param_p->vlan = B_TRUE; 499 dev_param_p->advanced_pm = B_TRUE; 500 dev_param_p->mac_addr_order = B_FALSE; 501 dev_param_p->tx_pause_frame = B_TRUE; 502 dev_param_p->rx_pause_frame = B_TRUE; 503 dev_param_p->jumbo = B_TRUE; 504 dev_param_p->tx_rx_64byte = B_TRUE; 505 dev_param_p->rx_hw_checksum = B_TRUE; 506 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 507 dev_param_p->desc_type = DESC_HOT; 508 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 509 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 510 dev_param_p->nge_split = NGE_SPLIT_96; 511 break; 512 513 case DEVICE_ID_MCP61_3EE: 514 case DEVICE_ID_MCP61_3EF: 515 dev_param_p->msi = B_FALSE; 516 dev_param_p->msi_x = B_FALSE; 517 dev_param_p->vlan = B_FALSE; 518 dev_param_p->advanced_pm = B_TRUE; 519 dev_param_p->mac_addr_order = B_TRUE; 520 dev_param_p->tx_pause_frame = B_FALSE; 521 dev_param_p->rx_pause_frame = B_FALSE; 522 dev_param_p->jumbo = B_FALSE; 523 dev_param_p->tx_rx_64byte = B_TRUE; 524 dev_param_p->rx_hw_checksum = B_FALSE; 525 dev_param_p->tx_hw_checksum = 0; 526 dev_param_p->desc_type = DESC_OFFLOAD; 527 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 528 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 529 dev_param_p->nge_split = NGE_SPLIT_32; 530 break; 531 532 default: 533 dev_param_p->msi = B_FALSE; 534 dev_param_p->msi_x = B_FALSE; 535 dev_param_p->vlan = B_FALSE; 536 dev_param_p->advanced_pm = B_FALSE; 537 dev_param_p->mac_addr_order = B_FALSE; 538 dev_param_p->tx_pause_frame = B_FALSE; 539 dev_param_p->rx_pause_frame = B_FALSE; 540 dev_param_p->jumbo = B_FALSE; 541 dev_param_p->tx_rx_64byte = B_FALSE; 542 dev_param_p->rx_hw_checksum = B_FALSE; 543 dev_param_p->tx_hw_checksum = 0; 544 dev_param_p->desc_type = DESC_OFFLOAD; 545 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 546 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 547 dev_param_p->nge_split = NGE_SPLIT_32; 548 return; 549 } 550 } 551 /* 552 * Perform first-stage chip (re-)initialisation, using only config-space 553 * accesses: 554 * 555 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 556 * returning the data in the structure pointed to by <infop>. 557 */ 558 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset); 559 #pragma no_inline(nge_chip_cfg_init) 560 561 void 562 nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset) 563 { 564 uint16_t command; 565 ddi_acc_handle_t handle; 566 nge_interbus_conf interbus_conf; 567 nge_msi_mask_conf msi_mask_conf; 568 nge_msi_map_cap_conf cap_conf; 569 570 NGE_TRACE(("nge_chip_cfg_init($%p, $%p, %d)", 571 (void *)ngep, (void *)infop, reset)); 572 573 /* 574 * save PCI cache line size and subsystem vendor ID 575 * 576 * Read all the config-space registers that characterise the 577 * chip, specifically vendor/device/revision/subsystem vendor 578 * and subsystem device id. We expect (but don't check) that 579 */ 580 handle = ngep->cfg_handle; 581 /* reading the vendor information once */ 582 if (reset == B_FALSE) { 583 infop->command = pci_config_get16(handle, 584 PCI_CONF_COMM); 585 infop->vendor = pci_config_get16(handle, 586 PCI_CONF_VENID); 587 infop->device = pci_config_get16(handle, 588 PCI_CONF_DEVID); 589 infop->subven = pci_config_get16(handle, 590 PCI_CONF_SUBVENID); 591 infop->subdev = pci_config_get16(handle, 592 PCI_CONF_SUBSYSID); 593 infop->class_code = pci_config_get8(handle, 594 PCI_CONF_BASCLASS); 595 infop->revision = pci_config_get8(handle, 596 PCI_CONF_REVID); 597 infop->clsize = pci_config_get8(handle, 598 PCI_CONF_CACHE_LINESZ); 599 infop->latency = pci_config_get8(handle, 600 PCI_CONF_LATENCY_TIMER); 601 } 602 if (nge_enable_msi) { 603 /* Disable the hidden for MSI support */ 604 interbus_conf.conf_val = pci_config_get32(handle, 605 PCI_CONF_HT_INTERNAL); 606 if ((infop->device == DEVICE_ID_MCP55_373) || 607 (infop->device == DEVICE_ID_MCP55_372)) 608 interbus_conf.conf_bits.msix_off = NGE_SET; 609 interbus_conf.conf_bits.msi_off = NGE_CLEAR; 610 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 611 interbus_conf.conf_val); 612 613 if ((infop->device == DEVICE_ID_MCP55_373) || 614 (infop->device == DEVICE_ID_MCP55_372)) { 615 616 /* Disable the vector off for mcp55 */ 617 msi_mask_conf.msi_mask_conf_val = 618 pci_config_get32(handle, PCI_CONF_HT_MSI_MASK); 619 msi_mask_conf.msi_mask_bits.vec0_off = NGE_CLEAR; 620 msi_mask_conf.msi_mask_bits.vec1_off = NGE_CLEAR; 621 msi_mask_conf.msi_mask_bits.vec2_off = NGE_CLEAR; 622 msi_mask_conf.msi_mask_bits.vec3_off = NGE_CLEAR; 623 msi_mask_conf.msi_mask_bits.vec4_off = NGE_CLEAR; 624 msi_mask_conf.msi_mask_bits.vec5_off = NGE_CLEAR; 625 msi_mask_conf.msi_mask_bits.vec6_off = NGE_CLEAR; 626 msi_mask_conf.msi_mask_bits.vec7_off = NGE_CLEAR; 627 pci_config_put32(handle, PCI_CONF_HT_MSI_MASK, 628 msi_mask_conf.msi_mask_conf_val); 629 630 /* Enable the MSI mapping */ 631 cap_conf.msi_map_cap_conf_val = 632 pci_config_get32(handle, PCI_CONF_HT_MSI_MAP_CAP); 633 cap_conf.map_cap_conf_bits.map_en = NGE_SET; 634 pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP, 635 cap_conf.msi_map_cap_conf_val); 636 } 637 } else { 638 interbus_conf.conf_val = pci_config_get32(handle, 639 PCI_CONF_HT_INTERNAL); 640 interbus_conf.conf_bits.msi_off = NGE_SET; 641 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 642 interbus_conf.conf_val); 643 } 644 command = infop->command | PCI_COMM_MAE; 645 command &= ~PCI_COMM_MEMWR_INVAL; 646 command |= PCI_COMM_ME; 647 pci_config_put16(handle, PCI_CONF_COMM, command); 648 pci_config_put16(handle, PCI_CONF_STAT, ~0); 649 650 } 651 652 int 653 nge_chip_stop(nge_t *ngep, boolean_t fault) 654 { 655 int err; 656 uint32_t reg_val; 657 uint32_t tries; 658 nge_mintr_src mintr_src; 659 nge_mii_cs mii_cs; 660 nge_rx_poll rx_poll; 661 nge_tx_poll tx_poll; 662 nge_rx_en rx_en; 663 nge_tx_en tx_en; 664 nge_tx_sta tx_sta; 665 nge_rx_sta rx_sta; 666 nge_mode_cntl mode; 667 nge_pmu_cntl2 pmu_cntl2; 668 669 NGE_TRACE(("nge_chip_stop($%p, %d)", (void *)ngep, fault)); 670 671 err = DDI_SUCCESS; 672 673 /* Clear any pending PHY interrupt */ 674 mintr_src.src_val = nge_reg_get8(ngep, NGE_MINTR_SRC); 675 nge_reg_put8(ngep, NGE_MINTR_SRC, mintr_src.src_val); 676 677 /* Mask all interrupts */ 678 reg_val = nge_reg_get32(ngep, NGE_INTR_MASK); 679 reg_val &= ~NGE_INTR_ALL_EN; 680 nge_reg_put32(ngep, NGE_INTR_MASK, reg_val); 681 682 /* Disable auto-polling of phy */ 683 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 684 mii_cs.cs_bits.ap_en = NGE_CLEAR; 685 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 686 687 /* Reset buffer management & DMA */ 688 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 689 mode.mode_bits.dma_dis = NGE_SET; 690 mode.mode_bits.desc_type = ngep->desc_mode; 691 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 692 693 for (tries = 0; tries < 10000; tries++) { 694 drv_usecwait(10); 695 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 696 if (mode.mode_bits.dma_status == NGE_SET) 697 break; 698 } 699 if (tries == 10000) { 700 ngep->nge_chip_state = NGE_CHIP_FAULT; 701 return (DDI_FAILURE); 702 } 703 704 /* Disable rx's machine */ 705 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 706 rx_en.bits.rx_en = NGE_CLEAR; 707 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 708 709 /* Disable tx's machine */ 710 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 711 tx_en.bits.tx_en = NGE_CLEAR; 712 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 713 714 /* 715 * Clean the status of tx's state machine 716 * and Make assure the tx's channel is idle 717 */ 718 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 719 for (tries = 0; tries < 1000; tries++) { 720 if (tx_sta.sta_bits.tx_chan_sta == NGE_CLEAR) 721 break; 722 drv_usecwait(10); 723 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 724 } 725 if (tries == 1000) { 726 ngep->nge_chip_state = NGE_CHIP_FAULT; 727 return (DDI_FAILURE); 728 } 729 nge_reg_put32(ngep, NGE_TX_STA, tx_sta.sta_val); 730 731 /* 732 * Clean the status of rx's state machine 733 * and Make assure the tx's channel is idle 734 */ 735 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 736 for (tries = 0; tries < 1000; tries++) { 737 if (rx_sta.sta_bits.rx_chan_sta == NGE_CLEAR) 738 break; 739 drv_usecwait(10); 740 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 741 } 742 if (tries == 1000) { 743 ngep->nge_chip_state = NGE_CHIP_FAULT; 744 return (DDI_FAILURE); 745 } 746 nge_reg_put32(ngep, NGE_RX_STA, rx_sta.sta_val); 747 748 /* Disable auto-poll of rx's state machine */ 749 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 750 rx_poll.poll_bits.rpen = NGE_CLEAR; 751 rx_poll.poll_bits.rpi = NGE_CLEAR; 752 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 753 754 /* Disable auto-polling of tx's state machine */ 755 tx_poll.poll_val = nge_reg_get32(ngep, NGE_TX_POLL); 756 tx_poll.poll_bits.tpen = NGE_CLEAR; 757 tx_poll.poll_bits.tpi = NGE_CLEAR; 758 nge_reg_put32(ngep, NGE_TX_POLL, tx_poll.poll_val); 759 760 /* Restore buffer management */ 761 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 762 mode.mode_bits.bm_reset = NGE_SET; 763 mode.mode_bits.tx_rcom_en = NGE_SET; 764 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 765 766 if (ngep->dev_spec_param.advanced_pm) { 767 768 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 0); 769 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 0); 770 771 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 772 pmu_cntl2.cntl2_bits.cidle_timer = NGE_CLEAR; 773 pmu_cntl2.cntl2_bits.didle_timer = NGE_CLEAR; 774 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 775 } 776 if (fault) 777 ngep->nge_chip_state = NGE_CHIP_FAULT; 778 else 779 ngep->nge_chip_state = NGE_CHIP_STOPPED; 780 781 return (err); 782 } 783 784 static void 785 nge_rx_setup(nge_t *ngep) 786 { 787 uint64_t desc_addr; 788 nge_rxtx_dlen dlen; 789 nge_rx_poll rx_poll; 790 791 /* 792 * Filling the address and length of rx's descriptors 793 */ 794 desc_addr = ngep->recv->desc.cookie.dmac_laddress; 795 nge_reg_put32(ngep, NGE_RX_DADR, desc_addr); 796 nge_reg_put32(ngep, NGE_RX_DADR_HI, desc_addr >> 32); 797 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 798 dlen.dlen_bits.rdlen = ngep->recv->desc.nslots - 1; 799 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 800 801 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 802 rx_poll.poll_bits.rpi = RX_POLL_INTV_1G; 803 rx_poll.poll_bits.rpen = NGE_SET; 804 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 805 } 806 807 static void 808 nge_tx_setup(nge_t *ngep) 809 { 810 uint64_t desc_addr; 811 nge_rxtx_dlen dlen; 812 813 /* 814 * Filling the address and length of tx's descriptors 815 */ 816 desc_addr = ngep->send->desc.cookie.dmac_laddress; 817 nge_reg_put32(ngep, NGE_TX_DADR, desc_addr); 818 nge_reg_put32(ngep, NGE_TX_DADR_HI, desc_addr >> 32); 819 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 820 dlen.dlen_bits.tdlen = ngep->send->desc.nslots - 1; 821 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 822 } 823 824 static int 825 nge_buff_setup(nge_t *ngep) 826 { 827 nge_mode_cntl mode_cntl; 828 nge_dev_spec_param_t *dev_param_p; 829 830 dev_param_p = &ngep->dev_spec_param; 831 832 /* 833 * Configure Rx&Tx's buffer 834 */ 835 nge_rx_setup(ngep); 836 nge_tx_setup(ngep); 837 838 /* 839 * Configure buffer attribute 840 */ 841 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 842 843 /* 844 * Enable Dma access request 845 */ 846 mode_cntl.mode_bits.dma_dis = NGE_CLEAR; 847 848 /* 849 * Enbale Buffer management 850 */ 851 mode_cntl.mode_bits.bm_reset = NGE_CLEAR; 852 853 /* 854 * Support Standoffload Descriptor 855 */ 856 mode_cntl.mode_bits.desc_type = ngep->desc_mode; 857 858 /* 859 * Support receive hardware checksum 860 */ 861 if (dev_param_p->rx_hw_checksum) { 862 mode_cntl.mode_bits.rx_sum_en = NGE_SET; 863 } else 864 mode_cntl.mode_bits.rx_sum_en = NGE_CLEAR; 865 866 /* 867 * Disable Tx PRD coarse update 868 */ 869 mode_cntl.mode_bits.tx_prd_cu_en = NGE_CLEAR; 870 871 /* 872 * Disable 64-byte access 873 */ 874 mode_cntl.mode_bits.w64_dis = NGE_SET; 875 876 /* 877 * Skip Rx Error Frame is not supported and if 878 * enable it, jumbo frame does not work any more. 879 */ 880 mode_cntl.mode_bits.rx_filter_en = NGE_CLEAR; 881 882 /* 883 * Can not support hot mode now 884 */ 885 mode_cntl.mode_bits.resv15 = NGE_CLEAR; 886 887 if (dev_param_p->vlan) { 888 /* Disable the vlan strip for devices which support vlan */ 889 mode_cntl.mode_bits.vlan_strip = NGE_CLEAR; 890 891 /* Disable the vlan insert for devices which supprot vlan */ 892 mode_cntl.mode_bits.vlan_ins = NGE_CLEAR; 893 } 894 895 if (dev_param_p->tx_rx_64byte) { 896 897 /* Set the maximum TX PRD fetch size to 64 bytes */ 898 mode_cntl.mode_bits.tx_fetch_prd = NGE_SET; 899 900 /* Set the maximum RX PRD fetch size to 64 bytes */ 901 mode_cntl.mode_bits.rx_fetch_prd = NGE_SET; 902 } 903 /* 904 * Upload Rx data as it arrives, rather than waiting for full frame 905 */ 906 mode_cntl.mode_bits.resv16 = NGE_CLEAR; 907 908 /* 909 * Normal HOT table accesses 910 */ 911 mode_cntl.mode_bits.resv17 = NGE_CLEAR; 912 913 /* 914 * Normal HOT buffer requesting 915 */ 916 mode_cntl.mode_bits.resv18 = NGE_CLEAR; 917 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 918 919 /* 920 * Signal controller to check for new Rx descriptors 921 */ 922 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 923 mode_cntl.mode_bits.rxdm = NGE_SET; 924 mode_cntl.mode_bits.tx_rcom_en = NGE_SET; 925 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 926 927 928 return (DDI_SUCCESS); 929 } 930 931 /* 932 * When chipset resets, the chipset can not restore the orignial 933 * mac address to the mac address registers. 934 * 935 * When the driver is dettached, the function will write the orignial 936 * mac address to the mac address registers. 937 */ 938 939 void 940 nge_restore_mac_addr(nge_t *ngep) 941 { 942 uint32_t mac_addr; 943 944 mac_addr = (uint32_t)ngep->chipinfo.hw_mac_addr; 945 nge_reg_put32(ngep, NGE_UNI_ADDR0, mac_addr); 946 mac_addr = (uint32_t)(ngep->chipinfo.hw_mac_addr >> 32); 947 nge_reg_put32(ngep, NGE_UNI_ADDR1, mac_addr); 948 } 949 950 int 951 nge_chip_reset(nge_t *ngep) 952 { 953 int err; 954 uint8_t i; 955 uint32_t regno; 956 uint64_t mac = 0; 957 uint64_t mac_tmp = 0; 958 nge_uni_addr1 uaddr1; 959 nge_cp_cntl ee_cntl; 960 nge_soft_misc soft_misc; 961 nge_pmu_cntl0 pmu_cntl0; 962 nge_pmu_cntl2 pmu_cntl2; 963 nge_pm_cntl2 pm_cntl2; 964 const nge_ksindex_t *ksip; 965 966 NGE_TRACE(("nge_chip_reset($%p)", (void *)ngep)); 967 968 /* 969 * Clear the statistics by reading the statistics register 970 */ 971 for (ksip = nge_statistics; ksip->name != NULL; ++ksip) { 972 regno = KS_BASE + ksip->index * sizeof (uint32_t); 973 (void) nge_reg_get32(ngep, regno); 974 } 975 976 /* 977 * Setup seeprom control 978 */ 979 ee_cntl.cntl_val = nge_reg_get32(ngep, NGE_EP_CNTL); 980 ee_cntl.cntl_bits.clkdiv = EEPROM_CLKDIV; 981 ee_cntl.cntl_bits.rom_size = EEPROM_32K; 982 ee_cntl.cntl_bits.word_wid = ACCESS_16BIT; 983 ee_cntl.cntl_bits.wait_slots = EEPROM_WAITCLK; 984 nge_reg_put32(ngep, NGE_EP_CNTL, ee_cntl.cntl_val); 985 986 /* 987 * Reading the unicast mac address table 988 */ 989 if (ngep->nge_chip_state == NGE_CHIP_INITIAL) { 990 uaddr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 991 mac = uaddr1.addr_bits.addr; 992 mac <<= 32; 993 mac |= nge_reg_get32(ngep, NGE_UNI_ADDR0); 994 if (mac != 0ULL && mac != ~0ULL) { 995 /* 996 * workaround for the MAC address reversed issue 997 * on some motherboards 998 */ 999 if (ngep->dev_spec_param.mac_addr_order && 1000 (ngep->mac_addr_reversion || 1001 (mac & LOW_24BITS_MASK) == REVERSE_MAC_ELITE || 1002 (mac & LOW_24BITS_MASK) == REVERSE_MAC_GIGABYTE || 1003 (mac & LOW_24BITS_MASK) == REVERSE_MAC_ASUS)) { 1004 for (i = 0; i < ETHERADDRL; i ++) { 1005 mac_tmp <<= 8; 1006 mac_tmp += (mac & 0xffULL); 1007 mac >>= 8; 1008 } 1009 mac = mac_tmp; 1010 nge_reg_put32(ngep, 1011 NGE_UNI_ADDR0, (uint32_t)mac); 1012 nge_reg_put32(ngep, 1013 NGE_UNI_ADDR1, (uint32_t)(mac>>32)); 1014 } 1015 1016 ngep->chipinfo.hw_mac_addr = mac; 1017 for (i = ETHERADDRL; i-- != 0; ) { 1018 ngep->chipinfo.vendor_addr.addr[i] = 1019 (uchar_t)mac; 1020 ngep->cur_uni_addr.addr[i] = (uchar_t)mac; 1021 mac >>= 8; 1022 } 1023 ngep->chipinfo.vendor_addr.set = 1; 1024 } 1025 } 1026 pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ, 1027 ngep->chipinfo.clsize); 1028 pci_config_put8(ngep->cfg_handle, PCI_CONF_LATENCY_TIMER, 1029 ngep->chipinfo.latency); 1030 1031 1032 if (ngep->dev_spec_param.advanced_pm) { 1033 1034 /* Program software misc register */ 1035 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1036 soft_misc.misc_bits.rx_clk_vx_rst = NGE_SET; 1037 soft_misc.misc_bits.tx_clk_vx_rst = NGE_SET; 1038 soft_misc.misc_bits.clk12m_vx_rst = NGE_SET; 1039 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_SET; 1040 soft_misc.misc_bits.rx_clk_vc_rst = NGE_SET; 1041 soft_misc.misc_bits.tx_clk_vc_rst = NGE_SET; 1042 soft_misc.misc_bits.fs_clk_vc_rst = NGE_SET; 1043 soft_misc.misc_bits.rst_ex_m2pintf = NGE_SET; 1044 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1045 1046 /* wait for 32 us */ 1047 drv_usecwait(32); 1048 1049 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1050 soft_misc.misc_bits.rx_clk_vx_rst = NGE_CLEAR; 1051 soft_misc.misc_bits.tx_clk_vx_rst = NGE_CLEAR; 1052 soft_misc.misc_bits.clk12m_vx_rst = NGE_CLEAR; 1053 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_CLEAR; 1054 soft_misc.misc_bits.rx_clk_vc_rst = NGE_CLEAR; 1055 soft_misc.misc_bits.tx_clk_vc_rst = NGE_CLEAR; 1056 soft_misc.misc_bits.fs_clk_vc_rst = NGE_CLEAR; 1057 soft_misc.misc_bits.rst_ex_m2pintf = NGE_CLEAR; 1058 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1059 1060 /* Program PMU registers */ 1061 pmu_cntl0.cntl0_val = nge_reg_get32(ngep, NGE_PMU_CNTL0); 1062 pmu_cntl0.cntl0_bits.core_spd10_fp = 1063 NGE_PMU_CORE_SPD10_BUSY; 1064 pmu_cntl0.cntl0_bits.core_spd10_idle = 1065 NGE_PMU_CORE_SPD10_IDLE; 1066 pmu_cntl0.cntl0_bits.core_spd100_fp = 1067 NGE_PMU_CORE_SPD100_BUSY; 1068 pmu_cntl0.cntl0_bits.core_spd100_idle = 1069 NGE_PMU_CORE_SPD100_IDLE; 1070 pmu_cntl0.cntl0_bits.core_spd1000_fp = 1071 NGE_PMU_CORE_SPD1000_BUSY; 1072 pmu_cntl0.cntl0_bits.core_spd1000_idle = 1073 NGE_PMU_CORE_SPD100_IDLE; 1074 pmu_cntl0.cntl0_bits.core_spd10_idle = 1075 NGE_PMU_CORE_SPD10_IDLE; 1076 nge_reg_put32(ngep, NGE_PMU_CNTL0, pmu_cntl0.cntl0_val); 1077 1078 /* Set the core idle limit value */ 1079 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 1080 NGE_PMU_CIDLE_LIMIT_DEF); 1081 1082 /* Set the device idle limit value */ 1083 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 1084 NGE_PMU_DIDLE_LIMIT_DEF); 1085 1086 /* Enable the core/device idle timer in PMU control 2 */ 1087 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 1088 pmu_cntl2.cntl2_bits.cidle_timer = NGE_SET; 1089 pmu_cntl2.cntl2_bits.didle_timer = NGE_SET; 1090 pmu_cntl2.cntl2_bits.core_enable = NGE_SET; 1091 pmu_cntl2.cntl2_bits.dev_enable = NGE_SET; 1092 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 1093 } 1094 /* 1095 * Stop the chipset and clear buffer management 1096 */ 1097 err = nge_chip_stop(ngep, B_FALSE); 1098 if (err == DDI_FAILURE) 1099 return (err); 1100 /* 1101 * Clear the power state bits for phy since interface no longer 1102 * works after rebooting from Windows on a multi-boot machine 1103 */ 1104 if (ngep->chipinfo.device == DEVICE_ID_MCP51_268 || 1105 ngep->chipinfo.device == DEVICE_ID_MCP51_269 || 1106 ngep->chipinfo.device == DEVICE_ID_MCP55_372 || 1107 ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1108 ngep->chipinfo.device == DEVICE_ID_MCP61_3EE || 1109 ngep->chipinfo.device == DEVICE_ID_MCP61_3EF) { 1110 1111 pm_cntl2.cntl_val = nge_reg_get32(ngep, NGE_PM_CNTL2); 1112 /* bring phy out of coma mode */ 1113 pm_cntl2.cntl_bits.phy_coma_set = NGE_CLEAR; 1114 /* disable auto reset coma bits */ 1115 pm_cntl2.cntl_bits.resv4 = NGE_CLEAR; 1116 /* restore power to gated clocks */ 1117 pm_cntl2.cntl_bits.resv8_11 = NGE_CLEAR; 1118 nge_reg_put32(ngep, NGE_PM_CNTL2, pm_cntl2.cntl_val); 1119 } 1120 1121 /* 1122 * Reset the external phy 1123 */ 1124 if (!nge_phy_reset(ngep)) 1125 return (DDI_FAILURE); 1126 ngep->nge_chip_state = NGE_CHIP_RESET; 1127 return (DDI_SUCCESS); 1128 } 1129 1130 int 1131 nge_chip_start(nge_t *ngep) 1132 { 1133 int err; 1134 nge_itc itc; 1135 nge_tx_cntl tx_cntl; 1136 nge_rx_cntrl0 rx_cntl0; 1137 nge_rx_cntl1 rx_cntl1; 1138 nge_tx_en tx_en; 1139 nge_rx_en rx_en; 1140 nge_mii_cs mii_cs; 1141 nge_swtr_cntl swtr_cntl; 1142 nge_rx_fifo_wm rx_fifo; 1143 nge_intr_mask intr_mask; 1144 nge_mintr_mask mintr_mask; 1145 nge_dev_spec_param_t *dev_param_p; 1146 1147 NGE_TRACE(("nge_chip_start($%p)", (void *)ngep)); 1148 1149 /* 1150 * Setup buffer management 1151 */ 1152 err = nge_buff_setup(ngep); 1153 if (err == DDI_FAILURE) 1154 return (err); 1155 1156 dev_param_p = &ngep->dev_spec_param; 1157 1158 /* 1159 * Enable polling attribute 1160 */ 1161 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 1162 mii_cs.cs_bits.ap_paddr = ngep->phy_xmii_addr; 1163 mii_cs.cs_bits.ap_en = NGE_SET; 1164 mii_cs.cs_bits.ap_intv = MII_POLL_INTV; 1165 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 1166 1167 /* 1168 * Setup link 1169 */ 1170 (*ngep->physops->phys_update)(ngep); 1171 1172 /* 1173 * Configure the tx's parameters 1174 */ 1175 tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL); 1176 if (dev_param_p->tx_pause_frame) 1177 tx_cntl.cntl_bits.paen = NGE_SET; 1178 else 1179 tx_cntl.cntl_bits.paen = NGE_CLEAR; 1180 tx_cntl.cntl_bits.retry_en = NGE_SET; 1181 tx_cntl.cntl_bits.pad_en = NGE_SET; 1182 tx_cntl.cntl_bits.fappend_en = NGE_SET; 1183 tx_cntl.cntl_bits.two_def_en = NGE_SET; 1184 tx_cntl.cntl_bits.max_retry = 15; 1185 tx_cntl.cntl_bits.burst_en = NGE_CLEAR; 1186 tx_cntl.cntl_bits.uflo_err_mask = NGE_CLEAR; 1187 tx_cntl.cntl_bits.tlcol_mask = NGE_CLEAR; 1188 tx_cntl.cntl_bits.lcar_mask = NGE_CLEAR; 1189 tx_cntl.cntl_bits.def_mask = NGE_CLEAR; 1190 tx_cntl.cntl_bits.exdef_mask = NGE_SET; 1191 tx_cntl.cntl_bits.lcar_mask = NGE_SET; 1192 tx_cntl.cntl_bits.tlcol_mask = NGE_SET; 1193 tx_cntl.cntl_bits.uflo_err_mask = NGE_SET; 1194 tx_cntl.cntl_bits.jam_seq_en = NGE_CLEAR; 1195 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val); 1196 1197 1198 /* 1199 * Configure the parameters of Rx's state machine 1200 * Enabe the parameters: 1201 * 1). Pad Strip 1202 * 2). FCS Relay 1203 * 3). Pause 1204 * 4). Address filter 1205 * 5). Runt Packet receive 1206 * 6). Broadcast 1207 * 7). Receive Deferral 1208 * 1209 * Disable the following parameters for decreasing 1210 * the number of interrupts: 1211 * 1). Runt Inerrupt. 1212 * 2). Rx's Late Collision interrupt. 1213 * 3). Rx's Max length Error Interrupt. 1214 * 4). Rx's Length Field error Interrupt. 1215 * 5). Rx's FCS error interrupt. 1216 * 6). Rx's overflow error interrupt. 1217 * 7). Rx's Frame alignment error interrupt. 1218 */ 1219 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1220 rx_cntl0.cntl_bits.padsen = NGE_CLEAR; 1221 rx_cntl0.cntl_bits.fcsren = NGE_CLEAR; 1222 if (dev_param_p->rx_pause_frame) 1223 rx_cntl0.cntl_bits.paen = NGE_SET; 1224 else 1225 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1226 rx_cntl0.cntl_bits.lben = NGE_CLEAR; 1227 rx_cntl0.cntl_bits.afen = NGE_SET; 1228 rx_cntl0.cntl_bits.runten = NGE_CLEAR; 1229 rx_cntl0.cntl_bits.brdis = NGE_CLEAR; 1230 rx_cntl0.cntl_bits.rdfen = NGE_CLEAR; 1231 rx_cntl0.cntl_bits.runtm = NGE_CLEAR; 1232 rx_cntl0.cntl_bits.slfb = NGE_CLEAR; 1233 rx_cntl0.cntl_bits.rlcolm = NGE_CLEAR; 1234 rx_cntl0.cntl_bits.maxerm = NGE_CLEAR; 1235 rx_cntl0.cntl_bits.lferm = NGE_CLEAR; 1236 rx_cntl0.cntl_bits.crcm = NGE_CLEAR; 1237 rx_cntl0.cntl_bits.ofolm = NGE_CLEAR; 1238 rx_cntl0.cntl_bits.framerm = NGE_CLEAR; 1239 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1240 1241 /* 1242 * Configure the watermark for the rx's statemachine 1243 */ 1244 rx_fifo.wm_val = nge_reg_get32(ngep, NGE_RX_FIFO_WM); 1245 rx_fifo.wm_bits.data_hwm = ngep->rx_datahwm; 1246 rx_fifo.wm_bits.prd_lwm = ngep->rx_prdlwm; 1247 rx_fifo.wm_bits.prd_hwm = ngep->rx_prdhwm; 1248 nge_reg_put32(ngep, NGE_RX_FIFO_WM, rx_fifo.wm_val); 1249 1250 /* 1251 * Configure the deffer time slot for rx's state machine 1252 */ 1253 nge_reg_put8(ngep, NGE_RX_DEf, ngep->rx_def); 1254 1255 /* 1256 * Configure the length of rx's packet 1257 */ 1258 rx_cntl1.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL1); 1259 rx_cntl1.cntl_bits.length = ngep->max_sdu; 1260 nge_reg_put32(ngep, NGE_RX_CNTL1, rx_cntl1.cntl_val); 1261 /* 1262 * Enable Tx's state machine 1263 */ 1264 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 1265 tx_en.bits.tx_en = NGE_SET; 1266 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 1267 1268 /* 1269 * Enable Rx's state machine 1270 */ 1271 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 1272 rx_en.bits.rx_en = NGE_SET; 1273 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 1274 1275 itc.itc_val = nge_reg_get32(ngep, NGE_SWTR_ITC); 1276 itc.itc_bits.sw_intv = ngep->sw_intr_intv; 1277 nge_reg_put32(ngep, NGE_SWTR_ITC, itc.itc_val); 1278 1279 swtr_cntl.ctrl_val = nge_reg_get8(ngep, NGE_SWTR_CNTL); 1280 swtr_cntl.cntl_bits.sten = NGE_SET; 1281 swtr_cntl.cntl_bits.stren = NGE_SET; 1282 nge_reg_put32(ngep, NGE_SWTR_CNTL, swtr_cntl.ctrl_val); 1283 1284 /* 1285 * Disable all mii read/write operation Interrupt 1286 */ 1287 mintr_mask.mask_val = nge_reg_get8(ngep, NGE_MINTR_MASK); 1288 mintr_mask.mask_bits.mrei = NGE_CLEAR; 1289 mintr_mask.mask_bits.mcc2 = NGE_CLEAR; 1290 mintr_mask.mask_bits.mcc1 = NGE_CLEAR; 1291 mintr_mask.mask_bits.mapi = NGE_SET; 1292 mintr_mask.mask_bits.mpdi = NGE_SET; 1293 nge_reg_put8(ngep, NGE_MINTR_MASK, mintr_mask.mask_val); 1294 1295 /* 1296 * Enable all interrupt event 1297 */ 1298 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1299 intr_mask.mask_bits.reint = NGE_SET; 1300 intr_mask.mask_bits.rcint = NGE_SET; 1301 intr_mask.mask_bits.miss = NGE_SET; 1302 intr_mask.mask_bits.teint = NGE_CLEAR; 1303 intr_mask.mask_bits.tcint = NGE_SET; 1304 intr_mask.mask_bits.stint = NGE_CLEAR; 1305 intr_mask.mask_bits.mint = NGE_CLEAR; 1306 intr_mask.mask_bits.rfint = NGE_CLEAR; 1307 intr_mask.mask_bits.tfint = NGE_CLEAR; 1308 intr_mask.mask_bits.feint = NGE_SET; 1309 intr_mask.mask_bits.resv10 = NGE_CLEAR; 1310 intr_mask.mask_bits.resv11 = NGE_CLEAR; 1311 intr_mask.mask_bits.resv12 = NGE_CLEAR; 1312 intr_mask.mask_bits.resv13 = NGE_CLEAR; 1313 intr_mask.mask_bits.phyint = NGE_CLEAR; 1314 ngep->intr_masks = intr_mask.mask_val; 1315 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1316 ngep->nge_chip_state = NGE_CHIP_RUNNING; 1317 return (DDI_SUCCESS); 1318 } 1319 1320 /* 1321 * nge_chip_sync() -- program the chip with the unicast MAC address, 1322 * the multicast hash table, the required level of promiscuity. 1323 */ 1324 void 1325 nge_chip_sync(nge_t *ngep) 1326 { 1327 uint8_t i; 1328 uint64_t macaddr; 1329 uint64_t mul_addr; 1330 uint64_t mul_mask; 1331 nge_rx_cntrl0 rx_cntl; 1332 nge_uni_addr1 uni_adr1; 1333 1334 NGE_TRACE(("nge_chip_sync($%p)", (void *)ngep)); 1335 1336 macaddr = 0x0ull; 1337 mul_addr = 0x0ull; 1338 mul_mask = 0x0ull; 1339 rx_cntl.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1340 1341 if (ngep->promisc) { 1342 rx_cntl.cntl_bits.afen = NGE_CLEAR; 1343 rx_cntl.cntl_bits.brdis = NGE_SET; 1344 } else { 1345 rx_cntl.cntl_bits.afen = NGE_SET; 1346 rx_cntl.cntl_bits.brdis = NGE_CLEAR; 1347 } 1348 1349 /* 1350 * Transform the MAC address from host to chip format, the unicast 1351 * MAC address(es) ... 1352 */ 1353 for (i = ETHERADDRL, macaddr = 0ull; i != 0; --i) { 1354 macaddr |= ngep->cur_uni_addr.addr[i-1]; 1355 macaddr <<= (i > 1) ? 8 : 0; 1356 } 1357 1358 nge_reg_put32(ngep, NGE_UNI_ADDR0, (uint32_t)macaddr); 1359 macaddr = macaddr >>32; 1360 uni_adr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 1361 uni_adr1.addr_bits.addr = (uint16_t)macaddr; 1362 uni_adr1.addr_bits.resv16_31 = (uint16_t)0; 1363 nge_reg_put32(ngep, NGE_UNI_ADDR1, uni_adr1.addr_val); 1364 1365 /* 1366 * Reprogram the multicast address table ... 1367 */ 1368 for (i = ETHERADDRL, mul_addr = 0ull; i != 0; --i) { 1369 mul_addr |= ngep->cur_mul_addr.addr[i-1]; 1370 mul_addr <<= (i > 1) ? 8 : 0; 1371 mul_mask |= ngep->cur_mul_mask.addr[i-1]; 1372 mul_mask <<= (i > 1) ? 8 : 0; 1373 } 1374 nge_reg_put32(ngep, NGE_MUL_ADDR0, (uint32_t)mul_addr); 1375 mul_addr >>= 32; 1376 nge_reg_put32(ngep, NGE_MUL_ADDR1, mul_addr); 1377 nge_reg_put32(ngep, NGE_MUL_MASK, (uint32_t)mul_mask); 1378 mul_mask >>= 32; 1379 nge_reg_put32(ngep, NGE_MUL_MASK1, mul_mask); 1380 /* 1381 * Set or clear the PROMISCUOUS mode bit 1382 */ 1383 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl.cntl_val); 1384 /* 1385 * For internal PHY loopback, the link will 1386 * not be up, so it need to sync mac modes directly. 1387 */ 1388 if (ngep->param_loop_mode == NGE_LOOP_INTERNAL_PHY) 1389 nge_sync_mac_modes(ngep); 1390 } 1391 1392 static void 1393 nge_chip_err(nge_t *ngep) 1394 { 1395 nge_reg010 reg010_ins; 1396 nge_sw_statistics_t *psw_stat; 1397 nge_intr_mask intr_mask; 1398 1399 NGE_TRACE(("nge_chip_err($%p)", (void *)ngep)); 1400 1401 psw_stat = (nge_sw_statistics_t *)&ngep->statistics.sw_statistics; 1402 reg010_ins.reg010_val = nge_reg_get32(ngep, NGE_REG010); 1403 if (reg010_ins.reg010_bits.resv0) 1404 psw_stat->fe_err.tso_err_mss ++; 1405 1406 if (reg010_ins.reg010_bits.resv1) 1407 psw_stat->fe_err.tso_dis ++; 1408 1409 if (reg010_ins.reg010_bits.resv2) 1410 psw_stat->fe_err.tso_err_nosum ++; 1411 1412 if (reg010_ins.reg010_bits.resv3) 1413 psw_stat->fe_err.tso_err_hov ++; 1414 1415 if (reg010_ins.reg010_bits.resv4) 1416 psw_stat->fe_err.tso_err_huf ++; 1417 1418 if (reg010_ins.reg010_bits.resv5) 1419 psw_stat->fe_err.tso_err_l2 ++; 1420 1421 if (reg010_ins.reg010_bits.resv6) 1422 psw_stat->fe_err.tso_err_ip ++; 1423 1424 if (reg010_ins.reg010_bits.resv7) 1425 psw_stat->fe_err.tso_err_l4 ++; 1426 1427 if (reg010_ins.reg010_bits.resv8) 1428 psw_stat->fe_err.tso_err_tcp ++; 1429 1430 if (reg010_ins.reg010_bits.resv9) 1431 psw_stat->fe_err.hsum_err_ip ++; 1432 1433 if (reg010_ins.reg010_bits.resv10) 1434 psw_stat->fe_err.hsum_err_l4 ++; 1435 1436 if (reg010_ins.reg010_val != 0) { 1437 1438 /* 1439 * Fatal error is triggered by malformed driver commands. 1440 * Disable unless debugging. 1441 */ 1442 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1443 intr_mask.mask_bits.feint = NGE_CLEAR; 1444 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1445 ngep->intr_masks = intr_mask.mask_val; 1446 1447 } 1448 } 1449 1450 static void 1451 nge_sync_mac_modes(nge_t *ngep) 1452 { 1453 nge_tx_def tx_def; 1454 nge_tx_fifo_wm tx_fifo; 1455 nge_bkoff_cntl bk_cntl; 1456 nge_mac2phy m2p; 1457 nge_rx_cntrl0 rx_cntl0; 1458 nge_dev_spec_param_t *dev_param_p; 1459 1460 dev_param_p = &ngep->dev_spec_param; 1461 1462 tx_def.def_val = nge_reg_get32(ngep, NGE_TX_DEF); 1463 m2p.m2p_val = nge_reg_get32(ngep, NGE_MAC2PHY); 1464 tx_fifo.wm_val = nge_reg_get32(ngep, NGE_TX_FIFO_WM); 1465 bk_cntl.cntl_val = nge_reg_get32(ngep, NGE_BKOFF_CNTL); 1466 bk_cntl.bkoff_bits.rseed = BKOFF_RSEED; 1467 switch (ngep->param_link_speed) { 1468 case 10: 1469 m2p.m2p_bits.speed = low_speed; 1470 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1471 if (ngep->phy_mode == RGMII_IN) { 1472 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1473 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1474 } else { 1475 tx_def.def_bits.if_def = TX_TIFG_MII; 1476 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1477 } 1478 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1479 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1480 break; 1481 1482 case 100: 1483 m2p.m2p_bits.speed = fast_speed; 1484 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1485 if (ngep->phy_mode == RGMII_IN) { 1486 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1487 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1488 } else { 1489 tx_def.def_bits.if_def = TX_TIFG_MII; 1490 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1491 } 1492 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1493 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1494 break; 1495 1496 case 1000: 1497 m2p.m2p_bits.speed = giga_speed; 1498 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1499 if (ngep->param_link_duplex == LINK_DUPLEX_FULL) { 1500 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1501 tx_def.def_bits.if_def = TX_IFG_RGMII_1000_FD; 1502 } else { 1503 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1504 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1505 } 1506 1507 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_GMII; 1508 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_GMII; 1509 break; 1510 } 1511 1512 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1513 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 1514 m2p.m2p_bits.phyintr = NGE_CLEAR; 1515 m2p.m2p_bits.phyintrlvl = NGE_CLEAR; 1516 } 1517 if (ngep->param_link_duplex == LINK_DUPLEX_HALF) { 1518 m2p.m2p_bits.hdup_en = NGE_SET; 1519 } 1520 else 1521 m2p.m2p_bits.hdup_en = NGE_CLEAR; 1522 nge_reg_put32(ngep, NGE_MAC2PHY, m2p.m2p_val); 1523 nge_reg_put32(ngep, NGE_TX_DEF, tx_def.def_val); 1524 1525 tx_fifo.wm_bits.data_lwm = TX_FIFO_DATA_LWM; 1526 tx_fifo.wm_bits.prd_lwm = TX_FIFO_PRD_LWM; 1527 tx_fifo.wm_bits.uprd_hwm = TX_FIFO_PRD_HWM; 1528 tx_fifo.wm_bits.fb_wm = TX_FIFO_TBFW; 1529 nge_reg_put32(ngep, NGE_TX_FIFO_WM, tx_fifo.wm_val); 1530 1531 nge_reg_put32(ngep, NGE_BKOFF_CNTL, bk_cntl.cntl_val); 1532 1533 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1534 if (ngep->param_link_rx_pause && dev_param_p->rx_pause_frame) 1535 rx_cntl0.cntl_bits.paen = NGE_SET; 1536 else 1537 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1538 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1539 } 1540 1541 /* 1542 * Handler for hardware link state change. 1543 * 1544 * When this routine is called, the hardware link state has changed 1545 * and the new state is reflected in the param_* variables. Here 1546 * we must update the softstate, reprogram the MAC to match, and 1547 * record the change in the log and/or on the console. 1548 */ 1549 static void 1550 nge_factotum_link_handler(nge_t *ngep) 1551 { 1552 /* 1553 * Update the s/w link_state 1554 */ 1555 if (ngep->param_link_up) 1556 ngep->link_state = LINK_STATE_UP; 1557 else 1558 ngep->link_state = LINK_STATE_DOWN; 1559 1560 /* 1561 * Reprogram the MAC modes to match 1562 */ 1563 nge_sync_mac_modes(ngep); 1564 } 1565 1566 static boolean_t 1567 nge_factotum_link_check(nge_t *ngep) 1568 { 1569 boolean_t lchg; 1570 boolean_t check; 1571 1572 ASSERT(mutex_owned(ngep->genlock)); 1573 1574 (*ngep->physops->phys_check)(ngep); 1575 switch (ngep->link_state) { 1576 case LINK_STATE_UP: 1577 lchg = (ngep->param_link_up == B_FALSE); 1578 check = (ngep->param_link_up == B_FALSE); 1579 break; 1580 1581 case LINK_STATE_DOWN: 1582 lchg = (ngep->param_link_up == B_TRUE); 1583 check = (ngep->param_link_up == B_TRUE); 1584 break; 1585 1586 default: 1587 check = B_TRUE; 1588 break; 1589 } 1590 1591 /* 1592 * If <check> is false, we're sure the link hasn't changed. 1593 * If true, however, it's not yet definitive; we have to call 1594 * nge_phys_check() to determine whether the link has settled 1595 * into a new state yet ... and if it has, then call the link 1596 * state change handler.But when the chip is 5700 in Dell 6650 1597 * ,even if check is false, the link may have changed.So we 1598 * have to call nge_phys_check() to determine the link state. 1599 */ 1600 if (check) 1601 nge_factotum_link_handler(ngep); 1602 1603 return (lchg); 1604 } 1605 1606 /* 1607 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1608 */ 1609 static boolean_t nge_factotum_stall_check(nge_t *ngep); 1610 1611 static boolean_t 1612 nge_factotum_stall_check(nge_t *ngep) 1613 { 1614 uint32_t dogval; 1615 /* 1616 * Specific check for Tx stall ... 1617 * 1618 * The 'watchdog' counter is incremented whenever a packet 1619 * is queued, reset to 1 when some (but not all) buffers 1620 * are reclaimed, reset to 0 (disabled) when all buffers 1621 * are reclaimed, and shifted left here. If it exceeds the 1622 * threshold value, the chip is assumed to have stalled and 1623 * is put into the ERROR state. The factotum will then reset 1624 * it on the next pass. 1625 * 1626 * All of which should ensure that we don't get into a state 1627 * where packets are left pending indefinitely! 1628 */ 1629 dogval = nge_atomic_shl32(&ngep->watchdog, 1); 1630 if (dogval < nge_watchdog_count) { 1631 ngep->stall_cknum = 0; 1632 } else { 1633 ngep->stall_cknum++; 1634 } 1635 if (ngep->stall_cknum < 16) { 1636 return (B_FALSE); 1637 } else { 1638 ngep->stall_cknum = 0; 1639 ngep->statistics.sw_statistics.tx_stall++; 1640 return (B_TRUE); 1641 } 1642 } 1643 1644 1645 1646 /* 1647 * The factotum is woken up when there's something to do that we'd rather 1648 * not do from inside a hardware interrupt handler or high-level cyclic. 1649 * Its two main tasks are: 1650 * reset & restart the chip after an error 1651 * check the link status whenever necessary 1652 */ 1653 /* ARGSUSED */ 1654 uint_t 1655 nge_chip_factotum(caddr_t args1, caddr_t args2) 1656 { 1657 uint_t result; 1658 nge_t *ngep; 1659 boolean_t err; 1660 boolean_t linkchg; 1661 1662 ngep = (nge_t *)args1; 1663 1664 NGE_TRACE(("nge_chip_factotum($%p)", (void *)ngep)); 1665 1666 mutex_enter(ngep->softlock); 1667 if (ngep->factotum_flag == 0) { 1668 mutex_exit(ngep->softlock); 1669 return (DDI_INTR_UNCLAIMED); 1670 } 1671 ngep->factotum_flag = 0; 1672 mutex_exit(ngep->softlock); 1673 err = B_FALSE; 1674 linkchg = B_FALSE; 1675 result = DDI_INTR_CLAIMED; 1676 1677 mutex_enter(ngep->genlock); 1678 switch (ngep->nge_chip_state) { 1679 default: 1680 break; 1681 1682 case NGE_CHIP_RUNNING: 1683 linkchg = nge_factotum_link_check(ngep); 1684 err = nge_factotum_stall_check(ngep); 1685 break; 1686 1687 case NGE_CHIP_FAULT: 1688 (void) nge_restart(ngep); 1689 NGE_REPORT((ngep, "automatic recovery activated")); 1690 break; 1691 } 1692 1693 if (err) 1694 (void) nge_chip_stop(ngep, B_TRUE); 1695 mutex_exit(ngep->genlock); 1696 1697 /* 1698 * If the link state changed, tell the world about it (if 1699 * this version of MAC supports link state notification). 1700 * Note: can't do this while still holding the mutex. 1701 */ 1702 if (linkchg) 1703 mac_link_update(ngep->mh, ngep->link_state); 1704 1705 return (result); 1706 1707 } 1708 1709 static void 1710 nge_intr_handle(nge_t *ngep, nge_intr_src *pintr_src) 1711 { 1712 boolean_t brx; 1713 boolean_t btx; 1714 nge_mintr_src mintr_src; 1715 1716 brx = B_FALSE; 1717 btx = B_FALSE; 1718 ngep->statistics.sw_statistics.intr_count++; 1719 ngep->statistics.sw_statistics.intr_lval = pintr_src->intr_val; 1720 brx = (pintr_src->int_bits.reint | pintr_src->int_bits.miss 1721 | pintr_src->int_bits.rcint | pintr_src->int_bits.stint) 1722 != 0 ? B_TRUE : B_FALSE; 1723 if (pintr_src->int_bits.reint) 1724 ngep->statistics.sw_statistics.rx_err++; 1725 if (pintr_src->int_bits.miss) 1726 ngep->statistics.sw_statistics.rx_nobuffer++; 1727 1728 btx = (pintr_src->int_bits.teint | pintr_src->int_bits.tcint) 1729 != 0 ? B_TRUE : B_FALSE; 1730 if (pintr_src->int_bits.stint && ngep->poll) 1731 ngep->stint_count ++; 1732 if (ngep->poll && (ngep->stint_count % ngep->param_tx_n_intr == 0)) 1733 btx = B_TRUE; 1734 if (btx) 1735 nge_tx_recycle(ngep, B_TRUE); 1736 if (brx) 1737 nge_receive(ngep); 1738 if (pintr_src->int_bits.teint) 1739 ngep->statistics.sw_statistics.tx_stop_err++; 1740 if (ngep->intr_moderation && brx) { 1741 if (ngep->poll) { 1742 if (ngep->recv_count < ngep->param_rx_intr_hwater) { 1743 ngep->quiet_time++; 1744 if (ngep->quiet_time == 1745 ngep->param_poll_quiet_time) { 1746 ngep->poll = B_FALSE; 1747 ngep->quiet_time = 0; 1748 ngep->stint_count = 0; 1749 nge_tx_recycle(ngep, B_TRUE); 1750 } 1751 } else 1752 ngep->quiet_time = 0; 1753 } else { 1754 if (ngep->recv_count > ngep->param_rx_intr_lwater) { 1755 ngep->busy_time++; 1756 if (ngep->busy_time == 1757 ngep->param_poll_busy_time) { 1758 ngep->poll = B_TRUE; 1759 ngep->busy_time = 0; 1760 } 1761 } else 1762 ngep->busy_time = 0; 1763 } 1764 } 1765 ngep->recv_count = 0; 1766 if (pintr_src->int_bits.feint) 1767 nge_chip_err(ngep); 1768 /* link interrupt, check the link state */ 1769 if (pintr_src->int_bits.mint) { 1770 mintr_src.src_val = nge_reg_get32(ngep, NGE_MINTR_SRC); 1771 nge_reg_put32(ngep, NGE_MINTR_SRC, mintr_src.src_val); 1772 nge_wake_factotum(ngep); 1773 } 1774 } 1775 1776 /* 1777 * nge_chip_intr() -- handle chip interrupts 1778 */ 1779 /* ARGSUSED */ 1780 uint_t 1781 nge_chip_intr(caddr_t arg1, caddr_t arg2) 1782 { 1783 nge_t *ngep = (nge_t *)arg1; 1784 nge_intr_src intr_src; 1785 nge_intr_mask intr_mask; 1786 1787 mutex_enter(ngep->genlock); 1788 1789 if (ngep->suspended) { 1790 mutex_exit(ngep->genlock); 1791 return (DDI_INTR_UNCLAIMED); 1792 } 1793 1794 /* 1795 * Check whether chip's says it's asserting #INTA; 1796 * if not, don't process or claim the interrupt. 1797 */ 1798 intr_src.intr_val = nge_reg_get32(ngep, NGE_INTR_SRC); 1799 if (intr_src.intr_val == 0) { 1800 mutex_exit(ngep->genlock); 1801 return (DDI_INTR_UNCLAIMED); 1802 } 1803 /* 1804 * Ack the interrupt 1805 */ 1806 nge_reg_put32(ngep, NGE_INTR_SRC, intr_src.intr_val); 1807 1808 if (ngep->nge_chip_state != NGE_CHIP_RUNNING) { 1809 mutex_exit(ngep->genlock); 1810 return (DDI_INTR_CLAIMED); 1811 } 1812 nge_intr_handle(ngep, &intr_src); 1813 if (ngep->poll && !ngep->ch_intr_mode) { 1814 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1815 intr_mask.mask_bits.stint = NGE_SET; 1816 intr_mask.mask_bits.rcint = NGE_CLEAR; 1817 intr_mask.mask_bits.reint = NGE_CLEAR; 1818 intr_mask.mask_bits.tcint = NGE_CLEAR; 1819 intr_mask.mask_bits.teint = NGE_CLEAR; 1820 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1821 ngep->ch_intr_mode = B_TRUE; 1822 } else if ((ngep->ch_intr_mode) && (!ngep->poll)) { 1823 nge_reg_put32(ngep, NGE_INTR_MASK, ngep->intr_masks); 1824 ngep->ch_intr_mode = B_FALSE; 1825 } 1826 mutex_exit(ngep->genlock); 1827 return (DDI_INTR_CLAIMED); 1828 } 1829 1830 static enum ioc_reply 1831 nge_pp_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1832 { 1833 int err; 1834 uint64_t sizemask; 1835 uint64_t mem_va; 1836 uint64_t maxoff; 1837 boolean_t peek; 1838 nge_peekpoke_t *ppd; 1839 int (*ppfn)(nge_t *ngep, nge_peekpoke_t *ppd); 1840 1841 switch (cmd) { 1842 default: 1843 return (IOC_INVAL); 1844 1845 case NGE_PEEK: 1846 peek = B_TRUE; 1847 break; 1848 1849 case NGE_POKE: 1850 peek = B_FALSE; 1851 break; 1852 } 1853 1854 /* 1855 * Validate format of ioctl 1856 */ 1857 if (iocp->ioc_count != sizeof (nge_peekpoke_t)) 1858 return (IOC_INVAL); 1859 if (mp->b_cont == NULL) 1860 return (IOC_INVAL); 1861 ppd = (nge_peekpoke_t *)mp->b_cont->b_rptr; 1862 1863 /* 1864 * Validate request parameters 1865 */ 1866 switch (ppd->pp_acc_space) { 1867 default: 1868 return (IOC_INVAL); 1869 1870 case NGE_PP_SPACE_CFG: 1871 /* 1872 * Config space 1873 */ 1874 sizemask = 8|4|2|1; 1875 mem_va = 0; 1876 maxoff = PCI_CONF_HDR_SIZE; 1877 ppfn = peek ? nge_chip_peek_cfg : nge_chip_poke_cfg; 1878 break; 1879 1880 case NGE_PP_SPACE_REG: 1881 /* 1882 * Memory-mapped I/O space 1883 */ 1884 sizemask = 8|4|2|1; 1885 mem_va = 0; 1886 maxoff = NGE_REG_SIZE; 1887 ppfn = peek ? nge_chip_peek_reg : nge_chip_poke_reg; 1888 break; 1889 1890 case NGE_PP_SPACE_MII: 1891 sizemask = 4|2|1; 1892 mem_va = 0; 1893 maxoff = NGE_MII_SIZE; 1894 ppfn = peek ? nge_chip_peek_mii : nge_chip_poke_mii; 1895 break; 1896 1897 case NGE_PP_SPACE_SEEPROM: 1898 sizemask = 4|2|1; 1899 mem_va = 0; 1900 maxoff = NGE_SEEROM_SIZE; 1901 ppfn = peek ? nge_chip_peek_seeprom : nge_chip_poke_seeprom; 1902 break; 1903 } 1904 1905 switch (ppd->pp_acc_size) { 1906 default: 1907 return (IOC_INVAL); 1908 1909 case 8: 1910 case 4: 1911 case 2: 1912 case 1: 1913 if ((ppd->pp_acc_size & sizemask) == 0) 1914 return (IOC_INVAL); 1915 break; 1916 } 1917 1918 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1919 return (IOC_INVAL); 1920 1921 if (ppd->pp_acc_offset >= maxoff) 1922 return (IOC_INVAL); 1923 1924 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1925 return (IOC_INVAL); 1926 1927 /* 1928 * All OK - go do it! 1929 */ 1930 ppd->pp_acc_offset += mem_va; 1931 if (ppfn) 1932 err = (*ppfn)(ngep, ppd); 1933 if (err != DDI_SUCCESS) 1934 return (IOC_INVAL); 1935 return (peek ? IOC_REPLY : IOC_ACK); 1936 } 1937 1938 static enum ioc_reply nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, 1939 struct iocblk *iocp); 1940 #pragma no_inline(nge_diag_ioctl) 1941 1942 static enum ioc_reply 1943 nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1944 { 1945 ASSERT(mutex_owned(ngep->genlock)); 1946 1947 switch (cmd) { 1948 default: 1949 nge_error(ngep, "nge_diag_ioctl: invalid cmd 0x%x", cmd); 1950 return (IOC_INVAL); 1951 1952 case NGE_DIAG: 1953 return (IOC_ACK); 1954 1955 case NGE_PEEK: 1956 case NGE_POKE: 1957 return (nge_pp_ioctl(ngep, cmd, mp, iocp)); 1958 1959 case NGE_PHY_RESET: 1960 return (IOC_RESTART_ACK); 1961 1962 case NGE_SOFT_RESET: 1963 case NGE_HARD_RESET: 1964 return (IOC_ACK); 1965 } 1966 1967 /* NOTREACHED */ 1968 } 1969 1970 enum ioc_reply 1971 nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp) 1972 { 1973 int cmd; 1974 1975 ASSERT(mutex_owned(ngep->genlock)); 1976 1977 cmd = iocp->ioc_cmd; 1978 1979 switch (cmd) { 1980 default: 1981 return (IOC_INVAL); 1982 1983 case NGE_DIAG: 1984 case NGE_PEEK: 1985 case NGE_POKE: 1986 case NGE_PHY_RESET: 1987 case NGE_SOFT_RESET: 1988 case NGE_HARD_RESET: 1989 #if NGE_DEBUGGING 1990 return (nge_diag_ioctl(ngep, cmd, mp, iocp)); 1991 #else 1992 return (IOC_INVAL); 1993 #endif 1994 1995 case NGE_MII_READ: 1996 case NGE_MII_WRITE: 1997 return (IOC_INVAL); 1998 1999 #if NGE_SEE_IO32 2000 case NGE_SEE_READ: 2001 case NGE_SEE_WRITE: 2002 return (IOC_INVAL); 2003 #endif 2004 2005 #if NGE_FLASH_IO32 2006 case NGE_FLASH_READ: 2007 case NGE_FLASH_WRITE: 2008 return (IOC_INVAL); 2009 #endif 2010 } 2011 } 2012