1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007-2009 Myricom, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _myri10ge_mcp_h 28 #define _myri10ge_mcp_h 29 30 #define MXGEFW_VERSION_MAJOR 1 31 #define MXGEFW_VERSION_MINOR 4 32 33 #ifdef MXGEFW 34 #ifndef _stdint_h_ 35 typedef signed char int8_t; 36 typedef signed short int16_t; 37 typedef signed int int32_t; 38 typedef signed long long int64_t; 39 typedef unsigned char uint8_t; 40 typedef unsigned short uint16_t; 41 typedef unsigned int uint32_t; 42 typedef unsigned long long uint64_t; 43 #endif 44 #endif 45 46 /* 8 Bytes */ 47 struct mcp_dma_addr { 48 uint32_t high; 49 uint32_t low; 50 }; 51 typedef struct mcp_dma_addr mcp_dma_addr_t; 52 53 /* 4 Bytes */ 54 struct mcp_slot { 55 uint16_t checksum; 56 uint16_t length; 57 }; 58 typedef struct mcp_slot mcp_slot_t; 59 60 #ifdef MXGEFW_NDIS 61 /* 8-byte descriptor, exclusively used by NDIS drivers. */ 62 struct mcp_slot_8 { 63 /* Place hash value at the top so it gets written before length. 64 * The driver polls length. 65 */ 66 uint32_t hash; 67 uint16_t checksum; 68 uint16_t length; 69 }; 70 typedef struct mcp_slot_8 mcp_slot_8_t; 71 72 /* Two bits of length in mcp_slot are used to indicate hash type. */ 73 #define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 74 #define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 75 #define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 76 #define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 77 #endif 78 79 /* 64 Bytes */ 80 struct mcp_cmd { 81 uint32_t cmd; 82 uint32_t data0; /* will be low portion if data > 32 bits */ 83 /* 8 */ 84 uint32_t data1; /* will be high portion if data > 32 bits */ 85 uint32_t data2; /* currently unused.. */ 86 /* 16 */ 87 struct mcp_dma_addr response_addr; 88 /* 24 */ 89 uint8_t pad[40]; 90 }; 91 typedef struct mcp_cmd mcp_cmd_t; 92 93 /* 8 Bytes */ 94 struct mcp_cmd_response { 95 uint32_t data; 96 uint32_t result; 97 }; 98 typedef struct mcp_cmd_response mcp_cmd_response_t; 99 100 101 102 /* 103 flags used in mcp_kreq_ether_send_t: 104 105 The SMALL flag is only needed in the first segment. It is raised 106 for packets that are total less or equal 512 bytes. 107 108 The CKSUM flag must be set in all segments. 109 110 The PADDED flags is set if the packet needs to be padded, and it 111 must be set for all segments. 112 113 The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 114 length of all previous segments was odd. 115 */ 116 117 118 #define MXGEFW_FLAGS_SMALL 0x1 119 #define MXGEFW_FLAGS_TSO_HDR 0x1 120 #define MXGEFW_FLAGS_FIRST 0x2 121 #define MXGEFW_FLAGS_ALIGN_ODD 0x4 122 #define MXGEFW_FLAGS_CKSUM 0x8 123 #define MXGEFW_FLAGS_TSO_LAST 0x8 124 #define MXGEFW_FLAGS_NO_TSO 0x10 125 #define MXGEFW_FLAGS_TSO_CHOP 0x10 126 #define MXGEFW_FLAGS_TSO_PLD 0x20 127 128 #define MXGEFW_SEND_SMALL_SIZE 1520 129 #define MXGEFW_MAX_MTU 9400 130 131 union mcp_pso_or_cumlen { 132 uint16_t pseudo_hdr_offset; 133 uint16_t cum_len; 134 }; 135 typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 136 137 #define MXGEFW_MAX_SEND_DESC 12 138 #define MXGEFW_PAD 2 139 140 /* 16 Bytes */ 141 struct mcp_kreq_ether_send { 142 uint32_t addr_high; 143 uint32_t addr_low; 144 uint16_t pseudo_hdr_offset; 145 uint16_t length; 146 uint8_t pad; 147 uint8_t rdma_count; 148 uint8_t cksum_offset; /* where to start computing cksum */ 149 uint8_t flags; /* as defined above */ 150 }; 151 typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 152 153 /* 8 Bytes */ 154 struct mcp_kreq_ether_recv { 155 uint32_t addr_high; 156 uint32_t addr_low; 157 }; 158 typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 159 160 161 /* Commands */ 162 163 #define MXGEFW_BOOT_HANDOFF 0xfc0000 164 #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 165 166 #define MXGEFW_ETH_CMD 0xf80000 167 #define MXGEFW_ETH_SEND_4 0x200000 168 #define MXGEFW_ETH_SEND_1 0x240000 169 #define MXGEFW_ETH_SEND_2 0x280000 170 #define MXGEFW_ETH_SEND_3 0x2c0000 171 #define MXGEFW_ETH_RECV_SMALL 0x300000 172 #define MXGEFW_ETH_RECV_BIG 0x340000 173 #define MXGEFW_ETH_SEND_GO 0x380000 174 #define MXGEFW_ETH_SEND_STOP 0x3C0000 175 176 #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 177 #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 178 179 enum myri10ge_mcp_cmd_type { 180 MXGEFW_CMD_NONE = 0, 181 /* Reset the mcp, it is left in a safe state, waiting 182 for the driver to set all its parameters */ 183 MXGEFW_CMD_RESET = 1, 184 185 /* get the version number of the current firmware.. 186 (may be available in the eeprom strings..? */ 187 MXGEFW_GET_MCP_VERSION = 2, 188 189 190 /* Parameters which must be set by the driver before it can 191 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 192 MXGEFW_CMD_RESET is issued */ 193 194 MXGEFW_CMD_SET_INTRQ_DMA = 3, 195 /* data0 = LSW of the host address 196 * data1 = MSW of the host address 197 * data2 = slice number if multiple slices are used 198 */ 199 200 MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 201 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 202 203 204 /* Parameters which refer to lanai SRAM addresses where the 205 driver must issue PIO writes for various things */ 206 207 MXGEFW_CMD_GET_SEND_OFFSET = 6, 208 MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 209 MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 210 /* data0 = slice number if multiple slices are used */ 211 212 MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 213 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 214 215 /* Parameters which refer to rings stored on the MCP, 216 and whose size is controlled by the mcp */ 217 218 MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 219 MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 220 221 /* Parameters which refer to rings stored in the host, 222 and whose size is controlled by the host. Note that 223 all must be physically contiguous and must contain 224 a power of 2 number of entries. */ 225 226 MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 227 #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) 228 229 /* command to bring ethernet interface up. Above parameters 230 (plus mtu & mac address) must have been exchanged prior 231 to issuing this command */ 232 MXGEFW_CMD_ETHERNET_UP = 14, 233 234 /* command to bring ethernet interface down. No further sends 235 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 236 is issued, and all interrupt queues must be flushed prior 237 to ack'ing this command */ 238 239 MXGEFW_CMD_ETHERNET_DOWN = 15, 240 241 /* commands the driver may issue live, without resetting 242 the nic. Note that increasing the mtu "live" should 243 only be done if the driver has already supplied buffers 244 sufficiently large to handle the new mtu. Decreasing 245 the mtu live is safe */ 246 247 MXGEFW_CMD_SET_MTU = 16, 248 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 249 MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 250 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 251 252 MXGEFW_ENABLE_PROMISC = 20, 253 MXGEFW_DISABLE_PROMISC = 21, 254 MXGEFW_SET_MAC_ADDRESS = 22, 255 256 MXGEFW_ENABLE_FLOW_CONTROL = 23, 257 MXGEFW_DISABLE_FLOW_CONTROL = 24, 258 259 /* do a DMA test 260 data0,data1 = DMA address 261 data2 = RDMA length (MSH), WDMA length (LSH) 262 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 263 */ 264 MXGEFW_DMA_TEST = 25, 265 266 MXGEFW_ENABLE_ALLMULTI = 26, 267 MXGEFW_DISABLE_ALLMULTI = 27, 268 269 /* returns MXGEFW_CMD_ERROR_MULTICAST 270 if there is no room in the cache 271 data0,MSH(data1) = multicast group address */ 272 MXGEFW_JOIN_MULTICAST_GROUP = 28, 273 /* returns MXGEFW_CMD_ERROR_MULTICAST 274 if the address is not in the cache, 275 or is equal to FF-FF-FF-FF-FF-FF 276 data0,MSH(data1) = multicast group address */ 277 MXGEFW_LEAVE_MULTICAST_GROUP = 29, 278 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 279 280 MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 281 /* data0, data1 = bus addr, 282 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 283 * adding new stuff to mcp_irq_data without changing the ABI 284 * 285 * If multiple slices are used, data2 contains both the size of the 286 * structure (in the lower 16 bits) and the slice number 287 * (in the upper 16 bits). 288 */ 289 290 MXGEFW_CMD_UNALIGNED_TEST = 32, 291 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 292 chipset */ 293 294 MXGEFW_CMD_UNALIGNED_STATUS = 33, 295 /* return data = boolean, true if the chipset is known to be unaligned */ 296 297 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 298 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 299 * 0 indicates that the NIC consumes as many buffers as they are required 300 * for packet. This is the default behavior. 301 * A power of 2 number indicates that the NIC always uses the specified 302 * number of buffers for each big receive packet. 303 * It is up to the driver to ensure that this value is big enough for 304 * the NIC to be able to receive maximum-sized packets. 305 */ 306 307 MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 308 MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 309 /* data0 = number of slices n (0, 1, ..., n-1) to enable 310 * data1 = interrupt mode | use of multiple transmit queues. 311 * 0=share one INTx/MSI. 312 * 1=use one MSI-X per queue. 313 * If all queues share one interrupt, the driver must have set 314 * RSS_SHARED_INTERRUPT_DMA before enabling queues. 315 * 2=enable both receive and send queues. 316 * Without this bit set, only one send queue (slice 0's send queue) 317 * is enabled. The receive queues are always enabled. 318 */ 319 #define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 320 #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 321 #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 322 323 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 324 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 325 /* data0, data1 = bus address lsw, msw */ 326 MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 327 /* get the offset of the indirection table */ 328 MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 329 /* set the size of the indirection table */ 330 MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 331 /* get the offset of the secret key */ 332 MXGEFW_CMD_RSS_KEY_UPDATED = 42, 333 /* tell nic that the secret key's been updated */ 334 MXGEFW_CMD_SET_RSS_ENABLE = 43, 335 /* data0 = enable/disable rss 336 * 0: disable rss. nic does not distribute receive packets. 337 * 1: enable rss. nic distributes receive packets among queues. 338 * data1 = hash type 339 * 1: IPV4 (required by RSS) 340 * 2: TCP_IPV4 (required by RSS) 341 * 3: IPV4 | TCP_IPV4 (required by RSS) 342 * 4: source port 343 * 5: source port + destination port 344 */ 345 #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 346 #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 347 #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 348 #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 349 #define MXGEFW_RSS_HASH_TYPE_MAX 0x5 350 351 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 352 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 353 * If the header size of a IPv6 TSO packet is larger than the specified 354 * value, then the driver must not use TSO. 355 * This size restriction only applies to IPv6 TSO. 356 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 357 * always has enough header buffer to store maximum-sized headers. 358 */ 359 360 MXGEFW_CMD_SET_TSO_MODE = 45, 361 /* data0 = TSO mode. 362 * 0: Linux/FreeBSD style (NIC default) 363 * 1: NDIS/NetBSD style 364 */ 365 #define MXGEFW_TSO_MODE_LINUX 0 366 #define MXGEFW_TSO_MODE_NDIS 1 367 368 MXGEFW_CMD_MDIO_READ = 46, 369 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 370 MXGEFW_CMD_MDIO_WRITE = 47, 371 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 372 373 MXGEFW_CMD_I2C_READ = 48, 374 /* Starts to get a fresh copy of one byte or of the module i2c table, the 375 * obtained data is cached inside the xaui-xfi chip : 376 * data0 : 0 => get one byte, 1=> get 256 bytes 377 * data1 : If data0 == 0: location to refresh 378 * bit 7:0 register location 379 * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 380 * bit 23:16 is the i2c bus number (for multi-port NICs) 381 * If data0 == 1: unused 382 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 383 * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 384 * will return MXGEFW_CMD_ERROR_BUSY 385 */ 386 MXGEFW_CMD_I2C_BYTE = 49, 387 /* Return the last obtained copy of a given byte in the xfp i2c table 388 * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 389 * data0 : index of the desired table entry 390 * Return data = the byte stored at the requested index in the table 391 */ 392 393 MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 394 /* Return data = NIC memory offset of mcp_vpump_public_global */ 395 MXGEFW_CMD_RESET_VPUMP = 51, 396 /* Resets the VPUMP state */ 397 398 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 399 /* data0 = mcp_slot type to use. 400 * 0 = the default 4B mcp_slot 401 * 1 = 8B mcp_slot_8 402 */ 403 #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 404 #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 405 406 MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 407 /* set the throttle factor for ethp_z8e 408 data0 = throttle_factor 409 throttle_factor = 256 * pcie-raw-speed / tx_speed 410 tx_speed = 256 * pcie-raw-speed / throttle_factor 411 412 For PCI-E x8: pcie-raw-speed == 16Gb/s 413 For PCI-E x4: pcie-raw-speed == 8Gb/s 414 415 ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 416 ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 417 418 with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 419 with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 420 */ 421 422 MXGEFW_CMD_VPUMP_UP = 54, 423 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 424 MXGEFW_CMD_GET_VPUMP_CLK = 55, 425 /* Get the lanai clock */ 426 427 MXGEFW_CMD_GET_DCA_OFFSET = 56, 428 /* offset of dca control for WDMAs */ 429 430 /* VMWare NetQueue commands */ 431 MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 432 MXGEFW_CMD_NETQ_ADD_FILTER = 58, 433 /* data0 = filter_id << 16 | queue << 8 | type */ 434 /* data1 = MS4 of MAC Addr */ 435 /* data2 = LS2_MAC << 16 | VLAN_tag */ 436 MXGEFW_CMD_NETQ_DEL_FILTER = 59, 437 /* data0 = filter_id */ 438 MXGEFW_CMD_NETQ_QUERY1 = 60, 439 MXGEFW_CMD_NETQ_QUERY2 = 61, 440 MXGEFW_CMD_NETQ_QUERY3 = 62, 441 MXGEFW_CMD_NETQ_QUERY4 = 63, 442 443 MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 444 /* When set, small receive buffers can cross page boundaries. 445 * Both small and big receive buffers may start at any address. 446 * This option has performance implications, so use with caution. 447 */ 448 }; 449 typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 450 451 452 enum myri10ge_mcp_cmd_status { 453 MXGEFW_CMD_OK = 0, 454 MXGEFW_CMD_UNKNOWN = 1, 455 MXGEFW_CMD_ERROR_RANGE = 2, 456 MXGEFW_CMD_ERROR_BUSY = 3, 457 MXGEFW_CMD_ERROR_EMPTY = 4, 458 MXGEFW_CMD_ERROR_CLOSED = 5, 459 MXGEFW_CMD_ERROR_HASH_ERROR = 6, 460 MXGEFW_CMD_ERROR_BAD_PORT = 7, 461 MXGEFW_CMD_ERROR_RESOURCES = 8, 462 MXGEFW_CMD_ERROR_MULTICAST = 9, 463 MXGEFW_CMD_ERROR_UNALIGNED = 10, 464 MXGEFW_CMD_ERROR_NO_MDIO = 11, 465 MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 466 MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 467 MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 468 }; 469 typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 470 471 472 #define MXGEFW_OLD_IRQ_DATA_LEN 40 473 474 struct mcp_irq_data { 475 /* add new counters at the beginning */ 476 uint32_t future_use[1]; 477 uint32_t dropped_pause; 478 uint32_t dropped_unicast_filtered; 479 uint32_t dropped_bad_crc32; 480 uint32_t dropped_bad_phy; 481 uint32_t dropped_multicast_filtered; 482 /* 40 Bytes */ 483 uint32_t send_done_count; 484 485 #define MXGEFW_LINK_DOWN 0 486 #define MXGEFW_LINK_UP 1 487 #define MXGEFW_LINK_MYRINET 2 488 #define MXGEFW_LINK_UNKNOWN 3 489 uint32_t link_up; 490 uint32_t dropped_link_overflow; 491 uint32_t dropped_link_error_or_filtered; 492 uint32_t dropped_runt; 493 uint32_t dropped_overrun; 494 uint32_t dropped_no_small_buffer; 495 uint32_t dropped_no_big_buffer; 496 uint32_t rdma_tags_available; 497 498 uint8_t tx_stopped; 499 uint8_t link_down; 500 uint8_t stats_updated; 501 uint8_t valid; 502 }; 503 typedef struct mcp_irq_data mcp_irq_data_t; 504 505 #ifdef MXGEFW_NDIS 506 /* Exclusively used by NDIS drivers */ 507 struct mcp_rss_shared_interrupt { 508 uint8_t pad[2]; 509 uint8_t queue; 510 uint8_t valid; 511 }; 512 #endif 513 514 /* definitions for NETQ filter type */ 515 #define MXGEFW_NETQ_FILTERTYPE_NONE 0 516 #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 517 #define MXGEFW_NETQ_FILTERTYPE_VLAN 2 518 #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 519 520 #endif /* _myri10ge_mcp_h */ 521