1 /* 2 * Solaris driver for ethernet cards based on the Macronix 98715 3 * 4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the author nor the names of any co-contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS'' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _MXFE_H 33 #define _MXFE_H 34 35 /* 36 * These are conveniently defined to have the same values 37 * as are used by the NDD utility, which is an undocumented 38 * interface. YMMV. 39 */ 40 #define NDIOC ('N' << 8) 41 #define NDIOC_GET (NDIOC|0) 42 #define NDIOC_SET (NDIOC|1) 43 44 /* 45 * Registers and values are here, becuase they can be exported to userland 46 * via the MXFEIOC_GETCSR and friends ioctls. These are private to this 47 * driver and the bundled diagnostic utility, and should not be used by 48 * end user application programs. 49 */ 50 51 /* 52 * MXFE register definitions. 53 */ 54 /* PCI configuration registers */ 55 #define PCI_VID 0x00 /* Loaded vendor ID */ 56 #define PCI_DID 0x02 /* Loaded device ID */ 57 #define PCI_CMD 0x04 /* Configuration command register */ 58 #define PCI_STAT 0x06 /* Configuration status register */ 59 #define PCI_RID 0x08 /* Revision ID */ 60 #define PCI_CLS 0x0c /* Cache line size */ 61 #define PCI_SVID 0x2c /* Subsystem vendor ID */ 62 #define PCI_SSID 0x2e /* Subsystem ID */ 63 #define PCI_MINGNT 0x3e /* Minimum Grant */ 64 #define PCI_MAXLAT 0x3f /* Maximum latency */ 65 66 /* 67 * Bits for PCI command register. 68 */ 69 #define PCI_CMD_MWIE 0x0010 /* memory write-invalidate enable */ 70 #define PCI_CMD_BME 0x0004 /* bus master enable */ 71 #define PCI_CMD_MAE 0x0002 /* memory access enable */ 72 #define PCI_CMD_IOE 0x0001 /* I/O access enable */ 73 74 /* Ordinary control/status registers */ 75 #define CSR_PAR 0x00 /* PCI access register */ 76 #define CSR_TDR 0x08 /* Transmit demand register */ 77 #define CSR_RDR 0x10 /* Receive demand register */ 78 #define CSR_RDB 0x18 /* Receive descriptor base address */ 79 #define CSR_TDB 0x20 /* Transmit descriptor base address */ 80 #define CSR_SR 0x28 /* Status register */ 81 #define CSR_NAR 0x30 /* Network access register */ 82 #define CSR_IER 0x38 /* Interrupt enable register */ 83 #define CSR_LPC 0x40 /* Lost packet counter */ 84 #define CSR_SPR 0x48 /* Serial port register */ 85 #define CSR_TIMER 0x58 /* Timer */ 86 #define CSR_TSTAT 0x60 /* 10Base-T status */ 87 #define CSR_SIA 0x68 /* SIA reset register */ 88 #define CSR_TCTL 0x70 /* 10Base-T control */ 89 #define CSR_WTMR 0x78 /* Watchdog timer */ 90 #define CSR_MXMAGIC 0x80 /* MXIC magic register */ 91 #define CSR_PMCSR 0x90 /* Power Management Command and Status */ 92 #define CSR_TXBR 0x9c /* Transmit burst counter/time-out register */ 93 #define CSR_FROM 0xa0 /* Flash(boot) ROM port */ 94 #define CSR_ACOMP 0xa0 /* Autocompensation */ 95 #define CSR_FLOW 0xa8 /* Flow control (newer parts only) */ 96 97 /* 98 * Bits for PCI access register. 99 */ 100 #define PAR_RESET 0x00000001U /* Reset the entire chip */ 101 #define PAR_MWIE 0x01000000U /* PCI memory-write-invalidate */ 102 #define PAR_MRLE 0x00800000U /* PCI memory-read-line */ 103 #define PAR_MRME 0x00200000U /* PCI memory-read-multiple */ 104 #define PAR_BAR 0x00000002U /* Bus arbitration */ 105 #define PAR_DESCSKIP 0x0000007cU /* Descriptor skip length in DW */ 106 #define PAR_BIGENDIAN 0x00000080U /* Use big endian data buffers */ 107 #define PAR_TXAUTOPOLL 0x00060000U /* Programmable TX autopoll interval */ 108 #define PAR_CALIGN_NONE 0x00000000U /* No cache alignment */ 109 #define PAR_CALIGN_8 0x00004000U /* 8 DW cache alignment */ 110 #define PAR_CALIGN_16 0x00008000U /* 16 DW cache alignment */ 111 #define PAR_CALIGN_32 0x0000c000U /* 32 DW cache alignment */ 112 #define PAR_BURSTLEN 0x00003F00U /* Programmable burst length */ 113 #define PAR_BURSTUNL 0x00000000U /* Unlimited burst length */ 114 #define PAR_BURST_1 0x00000100U /* 1 DW burst length */ 115 #define PAR_BURST_2 0x00000200U /* 2 DW burst length */ 116 #define PAR_BURST_4 0x00000400U /* 4 DW burst length */ 117 #define PAR_BURST_8 0x00000800U /* 8 DW burst length */ 118 #define PAR_BURST_16 0x00001000U /* 16 DW burst length */ 119 #define PAR_BURST_32 0x00002000U /* 32 DW burst length */ 120 121 /* 122 * Bits for status register. Interrupt bits are also used by 123 * the interrupt enable register. 124 */ 125 #define SR_BERR_TYPE 0x03800000U /* bus error type */ 126 #define SR_BERR_PARITY 0x00000000U /* parity error */ 127 #define SR_BERR_TARGET_ABORT 0x01000000U /* target abort */ 128 #define SR_BERR_MASTER_ABORT 0x00800000U /* master abort */ 129 #define SR_TX_STATE 0x00700000U /* transmit state */ 130 #define SR_RX_STATE 0x000E0000U /* transmit state */ 131 #define INT_100LINK 0x08000000U /* 100 Base-T link */ 132 #define INT_NORMAL 0x00010000U /* normal interrupt */ 133 #define INT_ABNORMAL 0x00008000U /* abnormal interrupt */ 134 #define INT_EARLYRX 0x00004000U /* early receive interrupt */ 135 #define INT_BUSERR 0x00002000U /* fatal bus error interrupt */ 136 #define INT_10LINK 0x00001000U /* 10 Base-T link */ 137 #define INT_TIMER 0x00000800U /* onboard timer interrupt */ 138 #define INT_EARLYTX 0x00000400U /* early transmit interrupt */ 139 #define INT_RXJABBER 0x00000200U /* receive watchdog timeout */ 140 #define INT_RXSTOPPED 0x00000100U /* receive stopped */ 141 #define INT_RXNOBUF 0x00000080U /* no rcv descriptor */ 142 #define INT_RXOK 0x00000040U /* rcv complete interrupt */ 143 #define INT_TXUNDERFLOW 0x00000020U /* transmit underflow */ 144 #define INT_ANEG 0x00000010U /* autonegotiation */ 145 #define INT_TXJABBER 0x00000008U /* transmit jabber timeout */ 146 #define INT_TXNOBUF 0x00000004U /* no xmt descriptor */ 147 #define INT_TXSTOPPED 0x00000002U /* transmit stopped */ 148 #define INT_TXOK 0x00000001U /* transmit ok interrupt */ 149 150 #define INT_NONE 0x00000000U /* no interrupts */ 151 #define INT_WANTED (INT_BUSERR | INT_RXJABBER | \ 152 INT_RXOK | INT_TXUNDERFLOW | \ 153 INT_RXNOBUF | INT_TXJABBER | \ 154 INT_RXSTOPPED | INT_TXSTOPPED | \ 155 INT_TIMER | \ 156 INT_ABNORMAL | INT_NORMAL) 157 158 #define INT_LINKSTATUS (INT_ANEG | INT_100LINK | INT_10LINK) 159 #define INT_ALL (INT_WANTED | INT_TXOK | \ 160 INT_TXNOBUF | INT_LINKSTATUS) 161 162 /* 163 * Bits for network access register. 164 */ 165 #define NAR_TX_ENABLE 0x00002000U /* Enable transmit */ 166 #define NAR_RX_MULTI 0x00000080U /* Receive all multicast packets */ 167 #define NAR_RX_PROMISC 0x00000040U /* Receive any good packet */ 168 #define NAR_RX_BAD 0x00000008U /* Pass bad packets */ 169 #define NAR_RX_HO 0x00000004U /* Hash only receive */ 170 #define NAR_RX_ENABLE 0x00000002U /* Enable receive */ 171 #define NAR_RX_HP 0x00000001U /* Hash perfect receive */ 172 #define NAR_TR 0x0000c000U /* Transmit threshold mask */ 173 #define NAR_TR_72 0x00000000U /* 72 B (128 @ 100Mbps) tx thresh */ 174 #define NAR_TR_96 0x00004000U /* 96 B (256 @ 100Mbps) tx thresh */ 175 #define NAR_TR_128 0x00008000U /* 128 B (512 @ 100Mbps) tx thresh */ 176 #define NAR_TR_160 0x0000c000U /* 160 B (1K @ 100Mbsp) tx thresh */ 177 #define NAR_SCR 0x01000000U /* scrambler mode */ 178 #define NAR_PCS 0x00800000U /* set for forced 100 mbit */ 179 #define NAR_SPEED 0x00400000U /* transmit threshold, set for 10bt */ 180 #define NAR_SF 0x00200000U /* store and forward */ 181 #define NAR_HBD 0x00080000U /* Disable SQE heartbeat */ 182 #define NAR_COE 0x00020000U /* collision offset enable */ 183 #define NAR_PORTSEL 0x00040000U /* 1 = 100 mbit */ 184 #define NAR_FDX 0x00000200U /* 1 = full duplex */ 185 186 /* 187 * Bits for lost packet counter. 188 */ 189 #define LPC_COUNT 0x0000FFFFU /* Count of missed frames */ 190 #define LPC_OFLOW 0x00010000U /* Counter overflow bit */ 191 192 /* 193 * Bits for CSR_SPR (MII and SROM access) 194 */ 195 #define SPR_MII_DIN 0x00080000U /* MII data input */ 196 #define SPR_MII_CTRL 0x00040000U /* MII management control, 1=read */ 197 #define SPR_MII_DOUT 0x00020000U /* MII data output */ 198 #define SPR_MII_CLOCK 0x00010000U /* MII data clock */ 199 #define SPR_SROM_READ 0x00004000U /* Serial EEPROM read control */ 200 #define SPR_SROM_WRITE 0x00002000U /* Serial EEPROM write control */ 201 #define SPR_SROM_SEL 0x00000800U /* Serial EEPROM select */ 202 #define SPR_SROM_DOUT 0x00000008U /* Serial EEPROM data out */ 203 #define SPR_SROM_DIN 0x00000004U /* Serial EEPROM data in */ 204 #define SPR_SROM_CLOCK 0x00000002U /* Serial EEPROM clock */ 205 #define SPR_SROM_CHIP 0x00000001U /* Serial EEPROM chip select */ 206 #define SROM_ENADDR 0x70 /* Ethernet address pointer! */ 207 #define SROM_READCMD 0x6 /* command to read SROM */ 208 209 /* 210 * Bits for CSR_TIMER 211 */ 212 #define TIMER_LOOP 0x00010000U /* continuous operating mode */ 213 #define TIMER_USEC 204 /* usecs per timer count */ 214 215 /* 216 * Bits for TSTAT 217 */ 218 #define TSTAT_LPC 0xFFFF0000U /* link partner's code word */ 219 #define TSTAT_LPN 0x00008000U /* link partner supports nway */ 220 #define TSTAT_ANS 0x00007000U /* autonegotiation state mask */ 221 #define TSTAT_TRF 0x00000800U /* transmit remote fault */ 222 #define TSTAT_APS 0x00000008U /* autopolarity state */ 223 #define TSTAT_10F 0x00000004U /* 10Base-T link failure */ 224 #define TSTAT_100F 0x00000002U /* 100Base-T link failure */ 225 #define TSTAT_ANS_DIS 0x00000000U /* autonegotiation disabled */ 226 #define TSTAT_ANS_OK 0x00005000U /* autonegotiation complete */ 227 #define TSTAT_ANS_START 0x00001000U /* restart autonegotiation */ 228 229 /* macro to convert TSTAT link partner's code word to MII equivalents */ 230 #define TSTAT_LPAR(x) ((x & TSTAT_LPC) >> 16) 231 232 /* 233 * Bits for SIA reset 234 */ 235 #define SIA_RESET 0x00000001U /* reset 100 PHY */ 236 #define SIA_NRESET 0x00000002U /* reset NWay */ 237 238 /* 239 * Bits for TCTL 240 */ 241 #define TCTL_PAUSE 0x00080000U /* Pause enable */ 242 #define TCTL_100BT4 0x00040000U /* 100 BaseT4 enable */ 243 #define TCTL_100FDX 0x00020000U /* 100 BaseT fdx enable */ 244 #define TCTL_100HDX 0x00010000U /* 100 BaseT hdx enable */ 245 #define TCTL_LTE 0x00001000U /* link test enable */ 246 #define TCTL_RSQ 0x00000100U /* receive squelch enable */ 247 #define TCTL_ANE 0x00000080U /* autoneg. enable */ 248 #define TCTL_HDX 0x00000040U /* half-duplex enable */ 249 #define TCTL_PWR 0x00000004U /* supply power to 10BaseT */ 250 251 /* 252 * Bits for flow control 253 */ 254 #define FLOW_TMVAL 0xffff0000U /* flow timer value */ 255 #define FLOW_TEST 0x00008000U /* test flow control timer */ 256 #define FLOW_RESTART 0x00004000U /* re-start mode */ 257 #define FLOW_RESTOP 0x00002000U /* re-stop mode */ 258 #define FLOW_TXFCEN 0x00001000U /* tx flow control enable */ 259 #define FLOW_RXFCEN 0x00000800U /* rx flow control enable */ 260 #define FLOW_RUFCEN 0x00000400U /* send pause when rxnobuf */ 261 #define FLOW_STOPTX 0x00000200U /* tx flow status */ 262 #define FLOW_REJECTFC 0x00000100U /* abort rx flow when set */ 263 #define FLOW_RXFCTH1 0x00000080U /* rx flow threshold 1 */ 264 #define FLOW_RXFCTH0 0x00000040U /* rx flow threshold 0 */ 265 #define FLOW_NFCEN 0x00000020U /* accept nway flow control */ 266 267 268 #endif /* _MXFE_H */ 269