1 /* 2 * mr_sas.h: header for mr_sas 3 * 4 * Solaris MegaRAID driver for SAS2.0 controllers 5 * Copyright (c) 2008-2009, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the author nor the names of its contributors may be 19 * used to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 * DAMAGE. 34 */ 35 36 /* 37 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 38 */ 39 #ifndef _MR_SAS_H_ 40 #define _MR_SAS_H_ 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #include <sys/scsi/scsi.h> 47 #include "mr_sas_list.h" 48 49 /* 50 * MegaRAID SAS2.0 Driver meta data 51 */ 52 #define MRSAS_VERSION "LSIv2.6" 53 #define MRSAS_RELDATE "Apr 21, 2010" 54 55 #define MRSAS_TRUE 1 56 #define MRSAS_FALSE 0 57 58 #define ADAPTER_RESET_NOT_REQUIRED 0 59 #define ADAPTER_RESET_REQUIRED 1 60 61 /* 62 * MegaRAID SAS2.0 device id conversion definitions. 63 */ 64 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT) 65 66 /* 67 * MegaRAID SAS2.0 supported controllers 68 */ 69 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078 70 #define PCI_DEVICE_ID_LSI_2108V 0x0079 71 72 /* 73 * Register Index for 2108 Controllers. 74 */ 75 #define REGISTER_SET_IO_2108 (2) 76 77 #define MRSAS_MAX_SGE_CNT 0x50 78 79 #define MRSAS_IOCTL_DRIVER 0x12341234 80 #define MRSAS_IOCTL_FIRMWARE 0x12345678 81 #define MRSAS_IOCTL_AEN 0x87654321 82 83 #define MRSAS_1_SECOND 1000000 84 85 /* Dynamic Enumeration Flags */ 86 #define MRSAS_PD_LUN 1 87 #define MRSAS_LD_LUN 0 88 #define MRSAS_PD_TGT_MAX 255 89 #define MRSAS_GET_PD_MAX(s) ((s)->mr_pd_max) 90 #define WWN_STRLEN 17 91 #define APP_RESERVE_CMDS 32 92 /* 93 * ===================================== 94 * MegaRAID SAS2.0 MFI firmware definitions 95 * ===================================== 96 */ 97 /* 98 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for 99 * protocol between the software and firmware. Commands are issued using 100 * "message frames" 101 */ 102 103 /* 104 * FW posts its state in upper 4 bits of outbound_msg_0 register 105 */ 106 #define MFI_STATE_SHIFT 28 107 #define MFI_STATE_MASK ((uint32_t)0xF<<MFI_STATE_SHIFT) 108 #define MFI_STATE_UNDEFINED ((uint32_t)0x0<<MFI_STATE_SHIFT) 109 #define MFI_STATE_BB_INIT ((uint32_t)0x1<<MFI_STATE_SHIFT) 110 #define MFI_STATE_FW_INIT ((uint32_t)0x4<<MFI_STATE_SHIFT) 111 #define MFI_STATE_WAIT_HANDSHAKE ((uint32_t)0x6<<MFI_STATE_SHIFT) 112 #define MFI_STATE_FW_INIT_2 ((uint32_t)0x7<<MFI_STATE_SHIFT) 113 #define MFI_STATE_DEVICE_SCAN ((uint32_t)0x8<<MFI_STATE_SHIFT) 114 #define MFI_STATE_BOOT_MESSAGE_PENDING ((uint32_t)0x9<<MFI_STATE_SHIFT) 115 #define MFI_STATE_FLUSH_CACHE ((uint32_t)0xA<<MFI_STATE_SHIFT) 116 #define MFI_STATE_READY ((uint32_t)0xB<<MFI_STATE_SHIFT) 117 #define MFI_STATE_OPERATIONAL ((uint32_t)0xC<<MFI_STATE_SHIFT) 118 #define MFI_STATE_FAULT ((uint32_t)0xF<<MFI_STATE_SHIFT) 119 120 #define MRMFI_FRAME_SIZE 64 121 122 /* 123 * During FW init, clear pending cmds & reset state using inbound_msg_0 124 * 125 * ABORT : Abort all pending cmds 126 * READY : Move from OPERATIONAL to READY state; discard queue info 127 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 128 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 129 */ 130 #define MFI_INIT_ABORT 0x00000001 131 #define MFI_INIT_READY 0x00000002 132 #define MFI_INIT_MFIMODE 0x00000004 133 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 134 #define MFI_INIT_HOTPLUG 0x00000010 135 #define MFI_STOP_ADP 0x00000020 136 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT 137 138 /* 139 * MFI frame flags 140 */ 141 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 142 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 143 #define MFI_FRAME_SGL32 0x0000 144 #define MFI_FRAME_SGL64 0x0002 145 #define MFI_FRAME_SENSE32 0x0000 146 #define MFI_FRAME_SENSE64 0x0004 147 #define MFI_FRAME_DIR_NONE 0x0000 148 #define MFI_FRAME_DIR_WRITE 0x0008 149 #define MFI_FRAME_DIR_READ 0x0010 150 #define MFI_FRAME_DIR_BOTH 0x0018 151 #define MFI_FRAME_IEEE 0x0020 152 153 /* 154 * Definition for cmd_status 155 */ 156 #define MFI_CMD_STATUS_POLL_MODE 0xFF 157 #define MFI_CMD_STATUS_SYNC_MODE 0xFF 158 159 /* 160 * MFI command opcodes 161 */ 162 #define MFI_CMD_OP_INIT 0x00 163 #define MFI_CMD_OP_LD_READ 0x01 164 #define MFI_CMD_OP_LD_WRITE 0x02 165 #define MFI_CMD_OP_LD_SCSI 0x03 166 #define MFI_CMD_OP_PD_SCSI 0x04 167 #define MFI_CMD_OP_DCMD 0x05 168 #define MFI_CMD_OP_ABORT 0x06 169 #define MFI_CMD_OP_SMP 0x07 170 #define MFI_CMD_OP_STP 0x08 171 172 #define MR_DCMD_CTRL_GET_INFO 0x01010000 173 174 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 175 #define MR_FLUSH_CTRL_CACHE 0x01 176 #define MR_FLUSH_DISK_CACHE 0x02 177 178 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 179 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01 180 181 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 182 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 183 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 184 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 185 #define MR_DCMD_PD_GET_INFO 0x02020000 186 187 /* 188 * Solaris Specific MAX values 189 */ 190 #define MAX_SGL 24 191 /* 192 * MFI command completion codes 193 */ 194 enum MFI_STAT { 195 MFI_STAT_OK = 0x00, 196 MFI_STAT_INVALID_CMD = 0x01, 197 MFI_STAT_INVALID_DCMD = 0x02, 198 MFI_STAT_INVALID_PARAMETER = 0x03, 199 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 200 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 201 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 202 MFI_STAT_APP_IN_USE = 0x07, 203 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 204 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 205 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 206 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 207 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 208 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 209 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 210 MFI_STAT_FLASH_BUSY = 0x0f, 211 MFI_STAT_FLASH_ERROR = 0x10, 212 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 213 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 214 MFI_STAT_FLASH_NOT_OPEN = 0x13, 215 MFI_STAT_FLASH_NOT_STARTED = 0x14, 216 MFI_STAT_FLUSH_FAILED = 0x15, 217 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 218 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 219 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 220 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 221 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 222 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 223 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 224 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 225 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 226 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 227 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 228 MFI_STAT_MFC_HW_ERROR = 0x21, 229 MFI_STAT_NO_HW_PRESENT = 0x22, 230 MFI_STAT_NOT_FOUND = 0x23, 231 MFI_STAT_NOT_IN_ENCL = 0x24, 232 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 233 MFI_STAT_PD_TYPE_WRONG = 0x26, 234 MFI_STAT_PR_DISABLED = 0x27, 235 MFI_STAT_ROW_INDEX_INVALID = 0x28, 236 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 237 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 238 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 239 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 240 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 241 MFI_STAT_SCSI_IO_FAILED = 0x2e, 242 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 243 MFI_STAT_SHUTDOWN_FAILED = 0x30, 244 MFI_STAT_TIME_NOT_SET = 0x31, 245 MFI_STAT_WRONG_STATE = 0x32, 246 MFI_STAT_LD_OFFLINE = 0x33, 247 /* UNUSED: 0x34 to 0xfe */ 248 MFI_STAT_INVALID_STATUS = 0xFF 249 }; 250 251 enum MR_EVT_CLASS { 252 MR_EVT_CLASS_DEBUG = -2, 253 MR_EVT_CLASS_PROGRESS = -1, 254 MR_EVT_CLASS_INFO = 0, 255 MR_EVT_CLASS_WARNING = 1, 256 MR_EVT_CLASS_CRITICAL = 2, 257 MR_EVT_CLASS_FATAL = 3, 258 MR_EVT_CLASS_DEAD = 4 259 }; 260 261 enum MR_EVT_LOCALE { 262 MR_EVT_LOCALE_LD = 0x0001, 263 MR_EVT_LOCALE_PD = 0x0002, 264 MR_EVT_LOCALE_ENCL = 0x0004, 265 MR_EVT_LOCALE_BBU = 0x0008, 266 MR_EVT_LOCALE_SAS = 0x0010, 267 MR_EVT_LOCALE_CTRL = 0x0020, 268 MR_EVT_LOCALE_CONFIG = 0x0040, 269 MR_EVT_LOCALE_CLUSTER = 0x0080, 270 MR_EVT_LOCALE_ALL = 0xffff 271 }; 272 273 #define MR_EVT_CFG_CLEARED 0x0004 274 #define MR_EVT_LD_CREATED 0x008a 275 #define MR_EVT_LD_DELETED 0x008b 276 #define MR_EVT_PD_REMOVED_EXT 0x00f8 277 #define MR_EVT_PD_INSERTED_EXT 0x00f7 278 279 enum LD_STATE { 280 LD_OFFLINE = 0, 281 LD_PARTIALLY_DEGRADED = 1, 282 LD_DEGRADED = 2, 283 LD_OPTIMAL = 3, 284 LD_INVALID = 0xFF 285 }; 286 287 enum MRSAS_EVT { 288 MRSAS_EVT_CONFIG_TGT = 0, 289 MRSAS_EVT_UNCONFIG_TGT = 1, 290 MRSAS_EVT_UNCONFIG_SMP = 2 291 }; 292 293 #define DMA_OBJ_ALLOCATED 1 294 #define DMA_OBJ_REALLOCATED 2 295 #define DMA_OBJ_FREED 3 296 297 /* 298 * dma_obj_t - Our DMA object 299 * @param buffer : kernel virtual address 300 * @param size : size of the data to be allocated 301 * @param acc_handle : access handle 302 * @param dma_handle : dma handle 303 * @param dma_cookie : scatter-gather list 304 * @param dma_attr : dma attributes for this buffer 305 * Our DMA object. The caller must initialize the size and dma attributes 306 * (dma_attr) fields before allocating the resources. 307 */ 308 typedef struct { 309 caddr_t buffer; 310 uint32_t size; 311 ddi_acc_handle_t acc_handle; 312 ddi_dma_handle_t dma_handle; 313 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT]; 314 ddi_dma_attr_t dma_attr; 315 uint8_t status; 316 uint8_t reserved[3]; 317 } dma_obj_t; 318 319 struct mrsas_eventinfo { 320 struct mrsas_instance *instance; 321 int tgt; 322 int lun; 323 int event; 324 }; 325 326 struct mrsas_ld { 327 dev_info_t *dip; 328 uint8_t lun_type; 329 uint8_t reserved[3]; 330 }; 331 332 struct mrsas_pd { 333 dev_info_t *dip; 334 uint8_t lun_type; 335 uint8_t dev_id; 336 uint8_t flags; 337 uint8_t reserved; 338 }; 339 340 struct mrsas_pd_info { 341 uint16_t deviceId; 342 uint16_t seqNum; 343 uint8_t inquiryData[96]; 344 uint8_t vpdPage83[64]; 345 uint8_t notSupported; 346 uint8_t scsiDevType; 347 uint8_t a; 348 uint8_t device_speed; 349 uint32_t mediaerrcnt; 350 uint32_t other; 351 uint32_t pred; 352 uint32_t lastpred; 353 uint16_t fwState; 354 uint8_t disabled; 355 uint8_t linkspwwd; 356 uint32_t ddfType; 357 struct { 358 uint8_t count; 359 uint8_t isPathBroken; 360 uint8_t connectorIndex[2]; 361 uint8_t reserved[4]; 362 uint64_t sasAddr[2]; 363 uint8_t reserved2[16]; 364 } pathInfo; 365 }; 366 367 typedef struct mrsas_instance { 368 uint32_t *producer; 369 uint32_t *consumer; 370 371 uint32_t *reply_queue; 372 dma_obj_t mfi_internal_dma_obj; 373 uint16_t adapterresetinprogress; 374 uint16_t deadadapter; 375 uint8_t init_id; 376 uint8_t flag_ieee; 377 uint8_t disable_online_ctrl_reset; 378 uint8_t fw_fault_count_after_ocr; 379 380 uint16_t max_num_sge; 381 uint16_t max_fw_cmds; 382 uint32_t max_sectors_per_req; 383 384 struct mrsas_cmd **cmd_list; 385 mlist_t cmd_pool_list; 386 kmutex_t cmd_pool_mtx; 387 388 mlist_t app_cmd_pool_list; 389 kmutex_t app_cmd_pool_mtx; 390 mlist_t cmd_pend_list; 391 kmutex_t cmd_pend_mtx; 392 393 dma_obj_t mfi_evt_detail_obj; 394 struct mrsas_cmd *aen_cmd; 395 396 uint32_t aen_seq_num; 397 uint32_t aen_class_locale_word; 398 399 scsi_hba_tran_t *tran; 400 401 kcondvar_t int_cmd_cv; 402 kmutex_t int_cmd_mtx; 403 404 kcondvar_t aen_cmd_cv; 405 kmutex_t aen_cmd_mtx; 406 407 kcondvar_t abort_cmd_cv; 408 kmutex_t abort_cmd_mtx; 409 410 dev_info_t *dip; 411 ddi_acc_handle_t pci_handle; 412 413 timeout_id_t timeout_id; 414 uint32_t unique_id; 415 uint16_t fw_outstanding; 416 caddr_t regmap; 417 ddi_acc_handle_t regmap_handle; 418 uint8_t isr_level; 419 ddi_iblock_cookie_t iblock_cookie; 420 ddi_iblock_cookie_t soft_iblock_cookie; 421 ddi_softintr_t soft_intr_id; 422 uint8_t softint_running; 423 kmutex_t completed_pool_mtx; 424 mlist_t completed_pool_list; 425 426 caddr_t internal_buf; 427 uint32_t internal_buf_dmac_add; 428 uint32_t internal_buf_size; 429 430 uint16_t vendor_id; 431 uint16_t device_id; 432 uint16_t subsysvid; 433 uint16_t subsysid; 434 int instance; 435 int baseaddress; 436 char iocnode[16]; 437 438 int fm_capabilities; 439 440 struct mrsas_func_ptr *func_ptr; 441 /* MSI interrupts specific */ 442 ddi_intr_handle_t *intr_htable; 443 int intr_type; 444 int intr_cnt; 445 size_t intr_size; 446 uint_t intr_pri; 447 int intr_cap; 448 449 ddi_taskq_t *taskq; 450 struct mrsas_ld *mr_ld_list; 451 kmutex_t ocr_flags_mtx; 452 } mrsas_t; 453 454 struct mrsas_func_ptr { 455 int (*read_fw_status_reg)(struct mrsas_instance *); 456 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *); 457 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *, 458 struct mrsas_cmd *); 459 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *, 460 struct mrsas_cmd *); 461 void (*enable_intr)(struct mrsas_instance *); 462 void (*disable_intr)(struct mrsas_instance *); 463 int (*intr_ack)(struct mrsas_instance *); 464 }; 465 466 /* 467 * ### Helper routines ### 468 */ 469 470 /* 471 * con_log() - console log routine 472 * @param level : indicates the severity of the message. 473 * @fparam mt : format string 474 * 475 * con_log displays the error messages on the console based on the current 476 * debug level. Also it attaches the appropriate kernel severity level with 477 * the message. 478 * 479 * 480 * console messages debug levels 481 */ 482 #define CL_NONE 0 /* No debug information */ 483 #define CL_TEST_OCR 1 484 #define CL_ANN 2 /* print unconditionally, announcements */ 485 #define CL_ANN1 3 /* No o/p */ 486 #define CL_DLEVEL1 4 /* debug level 1, informative */ 487 #define CL_DLEVEL2 5 /* debug level 2, verbose */ 488 #define CL_DLEVEL3 6 /* debug level 3, very verbose */ 489 490 491 #ifdef __SUNPRO_C 492 #define __func__ "" 493 #endif 494 495 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; } 496 497 /* 498 * ### SCSA definitions ### 499 */ 500 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target) 501 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun) 502 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran) 503 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 504 505 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private) 506 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap)) 507 508 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private) 509 #define CMD2PKT(sp) ((sp)->cmd_pkt) 510 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request)) 511 512 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address) 513 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran) 514 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd))) 515 516 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */ 517 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */ 518 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */ 519 520 /* 521 * ### Data structures for ioctl inteface and internal commands ### 522 */ 523 524 /* 525 * Data direction flags 526 */ 527 #define UIOC_RD 0x00001 528 #define UIOC_WR 0x00002 529 530 #define SCP2HOST(scp) (scp)->device->host /* to host */ 531 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */ 532 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */ 533 #define SCP2TARGET(scp) (scp)->device->id /* to target */ 534 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */ 535 536 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0]) 537 #define SCP2ADAPTER(scp) \ 538 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp)) 539 540 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \ 541 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0 542 #define MRDRV_IS_LOGICAL(ap) \ 543 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0 544 #define MAP_DEVICE_ID(instance, ap) \ 545 (ap->a_target) 546 547 #define HIGH_LEVEL_INTR 1 548 #define NORMAL_LEVEL_INTR 0 549 550 #define IO_RETRY_COUNT 3 551 #define MAX_FW_RESET_COUNT 3 552 553 /* 554 * scsa_cmd - Per-command mr private data 555 * @param cmd_dmahandle : dma handle 556 * @param cmd_dmacookies : current dma cookies 557 * @param cmd_pkt : scsi_pkt reference 558 * @param cmd_dmacount : dma count 559 * @param cmd_cookie : next cookie 560 * @param cmd_ncookies : cookies per window 561 * @param cmd_cookiecnt : cookies per sub-win 562 * @param cmd_nwin : number of dma windows 563 * @param cmd_curwin : current dma window 564 * @param cmd_dma_offset : current window offset 565 * @param cmd_dma_len : current window length 566 * @param cmd_flags : private flags 567 * @param cmd_cdblen : length of cdb 568 * @param cmd_scblen : length of scb 569 * @param cmd_buf : command buffer 570 * @param channel : channel for scsi sub-system 571 * @param target : target for scsi sub-system 572 * @param lun : LUN for scsi sub-system 573 * 574 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E) 575 * - Pointed to by pkt_ha_private field in scsi_pkt 576 */ 577 struct scsa_cmd { 578 ddi_dma_handle_t cmd_dmahandle; 579 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT]; 580 struct scsi_pkt *cmd_pkt; 581 ulong_t cmd_dmacount; 582 uint_t cmd_cookie; 583 uint_t cmd_ncookies; 584 uint_t cmd_cookiecnt; 585 uint_t cmd_nwin; 586 uint_t cmd_curwin; 587 off_t cmd_dma_offset; 588 ulong_t cmd_dma_len; 589 ulong_t cmd_flags; 590 uint_t cmd_cdblen; 591 uint_t cmd_scblen; 592 struct buf *cmd_buf; 593 ushort_t device_id; 594 uchar_t islogical; 595 uchar_t lun; 596 struct mrsas_device *mrsas_dev; 597 }; 598 599 600 struct mrsas_cmd { 601 union mrsas_frame *frame; 602 uint32_t frame_phys_addr; 603 uint8_t *sense; 604 uint32_t sense_phys_addr; 605 dma_obj_t frame_dma_obj; 606 uint8_t frame_dma_obj_status; 607 608 uint32_t index; 609 uint8_t sync_cmd; 610 uint8_t cmd_status; 611 uint16_t abort_aen; 612 mlist_t list; 613 uint32_t frame_count; 614 struct scsa_cmd *cmd; 615 struct scsi_pkt *pkt; 616 uint16_t retry_count_for_ocr; 617 uint16_t drv_pkt_time; 618 }; 619 620 #define MAX_MGMT_ADAPTERS 1024 621 #define IOC_SIGNATURE "MR-SAS" 622 623 #define IOC_CMD_FIRMWARE 0x0 624 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000 625 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100 626 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200 627 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300 628 629 630 #define MRSAS_MAX_SENSE_LENGTH 32 631 632 struct mrsas_mgmt_info { 633 634 uint16_t count; 635 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS]; 636 uint16_t map[MAX_MGMT_ADAPTERS]; 637 int max_index; 638 }; 639 640 #pragma pack(1) 641 642 /* 643 * SAS controller properties 644 */ 645 struct mrsas_ctrl_prop { 646 uint16_t seq_num; 647 uint16_t pred_fail_poll_interval; 648 uint16_t intr_throttle_count; 649 uint16_t intr_throttle_timeouts; 650 651 uint8_t rebuild_rate; 652 uint8_t patrol_read_rate; 653 uint8_t bgi_rate; 654 uint8_t cc_rate; 655 uint8_t recon_rate; 656 657 uint8_t cache_flush_interval; 658 659 uint8_t spinup_drv_count; 660 uint8_t spinup_delay; 661 662 uint8_t cluster_enable; 663 uint8_t coercion_mode; 664 uint8_t alarm_enable; 665 uint8_t reserved_1[13]; 666 /* Add properties that can be controlled by a bit in the following structure */ 667 struct { 668 uint32_t reserved_2 : 10; 669 uint32_t disable_online_ctrl_reset : 1; 670 uint32_t reserved_3 : 21; 671 } on_off_properties; 672 673 uint8_t reserved_4[28]; 674 }; 675 676 677 /* 678 * SAS controller information 679 */ 680 struct mrsas_ctrl_info { 681 /* PCI device information */ 682 struct { 683 uint16_t vendor_id; 684 uint16_t device_id; 685 uint16_t sub_vendor_id; 686 uint16_t sub_device_id; 687 uint8_t reserved[24]; 688 } pci; 689 690 /* Host interface information */ 691 struct { 692 uint8_t PCIX : 1; 693 uint8_t PCIE : 1; 694 uint8_t iSCSI : 1; 695 uint8_t SAS_3G : 1; 696 uint8_t reserved_0 : 4; 697 uint8_t reserved_1[6]; 698 uint8_t port_count; 699 uint64_t port_addr[8]; 700 } host_interface; 701 702 /* Device (backend) interface information */ 703 struct { 704 uint8_t SPI : 1; 705 uint8_t SAS_3G : 1; 706 uint8_t SATA_1_5G : 1; 707 uint8_t SATA_3G : 1; 708 uint8_t reserved_0 : 4; 709 uint8_t reserved_1[6]; 710 uint8_t port_count; 711 uint64_t port_addr[8]; 712 } device_interface; 713 714 /* List of components residing in flash. All str are null terminated */ 715 uint32_t image_check_word; 716 uint32_t image_component_count; 717 718 struct { 719 char name[8]; 720 char version[32]; 721 char build_date[16]; 722 char built_time[16]; 723 } image_component[8]; 724 725 /* 726 * List of flash components that have been flashed on the card, but 727 * are not in use, pending reset of the adapter. This list will be 728 * empty if a flash operation has not occurred. All stings are null 729 * terminated 730 */ 731 uint32_t pending_image_component_count; 732 733 struct { 734 char name[8]; 735 char version[32]; 736 char build_date[16]; 737 char build_time[16]; 738 } pending_image_component[8]; 739 740 uint8_t max_arms; 741 uint8_t max_spans; 742 uint8_t max_arrays; 743 uint8_t max_lds; 744 745 char product_name[80]; 746 char serial_no[32]; 747 748 /* 749 * Other physical/controller/operation information. Indicates the 750 * presence of the hardware 751 */ 752 struct { 753 uint32_t bbu : 1; 754 uint32_t alarm : 1; 755 uint32_t nvram : 1; 756 uint32_t uart : 1; 757 uint32_t reserved : 28; 758 } hw_present; 759 760 uint32_t current_fw_time; 761 762 /* Maximum data transfer sizes */ 763 uint16_t max_concurrent_cmds; 764 uint16_t max_sge_count; 765 uint32_t max_request_size; 766 767 /* Logical and physical device counts */ 768 uint16_t ld_present_count; 769 uint16_t ld_degraded_count; 770 uint16_t ld_offline_count; 771 772 uint16_t pd_present_count; 773 uint16_t pd_disk_present_count; 774 uint16_t pd_disk_pred_failure_count; 775 uint16_t pd_disk_failed_count; 776 777 /* Memory size information */ 778 uint16_t nvram_size; 779 uint16_t memory_size; 780 uint16_t flash_size; 781 782 /* Error counters */ 783 uint16_t mem_correctable_error_count; 784 uint16_t mem_uncorrectable_error_count; 785 786 /* Cluster information */ 787 uint8_t cluster_permitted; 788 uint8_t cluster_active; 789 uint8_t reserved_1[2]; 790 791 /* Controller capabilities structures */ 792 struct { 793 uint32_t raid_level_0 : 1; 794 uint32_t raid_level_1 : 1; 795 uint32_t raid_level_5 : 1; 796 uint32_t raid_level_1E : 1; 797 uint32_t reserved : 28; 798 } raid_levels; 799 800 struct { 801 uint32_t rbld_rate : 1; 802 uint32_t cc_rate : 1; 803 uint32_t bgi_rate : 1; 804 uint32_t recon_rate : 1; 805 uint32_t patrol_rate : 1; 806 uint32_t alarm_control : 1; 807 uint32_t cluster_supported : 1; 808 uint32_t bbu : 1; 809 uint32_t spanning_allowed : 1; 810 uint32_t dedicated_hotspares : 1; 811 uint32_t revertible_hotspares : 1; 812 uint32_t foreign_config_import : 1; 813 uint32_t self_diagnostic : 1; 814 uint32_t reserved : 19; 815 } adapter_operations; 816 817 struct { 818 uint32_t read_policy : 1; 819 uint32_t write_policy : 1; 820 uint32_t io_policy : 1; 821 uint32_t access_policy : 1; 822 uint32_t reserved : 28; 823 } ld_operations; 824 825 struct { 826 uint8_t min; 827 uint8_t max; 828 uint8_t reserved[2]; 829 } stripe_size_operations; 830 831 struct { 832 uint32_t force_online : 1; 833 uint32_t force_offline : 1; 834 uint32_t force_rebuild : 1; 835 uint32_t reserved : 29; 836 } pd_operations; 837 838 struct { 839 uint32_t ctrl_supports_sas : 1; 840 uint32_t ctrl_supports_sata : 1; 841 uint32_t allow_mix_in_encl : 1; 842 uint32_t allow_mix_in_ld : 1; 843 uint32_t allow_sata_in_cluster : 1; 844 uint32_t reserved : 27; 845 } pd_mix_support; 846 847 /* Include the controller properties (changeable items) */ 848 uint8_t reserved_2[12]; 849 struct mrsas_ctrl_prop properties; 850 851 uint8_t pad[0x800 - 0x640]; 852 }; 853 854 /* 855 * ================================== 856 * MegaRAID SAS2.0 driver definitions 857 * ================================== 858 */ 859 #define MRDRV_MAX_NUM_CMD 1024 860 861 #define MRDRV_MAX_PD_CHANNELS 2 862 #define MRDRV_MAX_LD_CHANNELS 2 863 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \ 864 MRDRV_MAX_LD_CHANNELS) 865 #define MRDRV_MAX_DEV_PER_CHANNEL 128 866 #define MRDRV_DEFAULT_INIT_ID -1 867 #define MRDRV_MAX_CMD_PER_LUN 1000 868 #define MRDRV_MAX_LUN 1 869 #define MRDRV_MAX_LD 64 870 871 #define MRDRV_RESET_WAIT_TIME 300 872 #define MRDRV_RESET_NOTICE_INTERVAL 5 873 874 #define MRSAS_IOCTL_CMD 0 875 876 /* 877 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 878 * SGLs based on the size of dma_addr_t 879 */ 880 #define IS_DMA64 (sizeof (dma_addr_t) == 8) 881 882 #define IB_MSG_0_OFF 0x10 /* XScale */ 883 #define OB_MSG_0_OFF 0x18 /* XScale */ 884 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */ 885 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */ 886 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */ 887 #define IB_QPORT_OFF 0x40 /* XScale & ROC */ 888 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */ 889 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */ 890 #define OB_INTR_MASK 0xFFFFFFFF 891 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF 892 #define WRITE_SEQ_OFF 0x000000FC 893 #define HOST_DIAG_OFF 0x000000F8 894 #define DIAG_RESET_ADAPTER 0x00000004 895 #define DIAG_WRITE_ENABLE 0x00000080 896 /* 897 * All MFI register set macros accept mrsas_register_set* 898 */ 899 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \ 900 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v)) 901 902 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \ 903 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF)) 904 905 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \ 906 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v)) 907 908 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \ 909 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v)) 910 911 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \ 912 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF)) 913 914 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \ 915 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v)) 916 917 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \ 918 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF)) 919 920 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \ 921 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v)) 922 923 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \ 924 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF)) 925 926 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \ 927 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v)) 928 929 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \ 930 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF)) 931 932 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 933 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v)) 934 935 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \ 936 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \ 937 (v)) 938 939 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \ 940 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF)) 941 942 /* 943 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data 944 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs 945 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled. 946 */ 947 #define MFI_OB_INTR_STATUS_MASK 0x00000002 948 949 /* 950 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also 951 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has 952 * been set in this flag along with bit 1. 953 */ 954 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001 955 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005 956 957 #define MFI_POLL_TIMEOUT_SECS 60 958 959 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \ 960 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1) 961 #define MFI_DISABLE_INTR(instance) \ 962 { \ 963 uint32_t disable = 1; \ 964 uint32_t mask = ddi_get32((instance)->regmap_handle, \ 965 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\ 966 mask &= ~disable; \ 967 ddi_put32((instance)->regmap_handle, (uint32_t *) \ 968 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \ 969 } 970 971 /* By default, the firmware programs for 8 Kbytes of memory */ 972 #define DEFAULT_MFI_MEM_SZ 8192 973 #define MINIMUM_MFI_MEM_SZ 4096 974 975 /* DCMD Message Frame MAILBOX0-11 */ 976 #define DCMD_MBOX_SZ 12 977 978 979 struct mrsas_register_set { 980 uint32_t reserved_0[4]; 981 982 uint32_t inbound_msg_0; 983 uint32_t inbound_msg_1; 984 uint32_t outbound_msg_0; 985 uint32_t outbound_msg_1; 986 987 uint32_t inbound_doorbell; 988 uint32_t inbound_intr_status; 989 uint32_t inbound_intr_mask; 990 991 uint32_t outbound_doorbell; 992 uint32_t outbound_intr_status; 993 uint32_t outbound_intr_mask; 994 995 uint32_t reserved_1[2]; 996 997 uint32_t inbound_queue_port; 998 uint32_t outbound_queue_port; 999 1000 uint32_t reserved_2[22]; 1001 1002 uint32_t outbound_doorbell_clear; 1003 1004 uint32_t reserved_3[3]; 1005 1006 uint32_t outbound_scratch_pad; 1007 1008 uint32_t reserved_4[3]; 1009 1010 uint32_t inbound_low_queue_port; 1011 1012 uint32_t inbound_high_queue_port; 1013 1014 uint32_t reserved_5; 1015 uint32_t index_registers[820]; 1016 }; 1017 1018 struct mrsas_sge32 { 1019 uint32_t phys_addr; 1020 uint32_t length; 1021 }; 1022 1023 struct mrsas_sge64 { 1024 uint64_t phys_addr; 1025 uint32_t length; 1026 }; 1027 1028 struct mrsas_sge_ieee { 1029 uint64_t phys_addr; 1030 uint32_t length; 1031 uint32_t flag; 1032 }; 1033 1034 union mrsas_sgl { 1035 struct mrsas_sge32 sge32[1]; 1036 struct mrsas_sge64 sge64[1]; 1037 struct mrsas_sge_ieee sge_ieee[1]; 1038 }; 1039 1040 struct mrsas_header { 1041 uint8_t cmd; 1042 uint8_t sense_len; 1043 uint8_t cmd_status; 1044 uint8_t scsi_status; 1045 1046 uint8_t target_id; 1047 uint8_t lun; 1048 uint8_t cdb_len; 1049 uint8_t sge_count; 1050 1051 uint32_t context; 1052 uint8_t req_id; 1053 uint8_t msgvector; 1054 uint16_t pad_0; 1055 1056 uint16_t flags; 1057 uint16_t timeout; 1058 uint32_t data_xferlen; 1059 }; 1060 1061 union mrsas_sgl_frame { 1062 struct mrsas_sge32 sge32[8]; 1063 struct mrsas_sge64 sge64[5]; 1064 }; 1065 1066 struct mrsas_init_frame { 1067 uint8_t cmd; 1068 uint8_t reserved_0; 1069 uint8_t cmd_status; 1070 1071 uint8_t reserved_1; 1072 uint32_t reserved_2; 1073 1074 uint32_t context; 1075 uint8_t req_id; 1076 uint8_t msgvector; 1077 uint16_t pad_0; 1078 1079 uint16_t flags; 1080 uint16_t reserved_3; 1081 uint32_t data_xfer_len; 1082 1083 uint32_t queue_info_new_phys_addr_lo; 1084 uint32_t queue_info_new_phys_addr_hi; 1085 uint32_t queue_info_old_phys_addr_lo; 1086 uint32_t queue_info_old_phys_addr_hi; 1087 1088 uint32_t reserved_4[6]; 1089 }; 1090 1091 struct mrsas_init_queue_info { 1092 uint32_t init_flags; 1093 uint32_t reply_queue_entries; 1094 1095 uint32_t reply_queue_start_phys_addr_lo; 1096 uint32_t reply_queue_start_phys_addr_hi; 1097 uint32_t producer_index_phys_addr_lo; 1098 uint32_t producer_index_phys_addr_hi; 1099 uint32_t consumer_index_phys_addr_lo; 1100 uint32_t consumer_index_phys_addr_hi; 1101 }; 1102 1103 struct mrsas_io_frame { 1104 uint8_t cmd; 1105 uint8_t sense_len; 1106 uint8_t cmd_status; 1107 uint8_t scsi_status; 1108 1109 uint8_t target_id; 1110 uint8_t access_byte; 1111 uint8_t reserved_0; 1112 uint8_t sge_count; 1113 1114 uint32_t context; 1115 uint8_t req_id; 1116 uint8_t msgvector; 1117 uint16_t pad_0; 1118 1119 uint16_t flags; 1120 uint16_t timeout; 1121 uint32_t lba_count; 1122 1123 uint32_t sense_buf_phys_addr_lo; 1124 uint32_t sense_buf_phys_addr_hi; 1125 1126 uint32_t start_lba_lo; 1127 uint32_t start_lba_hi; 1128 1129 union mrsas_sgl sgl; 1130 }; 1131 1132 struct mrsas_pthru_frame { 1133 uint8_t cmd; 1134 uint8_t sense_len; 1135 uint8_t cmd_status; 1136 uint8_t scsi_status; 1137 1138 uint8_t target_id; 1139 uint8_t lun; 1140 uint8_t cdb_len; 1141 uint8_t sge_count; 1142 1143 uint32_t context; 1144 uint8_t req_id; 1145 uint8_t msgvector; 1146 uint16_t pad_0; 1147 1148 uint16_t flags; 1149 uint16_t timeout; 1150 uint32_t data_xfer_len; 1151 1152 uint32_t sense_buf_phys_addr_lo; 1153 uint32_t sense_buf_phys_addr_hi; 1154 1155 uint8_t cdb[16]; 1156 union mrsas_sgl sgl; 1157 }; 1158 1159 struct mrsas_dcmd_frame { 1160 uint8_t cmd; 1161 uint8_t reserved_0; 1162 uint8_t cmd_status; 1163 uint8_t reserved_1[4]; 1164 uint8_t sge_count; 1165 1166 uint32_t context; 1167 uint8_t req_id; 1168 uint8_t msgvector; 1169 uint16_t pad_0; 1170 1171 uint16_t flags; 1172 uint16_t timeout; 1173 1174 uint32_t data_xfer_len; 1175 uint32_t opcode; 1176 1177 union { 1178 uint8_t b[DCMD_MBOX_SZ]; 1179 uint16_t s[6]; 1180 uint32_t w[3]; 1181 } mbox; 1182 1183 union mrsas_sgl sgl; 1184 }; 1185 1186 struct mrsas_abort_frame { 1187 uint8_t cmd; 1188 uint8_t reserved_0; 1189 uint8_t cmd_status; 1190 1191 uint8_t reserved_1; 1192 uint32_t reserved_2; 1193 1194 uint32_t context; 1195 uint8_t req_id; 1196 uint8_t msgvector; 1197 uint16_t pad_0; 1198 1199 uint16_t flags; 1200 uint16_t reserved_3; 1201 uint32_t reserved_4; 1202 1203 uint32_t abort_context; 1204 uint32_t pad_1; 1205 1206 uint32_t abort_mfi_phys_addr_lo; 1207 uint32_t abort_mfi_phys_addr_hi; 1208 1209 uint32_t reserved_5[6]; 1210 }; 1211 1212 struct mrsas_smp_frame { 1213 uint8_t cmd; 1214 uint8_t reserved_1; 1215 uint8_t cmd_status; 1216 uint8_t connection_status; 1217 1218 uint8_t reserved_2[3]; 1219 uint8_t sge_count; 1220 1221 uint32_t context; 1222 uint8_t req_id; 1223 uint8_t msgvector; 1224 uint16_t pad_0; 1225 1226 uint16_t flags; 1227 uint16_t timeout; 1228 1229 uint32_t data_xfer_len; 1230 1231 uint64_t sas_addr; 1232 1233 union mrsas_sgl sgl[2]; 1234 }; 1235 1236 struct mrsas_stp_frame { 1237 uint8_t cmd; 1238 uint8_t reserved_1; 1239 uint8_t cmd_status; 1240 uint8_t connection_status; 1241 1242 uint8_t target_id; 1243 uint8_t reserved_2[2]; 1244 uint8_t sge_count; 1245 1246 uint32_t context; 1247 uint8_t req_id; 1248 uint8_t msgvector; 1249 uint16_t pad_0; 1250 1251 uint16_t flags; 1252 uint16_t timeout; 1253 1254 uint32_t data_xfer_len; 1255 1256 uint16_t fis[10]; 1257 uint32_t stp_flags; 1258 union mrsas_sgl sgl; 1259 }; 1260 1261 union mrsas_frame { 1262 struct mrsas_header hdr; 1263 struct mrsas_init_frame init; 1264 struct mrsas_io_frame io; 1265 struct mrsas_pthru_frame pthru; 1266 struct mrsas_dcmd_frame dcmd; 1267 struct mrsas_abort_frame abort; 1268 struct mrsas_smp_frame smp; 1269 struct mrsas_stp_frame stp; 1270 1271 uint8_t raw_bytes[64]; 1272 }; 1273 1274 typedef struct mrsas_pd_address { 1275 uint16_t device_id; 1276 uint16_t encl_id; 1277 1278 union { 1279 struct { 1280 uint8_t encl_index; 1281 uint8_t slot_number; 1282 } pd_address; 1283 struct { 1284 uint8_t encl_position; 1285 uint8_t encl_connector_index; 1286 } encl_address; 1287 }address; 1288 1289 uint8_t scsi_dev_type; 1290 1291 union { 1292 uint8_t port_bitmap; 1293 uint8_t port_numbers; 1294 } connected; 1295 1296 uint64_t sas_addr[2]; 1297 } mrsas_pd_address_t; 1298 1299 union mrsas_evt_class_locale { 1300 struct { 1301 uint16_t locale; 1302 uint8_t reserved; 1303 int8_t class; 1304 } members; 1305 1306 uint32_t word; 1307 }; 1308 1309 struct mrsas_evt_log_info { 1310 uint32_t newest_seq_num; 1311 uint32_t oldest_seq_num; 1312 uint32_t clear_seq_num; 1313 uint32_t shutdown_seq_num; 1314 uint32_t boot_seq_num; 1315 }; 1316 1317 struct mrsas_progress { 1318 uint16_t progress; 1319 uint16_t elapsed_seconds; 1320 }; 1321 1322 struct mrsas_evtarg_ld { 1323 uint16_t target_id; 1324 uint8_t ld_index; 1325 uint8_t reserved; 1326 }; 1327 1328 struct mrsas_evtarg_pd { 1329 uint16_t device_id; 1330 uint8_t encl_index; 1331 uint8_t slot_number; 1332 }; 1333 1334 struct mrsas_evt_detail { 1335 uint32_t seq_num; 1336 uint32_t time_stamp; 1337 uint32_t code; 1338 union mrsas_evt_class_locale cl; 1339 uint8_t arg_type; 1340 uint8_t reserved1[15]; 1341 1342 union { 1343 struct { 1344 struct mrsas_evtarg_pd pd; 1345 uint8_t cdb_length; 1346 uint8_t sense_length; 1347 uint8_t reserved[2]; 1348 uint8_t cdb[16]; 1349 uint8_t sense[64]; 1350 } cdbSense; 1351 1352 struct mrsas_evtarg_ld ld; 1353 1354 struct { 1355 struct mrsas_evtarg_ld ld; 1356 uint64_t count; 1357 } ld_count; 1358 1359 struct { 1360 uint64_t lba; 1361 struct mrsas_evtarg_ld ld; 1362 } ld_lba; 1363 1364 struct { 1365 struct mrsas_evtarg_ld ld; 1366 uint32_t prevOwner; 1367 uint32_t newOwner; 1368 } ld_owner; 1369 1370 struct { 1371 uint64_t ld_lba; 1372 uint64_t pd_lba; 1373 struct mrsas_evtarg_ld ld; 1374 struct mrsas_evtarg_pd pd; 1375 } ld_lba_pd_lba; 1376 1377 struct { 1378 struct mrsas_evtarg_ld ld; 1379 struct mrsas_progress prog; 1380 } ld_prog; 1381 1382 struct { 1383 struct mrsas_evtarg_ld ld; 1384 uint32_t prev_state; 1385 uint32_t new_state; 1386 } ld_state; 1387 1388 struct { 1389 uint64_t strip; 1390 struct mrsas_evtarg_ld ld; 1391 } ld_strip; 1392 1393 struct mrsas_evtarg_pd pd; 1394 1395 struct { 1396 struct mrsas_evtarg_pd pd; 1397 uint32_t err; 1398 } pd_err; 1399 1400 struct { 1401 uint64_t lba; 1402 struct mrsas_evtarg_pd pd; 1403 } pd_lba; 1404 1405 struct { 1406 uint64_t lba; 1407 struct mrsas_evtarg_pd pd; 1408 struct mrsas_evtarg_ld ld; 1409 } pd_lba_ld; 1410 1411 struct { 1412 struct mrsas_evtarg_pd pd; 1413 struct mrsas_progress prog; 1414 } pd_prog; 1415 1416 struct { 1417 struct mrsas_evtarg_pd pd; 1418 uint32_t prevState; 1419 uint32_t newState; 1420 } pd_state; 1421 1422 struct { 1423 uint16_t vendorId; 1424 uint16_t deviceId; 1425 uint16_t subVendorId; 1426 uint16_t subDeviceId; 1427 } pci; 1428 1429 uint32_t rate; 1430 char str[96]; 1431 1432 struct { 1433 uint32_t rtc; 1434 uint32_t elapsedSeconds; 1435 } time; 1436 1437 struct { 1438 uint32_t ecar; 1439 uint32_t elog; 1440 char str[64]; 1441 } ecc; 1442 1443 mrsas_pd_address_t pd_addr; 1444 1445 uint8_t b[96]; 1446 uint16_t s[48]; 1447 uint32_t w[24]; 1448 uint64_t d[12]; 1449 } args; 1450 1451 char description[128]; 1452 1453 }; 1454 1455 /* only 63 are usable by the application */ 1456 #define MAX_LOGICAL_DRIVES 64 1457 /* only 255 physical devices may be used */ 1458 #define MAX_PHYSICAL_DEVICES 256 1459 #define MAX_PD_PER_ENCLOSURE 64 1460 /* maximum disks per array */ 1461 #define MAX_ROW_SIZE 32 1462 /* maximum spans per logical drive */ 1463 #define MAX_SPAN_DEPTH 8 1464 /* maximum number of arrays a hot spare may be dedicated to */ 1465 #define MAX_ARRAYS_DEDICATED 16 1466 /* maximum number of arrays which may exist */ 1467 #define MAX_ARRAYS 128 1468 /* maximum number of foreign configs that may ha managed at once */ 1469 #define MAX_FOREIGN_CONFIGS 8 1470 /* maximum spares (global and dedicated combined) */ 1471 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES 1472 /* maximum possible Target IDs (i.e. 0 to 63) */ 1473 #define MAX_TARGET_ID 63 1474 /* maximum number of supported enclosures */ 1475 #define MAX_ENCLOSURES 32 1476 /* maximum number of PHYs per controller */ 1477 #define MAX_PHYS_PER_CONTROLLER 16 1478 /* maximum number of LDs per array (due to DDF limitations) */ 1479 #define MAX_LDS_PER_ARRAY 16 1480 1481 /* 1482 * ----------------------------------------------------------------------------- 1483 * ----------------------------------------------------------------------------- 1484 * 1485 * Logical Drive commands 1486 * 1487 * ----------------------------------------------------------------------------- 1488 * ----------------------------------------------------------------------------- 1489 */ 1490 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */ 1491 1492 /* 1493 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST 1494 * dcmd.mbox - reserved 1495 * dcmd.sge IN - ptr to returned MR_LD_LIST structure 1496 * Desc: Return the logical drive list structure 1497 * Status: No error 1498 */ 1499 1500 /* 1501 * defines the logical drive reference structure 1502 */ 1503 typedef union _MR_LD_REF { /* LD reference structure */ 1504 struct { 1505 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */ 1506 uint8_t reserved; /* reserved for in line with MR_PD_REF */ 1507 uint16_t seqNum; /* Sequence Number */ 1508 } ld_ref; 1509 uint32_t ref; /* shorthand reference to full 32-bits */ 1510 } MR_LD_REF; /* 4 bytes */ 1511 1512 /* 1513 * defines the logical drive list structure 1514 */ 1515 typedef struct _MR_LD_LIST { 1516 uint32_t ldCount; /* number of LDs */ 1517 uint32_t reserved; /* pad to 8-byte boundary */ 1518 struct { 1519 MR_LD_REF ref; /* LD reference */ 1520 uint8_t state; /* current LD state (MR_LD_STATE) */ 1521 uint8_t reserved[3]; /* pad to 8-byte boundary */ 1522 uint64_t size; /* LD size */ 1523 } ldList[MAX_LOGICAL_DRIVES]; 1524 } MR_LD_LIST; 1525 1526 struct mrsas_drv_ver { 1527 uint8_t signature[12]; 1528 uint8_t os_name[16]; 1529 uint8_t os_ver[12]; 1530 uint8_t drv_name[20]; 1531 uint8_t drv_ver[32]; 1532 uint8_t drv_rel_date[20]; 1533 }; 1534 1535 #define PCI_TYPE0_ADDRESSES 6 1536 #define PCI_TYPE1_ADDRESSES 2 1537 #define PCI_TYPE2_ADDRESSES 5 1538 1539 struct mrsas_pci_common_header { 1540 uint16_t vendorID; /* (ro) */ 1541 uint16_t deviceID; /* (ro) */ 1542 uint16_t command; /* Device control */ 1543 uint16_t status; 1544 uint8_t revisionID; /* (ro) */ 1545 uint8_t progIf; /* (ro) */ 1546 uint8_t subClass; /* (ro) */ 1547 uint8_t baseClass; /* (ro) */ 1548 uint8_t cacheLineSize; /* (ro+) */ 1549 uint8_t latencyTimer; /* (ro+) */ 1550 uint8_t headerType; /* (ro) */ 1551 uint8_t bist; /* Built in self test */ 1552 1553 union { 1554 struct { 1555 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 1556 uint32_t cis; 1557 uint16_t subVendorID; 1558 uint16_t subSystemID; 1559 uint32_t romBaseAddress; 1560 uint8_t capabilitiesPtr; 1561 uint8_t reserved1[3]; 1562 uint32_t reserved2; 1563 uint8_t interruptLine; 1564 uint8_t interruptPin; /* (ro) */ 1565 uint8_t minimumGrant; /* (ro) */ 1566 uint8_t maximumLatency; /* (ro) */ 1567 } type_0; 1568 1569 struct { 1570 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 1571 uint8_t primaryBus; 1572 uint8_t secondaryBus; 1573 uint8_t subordinateBus; 1574 uint8_t secondaryLatency; 1575 uint8_t ioBase; 1576 uint8_t ioLimit; 1577 uint16_t secondaryStatus; 1578 uint16_t memoryBase; 1579 uint16_t memoryLimit; 1580 uint16_t prefetchBase; 1581 uint16_t prefetchLimit; 1582 uint32_t prefetchBaseUpper32; 1583 uint32_t prefetchLimitUpper32; 1584 uint16_t ioBaseUpper16; 1585 uint16_t ioLimitUpper16; 1586 uint8_t capabilitiesPtr; 1587 uint8_t reserved1[3]; 1588 uint32_t romBaseAddress; 1589 uint8_t interruptLine; 1590 uint8_t interruptPin; 1591 uint16_t bridgeControl; 1592 } type_1; 1593 1594 struct { 1595 uint32_t socketRegistersBaseAddress; 1596 uint8_t capabilitiesPtr; 1597 uint8_t reserved; 1598 uint16_t secondaryStatus; 1599 uint8_t primaryBus; 1600 uint8_t secondaryBus; 1601 uint8_t subordinateBus; 1602 uint8_t secondaryLatency; 1603 struct { 1604 uint32_t base; 1605 uint32_t limit; 1606 } range[PCI_TYPE2_ADDRESSES-1]; 1607 uint8_t interruptLine; 1608 uint8_t interruptPin; 1609 uint16_t bridgeControl; 1610 } type_2; 1611 } header; 1612 }; 1613 1614 struct mrsas_pci_link_capability { 1615 union { 1616 struct { 1617 uint32_t linkSpeed :4; 1618 uint32_t linkWidth :6; 1619 uint32_t aspmSupport :2; 1620 uint32_t losExitLatency :3; 1621 uint32_t l1ExitLatency :3; 1622 uint32_t rsvdp :6; 1623 uint32_t portNumber :8; 1624 } bits; 1625 1626 uint32_t asUlong; 1627 } cap; 1628 1629 }; 1630 1631 struct mrsas_pci_link_status_capability { 1632 union { 1633 struct { 1634 uint16_t linkSpeed :4; 1635 uint16_t negotiatedLinkWidth :6; 1636 uint16_t linkTrainingError :1; 1637 uint16_t linkTraning :1; 1638 uint16_t slotClockConfig :1; 1639 uint16_t rsvdZ :3; 1640 } bits; 1641 1642 uint16_t asUshort; 1643 } stat_cap; 1644 1645 uint16_t reserved; 1646 1647 }; 1648 1649 struct mrsas_pci_capabilities { 1650 struct mrsas_pci_link_capability linkCapability; 1651 struct mrsas_pci_link_status_capability linkStatusCapability; 1652 }; 1653 1654 struct mrsas_pci_information 1655 { 1656 uint32_t busNumber; 1657 uint8_t deviceNumber; 1658 uint8_t functionNumber; 1659 uint8_t interruptVector; 1660 uint8_t reserved; 1661 struct mrsas_pci_common_header pciHeaderInfo; 1662 struct mrsas_pci_capabilities capability; 1663 uint8_t reserved2[32]; 1664 }; 1665 1666 struct mrsas_ioctl { 1667 uint16_t version; 1668 uint16_t controller_id; 1669 uint8_t signature[8]; 1670 uint32_t reserved_1; 1671 uint32_t control_code; 1672 uint32_t reserved_2[2]; 1673 uint8_t frame[64]; 1674 union mrsas_sgl_frame sgl_frame; 1675 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH]; 1676 uint8_t data[1]; 1677 }; 1678 1679 struct mrsas_aen { 1680 uint16_t host_no; 1681 uint16_t cmd_status; 1682 uint32_t seq_num; 1683 uint32_t class_locale_word; 1684 }; 1685 #pragma pack() 1686 1687 #ifndef DDI_VENDOR_LSI 1688 #define DDI_VENDOR_LSI "LSI" 1689 #endif /* DDI_VENDOR_LSI */ 1690 1691 #ifndef KMDB_MODULE 1692 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 1693 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t); 1694 #ifdef __sparc 1695 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t); 1696 #else /* __sparc */ 1697 static int mrsas_quiesce(dev_info_t *); 1698 #endif /* __sparc */ 1699 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t); 1700 static int mrsas_open(dev_t *, int, int, cred_t *); 1701 static int mrsas_close(dev_t, int, int, cred_t *); 1702 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 1703 1704 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *, 1705 scsi_hba_tran_t *, struct scsi_device *); 1706 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register 1707 struct scsi_pkt *, struct buf *, int, int, int, int, 1708 int (*)(), caddr_t); 1709 static int mrsas_tran_start(struct scsi_address *, 1710 register struct scsi_pkt *); 1711 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *); 1712 static int mrsas_tran_reset(struct scsi_address *, int); 1713 static int mrsas_tran_getcap(struct scsi_address *, char *, int); 1714 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int); 1715 static void mrsas_tran_destroy_pkt(struct scsi_address *, 1716 struct scsi_pkt *); 1717 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *); 1718 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *); 1719 static uint_t mrsas_isr(); 1720 static uint_t mrsas_softintr(); 1721 1722 static int init_mfi(struct mrsas_instance *); 1723 static int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t); 1724 static int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *, 1725 uchar_t); 1726 static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *); 1727 static void return_mfi_pkt(struct mrsas_instance *, 1728 struct mrsas_cmd *); 1729 1730 static void free_space_for_mfi(struct mrsas_instance *); 1731 static void free_additional_dma_buffer(struct mrsas_instance *); 1732 static int alloc_additional_dma_buffer(struct mrsas_instance *); 1733 static int read_fw_status_reg_ppc(struct mrsas_instance *); 1734 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *); 1735 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *, 1736 struct mrsas_cmd *); 1737 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *, 1738 struct mrsas_cmd *); 1739 static void enable_intr_ppc(struct mrsas_instance *); 1740 static void disable_intr_ppc(struct mrsas_instance *); 1741 static int intr_ack_ppc(struct mrsas_instance *); 1742 static int mfi_state_transition_to_ready(struct mrsas_instance *); 1743 static void destroy_mfi_frame_pool(struct mrsas_instance *); 1744 static int create_mfi_frame_pool(struct mrsas_instance *); 1745 static int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *, 1746 struct buf *, int, int (*)()); 1747 static int mrsas_dma_move(struct mrsas_instance *, 1748 struct scsi_pkt *, struct buf *); 1749 static void flush_cache(struct mrsas_instance *instance); 1750 static void display_scsi_inquiry(caddr_t); 1751 static int start_mfi_aen(struct mrsas_instance *instance); 1752 static int handle_drv_ioctl(struct mrsas_instance *instance, 1753 struct mrsas_ioctl *ioctl, int mode); 1754 static int handle_mfi_ioctl(struct mrsas_instance *instance, 1755 struct mrsas_ioctl *ioctl, int mode); 1756 static int handle_mfi_aen(struct mrsas_instance *instance, 1757 struct mrsas_aen *aen); 1758 static void fill_up_drv_ver(struct mrsas_drv_ver *dv); 1759 static struct mrsas_cmd *build_cmd(struct mrsas_instance *instance, 1760 struct scsi_address *ap, struct scsi_pkt *pkt, 1761 uchar_t *cmd_done); 1762 #ifndef __sparc 1763 static int wait_for_outstanding(struct mrsas_instance *instance); 1764 #endif /* __sparc */ 1765 static int register_mfi_aen(struct mrsas_instance *instance, 1766 uint32_t seq_num, uint32_t class_locale_word); 1767 static int issue_mfi_pthru(struct mrsas_instance *instance, struct 1768 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1769 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct 1770 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1771 static int issue_mfi_smp(struct mrsas_instance *instance, struct 1772 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1773 static int issue_mfi_stp(struct mrsas_instance *instance, struct 1774 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1775 static int abort_aen_cmd(struct mrsas_instance *instance, 1776 struct mrsas_cmd *cmd_to_abort); 1777 1778 static int mrsas_common_check(struct mrsas_instance *instance, 1779 struct mrsas_cmd *cmd); 1780 static void mrsas_fm_init(struct mrsas_instance *instance); 1781 static void mrsas_fm_fini(struct mrsas_instance *instance); 1782 static int mrsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 1783 const void *); 1784 static void mrsas_fm_ereport(struct mrsas_instance *instance, 1785 char *detail); 1786 static int mrsas_check_dma_handle(ddi_dma_handle_t handle); 1787 static int mrsas_check_acc_handle(ddi_acc_handle_t handle); 1788 1789 static void mrsas_rem_intrs(struct mrsas_instance *instance); 1790 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type); 1791 1792 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *, 1793 scsi_hba_tran_t *, struct scsi_device *); 1794 static int mrsas_tran_bus_config(dev_info_t *, uint_t, 1795 ddi_bus_config_op_t, void *, dev_info_t **); 1796 static int mrsas_parse_devname(char *, int *, int *); 1797 static int mrsas_config_all_devices(struct mrsas_instance *); 1798 static int mrsas_config_scsi_device(struct mrsas_instance *, 1799 struct scsi_device *, dev_info_t **); 1800 static int mrsas_config_ld(struct mrsas_instance *, uint16_t, 1801 uint8_t, dev_info_t **); 1802 static dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, 1803 uint8_t); 1804 static int mrsas_name_node(dev_info_t *, char *, int); 1805 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *); 1806 static int mrsas_service_evt(struct mrsas_instance *, int, int, int, 1807 uint64_t); 1808 static int mrsas_mode_sense_build(struct scsi_pkt *); 1809 static void push_pending_mfi_pkt(struct mrsas_instance *, 1810 struct mrsas_cmd *); 1811 static int mrsas_issue_init_mfi(struct mrsas_instance *); 1812 static int mrsas_issue_pending_cmds(struct mrsas_instance *); 1813 static int mrsas_print_pending_cmds(struct mrsas_instance *); 1814 static int mrsas_complete_pending_cmds(struct mrsas_instance *); 1815 static int mrsas_reset_ppc(struct mrsas_instance *); 1816 static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *); 1817 static int mrsas_kill_adapter(struct mrsas_instance *); 1818 static void io_timeout_checker(void *instance); 1819 static void complete_cmd_in_sync_mode(struct mrsas_instance *, 1820 struct mrsas_cmd *); 1821 1822 #endif /* KMDB_MODULE */ 1823 1824 1825 #ifdef __cplusplus 1826 } 1827 #endif 1828 1829 #endif /* _MR_SAS_H_ */ 1830