1 /* 2 * mr_sas.h: header for mr_sas 3 * 4 * Solaris MegaRAID driver for SAS2.0 controllers 5 * Copyright (c) 2008-2009, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the author nor the names of its contributors may be 19 * used to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 * DAMAGE. 34 */ 35 36 /* 37 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 38 * Use is subject to license terms. 39 */ 40 41 #ifndef _MR_SAS_H_ 42 #define _MR_SAS_H_ 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 #include <sys/scsi/scsi.h> 49 #include "mr_sas_list.h" 50 51 /* 52 * MegaRAID SAS2.0 Driver meta data 53 */ 54 #define MRSAS_VERSION "LSIv2.0" 55 #define MRSAS_RELDATE "Jan 9, 2009" 56 57 #define MRSAS_TRUE 1 58 #define MRSAS_FALSE 0 59 60 /* 61 * MegaRAID SAS2.0 device id conversion definitions. 62 */ 63 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT) 64 65 /* 66 * MegaRAID SAS2.0 supported controllers 67 */ 68 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078 69 #define PCI_DEVICE_ID_LSI_2108V 0x0079 70 71 /* 72 * Register Index for 2108 Controllers. 73 */ 74 #define REGISTER_SET_IO_2108 (2) 75 76 #define MRSAS_MAX_SGE_CNT 0x50 77 78 #define MRSAS_IOCTL_DRIVER 0x12341234 79 #define MRSAS_IOCTL_FIRMWARE 0x12345678 80 #define MRSAS_IOCTL_AEN 0x87654321 81 82 #define MRSAS_1_SECOND 1000000 83 84 /* Dynamic Enumeration Flags */ 85 #define MRSAS_PD_LUN 1 86 #define MRSAS_LD_LUN 0 87 #define MRSAS_PD_TGT_MAX 255 88 #define MRSAS_GET_PD_MAX(s) ((s)->mr_pd_max) 89 #define WWN_STRLEN 17 90 91 /* 92 * ===================================== 93 * MegaRAID SAS2.0 MFI firmware definitions 94 * ===================================== 95 */ 96 /* 97 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for 98 * protocol between the software and firmware. Commands are issued using 99 * "message frames" 100 */ 101 102 /* 103 * FW posts its state in upper 4 bits of outbound_msg_0 register 104 */ 105 #define MFI_STATE_SHIFT 28 106 #define MFI_STATE_MASK ((uint32_t)0xF<<MFI_STATE_SHIFT) 107 #define MFI_STATE_UNDEFINED ((uint32_t)0x0<<MFI_STATE_SHIFT) 108 #define MFI_STATE_BB_INIT ((uint32_t)0x1<<MFI_STATE_SHIFT) 109 #define MFI_STATE_FW_INIT ((uint32_t)0x4<<MFI_STATE_SHIFT) 110 #define MFI_STATE_WAIT_HANDSHAKE ((uint32_t)0x6<<MFI_STATE_SHIFT) 111 #define MFI_STATE_FW_INIT_2 ((uint32_t)0x7<<MFI_STATE_SHIFT) 112 #define MFI_STATE_DEVICE_SCAN ((uint32_t)0x8<<MFI_STATE_SHIFT) 113 #define MFI_STATE_BOOT_MESSAGE_PENDING ((uint32_t)0x9<<MFI_STATE_SHIFT) 114 #define MFI_STATE_FLUSH_CACHE ((uint32_t)0xA<<MFI_STATE_SHIFT) 115 #define MFI_STATE_READY ((uint32_t)0xB<<MFI_STATE_SHIFT) 116 #define MFI_STATE_OPERATIONAL ((uint32_t)0xC<<MFI_STATE_SHIFT) 117 #define MFI_STATE_FAULT ((uint32_t)0xF<<MFI_STATE_SHIFT) 118 119 #define MRMFI_FRAME_SIZE 64 120 121 /* 122 * During FW init, clear pending cmds & reset state using inbound_msg_0 123 * 124 * ABORT : Abort all pending cmds 125 * READY : Move from OPERATIONAL to READY state; discard queue info 126 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 127 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 128 */ 129 #define MFI_INIT_ABORT 0x00000001 130 #define MFI_INIT_READY 0x00000002 131 #define MFI_INIT_MFIMODE 0x00000004 132 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 133 #define MFI_INIT_HOTPLUG 0x00000010 134 #define MFI_STOP_ADP 0x00000020 135 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT 136 137 /* 138 * MFI frame flags 139 */ 140 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 141 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 142 #define MFI_FRAME_SGL32 0x0000 143 #define MFI_FRAME_SGL64 0x0002 144 #define MFI_FRAME_SENSE32 0x0000 145 #define MFI_FRAME_SENSE64 0x0004 146 #define MFI_FRAME_DIR_NONE 0x0000 147 #define MFI_FRAME_DIR_WRITE 0x0008 148 #define MFI_FRAME_DIR_READ 0x0010 149 #define MFI_FRAME_DIR_BOTH 0x0018 150 151 /* 152 * Definition for cmd_status 153 */ 154 #define MFI_CMD_STATUS_POLL_MODE 0xFF 155 #define MFI_CMD_STATUS_SYNC_MODE 0xFF 156 157 /* 158 * MFI command opcodes 159 */ 160 #define MFI_CMD_OP_INIT 0x00 161 #define MFI_CMD_OP_LD_READ 0x01 162 #define MFI_CMD_OP_LD_WRITE 0x02 163 #define MFI_CMD_OP_LD_SCSI 0x03 164 #define MFI_CMD_OP_PD_SCSI 0x04 165 #define MFI_CMD_OP_DCMD 0x05 166 #define MFI_CMD_OP_ABORT 0x06 167 #define MFI_CMD_OP_SMP 0x07 168 #define MFI_CMD_OP_STP 0x08 169 170 #define MR_DCMD_CTRL_GET_INFO 0x01010000 171 172 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 173 #define MR_FLUSH_CTRL_CACHE 0x01 174 #define MR_FLUSH_DISK_CACHE 0x02 175 176 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 177 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01 178 179 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 180 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 181 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 182 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 183 #define MR_DCMD_PD_GET_INFO 0x02020000 184 185 /* 186 * Solaris Specific MAX values 187 */ 188 #define MAX_SGL 24 189 /* 190 * MFI command completion codes 191 */ 192 enum MFI_STAT { 193 MFI_STAT_OK = 0x00, 194 MFI_STAT_INVALID_CMD = 0x01, 195 MFI_STAT_INVALID_DCMD = 0x02, 196 MFI_STAT_INVALID_PARAMETER = 0x03, 197 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 198 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 199 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 200 MFI_STAT_APP_IN_USE = 0x07, 201 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 202 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 203 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 204 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 205 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 206 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 207 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 208 MFI_STAT_FLASH_BUSY = 0x0f, 209 MFI_STAT_FLASH_ERROR = 0x10, 210 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 211 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 212 MFI_STAT_FLASH_NOT_OPEN = 0x13, 213 MFI_STAT_FLASH_NOT_STARTED = 0x14, 214 MFI_STAT_FLUSH_FAILED = 0x15, 215 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 216 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 217 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 218 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 219 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 220 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 221 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 222 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 223 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 224 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 225 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 226 MFI_STAT_MFC_HW_ERROR = 0x21, 227 MFI_STAT_NO_HW_PRESENT = 0x22, 228 MFI_STAT_NOT_FOUND = 0x23, 229 MFI_STAT_NOT_IN_ENCL = 0x24, 230 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 231 MFI_STAT_PD_TYPE_WRONG = 0x26, 232 MFI_STAT_PR_DISABLED = 0x27, 233 MFI_STAT_ROW_INDEX_INVALID = 0x28, 234 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 235 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 236 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 237 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 238 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 239 MFI_STAT_SCSI_IO_FAILED = 0x2e, 240 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 241 MFI_STAT_SHUTDOWN_FAILED = 0x30, 242 MFI_STAT_TIME_NOT_SET = 0x31, 243 MFI_STAT_WRONG_STATE = 0x32, 244 MFI_STAT_LD_OFFLINE = 0x33, 245 /* UNUSED: 0x34 to 0xfe */ 246 MFI_STAT_INVALID_STATUS = 0xFF 247 }; 248 249 enum MR_EVT_CLASS { 250 MR_EVT_CLASS_DEBUG = -2, 251 MR_EVT_CLASS_PROGRESS = -1, 252 MR_EVT_CLASS_INFO = 0, 253 MR_EVT_CLASS_WARNING = 1, 254 MR_EVT_CLASS_CRITICAL = 2, 255 MR_EVT_CLASS_FATAL = 3, 256 MR_EVT_CLASS_DEAD = 4 257 }; 258 259 enum MR_EVT_LOCALE { 260 MR_EVT_LOCALE_LD = 0x0001, 261 MR_EVT_LOCALE_PD = 0x0002, 262 MR_EVT_LOCALE_ENCL = 0x0004, 263 MR_EVT_LOCALE_BBU = 0x0008, 264 MR_EVT_LOCALE_SAS = 0x0010, 265 MR_EVT_LOCALE_CTRL = 0x0020, 266 MR_EVT_LOCALE_CONFIG = 0x0040, 267 MR_EVT_LOCALE_CLUSTER = 0x0080, 268 MR_EVT_LOCALE_ALL = 0xffff 269 }; 270 271 #define MR_EVT_CFG_CLEARED 0x0004 272 #define MR_EVT_LD_CREATED 0x008a 273 #define MR_EVT_LD_DELETED 0x008b 274 #define MR_EVT_PD_REMOVED_EXT 0x00f8 275 #define MR_EVT_PD_INSERTED_EXT 0x00f7 276 277 enum LD_STATE { 278 LD_OFFLINE = 0, 279 LD_PARTIALLY_DEGRADED = 1, 280 LD_DEGRADED = 2, 281 LD_OPTIMAL = 3, 282 LD_INVALID = 0xFF 283 }; 284 285 enum MRSAS_EVT { 286 MRSAS_EVT_CONFIG_TGT = 0, 287 MRSAS_EVT_UNCONFIG_TGT = 1, 288 MRSAS_EVT_UNCONFIG_SMP = 2 289 }; 290 291 #define DMA_OBJ_ALLOCATED 1 292 #define DMA_OBJ_REALLOCATED 2 293 #define DMA_OBJ_FREED 3 294 295 /* 296 * dma_obj_t - Our DMA object 297 * @param buffer : kernel virtual address 298 * @param size : size of the data to be allocated 299 * @param acc_handle : access handle 300 * @param dma_handle : dma handle 301 * @param dma_cookie : scatter-gather list 302 * @param dma_attr : dma attributes for this buffer 303 * Our DMA object. The caller must initialize the size and dma attributes 304 * (dma_attr) fields before allocating the resources. 305 */ 306 typedef struct { 307 caddr_t buffer; 308 uint32_t size; 309 ddi_acc_handle_t acc_handle; 310 ddi_dma_handle_t dma_handle; 311 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT]; 312 ddi_dma_attr_t dma_attr; 313 uint8_t status; 314 uint8_t reserved[3]; 315 } dma_obj_t; 316 317 struct mrsas_eventinfo { 318 struct mrsas_instance *instance; 319 int tgt; 320 int lun; 321 int event; 322 }; 323 324 struct mrsas_ld { 325 dev_info_t *dip; 326 uint8_t lun_type; 327 uint8_t reserved[3]; 328 }; 329 330 struct mrsas_pd { 331 dev_info_t *dip; 332 uint8_t lun_type; 333 uint8_t dev_id; 334 uint8_t flags; 335 uint8_t reserved; 336 }; 337 338 struct mrsas_pd_info { 339 uint16_t deviceId; 340 uint16_t seqNum; 341 uint8_t inquiryData[96]; 342 uint8_t vpdPage83[64]; 343 uint8_t notSupported; 344 uint8_t scsiDevType; 345 uint8_t a; 346 uint8_t device_speed; 347 uint32_t mediaerrcnt; 348 uint32_t other; 349 uint32_t pred; 350 uint32_t lastpred; 351 uint16_t fwState; 352 uint8_t disabled; 353 uint8_t linkspwwd; 354 uint32_t ddfType; 355 struct { 356 uint8_t count; 357 uint8_t isPathBroken; 358 uint8_t connectorIndex[2]; 359 uint8_t reserved[4]; 360 uint64_t sasAddr[2]; 361 uint8_t reserved2[16]; 362 } pathInfo; 363 }; 364 365 typedef struct mrsas_instance { 366 uint32_t *producer; 367 uint32_t *consumer; 368 369 uint32_t *reply_queue; 370 dma_obj_t mfi_internal_dma_obj; 371 372 uint8_t init_id; 373 uint8_t reserved[3]; 374 375 uint16_t max_num_sge; 376 uint16_t max_fw_cmds; 377 uint32_t max_sectors_per_req; 378 379 struct mrsas_cmd **cmd_list; 380 381 mlist_t cmd_pool_list; 382 kmutex_t cmd_pool_mtx; 383 384 mlist_t cmd_pend_list; 385 kmutex_t cmd_pend_mtx; 386 387 dma_obj_t mfi_evt_detail_obj; 388 struct mrsas_cmd *aen_cmd; 389 390 uint32_t aen_seq_num; 391 uint32_t aen_class_locale_word; 392 393 scsi_hba_tran_t *tran; 394 395 kcondvar_t int_cmd_cv; 396 kmutex_t int_cmd_mtx; 397 398 kcondvar_t aen_cmd_cv; 399 kmutex_t aen_cmd_mtx; 400 401 kcondvar_t abort_cmd_cv; 402 kmutex_t abort_cmd_mtx; 403 404 dev_info_t *dip; 405 ddi_acc_handle_t pci_handle; 406 407 timeout_id_t timeout_id; 408 uint32_t unique_id; 409 uint16_t fw_outstanding; 410 caddr_t regmap; 411 ddi_acc_handle_t regmap_handle; 412 uint8_t isr_level; 413 ddi_iblock_cookie_t iblock_cookie; 414 ddi_iblock_cookie_t soft_iblock_cookie; 415 ddi_softintr_t soft_intr_id; 416 uint8_t softint_running; 417 kmutex_t completed_pool_mtx; 418 mlist_t completed_pool_list; 419 420 caddr_t internal_buf; 421 uint32_t internal_buf_dmac_add; 422 uint32_t internal_buf_size; 423 424 uint16_t vendor_id; 425 uint16_t device_id; 426 uint16_t subsysvid; 427 uint16_t subsysid; 428 int instance; 429 int baseaddress; 430 char iocnode[16]; 431 432 int fm_capabilities; 433 434 struct mrsas_func_ptr *func_ptr; 435 /* MSI interrupts specific */ 436 ddi_intr_handle_t *intr_htable; 437 int intr_type; 438 int intr_cnt; 439 size_t intr_size; 440 uint_t intr_pri; 441 int intr_cap; 442 443 ddi_taskq_t *taskq; 444 struct mrsas_ld *mr_ld_list; 445 } mrsas_t; 446 447 struct mrsas_func_ptr { 448 int (*read_fw_status_reg)(struct mrsas_instance *); 449 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *); 450 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *, 451 struct mrsas_cmd *); 452 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *, 453 struct mrsas_cmd *); 454 void (*enable_intr)(struct mrsas_instance *); 455 void (*disable_intr)(struct mrsas_instance *); 456 int (*intr_ack)(struct mrsas_instance *); 457 }; 458 459 /* 460 * ### Helper routines ### 461 */ 462 463 /* 464 * con_log() - console log routine 465 * @param level : indicates the severity of the message. 466 * @fparam mt : format string 467 * 468 * con_log displays the error messages on the console based on the current 469 * debug level. Also it attaches the appropriate kernel severity level with 470 * the message. 471 * 472 * 473 * console messages debug levels 474 */ 475 #define CL_NONE 0 /* No debug information */ 476 #define CL_ANN 1 /* print unconditionally, announcements */ 477 #define CL_ANN1 2 /* No o/p */ 478 #define CL_DLEVEL1 3 /* debug level 1, informative */ 479 #define CL_DLEVEL2 4 /* debug level 2, verbose */ 480 #define CL_DLEVEL3 5 /* debug level 3, very verbose */ 481 482 #ifdef __SUNPRO_C 483 #define __func__ "" 484 #endif 485 486 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; } 487 488 /* 489 * ### SCSA definitions ### 490 */ 491 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target) 492 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun) 493 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran) 494 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 495 496 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private) 497 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap)) 498 499 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private) 500 #define CMD2PKT(sp) ((sp)->cmd_pkt) 501 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request)) 502 503 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address) 504 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran) 505 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd))) 506 507 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */ 508 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */ 509 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */ 510 511 /* 512 * ### Data structures for ioctl inteface and internal commands ### 513 */ 514 515 /* 516 * Data direction flags 517 */ 518 #define UIOC_RD 0x00001 519 #define UIOC_WR 0x00002 520 521 #define SCP2HOST(scp) (scp)->device->host /* to host */ 522 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */ 523 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */ 524 #define SCP2TARGET(scp) (scp)->device->id /* to target */ 525 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */ 526 527 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0]) 528 #define SCP2ADAPTER(scp) \ 529 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp)) 530 531 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \ 532 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0 533 #define MRDRV_IS_LOGICAL(ap) \ 534 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0 535 #define MAP_DEVICE_ID(instance, ap) \ 536 (ap->a_target) 537 538 #define HIGH_LEVEL_INTR 1 539 #define NORMAL_LEVEL_INTR 0 540 541 /* 542 * scsa_cmd - Per-command mr private data 543 * @param cmd_dmahandle : dma handle 544 * @param cmd_dmacookies : current dma cookies 545 * @param cmd_pkt : scsi_pkt reference 546 * @param cmd_dmacount : dma count 547 * @param cmd_cookie : next cookie 548 * @param cmd_ncookies : cookies per window 549 * @param cmd_cookiecnt : cookies per sub-win 550 * @param cmd_nwin : number of dma windows 551 * @param cmd_curwin : current dma window 552 * @param cmd_dma_offset : current window offset 553 * @param cmd_dma_len : current window length 554 * @param cmd_flags : private flags 555 * @param cmd_cdblen : length of cdb 556 * @param cmd_scblen : length of scb 557 * @param cmd_buf : command buffer 558 * @param channel : channel for scsi sub-system 559 * @param target : target for scsi sub-system 560 * @param lun : LUN for scsi sub-system 561 * 562 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E) 563 * - Pointed to by pkt_ha_private field in scsi_pkt 564 */ 565 struct scsa_cmd { 566 ddi_dma_handle_t cmd_dmahandle; 567 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT]; 568 struct scsi_pkt *cmd_pkt; 569 ulong_t cmd_dmacount; 570 uint_t cmd_cookie; 571 uint_t cmd_ncookies; 572 uint_t cmd_cookiecnt; 573 uint_t cmd_nwin; 574 uint_t cmd_curwin; 575 off_t cmd_dma_offset; 576 ulong_t cmd_dma_len; 577 ulong_t cmd_flags; 578 uint_t cmd_cdblen; 579 uint_t cmd_scblen; 580 struct buf *cmd_buf; 581 ushort_t device_id; 582 uchar_t islogical; 583 uchar_t lun; 584 struct mrsas_device *mrsas_dev; 585 }; 586 587 588 struct mrsas_cmd { 589 union mrsas_frame *frame; 590 uint32_t frame_phys_addr; 591 uint8_t *sense; 592 uint32_t sense_phys_addr; 593 dma_obj_t frame_dma_obj; 594 uint8_t frame_dma_obj_status; 595 596 uint32_t index; 597 uint8_t sync_cmd; 598 uint8_t cmd_status; 599 uint16_t abort_aen; 600 mlist_t list; 601 uint32_t frame_count; 602 struct scsa_cmd *cmd; 603 struct scsi_pkt *pkt; 604 }; 605 606 #define MAX_MGMT_ADAPTERS 1024 607 #define IOC_SIGNATURE "MR-SAS" 608 609 #define IOC_CMD_FIRMWARE 0x0 610 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000 611 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100 612 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200 613 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300 614 615 616 #define MRSAS_MAX_SENSE_LENGTH 32 617 618 struct mrsas_mgmt_info { 619 620 uint16_t count; 621 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS]; 622 uint16_t map[MAX_MGMT_ADAPTERS]; 623 int max_index; 624 }; 625 626 #pragma pack(1) 627 628 /* 629 * SAS controller properties 630 */ 631 struct mrsas_ctrl_prop { 632 uint16_t seq_num; 633 uint16_t pred_fail_poll_interval; 634 uint16_t intr_throttle_count; 635 uint16_t intr_throttle_timeouts; 636 637 uint8_t rebuild_rate; 638 uint8_t patrol_read_rate; 639 uint8_t bgi_rate; 640 uint8_t cc_rate; 641 uint8_t recon_rate; 642 643 uint8_t cache_flush_interval; 644 645 uint8_t spinup_drv_count; 646 uint8_t spinup_delay; 647 648 uint8_t cluster_enable; 649 uint8_t coercion_mode; 650 uint8_t disk_write_cache_disable; 651 uint8_t alarm_enable; 652 653 uint8_t reserved[44]; 654 }; 655 656 /* 657 * SAS controller information 658 */ 659 struct mrsas_ctrl_info { 660 /* PCI device information */ 661 struct { 662 uint16_t vendor_id; 663 uint16_t device_id; 664 uint16_t sub_vendor_id; 665 uint16_t sub_device_id; 666 uint8_t reserved[24]; 667 } pci; 668 669 /* Host interface information */ 670 struct { 671 uint8_t PCIX : 1; 672 uint8_t PCIE : 1; 673 uint8_t iSCSI : 1; 674 uint8_t SAS_3G : 1; 675 uint8_t reserved_0 : 4; 676 uint8_t reserved_1[6]; 677 uint8_t port_count; 678 uint64_t port_addr[8]; 679 } host_interface; 680 681 /* Device (backend) interface information */ 682 struct { 683 uint8_t SPI : 1; 684 uint8_t SAS_3G : 1; 685 uint8_t SATA_1_5G : 1; 686 uint8_t SATA_3G : 1; 687 uint8_t reserved_0 : 4; 688 uint8_t reserved_1[6]; 689 uint8_t port_count; 690 uint64_t port_addr[8]; 691 } device_interface; 692 693 /* List of components residing in flash. All str are null terminated */ 694 uint32_t image_check_word; 695 uint32_t image_component_count; 696 697 struct { 698 char name[8]; 699 char version[32]; 700 char build_date[16]; 701 char built_time[16]; 702 } image_component[8]; 703 704 /* 705 * List of flash components that have been flashed on the card, but 706 * are not in use, pending reset of the adapter. This list will be 707 * empty if a flash operation has not occurred. All stings are null 708 * terminated 709 */ 710 uint32_t pending_image_component_count; 711 712 struct { 713 char name[8]; 714 char version[32]; 715 char build_date[16]; 716 char build_time[16]; 717 } pending_image_component[8]; 718 719 uint8_t max_arms; 720 uint8_t max_spans; 721 uint8_t max_arrays; 722 uint8_t max_lds; 723 724 char product_name[80]; 725 char serial_no[32]; 726 727 /* 728 * Other physical/controller/operation information. Indicates the 729 * presence of the hardware 730 */ 731 struct { 732 uint32_t bbu : 1; 733 uint32_t alarm : 1; 734 uint32_t nvram : 1; 735 uint32_t uart : 1; 736 uint32_t reserved : 28; 737 } hw_present; 738 739 uint32_t current_fw_time; 740 741 /* Maximum data transfer sizes */ 742 uint16_t max_concurrent_cmds; 743 uint16_t max_sge_count; 744 uint32_t max_request_size; 745 746 /* Logical and physical device counts */ 747 uint16_t ld_present_count; 748 uint16_t ld_degraded_count; 749 uint16_t ld_offline_count; 750 751 uint16_t pd_present_count; 752 uint16_t pd_disk_present_count; 753 uint16_t pd_disk_pred_failure_count; 754 uint16_t pd_disk_failed_count; 755 756 /* Memory size information */ 757 uint16_t nvram_size; 758 uint16_t memory_size; 759 uint16_t flash_size; 760 761 /* Error counters */ 762 uint16_t mem_correctable_error_count; 763 uint16_t mem_uncorrectable_error_count; 764 765 /* Cluster information */ 766 uint8_t cluster_permitted; 767 uint8_t cluster_active; 768 uint8_t reserved_1[2]; 769 770 /* Controller capabilities structures */ 771 struct { 772 uint32_t raid_level_0 : 1; 773 uint32_t raid_level_1 : 1; 774 uint32_t raid_level_5 : 1; 775 uint32_t raid_level_1E : 1; 776 uint32_t reserved : 28; 777 } raid_levels; 778 779 struct { 780 uint32_t rbld_rate : 1; 781 uint32_t cc_rate : 1; 782 uint32_t bgi_rate : 1; 783 uint32_t recon_rate : 1; 784 uint32_t patrol_rate : 1; 785 uint32_t alarm_control : 1; 786 uint32_t cluster_supported : 1; 787 uint32_t bbu : 1; 788 uint32_t spanning_allowed : 1; 789 uint32_t dedicated_hotspares : 1; 790 uint32_t revertible_hotspares : 1; 791 uint32_t foreign_config_import : 1; 792 uint32_t self_diagnostic : 1; 793 uint32_t reserved : 19; 794 } adapter_operations; 795 796 struct { 797 uint32_t read_policy : 1; 798 uint32_t write_policy : 1; 799 uint32_t io_policy : 1; 800 uint32_t access_policy : 1; 801 uint32_t reserved : 28; 802 } ld_operations; 803 804 struct { 805 uint8_t min; 806 uint8_t max; 807 uint8_t reserved[2]; 808 } stripe_size_operations; 809 810 struct { 811 uint32_t force_online : 1; 812 uint32_t force_offline : 1; 813 uint32_t force_rebuild : 1; 814 uint32_t reserved : 29; 815 } pd_operations; 816 817 struct { 818 uint32_t ctrl_supports_sas : 1; 819 uint32_t ctrl_supports_sata : 1; 820 uint32_t allow_mix_in_encl : 1; 821 uint32_t allow_mix_in_ld : 1; 822 uint32_t allow_sata_in_cluster : 1; 823 uint32_t reserved : 27; 824 } pd_mix_support; 825 826 /* Include the controller properties (changeable items) */ 827 uint8_t reserved_2[12]; 828 struct mrsas_ctrl_prop properties; 829 830 uint8_t pad[0x800 - 0x640]; 831 }; 832 833 /* 834 * ================================== 835 * MegaRAID SAS2.0 driver definitions 836 * ================================== 837 */ 838 #define MRDRV_MAX_NUM_CMD 1024 839 840 #define MRDRV_MAX_PD_CHANNELS 2 841 #define MRDRV_MAX_LD_CHANNELS 2 842 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \ 843 MRDRV_MAX_LD_CHANNELS) 844 #define MRDRV_MAX_DEV_PER_CHANNEL 128 845 #define MRDRV_DEFAULT_INIT_ID -1 846 #define MRDRV_MAX_CMD_PER_LUN 1000 847 #define MRDRV_MAX_LUN 1 848 #define MRDRV_MAX_LD 64 849 850 #define MRDRV_RESET_WAIT_TIME 300 851 #define MRDRV_RESET_NOTICE_INTERVAL 5 852 853 #define MRSAS_IOCTL_CMD 0 854 855 /* 856 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 857 * SGLs based on the size of dma_addr_t 858 */ 859 #define IS_DMA64 (sizeof (dma_addr_t) == 8) 860 861 #define IB_MSG_0_OFF 0x10 /* XScale */ 862 #define OB_MSG_0_OFF 0x18 /* XScale */ 863 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */ 864 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */ 865 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */ 866 #define IB_QPORT_OFF 0x40 /* XScale & ROC */ 867 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */ 868 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */ 869 #define OB_INTR_MASK 0xFFFFFFFF 870 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF 871 872 /* 873 * All MFI register set macros accept mrsas_register_set* 874 */ 875 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \ 876 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v)) 877 878 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \ 879 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF)) 880 881 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \ 882 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v)) 883 884 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \ 885 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF)) 886 887 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \ 888 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v)) 889 890 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \ 891 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF)) 892 893 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \ 894 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v)) 895 896 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \ 897 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF)) 898 899 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 900 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v)) 901 902 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \ 903 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \ 904 (v)) 905 906 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \ 907 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF)) 908 909 /* 910 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data 911 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs 912 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled. 913 */ 914 #define MFI_OB_INTR_STATUS_MASK 0x00000002 915 916 /* 917 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also 918 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has 919 * been set in this flag along with bit 1. 920 */ 921 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001 922 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005 923 924 #define MFI_POLL_TIMEOUT_SECS 60 925 926 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \ 927 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1) 928 #define MFI_DISABLE_INTR(instance) \ 929 { \ 930 uint32_t disable = 1; \ 931 uint32_t mask = ddi_get32((instance)->regmap_handle, \ 932 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\ 933 mask &= ~disable; \ 934 ddi_put32((instance)->regmap_handle, (uint32_t *) \ 935 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \ 936 } 937 938 /* By default, the firmware programs for 8 Kbytes of memory */ 939 #define DEFAULT_MFI_MEM_SZ 8192 940 #define MINIMUM_MFI_MEM_SZ 4096 941 942 /* DCMD Message Frame MAILBOX0-11 */ 943 #define DCMD_MBOX_SZ 12 944 945 946 struct mrsas_register_set { 947 uint32_t reserved_0[4]; 948 949 uint32_t inbound_msg_0; 950 uint32_t inbound_msg_1; 951 uint32_t outbound_msg_0; 952 uint32_t outbound_msg_1; 953 954 uint32_t inbound_doorbell; 955 uint32_t inbound_intr_status; 956 uint32_t inbound_intr_mask; 957 958 uint32_t outbound_doorbell; 959 uint32_t outbound_intr_status; 960 uint32_t outbound_intr_mask; 961 962 uint32_t reserved_1[2]; 963 964 uint32_t inbound_queue_port; 965 uint32_t outbound_queue_port; 966 967 uint32_t reserved_2[22]; 968 969 uint32_t outbound_doorbell_clear; 970 971 uint32_t reserved_3[3]; 972 973 uint32_t outbound_scratch_pad; 974 975 uint32_t reserved_4[3]; 976 977 uint32_t inbound_low_queue_port; 978 979 uint32_t inbound_high_queue_port; 980 981 uint32_t reserved_5; 982 uint32_t index_registers[820]; 983 }; 984 985 struct mrsas_sge32 { 986 uint32_t phys_addr; 987 uint32_t length; 988 }; 989 990 struct mrsas_sge64 { 991 uint64_t phys_addr; 992 uint32_t length; 993 }; 994 995 union mrsas_sgl { 996 struct mrsas_sge32 sge32[1]; 997 struct mrsas_sge64 sge64[1]; 998 }; 999 1000 struct mrsas_header { 1001 uint8_t cmd; 1002 uint8_t sense_len; 1003 uint8_t cmd_status; 1004 uint8_t scsi_status; 1005 1006 uint8_t target_id; 1007 uint8_t lun; 1008 uint8_t cdb_len; 1009 uint8_t sge_count; 1010 1011 uint32_t context; 1012 uint8_t req_id; 1013 uint8_t msgvector; 1014 uint16_t pad_0; 1015 1016 uint16_t flags; 1017 uint16_t timeout; 1018 uint32_t data_xferlen; 1019 }; 1020 1021 union mrsas_sgl_frame { 1022 struct mrsas_sge32 sge32[8]; 1023 struct mrsas_sge64 sge64[5]; 1024 }; 1025 1026 struct mrsas_init_frame { 1027 uint8_t cmd; 1028 uint8_t reserved_0; 1029 uint8_t cmd_status; 1030 1031 uint8_t reserved_1; 1032 uint32_t reserved_2; 1033 1034 uint32_t context; 1035 uint8_t req_id; 1036 uint8_t msgvector; 1037 uint16_t pad_0; 1038 1039 uint16_t flags; 1040 uint16_t reserved_3; 1041 uint32_t data_xfer_len; 1042 1043 uint32_t queue_info_new_phys_addr_lo; 1044 uint32_t queue_info_new_phys_addr_hi; 1045 uint32_t queue_info_old_phys_addr_lo; 1046 uint32_t queue_info_old_phys_addr_hi; 1047 1048 uint32_t reserved_4[6]; 1049 }; 1050 1051 struct mrsas_init_queue_info { 1052 uint32_t init_flags; 1053 uint32_t reply_queue_entries; 1054 1055 uint32_t reply_queue_start_phys_addr_lo; 1056 uint32_t reply_queue_start_phys_addr_hi; 1057 uint32_t producer_index_phys_addr_lo; 1058 uint32_t producer_index_phys_addr_hi; 1059 uint32_t consumer_index_phys_addr_lo; 1060 uint32_t consumer_index_phys_addr_hi; 1061 }; 1062 1063 struct mrsas_io_frame { 1064 uint8_t cmd; 1065 uint8_t sense_len; 1066 uint8_t cmd_status; 1067 uint8_t scsi_status; 1068 1069 uint8_t target_id; 1070 uint8_t access_byte; 1071 uint8_t reserved_0; 1072 uint8_t sge_count; 1073 1074 uint32_t context; 1075 uint8_t req_id; 1076 uint8_t msgvector; 1077 uint16_t pad_0; 1078 1079 uint16_t flags; 1080 uint16_t timeout; 1081 uint32_t lba_count; 1082 1083 uint32_t sense_buf_phys_addr_lo; 1084 uint32_t sense_buf_phys_addr_hi; 1085 1086 uint32_t start_lba_lo; 1087 uint32_t start_lba_hi; 1088 1089 union mrsas_sgl sgl; 1090 }; 1091 1092 struct mrsas_pthru_frame { 1093 uint8_t cmd; 1094 uint8_t sense_len; 1095 uint8_t cmd_status; 1096 uint8_t scsi_status; 1097 1098 uint8_t target_id; 1099 uint8_t lun; 1100 uint8_t cdb_len; 1101 uint8_t sge_count; 1102 1103 uint32_t context; 1104 uint8_t req_id; 1105 uint8_t msgvector; 1106 uint16_t pad_0; 1107 1108 uint16_t flags; 1109 uint16_t timeout; 1110 uint32_t data_xfer_len; 1111 1112 uint32_t sense_buf_phys_addr_lo; 1113 uint32_t sense_buf_phys_addr_hi; 1114 1115 uint8_t cdb[16]; 1116 union mrsas_sgl sgl; 1117 }; 1118 1119 struct mrsas_dcmd_frame { 1120 uint8_t cmd; 1121 uint8_t reserved_0; 1122 uint8_t cmd_status; 1123 uint8_t reserved_1[4]; 1124 uint8_t sge_count; 1125 1126 uint32_t context; 1127 uint8_t req_id; 1128 uint8_t msgvector; 1129 uint16_t pad_0; 1130 1131 uint16_t flags; 1132 uint16_t timeout; 1133 1134 uint32_t data_xfer_len; 1135 uint32_t opcode; 1136 1137 union { 1138 uint8_t b[DCMD_MBOX_SZ]; 1139 uint16_t s[6]; 1140 uint32_t w[3]; 1141 } mbox; 1142 1143 union mrsas_sgl sgl; 1144 }; 1145 1146 struct mrsas_abort_frame { 1147 uint8_t cmd; 1148 uint8_t reserved_0; 1149 uint8_t cmd_status; 1150 1151 uint8_t reserved_1; 1152 uint32_t reserved_2; 1153 1154 uint32_t context; 1155 uint8_t req_id; 1156 uint8_t msgvector; 1157 uint16_t pad_0; 1158 1159 uint16_t flags; 1160 uint16_t reserved_3; 1161 uint32_t reserved_4; 1162 1163 uint32_t abort_context; 1164 uint32_t pad_1; 1165 1166 uint32_t abort_mfi_phys_addr_lo; 1167 uint32_t abort_mfi_phys_addr_hi; 1168 1169 uint32_t reserved_5[6]; 1170 }; 1171 1172 struct mrsas_smp_frame { 1173 uint8_t cmd; 1174 uint8_t reserved_1; 1175 uint8_t cmd_status; 1176 uint8_t connection_status; 1177 1178 uint8_t reserved_2[3]; 1179 uint8_t sge_count; 1180 1181 uint32_t context; 1182 uint8_t req_id; 1183 uint8_t msgvector; 1184 uint16_t pad_0; 1185 1186 uint16_t flags; 1187 uint16_t timeout; 1188 1189 uint32_t data_xfer_len; 1190 1191 uint64_t sas_addr; 1192 1193 union mrsas_sgl sgl[2]; 1194 }; 1195 1196 struct mrsas_stp_frame { 1197 uint8_t cmd; 1198 uint8_t reserved_1; 1199 uint8_t cmd_status; 1200 uint8_t connection_status; 1201 1202 uint8_t target_id; 1203 uint8_t reserved_2[2]; 1204 uint8_t sge_count; 1205 1206 uint32_t context; 1207 uint8_t req_id; 1208 uint8_t msgvector; 1209 uint16_t pad_0; 1210 1211 uint16_t flags; 1212 uint16_t timeout; 1213 1214 uint32_t data_xfer_len; 1215 1216 uint16_t fis[10]; 1217 uint32_t stp_flags; 1218 union mrsas_sgl sgl; 1219 }; 1220 1221 union mrsas_frame { 1222 struct mrsas_header hdr; 1223 struct mrsas_init_frame init; 1224 struct mrsas_io_frame io; 1225 struct mrsas_pthru_frame pthru; 1226 struct mrsas_dcmd_frame dcmd; 1227 struct mrsas_abort_frame abort; 1228 struct mrsas_smp_frame smp; 1229 struct mrsas_stp_frame stp; 1230 1231 uint8_t raw_bytes[64]; 1232 }; 1233 1234 typedef struct mrsas_pd_address { 1235 uint16_t device_id; 1236 uint16_t encl_id; 1237 1238 union { 1239 struct { 1240 uint8_t encl_index; 1241 uint8_t slot_number; 1242 } pd_address; 1243 struct { 1244 uint8_t encl_position; 1245 uint8_t encl_connector_index; 1246 } encl_address; 1247 }address; 1248 1249 uint8_t scsi_dev_type; 1250 1251 union { 1252 uint8_t port_bitmap; 1253 uint8_t port_numbers; 1254 } connected; 1255 1256 uint64_t sas_addr[2]; 1257 } mrsas_pd_address_t; 1258 1259 union mrsas_evt_class_locale { 1260 struct { 1261 uint16_t locale; 1262 uint8_t reserved; 1263 int8_t class; 1264 } members; 1265 1266 uint32_t word; 1267 }; 1268 1269 struct mrsas_evt_log_info { 1270 uint32_t newest_seq_num; 1271 uint32_t oldest_seq_num; 1272 uint32_t clear_seq_num; 1273 uint32_t shutdown_seq_num; 1274 uint32_t boot_seq_num; 1275 }; 1276 1277 struct mrsas_progress { 1278 uint16_t progress; 1279 uint16_t elapsed_seconds; 1280 }; 1281 1282 struct mrsas_evtarg_ld { 1283 uint16_t target_id; 1284 uint8_t ld_index; 1285 uint8_t reserved; 1286 }; 1287 1288 struct mrsas_evtarg_pd { 1289 uint16_t device_id; 1290 uint8_t encl_index; 1291 uint8_t slot_number; 1292 }; 1293 1294 struct mrsas_evt_detail { 1295 uint32_t seq_num; 1296 uint32_t time_stamp; 1297 uint32_t code; 1298 union mrsas_evt_class_locale cl; 1299 uint8_t arg_type; 1300 uint8_t reserved1[15]; 1301 1302 union { 1303 struct { 1304 struct mrsas_evtarg_pd pd; 1305 uint8_t cdb_length; 1306 uint8_t sense_length; 1307 uint8_t reserved[2]; 1308 uint8_t cdb[16]; 1309 uint8_t sense[64]; 1310 } cdbSense; 1311 1312 struct mrsas_evtarg_ld ld; 1313 1314 struct { 1315 struct mrsas_evtarg_ld ld; 1316 uint64_t count; 1317 } ld_count; 1318 1319 struct { 1320 uint64_t lba; 1321 struct mrsas_evtarg_ld ld; 1322 } ld_lba; 1323 1324 struct { 1325 struct mrsas_evtarg_ld ld; 1326 uint32_t prevOwner; 1327 uint32_t newOwner; 1328 } ld_owner; 1329 1330 struct { 1331 uint64_t ld_lba; 1332 uint64_t pd_lba; 1333 struct mrsas_evtarg_ld ld; 1334 struct mrsas_evtarg_pd pd; 1335 } ld_lba_pd_lba; 1336 1337 struct { 1338 struct mrsas_evtarg_ld ld; 1339 struct mrsas_progress prog; 1340 } ld_prog; 1341 1342 struct { 1343 struct mrsas_evtarg_ld ld; 1344 uint32_t prev_state; 1345 uint32_t new_state; 1346 } ld_state; 1347 1348 struct { 1349 uint64_t strip; 1350 struct mrsas_evtarg_ld ld; 1351 } ld_strip; 1352 1353 struct mrsas_evtarg_pd pd; 1354 1355 struct { 1356 struct mrsas_evtarg_pd pd; 1357 uint32_t err; 1358 } pd_err; 1359 1360 struct { 1361 uint64_t lba; 1362 struct mrsas_evtarg_pd pd; 1363 } pd_lba; 1364 1365 struct { 1366 uint64_t lba; 1367 struct mrsas_evtarg_pd pd; 1368 struct mrsas_evtarg_ld ld; 1369 } pd_lba_ld; 1370 1371 struct { 1372 struct mrsas_evtarg_pd pd; 1373 struct mrsas_progress prog; 1374 } pd_prog; 1375 1376 struct { 1377 struct mrsas_evtarg_pd pd; 1378 uint32_t prevState; 1379 uint32_t newState; 1380 } pd_state; 1381 1382 struct { 1383 uint16_t vendorId; 1384 uint16_t deviceId; 1385 uint16_t subVendorId; 1386 uint16_t subDeviceId; 1387 } pci; 1388 1389 uint32_t rate; 1390 char str[96]; 1391 1392 struct { 1393 uint32_t rtc; 1394 uint32_t elapsedSeconds; 1395 } time; 1396 1397 struct { 1398 uint32_t ecar; 1399 uint32_t elog; 1400 char str[64]; 1401 } ecc; 1402 1403 mrsas_pd_address_t pd_addr; 1404 1405 uint8_t b[96]; 1406 uint16_t s[48]; 1407 uint32_t w[24]; 1408 uint64_t d[12]; 1409 } args; 1410 1411 char description[128]; 1412 1413 }; 1414 1415 /* only 63 are usable by the application */ 1416 #define MAX_LOGICAL_DRIVES 64 1417 /* only 255 physical devices may be used */ 1418 #define MAX_PHYSICAL_DEVICES 256 1419 #define MAX_PD_PER_ENCLOSURE 64 1420 /* maximum disks per array */ 1421 #define MAX_ROW_SIZE 32 1422 /* maximum spans per logical drive */ 1423 #define MAX_SPAN_DEPTH 8 1424 /* maximum number of arrays a hot spare may be dedicated to */ 1425 #define MAX_ARRAYS_DEDICATED 16 1426 /* maximum number of arrays which may exist */ 1427 #define MAX_ARRAYS 128 1428 /* maximum number of foreign configs that may ha managed at once */ 1429 #define MAX_FOREIGN_CONFIGS 8 1430 /* maximum spares (global and dedicated combined) */ 1431 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES 1432 /* maximum possible Target IDs (i.e. 0 to 63) */ 1433 #define MAX_TARGET_ID 63 1434 /* maximum number of supported enclosures */ 1435 #define MAX_ENCLOSURES 32 1436 /* maximum number of PHYs per controller */ 1437 #define MAX_PHYS_PER_CONTROLLER 16 1438 /* maximum number of LDs per array (due to DDF limitations) */ 1439 #define MAX_LDS_PER_ARRAY 16 1440 1441 /* 1442 * ----------------------------------------------------------------------------- 1443 * ----------------------------------------------------------------------------- 1444 * 1445 * Logical Drive commands 1446 * 1447 * ----------------------------------------------------------------------------- 1448 * ----------------------------------------------------------------------------- 1449 */ 1450 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */ 1451 1452 /* 1453 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST 1454 * dcmd.mbox - reserved 1455 * dcmd.sge IN - ptr to returned MR_LD_LIST structure 1456 * Desc: Return the logical drive list structure 1457 * Status: No error 1458 */ 1459 1460 /* 1461 * defines the logical drive reference structure 1462 */ 1463 typedef union _MR_LD_REF { /* LD reference structure */ 1464 struct { 1465 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */ 1466 uint8_t reserved; /* reserved for in line with MR_PD_REF */ 1467 uint16_t seqNum; /* Sequence Number */ 1468 } ld_ref; 1469 uint32_t ref; /* shorthand reference to full 32-bits */ 1470 } MR_LD_REF; /* 4 bytes */ 1471 1472 /* 1473 * defines the logical drive list structure 1474 */ 1475 typedef struct _MR_LD_LIST { 1476 uint32_t ldCount; /* number of LDs */ 1477 uint32_t reserved; /* pad to 8-byte boundary */ 1478 struct { 1479 MR_LD_REF ref; /* LD reference */ 1480 uint8_t state; /* current LD state (MR_LD_STATE) */ 1481 uint8_t reserved[3]; /* pad to 8-byte boundary */ 1482 uint64_t size; /* LD size */ 1483 } ldList[MAX_LOGICAL_DRIVES]; 1484 } MR_LD_LIST; 1485 1486 struct mrsas_drv_ver { 1487 uint8_t signature[12]; 1488 uint8_t os_name[16]; 1489 uint8_t os_ver[12]; 1490 uint8_t drv_name[20]; 1491 uint8_t drv_ver[32]; 1492 uint8_t drv_rel_date[20]; 1493 }; 1494 1495 #define PCI_TYPE0_ADDRESSES 6 1496 #define PCI_TYPE1_ADDRESSES 2 1497 #define PCI_TYPE2_ADDRESSES 5 1498 1499 struct mrsas_pci_common_header { 1500 uint16_t vendorID; /* (ro) */ 1501 uint16_t deviceID; /* (ro) */ 1502 uint16_t command; /* Device control */ 1503 uint16_t status; 1504 uint8_t revisionID; /* (ro) */ 1505 uint8_t progIf; /* (ro) */ 1506 uint8_t subClass; /* (ro) */ 1507 uint8_t baseClass; /* (ro) */ 1508 uint8_t cacheLineSize; /* (ro+) */ 1509 uint8_t latencyTimer; /* (ro+) */ 1510 uint8_t headerType; /* (ro) */ 1511 uint8_t bist; /* Built in self test */ 1512 1513 union { 1514 struct { 1515 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 1516 uint32_t cis; 1517 uint16_t subVendorID; 1518 uint16_t subSystemID; 1519 uint32_t romBaseAddress; 1520 uint8_t capabilitiesPtr; 1521 uint8_t reserved1[3]; 1522 uint32_t reserved2; 1523 uint8_t interruptLine; 1524 uint8_t interruptPin; /* (ro) */ 1525 uint8_t minimumGrant; /* (ro) */ 1526 uint8_t maximumLatency; /* (ro) */ 1527 } type_0; 1528 1529 struct { 1530 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 1531 uint8_t primaryBus; 1532 uint8_t secondaryBus; 1533 uint8_t subordinateBus; 1534 uint8_t secondaryLatency; 1535 uint8_t ioBase; 1536 uint8_t ioLimit; 1537 uint16_t secondaryStatus; 1538 uint16_t memoryBase; 1539 uint16_t memoryLimit; 1540 uint16_t prefetchBase; 1541 uint16_t prefetchLimit; 1542 uint32_t prefetchBaseUpper32; 1543 uint32_t prefetchLimitUpper32; 1544 uint16_t ioBaseUpper16; 1545 uint16_t ioLimitUpper16; 1546 uint8_t capabilitiesPtr; 1547 uint8_t reserved1[3]; 1548 uint32_t romBaseAddress; 1549 uint8_t interruptLine; 1550 uint8_t interruptPin; 1551 uint16_t bridgeControl; 1552 } type_1; 1553 1554 struct { 1555 uint32_t socketRegistersBaseAddress; 1556 uint8_t capabilitiesPtr; 1557 uint8_t reserved; 1558 uint16_t secondaryStatus; 1559 uint8_t primaryBus; 1560 uint8_t secondaryBus; 1561 uint8_t subordinateBus; 1562 uint8_t secondaryLatency; 1563 struct { 1564 uint32_t base; 1565 uint32_t limit; 1566 } range[PCI_TYPE2_ADDRESSES-1]; 1567 uint8_t interruptLine; 1568 uint8_t interruptPin; 1569 uint16_t bridgeControl; 1570 } type_2; 1571 } header; 1572 }; 1573 1574 struct mrsas_pci_link_capability { 1575 union { 1576 struct { 1577 uint32_t linkSpeed :4; 1578 uint32_t linkWidth :6; 1579 uint32_t aspmSupport :2; 1580 uint32_t losExitLatency :3; 1581 uint32_t l1ExitLatency :3; 1582 uint32_t rsvdp :6; 1583 uint32_t portNumber :8; 1584 } bits; 1585 1586 uint32_t asUlong; 1587 } cap; 1588 1589 }; 1590 1591 struct mrsas_pci_link_status_capability { 1592 union { 1593 struct { 1594 uint16_t linkSpeed :4; 1595 uint16_t negotiatedLinkWidth :6; 1596 uint16_t linkTrainingError :1; 1597 uint16_t linkTraning :1; 1598 uint16_t slotClockConfig :1; 1599 uint16_t rsvdZ :3; 1600 } bits; 1601 1602 uint16_t asUshort; 1603 } stat_cap; 1604 1605 uint16_t reserved; 1606 1607 }; 1608 1609 struct mrsas_pci_capabilities { 1610 struct mrsas_pci_link_capability linkCapability; 1611 struct mrsas_pci_link_status_capability linkStatusCapability; 1612 }; 1613 1614 struct mrsas_pci_information 1615 { 1616 uint32_t busNumber; 1617 uint8_t deviceNumber; 1618 uint8_t functionNumber; 1619 uint8_t interruptVector; 1620 uint8_t reserved; 1621 struct mrsas_pci_common_header pciHeaderInfo; 1622 struct mrsas_pci_capabilities capability; 1623 uint8_t reserved2[32]; 1624 }; 1625 1626 struct mrsas_ioctl { 1627 uint16_t version; 1628 uint16_t controller_id; 1629 uint8_t signature[8]; 1630 uint32_t reserved_1; 1631 uint32_t control_code; 1632 uint32_t reserved_2[2]; 1633 uint8_t frame[64]; 1634 union mrsas_sgl_frame sgl_frame; 1635 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH]; 1636 uint8_t data[1]; 1637 }; 1638 1639 struct mrsas_aen { 1640 uint16_t host_no; 1641 uint16_t cmd_status; 1642 uint32_t seq_num; 1643 uint32_t class_locale_word; 1644 }; 1645 #pragma pack() 1646 1647 #ifndef DDI_VENDOR_LSI 1648 #define DDI_VENDOR_LSI "LSI" 1649 #endif /* DDI_VENDOR_LSI */ 1650 1651 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 1652 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t); 1653 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t); 1654 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t); 1655 static int mrsas_open(dev_t *, int, int, cred_t *); 1656 static int mrsas_close(dev_t, int, int, cred_t *); 1657 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 1658 1659 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *, 1660 scsi_hba_tran_t *, struct scsi_device *); 1661 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register 1662 struct scsi_pkt *, struct buf *, int, int, int, int, 1663 int (*)(), caddr_t); 1664 static int mrsas_tran_start(struct scsi_address *, 1665 register struct scsi_pkt *); 1666 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *); 1667 static int mrsas_tran_reset(struct scsi_address *, int); 1668 static int mrsas_tran_getcap(struct scsi_address *, char *, int); 1669 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int); 1670 static void mrsas_tran_destroy_pkt(struct scsi_address *, 1671 struct scsi_pkt *); 1672 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *); 1673 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *); 1674 static uint_t mrsas_isr(); 1675 static uint_t mrsas_softintr(); 1676 1677 static int init_mfi(struct mrsas_instance *); 1678 static int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t); 1679 static int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *, 1680 uchar_t); 1681 static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *); 1682 static void return_mfi_pkt(struct mrsas_instance *, 1683 struct mrsas_cmd *); 1684 1685 static void free_space_for_mfi(struct mrsas_instance *); 1686 static void free_additional_dma_buffer(struct mrsas_instance *); 1687 static int alloc_additional_dma_buffer(struct mrsas_instance *); 1688 static int read_fw_status_reg_ppc(struct mrsas_instance *); 1689 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *); 1690 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *, 1691 struct mrsas_cmd *); 1692 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *, 1693 struct mrsas_cmd *); 1694 static void enable_intr_ppc(struct mrsas_instance *); 1695 static void disable_intr_ppc(struct mrsas_instance *); 1696 static int intr_ack_ppc(struct mrsas_instance *); 1697 static int mfi_state_transition_to_ready(struct mrsas_instance *); 1698 static void destroy_mfi_frame_pool(struct mrsas_instance *); 1699 static int create_mfi_frame_pool(struct mrsas_instance *); 1700 static int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *, 1701 struct buf *, int, int (*)()); 1702 static int mrsas_dma_move(struct mrsas_instance *, 1703 struct scsi_pkt *, struct buf *); 1704 static void flush_cache(struct mrsas_instance *instance); 1705 static void display_scsi_inquiry(caddr_t); 1706 static int start_mfi_aen(struct mrsas_instance *instance); 1707 static int handle_drv_ioctl(struct mrsas_instance *instance, 1708 struct mrsas_ioctl *ioctl, int mode); 1709 static int handle_mfi_ioctl(struct mrsas_instance *instance, 1710 struct mrsas_ioctl *ioctl, int mode); 1711 static int handle_mfi_aen(struct mrsas_instance *instance, 1712 struct mrsas_aen *aen); 1713 static void fill_up_drv_ver(struct mrsas_drv_ver *dv); 1714 static struct mrsas_cmd *build_cmd(struct mrsas_instance *instance, 1715 struct scsi_address *ap, struct scsi_pkt *pkt, 1716 uchar_t *cmd_done); 1717 static int register_mfi_aen(struct mrsas_instance *instance, 1718 uint32_t seq_num, uint32_t class_locale_word); 1719 static int issue_mfi_pthru(struct mrsas_instance *instance, struct 1720 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1721 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct 1722 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1723 static int issue_mfi_smp(struct mrsas_instance *instance, struct 1724 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1725 static int issue_mfi_stp(struct mrsas_instance *instance, struct 1726 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1727 static int abort_aen_cmd(struct mrsas_instance *instance, 1728 struct mrsas_cmd *cmd_to_abort); 1729 1730 static int mrsas_common_check(struct mrsas_instance *instance, 1731 struct mrsas_cmd *cmd); 1732 static void mrsas_fm_init(struct mrsas_instance *instance); 1733 static void mrsas_fm_fini(struct mrsas_instance *instance); 1734 static int mrsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 1735 const void *); 1736 static void mrsas_fm_ereport(struct mrsas_instance *instance, 1737 char *detail); 1738 static int mrsas_check_dma_handle(ddi_dma_handle_t handle); 1739 static int mrsas_check_acc_handle(ddi_acc_handle_t handle); 1740 1741 static void mrsas_rem_intrs(struct mrsas_instance *instance); 1742 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type); 1743 1744 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *, 1745 scsi_hba_tran_t *, struct scsi_device *); 1746 static int mrsas_tran_bus_config(dev_info_t *, uint_t, 1747 ddi_bus_config_op_t, void *, dev_info_t **); 1748 static int mrsas_parse_devname(char *, int *, int *); 1749 static int mrsas_config_all_devices(struct mrsas_instance *); 1750 static int mrsas_config_scsi_device(struct mrsas_instance *, 1751 struct scsi_device *, dev_info_t **); 1752 static int mrsas_config_ld(struct mrsas_instance *, uint16_t, 1753 uint8_t, dev_info_t **); 1754 static dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, 1755 uint8_t); 1756 static int mrsas_name_node(dev_info_t *, char *, int); 1757 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *); 1758 static int mrsas_service_evt(struct mrsas_instance *, int, int, int, 1759 uint64_t); 1760 static int mrsas_mode_sense_build(struct scsi_pkt *); 1761 1762 #ifdef __cplusplus 1763 } 1764 #endif 1765 1766 #endif /* _MR_SAS_H_ */ 1767