1 /* 2 * mr_sas.h: header for mr_sas 3 * 4 * Solaris MegaRAID driver for SAS2.0 controllers 5 * Copyright (c) 2008-2009, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the author nor the names of its contributors may be 19 * used to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 * DAMAGE. 34 */ 35 36 /* 37 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 38 * Use is subject to license terms. 39 */ 40 #ifndef _MR_SAS_H_ 41 #define _MR_SAS_H_ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 #include <sys/scsi/scsi.h> 48 #include "mr_sas_list.h" 49 50 /* 51 * MegaRAID SAS2.0 Driver meta data 52 */ 53 #define MRSAS_VERSION "LSIv2.1" 54 #define MRSAS_RELDATE "May 11, 2009" 55 56 #define MRSAS_TRUE 1 57 #define MRSAS_FALSE 0 58 59 /* 60 * MegaRAID SAS2.0 device id conversion definitions. 61 */ 62 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT) 63 64 /* 65 * MegaRAID SAS2.0 supported controllers 66 */ 67 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078 68 #define PCI_DEVICE_ID_LSI_2108V 0x0079 69 70 /* 71 * Register Index for 2108 Controllers. 72 */ 73 #define REGISTER_SET_IO_2108 (2) 74 75 #define MRSAS_MAX_SGE_CNT 0x50 76 77 #define MRSAS_IOCTL_DRIVER 0x12341234 78 #define MRSAS_IOCTL_FIRMWARE 0x12345678 79 #define MRSAS_IOCTL_AEN 0x87654321 80 81 #define MRSAS_1_SECOND 1000000 82 83 /* Dynamic Enumeration Flags */ 84 #define MRSAS_PD_LUN 1 85 #define MRSAS_LD_LUN 0 86 #define MRSAS_PD_TGT_MAX 255 87 #define MRSAS_GET_PD_MAX(s) ((s)->mr_pd_max) 88 #define WWN_STRLEN 17 89 90 /* 91 * ===================================== 92 * MegaRAID SAS2.0 MFI firmware definitions 93 * ===================================== 94 */ 95 /* 96 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for 97 * protocol between the software and firmware. Commands are issued using 98 * "message frames" 99 */ 100 101 /* 102 * FW posts its state in upper 4 bits of outbound_msg_0 register 103 */ 104 #define MFI_STATE_SHIFT 28 105 #define MFI_STATE_MASK ((uint32_t)0xF<<MFI_STATE_SHIFT) 106 #define MFI_STATE_UNDEFINED ((uint32_t)0x0<<MFI_STATE_SHIFT) 107 #define MFI_STATE_BB_INIT ((uint32_t)0x1<<MFI_STATE_SHIFT) 108 #define MFI_STATE_FW_INIT ((uint32_t)0x4<<MFI_STATE_SHIFT) 109 #define MFI_STATE_WAIT_HANDSHAKE ((uint32_t)0x6<<MFI_STATE_SHIFT) 110 #define MFI_STATE_FW_INIT_2 ((uint32_t)0x7<<MFI_STATE_SHIFT) 111 #define MFI_STATE_DEVICE_SCAN ((uint32_t)0x8<<MFI_STATE_SHIFT) 112 #define MFI_STATE_BOOT_MESSAGE_PENDING ((uint32_t)0x9<<MFI_STATE_SHIFT) 113 #define MFI_STATE_FLUSH_CACHE ((uint32_t)0xA<<MFI_STATE_SHIFT) 114 #define MFI_STATE_READY ((uint32_t)0xB<<MFI_STATE_SHIFT) 115 #define MFI_STATE_OPERATIONAL ((uint32_t)0xC<<MFI_STATE_SHIFT) 116 #define MFI_STATE_FAULT ((uint32_t)0xF<<MFI_STATE_SHIFT) 117 118 #define MRMFI_FRAME_SIZE 64 119 120 /* 121 * During FW init, clear pending cmds & reset state using inbound_msg_0 122 * 123 * ABORT : Abort all pending cmds 124 * READY : Move from OPERATIONAL to READY state; discard queue info 125 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 126 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 127 */ 128 #define MFI_INIT_ABORT 0x00000001 129 #define MFI_INIT_READY 0x00000002 130 #define MFI_INIT_MFIMODE 0x00000004 131 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 132 #define MFI_INIT_HOTPLUG 0x00000010 133 #define MFI_STOP_ADP 0x00000020 134 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT 135 136 /* 137 * MFI frame flags 138 */ 139 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 140 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 141 #define MFI_FRAME_SGL32 0x0000 142 #define MFI_FRAME_SGL64 0x0002 143 #define MFI_FRAME_SENSE32 0x0000 144 #define MFI_FRAME_SENSE64 0x0004 145 #define MFI_FRAME_DIR_NONE 0x0000 146 #define MFI_FRAME_DIR_WRITE 0x0008 147 #define MFI_FRAME_DIR_READ 0x0010 148 #define MFI_FRAME_DIR_BOTH 0x0018 149 150 /* 151 * Definition for cmd_status 152 */ 153 #define MFI_CMD_STATUS_POLL_MODE 0xFF 154 #define MFI_CMD_STATUS_SYNC_MODE 0xFF 155 156 /* 157 * MFI command opcodes 158 */ 159 #define MFI_CMD_OP_INIT 0x00 160 #define MFI_CMD_OP_LD_READ 0x01 161 #define MFI_CMD_OP_LD_WRITE 0x02 162 #define MFI_CMD_OP_LD_SCSI 0x03 163 #define MFI_CMD_OP_PD_SCSI 0x04 164 #define MFI_CMD_OP_DCMD 0x05 165 #define MFI_CMD_OP_ABORT 0x06 166 #define MFI_CMD_OP_SMP 0x07 167 #define MFI_CMD_OP_STP 0x08 168 169 #define MR_DCMD_CTRL_GET_INFO 0x01010000 170 171 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 172 #define MR_FLUSH_CTRL_CACHE 0x01 173 #define MR_FLUSH_DISK_CACHE 0x02 174 175 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 176 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01 177 178 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 179 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 180 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 181 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 182 #define MR_DCMD_PD_GET_INFO 0x02020000 183 184 /* 185 * Solaris Specific MAX values 186 */ 187 #define MAX_SGL 24 188 /* 189 * MFI command completion codes 190 */ 191 enum MFI_STAT { 192 MFI_STAT_OK = 0x00, 193 MFI_STAT_INVALID_CMD = 0x01, 194 MFI_STAT_INVALID_DCMD = 0x02, 195 MFI_STAT_INVALID_PARAMETER = 0x03, 196 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 197 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 198 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 199 MFI_STAT_APP_IN_USE = 0x07, 200 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 201 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 202 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 203 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 204 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 205 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 206 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 207 MFI_STAT_FLASH_BUSY = 0x0f, 208 MFI_STAT_FLASH_ERROR = 0x10, 209 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 210 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 211 MFI_STAT_FLASH_NOT_OPEN = 0x13, 212 MFI_STAT_FLASH_NOT_STARTED = 0x14, 213 MFI_STAT_FLUSH_FAILED = 0x15, 214 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 215 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 216 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 217 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 218 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 219 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 220 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 221 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 222 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 223 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 224 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 225 MFI_STAT_MFC_HW_ERROR = 0x21, 226 MFI_STAT_NO_HW_PRESENT = 0x22, 227 MFI_STAT_NOT_FOUND = 0x23, 228 MFI_STAT_NOT_IN_ENCL = 0x24, 229 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 230 MFI_STAT_PD_TYPE_WRONG = 0x26, 231 MFI_STAT_PR_DISABLED = 0x27, 232 MFI_STAT_ROW_INDEX_INVALID = 0x28, 233 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 234 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 235 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 236 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 237 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 238 MFI_STAT_SCSI_IO_FAILED = 0x2e, 239 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 240 MFI_STAT_SHUTDOWN_FAILED = 0x30, 241 MFI_STAT_TIME_NOT_SET = 0x31, 242 MFI_STAT_WRONG_STATE = 0x32, 243 MFI_STAT_LD_OFFLINE = 0x33, 244 /* UNUSED: 0x34 to 0xfe */ 245 MFI_STAT_INVALID_STATUS = 0xFF 246 }; 247 248 enum MR_EVT_CLASS { 249 MR_EVT_CLASS_DEBUG = -2, 250 MR_EVT_CLASS_PROGRESS = -1, 251 MR_EVT_CLASS_INFO = 0, 252 MR_EVT_CLASS_WARNING = 1, 253 MR_EVT_CLASS_CRITICAL = 2, 254 MR_EVT_CLASS_FATAL = 3, 255 MR_EVT_CLASS_DEAD = 4 256 }; 257 258 enum MR_EVT_LOCALE { 259 MR_EVT_LOCALE_LD = 0x0001, 260 MR_EVT_LOCALE_PD = 0x0002, 261 MR_EVT_LOCALE_ENCL = 0x0004, 262 MR_EVT_LOCALE_BBU = 0x0008, 263 MR_EVT_LOCALE_SAS = 0x0010, 264 MR_EVT_LOCALE_CTRL = 0x0020, 265 MR_EVT_LOCALE_CONFIG = 0x0040, 266 MR_EVT_LOCALE_CLUSTER = 0x0080, 267 MR_EVT_LOCALE_ALL = 0xffff 268 }; 269 270 #define MR_EVT_CFG_CLEARED 0x0004 271 #define MR_EVT_LD_CREATED 0x008a 272 #define MR_EVT_LD_DELETED 0x008b 273 #define MR_EVT_PD_REMOVED_EXT 0x00f8 274 #define MR_EVT_PD_INSERTED_EXT 0x00f7 275 276 enum LD_STATE { 277 LD_OFFLINE = 0, 278 LD_PARTIALLY_DEGRADED = 1, 279 LD_DEGRADED = 2, 280 LD_OPTIMAL = 3, 281 LD_INVALID = 0xFF 282 }; 283 284 enum MRSAS_EVT { 285 MRSAS_EVT_CONFIG_TGT = 0, 286 MRSAS_EVT_UNCONFIG_TGT = 1, 287 MRSAS_EVT_UNCONFIG_SMP = 2 288 }; 289 290 #define DMA_OBJ_ALLOCATED 1 291 #define DMA_OBJ_REALLOCATED 2 292 #define DMA_OBJ_FREED 3 293 294 /* 295 * dma_obj_t - Our DMA object 296 * @param buffer : kernel virtual address 297 * @param size : size of the data to be allocated 298 * @param acc_handle : access handle 299 * @param dma_handle : dma handle 300 * @param dma_cookie : scatter-gather list 301 * @param dma_attr : dma attributes for this buffer 302 * Our DMA object. The caller must initialize the size and dma attributes 303 * (dma_attr) fields before allocating the resources. 304 */ 305 typedef struct { 306 caddr_t buffer; 307 uint32_t size; 308 ddi_acc_handle_t acc_handle; 309 ddi_dma_handle_t dma_handle; 310 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT]; 311 ddi_dma_attr_t dma_attr; 312 uint8_t status; 313 uint8_t reserved[3]; 314 } dma_obj_t; 315 316 struct mrsas_eventinfo { 317 struct mrsas_instance *instance; 318 int tgt; 319 int lun; 320 int event; 321 }; 322 323 struct mrsas_ld { 324 dev_info_t *dip; 325 uint8_t lun_type; 326 uint8_t reserved[3]; 327 }; 328 329 struct mrsas_pd { 330 dev_info_t *dip; 331 uint8_t lun_type; 332 uint8_t dev_id; 333 uint8_t flags; 334 uint8_t reserved; 335 }; 336 337 struct mrsas_pd_info { 338 uint16_t deviceId; 339 uint16_t seqNum; 340 uint8_t inquiryData[96]; 341 uint8_t vpdPage83[64]; 342 uint8_t notSupported; 343 uint8_t scsiDevType; 344 uint8_t a; 345 uint8_t device_speed; 346 uint32_t mediaerrcnt; 347 uint32_t other; 348 uint32_t pred; 349 uint32_t lastpred; 350 uint16_t fwState; 351 uint8_t disabled; 352 uint8_t linkspwwd; 353 uint32_t ddfType; 354 struct { 355 uint8_t count; 356 uint8_t isPathBroken; 357 uint8_t connectorIndex[2]; 358 uint8_t reserved[4]; 359 uint64_t sasAddr[2]; 360 uint8_t reserved2[16]; 361 } pathInfo; 362 }; 363 364 typedef struct mrsas_instance { 365 uint32_t *producer; 366 uint32_t *consumer; 367 368 uint32_t *reply_queue; 369 dma_obj_t mfi_internal_dma_obj; 370 371 uint8_t init_id; 372 uint8_t reserved[3]; 373 374 uint16_t max_num_sge; 375 uint16_t max_fw_cmds; 376 uint32_t max_sectors_per_req; 377 378 struct mrsas_cmd **cmd_list; 379 380 mlist_t cmd_pool_list; 381 kmutex_t cmd_pool_mtx; 382 383 mlist_t cmd_pend_list; 384 kmutex_t cmd_pend_mtx; 385 386 dma_obj_t mfi_evt_detail_obj; 387 struct mrsas_cmd *aen_cmd; 388 389 uint32_t aen_seq_num; 390 uint32_t aen_class_locale_word; 391 392 scsi_hba_tran_t *tran; 393 394 kcondvar_t int_cmd_cv; 395 kmutex_t int_cmd_mtx; 396 397 kcondvar_t aen_cmd_cv; 398 kmutex_t aen_cmd_mtx; 399 400 kcondvar_t abort_cmd_cv; 401 kmutex_t abort_cmd_mtx; 402 403 dev_info_t *dip; 404 ddi_acc_handle_t pci_handle; 405 406 timeout_id_t timeout_id; 407 uint32_t unique_id; 408 uint16_t fw_outstanding; 409 caddr_t regmap; 410 ddi_acc_handle_t regmap_handle; 411 uint8_t isr_level; 412 ddi_iblock_cookie_t iblock_cookie; 413 ddi_iblock_cookie_t soft_iblock_cookie; 414 ddi_softintr_t soft_intr_id; 415 uint8_t softint_running; 416 kmutex_t completed_pool_mtx; 417 mlist_t completed_pool_list; 418 419 caddr_t internal_buf; 420 uint32_t internal_buf_dmac_add; 421 uint32_t internal_buf_size; 422 423 uint16_t vendor_id; 424 uint16_t device_id; 425 uint16_t subsysvid; 426 uint16_t subsysid; 427 int instance; 428 int baseaddress; 429 char iocnode[16]; 430 431 int fm_capabilities; 432 433 struct mrsas_func_ptr *func_ptr; 434 /* MSI interrupts specific */ 435 ddi_intr_handle_t *intr_htable; 436 int intr_type; 437 int intr_cnt; 438 size_t intr_size; 439 uint_t intr_pri; 440 int intr_cap; 441 442 ddi_taskq_t *taskq; 443 struct mrsas_ld *mr_ld_list; 444 } mrsas_t; 445 446 struct mrsas_func_ptr { 447 int (*read_fw_status_reg)(struct mrsas_instance *); 448 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *); 449 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *, 450 struct mrsas_cmd *); 451 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *, 452 struct mrsas_cmd *); 453 void (*enable_intr)(struct mrsas_instance *); 454 void (*disable_intr)(struct mrsas_instance *); 455 int (*intr_ack)(struct mrsas_instance *); 456 }; 457 458 /* 459 * ### Helper routines ### 460 */ 461 462 /* 463 * con_log() - console log routine 464 * @param level : indicates the severity of the message. 465 * @fparam mt : format string 466 * 467 * con_log displays the error messages on the console based on the current 468 * debug level. Also it attaches the appropriate kernel severity level with 469 * the message. 470 * 471 * 472 * console messages debug levels 473 */ 474 #define CL_NONE 0 /* No debug information */ 475 #define CL_ANN 1 /* print unconditionally, announcements */ 476 #define CL_ANN1 2 /* No o/p */ 477 #define CL_DLEVEL1 3 /* debug level 1, informative */ 478 #define CL_DLEVEL2 4 /* debug level 2, verbose */ 479 #define CL_DLEVEL3 5 /* debug level 3, very verbose */ 480 481 #ifdef __SUNPRO_C 482 #define __func__ "" 483 #endif 484 485 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; } 486 487 /* 488 * ### SCSA definitions ### 489 */ 490 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target) 491 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun) 492 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran) 493 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 494 495 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private) 496 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap)) 497 498 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private) 499 #define CMD2PKT(sp) ((sp)->cmd_pkt) 500 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request)) 501 502 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address) 503 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran) 504 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd))) 505 506 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */ 507 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */ 508 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */ 509 510 /* 511 * ### Data structures for ioctl inteface and internal commands ### 512 */ 513 514 /* 515 * Data direction flags 516 */ 517 #define UIOC_RD 0x00001 518 #define UIOC_WR 0x00002 519 520 #define SCP2HOST(scp) (scp)->device->host /* to host */ 521 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */ 522 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */ 523 #define SCP2TARGET(scp) (scp)->device->id /* to target */ 524 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */ 525 526 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0]) 527 #define SCP2ADAPTER(scp) \ 528 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp)) 529 530 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \ 531 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0 532 #define MRDRV_IS_LOGICAL(ap) \ 533 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0 534 #define MAP_DEVICE_ID(instance, ap) \ 535 (ap->a_target) 536 537 #define HIGH_LEVEL_INTR 1 538 #define NORMAL_LEVEL_INTR 0 539 540 /* 541 * scsa_cmd - Per-command mr private data 542 * @param cmd_dmahandle : dma handle 543 * @param cmd_dmacookies : current dma cookies 544 * @param cmd_pkt : scsi_pkt reference 545 * @param cmd_dmacount : dma count 546 * @param cmd_cookie : next cookie 547 * @param cmd_ncookies : cookies per window 548 * @param cmd_cookiecnt : cookies per sub-win 549 * @param cmd_nwin : number of dma windows 550 * @param cmd_curwin : current dma window 551 * @param cmd_dma_offset : current window offset 552 * @param cmd_dma_len : current window length 553 * @param cmd_flags : private flags 554 * @param cmd_cdblen : length of cdb 555 * @param cmd_scblen : length of scb 556 * @param cmd_buf : command buffer 557 * @param channel : channel for scsi sub-system 558 * @param target : target for scsi sub-system 559 * @param lun : LUN for scsi sub-system 560 * 561 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E) 562 * - Pointed to by pkt_ha_private field in scsi_pkt 563 */ 564 struct scsa_cmd { 565 ddi_dma_handle_t cmd_dmahandle; 566 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT]; 567 struct scsi_pkt *cmd_pkt; 568 ulong_t cmd_dmacount; 569 uint_t cmd_cookie; 570 uint_t cmd_ncookies; 571 uint_t cmd_cookiecnt; 572 uint_t cmd_nwin; 573 uint_t cmd_curwin; 574 off_t cmd_dma_offset; 575 ulong_t cmd_dma_len; 576 ulong_t cmd_flags; 577 uint_t cmd_cdblen; 578 uint_t cmd_scblen; 579 struct buf *cmd_buf; 580 ushort_t device_id; 581 uchar_t islogical; 582 uchar_t lun; 583 struct mrsas_device *mrsas_dev; 584 }; 585 586 587 struct mrsas_cmd { 588 union mrsas_frame *frame; 589 uint32_t frame_phys_addr; 590 uint8_t *sense; 591 uint32_t sense_phys_addr; 592 dma_obj_t frame_dma_obj; 593 uint8_t frame_dma_obj_status; 594 595 uint32_t index; 596 uint8_t sync_cmd; 597 uint8_t cmd_status; 598 uint16_t abort_aen; 599 mlist_t list; 600 uint32_t frame_count; 601 struct scsa_cmd *cmd; 602 struct scsi_pkt *pkt; 603 }; 604 605 #define MAX_MGMT_ADAPTERS 1024 606 #define IOC_SIGNATURE "MR-SAS" 607 608 #define IOC_CMD_FIRMWARE 0x0 609 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000 610 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100 611 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200 612 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300 613 614 615 #define MRSAS_MAX_SENSE_LENGTH 32 616 617 struct mrsas_mgmt_info { 618 619 uint16_t count; 620 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS]; 621 uint16_t map[MAX_MGMT_ADAPTERS]; 622 int max_index; 623 }; 624 625 #pragma pack(1) 626 627 /* 628 * SAS controller properties 629 */ 630 struct mrsas_ctrl_prop { 631 uint16_t seq_num; 632 uint16_t pred_fail_poll_interval; 633 uint16_t intr_throttle_count; 634 uint16_t intr_throttle_timeouts; 635 636 uint8_t rebuild_rate; 637 uint8_t patrol_read_rate; 638 uint8_t bgi_rate; 639 uint8_t cc_rate; 640 uint8_t recon_rate; 641 642 uint8_t cache_flush_interval; 643 644 uint8_t spinup_drv_count; 645 uint8_t spinup_delay; 646 647 uint8_t cluster_enable; 648 uint8_t coercion_mode; 649 uint8_t disk_write_cache_disable; 650 uint8_t alarm_enable; 651 652 uint8_t reserved[44]; 653 }; 654 655 /* 656 * SAS controller information 657 */ 658 struct mrsas_ctrl_info { 659 /* PCI device information */ 660 struct { 661 uint16_t vendor_id; 662 uint16_t device_id; 663 uint16_t sub_vendor_id; 664 uint16_t sub_device_id; 665 uint8_t reserved[24]; 666 } pci; 667 668 /* Host interface information */ 669 struct { 670 uint8_t PCIX : 1; 671 uint8_t PCIE : 1; 672 uint8_t iSCSI : 1; 673 uint8_t SAS_3G : 1; 674 uint8_t reserved_0 : 4; 675 uint8_t reserved_1[6]; 676 uint8_t port_count; 677 uint64_t port_addr[8]; 678 } host_interface; 679 680 /* Device (backend) interface information */ 681 struct { 682 uint8_t SPI : 1; 683 uint8_t SAS_3G : 1; 684 uint8_t SATA_1_5G : 1; 685 uint8_t SATA_3G : 1; 686 uint8_t reserved_0 : 4; 687 uint8_t reserved_1[6]; 688 uint8_t port_count; 689 uint64_t port_addr[8]; 690 } device_interface; 691 692 /* List of components residing in flash. All str are null terminated */ 693 uint32_t image_check_word; 694 uint32_t image_component_count; 695 696 struct { 697 char name[8]; 698 char version[32]; 699 char build_date[16]; 700 char built_time[16]; 701 } image_component[8]; 702 703 /* 704 * List of flash components that have been flashed on the card, but 705 * are not in use, pending reset of the adapter. This list will be 706 * empty if a flash operation has not occurred. All stings are null 707 * terminated 708 */ 709 uint32_t pending_image_component_count; 710 711 struct { 712 char name[8]; 713 char version[32]; 714 char build_date[16]; 715 char build_time[16]; 716 } pending_image_component[8]; 717 718 uint8_t max_arms; 719 uint8_t max_spans; 720 uint8_t max_arrays; 721 uint8_t max_lds; 722 723 char product_name[80]; 724 char serial_no[32]; 725 726 /* 727 * Other physical/controller/operation information. Indicates the 728 * presence of the hardware 729 */ 730 struct { 731 uint32_t bbu : 1; 732 uint32_t alarm : 1; 733 uint32_t nvram : 1; 734 uint32_t uart : 1; 735 uint32_t reserved : 28; 736 } hw_present; 737 738 uint32_t current_fw_time; 739 740 /* Maximum data transfer sizes */ 741 uint16_t max_concurrent_cmds; 742 uint16_t max_sge_count; 743 uint32_t max_request_size; 744 745 /* Logical and physical device counts */ 746 uint16_t ld_present_count; 747 uint16_t ld_degraded_count; 748 uint16_t ld_offline_count; 749 750 uint16_t pd_present_count; 751 uint16_t pd_disk_present_count; 752 uint16_t pd_disk_pred_failure_count; 753 uint16_t pd_disk_failed_count; 754 755 /* Memory size information */ 756 uint16_t nvram_size; 757 uint16_t memory_size; 758 uint16_t flash_size; 759 760 /* Error counters */ 761 uint16_t mem_correctable_error_count; 762 uint16_t mem_uncorrectable_error_count; 763 764 /* Cluster information */ 765 uint8_t cluster_permitted; 766 uint8_t cluster_active; 767 uint8_t reserved_1[2]; 768 769 /* Controller capabilities structures */ 770 struct { 771 uint32_t raid_level_0 : 1; 772 uint32_t raid_level_1 : 1; 773 uint32_t raid_level_5 : 1; 774 uint32_t raid_level_1E : 1; 775 uint32_t reserved : 28; 776 } raid_levels; 777 778 struct { 779 uint32_t rbld_rate : 1; 780 uint32_t cc_rate : 1; 781 uint32_t bgi_rate : 1; 782 uint32_t recon_rate : 1; 783 uint32_t patrol_rate : 1; 784 uint32_t alarm_control : 1; 785 uint32_t cluster_supported : 1; 786 uint32_t bbu : 1; 787 uint32_t spanning_allowed : 1; 788 uint32_t dedicated_hotspares : 1; 789 uint32_t revertible_hotspares : 1; 790 uint32_t foreign_config_import : 1; 791 uint32_t self_diagnostic : 1; 792 uint32_t reserved : 19; 793 } adapter_operations; 794 795 struct { 796 uint32_t read_policy : 1; 797 uint32_t write_policy : 1; 798 uint32_t io_policy : 1; 799 uint32_t access_policy : 1; 800 uint32_t reserved : 28; 801 } ld_operations; 802 803 struct { 804 uint8_t min; 805 uint8_t max; 806 uint8_t reserved[2]; 807 } stripe_size_operations; 808 809 struct { 810 uint32_t force_online : 1; 811 uint32_t force_offline : 1; 812 uint32_t force_rebuild : 1; 813 uint32_t reserved : 29; 814 } pd_operations; 815 816 struct { 817 uint32_t ctrl_supports_sas : 1; 818 uint32_t ctrl_supports_sata : 1; 819 uint32_t allow_mix_in_encl : 1; 820 uint32_t allow_mix_in_ld : 1; 821 uint32_t allow_sata_in_cluster : 1; 822 uint32_t reserved : 27; 823 } pd_mix_support; 824 825 /* Include the controller properties (changeable items) */ 826 uint8_t reserved_2[12]; 827 struct mrsas_ctrl_prop properties; 828 829 uint8_t pad[0x800 - 0x640]; 830 }; 831 832 /* 833 * ================================== 834 * MegaRAID SAS2.0 driver definitions 835 * ================================== 836 */ 837 #define MRDRV_MAX_NUM_CMD 1024 838 839 #define MRDRV_MAX_PD_CHANNELS 2 840 #define MRDRV_MAX_LD_CHANNELS 2 841 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \ 842 MRDRV_MAX_LD_CHANNELS) 843 #define MRDRV_MAX_DEV_PER_CHANNEL 128 844 #define MRDRV_DEFAULT_INIT_ID -1 845 #define MRDRV_MAX_CMD_PER_LUN 1000 846 #define MRDRV_MAX_LUN 1 847 #define MRDRV_MAX_LD 64 848 849 #define MRDRV_RESET_WAIT_TIME 300 850 #define MRDRV_RESET_NOTICE_INTERVAL 5 851 852 #define MRSAS_IOCTL_CMD 0 853 854 /* 855 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 856 * SGLs based on the size of dma_addr_t 857 */ 858 #define IS_DMA64 (sizeof (dma_addr_t) == 8) 859 860 #define IB_MSG_0_OFF 0x10 /* XScale */ 861 #define OB_MSG_0_OFF 0x18 /* XScale */ 862 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */ 863 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */ 864 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */ 865 #define IB_QPORT_OFF 0x40 /* XScale & ROC */ 866 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */ 867 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */ 868 #define OB_INTR_MASK 0xFFFFFFFF 869 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF 870 871 /* 872 * All MFI register set macros accept mrsas_register_set* 873 */ 874 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \ 875 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v)) 876 877 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \ 878 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF)) 879 880 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \ 881 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v)) 882 883 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \ 884 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF)) 885 886 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \ 887 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v)) 888 889 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \ 890 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF)) 891 892 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \ 893 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v)) 894 895 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \ 896 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF)) 897 898 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 899 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v)) 900 901 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \ 902 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \ 903 (v)) 904 905 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \ 906 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF)) 907 908 /* 909 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data 910 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs 911 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled. 912 */ 913 #define MFI_OB_INTR_STATUS_MASK 0x00000002 914 915 /* 916 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also 917 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has 918 * been set in this flag along with bit 1. 919 */ 920 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001 921 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005 922 923 #define MFI_POLL_TIMEOUT_SECS 60 924 925 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \ 926 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1) 927 #define MFI_DISABLE_INTR(instance) \ 928 { \ 929 uint32_t disable = 1; \ 930 uint32_t mask = ddi_get32((instance)->regmap_handle, \ 931 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\ 932 mask &= ~disable; \ 933 ddi_put32((instance)->regmap_handle, (uint32_t *) \ 934 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \ 935 } 936 937 /* By default, the firmware programs for 8 Kbytes of memory */ 938 #define DEFAULT_MFI_MEM_SZ 8192 939 #define MINIMUM_MFI_MEM_SZ 4096 940 941 /* DCMD Message Frame MAILBOX0-11 */ 942 #define DCMD_MBOX_SZ 12 943 944 945 struct mrsas_register_set { 946 uint32_t reserved_0[4]; 947 948 uint32_t inbound_msg_0; 949 uint32_t inbound_msg_1; 950 uint32_t outbound_msg_0; 951 uint32_t outbound_msg_1; 952 953 uint32_t inbound_doorbell; 954 uint32_t inbound_intr_status; 955 uint32_t inbound_intr_mask; 956 957 uint32_t outbound_doorbell; 958 uint32_t outbound_intr_status; 959 uint32_t outbound_intr_mask; 960 961 uint32_t reserved_1[2]; 962 963 uint32_t inbound_queue_port; 964 uint32_t outbound_queue_port; 965 966 uint32_t reserved_2[22]; 967 968 uint32_t outbound_doorbell_clear; 969 970 uint32_t reserved_3[3]; 971 972 uint32_t outbound_scratch_pad; 973 974 uint32_t reserved_4[3]; 975 976 uint32_t inbound_low_queue_port; 977 978 uint32_t inbound_high_queue_port; 979 980 uint32_t reserved_5; 981 uint32_t index_registers[820]; 982 }; 983 984 struct mrsas_sge32 { 985 uint32_t phys_addr; 986 uint32_t length; 987 }; 988 989 struct mrsas_sge64 { 990 uint64_t phys_addr; 991 uint32_t length; 992 }; 993 994 union mrsas_sgl { 995 struct mrsas_sge32 sge32[1]; 996 struct mrsas_sge64 sge64[1]; 997 }; 998 999 struct mrsas_header { 1000 uint8_t cmd; 1001 uint8_t sense_len; 1002 uint8_t cmd_status; 1003 uint8_t scsi_status; 1004 1005 uint8_t target_id; 1006 uint8_t lun; 1007 uint8_t cdb_len; 1008 uint8_t sge_count; 1009 1010 uint32_t context; 1011 uint8_t req_id; 1012 uint8_t msgvector; 1013 uint16_t pad_0; 1014 1015 uint16_t flags; 1016 uint16_t timeout; 1017 uint32_t data_xferlen; 1018 }; 1019 1020 union mrsas_sgl_frame { 1021 struct mrsas_sge32 sge32[8]; 1022 struct mrsas_sge64 sge64[5]; 1023 }; 1024 1025 struct mrsas_init_frame { 1026 uint8_t cmd; 1027 uint8_t reserved_0; 1028 uint8_t cmd_status; 1029 1030 uint8_t reserved_1; 1031 uint32_t reserved_2; 1032 1033 uint32_t context; 1034 uint8_t req_id; 1035 uint8_t msgvector; 1036 uint16_t pad_0; 1037 1038 uint16_t flags; 1039 uint16_t reserved_3; 1040 uint32_t data_xfer_len; 1041 1042 uint32_t queue_info_new_phys_addr_lo; 1043 uint32_t queue_info_new_phys_addr_hi; 1044 uint32_t queue_info_old_phys_addr_lo; 1045 uint32_t queue_info_old_phys_addr_hi; 1046 1047 uint32_t reserved_4[6]; 1048 }; 1049 1050 struct mrsas_init_queue_info { 1051 uint32_t init_flags; 1052 uint32_t reply_queue_entries; 1053 1054 uint32_t reply_queue_start_phys_addr_lo; 1055 uint32_t reply_queue_start_phys_addr_hi; 1056 uint32_t producer_index_phys_addr_lo; 1057 uint32_t producer_index_phys_addr_hi; 1058 uint32_t consumer_index_phys_addr_lo; 1059 uint32_t consumer_index_phys_addr_hi; 1060 }; 1061 1062 struct mrsas_io_frame { 1063 uint8_t cmd; 1064 uint8_t sense_len; 1065 uint8_t cmd_status; 1066 uint8_t scsi_status; 1067 1068 uint8_t target_id; 1069 uint8_t access_byte; 1070 uint8_t reserved_0; 1071 uint8_t sge_count; 1072 1073 uint32_t context; 1074 uint8_t req_id; 1075 uint8_t msgvector; 1076 uint16_t pad_0; 1077 1078 uint16_t flags; 1079 uint16_t timeout; 1080 uint32_t lba_count; 1081 1082 uint32_t sense_buf_phys_addr_lo; 1083 uint32_t sense_buf_phys_addr_hi; 1084 1085 uint32_t start_lba_lo; 1086 uint32_t start_lba_hi; 1087 1088 union mrsas_sgl sgl; 1089 }; 1090 1091 struct mrsas_pthru_frame { 1092 uint8_t cmd; 1093 uint8_t sense_len; 1094 uint8_t cmd_status; 1095 uint8_t scsi_status; 1096 1097 uint8_t target_id; 1098 uint8_t lun; 1099 uint8_t cdb_len; 1100 uint8_t sge_count; 1101 1102 uint32_t context; 1103 uint8_t req_id; 1104 uint8_t msgvector; 1105 uint16_t pad_0; 1106 1107 uint16_t flags; 1108 uint16_t timeout; 1109 uint32_t data_xfer_len; 1110 1111 uint32_t sense_buf_phys_addr_lo; 1112 uint32_t sense_buf_phys_addr_hi; 1113 1114 uint8_t cdb[16]; 1115 union mrsas_sgl sgl; 1116 }; 1117 1118 struct mrsas_dcmd_frame { 1119 uint8_t cmd; 1120 uint8_t reserved_0; 1121 uint8_t cmd_status; 1122 uint8_t reserved_1[4]; 1123 uint8_t sge_count; 1124 1125 uint32_t context; 1126 uint8_t req_id; 1127 uint8_t msgvector; 1128 uint16_t pad_0; 1129 1130 uint16_t flags; 1131 uint16_t timeout; 1132 1133 uint32_t data_xfer_len; 1134 uint32_t opcode; 1135 1136 union { 1137 uint8_t b[DCMD_MBOX_SZ]; 1138 uint16_t s[6]; 1139 uint32_t w[3]; 1140 } mbox; 1141 1142 union mrsas_sgl sgl; 1143 }; 1144 1145 struct mrsas_abort_frame { 1146 uint8_t cmd; 1147 uint8_t reserved_0; 1148 uint8_t cmd_status; 1149 1150 uint8_t reserved_1; 1151 uint32_t reserved_2; 1152 1153 uint32_t context; 1154 uint8_t req_id; 1155 uint8_t msgvector; 1156 uint16_t pad_0; 1157 1158 uint16_t flags; 1159 uint16_t reserved_3; 1160 uint32_t reserved_4; 1161 1162 uint32_t abort_context; 1163 uint32_t pad_1; 1164 1165 uint32_t abort_mfi_phys_addr_lo; 1166 uint32_t abort_mfi_phys_addr_hi; 1167 1168 uint32_t reserved_5[6]; 1169 }; 1170 1171 struct mrsas_smp_frame { 1172 uint8_t cmd; 1173 uint8_t reserved_1; 1174 uint8_t cmd_status; 1175 uint8_t connection_status; 1176 1177 uint8_t reserved_2[3]; 1178 uint8_t sge_count; 1179 1180 uint32_t context; 1181 uint8_t req_id; 1182 uint8_t msgvector; 1183 uint16_t pad_0; 1184 1185 uint16_t flags; 1186 uint16_t timeout; 1187 1188 uint32_t data_xfer_len; 1189 1190 uint64_t sas_addr; 1191 1192 union mrsas_sgl sgl[2]; 1193 }; 1194 1195 struct mrsas_stp_frame { 1196 uint8_t cmd; 1197 uint8_t reserved_1; 1198 uint8_t cmd_status; 1199 uint8_t connection_status; 1200 1201 uint8_t target_id; 1202 uint8_t reserved_2[2]; 1203 uint8_t sge_count; 1204 1205 uint32_t context; 1206 uint8_t req_id; 1207 uint8_t msgvector; 1208 uint16_t pad_0; 1209 1210 uint16_t flags; 1211 uint16_t timeout; 1212 1213 uint32_t data_xfer_len; 1214 1215 uint16_t fis[10]; 1216 uint32_t stp_flags; 1217 union mrsas_sgl sgl; 1218 }; 1219 1220 union mrsas_frame { 1221 struct mrsas_header hdr; 1222 struct mrsas_init_frame init; 1223 struct mrsas_io_frame io; 1224 struct mrsas_pthru_frame pthru; 1225 struct mrsas_dcmd_frame dcmd; 1226 struct mrsas_abort_frame abort; 1227 struct mrsas_smp_frame smp; 1228 struct mrsas_stp_frame stp; 1229 1230 uint8_t raw_bytes[64]; 1231 }; 1232 1233 typedef struct mrsas_pd_address { 1234 uint16_t device_id; 1235 uint16_t encl_id; 1236 1237 union { 1238 struct { 1239 uint8_t encl_index; 1240 uint8_t slot_number; 1241 } pd_address; 1242 struct { 1243 uint8_t encl_position; 1244 uint8_t encl_connector_index; 1245 } encl_address; 1246 }address; 1247 1248 uint8_t scsi_dev_type; 1249 1250 union { 1251 uint8_t port_bitmap; 1252 uint8_t port_numbers; 1253 } connected; 1254 1255 uint64_t sas_addr[2]; 1256 } mrsas_pd_address_t; 1257 1258 union mrsas_evt_class_locale { 1259 struct { 1260 uint16_t locale; 1261 uint8_t reserved; 1262 int8_t class; 1263 } members; 1264 1265 uint32_t word; 1266 }; 1267 1268 struct mrsas_evt_log_info { 1269 uint32_t newest_seq_num; 1270 uint32_t oldest_seq_num; 1271 uint32_t clear_seq_num; 1272 uint32_t shutdown_seq_num; 1273 uint32_t boot_seq_num; 1274 }; 1275 1276 struct mrsas_progress { 1277 uint16_t progress; 1278 uint16_t elapsed_seconds; 1279 }; 1280 1281 struct mrsas_evtarg_ld { 1282 uint16_t target_id; 1283 uint8_t ld_index; 1284 uint8_t reserved; 1285 }; 1286 1287 struct mrsas_evtarg_pd { 1288 uint16_t device_id; 1289 uint8_t encl_index; 1290 uint8_t slot_number; 1291 }; 1292 1293 struct mrsas_evt_detail { 1294 uint32_t seq_num; 1295 uint32_t time_stamp; 1296 uint32_t code; 1297 union mrsas_evt_class_locale cl; 1298 uint8_t arg_type; 1299 uint8_t reserved1[15]; 1300 1301 union { 1302 struct { 1303 struct mrsas_evtarg_pd pd; 1304 uint8_t cdb_length; 1305 uint8_t sense_length; 1306 uint8_t reserved[2]; 1307 uint8_t cdb[16]; 1308 uint8_t sense[64]; 1309 } cdbSense; 1310 1311 struct mrsas_evtarg_ld ld; 1312 1313 struct { 1314 struct mrsas_evtarg_ld ld; 1315 uint64_t count; 1316 } ld_count; 1317 1318 struct { 1319 uint64_t lba; 1320 struct mrsas_evtarg_ld ld; 1321 } ld_lba; 1322 1323 struct { 1324 struct mrsas_evtarg_ld ld; 1325 uint32_t prevOwner; 1326 uint32_t newOwner; 1327 } ld_owner; 1328 1329 struct { 1330 uint64_t ld_lba; 1331 uint64_t pd_lba; 1332 struct mrsas_evtarg_ld ld; 1333 struct mrsas_evtarg_pd pd; 1334 } ld_lba_pd_lba; 1335 1336 struct { 1337 struct mrsas_evtarg_ld ld; 1338 struct mrsas_progress prog; 1339 } ld_prog; 1340 1341 struct { 1342 struct mrsas_evtarg_ld ld; 1343 uint32_t prev_state; 1344 uint32_t new_state; 1345 } ld_state; 1346 1347 struct { 1348 uint64_t strip; 1349 struct mrsas_evtarg_ld ld; 1350 } ld_strip; 1351 1352 struct mrsas_evtarg_pd pd; 1353 1354 struct { 1355 struct mrsas_evtarg_pd pd; 1356 uint32_t err; 1357 } pd_err; 1358 1359 struct { 1360 uint64_t lba; 1361 struct mrsas_evtarg_pd pd; 1362 } pd_lba; 1363 1364 struct { 1365 uint64_t lba; 1366 struct mrsas_evtarg_pd pd; 1367 struct mrsas_evtarg_ld ld; 1368 } pd_lba_ld; 1369 1370 struct { 1371 struct mrsas_evtarg_pd pd; 1372 struct mrsas_progress prog; 1373 } pd_prog; 1374 1375 struct { 1376 struct mrsas_evtarg_pd pd; 1377 uint32_t prevState; 1378 uint32_t newState; 1379 } pd_state; 1380 1381 struct { 1382 uint16_t vendorId; 1383 uint16_t deviceId; 1384 uint16_t subVendorId; 1385 uint16_t subDeviceId; 1386 } pci; 1387 1388 uint32_t rate; 1389 char str[96]; 1390 1391 struct { 1392 uint32_t rtc; 1393 uint32_t elapsedSeconds; 1394 } time; 1395 1396 struct { 1397 uint32_t ecar; 1398 uint32_t elog; 1399 char str[64]; 1400 } ecc; 1401 1402 mrsas_pd_address_t pd_addr; 1403 1404 uint8_t b[96]; 1405 uint16_t s[48]; 1406 uint32_t w[24]; 1407 uint64_t d[12]; 1408 } args; 1409 1410 char description[128]; 1411 1412 }; 1413 1414 /* only 63 are usable by the application */ 1415 #define MAX_LOGICAL_DRIVES 64 1416 /* only 255 physical devices may be used */ 1417 #define MAX_PHYSICAL_DEVICES 256 1418 #define MAX_PD_PER_ENCLOSURE 64 1419 /* maximum disks per array */ 1420 #define MAX_ROW_SIZE 32 1421 /* maximum spans per logical drive */ 1422 #define MAX_SPAN_DEPTH 8 1423 /* maximum number of arrays a hot spare may be dedicated to */ 1424 #define MAX_ARRAYS_DEDICATED 16 1425 /* maximum number of arrays which may exist */ 1426 #define MAX_ARRAYS 128 1427 /* maximum number of foreign configs that may ha managed at once */ 1428 #define MAX_FOREIGN_CONFIGS 8 1429 /* maximum spares (global and dedicated combined) */ 1430 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES 1431 /* maximum possible Target IDs (i.e. 0 to 63) */ 1432 #define MAX_TARGET_ID 63 1433 /* maximum number of supported enclosures */ 1434 #define MAX_ENCLOSURES 32 1435 /* maximum number of PHYs per controller */ 1436 #define MAX_PHYS_PER_CONTROLLER 16 1437 /* maximum number of LDs per array (due to DDF limitations) */ 1438 #define MAX_LDS_PER_ARRAY 16 1439 1440 /* 1441 * ----------------------------------------------------------------------------- 1442 * ----------------------------------------------------------------------------- 1443 * 1444 * Logical Drive commands 1445 * 1446 * ----------------------------------------------------------------------------- 1447 * ----------------------------------------------------------------------------- 1448 */ 1449 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */ 1450 1451 /* 1452 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST 1453 * dcmd.mbox - reserved 1454 * dcmd.sge IN - ptr to returned MR_LD_LIST structure 1455 * Desc: Return the logical drive list structure 1456 * Status: No error 1457 */ 1458 1459 /* 1460 * defines the logical drive reference structure 1461 */ 1462 typedef union _MR_LD_REF { /* LD reference structure */ 1463 struct { 1464 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */ 1465 uint8_t reserved; /* reserved for in line with MR_PD_REF */ 1466 uint16_t seqNum; /* Sequence Number */ 1467 } ld_ref; 1468 uint32_t ref; /* shorthand reference to full 32-bits */ 1469 } MR_LD_REF; /* 4 bytes */ 1470 1471 /* 1472 * defines the logical drive list structure 1473 */ 1474 typedef struct _MR_LD_LIST { 1475 uint32_t ldCount; /* number of LDs */ 1476 uint32_t reserved; /* pad to 8-byte boundary */ 1477 struct { 1478 MR_LD_REF ref; /* LD reference */ 1479 uint8_t state; /* current LD state (MR_LD_STATE) */ 1480 uint8_t reserved[3]; /* pad to 8-byte boundary */ 1481 uint64_t size; /* LD size */ 1482 } ldList[MAX_LOGICAL_DRIVES]; 1483 } MR_LD_LIST; 1484 1485 struct mrsas_drv_ver { 1486 uint8_t signature[12]; 1487 uint8_t os_name[16]; 1488 uint8_t os_ver[12]; 1489 uint8_t drv_name[20]; 1490 uint8_t drv_ver[32]; 1491 uint8_t drv_rel_date[20]; 1492 }; 1493 1494 #define PCI_TYPE0_ADDRESSES 6 1495 #define PCI_TYPE1_ADDRESSES 2 1496 #define PCI_TYPE2_ADDRESSES 5 1497 1498 struct mrsas_pci_common_header { 1499 uint16_t vendorID; /* (ro) */ 1500 uint16_t deviceID; /* (ro) */ 1501 uint16_t command; /* Device control */ 1502 uint16_t status; 1503 uint8_t revisionID; /* (ro) */ 1504 uint8_t progIf; /* (ro) */ 1505 uint8_t subClass; /* (ro) */ 1506 uint8_t baseClass; /* (ro) */ 1507 uint8_t cacheLineSize; /* (ro+) */ 1508 uint8_t latencyTimer; /* (ro+) */ 1509 uint8_t headerType; /* (ro) */ 1510 uint8_t bist; /* Built in self test */ 1511 1512 union { 1513 struct { 1514 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 1515 uint32_t cis; 1516 uint16_t subVendorID; 1517 uint16_t subSystemID; 1518 uint32_t romBaseAddress; 1519 uint8_t capabilitiesPtr; 1520 uint8_t reserved1[3]; 1521 uint32_t reserved2; 1522 uint8_t interruptLine; 1523 uint8_t interruptPin; /* (ro) */ 1524 uint8_t minimumGrant; /* (ro) */ 1525 uint8_t maximumLatency; /* (ro) */ 1526 } type_0; 1527 1528 struct { 1529 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 1530 uint8_t primaryBus; 1531 uint8_t secondaryBus; 1532 uint8_t subordinateBus; 1533 uint8_t secondaryLatency; 1534 uint8_t ioBase; 1535 uint8_t ioLimit; 1536 uint16_t secondaryStatus; 1537 uint16_t memoryBase; 1538 uint16_t memoryLimit; 1539 uint16_t prefetchBase; 1540 uint16_t prefetchLimit; 1541 uint32_t prefetchBaseUpper32; 1542 uint32_t prefetchLimitUpper32; 1543 uint16_t ioBaseUpper16; 1544 uint16_t ioLimitUpper16; 1545 uint8_t capabilitiesPtr; 1546 uint8_t reserved1[3]; 1547 uint32_t romBaseAddress; 1548 uint8_t interruptLine; 1549 uint8_t interruptPin; 1550 uint16_t bridgeControl; 1551 } type_1; 1552 1553 struct { 1554 uint32_t socketRegistersBaseAddress; 1555 uint8_t capabilitiesPtr; 1556 uint8_t reserved; 1557 uint16_t secondaryStatus; 1558 uint8_t primaryBus; 1559 uint8_t secondaryBus; 1560 uint8_t subordinateBus; 1561 uint8_t secondaryLatency; 1562 struct { 1563 uint32_t base; 1564 uint32_t limit; 1565 } range[PCI_TYPE2_ADDRESSES-1]; 1566 uint8_t interruptLine; 1567 uint8_t interruptPin; 1568 uint16_t bridgeControl; 1569 } type_2; 1570 } header; 1571 }; 1572 1573 struct mrsas_pci_link_capability { 1574 union { 1575 struct { 1576 uint32_t linkSpeed :4; 1577 uint32_t linkWidth :6; 1578 uint32_t aspmSupport :2; 1579 uint32_t losExitLatency :3; 1580 uint32_t l1ExitLatency :3; 1581 uint32_t rsvdp :6; 1582 uint32_t portNumber :8; 1583 } bits; 1584 1585 uint32_t asUlong; 1586 } cap; 1587 1588 }; 1589 1590 struct mrsas_pci_link_status_capability { 1591 union { 1592 struct { 1593 uint16_t linkSpeed :4; 1594 uint16_t negotiatedLinkWidth :6; 1595 uint16_t linkTrainingError :1; 1596 uint16_t linkTraning :1; 1597 uint16_t slotClockConfig :1; 1598 uint16_t rsvdZ :3; 1599 } bits; 1600 1601 uint16_t asUshort; 1602 } stat_cap; 1603 1604 uint16_t reserved; 1605 1606 }; 1607 1608 struct mrsas_pci_capabilities { 1609 struct mrsas_pci_link_capability linkCapability; 1610 struct mrsas_pci_link_status_capability linkStatusCapability; 1611 }; 1612 1613 struct mrsas_pci_information 1614 { 1615 uint32_t busNumber; 1616 uint8_t deviceNumber; 1617 uint8_t functionNumber; 1618 uint8_t interruptVector; 1619 uint8_t reserved; 1620 struct mrsas_pci_common_header pciHeaderInfo; 1621 struct mrsas_pci_capabilities capability; 1622 uint8_t reserved2[32]; 1623 }; 1624 1625 struct mrsas_ioctl { 1626 uint16_t version; 1627 uint16_t controller_id; 1628 uint8_t signature[8]; 1629 uint32_t reserved_1; 1630 uint32_t control_code; 1631 uint32_t reserved_2[2]; 1632 uint8_t frame[64]; 1633 union mrsas_sgl_frame sgl_frame; 1634 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH]; 1635 uint8_t data[1]; 1636 }; 1637 1638 struct mrsas_aen { 1639 uint16_t host_no; 1640 uint16_t cmd_status; 1641 uint32_t seq_num; 1642 uint32_t class_locale_word; 1643 }; 1644 #pragma pack() 1645 1646 #ifndef DDI_VENDOR_LSI 1647 #define DDI_VENDOR_LSI "LSI" 1648 #endif /* DDI_VENDOR_LSI */ 1649 1650 #ifndef KMDB_MODULE 1651 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 1652 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t); 1653 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t); 1654 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t); 1655 static int mrsas_open(dev_t *, int, int, cred_t *); 1656 static int mrsas_close(dev_t, int, int, cred_t *); 1657 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 1658 1659 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *, 1660 scsi_hba_tran_t *, struct scsi_device *); 1661 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register 1662 struct scsi_pkt *, struct buf *, int, int, int, int, 1663 int (*)(), caddr_t); 1664 static int mrsas_tran_start(struct scsi_address *, 1665 register struct scsi_pkt *); 1666 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *); 1667 static int mrsas_tran_reset(struct scsi_address *, int); 1668 static int mrsas_tran_getcap(struct scsi_address *, char *, int); 1669 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int); 1670 static void mrsas_tran_destroy_pkt(struct scsi_address *, 1671 struct scsi_pkt *); 1672 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *); 1673 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *); 1674 static uint_t mrsas_isr(); 1675 static uint_t mrsas_softintr(); 1676 1677 static int init_mfi(struct mrsas_instance *); 1678 static int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t); 1679 static int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *, 1680 uchar_t); 1681 static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *); 1682 static void return_mfi_pkt(struct mrsas_instance *, 1683 struct mrsas_cmd *); 1684 1685 static void free_space_for_mfi(struct mrsas_instance *); 1686 static void free_additional_dma_buffer(struct mrsas_instance *); 1687 static int alloc_additional_dma_buffer(struct mrsas_instance *); 1688 static int read_fw_status_reg_ppc(struct mrsas_instance *); 1689 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *); 1690 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *, 1691 struct mrsas_cmd *); 1692 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *, 1693 struct mrsas_cmd *); 1694 static void enable_intr_ppc(struct mrsas_instance *); 1695 static void disable_intr_ppc(struct mrsas_instance *); 1696 static int intr_ack_ppc(struct mrsas_instance *); 1697 static int mfi_state_transition_to_ready(struct mrsas_instance *); 1698 static void destroy_mfi_frame_pool(struct mrsas_instance *); 1699 static int create_mfi_frame_pool(struct mrsas_instance *); 1700 static int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *, 1701 struct buf *, int, int (*)()); 1702 static int mrsas_dma_move(struct mrsas_instance *, 1703 struct scsi_pkt *, struct buf *); 1704 static void flush_cache(struct mrsas_instance *instance); 1705 static void display_scsi_inquiry(caddr_t); 1706 static int start_mfi_aen(struct mrsas_instance *instance); 1707 static int handle_drv_ioctl(struct mrsas_instance *instance, 1708 struct mrsas_ioctl *ioctl, int mode); 1709 static int handle_mfi_ioctl(struct mrsas_instance *instance, 1710 struct mrsas_ioctl *ioctl, int mode); 1711 static int handle_mfi_aen(struct mrsas_instance *instance, 1712 struct mrsas_aen *aen); 1713 static void fill_up_drv_ver(struct mrsas_drv_ver *dv); 1714 static struct mrsas_cmd *build_cmd(struct mrsas_instance *instance, 1715 struct scsi_address *ap, struct scsi_pkt *pkt, 1716 uchar_t *cmd_done); 1717 static int register_mfi_aen(struct mrsas_instance *instance, 1718 uint32_t seq_num, uint32_t class_locale_word); 1719 static int issue_mfi_pthru(struct mrsas_instance *instance, struct 1720 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1721 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct 1722 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1723 static int issue_mfi_smp(struct mrsas_instance *instance, struct 1724 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1725 static int issue_mfi_stp(struct mrsas_instance *instance, struct 1726 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 1727 static int abort_aen_cmd(struct mrsas_instance *instance, 1728 struct mrsas_cmd *cmd_to_abort); 1729 1730 static int mrsas_common_check(struct mrsas_instance *instance, 1731 struct mrsas_cmd *cmd); 1732 static void mrsas_fm_init(struct mrsas_instance *instance); 1733 static void mrsas_fm_fini(struct mrsas_instance *instance); 1734 static int mrsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 1735 const void *); 1736 static void mrsas_fm_ereport(struct mrsas_instance *instance, 1737 char *detail); 1738 static int mrsas_check_dma_handle(ddi_dma_handle_t handle); 1739 static int mrsas_check_acc_handle(ddi_acc_handle_t handle); 1740 1741 static void mrsas_rem_intrs(struct mrsas_instance *instance); 1742 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type); 1743 1744 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *, 1745 scsi_hba_tran_t *, struct scsi_device *); 1746 static int mrsas_tran_bus_config(dev_info_t *, uint_t, 1747 ddi_bus_config_op_t, void *, dev_info_t **); 1748 static int mrsas_parse_devname(char *, int *, int *); 1749 static int mrsas_config_all_devices(struct mrsas_instance *); 1750 static int mrsas_config_scsi_device(struct mrsas_instance *, 1751 struct scsi_device *, dev_info_t **); 1752 static int mrsas_config_ld(struct mrsas_instance *, uint16_t, 1753 uint8_t, dev_info_t **); 1754 static dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, 1755 uint8_t); 1756 static int mrsas_name_node(dev_info_t *, char *, int); 1757 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *); 1758 static int mrsas_service_evt(struct mrsas_instance *, int, int, int, 1759 uint64_t); 1760 static int mrsas_mode_sense_build(struct scsi_pkt *); 1761 #endif /* KMDB_MODULE */ 1762 1763 #ifdef __cplusplus 1764 } 1765 #endif 1766 1767 #endif /* _MR_SAS_H_ */ 1768