1 /* 2 * mr_sas.c: source for mr_sas driver 3 * 4 * Solaris MegaRAID device driver for SAS2.0 controllers 5 * Copyright (c) 2008-2012, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Version: 9 * Author: 10 * Swaminathan K S 11 * Arun Chandrashekhar 12 * Manju R 13 * Rasheed 14 * Shakeel Bukhari 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions are met: 18 * 19 * 1. Redistributions of source code must retain the above copyright notice, 20 * this list of conditions and the following disclaimer. 21 * 22 * 2. Redistributions in binary form must reproduce the above copyright notice, 23 * this list of conditions and the following disclaimer in the documentation 24 * and/or other materials provided with the distribution. 25 * 26 * 3. Neither the name of the author nor the names of its contributors may be 27 * used to endorse or promote products derived from this software without 28 * specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 41 * DAMAGE. 42 */ 43 44 /* 45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 46 * Copyright (c) 2011 Bayard G. Bell. All rights reserved. 47 * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 48 * Copyright 2015 Citrus IT Limited. All rights reserved. 49 */ 50 51 #include <sys/types.h> 52 #include <sys/param.h> 53 #include <sys/file.h> 54 #include <sys/errno.h> 55 #include <sys/open.h> 56 #include <sys/cred.h> 57 #include <sys/modctl.h> 58 #include <sys/conf.h> 59 #include <sys/devops.h> 60 #include <sys/cmn_err.h> 61 #include <sys/kmem.h> 62 #include <sys/stat.h> 63 #include <sys/mkdev.h> 64 #include <sys/pci.h> 65 #include <sys/scsi/scsi.h> 66 #include <sys/ddi.h> 67 #include <sys/sunddi.h> 68 #include <sys/atomic.h> 69 #include <sys/signal.h> 70 #include <sys/byteorder.h> 71 #include <sys/sdt.h> 72 #include <sys/fs/dv_node.h> /* devfs_clean */ 73 74 #include "mr_sas.h" 75 76 /* 77 * FMA header files 78 */ 79 #include <sys/ddifm.h> 80 #include <sys/fm/protocol.h> 81 #include <sys/fm/util.h> 82 #include <sys/fm/io/ddi.h> 83 84 /* Macros to help Skinny and stock 2108/MFI live together. */ 85 #define WR_IB_PICK_QPORT(addr, instance) \ 86 if ((instance)->skinny) { \ 87 WR_IB_LOW_QPORT((addr), (instance)); \ 88 WR_IB_HIGH_QPORT(0, (instance)); \ 89 } else { \ 90 WR_IB_QPORT((addr), (instance)); \ 91 } 92 93 /* 94 * Local static data 95 */ 96 static void *mrsas_state = NULL; 97 static volatile boolean_t mrsas_relaxed_ordering = B_TRUE; 98 volatile int debug_level_g = CL_NONE; 99 static volatile int msi_enable = 1; 100 static volatile int ctio_enable = 1; 101 102 /* Default Timeout value to issue online controller reset */ 103 volatile int debug_timeout_g = 0xF0; /* 0xB4; */ 104 /* Simulate consecutive firmware fault */ 105 static volatile int debug_fw_faults_after_ocr_g = 0; 106 #ifdef OCRDEBUG 107 /* Simulate three consecutive timeout for an IO */ 108 static volatile int debug_consecutive_timeout_after_ocr_g = 0; 109 #endif 110 111 #pragma weak scsi_hba_open 112 #pragma weak scsi_hba_close 113 #pragma weak scsi_hba_ioctl 114 115 /* Local static prototypes. */ 116 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 117 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t); 118 #ifdef __sparc 119 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t); 120 #else 121 static int mrsas_quiesce(dev_info_t *); 122 #endif 123 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t); 124 static int mrsas_open(dev_t *, int, int, cred_t *); 125 static int mrsas_close(dev_t, int, int, cred_t *); 126 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 127 128 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *, 129 scsi_hba_tran_t *, struct scsi_device *); 130 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register 131 struct scsi_pkt *, struct buf *, int, int, int, int, 132 int (*)(), caddr_t); 133 static int mrsas_tran_start(struct scsi_address *, 134 register struct scsi_pkt *); 135 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *); 136 static int mrsas_tran_reset(struct scsi_address *, int); 137 static int mrsas_tran_getcap(struct scsi_address *, char *, int); 138 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int); 139 static void mrsas_tran_destroy_pkt(struct scsi_address *, 140 struct scsi_pkt *); 141 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *); 142 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *); 143 static int mrsas_tran_quiesce(dev_info_t *dip); 144 static int mrsas_tran_unquiesce(dev_info_t *dip); 145 static uint_t mrsas_isr(); 146 static uint_t mrsas_softintr(); 147 static void mrsas_undo_resources(dev_info_t *, struct mrsas_instance *); 148 149 static void free_space_for_mfi(struct mrsas_instance *); 150 static uint32_t read_fw_status_reg_ppc(struct mrsas_instance *); 151 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *); 152 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *, 153 struct mrsas_cmd *); 154 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *, 155 struct mrsas_cmd *); 156 static void enable_intr_ppc(struct mrsas_instance *); 157 static void disable_intr_ppc(struct mrsas_instance *); 158 static int intr_ack_ppc(struct mrsas_instance *); 159 static void flush_cache(struct mrsas_instance *instance); 160 void display_scsi_inquiry(caddr_t); 161 static int start_mfi_aen(struct mrsas_instance *instance); 162 static int handle_drv_ioctl(struct mrsas_instance *instance, 163 struct mrsas_ioctl *ioctl, int mode); 164 static int handle_mfi_ioctl(struct mrsas_instance *instance, 165 struct mrsas_ioctl *ioctl, int mode); 166 static int handle_mfi_aen(struct mrsas_instance *instance, 167 struct mrsas_aen *aen); 168 static struct mrsas_cmd *build_cmd(struct mrsas_instance *, 169 struct scsi_address *, struct scsi_pkt *, uchar_t *); 170 static int alloc_additional_dma_buffer(struct mrsas_instance *); 171 static void complete_cmd_in_sync_mode(struct mrsas_instance *, 172 struct mrsas_cmd *); 173 static int mrsas_kill_adapter(struct mrsas_instance *); 174 static int mrsas_issue_init_mfi(struct mrsas_instance *); 175 static int mrsas_reset_ppc(struct mrsas_instance *); 176 static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *); 177 static int wait_for_outstanding(struct mrsas_instance *instance); 178 static int register_mfi_aen(struct mrsas_instance *instance, 179 uint32_t seq_num, uint32_t class_locale_word); 180 static int issue_mfi_pthru(struct mrsas_instance *instance, struct 181 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 182 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct 183 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 184 static int issue_mfi_smp(struct mrsas_instance *instance, struct 185 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 186 static int issue_mfi_stp(struct mrsas_instance *instance, struct 187 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 188 static int abort_aen_cmd(struct mrsas_instance *instance, 189 struct mrsas_cmd *cmd_to_abort); 190 191 static void mrsas_rem_intrs(struct mrsas_instance *instance); 192 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type); 193 194 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *, 195 scsi_hba_tran_t *, struct scsi_device *); 196 static int mrsas_tran_bus_config(dev_info_t *, uint_t, 197 ddi_bus_config_op_t, void *, dev_info_t **); 198 static int mrsas_parse_devname(char *, int *, int *); 199 static int mrsas_config_all_devices(struct mrsas_instance *); 200 static int mrsas_config_ld(struct mrsas_instance *, uint16_t, 201 uint8_t, dev_info_t **); 202 static int mrsas_name_node(dev_info_t *, char *, int); 203 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *); 204 static void free_additional_dma_buffer(struct mrsas_instance *); 205 static void io_timeout_checker(void *); 206 static void mrsas_fm_init(struct mrsas_instance *); 207 static void mrsas_fm_fini(struct mrsas_instance *); 208 209 static struct mrsas_function_template mrsas_function_template_ppc = { 210 .read_fw_status_reg = read_fw_status_reg_ppc, 211 .issue_cmd = issue_cmd_ppc, 212 .issue_cmd_in_sync_mode = issue_cmd_in_sync_mode_ppc, 213 .issue_cmd_in_poll_mode = issue_cmd_in_poll_mode_ppc, 214 .enable_intr = enable_intr_ppc, 215 .disable_intr = disable_intr_ppc, 216 .intr_ack = intr_ack_ppc, 217 .init_adapter = mrsas_init_adapter_ppc 218 }; 219 220 221 static struct mrsas_function_template mrsas_function_template_fusion = { 222 .read_fw_status_reg = tbolt_read_fw_status_reg, 223 .issue_cmd = tbolt_issue_cmd, 224 .issue_cmd_in_sync_mode = tbolt_issue_cmd_in_sync_mode, 225 .issue_cmd_in_poll_mode = tbolt_issue_cmd_in_poll_mode, 226 .enable_intr = tbolt_enable_intr, 227 .disable_intr = tbolt_disable_intr, 228 .intr_ack = tbolt_intr_ack, 229 .init_adapter = mrsas_init_adapter_tbolt 230 }; 231 232 233 ddi_dma_attr_t mrsas_generic_dma_attr = { 234 DMA_ATTR_V0, /* dma_attr_version */ 235 0, /* low DMA address range */ 236 0xFFFFFFFFU, /* high DMA address range */ 237 0xFFFFFFFFU, /* DMA counter register */ 238 8, /* DMA address alignment */ 239 0x07, /* DMA burstsizes */ 240 1, /* min DMA size */ 241 0xFFFFFFFFU, /* max DMA size */ 242 0xFFFFFFFFU, /* segment boundary */ 243 MRSAS_MAX_SGE_CNT, /* dma_attr_sglen */ 244 512, /* granularity of device */ 245 0 /* bus specific DMA flags */ 246 }; 247 248 int32_t mrsas_max_cap_maxxfer = 0x1000000; 249 250 /* 251 * Fix for: Thunderbolt controller IO timeout when IO write size is 1MEG, 252 * Limit size to 256K 253 */ 254 uint32_t mrsas_tbolt_max_cap_maxxfer = (512 * 512); 255 256 /* 257 * cb_ops contains base level routines 258 */ 259 static struct cb_ops mrsas_cb_ops = { 260 mrsas_open, /* open */ 261 mrsas_close, /* close */ 262 nodev, /* strategy */ 263 nodev, /* print */ 264 nodev, /* dump */ 265 nodev, /* read */ 266 nodev, /* write */ 267 mrsas_ioctl, /* ioctl */ 268 nodev, /* devmap */ 269 nodev, /* mmap */ 270 nodev, /* segmap */ 271 nochpoll, /* poll */ 272 nodev, /* cb_prop_op */ 273 0, /* streamtab */ 274 D_NEW | D_HOTPLUG, /* cb_flag */ 275 CB_REV, /* cb_rev */ 276 nodev, /* cb_aread */ 277 nodev /* cb_awrite */ 278 }; 279 280 /* 281 * dev_ops contains configuration routines 282 */ 283 static struct dev_ops mrsas_ops = { 284 DEVO_REV, /* rev, */ 285 0, /* refcnt */ 286 mrsas_getinfo, /* getinfo */ 287 nulldev, /* identify */ 288 nulldev, /* probe */ 289 mrsas_attach, /* attach */ 290 mrsas_detach, /* detach */ 291 #ifdef __sparc 292 mrsas_reset, /* reset */ 293 #else /* __sparc */ 294 nodev, 295 #endif /* __sparc */ 296 &mrsas_cb_ops, /* char/block ops */ 297 NULL, /* bus ops */ 298 NULL, /* power */ 299 #ifdef __sparc 300 ddi_quiesce_not_needed 301 #else /* __sparc */ 302 mrsas_quiesce /* quiesce */ 303 #endif /* __sparc */ 304 }; 305 306 static struct modldrv modldrv = { 307 &mod_driverops, /* module type - driver */ 308 MRSAS_VERSION, 309 &mrsas_ops, /* driver ops */ 310 }; 311 312 static struct modlinkage modlinkage = { 313 MODREV_1, /* ml_rev - must be MODREV_1 */ 314 &modldrv, /* ml_linkage */ 315 NULL /* end of driver linkage */ 316 }; 317 318 static struct ddi_device_acc_attr endian_attr = { 319 DDI_DEVICE_ATTR_V1, 320 DDI_STRUCTURE_LE_ACC, 321 DDI_STRICTORDER_ACC, 322 DDI_DEFAULT_ACC 323 }; 324 325 /* Use the LSI Fast Path for the 2208 (tbolt) commands. */ 326 unsigned int enable_fp = 1; 327 328 329 /* 330 * ************************************************************************** * 331 * * 332 * common entry points - for loadable kernel modules * 333 * * 334 * ************************************************************************** * 335 */ 336 337 /* 338 * _init - initialize a loadable module 339 * @void 340 * 341 * The driver should perform any one-time resource allocation or data 342 * initialization during driver loading in _init(). For example, the driver 343 * should initialize any mutexes global to the driver in this routine. 344 * The driver should not, however, use _init() to allocate or initialize 345 * anything that has to do with a particular instance of the device. 346 * Per-instance initialization must be done in attach(). 347 */ 348 int 349 _init(void) 350 { 351 int ret; 352 353 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 354 355 ret = ddi_soft_state_init(&mrsas_state, 356 sizeof (struct mrsas_instance), 0); 357 358 if (ret != DDI_SUCCESS) { 359 cmn_err(CE_WARN, "mr_sas: could not init state"); 360 return (ret); 361 } 362 363 if ((ret = scsi_hba_init(&modlinkage)) != DDI_SUCCESS) { 364 cmn_err(CE_WARN, "mr_sas: could not init scsi hba"); 365 ddi_soft_state_fini(&mrsas_state); 366 return (ret); 367 } 368 369 ret = mod_install(&modlinkage); 370 371 if (ret != DDI_SUCCESS) { 372 cmn_err(CE_WARN, "mr_sas: mod_install failed"); 373 scsi_hba_fini(&modlinkage); 374 ddi_soft_state_fini(&mrsas_state); 375 } 376 377 return (ret); 378 } 379 380 /* 381 * _info - returns information about a loadable module. 382 * @void 383 * 384 * _info() is called to return module information. This is a typical entry 385 * point that does predefined role. It simply calls mod_info(). 386 */ 387 int 388 _info(struct modinfo *modinfop) 389 { 390 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 391 392 return (mod_info(&modlinkage, modinfop)); 393 } 394 395 /* 396 * _fini - prepare a loadable module for unloading 397 * @void 398 * 399 * In _fini(), the driver should release any resources that were allocated in 400 * _init(). The driver must remove itself from the system module list. 401 */ 402 int 403 _fini(void) 404 { 405 int ret; 406 407 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 408 409 if ((ret = mod_remove(&modlinkage)) != DDI_SUCCESS) { 410 con_log(CL_ANN1, 411 (CE_WARN, "_fini: mod_remove() failed, error 0x%X", ret)); 412 return (ret); 413 } 414 415 scsi_hba_fini(&modlinkage); 416 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: scsi_hba_fini() done.")); 417 418 ddi_soft_state_fini(&mrsas_state); 419 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: ddi_soft_state_fini() done.")); 420 421 return (ret); 422 } 423 424 425 /* 426 * ************************************************************************** * 427 * * 428 * common entry points - for autoconfiguration * 429 * * 430 * ************************************************************************** * 431 */ 432 /* 433 * attach - adds a device to the system as part of initialization 434 * @dip: 435 * @cmd: 436 * 437 * The kernel calls a driver's attach() entry point to attach an instance of 438 * a device (for MegaRAID, it is instance of a controller) or to resume 439 * operation for an instance of a device that has been suspended or has been 440 * shut down by the power management framework 441 * The attach() entry point typically includes the following types of 442 * processing: 443 * - allocate a soft-state structure for the device instance (for MegaRAID, 444 * controller instance) 445 * - initialize per-instance mutexes 446 * - initialize condition variables 447 * - register the device's interrupts (for MegaRAID, controller's interrupts) 448 * - map the registers and memory of the device instance (for MegaRAID, 449 * controller instance) 450 * - create minor device nodes for the device instance (for MegaRAID, 451 * controller instance) 452 * - report that the device instance (for MegaRAID, controller instance) has 453 * attached 454 */ 455 static int 456 mrsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 457 { 458 int instance_no; 459 int nregs; 460 int i = 0; 461 uint8_t irq; 462 uint16_t vendor_id; 463 uint16_t device_id; 464 uint16_t subsysvid; 465 uint16_t subsysid; 466 uint16_t command; 467 off_t reglength = 0; 468 int intr_types = 0; 469 char *data; 470 471 scsi_hba_tran_t *tran; 472 ddi_dma_attr_t tran_dma_attr; 473 struct mrsas_instance *instance; 474 475 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 476 477 /* CONSTCOND */ 478 ASSERT(NO_COMPETING_THREADS); 479 480 instance_no = ddi_get_instance(dip); 481 482 /* 483 * check to see whether this device is in a DMA-capable slot. 484 */ 485 if (ddi_slaveonly(dip) == DDI_SUCCESS) { 486 dev_err(dip, CE_WARN, "Device in slave-only slot, unused"); 487 return (DDI_FAILURE); 488 } 489 490 switch (cmd) { 491 case DDI_ATTACH: 492 /* allocate the soft state for the instance */ 493 if (ddi_soft_state_zalloc(mrsas_state, instance_no) 494 != DDI_SUCCESS) { 495 dev_err(dip, CE_WARN, "Failed to allocate soft state"); 496 return (DDI_FAILURE); 497 } 498 499 instance = (struct mrsas_instance *)ddi_get_soft_state 500 (mrsas_state, instance_no); 501 502 if (instance == NULL) { 503 dev_err(dip, CE_WARN, "Bad soft state"); 504 ddi_soft_state_free(mrsas_state, instance_no); 505 return (DDI_FAILURE); 506 } 507 508 instance->unroll.softs = 1; 509 510 /* Setup the PCI configuration space handles */ 511 if (pci_config_setup(dip, &instance->pci_handle) != 512 DDI_SUCCESS) { 513 dev_err(dip, CE_WARN, "pci config setup failed"); 514 515 ddi_soft_state_free(mrsas_state, instance_no); 516 return (DDI_FAILURE); 517 } 518 519 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) { 520 dev_err(dip, CE_WARN, "Failed to get registers"); 521 522 pci_config_teardown(&instance->pci_handle); 523 ddi_soft_state_free(mrsas_state, instance_no); 524 return (DDI_FAILURE); 525 } 526 527 vendor_id = pci_config_get16(instance->pci_handle, 528 PCI_CONF_VENID); 529 device_id = pci_config_get16(instance->pci_handle, 530 PCI_CONF_DEVID); 531 532 subsysvid = pci_config_get16(instance->pci_handle, 533 PCI_CONF_SUBVENID); 534 subsysid = pci_config_get16(instance->pci_handle, 535 PCI_CONF_SUBSYSID); 536 537 pci_config_put16(instance->pci_handle, PCI_CONF_COMM, 538 (pci_config_get16(instance->pci_handle, 539 PCI_CONF_COMM) | PCI_COMM_ME)); 540 irq = pci_config_get8(instance->pci_handle, 541 PCI_CONF_ILINE); 542 543 dev_err(dip, CE_CONT, 544 "?0x%x:0x%x 0x%x:0x%x, irq:%d drv-ver:%s\n", 545 vendor_id, device_id, subsysvid, 546 subsysid, irq, MRSAS_VERSION); 547 548 /* enable bus-mastering */ 549 command = pci_config_get16(instance->pci_handle, 550 PCI_CONF_COMM); 551 552 if (!(command & PCI_COMM_ME)) { 553 command |= PCI_COMM_ME; 554 555 pci_config_put16(instance->pci_handle, 556 PCI_CONF_COMM, command); 557 558 con_log(CL_ANN, (CE_CONT, "mr_sas%d: " 559 "enable bus-mastering", instance_no)); 560 } else { 561 con_log(CL_DLEVEL1, (CE_CONT, "mr_sas%d: " 562 "bus-mastering already set", instance_no)); 563 } 564 565 /* initialize function pointers */ 566 switch (device_id) { 567 case PCI_DEVICE_ID_LSI_TBOLT: 568 case PCI_DEVICE_ID_LSI_INVADER: 569 dev_err(dip, CE_CONT, "?TBOLT device detected\n"); 570 571 instance->func_ptr = 572 &mrsas_function_template_fusion; 573 instance->tbolt = 1; 574 break; 575 576 case PCI_DEVICE_ID_LSI_SKINNY: 577 case PCI_DEVICE_ID_LSI_SKINNY_NEW: 578 /* 579 * FALLTHRU to PPC-style functions, but mark this 580 * instance as Skinny, because the register set is 581 * slightly different (See WR_IB_PICK_QPORT), and 582 * certain other features are available to a Skinny 583 * HBA. 584 */ 585 instance->skinny = 1; 586 /* FALLTHRU */ 587 588 case PCI_DEVICE_ID_LSI_2108VDE: 589 case PCI_DEVICE_ID_LSI_2108V: 590 dev_err(dip, CE_CONT, 591 "?2108 Liberator device detected\n"); 592 593 instance->func_ptr = 594 &mrsas_function_template_ppc; 595 break; 596 597 default: 598 dev_err(dip, CE_WARN, "Invalid device detected"); 599 600 pci_config_teardown(&instance->pci_handle); 601 ddi_soft_state_free(mrsas_state, instance_no); 602 return (DDI_FAILURE); 603 } 604 605 instance->baseaddress = pci_config_get32( 606 instance->pci_handle, PCI_CONF_BASE0); 607 instance->baseaddress &= 0x0fffc; 608 609 instance->dip = dip; 610 instance->vendor_id = vendor_id; 611 instance->device_id = device_id; 612 instance->subsysvid = subsysvid; 613 instance->subsysid = subsysid; 614 instance->instance = instance_no; 615 616 /* Initialize FMA */ 617 instance->fm_capabilities = ddi_prop_get_int( 618 DDI_DEV_T_ANY, instance->dip, DDI_PROP_DONTPASS, 619 "fm-capable", DDI_FM_EREPORT_CAPABLE | 620 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE 621 | DDI_FM_ERRCB_CAPABLE); 622 623 mrsas_fm_init(instance); 624 625 /* Setup register map */ 626 if ((ddi_dev_regsize(instance->dip, 627 REGISTER_SET_IO_2108, ®length) != DDI_SUCCESS) || 628 reglength < MINIMUM_MFI_MEM_SZ) { 629 goto fail_attach; 630 } 631 if (reglength > DEFAULT_MFI_MEM_SZ) { 632 reglength = DEFAULT_MFI_MEM_SZ; 633 con_log(CL_DLEVEL1, (CE_NOTE, 634 "mr_sas: register length to map is 0x%lx bytes", 635 reglength)); 636 } 637 if (ddi_regs_map_setup(instance->dip, 638 REGISTER_SET_IO_2108, &instance->regmap, 0, 639 reglength, &endian_attr, &instance->regmap_handle) 640 != DDI_SUCCESS) { 641 dev_err(dip, CE_WARN, "couldn't map control registers"); 642 goto fail_attach; 643 } 644 645 instance->unroll.regs = 1; 646 647 /* 648 * Disable Interrupt Now. 649 * Setup Software interrupt 650 */ 651 instance->func_ptr->disable_intr(instance); 652 653 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 654 "mrsas-enable-msi", &data) == DDI_SUCCESS) { 655 if (strncmp(data, "no", 3) == 0) { 656 msi_enable = 0; 657 con_log(CL_ANN1, (CE_WARN, 658 "msi_enable = %d disabled", msi_enable)); 659 } 660 ddi_prop_free(data); 661 } 662 663 dev_err(dip, CE_CONT, "?msi_enable = %d\n", msi_enable); 664 665 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 666 "mrsas-enable-fp", &data) == DDI_SUCCESS) { 667 if (strncmp(data, "no", 3) == 0) { 668 enable_fp = 0; 669 dev_err(dip, CE_NOTE, 670 "enable_fp = %d, Fast-Path disabled.\n", 671 enable_fp); 672 } 673 674 ddi_prop_free(data); 675 } 676 677 dev_err(dip, CE_CONT, "?enable_fp = %d\n", enable_fp); 678 679 /* Check for all supported interrupt types */ 680 if (ddi_intr_get_supported_types( 681 dip, &intr_types) != DDI_SUCCESS) { 682 dev_err(dip, CE_WARN, 683 "ddi_intr_get_supported_types() failed"); 684 goto fail_attach; 685 } 686 687 con_log(CL_DLEVEL1, (CE_NOTE, 688 "ddi_intr_get_supported_types() ret: 0x%x", intr_types)); 689 690 /* Initialize and Setup Interrupt handler */ 691 if (msi_enable && (intr_types & DDI_INTR_TYPE_MSIX)) { 692 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSIX) != 693 DDI_SUCCESS) { 694 dev_err(dip, CE_WARN, 695 "MSIX interrupt query failed"); 696 goto fail_attach; 697 } 698 instance->intr_type = DDI_INTR_TYPE_MSIX; 699 } else if (msi_enable && (intr_types & DDI_INTR_TYPE_MSI)) { 700 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSI) != 701 DDI_SUCCESS) { 702 dev_err(dip, CE_WARN, 703 "MSI interrupt query failed"); 704 goto fail_attach; 705 } 706 instance->intr_type = DDI_INTR_TYPE_MSI; 707 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 708 msi_enable = 0; 709 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_FIXED) != 710 DDI_SUCCESS) { 711 dev_err(dip, CE_WARN, 712 "FIXED interrupt query failed"); 713 goto fail_attach; 714 } 715 instance->intr_type = DDI_INTR_TYPE_FIXED; 716 } else { 717 dev_err(dip, CE_WARN, "Device cannot " 718 "suppport either FIXED or MSI/X " 719 "interrupts"); 720 goto fail_attach; 721 } 722 723 instance->unroll.intr = 1; 724 725 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 726 "mrsas-enable-ctio", &data) == DDI_SUCCESS) { 727 if (strncmp(data, "no", 3) == 0) { 728 ctio_enable = 0; 729 con_log(CL_ANN1, (CE_WARN, 730 "ctio_enable = %d disabled", ctio_enable)); 731 } 732 ddi_prop_free(data); 733 } 734 735 dev_err(dip, CE_CONT, "?ctio_enable = %d\n", ctio_enable); 736 737 /* setup the mfi based low level driver */ 738 if (mrsas_init_adapter(instance) != DDI_SUCCESS) { 739 dev_err(dip, CE_WARN, 740 "could not initialize the low level driver"); 741 742 goto fail_attach; 743 } 744 745 /* Initialize all Mutex */ 746 INIT_LIST_HEAD(&instance->completed_pool_list); 747 mutex_init(&instance->completed_pool_mtx, NULL, 748 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 749 750 mutex_init(&instance->sync_map_mtx, NULL, 751 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 752 753 mutex_init(&instance->app_cmd_pool_mtx, NULL, 754 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 755 756 mutex_init(&instance->config_dev_mtx, NULL, 757 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 758 759 mutex_init(&instance->cmd_pend_mtx, NULL, 760 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 761 762 mutex_init(&instance->ocr_flags_mtx, NULL, 763 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 764 765 mutex_init(&instance->int_cmd_mtx, NULL, 766 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 767 cv_init(&instance->int_cmd_cv, NULL, CV_DRIVER, NULL); 768 769 mutex_init(&instance->cmd_pool_mtx, NULL, 770 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 771 772 mutex_init(&instance->reg_write_mtx, NULL, 773 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 774 775 if (instance->tbolt) { 776 mutex_init(&instance->cmd_app_pool_mtx, NULL, 777 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 778 779 mutex_init(&instance->chip_mtx, NULL, 780 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 781 782 } 783 784 instance->unroll.mutexs = 1; 785 786 instance->timeout_id = (timeout_id_t)-1; 787 788 /* Register our soft-isr for highlevel interrupts. */ 789 instance->isr_level = instance->intr_pri; 790 if (!(instance->tbolt)) { 791 if (instance->isr_level == HIGH_LEVEL_INTR) { 792 if (ddi_add_softintr(dip, 793 DDI_SOFTINT_HIGH, 794 &instance->soft_intr_id, NULL, NULL, 795 mrsas_softintr, (caddr_t)instance) != 796 DDI_SUCCESS) { 797 dev_err(dip, CE_WARN, 798 "Software ISR did not register"); 799 800 goto fail_attach; 801 } 802 803 instance->unroll.soft_isr = 1; 804 805 } 806 } 807 808 instance->softint_running = 0; 809 810 /* Allocate a transport structure */ 811 tran = scsi_hba_tran_alloc(dip, SCSI_HBA_CANSLEEP); 812 813 if (tran == NULL) { 814 dev_err(dip, CE_WARN, 815 "scsi_hba_tran_alloc failed"); 816 goto fail_attach; 817 } 818 819 instance->tran = tran; 820 instance->unroll.tran = 1; 821 822 tran->tran_hba_private = instance; 823 tran->tran_tgt_init = mrsas_tran_tgt_init; 824 tran->tran_tgt_probe = scsi_hba_probe; 825 tran->tran_tgt_free = mrsas_tran_tgt_free; 826 tran->tran_init_pkt = mrsas_tran_init_pkt; 827 if (instance->tbolt) 828 tran->tran_start = mrsas_tbolt_tran_start; 829 else 830 tran->tran_start = mrsas_tran_start; 831 tran->tran_abort = mrsas_tran_abort; 832 tran->tran_reset = mrsas_tran_reset; 833 tran->tran_getcap = mrsas_tran_getcap; 834 tran->tran_setcap = mrsas_tran_setcap; 835 tran->tran_destroy_pkt = mrsas_tran_destroy_pkt; 836 tran->tran_dmafree = mrsas_tran_dmafree; 837 tran->tran_sync_pkt = mrsas_tran_sync_pkt; 838 tran->tran_quiesce = mrsas_tran_quiesce; 839 tran->tran_unquiesce = mrsas_tran_unquiesce; 840 tran->tran_bus_config = mrsas_tran_bus_config; 841 842 if (mrsas_relaxed_ordering) 843 mrsas_generic_dma_attr.dma_attr_flags |= 844 DDI_DMA_RELAXED_ORDERING; 845 846 847 tran_dma_attr = mrsas_generic_dma_attr; 848 tran_dma_attr.dma_attr_sgllen = instance->max_num_sge; 849 850 /* Attach this instance of the hba */ 851 if (scsi_hba_attach_setup(dip, &tran_dma_attr, tran, 0) 852 != DDI_SUCCESS) { 853 dev_err(dip, CE_WARN, 854 "scsi_hba_attach failed"); 855 856 goto fail_attach; 857 } 858 instance->unroll.tranSetup = 1; 859 con_log(CL_ANN1, 860 (CE_CONT, "scsi_hba_attach_setup() done.")); 861 862 /* create devctl node for cfgadm command */ 863 if (ddi_create_minor_node(dip, "devctl", 864 S_IFCHR, INST2DEVCTL(instance_no), 865 DDI_NT_SCSI_NEXUS, 0) == DDI_FAILURE) { 866 dev_err(dip, CE_WARN, "failed to create devctl node."); 867 868 goto fail_attach; 869 } 870 871 instance->unroll.devctl = 1; 872 873 /* create scsi node for cfgadm command */ 874 if (ddi_create_minor_node(dip, "scsi", S_IFCHR, 875 INST2SCSI(instance_no), DDI_NT_SCSI_ATTACHMENT_POINT, 0) == 876 DDI_FAILURE) { 877 dev_err(dip, CE_WARN, "failed to create scsi node."); 878 879 goto fail_attach; 880 } 881 882 instance->unroll.scsictl = 1; 883 884 (void) sprintf(instance->iocnode, "%d:lsirdctl", instance_no); 885 886 /* 887 * Create a node for applications 888 * for issuing ioctl to the driver. 889 */ 890 if (ddi_create_minor_node(dip, instance->iocnode, 891 S_IFCHR, INST2LSIRDCTL(instance_no), DDI_PSEUDO, 0) == 892 DDI_FAILURE) { 893 dev_err(dip, CE_WARN, "failed to create ioctl node."); 894 895 goto fail_attach; 896 } 897 898 instance->unroll.ioctl = 1; 899 900 /* Create a taskq to handle dr events */ 901 if ((instance->taskq = ddi_taskq_create(dip, 902 "mrsas_dr_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 903 dev_err(dip, CE_WARN, "failed to create taskq."); 904 instance->taskq = NULL; 905 goto fail_attach; 906 } 907 instance->unroll.taskq = 1; 908 con_log(CL_ANN1, (CE_CONT, "ddi_taskq_create() done.")); 909 910 /* enable interrupt */ 911 instance->func_ptr->enable_intr(instance); 912 913 /* initiate AEN */ 914 if (start_mfi_aen(instance)) { 915 dev_err(dip, CE_WARN, "failed to initiate AEN."); 916 goto fail_attach; 917 } 918 instance->unroll.aenPend = 1; 919 con_log(CL_ANN1, 920 (CE_CONT, "AEN started for instance %d.", instance_no)); 921 922 /* Finally! We are on the air. */ 923 ddi_report_dev(dip); 924 925 /* FMA handle checking. */ 926 if (mrsas_check_acc_handle(instance->regmap_handle) != 927 DDI_SUCCESS) { 928 goto fail_attach; 929 } 930 if (mrsas_check_acc_handle(instance->pci_handle) != 931 DDI_SUCCESS) { 932 goto fail_attach; 933 } 934 935 instance->mr_ld_list = 936 kmem_zalloc(MRDRV_MAX_LD * sizeof (struct mrsas_ld), 937 KM_SLEEP); 938 instance->unroll.ldlist_buff = 1; 939 940 #ifdef PDSUPPORT 941 if (instance->tbolt || instance->skinny) { 942 instance->mr_tbolt_pd_max = MRSAS_TBOLT_PD_TGT_MAX; 943 instance->mr_tbolt_pd_list = 944 kmem_zalloc(MRSAS_TBOLT_GET_PD_MAX(instance) * 945 sizeof (struct mrsas_tbolt_pd), KM_SLEEP); 946 ASSERT(instance->mr_tbolt_pd_list); 947 for (i = 0; i < instance->mr_tbolt_pd_max; i++) { 948 instance->mr_tbolt_pd_list[i].lun_type = 949 MRSAS_TBOLT_PD_LUN; 950 instance->mr_tbolt_pd_list[i].dev_id = 951 (uint8_t)i; 952 } 953 954 instance->unroll.pdlist_buff = 1; 955 } 956 #endif 957 break; 958 case DDI_PM_RESUME: 959 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_PM_RESUME")); 960 break; 961 case DDI_RESUME: 962 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_RESUME")); 963 break; 964 default: 965 con_log(CL_ANN, 966 (CE_WARN, "mr_sas: invalid attach cmd=%x", cmd)); 967 return (DDI_FAILURE); 968 } 969 970 971 con_log(CL_DLEVEL1, 972 (CE_NOTE, "mrsas_attach() return SUCCESS instance_num %d", 973 instance_no)); 974 return (DDI_SUCCESS); 975 976 fail_attach: 977 978 mrsas_undo_resources(dip, instance); 979 980 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 981 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 982 983 mrsas_fm_fini(instance); 984 985 pci_config_teardown(&instance->pci_handle); 986 ddi_soft_state_free(mrsas_state, instance_no); 987 988 return (DDI_FAILURE); 989 } 990 991 /* 992 * getinfo - gets device information 993 * @dip: 994 * @cmd: 995 * @arg: 996 * @resultp: 997 * 998 * The system calls getinfo() to obtain configuration information that only 999 * the driver knows. The mapping of minor numbers to device instance is 1000 * entirely under the control of the driver. The system sometimes needs to ask 1001 * the driver which device a particular dev_t represents. 1002 * Given the device number return the devinfo pointer from the scsi_device 1003 * structure. 1004 */ 1005 /*ARGSUSED*/ 1006 static int 1007 mrsas_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **resultp) 1008 { 1009 int rval; 1010 int mrsas_minor = getminor((dev_t)arg); 1011 1012 struct mrsas_instance *instance; 1013 1014 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1015 1016 switch (cmd) { 1017 case DDI_INFO_DEVT2DEVINFO: 1018 instance = (struct mrsas_instance *) 1019 ddi_get_soft_state(mrsas_state, 1020 MINOR2INST(mrsas_minor)); 1021 1022 if (instance == NULL) { 1023 *resultp = NULL; 1024 rval = DDI_FAILURE; 1025 } else { 1026 *resultp = instance->dip; 1027 rval = DDI_SUCCESS; 1028 } 1029 break; 1030 case DDI_INFO_DEVT2INSTANCE: 1031 *resultp = (void *)(intptr_t) 1032 (MINOR2INST(getminor((dev_t)arg))); 1033 rval = DDI_SUCCESS; 1034 break; 1035 default: 1036 *resultp = NULL; 1037 rval = DDI_FAILURE; 1038 } 1039 1040 return (rval); 1041 } 1042 1043 /* 1044 * detach - detaches a device from the system 1045 * @dip: pointer to the device's dev_info structure 1046 * @cmd: type of detach 1047 * 1048 * A driver's detach() entry point is called to detach an instance of a device 1049 * that is bound to the driver. The entry point is called with the instance of 1050 * the device node to be detached and with DDI_DETACH, which is specified as 1051 * the cmd argument to the entry point. 1052 * This routine is called during driver unload. We free all the allocated 1053 * resources and call the corresponding LLD so that it can also release all 1054 * its resources. 1055 */ 1056 static int 1057 mrsas_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1058 { 1059 int instance_no; 1060 1061 struct mrsas_instance *instance; 1062 1063 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1064 1065 1066 /* CONSTCOND */ 1067 ASSERT(NO_COMPETING_THREADS); 1068 1069 instance_no = ddi_get_instance(dip); 1070 1071 instance = (struct mrsas_instance *)ddi_get_soft_state(mrsas_state, 1072 instance_no); 1073 1074 if (!instance) { 1075 dev_err(dip, CE_WARN, "could not get instance in detach"); 1076 1077 return (DDI_FAILURE); 1078 } 1079 1080 switch (cmd) { 1081 case DDI_DETACH: 1082 con_log(CL_ANN, (CE_NOTE, 1083 "mrsas_detach: DDI_DETACH")); 1084 1085 mutex_enter(&instance->config_dev_mtx); 1086 if (instance->timeout_id != (timeout_id_t)-1) { 1087 mutex_exit(&instance->config_dev_mtx); 1088 (void) untimeout(instance->timeout_id); 1089 instance->timeout_id = (timeout_id_t)-1; 1090 mutex_enter(&instance->config_dev_mtx); 1091 instance->unroll.timer = 0; 1092 } 1093 mutex_exit(&instance->config_dev_mtx); 1094 1095 if (instance->unroll.tranSetup == 1) { 1096 if (scsi_hba_detach(dip) != DDI_SUCCESS) { 1097 dev_err(dip, CE_WARN, 1098 "failed to detach"); 1099 return (DDI_FAILURE); 1100 } 1101 instance->unroll.tranSetup = 0; 1102 con_log(CL_ANN1, 1103 (CE_CONT, "scsi_hba_dettach() done.")); 1104 } 1105 1106 flush_cache(instance); 1107 1108 mrsas_undo_resources(dip, instance); 1109 1110 mrsas_fm_fini(instance); 1111 1112 pci_config_teardown(&instance->pci_handle); 1113 ddi_soft_state_free(mrsas_state, instance_no); 1114 break; 1115 1116 case DDI_PM_SUSPEND: 1117 con_log(CL_ANN, (CE_NOTE, 1118 "mrsas_detach: DDI_PM_SUSPEND")); 1119 1120 break; 1121 case DDI_SUSPEND: 1122 con_log(CL_ANN, (CE_NOTE, 1123 "mrsas_detach: DDI_SUSPEND")); 1124 1125 break; 1126 default: 1127 con_log(CL_ANN, (CE_WARN, 1128 "invalid detach command:0x%x", cmd)); 1129 return (DDI_FAILURE); 1130 } 1131 1132 return (DDI_SUCCESS); 1133 } 1134 1135 1136 static void 1137 mrsas_undo_resources(dev_info_t *dip, struct mrsas_instance *instance) 1138 { 1139 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1140 1141 if (instance->unroll.ioctl == 1) { 1142 ddi_remove_minor_node(dip, instance->iocnode); 1143 instance->unroll.ioctl = 0; 1144 } 1145 1146 if (instance->unroll.scsictl == 1) { 1147 ddi_remove_minor_node(dip, "scsi"); 1148 instance->unroll.scsictl = 0; 1149 } 1150 1151 if (instance->unroll.devctl == 1) { 1152 ddi_remove_minor_node(dip, "devctl"); 1153 instance->unroll.devctl = 0; 1154 } 1155 1156 if (instance->unroll.tranSetup == 1) { 1157 if (scsi_hba_detach(dip) != DDI_SUCCESS) { 1158 dev_err(dip, CE_WARN, "failed to detach"); 1159 return; /* DDI_FAILURE */ 1160 } 1161 instance->unroll.tranSetup = 0; 1162 con_log(CL_ANN1, (CE_CONT, "scsi_hba_dettach() done.")); 1163 } 1164 1165 if (instance->unroll.tran == 1) { 1166 scsi_hba_tran_free(instance->tran); 1167 instance->unroll.tran = 0; 1168 con_log(CL_ANN1, (CE_CONT, "scsi_hba_tran_free() done.")); 1169 } 1170 1171 if (instance->unroll.syncCmd == 1) { 1172 if (instance->tbolt) { 1173 if (abort_syncmap_cmd(instance, 1174 instance->map_update_cmd)) { 1175 dev_err(dip, CE_WARN, "mrsas_detach: " 1176 "failed to abort previous syncmap command"); 1177 } 1178 1179 instance->unroll.syncCmd = 0; 1180 con_log(CL_ANN1, (CE_CONT, "sync cmd aborted, done.")); 1181 } 1182 } 1183 1184 if (instance->unroll.aenPend == 1) { 1185 if (abort_aen_cmd(instance, instance->aen_cmd)) 1186 dev_err(dip, CE_WARN, "mrsas_detach: " 1187 "failed to abort prevous AEN command"); 1188 1189 instance->unroll.aenPend = 0; 1190 con_log(CL_ANN1, (CE_CONT, "aen cmd aborted, done.")); 1191 /* This means the controller is fully initialized and running */ 1192 /* Shutdown should be a last command to controller. */ 1193 /* shutdown_controller(); */ 1194 } 1195 1196 1197 if (instance->unroll.timer == 1) { 1198 if (instance->timeout_id != (timeout_id_t)-1) { 1199 (void) untimeout(instance->timeout_id); 1200 instance->timeout_id = (timeout_id_t)-1; 1201 1202 instance->unroll.timer = 0; 1203 } 1204 } 1205 1206 instance->func_ptr->disable_intr(instance); 1207 1208 1209 if (instance->unroll.mutexs == 1) { 1210 mutex_destroy(&instance->cmd_pool_mtx); 1211 mutex_destroy(&instance->app_cmd_pool_mtx); 1212 mutex_destroy(&instance->cmd_pend_mtx); 1213 mutex_destroy(&instance->completed_pool_mtx); 1214 mutex_destroy(&instance->sync_map_mtx); 1215 mutex_destroy(&instance->int_cmd_mtx); 1216 cv_destroy(&instance->int_cmd_cv); 1217 mutex_destroy(&instance->config_dev_mtx); 1218 mutex_destroy(&instance->ocr_flags_mtx); 1219 mutex_destroy(&instance->reg_write_mtx); 1220 1221 if (instance->tbolt) { 1222 mutex_destroy(&instance->cmd_app_pool_mtx); 1223 mutex_destroy(&instance->chip_mtx); 1224 } 1225 1226 instance->unroll.mutexs = 0; 1227 con_log(CL_ANN1, (CE_CONT, "Destroy mutex & cv, done.")); 1228 } 1229 1230 1231 if (instance->unroll.soft_isr == 1) { 1232 ddi_remove_softintr(instance->soft_intr_id); 1233 instance->unroll.soft_isr = 0; 1234 } 1235 1236 if (instance->unroll.intr == 1) { 1237 mrsas_rem_intrs(instance); 1238 instance->unroll.intr = 0; 1239 } 1240 1241 1242 if (instance->unroll.taskq == 1) { 1243 if (instance->taskq) { 1244 ddi_taskq_destroy(instance->taskq); 1245 instance->unroll.taskq = 0; 1246 } 1247 1248 } 1249 1250 /* 1251 * free dma memory allocated for 1252 * cmds/frames/queues/driver version etc 1253 */ 1254 if (instance->unroll.verBuff == 1) { 1255 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj); 1256 instance->unroll.verBuff = 0; 1257 } 1258 1259 if (instance->unroll.pdlist_buff == 1) { 1260 if (instance->mr_tbolt_pd_list != NULL) { 1261 kmem_free(instance->mr_tbolt_pd_list, 1262 MRSAS_TBOLT_GET_PD_MAX(instance) * 1263 sizeof (struct mrsas_tbolt_pd)); 1264 } 1265 1266 instance->mr_tbolt_pd_list = NULL; 1267 instance->unroll.pdlist_buff = 0; 1268 } 1269 1270 if (instance->unroll.ldlist_buff == 1) { 1271 if (instance->mr_ld_list != NULL) { 1272 kmem_free(instance->mr_ld_list, MRDRV_MAX_LD 1273 * sizeof (struct mrsas_ld)); 1274 } 1275 1276 instance->mr_ld_list = NULL; 1277 instance->unroll.ldlist_buff = 0; 1278 } 1279 1280 if (instance->tbolt) { 1281 if (instance->unroll.alloc_space_mpi2 == 1) { 1282 free_space_for_mpi2(instance); 1283 instance->unroll.alloc_space_mpi2 = 0; 1284 } 1285 } else { 1286 if (instance->unroll.alloc_space_mfi == 1) { 1287 free_space_for_mfi(instance); 1288 instance->unroll.alloc_space_mfi = 0; 1289 } 1290 } 1291 1292 if (instance->unroll.regs == 1) { 1293 ddi_regs_map_free(&instance->regmap_handle); 1294 instance->unroll.regs = 0; 1295 con_log(CL_ANN1, (CE_CONT, "ddi_regs_map_free() done.")); 1296 } 1297 } 1298 1299 1300 1301 /* 1302 * ************************************************************************** * 1303 * * 1304 * common entry points - for character driver types * 1305 * * 1306 * ************************************************************************** * 1307 */ 1308 /* 1309 * open - gets access to a device 1310 * @dev: 1311 * @openflags: 1312 * @otyp: 1313 * @credp: 1314 * 1315 * Access to a device by one or more application programs is controlled 1316 * through the open() and close() entry points. The primary function of 1317 * open() is to verify that the open request is allowed. 1318 */ 1319 static int 1320 mrsas_open(dev_t *dev, int openflags, int otyp, cred_t *credp) 1321 { 1322 int rval = 0; 1323 1324 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1325 1326 /* Check root permissions */ 1327 if (drv_priv(credp) != 0) { 1328 con_log(CL_ANN, (CE_WARN, 1329 "mr_sas: Non-root ioctl access denied!")); 1330 return (EPERM); 1331 } 1332 1333 /* Verify we are being opened as a character device */ 1334 if (otyp != OTYP_CHR) { 1335 con_log(CL_ANN, (CE_WARN, 1336 "mr_sas: ioctl node must be a char node")); 1337 return (EINVAL); 1338 } 1339 1340 if (ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(*dev))) 1341 == NULL) { 1342 return (ENXIO); 1343 } 1344 1345 if (scsi_hba_open) { 1346 rval = scsi_hba_open(dev, openflags, otyp, credp); 1347 } 1348 1349 return (rval); 1350 } 1351 1352 /* 1353 * close - gives up access to a device 1354 * @dev: 1355 * @openflags: 1356 * @otyp: 1357 * @credp: 1358 * 1359 * close() should perform any cleanup necessary to finish using the minor 1360 * device, and prepare the device (and driver) to be opened again. 1361 */ 1362 static int 1363 mrsas_close(dev_t dev, int openflags, int otyp, cred_t *credp) 1364 { 1365 int rval = 0; 1366 1367 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1368 1369 /* no need for locks! */ 1370 1371 if (scsi_hba_close) { 1372 rval = scsi_hba_close(dev, openflags, otyp, credp); 1373 } 1374 1375 return (rval); 1376 } 1377 1378 /* 1379 * ioctl - performs a range of I/O commands for character drivers 1380 * @dev: 1381 * @cmd: 1382 * @arg: 1383 * @mode: 1384 * @credp: 1385 * @rvalp: 1386 * 1387 * ioctl() routine must make sure that user data is copied into or out of the 1388 * kernel address space explicitly using copyin(), copyout(), ddi_copyin(), 1389 * and ddi_copyout(), as appropriate. 1390 * This is a wrapper routine to serialize access to the actual ioctl routine. 1391 * ioctl() should return 0 on success, or the appropriate error number. The 1392 * driver may also set the value returned to the calling process through rvalp. 1393 */ 1394 1395 static int 1396 mrsas_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1397 int *rvalp) 1398 { 1399 int rval = 0; 1400 1401 struct mrsas_instance *instance; 1402 struct mrsas_ioctl *ioctl; 1403 struct mrsas_aen aen; 1404 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1405 1406 instance = ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(dev))); 1407 1408 if (instance == NULL) { 1409 /* invalid minor number */ 1410 con_log(CL_ANN, (CE_WARN, "mr_sas: adapter not found.")); 1411 return (ENXIO); 1412 } 1413 1414 ioctl = (struct mrsas_ioctl *)kmem_zalloc(sizeof (struct mrsas_ioctl), 1415 KM_SLEEP); 1416 ASSERT(ioctl); 1417 1418 switch ((uint_t)cmd) { 1419 case MRSAS_IOCTL_FIRMWARE: 1420 if (ddi_copyin((void *)arg, ioctl, 1421 sizeof (struct mrsas_ioctl), mode)) { 1422 con_log(CL_ANN, (CE_WARN, "mrsas_ioctl: " 1423 "ERROR IOCTL copyin")); 1424 kmem_free(ioctl, sizeof (struct mrsas_ioctl)); 1425 return (EFAULT); 1426 } 1427 1428 if (ioctl->control_code == MRSAS_DRIVER_IOCTL_COMMON) { 1429 rval = handle_drv_ioctl(instance, ioctl, mode); 1430 } else { 1431 rval = handle_mfi_ioctl(instance, ioctl, mode); 1432 } 1433 1434 if (ddi_copyout((void *)ioctl, (void *)arg, 1435 (sizeof (struct mrsas_ioctl) - 1), mode)) { 1436 con_log(CL_ANN, (CE_WARN, 1437 "mrsas_ioctl: copy_to_user failed")); 1438 rval = 1; 1439 } 1440 1441 break; 1442 case MRSAS_IOCTL_AEN: 1443 if (ddi_copyin((void *) arg, &aen, 1444 sizeof (struct mrsas_aen), mode)) { 1445 con_log(CL_ANN, (CE_WARN, 1446 "mrsas_ioctl: ERROR AEN copyin")); 1447 kmem_free(ioctl, sizeof (struct mrsas_ioctl)); 1448 return (EFAULT); 1449 } 1450 1451 rval = handle_mfi_aen(instance, &aen); 1452 1453 if (ddi_copyout((void *) &aen, (void *)arg, 1454 sizeof (struct mrsas_aen), mode)) { 1455 con_log(CL_ANN, (CE_WARN, 1456 "mrsas_ioctl: copy_to_user failed")); 1457 rval = 1; 1458 } 1459 1460 break; 1461 default: 1462 rval = scsi_hba_ioctl(dev, cmd, arg, 1463 mode, credp, rvalp); 1464 1465 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_ioctl: " 1466 "scsi_hba_ioctl called, ret = %x.", rval)); 1467 } 1468 1469 kmem_free(ioctl, sizeof (struct mrsas_ioctl)); 1470 return (rval); 1471 } 1472 1473 /* 1474 * ************************************************************************** * 1475 * * 1476 * common entry points - for block driver types * 1477 * * 1478 * ************************************************************************** * 1479 */ 1480 #ifdef __sparc 1481 /* 1482 * reset - TBD 1483 * @dip: 1484 * @cmd: 1485 * 1486 * TBD 1487 */ 1488 /*ARGSUSED*/ 1489 static int 1490 mrsas_reset(dev_info_t *dip, ddi_reset_cmd_t cmd) 1491 { 1492 int instance_no; 1493 1494 struct mrsas_instance *instance; 1495 1496 instance_no = ddi_get_instance(dip); 1497 instance = (struct mrsas_instance *)ddi_get_soft_state 1498 (mrsas_state, instance_no); 1499 1500 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1501 1502 if (!instance) { 1503 con_log(CL_ANN, (CE_WARN, "mr_sas:%d could not get adapter " 1504 "in reset", instance_no)); 1505 return (DDI_FAILURE); 1506 } 1507 1508 instance->func_ptr->disable_intr(instance); 1509 1510 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d", 1511 instance_no)); 1512 1513 flush_cache(instance); 1514 1515 return (DDI_SUCCESS); 1516 } 1517 #else /* __sparc */ 1518 /*ARGSUSED*/ 1519 static int 1520 mrsas_quiesce(dev_info_t *dip) 1521 { 1522 int instance_no; 1523 1524 struct mrsas_instance *instance; 1525 1526 instance_no = ddi_get_instance(dip); 1527 instance = (struct mrsas_instance *)ddi_get_soft_state 1528 (mrsas_state, instance_no); 1529 1530 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1531 1532 if (!instance) { 1533 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d could not get adapter " 1534 "in quiesce", instance_no)); 1535 return (DDI_FAILURE); 1536 } 1537 if (instance->deadadapter || instance->adapterresetinprogress) { 1538 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d adapter is not in " 1539 "healthy state", instance_no)); 1540 return (DDI_FAILURE); 1541 } 1542 1543 if (abort_aen_cmd(instance, instance->aen_cmd)) { 1544 con_log(CL_ANN1, (CE_WARN, "mrsas_quiesce: " 1545 "failed to abort prevous AEN command QUIESCE")); 1546 } 1547 1548 if (instance->tbolt) { 1549 if (abort_syncmap_cmd(instance, 1550 instance->map_update_cmd)) { 1551 dev_err(dip, CE_WARN, 1552 "mrsas_detach: failed to abort " 1553 "previous syncmap command"); 1554 return (DDI_FAILURE); 1555 } 1556 } 1557 1558 instance->func_ptr->disable_intr(instance); 1559 1560 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d", 1561 instance_no)); 1562 1563 flush_cache(instance); 1564 1565 if (wait_for_outstanding(instance)) { 1566 con_log(CL_ANN1, 1567 (CE_CONT, "wait_for_outstanding: return FAIL.\n")); 1568 return (DDI_FAILURE); 1569 } 1570 return (DDI_SUCCESS); 1571 } 1572 #endif /* __sparc */ 1573 1574 /* 1575 * ************************************************************************** * 1576 * * 1577 * entry points (SCSI HBA) * 1578 * * 1579 * ************************************************************************** * 1580 */ 1581 /* 1582 * tran_tgt_init - initialize a target device instance 1583 * @hba_dip: 1584 * @tgt_dip: 1585 * @tran: 1586 * @sd: 1587 * 1588 * The tran_tgt_init() entry point enables the HBA to allocate and initialize 1589 * any per-target resources. tran_tgt_init() also enables the HBA to qualify 1590 * the device's address as valid and supportable for that particular HBA. 1591 * By returning DDI_FAILURE, the instance of the target driver for that device 1592 * is not probed or attached. 1593 */ 1594 /*ARGSUSED*/ 1595 static int 1596 mrsas_tran_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 1597 scsi_hba_tran_t *tran, struct scsi_device *sd) 1598 { 1599 struct mrsas_instance *instance; 1600 uint16_t tgt = sd->sd_address.a_target; 1601 uint8_t lun = sd->sd_address.a_lun; 1602 dev_info_t *child = NULL; 1603 1604 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init target %d lun %d", 1605 tgt, lun)); 1606 1607 instance = ADDR2MR(&sd->sd_address); 1608 1609 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 1610 /* 1611 * If no persistent node exists, we don't allow .conf node 1612 * to be created. 1613 */ 1614 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) { 1615 con_log(CL_DLEVEL2, 1616 (CE_NOTE, "mrsas_tgt_init find child =" 1617 " %p t = %d l = %d", (void *)child, tgt, lun)); 1618 if (ndi_merge_node(tgt_dip, mrsas_name_node) != 1619 DDI_SUCCESS) 1620 /* Create this .conf node */ 1621 return (DDI_SUCCESS); 1622 } 1623 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init in ndi_per " 1624 "DDI_FAILURE t = %d l = %d", tgt, lun)); 1625 return (DDI_FAILURE); 1626 1627 } 1628 1629 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init dev_dip %p tgt_dip %p", 1630 (void *)instance->mr_ld_list[tgt].dip, (void *)tgt_dip)); 1631 1632 if (tgt < MRDRV_MAX_LD && lun == 0) { 1633 if (instance->mr_ld_list[tgt].dip == NULL && 1634 strcmp(ddi_driver_name(sd->sd_dev), "sd") == 0) { 1635 mutex_enter(&instance->config_dev_mtx); 1636 instance->mr_ld_list[tgt].dip = tgt_dip; 1637 instance->mr_ld_list[tgt].lun_type = MRSAS_LD_LUN; 1638 instance->mr_ld_list[tgt].flag = MRDRV_TGT_VALID; 1639 mutex_exit(&instance->config_dev_mtx); 1640 } 1641 } 1642 1643 #ifdef PDSUPPORT 1644 else if (instance->tbolt || instance->skinny) { 1645 if (instance->mr_tbolt_pd_list[tgt].dip == NULL) { 1646 mutex_enter(&instance->config_dev_mtx); 1647 instance->mr_tbolt_pd_list[tgt].dip = tgt_dip; 1648 instance->mr_tbolt_pd_list[tgt].flag = 1649 MRDRV_TGT_VALID; 1650 mutex_exit(&instance->config_dev_mtx); 1651 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_tgt_init:" 1652 "t%xl%x", tgt, lun)); 1653 } 1654 } 1655 #endif 1656 1657 return (DDI_SUCCESS); 1658 } 1659 1660 /*ARGSUSED*/ 1661 static void 1662 mrsas_tran_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 1663 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 1664 { 1665 struct mrsas_instance *instance; 1666 int tgt = sd->sd_address.a_target; 1667 int lun = sd->sd_address.a_lun; 1668 1669 instance = ADDR2MR(&sd->sd_address); 1670 1671 con_log(CL_DLEVEL2, (CE_NOTE, "tgt_free t = %d l = %d", tgt, lun)); 1672 1673 if (tgt < MRDRV_MAX_LD && lun == 0) { 1674 if (instance->mr_ld_list[tgt].dip == tgt_dip) { 1675 mutex_enter(&instance->config_dev_mtx); 1676 instance->mr_ld_list[tgt].dip = NULL; 1677 mutex_exit(&instance->config_dev_mtx); 1678 } 1679 } 1680 1681 #ifdef PDSUPPORT 1682 else if (instance->tbolt || instance->skinny) { 1683 mutex_enter(&instance->config_dev_mtx); 1684 instance->mr_tbolt_pd_list[tgt].dip = NULL; 1685 mutex_exit(&instance->config_dev_mtx); 1686 con_log(CL_ANN1, (CE_NOTE, "tgt_free: Setting dip = NULL" 1687 "for tgt:%x", tgt)); 1688 } 1689 #endif 1690 1691 } 1692 1693 dev_info_t * 1694 mrsas_find_child(struct mrsas_instance *instance, uint16_t tgt, uint8_t lun) 1695 { 1696 dev_info_t *child = NULL; 1697 char addr[SCSI_MAXNAMELEN]; 1698 char tmp[MAXNAMELEN]; 1699 1700 (void) sprintf(addr, "%x,%x", tgt, lun); 1701 for (child = ddi_get_child(instance->dip); child; 1702 child = ddi_get_next_sibling(child)) { 1703 1704 if (ndi_dev_is_persistent_node(child) == 0) { 1705 continue; 1706 } 1707 1708 if (mrsas_name_node(child, tmp, MAXNAMELEN) != 1709 DDI_SUCCESS) { 1710 continue; 1711 } 1712 1713 if (strcmp(addr, tmp) == 0) { 1714 break; 1715 } 1716 } 1717 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_find_child: return child = %p", 1718 (void *)child)); 1719 return (child); 1720 } 1721 1722 /* 1723 * mrsas_name_node - 1724 * @dip: 1725 * @name: 1726 * @len: 1727 */ 1728 static int 1729 mrsas_name_node(dev_info_t *dip, char *name, int len) 1730 { 1731 int tgt, lun; 1732 1733 tgt = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1734 DDI_PROP_DONTPASS, "target", -1); 1735 con_log(CL_DLEVEL2, (CE_NOTE, 1736 "mrsas_name_node: dip %p tgt %d", (void *)dip, tgt)); 1737 if (tgt == -1) { 1738 return (DDI_FAILURE); 1739 } 1740 lun = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1741 "lun", -1); 1742 con_log(CL_DLEVEL2, 1743 (CE_NOTE, "mrsas_name_node: tgt %d lun %d", tgt, lun)); 1744 if (lun == -1) { 1745 return (DDI_FAILURE); 1746 } 1747 (void) snprintf(name, len, "%x,%x", tgt, lun); 1748 return (DDI_SUCCESS); 1749 } 1750 1751 /* 1752 * tran_init_pkt - allocate & initialize a scsi_pkt structure 1753 * @ap: 1754 * @pkt: 1755 * @bp: 1756 * @cmdlen: 1757 * @statuslen: 1758 * @tgtlen: 1759 * @flags: 1760 * @callback: 1761 * 1762 * The tran_init_pkt() entry point allocates and initializes a scsi_pkt 1763 * structure and DMA resources for a target driver request. The 1764 * tran_init_pkt() entry point is called when the target driver calls the 1765 * SCSA function scsi_init_pkt(). Each call of the tran_init_pkt() entry point 1766 * is a request to perform one or more of three possible services: 1767 * - allocation and initialization of a scsi_pkt structure 1768 * - allocation of DMA resources for data transfer 1769 * - reallocation of DMA resources for the next portion of the data transfer 1770 */ 1771 static struct scsi_pkt * 1772 mrsas_tran_init_pkt(struct scsi_address *ap, register struct scsi_pkt *pkt, 1773 struct buf *bp, int cmdlen, int statuslen, int tgtlen, 1774 int flags, int (*callback)(), caddr_t arg) 1775 { 1776 struct scsa_cmd *acmd; 1777 struct mrsas_instance *instance; 1778 struct scsi_pkt *new_pkt; 1779 1780 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1781 1782 instance = ADDR2MR(ap); 1783 1784 /* step #1 : pkt allocation */ 1785 if (pkt == NULL) { 1786 pkt = scsi_hba_pkt_alloc(instance->dip, ap, cmdlen, statuslen, 1787 tgtlen, sizeof (struct scsa_cmd), callback, arg); 1788 if (pkt == NULL) { 1789 return (NULL); 1790 } 1791 1792 acmd = PKT2CMD(pkt); 1793 1794 /* 1795 * Initialize the new pkt - we redundantly initialize 1796 * all the fields for illustrative purposes. 1797 */ 1798 acmd->cmd_pkt = pkt; 1799 acmd->cmd_flags = 0; 1800 acmd->cmd_scblen = statuslen; 1801 acmd->cmd_cdblen = cmdlen; 1802 acmd->cmd_dmahandle = NULL; 1803 acmd->cmd_ncookies = 0; 1804 acmd->cmd_cookie = 0; 1805 acmd->cmd_cookiecnt = 0; 1806 acmd->cmd_nwin = 0; 1807 1808 pkt->pkt_address = *ap; 1809 pkt->pkt_comp = (void (*)())NULL; 1810 pkt->pkt_flags = 0; 1811 pkt->pkt_time = 0; 1812 pkt->pkt_resid = 0; 1813 pkt->pkt_state = 0; 1814 pkt->pkt_statistics = 0; 1815 pkt->pkt_reason = 0; 1816 new_pkt = pkt; 1817 } else { 1818 acmd = PKT2CMD(pkt); 1819 new_pkt = NULL; 1820 } 1821 1822 /* step #2 : dma allocation/move */ 1823 if (bp && bp->b_bcount != 0) { 1824 if (acmd->cmd_dmahandle == NULL) { 1825 if (mrsas_dma_alloc(instance, pkt, bp, flags, 1826 callback) == DDI_FAILURE) { 1827 if (new_pkt) { 1828 scsi_hba_pkt_free(ap, new_pkt); 1829 } 1830 return ((struct scsi_pkt *)NULL); 1831 } 1832 } else { 1833 if (mrsas_dma_move(instance, pkt, bp) == DDI_FAILURE) { 1834 return ((struct scsi_pkt *)NULL); 1835 } 1836 } 1837 } 1838 1839 return (pkt); 1840 } 1841 1842 /* 1843 * tran_start - transport a SCSI command to the addressed target 1844 * @ap: 1845 * @pkt: 1846 * 1847 * The tran_start() entry point for a SCSI HBA driver is called to transport a 1848 * SCSI command to the addressed target. The SCSI command is described 1849 * entirely within the scsi_pkt structure, which the target driver allocated 1850 * through the HBA driver's tran_init_pkt() entry point. If the command 1851 * involves a data transfer, DMA resources must also have been allocated for 1852 * the scsi_pkt structure. 1853 * 1854 * Return Values : 1855 * TRAN_BUSY - request queue is full, no more free scbs 1856 * TRAN_ACCEPT - pkt has been submitted to the instance 1857 */ 1858 static int 1859 mrsas_tran_start(struct scsi_address *ap, register struct scsi_pkt *pkt) 1860 { 1861 uchar_t cmd_done = 0; 1862 1863 struct mrsas_instance *instance = ADDR2MR(ap); 1864 struct mrsas_cmd *cmd; 1865 1866 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1867 if (instance->deadadapter == 1) { 1868 con_log(CL_ANN1, (CE_WARN, 1869 "mrsas_tran_start: return TRAN_FATAL_ERROR " 1870 "for IO, as the HBA doesnt take any more IOs")); 1871 if (pkt) { 1872 pkt->pkt_reason = CMD_DEV_GONE; 1873 pkt->pkt_statistics = STAT_DISCON; 1874 } 1875 return (TRAN_FATAL_ERROR); 1876 } 1877 1878 if (instance->adapterresetinprogress) { 1879 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_start: Reset flag set, " 1880 "returning mfi_pkt and setting TRAN_BUSY\n")); 1881 return (TRAN_BUSY); 1882 } 1883 1884 con_log(CL_ANN1, (CE_CONT, "chkpnt:%s:%d:SCSI CDB[0]=0x%x time:%x", 1885 __func__, __LINE__, pkt->pkt_cdbp[0], pkt->pkt_time)); 1886 1887 pkt->pkt_reason = CMD_CMPLT; 1888 *pkt->pkt_scbp = STATUS_GOOD; /* clear arq scsi_status */ 1889 1890 cmd = build_cmd(instance, ap, pkt, &cmd_done); 1891 1892 /* 1893 * Check if the command is already completed by the mrsas_build_cmd() 1894 * routine. In which case the busy_flag would be clear and scb will be 1895 * NULL and appropriate reason provided in pkt_reason field 1896 */ 1897 if (cmd_done) { 1898 pkt->pkt_reason = CMD_CMPLT; 1899 pkt->pkt_scbp[0] = STATUS_GOOD; 1900 pkt->pkt_state |= STATE_GOT_BUS | STATE_GOT_TARGET 1901 | STATE_SENT_CMD; 1902 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && pkt->pkt_comp) { 1903 (*pkt->pkt_comp)(pkt); 1904 } 1905 1906 return (TRAN_ACCEPT); 1907 } 1908 1909 if (cmd == NULL) { 1910 return (TRAN_BUSY); 1911 } 1912 1913 if ((pkt->pkt_flags & FLAG_NOINTR) == 0) { 1914 if (instance->fw_outstanding > instance->max_fw_cmds) { 1915 con_log(CL_ANN, (CE_CONT, "mr_sas:Firmware busy")); 1916 DTRACE_PROBE2(start_tran_err, 1917 uint16_t, instance->fw_outstanding, 1918 uint16_t, instance->max_fw_cmds); 1919 mrsas_return_mfi_pkt(instance, cmd); 1920 return (TRAN_BUSY); 1921 } 1922 1923 /* Synchronize the Cmd frame for the controller */ 1924 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0, 1925 DDI_DMA_SYNC_FORDEV); 1926 con_log(CL_ANN, (CE_CONT, "issue_cmd_ppc: SCSI CDB[0]=0x%x" 1927 "cmd->index:%x\n", pkt->pkt_cdbp[0], cmd->index)); 1928 instance->func_ptr->issue_cmd(cmd, instance); 1929 1930 } else { 1931 struct mrsas_header *hdr = &cmd->frame->hdr; 1932 1933 instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd); 1934 1935 pkt->pkt_reason = CMD_CMPLT; 1936 pkt->pkt_statistics = 0; 1937 pkt->pkt_state |= STATE_XFERRED_DATA | STATE_GOT_STATUS; 1938 1939 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, 1940 &hdr->cmd_status)) { 1941 case MFI_STAT_OK: 1942 pkt->pkt_scbp[0] = STATUS_GOOD; 1943 break; 1944 1945 case MFI_STAT_SCSI_DONE_WITH_ERROR: 1946 con_log(CL_ANN, (CE_CONT, 1947 "mrsas_tran_start: scsi done with error")); 1948 pkt->pkt_reason = CMD_CMPLT; 1949 pkt->pkt_statistics = 0; 1950 1951 ((struct scsi_status *)pkt->pkt_scbp)->sts_chk = 1; 1952 break; 1953 1954 case MFI_STAT_DEVICE_NOT_FOUND: 1955 con_log(CL_ANN, (CE_CONT, 1956 "mrsas_tran_start: device not found error")); 1957 pkt->pkt_reason = CMD_DEV_GONE; 1958 pkt->pkt_statistics = STAT_DISCON; 1959 break; 1960 1961 default: 1962 ((struct scsi_status *)pkt->pkt_scbp)->sts_busy = 1; 1963 } 1964 1965 (void) mrsas_common_check(instance, cmd); 1966 DTRACE_PROBE2(start_nointr_done, uint8_t, hdr->cmd, 1967 uint8_t, hdr->cmd_status); 1968 mrsas_return_mfi_pkt(instance, cmd); 1969 1970 if (pkt->pkt_comp) { 1971 (*pkt->pkt_comp)(pkt); 1972 } 1973 1974 } 1975 1976 return (TRAN_ACCEPT); 1977 } 1978 1979 /* 1980 * tran_abort - Abort any commands that are currently in transport 1981 * @ap: 1982 * @pkt: 1983 * 1984 * The tran_abort() entry point for a SCSI HBA driver is called to abort any 1985 * commands that are currently in transport for a particular target. This entry 1986 * point is called when a target driver calls scsi_abort(). The tran_abort() 1987 * entry point should attempt to abort the command denoted by the pkt 1988 * parameter. If the pkt parameter is NULL, tran_abort() should attempt to 1989 * abort all outstanding commands in the transport layer for the particular 1990 * target or logical unit. 1991 */ 1992 /*ARGSUSED*/ 1993 static int 1994 mrsas_tran_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 1995 { 1996 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1997 1998 /* abort command not supported by H/W */ 1999 2000 return (DDI_FAILURE); 2001 } 2002 2003 /* 2004 * tran_reset - reset either the SCSI bus or target 2005 * @ap: 2006 * @level: 2007 * 2008 * The tran_reset() entry point for a SCSI HBA driver is called to reset either 2009 * the SCSI bus or a particular SCSI target device. This entry point is called 2010 * when a target driver calls scsi_reset(). The tran_reset() entry point must 2011 * reset the SCSI bus if level is RESET_ALL. If level is RESET_TARGET, just the 2012 * particular target or logical unit must be reset. 2013 */ 2014 /*ARGSUSED*/ 2015 static int 2016 mrsas_tran_reset(struct scsi_address *ap, int level) 2017 { 2018 struct mrsas_instance *instance = ADDR2MR(ap); 2019 2020 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2021 2022 if (wait_for_outstanding(instance)) { 2023 con_log(CL_ANN1, 2024 (CE_CONT, "wait_for_outstanding: return FAIL.\n")); 2025 return (DDI_FAILURE); 2026 } else { 2027 return (DDI_SUCCESS); 2028 } 2029 } 2030 2031 /* 2032 * tran_getcap - get one of a set of SCSA-defined capabilities 2033 * @ap: 2034 * @cap: 2035 * @whom: 2036 * 2037 * The target driver can request the current setting of the capability for a 2038 * particular target by setting the whom parameter to nonzero. A whom value of 2039 * zero indicates a request for the current setting of the general capability 2040 * for the SCSI bus or for adapter hardware. The tran_getcap() should return -1 2041 * for undefined capabilities or the current value of the requested capability. 2042 */ 2043 /*ARGSUSED*/ 2044 static int 2045 mrsas_tran_getcap(struct scsi_address *ap, char *cap, int whom) 2046 { 2047 int rval = 0; 2048 2049 struct mrsas_instance *instance = ADDR2MR(ap); 2050 2051 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2052 2053 /* we do allow inquiring about capabilities for other targets */ 2054 if (cap == NULL) { 2055 return (-1); 2056 } 2057 2058 switch (scsi_hba_lookup_capstr(cap)) { 2059 case SCSI_CAP_DMA_MAX: 2060 if (instance->tbolt) { 2061 /* Limit to 256k max transfer */ 2062 rval = mrsas_tbolt_max_cap_maxxfer; 2063 } else { 2064 /* Limit to 16MB max transfer */ 2065 rval = mrsas_max_cap_maxxfer; 2066 } 2067 break; 2068 case SCSI_CAP_MSG_OUT: 2069 rval = 1; 2070 break; 2071 case SCSI_CAP_DISCONNECT: 2072 rval = 0; 2073 break; 2074 case SCSI_CAP_SYNCHRONOUS: 2075 rval = 0; 2076 break; 2077 case SCSI_CAP_WIDE_XFER: 2078 rval = 1; 2079 break; 2080 case SCSI_CAP_TAGGED_QING: 2081 rval = 1; 2082 break; 2083 case SCSI_CAP_UNTAGGED_QING: 2084 rval = 1; 2085 break; 2086 case SCSI_CAP_PARITY: 2087 rval = 1; 2088 break; 2089 case SCSI_CAP_INITIATOR_ID: 2090 rval = instance->init_id; 2091 break; 2092 case SCSI_CAP_ARQ: 2093 rval = 1; 2094 break; 2095 case SCSI_CAP_LINKED_CMDS: 2096 rval = 0; 2097 break; 2098 case SCSI_CAP_RESET_NOTIFICATION: 2099 rval = 1; 2100 break; 2101 case SCSI_CAP_GEOMETRY: 2102 rval = -1; 2103 2104 break; 2105 default: 2106 con_log(CL_DLEVEL2, (CE_NOTE, "Default cap coming 0x%x", 2107 scsi_hba_lookup_capstr(cap))); 2108 rval = -1; 2109 break; 2110 } 2111 2112 return (rval); 2113 } 2114 2115 /* 2116 * tran_setcap - set one of a set of SCSA-defined capabilities 2117 * @ap: 2118 * @cap: 2119 * @value: 2120 * @whom: 2121 * 2122 * The target driver might request that the new value be set for a particular 2123 * target by setting the whom parameter to nonzero. A whom value of zero 2124 * means that request is to set the new value for the SCSI bus or for adapter 2125 * hardware in general. 2126 * The tran_setcap() should return the following values as appropriate: 2127 * - -1 for undefined capabilities 2128 * - 0 if the HBA driver cannot set the capability to the requested value 2129 * - 1 if the HBA driver is able to set the capability to the requested value 2130 */ 2131 /*ARGSUSED*/ 2132 static int 2133 mrsas_tran_setcap(struct scsi_address *ap, char *cap, int value, int whom) 2134 { 2135 int rval = 1; 2136 2137 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2138 2139 /* We don't allow setting capabilities for other targets */ 2140 if (cap == NULL || whom == 0) { 2141 return (-1); 2142 } 2143 2144 switch (scsi_hba_lookup_capstr(cap)) { 2145 case SCSI_CAP_DMA_MAX: 2146 case SCSI_CAP_MSG_OUT: 2147 case SCSI_CAP_PARITY: 2148 case SCSI_CAP_LINKED_CMDS: 2149 case SCSI_CAP_RESET_NOTIFICATION: 2150 case SCSI_CAP_DISCONNECT: 2151 case SCSI_CAP_SYNCHRONOUS: 2152 case SCSI_CAP_UNTAGGED_QING: 2153 case SCSI_CAP_WIDE_XFER: 2154 case SCSI_CAP_INITIATOR_ID: 2155 case SCSI_CAP_ARQ: 2156 /* 2157 * None of these are settable via 2158 * the capability interface. 2159 */ 2160 break; 2161 case SCSI_CAP_TAGGED_QING: 2162 rval = 1; 2163 break; 2164 case SCSI_CAP_SECTOR_SIZE: 2165 rval = 1; 2166 break; 2167 2168 case SCSI_CAP_TOTAL_SECTORS: 2169 rval = 1; 2170 break; 2171 default: 2172 rval = -1; 2173 break; 2174 } 2175 2176 return (rval); 2177 } 2178 2179 /* 2180 * tran_destroy_pkt - deallocate scsi_pkt structure 2181 * @ap: 2182 * @pkt: 2183 * 2184 * The tran_destroy_pkt() entry point is the HBA driver function that 2185 * deallocates scsi_pkt structures. The tran_destroy_pkt() entry point is 2186 * called when the target driver calls scsi_destroy_pkt(). The 2187 * tran_destroy_pkt() entry point must free any DMA resources that have been 2188 * allocated for the packet. An implicit DMA synchronization occurs if the 2189 * DMA resources are freed and any cached data remains after the completion 2190 * of the transfer. 2191 */ 2192 static void 2193 mrsas_tran_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 2194 { 2195 struct scsa_cmd *acmd = PKT2CMD(pkt); 2196 2197 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2198 2199 if (acmd->cmd_flags & CFLAG_DMAVALID) { 2200 acmd->cmd_flags &= ~CFLAG_DMAVALID; 2201 2202 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle); 2203 2204 ddi_dma_free_handle(&acmd->cmd_dmahandle); 2205 2206 acmd->cmd_dmahandle = NULL; 2207 } 2208 2209 /* free the pkt */ 2210 scsi_hba_pkt_free(ap, pkt); 2211 } 2212 2213 /* 2214 * tran_dmafree - deallocates DMA resources 2215 * @ap: 2216 * @pkt: 2217 * 2218 * The tran_dmafree() entry point deallocates DMAQ resources that have been 2219 * allocated for a scsi_pkt structure. The tran_dmafree() entry point is 2220 * called when the target driver calls scsi_dmafree(). The tran_dmafree() must 2221 * free only DMA resources allocated for a scsi_pkt structure, not the 2222 * scsi_pkt itself. When DMA resources are freed, a DMA synchronization is 2223 * implicitly performed. 2224 */ 2225 /*ARGSUSED*/ 2226 static void 2227 mrsas_tran_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 2228 { 2229 register struct scsa_cmd *acmd = PKT2CMD(pkt); 2230 2231 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2232 2233 if (acmd->cmd_flags & CFLAG_DMAVALID) { 2234 acmd->cmd_flags &= ~CFLAG_DMAVALID; 2235 2236 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle); 2237 2238 ddi_dma_free_handle(&acmd->cmd_dmahandle); 2239 2240 acmd->cmd_dmahandle = NULL; 2241 } 2242 } 2243 2244 /* 2245 * tran_sync_pkt - synchronize the DMA object allocated 2246 * @ap: 2247 * @pkt: 2248 * 2249 * The tran_sync_pkt() entry point synchronizes the DMA object allocated for 2250 * the scsi_pkt structure before or after a DMA transfer. The tran_sync_pkt() 2251 * entry point is called when the target driver calls scsi_sync_pkt(). If the 2252 * data transfer direction is a DMA read from device to memory, tran_sync_pkt() 2253 * must synchronize the CPU's view of the data. If the data transfer direction 2254 * is a DMA write from memory to device, tran_sync_pkt() must synchronize the 2255 * device's view of the data. 2256 */ 2257 /*ARGSUSED*/ 2258 static void 2259 mrsas_tran_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 2260 { 2261 register struct scsa_cmd *acmd = PKT2CMD(pkt); 2262 2263 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2264 2265 if (acmd->cmd_flags & CFLAG_DMAVALID) { 2266 (void) ddi_dma_sync(acmd->cmd_dmahandle, acmd->cmd_dma_offset, 2267 acmd->cmd_dma_len, (acmd->cmd_flags & CFLAG_DMASEND) ? 2268 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 2269 } 2270 } 2271 2272 /*ARGSUSED*/ 2273 static int 2274 mrsas_tran_quiesce(dev_info_t *dip) 2275 { 2276 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2277 2278 return (1); 2279 } 2280 2281 /*ARGSUSED*/ 2282 static int 2283 mrsas_tran_unquiesce(dev_info_t *dip) 2284 { 2285 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2286 2287 return (1); 2288 } 2289 2290 2291 /* 2292 * mrsas_isr(caddr_t) 2293 * 2294 * The Interrupt Service Routine 2295 * 2296 * Collect status for all completed commands and do callback 2297 * 2298 */ 2299 static uint_t 2300 mrsas_isr(struct mrsas_instance *instance) 2301 { 2302 int need_softintr; 2303 uint32_t producer; 2304 uint32_t consumer; 2305 uint32_t context; 2306 int retval; 2307 2308 struct mrsas_cmd *cmd; 2309 struct mrsas_header *hdr; 2310 struct scsi_pkt *pkt; 2311 2312 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2313 ASSERT(instance); 2314 if (instance->tbolt) { 2315 mutex_enter(&instance->chip_mtx); 2316 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) && 2317 !(instance->func_ptr->intr_ack(instance))) { 2318 mutex_exit(&instance->chip_mtx); 2319 return (DDI_INTR_UNCLAIMED); 2320 } 2321 retval = mr_sas_tbolt_process_outstanding_cmd(instance); 2322 mutex_exit(&instance->chip_mtx); 2323 return (retval); 2324 } else { 2325 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) && 2326 !instance->func_ptr->intr_ack(instance)) { 2327 return (DDI_INTR_UNCLAIMED); 2328 } 2329 } 2330 2331 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle, 2332 0, 0, DDI_DMA_SYNC_FORCPU); 2333 2334 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle) 2335 != DDI_SUCCESS) { 2336 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 2337 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 2338 con_log(CL_ANN1, (CE_WARN, 2339 "mr_sas_isr(): FMA check, returning DDI_INTR_UNCLAIMED")); 2340 return (DDI_INTR_CLAIMED); 2341 } 2342 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2343 2344 #ifdef OCRDEBUG 2345 if (debug_consecutive_timeout_after_ocr_g == 1) { 2346 con_log(CL_ANN1, (CE_NOTE, 2347 "simulating consecutive timeout after ocr")); 2348 return (DDI_INTR_CLAIMED); 2349 } 2350 #endif 2351 2352 mutex_enter(&instance->completed_pool_mtx); 2353 mutex_enter(&instance->cmd_pend_mtx); 2354 2355 producer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle, 2356 instance->producer); 2357 consumer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle, 2358 instance->consumer); 2359 2360 con_log(CL_ANN, (CE_CONT, " producer %x consumer %x ", 2361 producer, consumer)); 2362 if (producer == consumer) { 2363 con_log(CL_ANN, (CE_WARN, "producer == consumer case")); 2364 DTRACE_PROBE2(isr_pc_err, uint32_t, producer, 2365 uint32_t, consumer); 2366 mutex_exit(&instance->cmd_pend_mtx); 2367 mutex_exit(&instance->completed_pool_mtx); 2368 return (DDI_INTR_CLAIMED); 2369 } 2370 2371 while (consumer != producer) { 2372 context = ddi_get32(instance->mfi_internal_dma_obj.acc_handle, 2373 &instance->reply_queue[consumer]); 2374 cmd = instance->cmd_list[context]; 2375 2376 if (cmd->sync_cmd == MRSAS_TRUE) { 2377 hdr = (struct mrsas_header *)&cmd->frame->hdr; 2378 if (hdr) { 2379 mlist_del_init(&cmd->list); 2380 } 2381 } else { 2382 pkt = cmd->pkt; 2383 if (pkt) { 2384 mlist_del_init(&cmd->list); 2385 } 2386 } 2387 2388 mlist_add_tail(&cmd->list, &instance->completed_pool_list); 2389 2390 consumer++; 2391 if (consumer == (instance->max_fw_cmds + 1)) { 2392 consumer = 0; 2393 } 2394 } 2395 ddi_put32(instance->mfi_internal_dma_obj.acc_handle, 2396 instance->consumer, consumer); 2397 mutex_exit(&instance->cmd_pend_mtx); 2398 mutex_exit(&instance->completed_pool_mtx); 2399 2400 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle, 2401 0, 0, DDI_DMA_SYNC_FORDEV); 2402 2403 if (instance->softint_running) { 2404 need_softintr = 0; 2405 } else { 2406 need_softintr = 1; 2407 } 2408 2409 if (instance->isr_level == HIGH_LEVEL_INTR) { 2410 if (need_softintr) { 2411 ddi_trigger_softintr(instance->soft_intr_id); 2412 } 2413 } else { 2414 /* 2415 * Not a high-level interrupt, therefore call the soft level 2416 * interrupt explicitly 2417 */ 2418 (void) mrsas_softintr(instance); 2419 } 2420 2421 return (DDI_INTR_CLAIMED); 2422 } 2423 2424 2425 /* 2426 * ************************************************************************** * 2427 * * 2428 * libraries * 2429 * * 2430 * ************************************************************************** * 2431 */ 2432 /* 2433 * get_mfi_pkt : Get a command from the free pool 2434 * After successful allocation, the caller of this routine 2435 * must clear the frame buffer (memset to zero) before 2436 * using the packet further. 2437 * 2438 * ***** Note ***** 2439 * After clearing the frame buffer the context id of the 2440 * frame buffer SHOULD be restored back. 2441 */ 2442 struct mrsas_cmd * 2443 mrsas_get_mfi_pkt(struct mrsas_instance *instance) 2444 { 2445 mlist_t *head = &instance->cmd_pool_list; 2446 struct mrsas_cmd *cmd = NULL; 2447 2448 mutex_enter(&instance->cmd_pool_mtx); 2449 2450 if (!mlist_empty(head)) { 2451 cmd = mlist_entry(head->next, struct mrsas_cmd, list); 2452 mlist_del_init(head->next); 2453 } 2454 if (cmd != NULL) { 2455 cmd->pkt = NULL; 2456 cmd->retry_count_for_ocr = 0; 2457 cmd->drv_pkt_time = 0; 2458 2459 } 2460 mutex_exit(&instance->cmd_pool_mtx); 2461 2462 return (cmd); 2463 } 2464 2465 static struct mrsas_cmd * 2466 get_mfi_app_pkt(struct mrsas_instance *instance) 2467 { 2468 mlist_t *head = &instance->app_cmd_pool_list; 2469 struct mrsas_cmd *cmd = NULL; 2470 2471 mutex_enter(&instance->app_cmd_pool_mtx); 2472 2473 if (!mlist_empty(head)) { 2474 cmd = mlist_entry(head->next, struct mrsas_cmd, list); 2475 mlist_del_init(head->next); 2476 } 2477 if (cmd != NULL) { 2478 cmd->pkt = NULL; 2479 cmd->retry_count_for_ocr = 0; 2480 cmd->drv_pkt_time = 0; 2481 } 2482 2483 mutex_exit(&instance->app_cmd_pool_mtx); 2484 2485 return (cmd); 2486 } 2487 /* 2488 * return_mfi_pkt : Return a cmd to free command pool 2489 */ 2490 void 2491 mrsas_return_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 2492 { 2493 mutex_enter(&instance->cmd_pool_mtx); 2494 /* use mlist_add_tail for debug assistance */ 2495 mlist_add_tail(&cmd->list, &instance->cmd_pool_list); 2496 2497 mutex_exit(&instance->cmd_pool_mtx); 2498 } 2499 2500 static void 2501 return_mfi_app_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 2502 { 2503 mutex_enter(&instance->app_cmd_pool_mtx); 2504 2505 mlist_add(&cmd->list, &instance->app_cmd_pool_list); 2506 2507 mutex_exit(&instance->app_cmd_pool_mtx); 2508 } 2509 void 2510 push_pending_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 2511 { 2512 struct scsi_pkt *pkt; 2513 struct mrsas_header *hdr; 2514 con_log(CL_DLEVEL2, (CE_NOTE, "push_pending_pkt(): Called\n")); 2515 mutex_enter(&instance->cmd_pend_mtx); 2516 mlist_del_init(&cmd->list); 2517 mlist_add_tail(&cmd->list, &instance->cmd_pend_list); 2518 if (cmd->sync_cmd == MRSAS_TRUE) { 2519 hdr = (struct mrsas_header *)&cmd->frame->hdr; 2520 if (hdr) { 2521 con_log(CL_ANN1, (CE_CONT, 2522 "push_pending_mfi_pkt: " 2523 "cmd %p index %x " 2524 "time %llx", 2525 (void *)cmd, cmd->index, 2526 gethrtime())); 2527 /* Wait for specified interval */ 2528 cmd->drv_pkt_time = ddi_get16( 2529 cmd->frame_dma_obj.acc_handle, &hdr->timeout); 2530 if (cmd->drv_pkt_time < debug_timeout_g) 2531 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 2532 con_log(CL_ANN1, (CE_CONT, 2533 "push_pending_pkt(): " 2534 "Called IO Timeout Value %x\n", 2535 cmd->drv_pkt_time)); 2536 } 2537 if (hdr && instance->timeout_id == (timeout_id_t)-1) { 2538 instance->timeout_id = timeout(io_timeout_checker, 2539 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 2540 } 2541 } else { 2542 pkt = cmd->pkt; 2543 if (pkt) { 2544 con_log(CL_ANN1, (CE_CONT, 2545 "push_pending_mfi_pkt: " 2546 "cmd %p index %x pkt %p, " 2547 "time %llx", 2548 (void *)cmd, cmd->index, (void *)pkt, 2549 gethrtime())); 2550 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 2551 } 2552 if (pkt && instance->timeout_id == (timeout_id_t)-1) { 2553 instance->timeout_id = timeout(io_timeout_checker, 2554 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 2555 } 2556 } 2557 2558 mutex_exit(&instance->cmd_pend_mtx); 2559 2560 } 2561 2562 int 2563 mrsas_print_pending_cmds(struct mrsas_instance *instance) 2564 { 2565 mlist_t *head = &instance->cmd_pend_list; 2566 mlist_t *tmp = head; 2567 struct mrsas_cmd *cmd = NULL; 2568 struct mrsas_header *hdr; 2569 unsigned int flag = 1; 2570 struct scsi_pkt *pkt; 2571 int saved_level; 2572 int cmd_count = 0; 2573 2574 saved_level = debug_level_g; 2575 debug_level_g = CL_ANN1; 2576 2577 dev_err(instance->dip, CE_NOTE, 2578 "mrsas_print_pending_cmds(): Called"); 2579 2580 while (flag) { 2581 mutex_enter(&instance->cmd_pend_mtx); 2582 tmp = tmp->next; 2583 if (tmp == head) { 2584 mutex_exit(&instance->cmd_pend_mtx); 2585 flag = 0; 2586 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds():" 2587 " NO MORE CMDS PENDING....\n")); 2588 break; 2589 } else { 2590 cmd = mlist_entry(tmp, struct mrsas_cmd, list); 2591 mutex_exit(&instance->cmd_pend_mtx); 2592 if (cmd) { 2593 if (cmd->sync_cmd == MRSAS_TRUE) { 2594 hdr = (struct mrsas_header *) 2595 &cmd->frame->hdr; 2596 if (hdr) { 2597 con_log(CL_ANN1, (CE_CONT, 2598 "print: cmd %p index 0x%x " 2599 "drv_pkt_time 0x%x (NO-PKT)" 2600 " hdr %p\n", (void *)cmd, 2601 cmd->index, 2602 cmd->drv_pkt_time, 2603 (void *)hdr)); 2604 } 2605 } else { 2606 pkt = cmd->pkt; 2607 if (pkt) { 2608 con_log(CL_ANN1, (CE_CONT, 2609 "print: cmd %p index 0x%x " 2610 "drv_pkt_time 0x%x pkt %p \n", 2611 (void *)cmd, cmd->index, 2612 cmd->drv_pkt_time, (void *)pkt)); 2613 } 2614 } 2615 2616 if (++cmd_count == 1) { 2617 mrsas_print_cmd_details(instance, cmd, 2618 0xDD); 2619 } else { 2620 mrsas_print_cmd_details(instance, cmd, 2621 1); 2622 } 2623 2624 } 2625 } 2626 } 2627 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds(): Done\n")); 2628 2629 2630 debug_level_g = saved_level; 2631 2632 return (DDI_SUCCESS); 2633 } 2634 2635 2636 int 2637 mrsas_complete_pending_cmds(struct mrsas_instance *instance) 2638 { 2639 2640 struct mrsas_cmd *cmd = NULL; 2641 struct scsi_pkt *pkt; 2642 struct mrsas_header *hdr; 2643 2644 struct mlist_head *pos, *next; 2645 2646 con_log(CL_ANN1, (CE_NOTE, 2647 "mrsas_complete_pending_cmds(): Called")); 2648 2649 mutex_enter(&instance->cmd_pend_mtx); 2650 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) { 2651 cmd = mlist_entry(pos, struct mrsas_cmd, list); 2652 if (cmd) { 2653 pkt = cmd->pkt; 2654 if (pkt) { /* for IO */ 2655 if (((pkt->pkt_flags & FLAG_NOINTR) 2656 == 0) && pkt->pkt_comp) { 2657 pkt->pkt_reason 2658 = CMD_DEV_GONE; 2659 pkt->pkt_statistics 2660 = STAT_DISCON; 2661 con_log(CL_ANN1, (CE_CONT, 2662 "fail and posting to scsa " 2663 "cmd %p index %x" 2664 " pkt %p " 2665 "time : %llx", 2666 (void *)cmd, cmd->index, 2667 (void *)pkt, gethrtime())); 2668 (*pkt->pkt_comp)(pkt); 2669 } 2670 } else { /* for DCMDS */ 2671 if (cmd->sync_cmd == MRSAS_TRUE) { 2672 hdr = (struct mrsas_header *)&cmd->frame->hdr; 2673 con_log(CL_ANN1, (CE_CONT, 2674 "posting invalid status to application " 2675 "cmd %p index %x" 2676 " hdr %p " 2677 "time : %llx", 2678 (void *)cmd, cmd->index, 2679 (void *)hdr, gethrtime())); 2680 hdr->cmd_status = MFI_STAT_INVALID_STATUS; 2681 complete_cmd_in_sync_mode(instance, cmd); 2682 } 2683 } 2684 mlist_del_init(&cmd->list); 2685 } else { 2686 con_log(CL_ANN1, (CE_CONT, 2687 "mrsas_complete_pending_cmds:" 2688 "NULL command\n")); 2689 } 2690 con_log(CL_ANN1, (CE_CONT, 2691 "mrsas_complete_pending_cmds:" 2692 "looping for more commands\n")); 2693 } 2694 mutex_exit(&instance->cmd_pend_mtx); 2695 2696 con_log(CL_ANN1, (CE_CONT, "mrsas_complete_pending_cmds(): DONE\n")); 2697 return (DDI_SUCCESS); 2698 } 2699 2700 void 2701 mrsas_print_cmd_details(struct mrsas_instance *instance, struct mrsas_cmd *cmd, 2702 int detail) 2703 { 2704 struct scsi_pkt *pkt = cmd->pkt; 2705 Mpi2RaidSCSIIORequest_t *scsi_io = cmd->scsi_io_request; 2706 int i; 2707 int saved_level; 2708 ddi_acc_handle_t acc_handle = 2709 instance->mpi2_frame_pool_dma_obj.acc_handle; 2710 2711 if (detail == 0xDD) { 2712 saved_level = debug_level_g; 2713 debug_level_g = CL_ANN1; 2714 } 2715 2716 2717 if (instance->tbolt) { 2718 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p " 2719 "cmd->index 0x%x SMID 0x%x timer 0x%x sec\n", 2720 (void *)cmd, cmd->index, cmd->SMID, cmd->drv_pkt_time)); 2721 } else { 2722 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p " 2723 "cmd->index 0x%x timer 0x%x sec\n", 2724 (void *)cmd, cmd->index, cmd->drv_pkt_time)); 2725 } 2726 2727 if (pkt) { 2728 con_log(CL_ANN1, (CE_CONT, "scsi_pkt CDB[0]=0x%x", 2729 pkt->pkt_cdbp[0])); 2730 } else { 2731 con_log(CL_ANN1, (CE_CONT, "NO-PKT")); 2732 } 2733 2734 if ((detail == 0xDD) && instance->tbolt) { 2735 con_log(CL_ANN1, (CE_CONT, "RAID_SCSI_IO_REQUEST\n")); 2736 con_log(CL_ANN1, (CE_CONT, "DevHandle=0x%X Function=0x%X " 2737 "IoFlags=0x%X SGLFlags=0x%X DataLength=0x%X\n", 2738 ddi_get16(acc_handle, &scsi_io->DevHandle), 2739 ddi_get8(acc_handle, &scsi_io->Function), 2740 ddi_get16(acc_handle, &scsi_io->IoFlags), 2741 ddi_get16(acc_handle, &scsi_io->SGLFlags), 2742 ddi_get32(acc_handle, &scsi_io->DataLength))); 2743 2744 for (i = 0; i < 32; i++) { 2745 con_log(CL_ANN1, (CE_CONT, "CDB[%d]=0x%x ", i, 2746 ddi_get8(acc_handle, &scsi_io->CDB.CDB32[i]))); 2747 } 2748 2749 con_log(CL_ANN1, (CE_CONT, "RAID-CONTEXT\n")); 2750 con_log(CL_ANN1, (CE_CONT, "status=0x%X extStatus=0x%X " 2751 "ldTargetId=0x%X timeoutValue=0x%X regLockFlags=0x%X " 2752 "RAIDFlags=0x%X regLockRowLBA=0x%" PRIu64 2753 " regLockLength=0x%X spanArm=0x%X\n", 2754 ddi_get8(acc_handle, &scsi_io->RaidContext.status), 2755 ddi_get8(acc_handle, &scsi_io->RaidContext.extStatus), 2756 ddi_get16(acc_handle, &scsi_io->RaidContext.ldTargetId), 2757 ddi_get16(acc_handle, &scsi_io->RaidContext.timeoutValue), 2758 ddi_get8(acc_handle, &scsi_io->RaidContext.regLockFlags), 2759 ddi_get8(acc_handle, &scsi_io->RaidContext.RAIDFlags), 2760 ddi_get64(acc_handle, &scsi_io->RaidContext.regLockRowLBA), 2761 ddi_get32(acc_handle, &scsi_io->RaidContext.regLockLength), 2762 ddi_get8(acc_handle, &scsi_io->RaidContext.spanArm))); 2763 } 2764 2765 if (detail == 0xDD) { 2766 debug_level_g = saved_level; 2767 } 2768 } 2769 2770 2771 int 2772 mrsas_issue_pending_cmds(struct mrsas_instance *instance) 2773 { 2774 mlist_t *head = &instance->cmd_pend_list; 2775 mlist_t *tmp = head->next; 2776 struct mrsas_cmd *cmd = NULL; 2777 struct scsi_pkt *pkt; 2778 2779 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_pending_cmds(): Called")); 2780 while (tmp != head) { 2781 mutex_enter(&instance->cmd_pend_mtx); 2782 cmd = mlist_entry(tmp, struct mrsas_cmd, list); 2783 tmp = tmp->next; 2784 mutex_exit(&instance->cmd_pend_mtx); 2785 if (cmd) { 2786 con_log(CL_ANN1, (CE_CONT, 2787 "mrsas_issue_pending_cmds(): " 2788 "Got a cmd: cmd %p index 0x%x drv_pkt_time 0x%x ", 2789 (void *)cmd, cmd->index, cmd->drv_pkt_time)); 2790 2791 /* Reset command timeout value */ 2792 if (cmd->drv_pkt_time < debug_timeout_g) 2793 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 2794 2795 cmd->retry_count_for_ocr++; 2796 2797 dev_err(instance->dip, CE_CONT, 2798 "cmd retry count = %d\n", 2799 cmd->retry_count_for_ocr); 2800 2801 if (cmd->retry_count_for_ocr > IO_RETRY_COUNT) { 2802 dev_err(instance->dip, 2803 CE_WARN, "mrsas_issue_pending_cmds(): " 2804 "cmd->retry_count exceeded limit >%d\n", 2805 IO_RETRY_COUNT); 2806 mrsas_print_cmd_details(instance, cmd, 0xDD); 2807 2808 dev_err(instance->dip, CE_WARN, 2809 "mrsas_issue_pending_cmds():" 2810 "Calling KILL Adapter"); 2811 if (instance->tbolt) 2812 mrsas_tbolt_kill_adapter(instance); 2813 else 2814 (void) mrsas_kill_adapter(instance); 2815 return (DDI_FAILURE); 2816 } 2817 2818 pkt = cmd->pkt; 2819 if (pkt) { 2820 con_log(CL_ANN1, (CE_CONT, 2821 "PENDING PKT-CMD ISSUE: cmd %p index %x " 2822 "pkt %p time %llx", 2823 (void *)cmd, cmd->index, 2824 (void *)pkt, 2825 gethrtime())); 2826 2827 } else { 2828 dev_err(instance->dip, CE_CONT, 2829 "mrsas_issue_pending_cmds(): NO-PKT, " 2830 "cmd %p index 0x%x drv_pkt_time 0x%x", 2831 (void *)cmd, cmd->index, cmd->drv_pkt_time); 2832 } 2833 2834 2835 if (cmd->sync_cmd == MRSAS_TRUE) { 2836 dev_err(instance->dip, CE_CONT, 2837 "mrsas_issue_pending_cmds(): " 2838 "SYNC_CMD == TRUE \n"); 2839 instance->func_ptr->issue_cmd_in_sync_mode( 2840 instance, cmd); 2841 } else { 2842 instance->func_ptr->issue_cmd(cmd, instance); 2843 } 2844 } else { 2845 con_log(CL_ANN1, (CE_CONT, 2846 "mrsas_issue_pending_cmds: NULL command\n")); 2847 } 2848 con_log(CL_ANN1, (CE_CONT, 2849 "mrsas_issue_pending_cmds:" 2850 "looping for more commands")); 2851 } 2852 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_pending_cmds(): DONE\n")); 2853 return (DDI_SUCCESS); 2854 } 2855 2856 2857 2858 /* 2859 * destroy_mfi_frame_pool 2860 */ 2861 void 2862 destroy_mfi_frame_pool(struct mrsas_instance *instance) 2863 { 2864 int i; 2865 uint32_t max_cmd = instance->max_fw_cmds; 2866 2867 struct mrsas_cmd *cmd; 2868 2869 /* return all frames to pool */ 2870 2871 for (i = 0; i < max_cmd; i++) { 2872 2873 cmd = instance->cmd_list[i]; 2874 2875 if (cmd->frame_dma_obj_status == DMA_OBJ_ALLOCATED) 2876 (void) mrsas_free_dma_obj(instance, cmd->frame_dma_obj); 2877 2878 cmd->frame_dma_obj_status = DMA_OBJ_FREED; 2879 } 2880 2881 } 2882 2883 /* 2884 * create_mfi_frame_pool 2885 */ 2886 int 2887 create_mfi_frame_pool(struct mrsas_instance *instance) 2888 { 2889 int i = 0; 2890 int cookie_cnt; 2891 uint16_t max_cmd; 2892 uint16_t sge_sz; 2893 uint32_t sgl_sz; 2894 uint32_t tot_frame_size; 2895 struct mrsas_cmd *cmd; 2896 int retval = DDI_SUCCESS; 2897 2898 max_cmd = instance->max_fw_cmds; 2899 sge_sz = sizeof (struct mrsas_sge_ieee); 2900 /* calculated the number of 64byte frames required for SGL */ 2901 sgl_sz = sge_sz * instance->max_num_sge; 2902 tot_frame_size = sgl_sz + MRMFI_FRAME_SIZE + SENSE_LENGTH; 2903 2904 con_log(CL_DLEVEL3, (CE_NOTE, "create_mfi_frame_pool: " 2905 "sgl_sz %x tot_frame_size %x", sgl_sz, tot_frame_size)); 2906 2907 while (i < max_cmd) { 2908 cmd = instance->cmd_list[i]; 2909 2910 cmd->frame_dma_obj.size = tot_frame_size; 2911 cmd->frame_dma_obj.dma_attr = mrsas_generic_dma_attr; 2912 cmd->frame_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 2913 cmd->frame_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 2914 cmd->frame_dma_obj.dma_attr.dma_attr_sgllen = 1; 2915 cmd->frame_dma_obj.dma_attr.dma_attr_align = 64; 2916 2917 cookie_cnt = mrsas_alloc_dma_obj(instance, &cmd->frame_dma_obj, 2918 (uchar_t)DDI_STRUCTURE_LE_ACC); 2919 2920 if (cookie_cnt == -1 || cookie_cnt > 1) { 2921 dev_err(instance->dip, CE_WARN, 2922 "create_mfi_frame_pool: could not alloc."); 2923 retval = DDI_FAILURE; 2924 goto mrsas_undo_frame_pool; 2925 } 2926 2927 bzero(cmd->frame_dma_obj.buffer, tot_frame_size); 2928 2929 cmd->frame_dma_obj_status = DMA_OBJ_ALLOCATED; 2930 cmd->frame = (union mrsas_frame *)cmd->frame_dma_obj.buffer; 2931 cmd->frame_phys_addr = 2932 cmd->frame_dma_obj.dma_cookie[0].dmac_address; 2933 2934 cmd->sense = (uint8_t *)(((unsigned long) 2935 cmd->frame_dma_obj.buffer) + 2936 tot_frame_size - SENSE_LENGTH); 2937 cmd->sense_phys_addr = 2938 cmd->frame_dma_obj.dma_cookie[0].dmac_address + 2939 tot_frame_size - SENSE_LENGTH; 2940 2941 if (!cmd->frame || !cmd->sense) { 2942 dev_err(instance->dip, CE_WARN, 2943 "pci_pool_alloc failed"); 2944 retval = ENOMEM; 2945 goto mrsas_undo_frame_pool; 2946 } 2947 2948 ddi_put32(cmd->frame_dma_obj.acc_handle, 2949 &cmd->frame->io.context, cmd->index); 2950 i++; 2951 2952 con_log(CL_DLEVEL3, (CE_NOTE, "[%x]-%x", 2953 cmd->index, cmd->frame_phys_addr)); 2954 } 2955 2956 return (DDI_SUCCESS); 2957 2958 mrsas_undo_frame_pool: 2959 if (i > 0) 2960 destroy_mfi_frame_pool(instance); 2961 2962 return (retval); 2963 } 2964 2965 /* 2966 * free_additional_dma_buffer 2967 */ 2968 static void 2969 free_additional_dma_buffer(struct mrsas_instance *instance) 2970 { 2971 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) { 2972 (void) mrsas_free_dma_obj(instance, 2973 instance->mfi_internal_dma_obj); 2974 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED; 2975 } 2976 2977 if (instance->mfi_evt_detail_obj.status == DMA_OBJ_ALLOCATED) { 2978 (void) mrsas_free_dma_obj(instance, 2979 instance->mfi_evt_detail_obj); 2980 instance->mfi_evt_detail_obj.status = DMA_OBJ_FREED; 2981 } 2982 } 2983 2984 /* 2985 * alloc_additional_dma_buffer 2986 */ 2987 static int 2988 alloc_additional_dma_buffer(struct mrsas_instance *instance) 2989 { 2990 uint32_t reply_q_sz; 2991 uint32_t internal_buf_size = PAGESIZE*2; 2992 2993 /* max cmds plus 1 + producer & consumer */ 2994 reply_q_sz = sizeof (uint32_t) * (instance->max_fw_cmds + 1 + 2); 2995 2996 instance->mfi_internal_dma_obj.size = internal_buf_size; 2997 instance->mfi_internal_dma_obj.dma_attr = mrsas_generic_dma_attr; 2998 instance->mfi_internal_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 2999 instance->mfi_internal_dma_obj.dma_attr.dma_attr_count_max = 3000 0xFFFFFFFFU; 3001 instance->mfi_internal_dma_obj.dma_attr.dma_attr_sgllen = 1; 3002 3003 if (mrsas_alloc_dma_obj(instance, &instance->mfi_internal_dma_obj, 3004 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 3005 dev_err(instance->dip, CE_WARN, 3006 "could not alloc reply queue"); 3007 return (DDI_FAILURE); 3008 } 3009 3010 bzero(instance->mfi_internal_dma_obj.buffer, internal_buf_size); 3011 3012 instance->mfi_internal_dma_obj.status |= DMA_OBJ_ALLOCATED; 3013 3014 instance->producer = (uint32_t *)((unsigned long) 3015 instance->mfi_internal_dma_obj.buffer); 3016 instance->consumer = (uint32_t *)((unsigned long) 3017 instance->mfi_internal_dma_obj.buffer + 4); 3018 instance->reply_queue = (uint32_t *)((unsigned long) 3019 instance->mfi_internal_dma_obj.buffer + 8); 3020 instance->internal_buf = (caddr_t)(((unsigned long) 3021 instance->mfi_internal_dma_obj.buffer) + reply_q_sz + 8); 3022 instance->internal_buf_dmac_add = 3023 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 3024 (reply_q_sz + 8); 3025 instance->internal_buf_size = internal_buf_size - 3026 (reply_q_sz + 8); 3027 3028 /* allocate evt_detail */ 3029 instance->mfi_evt_detail_obj.size = sizeof (struct mrsas_evt_detail); 3030 instance->mfi_evt_detail_obj.dma_attr = mrsas_generic_dma_attr; 3031 instance->mfi_evt_detail_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 3032 instance->mfi_evt_detail_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 3033 instance->mfi_evt_detail_obj.dma_attr.dma_attr_sgllen = 1; 3034 instance->mfi_evt_detail_obj.dma_attr.dma_attr_align = 1; 3035 3036 if (mrsas_alloc_dma_obj(instance, &instance->mfi_evt_detail_obj, 3037 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 3038 dev_err(instance->dip, CE_WARN, "alloc_additional_dma_buffer: " 3039 "could not allocate data transfer buffer."); 3040 goto mrsas_undo_internal_buff; 3041 } 3042 3043 bzero(instance->mfi_evt_detail_obj.buffer, 3044 sizeof (struct mrsas_evt_detail)); 3045 3046 instance->mfi_evt_detail_obj.status |= DMA_OBJ_ALLOCATED; 3047 3048 return (DDI_SUCCESS); 3049 3050 mrsas_undo_internal_buff: 3051 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) { 3052 (void) mrsas_free_dma_obj(instance, 3053 instance->mfi_internal_dma_obj); 3054 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED; 3055 } 3056 3057 return (DDI_FAILURE); 3058 } 3059 3060 3061 void 3062 mrsas_free_cmd_pool(struct mrsas_instance *instance) 3063 { 3064 int i; 3065 uint32_t max_cmd; 3066 size_t sz; 3067 3068 /* already freed */ 3069 if (instance->cmd_list == NULL) { 3070 return; 3071 } 3072 3073 max_cmd = instance->max_fw_cmds; 3074 3075 /* size of cmd_list array */ 3076 sz = sizeof (struct mrsas_cmd *) * max_cmd; 3077 3078 /* First free each cmd */ 3079 for (i = 0; i < max_cmd; i++) { 3080 if (instance->cmd_list[i] != NULL) { 3081 kmem_free(instance->cmd_list[i], 3082 sizeof (struct mrsas_cmd)); 3083 } 3084 3085 instance->cmd_list[i] = NULL; 3086 } 3087 3088 /* Now, free cmd_list array */ 3089 if (instance->cmd_list != NULL) 3090 kmem_free(instance->cmd_list, sz); 3091 3092 instance->cmd_list = NULL; 3093 3094 INIT_LIST_HEAD(&instance->cmd_pool_list); 3095 INIT_LIST_HEAD(&instance->cmd_pend_list); 3096 if (instance->tbolt) { 3097 INIT_LIST_HEAD(&instance->cmd_app_pool_list); 3098 } else { 3099 INIT_LIST_HEAD(&instance->app_cmd_pool_list); 3100 } 3101 3102 } 3103 3104 3105 /* 3106 * mrsas_alloc_cmd_pool 3107 */ 3108 int 3109 mrsas_alloc_cmd_pool(struct mrsas_instance *instance) 3110 { 3111 int i; 3112 int count; 3113 uint32_t max_cmd; 3114 uint32_t reserve_cmd; 3115 size_t sz; 3116 3117 struct mrsas_cmd *cmd; 3118 3119 max_cmd = instance->max_fw_cmds; 3120 con_log(CL_ANN1, (CE_NOTE, "mrsas_alloc_cmd_pool: " 3121 "max_cmd %x", max_cmd)); 3122 3123 3124 sz = sizeof (struct mrsas_cmd *) * max_cmd; 3125 3126 /* 3127 * instance->cmd_list is an array of struct mrsas_cmd pointers. 3128 * Allocate the dynamic array first and then allocate individual 3129 * commands. 3130 */ 3131 instance->cmd_list = kmem_zalloc(sz, KM_SLEEP); 3132 ASSERT(instance->cmd_list); 3133 3134 /* create a frame pool and assign one frame to each cmd */ 3135 for (count = 0; count < max_cmd; count++) { 3136 instance->cmd_list[count] = 3137 kmem_zalloc(sizeof (struct mrsas_cmd), KM_SLEEP); 3138 ASSERT(instance->cmd_list[count]); 3139 } 3140 3141 /* add all the commands to command pool */ 3142 3143 INIT_LIST_HEAD(&instance->cmd_pool_list); 3144 INIT_LIST_HEAD(&instance->cmd_pend_list); 3145 INIT_LIST_HEAD(&instance->app_cmd_pool_list); 3146 3147 /* 3148 * When max_cmd is lower than MRSAS_APP_RESERVED_CMDS, how do I split 3149 * into app_cmd and regular cmd? For now, just take 3150 * max(1/8th of max, 4); 3151 */ 3152 reserve_cmd = min(MRSAS_APP_RESERVED_CMDS, 3153 max(max_cmd >> 3, MRSAS_APP_MIN_RESERVED_CMDS)); 3154 3155 for (i = 0; i < reserve_cmd; i++) { 3156 cmd = instance->cmd_list[i]; 3157 cmd->index = i; 3158 mlist_add_tail(&cmd->list, &instance->app_cmd_pool_list); 3159 } 3160 3161 3162 for (i = reserve_cmd; i < max_cmd; i++) { 3163 cmd = instance->cmd_list[i]; 3164 cmd->index = i; 3165 mlist_add_tail(&cmd->list, &instance->cmd_pool_list); 3166 } 3167 3168 return (DDI_SUCCESS); 3169 3170 mrsas_undo_cmds: 3171 if (count > 0) { 3172 /* free each cmd */ 3173 for (i = 0; i < count; i++) { 3174 if (instance->cmd_list[i] != NULL) { 3175 kmem_free(instance->cmd_list[i], 3176 sizeof (struct mrsas_cmd)); 3177 } 3178 instance->cmd_list[i] = NULL; 3179 } 3180 } 3181 3182 mrsas_undo_cmd_list: 3183 if (instance->cmd_list != NULL) 3184 kmem_free(instance->cmd_list, sz); 3185 instance->cmd_list = NULL; 3186 3187 return (DDI_FAILURE); 3188 } 3189 3190 3191 /* 3192 * free_space_for_mfi 3193 */ 3194 static void 3195 free_space_for_mfi(struct mrsas_instance *instance) 3196 { 3197 3198 /* already freed */ 3199 if (instance->cmd_list == NULL) { 3200 return; 3201 } 3202 3203 /* Free additional dma buffer */ 3204 free_additional_dma_buffer(instance); 3205 3206 /* Free the MFI frame pool */ 3207 destroy_mfi_frame_pool(instance); 3208 3209 /* Free all the commands in the cmd_list */ 3210 /* Free the cmd_list buffer itself */ 3211 mrsas_free_cmd_pool(instance); 3212 } 3213 3214 /* 3215 * alloc_space_for_mfi 3216 */ 3217 static int 3218 alloc_space_for_mfi(struct mrsas_instance *instance) 3219 { 3220 /* Allocate command pool (memory for cmd_list & individual commands) */ 3221 if (mrsas_alloc_cmd_pool(instance)) { 3222 dev_err(instance->dip, CE_WARN, "error creating cmd pool"); 3223 return (DDI_FAILURE); 3224 } 3225 3226 /* Allocate MFI Frame pool */ 3227 if (create_mfi_frame_pool(instance)) { 3228 dev_err(instance->dip, CE_WARN, 3229 "error creating frame DMA pool"); 3230 goto mfi_undo_cmd_pool; 3231 } 3232 3233 /* Allocate additional DMA buffer */ 3234 if (alloc_additional_dma_buffer(instance)) { 3235 dev_err(instance->dip, CE_WARN, 3236 "error creating frame DMA pool"); 3237 goto mfi_undo_frame_pool; 3238 } 3239 3240 return (DDI_SUCCESS); 3241 3242 mfi_undo_frame_pool: 3243 destroy_mfi_frame_pool(instance); 3244 3245 mfi_undo_cmd_pool: 3246 mrsas_free_cmd_pool(instance); 3247 3248 return (DDI_FAILURE); 3249 } 3250 3251 3252 3253 /* 3254 * get_ctrl_info 3255 */ 3256 static int 3257 get_ctrl_info(struct mrsas_instance *instance, 3258 struct mrsas_ctrl_info *ctrl_info) 3259 { 3260 int ret = 0; 3261 3262 struct mrsas_cmd *cmd; 3263 struct mrsas_dcmd_frame *dcmd; 3264 struct mrsas_ctrl_info *ci; 3265 3266 if (instance->tbolt) { 3267 cmd = get_raid_msg_mfi_pkt(instance); 3268 } else { 3269 cmd = mrsas_get_mfi_pkt(instance); 3270 } 3271 3272 if (!cmd) { 3273 con_log(CL_ANN, (CE_WARN, 3274 "Failed to get a cmd for ctrl info")); 3275 DTRACE_PROBE2(info_mfi_err, uint16_t, instance->fw_outstanding, 3276 uint16_t, instance->max_fw_cmds); 3277 return (DDI_FAILURE); 3278 } 3279 3280 /* Clear the frame buffer and assign back the context id */ 3281 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3282 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 3283 cmd->index); 3284 3285 dcmd = &cmd->frame->dcmd; 3286 3287 ci = (struct mrsas_ctrl_info *)instance->internal_buf; 3288 3289 if (!ci) { 3290 dev_err(instance->dip, CE_WARN, 3291 "Failed to alloc mem for ctrl info"); 3292 mrsas_return_mfi_pkt(instance, cmd); 3293 return (DDI_FAILURE); 3294 } 3295 3296 (void) memset(ci, 0, sizeof (struct mrsas_ctrl_info)); 3297 3298 /* for( i = 0; i < DCMD_MBOX_SZ; i++ ) dcmd->mbox.b[i] = 0; */ 3299 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 3300 3301 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 3302 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 3303 MFI_CMD_STATUS_POLL_MODE); 3304 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1); 3305 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 3306 MFI_FRAME_DIR_READ); 3307 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 3308 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 3309 sizeof (struct mrsas_ctrl_info)); 3310 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 3311 MR_DCMD_CTRL_GET_INFO); 3312 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr, 3313 instance->internal_buf_dmac_add); 3314 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length, 3315 sizeof (struct mrsas_ctrl_info)); 3316 3317 cmd->frame_count = 1; 3318 3319 if (instance->tbolt) { 3320 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 3321 } 3322 3323 if (!instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 3324 ret = 0; 3325 3326 ctrl_info->max_request_size = ddi_get32( 3327 cmd->frame_dma_obj.acc_handle, &ci->max_request_size); 3328 3329 ctrl_info->ld_present_count = ddi_get16( 3330 cmd->frame_dma_obj.acc_handle, &ci->ld_present_count); 3331 3332 ctrl_info->properties.on_off_properties = ddi_get32( 3333 cmd->frame_dma_obj.acc_handle, 3334 &ci->properties.on_off_properties); 3335 ddi_rep_get8(cmd->frame_dma_obj.acc_handle, 3336 (uint8_t *)(ctrl_info->product_name), 3337 (uint8_t *)(ci->product_name), 80 * sizeof (char), 3338 DDI_DEV_AUTOINCR); 3339 /* should get more members of ci with ddi_get when needed */ 3340 } else { 3341 dev_err(instance->dip, CE_WARN, 3342 "get_ctrl_info: Ctrl info failed"); 3343 ret = -1; 3344 } 3345 3346 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) { 3347 ret = -1; 3348 } 3349 if (instance->tbolt) { 3350 return_raid_msg_mfi_pkt(instance, cmd); 3351 } else { 3352 mrsas_return_mfi_pkt(instance, cmd); 3353 } 3354 3355 return (ret); 3356 } 3357 3358 /* 3359 * abort_aen_cmd 3360 */ 3361 static int 3362 abort_aen_cmd(struct mrsas_instance *instance, 3363 struct mrsas_cmd *cmd_to_abort) 3364 { 3365 int ret = 0; 3366 3367 struct mrsas_cmd *cmd; 3368 struct mrsas_abort_frame *abort_fr; 3369 3370 con_log(CL_ANN1, (CE_NOTE, "chkpnt: abort_aen:%d", __LINE__)); 3371 3372 if (instance->tbolt) { 3373 cmd = get_raid_msg_mfi_pkt(instance); 3374 } else { 3375 cmd = mrsas_get_mfi_pkt(instance); 3376 } 3377 3378 if (!cmd) { 3379 con_log(CL_ANN1, (CE_WARN, 3380 "abort_aen_cmd():Failed to get a cmd for abort_aen_cmd")); 3381 DTRACE_PROBE2(abort_mfi_err, uint16_t, instance->fw_outstanding, 3382 uint16_t, instance->max_fw_cmds); 3383 return (DDI_FAILURE); 3384 } 3385 3386 /* Clear the frame buffer and assign back the context id */ 3387 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3388 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 3389 cmd->index); 3390 3391 abort_fr = &cmd->frame->abort; 3392 3393 /* prepare and issue the abort frame */ 3394 ddi_put8(cmd->frame_dma_obj.acc_handle, 3395 &abort_fr->cmd, MFI_CMD_OP_ABORT); 3396 ddi_put8(cmd->frame_dma_obj.acc_handle, &abort_fr->cmd_status, 3397 MFI_CMD_STATUS_SYNC_MODE); 3398 ddi_put16(cmd->frame_dma_obj.acc_handle, &abort_fr->flags, 0); 3399 ddi_put32(cmd->frame_dma_obj.acc_handle, &abort_fr->abort_context, 3400 cmd_to_abort->index); 3401 ddi_put32(cmd->frame_dma_obj.acc_handle, 3402 &abort_fr->abort_mfi_phys_addr_lo, cmd_to_abort->frame_phys_addr); 3403 ddi_put32(cmd->frame_dma_obj.acc_handle, 3404 &abort_fr->abort_mfi_phys_addr_hi, 0); 3405 3406 instance->aen_cmd->abort_aen = 1; 3407 3408 cmd->frame_count = 1; 3409 3410 if (instance->tbolt) { 3411 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 3412 } 3413 3414 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 3415 con_log(CL_ANN1, (CE_WARN, 3416 "abort_aen_cmd: issue_cmd_in_poll_mode failed")); 3417 ret = -1; 3418 } else { 3419 ret = 0; 3420 } 3421 3422 instance->aen_cmd->abort_aen = 1; 3423 instance->aen_cmd = 0; 3424 3425 if (instance->tbolt) { 3426 return_raid_msg_mfi_pkt(instance, cmd); 3427 } else { 3428 mrsas_return_mfi_pkt(instance, cmd); 3429 } 3430 3431 atomic_add_16(&instance->fw_outstanding, (-1)); 3432 3433 return (ret); 3434 } 3435 3436 3437 static int 3438 mrsas_build_init_cmd(struct mrsas_instance *instance, 3439 struct mrsas_cmd **cmd_ptr) 3440 { 3441 struct mrsas_cmd *cmd; 3442 struct mrsas_init_frame *init_frame; 3443 struct mrsas_init_queue_info *initq_info; 3444 struct mrsas_drv_ver drv_ver_info; 3445 3446 3447 /* 3448 * Prepare a init frame. Note the init frame points to queue info 3449 * structure. Each frame has SGL allocated after first 64 bytes. For 3450 * this frame - since we don't need any SGL - we use SGL's space as 3451 * queue info structure 3452 */ 3453 cmd = *cmd_ptr; 3454 3455 3456 /* Clear the frame buffer and assign back the context id */ 3457 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3458 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 3459 cmd->index); 3460 3461 init_frame = (struct mrsas_init_frame *)cmd->frame; 3462 initq_info = (struct mrsas_init_queue_info *) 3463 ((unsigned long)init_frame + 64); 3464 3465 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE); 3466 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info)); 3467 3468 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0); 3469 3470 ddi_put32(cmd->frame_dma_obj.acc_handle, 3471 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1); 3472 3473 ddi_put32(cmd->frame_dma_obj.acc_handle, 3474 &initq_info->producer_index_phys_addr_hi, 0); 3475 ddi_put32(cmd->frame_dma_obj.acc_handle, 3476 &initq_info->producer_index_phys_addr_lo, 3477 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address); 3478 3479 ddi_put32(cmd->frame_dma_obj.acc_handle, 3480 &initq_info->consumer_index_phys_addr_hi, 0); 3481 ddi_put32(cmd->frame_dma_obj.acc_handle, 3482 &initq_info->consumer_index_phys_addr_lo, 3483 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4); 3484 3485 ddi_put32(cmd->frame_dma_obj.acc_handle, 3486 &initq_info->reply_queue_start_phys_addr_hi, 0); 3487 ddi_put32(cmd->frame_dma_obj.acc_handle, 3488 &initq_info->reply_queue_start_phys_addr_lo, 3489 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8); 3490 3491 ddi_put8(cmd->frame_dma_obj.acc_handle, 3492 &init_frame->cmd, MFI_CMD_OP_INIT); 3493 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status, 3494 MFI_CMD_STATUS_POLL_MODE); 3495 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0); 3496 ddi_put32(cmd->frame_dma_obj.acc_handle, 3497 &init_frame->queue_info_new_phys_addr_lo, 3498 cmd->frame_phys_addr + 64); 3499 ddi_put32(cmd->frame_dma_obj.acc_handle, 3500 &init_frame->queue_info_new_phys_addr_hi, 0); 3501 3502 3503 /* fill driver version information */ 3504 fill_up_drv_ver(&drv_ver_info); 3505 3506 /* allocate the driver version data transfer buffer */ 3507 instance->drv_ver_dma_obj.size = sizeof (drv_ver_info.drv_ver); 3508 instance->drv_ver_dma_obj.dma_attr = mrsas_generic_dma_attr; 3509 instance->drv_ver_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 3510 instance->drv_ver_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 3511 instance->drv_ver_dma_obj.dma_attr.dma_attr_sgllen = 1; 3512 instance->drv_ver_dma_obj.dma_attr.dma_attr_align = 1; 3513 3514 if (mrsas_alloc_dma_obj(instance, &instance->drv_ver_dma_obj, 3515 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 3516 con_log(CL_ANN, (CE_WARN, 3517 "init_mfi : Could not allocate driver version buffer.")); 3518 return (DDI_FAILURE); 3519 } 3520 /* copy driver version to dma buffer */ 3521 (void) memset(instance->drv_ver_dma_obj.buffer, 0, 3522 sizeof (drv_ver_info.drv_ver)); 3523 ddi_rep_put8(cmd->frame_dma_obj.acc_handle, 3524 (uint8_t *)drv_ver_info.drv_ver, 3525 (uint8_t *)instance->drv_ver_dma_obj.buffer, 3526 sizeof (drv_ver_info.drv_ver), DDI_DEV_AUTOINCR); 3527 3528 3529 /* copy driver version physical address to init frame */ 3530 ddi_put64(cmd->frame_dma_obj.acc_handle, &init_frame->driverversion, 3531 instance->drv_ver_dma_obj.dma_cookie[0].dmac_address); 3532 3533 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len, 3534 sizeof (struct mrsas_init_queue_info)); 3535 3536 cmd->frame_count = 1; 3537 3538 *cmd_ptr = cmd; 3539 3540 return (DDI_SUCCESS); 3541 } 3542 3543 3544 /* 3545 * mrsas_init_adapter_ppc - Initialize MFI interface adapter. 3546 */ 3547 int 3548 mrsas_init_adapter_ppc(struct mrsas_instance *instance) 3549 { 3550 struct mrsas_cmd *cmd; 3551 3552 /* 3553 * allocate memory for mfi adapter(cmd pool, individual commands, mfi 3554 * frames etc 3555 */ 3556 if (alloc_space_for_mfi(instance) != DDI_SUCCESS) { 3557 con_log(CL_ANN, (CE_NOTE, 3558 "Error, failed to allocate memory for MFI adapter")); 3559 return (DDI_FAILURE); 3560 } 3561 3562 /* Build INIT command */ 3563 cmd = mrsas_get_mfi_pkt(instance); 3564 if (cmd == NULL) { 3565 DTRACE_PROBE2(init_adapter_mfi_err, uint16_t, 3566 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 3567 return (DDI_FAILURE); 3568 } 3569 3570 if (mrsas_build_init_cmd(instance, &cmd) != DDI_SUCCESS) { 3571 con_log(CL_ANN, 3572 (CE_NOTE, "Error, failed to build INIT command")); 3573 3574 goto fail_undo_alloc_mfi_space; 3575 } 3576 3577 /* 3578 * Disable interrupt before sending init frame ( see linux driver code) 3579 * send INIT MFI frame in polled mode 3580 */ 3581 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 3582 con_log(CL_ANN, (CE_WARN, "failed to init firmware")); 3583 goto fail_fw_init; 3584 } 3585 3586 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) 3587 goto fail_fw_init; 3588 mrsas_return_mfi_pkt(instance, cmd); 3589 3590 if (ctio_enable && 3591 (instance->func_ptr->read_fw_status_reg(instance) & 0x04000000)) { 3592 con_log(CL_ANN, (CE_NOTE, "mr_sas: IEEE SGL's supported")); 3593 instance->flag_ieee = 1; 3594 } else { 3595 instance->flag_ieee = 0; 3596 } 3597 3598 ASSERT(!instance->skinny || instance->flag_ieee); 3599 3600 instance->unroll.alloc_space_mfi = 1; 3601 instance->unroll.verBuff = 1; 3602 3603 return (DDI_SUCCESS); 3604 3605 3606 fail_fw_init: 3607 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj); 3608 3609 fail_undo_alloc_mfi_space: 3610 mrsas_return_mfi_pkt(instance, cmd); 3611 free_space_for_mfi(instance); 3612 3613 return (DDI_FAILURE); 3614 3615 } 3616 3617 /* 3618 * mrsas_init_adapter - Initialize adapter. 3619 */ 3620 int 3621 mrsas_init_adapter(struct mrsas_instance *instance) 3622 { 3623 struct mrsas_ctrl_info ctrl_info; 3624 3625 3626 /* we expect the FW state to be READY */ 3627 if (mfi_state_transition_to_ready(instance)) { 3628 con_log(CL_ANN, (CE_WARN, "mr_sas: F/W is not ready")); 3629 return (DDI_FAILURE); 3630 } 3631 3632 /* get various operational parameters from status register */ 3633 instance->max_num_sge = 3634 (instance->func_ptr->read_fw_status_reg(instance) & 3635 0xFF0000) >> 0x10; 3636 instance->max_num_sge = 3637 (instance->max_num_sge > MRSAS_MAX_SGE_CNT) ? 3638 MRSAS_MAX_SGE_CNT : instance->max_num_sge; 3639 3640 /* 3641 * Reduce the max supported cmds by 1. This is to ensure that the 3642 * reply_q_sz (1 more than the max cmd that driver may send) 3643 * does not exceed max cmds that the FW can support 3644 */ 3645 instance->max_fw_cmds = 3646 instance->func_ptr->read_fw_status_reg(instance) & 0xFFFF; 3647 instance->max_fw_cmds = instance->max_fw_cmds - 1; 3648 3649 3650 3651 /* Initialize adapter */ 3652 if (instance->func_ptr->init_adapter(instance) != DDI_SUCCESS) { 3653 con_log(CL_ANN, 3654 (CE_WARN, "mr_sas: could not initialize adapter")); 3655 return (DDI_FAILURE); 3656 } 3657 3658 /* gather misc FW related information */ 3659 instance->disable_online_ctrl_reset = 0; 3660 3661 if (!get_ctrl_info(instance, &ctrl_info)) { 3662 instance->max_sectors_per_req = ctrl_info.max_request_size; 3663 con_log(CL_ANN1, (CE_NOTE, 3664 "product name %s ld present %d", 3665 ctrl_info.product_name, ctrl_info.ld_present_count)); 3666 } else { 3667 instance->max_sectors_per_req = instance->max_num_sge * 3668 PAGESIZE / 512; 3669 } 3670 3671 if (ctrl_info.properties.on_off_properties & DISABLE_OCR_PROP_FLAG) 3672 instance->disable_online_ctrl_reset = 1; 3673 3674 return (DDI_SUCCESS); 3675 3676 } 3677 3678 3679 3680 static int 3681 mrsas_issue_init_mfi(struct mrsas_instance *instance) 3682 { 3683 struct mrsas_cmd *cmd; 3684 struct mrsas_init_frame *init_frame; 3685 struct mrsas_init_queue_info *initq_info; 3686 3687 /* 3688 * Prepare a init frame. Note the init frame points to queue info 3689 * structure. Each frame has SGL allocated after first 64 bytes. For 3690 * this frame - since we don't need any SGL - we use SGL's space as 3691 * queue info structure 3692 */ 3693 con_log(CL_ANN1, (CE_NOTE, 3694 "mrsas_issue_init_mfi: entry\n")); 3695 cmd = get_mfi_app_pkt(instance); 3696 3697 if (!cmd) { 3698 con_log(CL_ANN1, (CE_WARN, 3699 "mrsas_issue_init_mfi: get_pkt failed\n")); 3700 return (DDI_FAILURE); 3701 } 3702 3703 /* Clear the frame buffer and assign back the context id */ 3704 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3705 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 3706 cmd->index); 3707 3708 init_frame = (struct mrsas_init_frame *)cmd->frame; 3709 initq_info = (struct mrsas_init_queue_info *) 3710 ((unsigned long)init_frame + 64); 3711 3712 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE); 3713 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info)); 3714 3715 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0); 3716 3717 ddi_put32(cmd->frame_dma_obj.acc_handle, 3718 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1); 3719 ddi_put32(cmd->frame_dma_obj.acc_handle, 3720 &initq_info->producer_index_phys_addr_hi, 0); 3721 ddi_put32(cmd->frame_dma_obj.acc_handle, 3722 &initq_info->producer_index_phys_addr_lo, 3723 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address); 3724 ddi_put32(cmd->frame_dma_obj.acc_handle, 3725 &initq_info->consumer_index_phys_addr_hi, 0); 3726 ddi_put32(cmd->frame_dma_obj.acc_handle, 3727 &initq_info->consumer_index_phys_addr_lo, 3728 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4); 3729 3730 ddi_put32(cmd->frame_dma_obj.acc_handle, 3731 &initq_info->reply_queue_start_phys_addr_hi, 0); 3732 ddi_put32(cmd->frame_dma_obj.acc_handle, 3733 &initq_info->reply_queue_start_phys_addr_lo, 3734 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8); 3735 3736 ddi_put8(cmd->frame_dma_obj.acc_handle, 3737 &init_frame->cmd, MFI_CMD_OP_INIT); 3738 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status, 3739 MFI_CMD_STATUS_POLL_MODE); 3740 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0); 3741 ddi_put32(cmd->frame_dma_obj.acc_handle, 3742 &init_frame->queue_info_new_phys_addr_lo, 3743 cmd->frame_phys_addr + 64); 3744 ddi_put32(cmd->frame_dma_obj.acc_handle, 3745 &init_frame->queue_info_new_phys_addr_hi, 0); 3746 3747 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len, 3748 sizeof (struct mrsas_init_queue_info)); 3749 3750 cmd->frame_count = 1; 3751 3752 /* issue the init frame in polled mode */ 3753 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 3754 con_log(CL_ANN1, (CE_WARN, 3755 "mrsas_issue_init_mfi():failed to " 3756 "init firmware")); 3757 return_mfi_app_pkt(instance, cmd); 3758 return (DDI_FAILURE); 3759 } 3760 3761 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) { 3762 return_mfi_app_pkt(instance, cmd); 3763 return (DDI_FAILURE); 3764 } 3765 3766 return_mfi_app_pkt(instance, cmd); 3767 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_init_mfi: Done")); 3768 3769 return (DDI_SUCCESS); 3770 } 3771 /* 3772 * mfi_state_transition_to_ready : Move the FW to READY state 3773 * 3774 * @reg_set : MFI register set 3775 */ 3776 int 3777 mfi_state_transition_to_ready(struct mrsas_instance *instance) 3778 { 3779 int i; 3780 uint8_t max_wait; 3781 uint32_t fw_ctrl = 0; 3782 uint32_t fw_state; 3783 uint32_t cur_state; 3784 uint32_t cur_abs_reg_val; 3785 uint32_t prev_abs_reg_val; 3786 uint32_t status; 3787 3788 cur_abs_reg_val = 3789 instance->func_ptr->read_fw_status_reg(instance); 3790 fw_state = 3791 cur_abs_reg_val & MFI_STATE_MASK; 3792 con_log(CL_ANN1, (CE_CONT, 3793 "mfi_state_transition_to_ready:FW state = 0x%x", fw_state)); 3794 3795 while (fw_state != MFI_STATE_READY) { 3796 con_log(CL_ANN, (CE_CONT, 3797 "mfi_state_transition_to_ready:FW state%x", fw_state)); 3798 3799 switch (fw_state) { 3800 case MFI_STATE_FAULT: 3801 con_log(CL_ANN, (CE_NOTE, 3802 "mr_sas: FW in FAULT state!!")); 3803 3804 return (ENODEV); 3805 case MFI_STATE_WAIT_HANDSHAKE: 3806 /* set the CLR bit in IMR0 */ 3807 con_log(CL_ANN1, (CE_NOTE, 3808 "mr_sas: FW waiting for HANDSHAKE")); 3809 /* 3810 * PCI_Hot Plug: MFI F/W requires 3811 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG) 3812 * to be set 3813 */ 3814 /* WR_IB_MSG_0(MFI_INIT_CLEAR_HANDSHAKE, instance); */ 3815 if (!instance->tbolt && !instance->skinny) { 3816 WR_IB_DOORBELL(MFI_INIT_CLEAR_HANDSHAKE | 3817 MFI_INIT_HOTPLUG, instance); 3818 } else { 3819 WR_RESERVED0_REGISTER(MFI_INIT_CLEAR_HANDSHAKE | 3820 MFI_INIT_HOTPLUG, instance); 3821 } 3822 max_wait = (instance->tbolt == 1) ? 180 : 2; 3823 cur_state = MFI_STATE_WAIT_HANDSHAKE; 3824 break; 3825 case MFI_STATE_BOOT_MESSAGE_PENDING: 3826 /* set the CLR bit in IMR0 */ 3827 con_log(CL_ANN1, (CE_NOTE, 3828 "mr_sas: FW state boot message pending")); 3829 /* 3830 * PCI_Hot Plug: MFI F/W requires 3831 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG) 3832 * to be set 3833 */ 3834 if (!instance->tbolt && !instance->skinny) { 3835 WR_IB_DOORBELL(MFI_INIT_HOTPLUG, instance); 3836 } else { 3837 WR_RESERVED0_REGISTER(MFI_INIT_HOTPLUG, 3838 instance); 3839 } 3840 max_wait = (instance->tbolt == 1) ? 180 : 10; 3841 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING; 3842 break; 3843 case MFI_STATE_OPERATIONAL: 3844 /* bring it to READY state; assuming max wait 2 secs */ 3845 instance->func_ptr->disable_intr(instance); 3846 con_log(CL_ANN1, (CE_NOTE, 3847 "mr_sas: FW in OPERATIONAL state")); 3848 /* 3849 * PCI_Hot Plug: MFI F/W requires 3850 * (MFI_INIT_READY | MFI_INIT_MFIMODE | MFI_INIT_ABORT) 3851 * to be set 3852 */ 3853 /* WR_IB_DOORBELL(MFI_INIT_READY, instance); */ 3854 if (!instance->tbolt && !instance->skinny) { 3855 WR_IB_DOORBELL(MFI_RESET_FLAGS, instance); 3856 } else { 3857 WR_RESERVED0_REGISTER(MFI_RESET_FLAGS, 3858 instance); 3859 3860 for (i = 0; i < (10 * 1000); i++) { 3861 status = 3862 RD_RESERVED0_REGISTER(instance); 3863 if (status & 1) { 3864 delay(1 * 3865 drv_usectohz(MILLISEC)); 3866 } else { 3867 break; 3868 } 3869 } 3870 3871 } 3872 max_wait = (instance->tbolt == 1) ? 180 : 10; 3873 cur_state = MFI_STATE_OPERATIONAL; 3874 break; 3875 case MFI_STATE_UNDEFINED: 3876 /* this state should not last for more than 2 seconds */ 3877 con_log(CL_ANN1, (CE_NOTE, "FW state undefined")); 3878 3879 max_wait = (instance->tbolt == 1) ? 180 : 2; 3880 cur_state = MFI_STATE_UNDEFINED; 3881 break; 3882 case MFI_STATE_BB_INIT: 3883 max_wait = (instance->tbolt == 1) ? 180 : 2; 3884 cur_state = MFI_STATE_BB_INIT; 3885 break; 3886 case MFI_STATE_FW_INIT: 3887 max_wait = (instance->tbolt == 1) ? 180 : 2; 3888 cur_state = MFI_STATE_FW_INIT; 3889 break; 3890 case MFI_STATE_FW_INIT_2: 3891 max_wait = 180; 3892 cur_state = MFI_STATE_FW_INIT_2; 3893 break; 3894 case MFI_STATE_DEVICE_SCAN: 3895 max_wait = 180; 3896 cur_state = MFI_STATE_DEVICE_SCAN; 3897 prev_abs_reg_val = cur_abs_reg_val; 3898 con_log(CL_NONE, (CE_NOTE, 3899 "Device scan in progress ...\n")); 3900 break; 3901 case MFI_STATE_FLUSH_CACHE: 3902 max_wait = 180; 3903 cur_state = MFI_STATE_FLUSH_CACHE; 3904 break; 3905 default: 3906 con_log(CL_ANN1, (CE_NOTE, 3907 "mr_sas: Unknown state 0x%x", fw_state)); 3908 return (ENODEV); 3909 } 3910 3911 /* the cur_state should not last for more than max_wait secs */ 3912 for (i = 0; i < (max_wait * MILLISEC); i++) { 3913 /* fw_state = RD_OB_MSG_0(instance) & MFI_STATE_MASK; */ 3914 cur_abs_reg_val = 3915 instance->func_ptr->read_fw_status_reg(instance); 3916 fw_state = cur_abs_reg_val & MFI_STATE_MASK; 3917 3918 if (fw_state == cur_state) { 3919 delay(1 * drv_usectohz(MILLISEC)); 3920 } else { 3921 break; 3922 } 3923 } 3924 if (fw_state == MFI_STATE_DEVICE_SCAN) { 3925 if (prev_abs_reg_val != cur_abs_reg_val) { 3926 continue; 3927 } 3928 } 3929 3930 /* return error if fw_state hasn't changed after max_wait */ 3931 if (fw_state == cur_state) { 3932 con_log(CL_ANN1, (CE_WARN, 3933 "FW state hasn't changed in %d secs", max_wait)); 3934 return (ENODEV); 3935 } 3936 }; 3937 3938 /* This may also need to apply to Skinny, but for now, don't worry. */ 3939 if (!instance->tbolt && !instance->skinny) { 3940 fw_ctrl = RD_IB_DOORBELL(instance); 3941 con_log(CL_ANN1, (CE_CONT, 3942 "mfi_state_transition_to_ready:FW ctrl = 0x%x", fw_ctrl)); 3943 3944 /* 3945 * Write 0xF to the doorbell register to do the following. 3946 * - Abort all outstanding commands (bit 0). 3947 * - Transition from OPERATIONAL to READY state (bit 1). 3948 * - Discard (possible) low MFA posted in 64-bit mode (bit-2). 3949 * - Set to release FW to continue running (i.e. BIOS handshake 3950 * (bit 3). 3951 */ 3952 WR_IB_DOORBELL(0xF, instance); 3953 } 3954 3955 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) { 3956 return (EIO); 3957 } 3958 3959 return (DDI_SUCCESS); 3960 } 3961 3962 /* 3963 * get_seq_num 3964 */ 3965 static int 3966 get_seq_num(struct mrsas_instance *instance, 3967 struct mrsas_evt_log_info *eli) 3968 { 3969 int ret = DDI_SUCCESS; 3970 3971 dma_obj_t dcmd_dma_obj; 3972 struct mrsas_cmd *cmd; 3973 struct mrsas_dcmd_frame *dcmd; 3974 struct mrsas_evt_log_info *eli_tmp; 3975 if (instance->tbolt) { 3976 cmd = get_raid_msg_mfi_pkt(instance); 3977 } else { 3978 cmd = mrsas_get_mfi_pkt(instance); 3979 } 3980 3981 if (!cmd) { 3982 dev_err(instance->dip, CE_WARN, "failed to get a cmd"); 3983 DTRACE_PROBE2(seq_num_mfi_err, uint16_t, 3984 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 3985 return (ENOMEM); 3986 } 3987 3988 /* Clear the frame buffer and assign back the context id */ 3989 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3990 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 3991 cmd->index); 3992 3993 dcmd = &cmd->frame->dcmd; 3994 3995 /* allocate the data transfer buffer */ 3996 dcmd_dma_obj.size = sizeof (struct mrsas_evt_log_info); 3997 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr; 3998 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 3999 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 4000 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1; 4001 dcmd_dma_obj.dma_attr.dma_attr_align = 1; 4002 4003 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj, 4004 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 4005 dev_err(instance->dip, CE_WARN, 4006 "get_seq_num: could not allocate data transfer buffer."); 4007 return (DDI_FAILURE); 4008 } 4009 4010 (void) memset(dcmd_dma_obj.buffer, 0, 4011 sizeof (struct mrsas_evt_log_info)); 4012 4013 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 4014 4015 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 4016 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0); 4017 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1); 4018 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 4019 MFI_FRAME_DIR_READ); 4020 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 4021 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 4022 sizeof (struct mrsas_evt_log_info)); 4023 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 4024 MR_DCMD_CTRL_EVENT_GET_INFO); 4025 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length, 4026 sizeof (struct mrsas_evt_log_info)); 4027 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr, 4028 dcmd_dma_obj.dma_cookie[0].dmac_address); 4029 4030 cmd->sync_cmd = MRSAS_TRUE; 4031 cmd->frame_count = 1; 4032 4033 if (instance->tbolt) { 4034 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 4035 } 4036 4037 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 4038 dev_err(instance->dip, CE_WARN, "get_seq_num: " 4039 "failed to issue MRSAS_DCMD_CTRL_EVENT_GET_INFO"); 4040 ret = DDI_FAILURE; 4041 } else { 4042 eli_tmp = (struct mrsas_evt_log_info *)dcmd_dma_obj.buffer; 4043 eli->newest_seq_num = ddi_get32(cmd->frame_dma_obj.acc_handle, 4044 &eli_tmp->newest_seq_num); 4045 ret = DDI_SUCCESS; 4046 } 4047 4048 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS) 4049 ret = DDI_FAILURE; 4050 4051 if (instance->tbolt) { 4052 return_raid_msg_mfi_pkt(instance, cmd); 4053 } else { 4054 mrsas_return_mfi_pkt(instance, cmd); 4055 } 4056 4057 return (ret); 4058 } 4059 4060 /* 4061 * start_mfi_aen 4062 */ 4063 static int 4064 start_mfi_aen(struct mrsas_instance *instance) 4065 { 4066 int ret = 0; 4067 4068 struct mrsas_evt_log_info eli; 4069 union mrsas_evt_class_locale class_locale; 4070 4071 /* get the latest sequence number from FW */ 4072 (void) memset(&eli, 0, sizeof (struct mrsas_evt_log_info)); 4073 4074 if (get_seq_num(instance, &eli)) { 4075 dev_err(instance->dip, CE_WARN, 4076 "start_mfi_aen: failed to get seq num"); 4077 return (-1); 4078 } 4079 4080 /* register AEN with FW for latest sequence number plus 1 */ 4081 class_locale.members.reserved = 0; 4082 class_locale.members.locale = LE_16(MR_EVT_LOCALE_ALL); 4083 class_locale.members.class = MR_EVT_CLASS_INFO; 4084 class_locale.word = LE_32(class_locale.word); 4085 ret = register_mfi_aen(instance, eli.newest_seq_num + 1, 4086 class_locale.word); 4087 4088 if (ret) { 4089 dev_err(instance->dip, CE_WARN, 4090 "start_mfi_aen: aen registration failed"); 4091 return (-1); 4092 } 4093 4094 4095 return (ret); 4096 } 4097 4098 /* 4099 * flush_cache 4100 */ 4101 static void 4102 flush_cache(struct mrsas_instance *instance) 4103 { 4104 struct mrsas_cmd *cmd = NULL; 4105 struct mrsas_dcmd_frame *dcmd; 4106 if (instance->tbolt) { 4107 cmd = get_raid_msg_mfi_pkt(instance); 4108 } else { 4109 cmd = mrsas_get_mfi_pkt(instance); 4110 } 4111 4112 if (!cmd) { 4113 con_log(CL_ANN1, (CE_WARN, 4114 "flush_cache():Failed to get a cmd for flush_cache")); 4115 DTRACE_PROBE2(flush_cache_err, uint16_t, 4116 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 4117 return; 4118 } 4119 4120 /* Clear the frame buffer and assign back the context id */ 4121 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 4122 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 4123 cmd->index); 4124 4125 dcmd = &cmd->frame->dcmd; 4126 4127 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 4128 4129 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 4130 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0); 4131 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 0); 4132 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 4133 MFI_FRAME_DIR_NONE); 4134 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 4135 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 0); 4136 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 4137 MR_DCMD_CTRL_CACHE_FLUSH); 4138 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.b[0], 4139 MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE); 4140 4141 cmd->frame_count = 1; 4142 4143 if (instance->tbolt) { 4144 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 4145 } 4146 4147 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 4148 con_log(CL_ANN1, (CE_WARN, 4149 "flush_cache: failed to issue MFI_DCMD_CTRL_CACHE_FLUSH")); 4150 } 4151 con_log(CL_ANN1, (CE_CONT, "flush_cache done")); 4152 if (instance->tbolt) { 4153 return_raid_msg_mfi_pkt(instance, cmd); 4154 } else { 4155 mrsas_return_mfi_pkt(instance, cmd); 4156 } 4157 4158 } 4159 4160 /* 4161 * service_mfi_aen- Completes an AEN command 4162 * @instance: Adapter soft state 4163 * @cmd: Command to be completed 4164 * 4165 */ 4166 void 4167 service_mfi_aen(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 4168 { 4169 uint32_t seq_num; 4170 struct mrsas_evt_detail *evt_detail = 4171 (struct mrsas_evt_detail *)instance->mfi_evt_detail_obj.buffer; 4172 int rval = 0; 4173 int tgt = 0; 4174 uint8_t dtype; 4175 #ifdef PDSUPPORT 4176 mrsas_pd_address_t *pd_addr; 4177 #endif 4178 ddi_acc_handle_t acc_handle; 4179 4180 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 4181 4182 acc_handle = cmd->frame_dma_obj.acc_handle; 4183 cmd->cmd_status = ddi_get8(acc_handle, &cmd->frame->io.cmd_status); 4184 if (cmd->cmd_status == ENODATA) { 4185 cmd->cmd_status = 0; 4186 } 4187 4188 /* 4189 * log the MFI AEN event to the sysevent queue so that 4190 * application will get noticed 4191 */ 4192 if (ddi_log_sysevent(instance->dip, DDI_VENDOR_LSI, "LSIMEGA", "SAS", 4193 NULL, NULL, DDI_NOSLEEP) != DDI_SUCCESS) { 4194 int instance_no = ddi_get_instance(instance->dip); 4195 con_log(CL_ANN, (CE_WARN, 4196 "mr_sas%d: Failed to log AEN event", instance_no)); 4197 } 4198 /* 4199 * Check for any ld devices that has changed state. i.e. online 4200 * or offline. 4201 */ 4202 con_log(CL_ANN1, (CE_CONT, 4203 "AEN: code = %x class = %x locale = %x args = %x", 4204 ddi_get32(acc_handle, &evt_detail->code), 4205 evt_detail->cl.members.class, 4206 ddi_get16(acc_handle, &evt_detail->cl.members.locale), 4207 ddi_get8(acc_handle, &evt_detail->arg_type))); 4208 4209 switch (ddi_get32(acc_handle, &evt_detail->code)) { 4210 case MR_EVT_CFG_CLEARED: { 4211 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) { 4212 if (instance->mr_ld_list[tgt].dip != NULL) { 4213 mutex_enter(&instance->config_dev_mtx); 4214 instance->mr_ld_list[tgt].flag = 4215 (uint8_t)~MRDRV_TGT_VALID; 4216 mutex_exit(&instance->config_dev_mtx); 4217 rval = mrsas_service_evt(instance, tgt, 0, 4218 MRSAS_EVT_UNCONFIG_TGT, NULL); 4219 con_log(CL_ANN1, (CE_WARN, 4220 "mr_sas: CFG CLEARED AEN rval = %d " 4221 "tgt id = %d", rval, tgt)); 4222 } 4223 } 4224 break; 4225 } 4226 4227 case MR_EVT_LD_DELETED: { 4228 tgt = ddi_get16(acc_handle, &evt_detail->args.ld.target_id); 4229 mutex_enter(&instance->config_dev_mtx); 4230 instance->mr_ld_list[tgt].flag = (uint8_t)~MRDRV_TGT_VALID; 4231 mutex_exit(&instance->config_dev_mtx); 4232 rval = mrsas_service_evt(instance, 4233 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0, 4234 MRSAS_EVT_UNCONFIG_TGT, NULL); 4235 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD DELETED AEN rval = %d " 4236 "tgt id = %d index = %d", rval, 4237 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 4238 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index))); 4239 break; 4240 } /* End of MR_EVT_LD_DELETED */ 4241 4242 case MR_EVT_LD_CREATED: { 4243 rval = mrsas_service_evt(instance, 4244 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0, 4245 MRSAS_EVT_CONFIG_TGT, NULL); 4246 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD CREATED AEN rval = %d " 4247 "tgt id = %d index = %d", rval, 4248 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 4249 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index))); 4250 break; 4251 } /* End of MR_EVT_LD_CREATED */ 4252 4253 #ifdef PDSUPPORT 4254 case MR_EVT_PD_REMOVED_EXT: { 4255 if (instance->tbolt || instance->skinny) { 4256 pd_addr = &evt_detail->args.pd_addr; 4257 dtype = pd_addr->scsi_dev_type; 4258 con_log(CL_DLEVEL1, (CE_NOTE, 4259 " MR_EVT_PD_REMOVED_EXT: dtype = %x," 4260 " arg_type = %d ", dtype, evt_detail->arg_type)); 4261 tgt = ddi_get16(acc_handle, 4262 &evt_detail->args.pd.device_id); 4263 mutex_enter(&instance->config_dev_mtx); 4264 instance->mr_tbolt_pd_list[tgt].flag = 4265 (uint8_t)~MRDRV_TGT_VALID; 4266 mutex_exit(&instance->config_dev_mtx); 4267 rval = mrsas_service_evt(instance, ddi_get16( 4268 acc_handle, &evt_detail->args.pd.device_id), 4269 1, MRSAS_EVT_UNCONFIG_TGT, NULL); 4270 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:" 4271 "rval = %d tgt id = %d ", rval, 4272 ddi_get16(acc_handle, 4273 &evt_detail->args.pd.device_id))); 4274 } 4275 break; 4276 } /* End of MR_EVT_PD_REMOVED_EXT */ 4277 4278 case MR_EVT_PD_INSERTED_EXT: { 4279 if (instance->tbolt || instance->skinny) { 4280 rval = mrsas_service_evt(instance, 4281 ddi_get16(acc_handle, 4282 &evt_detail->args.pd.device_id), 4283 1, MRSAS_EVT_CONFIG_TGT, NULL); 4284 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_INSERTEDi_EXT:" 4285 "rval = %d tgt id = %d ", rval, 4286 ddi_get16(acc_handle, 4287 &evt_detail->args.pd.device_id))); 4288 } 4289 break; 4290 } /* End of MR_EVT_PD_INSERTED_EXT */ 4291 4292 case MR_EVT_PD_STATE_CHANGE: { 4293 if (instance->tbolt || instance->skinny) { 4294 tgt = ddi_get16(acc_handle, 4295 &evt_detail->args.pd.device_id); 4296 if ((evt_detail->args.pd_state.prevState == 4297 PD_SYSTEM) && 4298 (evt_detail->args.pd_state.newState != PD_SYSTEM)) { 4299 mutex_enter(&instance->config_dev_mtx); 4300 instance->mr_tbolt_pd_list[tgt].flag = 4301 (uint8_t)~MRDRV_TGT_VALID; 4302 mutex_exit(&instance->config_dev_mtx); 4303 rval = mrsas_service_evt(instance, 4304 ddi_get16(acc_handle, 4305 &evt_detail->args.pd.device_id), 4306 1, MRSAS_EVT_UNCONFIG_TGT, NULL); 4307 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:" 4308 "rval = %d tgt id = %d ", rval, 4309 ddi_get16(acc_handle, 4310 &evt_detail->args.pd.device_id))); 4311 break; 4312 } 4313 if ((evt_detail->args.pd_state.prevState 4314 == UNCONFIGURED_GOOD) && 4315 (evt_detail->args.pd_state.newState == PD_SYSTEM)) { 4316 rval = mrsas_service_evt(instance, 4317 ddi_get16(acc_handle, 4318 &evt_detail->args.pd.device_id), 4319 1, MRSAS_EVT_CONFIG_TGT, NULL); 4320 con_log(CL_ANN1, (CE_WARN, 4321 "mr_sas: PD_INSERTED: rval = %d " 4322 " tgt id = %d ", rval, 4323 ddi_get16(acc_handle, 4324 &evt_detail->args.pd.device_id))); 4325 break; 4326 } 4327 } 4328 break; 4329 } 4330 #endif 4331 4332 } /* End of Main Switch */ 4333 4334 /* get copy of seq_num and class/locale for re-registration */ 4335 seq_num = ddi_get32(acc_handle, &evt_detail->seq_num); 4336 seq_num++; 4337 (void) memset(instance->mfi_evt_detail_obj.buffer, 0, 4338 sizeof (struct mrsas_evt_detail)); 4339 4340 ddi_put8(acc_handle, &cmd->frame->dcmd.cmd_status, 0x0); 4341 ddi_put32(acc_handle, &cmd->frame->dcmd.mbox.w[0], seq_num); 4342 4343 instance->aen_seq_num = seq_num; 4344 4345 cmd->frame_count = 1; 4346 4347 cmd->retry_count_for_ocr = 0; 4348 cmd->drv_pkt_time = 0; 4349 4350 /* Issue the aen registration frame */ 4351 instance->func_ptr->issue_cmd(cmd, instance); 4352 } 4353 4354 /* 4355 * complete_cmd_in_sync_mode - Completes an internal command 4356 * @instance: Adapter soft state 4357 * @cmd: Command to be completed 4358 * 4359 * The issue_cmd_in_sync_mode() function waits for a command to complete 4360 * after it issues a command. This function wakes up that waiting routine by 4361 * calling wake_up() on the wait queue. 4362 */ 4363 static void 4364 complete_cmd_in_sync_mode(struct mrsas_instance *instance, 4365 struct mrsas_cmd *cmd) 4366 { 4367 cmd->cmd_status = ddi_get8(cmd->frame_dma_obj.acc_handle, 4368 &cmd->frame->io.cmd_status); 4369 4370 cmd->sync_cmd = MRSAS_FALSE; 4371 4372 con_log(CL_ANN1, (CE_NOTE, "complete_cmd_in_sync_mode called %p \n", 4373 (void *)cmd)); 4374 4375 mutex_enter(&instance->int_cmd_mtx); 4376 if (cmd->cmd_status == ENODATA) { 4377 cmd->cmd_status = 0; 4378 } 4379 cv_broadcast(&instance->int_cmd_cv); 4380 mutex_exit(&instance->int_cmd_mtx); 4381 4382 } 4383 4384 /* 4385 * Call this function inside mrsas_softintr. 4386 * mrsas_initiate_ocr_if_fw_is_faulty - Initiates OCR if FW status is faulty 4387 * @instance: Adapter soft state 4388 */ 4389 4390 static uint32_t 4391 mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *instance) 4392 { 4393 uint32_t cur_abs_reg_val; 4394 uint32_t fw_state; 4395 4396 cur_abs_reg_val = instance->func_ptr->read_fw_status_reg(instance); 4397 fw_state = cur_abs_reg_val & MFI_STATE_MASK; 4398 if (fw_state == MFI_STATE_FAULT) { 4399 if (instance->disable_online_ctrl_reset == 1) { 4400 dev_err(instance->dip, CE_WARN, 4401 "mrsas_initiate_ocr_if_fw_is_faulty: " 4402 "FW in Fault state, detected in ISR: " 4403 "FW doesn't support ocr "); 4404 4405 return (ADAPTER_RESET_NOT_REQUIRED); 4406 } else { 4407 con_log(CL_ANN, (CE_NOTE, 4408 "mrsas_initiate_ocr_if_fw_is_faulty: FW in Fault " 4409 "state, detected in ISR: FW supports ocr ")); 4410 4411 return (ADAPTER_RESET_REQUIRED); 4412 } 4413 } 4414 4415 return (ADAPTER_RESET_NOT_REQUIRED); 4416 } 4417 4418 /* 4419 * mrsas_softintr - The Software ISR 4420 * @param arg : HBA soft state 4421 * 4422 * called from high-level interrupt if hi-level interrupt are not there, 4423 * otherwise triggered as a soft interrupt 4424 */ 4425 static uint_t 4426 mrsas_softintr(struct mrsas_instance *instance) 4427 { 4428 struct scsi_pkt *pkt; 4429 struct scsa_cmd *acmd; 4430 struct mrsas_cmd *cmd; 4431 struct mlist_head *pos, *next; 4432 mlist_t process_list; 4433 struct mrsas_header *hdr; 4434 struct scsi_arq_status *arqstat; 4435 4436 con_log(CL_ANN1, (CE_NOTE, "mrsas_softintr() called.")); 4437 4438 ASSERT(instance); 4439 4440 mutex_enter(&instance->completed_pool_mtx); 4441 4442 if (mlist_empty(&instance->completed_pool_list)) { 4443 mutex_exit(&instance->completed_pool_mtx); 4444 return (DDI_INTR_CLAIMED); 4445 } 4446 4447 instance->softint_running = 1; 4448 4449 INIT_LIST_HEAD(&process_list); 4450 mlist_splice(&instance->completed_pool_list, &process_list); 4451 INIT_LIST_HEAD(&instance->completed_pool_list); 4452 4453 mutex_exit(&instance->completed_pool_mtx); 4454 4455 /* perform all callbacks first, before releasing the SCBs */ 4456 mlist_for_each_safe(pos, next, &process_list) { 4457 cmd = mlist_entry(pos, struct mrsas_cmd, list); 4458 4459 /* syncronize the Cmd frame for the controller */ 4460 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 4461 0, 0, DDI_DMA_SYNC_FORCPU); 4462 4463 if (mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) != 4464 DDI_SUCCESS) { 4465 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 4466 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 4467 con_log(CL_ANN1, (CE_WARN, 4468 "mrsas_softintr: " 4469 "FMA check reports DMA handle failure")); 4470 return (DDI_INTR_CLAIMED); 4471 } 4472 4473 hdr = &cmd->frame->hdr; 4474 4475 /* remove the internal command from the process list */ 4476 mlist_del_init(&cmd->list); 4477 4478 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) { 4479 case MFI_CMD_OP_PD_SCSI: 4480 case MFI_CMD_OP_LD_SCSI: 4481 case MFI_CMD_OP_LD_READ: 4482 case MFI_CMD_OP_LD_WRITE: 4483 /* 4484 * MFI_CMD_OP_PD_SCSI and MFI_CMD_OP_LD_SCSI 4485 * could have been issued either through an 4486 * IO path or an IOCTL path. If it was via IOCTL, 4487 * we will send it to internal completion. 4488 */ 4489 if (cmd->sync_cmd == MRSAS_TRUE) { 4490 complete_cmd_in_sync_mode(instance, cmd); 4491 break; 4492 } 4493 4494 /* regular commands */ 4495 acmd = cmd->cmd; 4496 pkt = CMD2PKT(acmd); 4497 4498 if (acmd->cmd_flags & CFLAG_DMAVALID) { 4499 if (acmd->cmd_flags & CFLAG_CONSISTENT) { 4500 (void) ddi_dma_sync(acmd->cmd_dmahandle, 4501 acmd->cmd_dma_offset, 4502 acmd->cmd_dma_len, 4503 DDI_DMA_SYNC_FORCPU); 4504 } 4505 } 4506 4507 pkt->pkt_reason = CMD_CMPLT; 4508 pkt->pkt_statistics = 0; 4509 pkt->pkt_state = STATE_GOT_BUS 4510 | STATE_GOT_TARGET | STATE_SENT_CMD 4511 | STATE_XFERRED_DATA | STATE_GOT_STATUS; 4512 4513 con_log(CL_ANN, (CE_CONT, 4514 "CDB[0] = %x completed for %s: size %lx context %x", 4515 pkt->pkt_cdbp[0], ((acmd->islogical) ? "LD" : "PD"), 4516 acmd->cmd_dmacount, hdr->context)); 4517 DTRACE_PROBE3(softintr_cdb, uint8_t, pkt->pkt_cdbp[0], 4518 uint_t, acmd->cmd_cdblen, ulong_t, 4519 acmd->cmd_dmacount); 4520 4521 if (pkt->pkt_cdbp[0] == SCMD_INQUIRY) { 4522 struct scsi_inquiry *inq; 4523 4524 if (acmd->cmd_dmacount != 0) { 4525 bp_mapin(acmd->cmd_buf); 4526 inq = (struct scsi_inquiry *) 4527 acmd->cmd_buf->b_un.b_addr; 4528 4529 #ifdef PDSUPPORT 4530 if (hdr->cmd_status == MFI_STAT_OK) { 4531 display_scsi_inquiry( 4532 (caddr_t)inq); 4533 } 4534 #else 4535 /* don't expose physical drives to OS */ 4536 if (acmd->islogical && 4537 (hdr->cmd_status == MFI_STAT_OK)) { 4538 display_scsi_inquiry( 4539 (caddr_t)inq); 4540 } else if ((hdr->cmd_status == 4541 MFI_STAT_OK) && inq->inq_dtype == 4542 DTYPE_DIRECT) { 4543 4544 display_scsi_inquiry( 4545 (caddr_t)inq); 4546 4547 /* for physical disk */ 4548 hdr->cmd_status = 4549 MFI_STAT_DEVICE_NOT_FOUND; 4550 } 4551 #endif /* PDSUPPORT */ 4552 } 4553 } 4554 4555 DTRACE_PROBE2(softintr_done, uint8_t, hdr->cmd, 4556 uint8_t, hdr->cmd_status); 4557 4558 switch (hdr->cmd_status) { 4559 case MFI_STAT_OK: 4560 pkt->pkt_scbp[0] = STATUS_GOOD; 4561 break; 4562 case MFI_STAT_LD_CC_IN_PROGRESS: 4563 case MFI_STAT_LD_RECON_IN_PROGRESS: 4564 pkt->pkt_scbp[0] = STATUS_GOOD; 4565 break; 4566 case MFI_STAT_LD_INIT_IN_PROGRESS: 4567 con_log(CL_ANN, 4568 (CE_WARN, "Initialization in Progress")); 4569 pkt->pkt_reason = CMD_TRAN_ERR; 4570 4571 break; 4572 case MFI_STAT_SCSI_DONE_WITH_ERROR: 4573 con_log(CL_ANN, (CE_CONT, "scsi_done error")); 4574 4575 pkt->pkt_reason = CMD_CMPLT; 4576 ((struct scsi_status *) 4577 pkt->pkt_scbp)->sts_chk = 1; 4578 4579 if (pkt->pkt_cdbp[0] == SCMD_TEST_UNIT_READY) { 4580 con_log(CL_ANN, 4581 (CE_WARN, "TEST_UNIT_READY fail")); 4582 } else { 4583 pkt->pkt_state |= STATE_ARQ_DONE; 4584 arqstat = (void *)(pkt->pkt_scbp); 4585 arqstat->sts_rqpkt_reason = CMD_CMPLT; 4586 arqstat->sts_rqpkt_resid = 0; 4587 arqstat->sts_rqpkt_state |= 4588 STATE_GOT_BUS | STATE_GOT_TARGET 4589 | STATE_SENT_CMD 4590 | STATE_XFERRED_DATA; 4591 *(uint8_t *)&arqstat->sts_rqpkt_status = 4592 STATUS_GOOD; 4593 ddi_rep_get8( 4594 cmd->frame_dma_obj.acc_handle, 4595 (uint8_t *) 4596 &(arqstat->sts_sensedata), 4597 cmd->sense, 4598 sizeof (struct scsi_extended_sense), 4599 DDI_DEV_AUTOINCR); 4600 } 4601 break; 4602 case MFI_STAT_LD_OFFLINE: 4603 case MFI_STAT_DEVICE_NOT_FOUND: 4604 con_log(CL_ANN, (CE_CONT, 4605 "mrsas_softintr:device not found error")); 4606 pkt->pkt_reason = CMD_DEV_GONE; 4607 pkt->pkt_statistics = STAT_DISCON; 4608 break; 4609 case MFI_STAT_LD_LBA_OUT_OF_RANGE: 4610 pkt->pkt_state |= STATE_ARQ_DONE; 4611 pkt->pkt_reason = CMD_CMPLT; 4612 ((struct scsi_status *) 4613 pkt->pkt_scbp)->sts_chk = 1; 4614 4615 arqstat = (void *)(pkt->pkt_scbp); 4616 arqstat->sts_rqpkt_reason = CMD_CMPLT; 4617 arqstat->sts_rqpkt_resid = 0; 4618 arqstat->sts_rqpkt_state |= STATE_GOT_BUS 4619 | STATE_GOT_TARGET | STATE_SENT_CMD 4620 | STATE_XFERRED_DATA; 4621 *(uint8_t *)&arqstat->sts_rqpkt_status = 4622 STATUS_GOOD; 4623 4624 arqstat->sts_sensedata.es_valid = 1; 4625 arqstat->sts_sensedata.es_key = 4626 KEY_ILLEGAL_REQUEST; 4627 arqstat->sts_sensedata.es_class = 4628 CLASS_EXTENDED_SENSE; 4629 4630 /* 4631 * LOGICAL BLOCK ADDRESS OUT OF RANGE: 4632 * ASC: 0x21h; ASCQ: 0x00h; 4633 */ 4634 arqstat->sts_sensedata.es_add_code = 0x21; 4635 arqstat->sts_sensedata.es_qual_code = 0x00; 4636 4637 break; 4638 4639 default: 4640 con_log(CL_ANN, (CE_CONT, "Unknown status!")); 4641 pkt->pkt_reason = CMD_TRAN_ERR; 4642 4643 break; 4644 } 4645 4646 atomic_add_16(&instance->fw_outstanding, (-1)); 4647 4648 (void) mrsas_common_check(instance, cmd); 4649 4650 if (acmd->cmd_dmahandle) { 4651 if (mrsas_check_dma_handle( 4652 acmd->cmd_dmahandle) != DDI_SUCCESS) { 4653 ddi_fm_service_impact(instance->dip, 4654 DDI_SERVICE_UNAFFECTED); 4655 pkt->pkt_reason = CMD_TRAN_ERR; 4656 pkt->pkt_statistics = 0; 4657 } 4658 } 4659 4660 mrsas_return_mfi_pkt(instance, cmd); 4661 4662 /* Call the callback routine */ 4663 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && 4664 pkt->pkt_comp) { 4665 (*pkt->pkt_comp)(pkt); 4666 } 4667 4668 break; 4669 4670 case MFI_CMD_OP_SMP: 4671 case MFI_CMD_OP_STP: 4672 complete_cmd_in_sync_mode(instance, cmd); 4673 break; 4674 4675 case MFI_CMD_OP_DCMD: 4676 /* see if got an event notification */ 4677 if (ddi_get32(cmd->frame_dma_obj.acc_handle, 4678 &cmd->frame->dcmd.opcode) == 4679 MR_DCMD_CTRL_EVENT_WAIT) { 4680 if ((instance->aen_cmd == cmd) && 4681 (instance->aen_cmd->abort_aen)) { 4682 con_log(CL_ANN, (CE_WARN, 4683 "mrsas_softintr: " 4684 "aborted_aen returned")); 4685 } else { 4686 atomic_add_16(&instance->fw_outstanding, 4687 (-1)); 4688 service_mfi_aen(instance, cmd); 4689 } 4690 } else { 4691 complete_cmd_in_sync_mode(instance, cmd); 4692 } 4693 4694 break; 4695 4696 case MFI_CMD_OP_ABORT: 4697 con_log(CL_ANN, (CE_NOTE, "MFI_CMD_OP_ABORT complete")); 4698 /* 4699 * MFI_CMD_OP_ABORT successfully completed 4700 * in the synchronous mode 4701 */ 4702 complete_cmd_in_sync_mode(instance, cmd); 4703 break; 4704 4705 default: 4706 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 4707 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 4708 4709 if (cmd->pkt != NULL) { 4710 pkt = cmd->pkt; 4711 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && 4712 pkt->pkt_comp) { 4713 4714 con_log(CL_ANN1, (CE_CONT, "posting to " 4715 "scsa cmd %p index %x pkt %p" 4716 "time %llx, default ", (void *)cmd, 4717 cmd->index, (void *)pkt, 4718 gethrtime())); 4719 4720 (*pkt->pkt_comp)(pkt); 4721 4722 } 4723 } 4724 con_log(CL_ANN, (CE_WARN, "Cmd type unknown !")); 4725 break; 4726 } 4727 } 4728 4729 instance->softint_running = 0; 4730 4731 return (DDI_INTR_CLAIMED); 4732 } 4733 4734 /* 4735 * mrsas_alloc_dma_obj 4736 * 4737 * Allocate the memory and other resources for an dma object. 4738 */ 4739 int 4740 mrsas_alloc_dma_obj(struct mrsas_instance *instance, dma_obj_t *obj, 4741 uchar_t endian_flags) 4742 { 4743 int i; 4744 size_t alen = 0; 4745 uint_t cookie_cnt; 4746 struct ddi_device_acc_attr tmp_endian_attr; 4747 4748 tmp_endian_attr = endian_attr; 4749 tmp_endian_attr.devacc_attr_endian_flags = endian_flags; 4750 tmp_endian_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4751 4752 i = ddi_dma_alloc_handle(instance->dip, &obj->dma_attr, 4753 DDI_DMA_SLEEP, NULL, &obj->dma_handle); 4754 if (i != DDI_SUCCESS) { 4755 4756 switch (i) { 4757 case DDI_DMA_BADATTR : 4758 con_log(CL_ANN, (CE_WARN, 4759 "Failed ddi_dma_alloc_handle- Bad attribute")); 4760 break; 4761 case DDI_DMA_NORESOURCES : 4762 con_log(CL_ANN, (CE_WARN, 4763 "Failed ddi_dma_alloc_handle- No Resources")); 4764 break; 4765 default : 4766 con_log(CL_ANN, (CE_WARN, 4767 "Failed ddi_dma_alloc_handle: " 4768 "unknown status %d", i)); 4769 break; 4770 } 4771 4772 return (-1); 4773 } 4774 4775 if ((ddi_dma_mem_alloc(obj->dma_handle, obj->size, &tmp_endian_attr, 4776 DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, 4777 &obj->buffer, &alen, &obj->acc_handle) != DDI_SUCCESS) || 4778 alen < obj->size) { 4779 4780 ddi_dma_free_handle(&obj->dma_handle); 4781 4782 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_mem_alloc")); 4783 4784 return (-1); 4785 } 4786 4787 if (ddi_dma_addr_bind_handle(obj->dma_handle, NULL, obj->buffer, 4788 obj->size, DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP, 4789 NULL, &obj->dma_cookie[0], &cookie_cnt) != DDI_SUCCESS) { 4790 4791 ddi_dma_mem_free(&obj->acc_handle); 4792 ddi_dma_free_handle(&obj->dma_handle); 4793 4794 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_addr_bind_handle")); 4795 4796 return (-1); 4797 } 4798 4799 if (mrsas_check_dma_handle(obj->dma_handle) != DDI_SUCCESS) { 4800 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 4801 return (-1); 4802 } 4803 4804 if (mrsas_check_acc_handle(obj->acc_handle) != DDI_SUCCESS) { 4805 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 4806 return (-1); 4807 } 4808 4809 return (cookie_cnt); 4810 } 4811 4812 /* 4813 * mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t) 4814 * 4815 * De-allocate the memory and other resources for an dma object, which must 4816 * have been alloated by a previous call to mrsas_alloc_dma_obj() 4817 */ 4818 int 4819 mrsas_free_dma_obj(struct mrsas_instance *instance, dma_obj_t obj) 4820 { 4821 4822 if ((obj.dma_handle == NULL) || (obj.acc_handle == NULL)) { 4823 return (DDI_SUCCESS); 4824 } 4825 4826 /* 4827 * NOTE: These check-handle functions fail if *_handle == NULL, but 4828 * this function succeeds because of the previous check. 4829 */ 4830 if (mrsas_check_dma_handle(obj.dma_handle) != DDI_SUCCESS) { 4831 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 4832 return (DDI_FAILURE); 4833 } 4834 4835 if (mrsas_check_acc_handle(obj.acc_handle) != DDI_SUCCESS) { 4836 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 4837 return (DDI_FAILURE); 4838 } 4839 4840 (void) ddi_dma_unbind_handle(obj.dma_handle); 4841 ddi_dma_mem_free(&obj.acc_handle); 4842 ddi_dma_free_handle(&obj.dma_handle); 4843 obj.acc_handle = NULL; 4844 return (DDI_SUCCESS); 4845 } 4846 4847 /* 4848 * mrsas_dma_alloc(instance_t *, struct scsi_pkt *, struct buf *, 4849 * int, int (*)()) 4850 * 4851 * Allocate dma resources for a new scsi command 4852 */ 4853 int 4854 mrsas_dma_alloc(struct mrsas_instance *instance, struct scsi_pkt *pkt, 4855 struct buf *bp, int flags, int (*callback)()) 4856 { 4857 int dma_flags; 4858 int (*cb)(caddr_t); 4859 int i; 4860 4861 ddi_dma_attr_t tmp_dma_attr = mrsas_generic_dma_attr; 4862 struct scsa_cmd *acmd = PKT2CMD(pkt); 4863 4864 acmd->cmd_buf = bp; 4865 4866 if (bp->b_flags & B_READ) { 4867 acmd->cmd_flags &= ~CFLAG_DMASEND; 4868 dma_flags = DDI_DMA_READ; 4869 } else { 4870 acmd->cmd_flags |= CFLAG_DMASEND; 4871 dma_flags = DDI_DMA_WRITE; 4872 } 4873 4874 if (flags & PKT_CONSISTENT) { 4875 acmd->cmd_flags |= CFLAG_CONSISTENT; 4876 dma_flags |= DDI_DMA_CONSISTENT; 4877 } 4878 4879 if (flags & PKT_DMA_PARTIAL) { 4880 dma_flags |= DDI_DMA_PARTIAL; 4881 } 4882 4883 dma_flags |= DDI_DMA_REDZONE; 4884 4885 cb = (callback == NULL_FUNC) ? DDI_DMA_DONTWAIT : DDI_DMA_SLEEP; 4886 4887 tmp_dma_attr.dma_attr_sgllen = instance->max_num_sge; 4888 tmp_dma_attr.dma_attr_addr_hi = 0xffffffffffffffffull; 4889 if (instance->tbolt) { 4890 /* OCR-RESET FIX */ 4891 tmp_dma_attr.dma_attr_count_max = 4892 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */ 4893 tmp_dma_attr.dma_attr_maxxfer = 4894 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */ 4895 } 4896 4897 if ((i = ddi_dma_alloc_handle(instance->dip, &tmp_dma_attr, 4898 cb, 0, &acmd->cmd_dmahandle)) != DDI_SUCCESS) { 4899 switch (i) { 4900 case DDI_DMA_BADATTR: 4901 bioerror(bp, EFAULT); 4902 return (DDI_FAILURE); 4903 4904 case DDI_DMA_NORESOURCES: 4905 bioerror(bp, 0); 4906 return (DDI_FAILURE); 4907 4908 default: 4909 con_log(CL_ANN, (CE_PANIC, "ddi_dma_alloc_handle: " 4910 "impossible result (0x%x)", i)); 4911 bioerror(bp, EFAULT); 4912 return (DDI_FAILURE); 4913 } 4914 } 4915 4916 i = ddi_dma_buf_bind_handle(acmd->cmd_dmahandle, bp, dma_flags, 4917 cb, 0, &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies); 4918 4919 switch (i) { 4920 case DDI_DMA_PARTIAL_MAP: 4921 if ((dma_flags & DDI_DMA_PARTIAL) == 0) { 4922 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: " 4923 "DDI_DMA_PARTIAL_MAP impossible")); 4924 goto no_dma_cookies; 4925 } 4926 4927 if (ddi_dma_numwin(acmd->cmd_dmahandle, &acmd->cmd_nwin) == 4928 DDI_FAILURE) { 4929 con_log(CL_ANN, (CE_PANIC, "ddi_dma_numwin failed")); 4930 goto no_dma_cookies; 4931 } 4932 4933 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin, 4934 &acmd->cmd_dma_offset, &acmd->cmd_dma_len, 4935 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) == 4936 DDI_FAILURE) { 4937 4938 con_log(CL_ANN, (CE_PANIC, "ddi_dma_getwin failed")); 4939 goto no_dma_cookies; 4940 } 4941 4942 goto get_dma_cookies; 4943 case DDI_DMA_MAPPED: 4944 acmd->cmd_nwin = 1; 4945 acmd->cmd_dma_len = 0; 4946 acmd->cmd_dma_offset = 0; 4947 4948 get_dma_cookies: 4949 i = 0; 4950 acmd->cmd_dmacount = 0; 4951 for (;;) { 4952 acmd->cmd_dmacount += 4953 acmd->cmd_dmacookies[i++].dmac_size; 4954 4955 if (i == instance->max_num_sge || 4956 i == acmd->cmd_ncookies) 4957 break; 4958 4959 ddi_dma_nextcookie(acmd->cmd_dmahandle, 4960 &acmd->cmd_dmacookies[i]); 4961 } 4962 4963 acmd->cmd_cookie = i; 4964 acmd->cmd_cookiecnt = i; 4965 4966 acmd->cmd_flags |= CFLAG_DMAVALID; 4967 4968 if (bp->b_bcount >= acmd->cmd_dmacount) { 4969 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount; 4970 } else { 4971 pkt->pkt_resid = 0; 4972 } 4973 4974 return (DDI_SUCCESS); 4975 case DDI_DMA_NORESOURCES: 4976 bioerror(bp, 0); 4977 break; 4978 case DDI_DMA_NOMAPPING: 4979 bioerror(bp, EFAULT); 4980 break; 4981 case DDI_DMA_TOOBIG: 4982 bioerror(bp, EINVAL); 4983 break; 4984 case DDI_DMA_INUSE: 4985 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle:" 4986 " DDI_DMA_INUSE impossible")); 4987 break; 4988 default: 4989 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: " 4990 "impossible result (0x%x)", i)); 4991 break; 4992 } 4993 4994 no_dma_cookies: 4995 ddi_dma_free_handle(&acmd->cmd_dmahandle); 4996 acmd->cmd_dmahandle = NULL; 4997 acmd->cmd_flags &= ~CFLAG_DMAVALID; 4998 return (DDI_FAILURE); 4999 } 5000 5001 /* 5002 * mrsas_dma_move(struct mrsas_instance *, struct scsi_pkt *, struct buf *) 5003 * 5004 * move dma resources to next dma window 5005 * 5006 */ 5007 int 5008 mrsas_dma_move(struct mrsas_instance *instance, struct scsi_pkt *pkt, 5009 struct buf *bp) 5010 { 5011 int i = 0; 5012 5013 struct scsa_cmd *acmd = PKT2CMD(pkt); 5014 5015 /* 5016 * If there are no more cookies remaining in this window, 5017 * must move to the next window first. 5018 */ 5019 if (acmd->cmd_cookie == acmd->cmd_ncookies) { 5020 if (acmd->cmd_curwin == acmd->cmd_nwin && acmd->cmd_nwin == 1) { 5021 return (DDI_SUCCESS); 5022 } 5023 5024 /* at last window, cannot move */ 5025 if (++acmd->cmd_curwin >= acmd->cmd_nwin) { 5026 return (DDI_FAILURE); 5027 } 5028 5029 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin, 5030 &acmd->cmd_dma_offset, &acmd->cmd_dma_len, 5031 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) == 5032 DDI_FAILURE) { 5033 return (DDI_FAILURE); 5034 } 5035 5036 acmd->cmd_cookie = 0; 5037 } else { 5038 /* still more cookies in this window - get the next one */ 5039 ddi_dma_nextcookie(acmd->cmd_dmahandle, 5040 &acmd->cmd_dmacookies[0]); 5041 } 5042 5043 /* get remaining cookies in this window, up to our maximum */ 5044 for (;;) { 5045 acmd->cmd_dmacount += acmd->cmd_dmacookies[i++].dmac_size; 5046 acmd->cmd_cookie++; 5047 5048 if (i == instance->max_num_sge || 5049 acmd->cmd_cookie == acmd->cmd_ncookies) { 5050 break; 5051 } 5052 5053 ddi_dma_nextcookie(acmd->cmd_dmahandle, 5054 &acmd->cmd_dmacookies[i]); 5055 } 5056 5057 acmd->cmd_cookiecnt = i; 5058 5059 if (bp->b_bcount >= acmd->cmd_dmacount) { 5060 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount; 5061 } else { 5062 pkt->pkt_resid = 0; 5063 } 5064 5065 return (DDI_SUCCESS); 5066 } 5067 5068 /* 5069 * build_cmd 5070 */ 5071 static struct mrsas_cmd * 5072 build_cmd(struct mrsas_instance *instance, struct scsi_address *ap, 5073 struct scsi_pkt *pkt, uchar_t *cmd_done) 5074 { 5075 uint16_t flags = 0; 5076 uint32_t i; 5077 uint32_t context; 5078 uint32_t sge_bytes; 5079 uint32_t tmp_data_xfer_len; 5080 ddi_acc_handle_t acc_handle; 5081 struct mrsas_cmd *cmd; 5082 struct mrsas_sge64 *mfi_sgl; 5083 struct mrsas_sge_ieee *mfi_sgl_ieee; 5084 struct scsa_cmd *acmd = PKT2CMD(pkt); 5085 struct mrsas_pthru_frame *pthru; 5086 struct mrsas_io_frame *ldio; 5087 5088 /* find out if this is logical or physical drive command. */ 5089 acmd->islogical = MRDRV_IS_LOGICAL(ap); 5090 acmd->device_id = MAP_DEVICE_ID(instance, ap); 5091 *cmd_done = 0; 5092 5093 /* get the command packet */ 5094 if (!(cmd = mrsas_get_mfi_pkt(instance))) { 5095 DTRACE_PROBE2(build_cmd_mfi_err, uint16_t, 5096 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 5097 return (NULL); 5098 } 5099 5100 acc_handle = cmd->frame_dma_obj.acc_handle; 5101 5102 /* Clear the frame buffer and assign back the context id */ 5103 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 5104 ddi_put32(acc_handle, &cmd->frame->hdr.context, cmd->index); 5105 5106 cmd->pkt = pkt; 5107 cmd->cmd = acmd; 5108 DTRACE_PROBE3(build_cmds, uint8_t, pkt->pkt_cdbp[0], 5109 ulong_t, acmd->cmd_dmacount, ulong_t, acmd->cmd_dma_len); 5110 5111 /* lets get the command directions */ 5112 if (acmd->cmd_flags & CFLAG_DMASEND) { 5113 flags = MFI_FRAME_DIR_WRITE; 5114 5115 if (acmd->cmd_flags & CFLAG_CONSISTENT) { 5116 (void) ddi_dma_sync(acmd->cmd_dmahandle, 5117 acmd->cmd_dma_offset, acmd->cmd_dma_len, 5118 DDI_DMA_SYNC_FORDEV); 5119 } 5120 } else if (acmd->cmd_flags & ~CFLAG_DMASEND) { 5121 flags = MFI_FRAME_DIR_READ; 5122 5123 if (acmd->cmd_flags & CFLAG_CONSISTENT) { 5124 (void) ddi_dma_sync(acmd->cmd_dmahandle, 5125 acmd->cmd_dma_offset, acmd->cmd_dma_len, 5126 DDI_DMA_SYNC_FORCPU); 5127 } 5128 } else { 5129 flags = MFI_FRAME_DIR_NONE; 5130 } 5131 5132 if (instance->flag_ieee) { 5133 flags |= MFI_FRAME_IEEE; 5134 } 5135 flags |= MFI_FRAME_SGL64; 5136 5137 switch (pkt->pkt_cdbp[0]) { 5138 5139 /* 5140 * case SCMD_SYNCHRONIZE_CACHE: 5141 * flush_cache(instance); 5142 * mrsas_return_mfi_pkt(instance, cmd); 5143 * *cmd_done = 1; 5144 * 5145 * return (NULL); 5146 */ 5147 5148 case SCMD_READ: 5149 case SCMD_WRITE: 5150 case SCMD_READ_G1: 5151 case SCMD_WRITE_G1: 5152 case SCMD_READ_G4: 5153 case SCMD_WRITE_G4: 5154 case SCMD_READ_G5: 5155 case SCMD_WRITE_G5: 5156 if (acmd->islogical) { 5157 ldio = (struct mrsas_io_frame *)cmd->frame; 5158 5159 /* 5160 * preare the Logical IO frame: 5161 * 2nd bit is zero for all read cmds 5162 */ 5163 ddi_put8(acc_handle, &ldio->cmd, 5164 (pkt->pkt_cdbp[0] & 0x02) ? MFI_CMD_OP_LD_WRITE 5165 : MFI_CMD_OP_LD_READ); 5166 ddi_put8(acc_handle, &ldio->cmd_status, 0x0); 5167 ddi_put8(acc_handle, &ldio->scsi_status, 0x0); 5168 ddi_put8(acc_handle, &ldio->target_id, acmd->device_id); 5169 ddi_put16(acc_handle, &ldio->timeout, 0); 5170 ddi_put8(acc_handle, &ldio->reserved_0, 0); 5171 ddi_put16(acc_handle, &ldio->pad_0, 0); 5172 ddi_put16(acc_handle, &ldio->flags, flags); 5173 5174 /* Initialize sense Information */ 5175 bzero(cmd->sense, SENSE_LENGTH); 5176 ddi_put8(acc_handle, &ldio->sense_len, SENSE_LENGTH); 5177 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_hi, 0); 5178 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_lo, 5179 cmd->sense_phys_addr); 5180 ddi_put32(acc_handle, &ldio->start_lba_hi, 0); 5181 ddi_put8(acc_handle, &ldio->access_byte, 5182 (acmd->cmd_cdblen != 6) ? pkt->pkt_cdbp[1] : 0); 5183 ddi_put8(acc_handle, &ldio->sge_count, 5184 acmd->cmd_cookiecnt); 5185 if (instance->flag_ieee) { 5186 mfi_sgl_ieee = 5187 (struct mrsas_sge_ieee *)&ldio->sgl; 5188 } else { 5189 mfi_sgl = (struct mrsas_sge64 *)&ldio->sgl; 5190 } 5191 5192 context = ddi_get32(acc_handle, &ldio->context); 5193 5194 if (acmd->cmd_cdblen == CDB_GROUP0) { 5195 /* 6-byte cdb */ 5196 ddi_put32(acc_handle, &ldio->lba_count, ( 5197 (uint16_t)(pkt->pkt_cdbp[4]))); 5198 5199 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 5200 ((uint32_t)(pkt->pkt_cdbp[3])) | 5201 ((uint32_t)(pkt->pkt_cdbp[2]) << 8) | 5202 ((uint32_t)((pkt->pkt_cdbp[1]) & 0x1F) 5203 << 16))); 5204 } else if (acmd->cmd_cdblen == CDB_GROUP1) { 5205 /* 10-byte cdb */ 5206 ddi_put32(acc_handle, &ldio->lba_count, ( 5207 ((uint16_t)(pkt->pkt_cdbp[8])) | 5208 ((uint16_t)(pkt->pkt_cdbp[7]) << 8))); 5209 5210 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 5211 ((uint32_t)(pkt->pkt_cdbp[5])) | 5212 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) | 5213 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) | 5214 ((uint32_t)(pkt->pkt_cdbp[2]) << 24))); 5215 } else if (acmd->cmd_cdblen == CDB_GROUP5) { 5216 /* 12-byte cdb */ 5217 ddi_put32(acc_handle, &ldio->lba_count, ( 5218 ((uint32_t)(pkt->pkt_cdbp[9])) | 5219 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) | 5220 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) | 5221 ((uint32_t)(pkt->pkt_cdbp[6]) << 24))); 5222 5223 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 5224 ((uint32_t)(pkt->pkt_cdbp[5])) | 5225 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) | 5226 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) | 5227 ((uint32_t)(pkt->pkt_cdbp[2]) << 24))); 5228 } else if (acmd->cmd_cdblen == CDB_GROUP4) { 5229 /* 16-byte cdb */ 5230 ddi_put32(acc_handle, &ldio->lba_count, ( 5231 ((uint32_t)(pkt->pkt_cdbp[13])) | 5232 ((uint32_t)(pkt->pkt_cdbp[12]) << 8) | 5233 ((uint32_t)(pkt->pkt_cdbp[11]) << 16) | 5234 ((uint32_t)(pkt->pkt_cdbp[10]) << 24))); 5235 5236 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 5237 ((uint32_t)(pkt->pkt_cdbp[9])) | 5238 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) | 5239 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) | 5240 ((uint32_t)(pkt->pkt_cdbp[6]) << 24))); 5241 5242 ddi_put32(acc_handle, &ldio->start_lba_hi, ( 5243 ((uint32_t)(pkt->pkt_cdbp[5])) | 5244 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) | 5245 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) | 5246 ((uint32_t)(pkt->pkt_cdbp[2]) << 24))); 5247 } 5248 5249 break; 5250 } 5251 /* fall through For all non-rd/wr and physical disk cmds */ 5252 default: 5253 5254 switch (pkt->pkt_cdbp[0]) { 5255 case SCMD_MODE_SENSE: 5256 case SCMD_MODE_SENSE_G1: { 5257 union scsi_cdb *cdbp; 5258 uint16_t page_code; 5259 5260 cdbp = (void *)pkt->pkt_cdbp; 5261 page_code = (uint16_t)cdbp->cdb_un.sg.scsi[0]; 5262 switch (page_code) { 5263 case 0x3: 5264 case 0x4: 5265 (void) mrsas_mode_sense_build(pkt); 5266 mrsas_return_mfi_pkt(instance, cmd); 5267 *cmd_done = 1; 5268 return (NULL); 5269 } 5270 break; 5271 } 5272 default: 5273 break; 5274 } 5275 5276 pthru = (struct mrsas_pthru_frame *)cmd->frame; 5277 5278 /* prepare the DCDB frame */ 5279 ddi_put8(acc_handle, &pthru->cmd, (acmd->islogical) ? 5280 MFI_CMD_OP_LD_SCSI : MFI_CMD_OP_PD_SCSI); 5281 ddi_put8(acc_handle, &pthru->cmd_status, 0x0); 5282 ddi_put8(acc_handle, &pthru->scsi_status, 0x0); 5283 ddi_put8(acc_handle, &pthru->target_id, acmd->device_id); 5284 ddi_put8(acc_handle, &pthru->lun, 0); 5285 ddi_put8(acc_handle, &pthru->cdb_len, acmd->cmd_cdblen); 5286 ddi_put16(acc_handle, &pthru->timeout, 0); 5287 ddi_put16(acc_handle, &pthru->flags, flags); 5288 tmp_data_xfer_len = 0; 5289 for (i = 0; i < acmd->cmd_cookiecnt; i++) { 5290 tmp_data_xfer_len += acmd->cmd_dmacookies[i].dmac_size; 5291 } 5292 ddi_put32(acc_handle, &pthru->data_xfer_len, 5293 tmp_data_xfer_len); 5294 ddi_put8(acc_handle, &pthru->sge_count, acmd->cmd_cookiecnt); 5295 if (instance->flag_ieee) { 5296 mfi_sgl_ieee = (struct mrsas_sge_ieee *)&pthru->sgl; 5297 } else { 5298 mfi_sgl = (struct mrsas_sge64 *)&pthru->sgl; 5299 } 5300 5301 bzero(cmd->sense, SENSE_LENGTH); 5302 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH); 5303 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0); 5304 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo, 5305 cmd->sense_phys_addr); 5306 5307 context = ddi_get32(acc_handle, &pthru->context); 5308 ddi_rep_put8(acc_handle, (uint8_t *)pkt->pkt_cdbp, 5309 (uint8_t *)pthru->cdb, acmd->cmd_cdblen, DDI_DEV_AUTOINCR); 5310 5311 break; 5312 } 5313 #ifdef lint 5314 context = context; 5315 #endif 5316 /* prepare the scatter-gather list for the firmware */ 5317 if (instance->flag_ieee) { 5318 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl_ieee++) { 5319 ddi_put64(acc_handle, &mfi_sgl_ieee->phys_addr, 5320 acmd->cmd_dmacookies[i].dmac_laddress); 5321 ddi_put32(acc_handle, &mfi_sgl_ieee->length, 5322 acmd->cmd_dmacookies[i].dmac_size); 5323 } 5324 sge_bytes = sizeof (struct mrsas_sge_ieee)*acmd->cmd_cookiecnt; 5325 } else { 5326 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl++) { 5327 ddi_put64(acc_handle, &mfi_sgl->phys_addr, 5328 acmd->cmd_dmacookies[i].dmac_laddress); 5329 ddi_put32(acc_handle, &mfi_sgl->length, 5330 acmd->cmd_dmacookies[i].dmac_size); 5331 } 5332 sge_bytes = sizeof (struct mrsas_sge64)*acmd->cmd_cookiecnt; 5333 } 5334 5335 cmd->frame_count = (sge_bytes / MRMFI_FRAME_SIZE) + 5336 ((sge_bytes % MRMFI_FRAME_SIZE) ? 1 : 0) + 1; 5337 5338 if (cmd->frame_count >= 8) { 5339 cmd->frame_count = 8; 5340 } 5341 5342 return (cmd); 5343 } 5344 5345 /* 5346 * wait_for_outstanding - Wait for all outstanding cmds 5347 * @instance: Adapter soft state 5348 * 5349 * This function waits for upto MRDRV_RESET_WAIT_TIME seconds for FW to 5350 * complete all its outstanding commands. Returns error if one or more IOs 5351 * are pending after this time period. 5352 */ 5353 static int 5354 wait_for_outstanding(struct mrsas_instance *instance) 5355 { 5356 int i; 5357 uint32_t wait_time = 90; 5358 5359 for (i = 0; i < wait_time; i++) { 5360 if (!instance->fw_outstanding) { 5361 break; 5362 } 5363 5364 drv_usecwait(MILLISEC); /* wait for 1000 usecs */; 5365 } 5366 5367 if (instance->fw_outstanding) { 5368 return (1); 5369 } 5370 5371 return (0); 5372 } 5373 5374 /* 5375 * issue_mfi_pthru 5376 */ 5377 static int 5378 issue_mfi_pthru(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 5379 struct mrsas_cmd *cmd, int mode) 5380 { 5381 void *ubuf; 5382 uint32_t kphys_addr = 0; 5383 uint32_t xferlen = 0; 5384 uint32_t new_xfer_length = 0; 5385 uint_t model; 5386 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 5387 dma_obj_t pthru_dma_obj; 5388 struct mrsas_pthru_frame *kpthru; 5389 struct mrsas_pthru_frame *pthru; 5390 int i; 5391 pthru = &cmd->frame->pthru; 5392 kpthru = (struct mrsas_pthru_frame *)&ioctl->frame[0]; 5393 5394 if (instance->adapterresetinprogress) { 5395 con_log(CL_ANN1, (CE_WARN, "issue_mfi_pthru: Reset flag set, " 5396 "returning mfi_pkt and setting TRAN_BUSY\n")); 5397 return (DDI_FAILURE); 5398 } 5399 model = ddi_model_convert_from(mode & FMODELS); 5400 if (model == DDI_MODEL_ILP32) { 5401 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32")); 5402 5403 xferlen = kpthru->sgl.sge32[0].length; 5404 5405 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr; 5406 } else { 5407 #ifdef _ILP32 5408 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32")); 5409 xferlen = kpthru->sgl.sge32[0].length; 5410 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr; 5411 #else 5412 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP64")); 5413 xferlen = kpthru->sgl.sge64[0].length; 5414 ubuf = (void *)(ulong_t)kpthru->sgl.sge64[0].phys_addr; 5415 #endif 5416 } 5417 5418 if (xferlen) { 5419 /* means IOCTL requires DMA */ 5420 /* allocate the data transfer buffer */ 5421 /* pthru_dma_obj.size = xferlen; */ 5422 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length, 5423 PAGESIZE); 5424 pthru_dma_obj.size = new_xfer_length; 5425 pthru_dma_obj.dma_attr = mrsas_generic_dma_attr; 5426 pthru_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 5427 pthru_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 5428 pthru_dma_obj.dma_attr.dma_attr_sgllen = 1; 5429 pthru_dma_obj.dma_attr.dma_attr_align = 1; 5430 5431 /* allocate kernel buffer for DMA */ 5432 if (mrsas_alloc_dma_obj(instance, &pthru_dma_obj, 5433 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 5434 con_log(CL_ANN, (CE_WARN, "issue_mfi_pthru: " 5435 "could not allocate data transfer buffer.")); 5436 return (DDI_FAILURE); 5437 } 5438 (void) memset(pthru_dma_obj.buffer, 0, xferlen); 5439 5440 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 5441 if (kpthru->flags & MFI_FRAME_DIR_WRITE) { 5442 for (i = 0; i < xferlen; i++) { 5443 if (ddi_copyin((uint8_t *)ubuf+i, 5444 (uint8_t *)pthru_dma_obj.buffer+i, 5445 1, mode)) { 5446 con_log(CL_ANN, (CE_WARN, 5447 "issue_mfi_pthru : " 5448 "copy from user space failed")); 5449 return (DDI_FAILURE); 5450 } 5451 } 5452 } 5453 5454 kphys_addr = pthru_dma_obj.dma_cookie[0].dmac_address; 5455 } 5456 5457 ddi_put8(acc_handle, &pthru->cmd, kpthru->cmd); 5458 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH); 5459 ddi_put8(acc_handle, &pthru->cmd_status, 0); 5460 ddi_put8(acc_handle, &pthru->scsi_status, 0); 5461 ddi_put8(acc_handle, &pthru->target_id, kpthru->target_id); 5462 ddi_put8(acc_handle, &pthru->lun, kpthru->lun); 5463 ddi_put8(acc_handle, &pthru->cdb_len, kpthru->cdb_len); 5464 ddi_put8(acc_handle, &pthru->sge_count, kpthru->sge_count); 5465 ddi_put16(acc_handle, &pthru->timeout, kpthru->timeout); 5466 ddi_put32(acc_handle, &pthru->data_xfer_len, kpthru->data_xfer_len); 5467 5468 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0); 5469 pthru->sense_buf_phys_addr_lo = cmd->sense_phys_addr; 5470 /* ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo, 0); */ 5471 5472 ddi_rep_put8(acc_handle, (uint8_t *)kpthru->cdb, (uint8_t *)pthru->cdb, 5473 pthru->cdb_len, DDI_DEV_AUTOINCR); 5474 5475 ddi_put16(acc_handle, &pthru->flags, kpthru->flags & ~MFI_FRAME_SGL64); 5476 ddi_put32(acc_handle, &pthru->sgl.sge32[0].length, xferlen); 5477 ddi_put32(acc_handle, &pthru->sgl.sge32[0].phys_addr, kphys_addr); 5478 5479 cmd->sync_cmd = MRSAS_TRUE; 5480 cmd->frame_count = 1; 5481 5482 if (instance->tbolt) { 5483 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 5484 } 5485 5486 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 5487 con_log(CL_ANN, (CE_WARN, 5488 "issue_mfi_pthru: fw_ioctl failed")); 5489 } else { 5490 if (xferlen && kpthru->flags & MFI_FRAME_DIR_READ) { 5491 for (i = 0; i < xferlen; i++) { 5492 if (ddi_copyout( 5493 (uint8_t *)pthru_dma_obj.buffer+i, 5494 (uint8_t *)ubuf+i, 1, mode)) { 5495 con_log(CL_ANN, (CE_WARN, 5496 "issue_mfi_pthru : " 5497 "copy to user space failed")); 5498 return (DDI_FAILURE); 5499 } 5500 } 5501 } 5502 } 5503 5504 kpthru->cmd_status = ddi_get8(acc_handle, &pthru->cmd_status); 5505 kpthru->scsi_status = ddi_get8(acc_handle, &pthru->scsi_status); 5506 5507 con_log(CL_ANN, (CE_CONT, "issue_mfi_pthru: cmd_status %x, " 5508 "scsi_status %x", kpthru->cmd_status, kpthru->scsi_status)); 5509 DTRACE_PROBE3(issue_pthru, uint8_t, kpthru->cmd, uint8_t, 5510 kpthru->cmd_status, uint8_t, kpthru->scsi_status); 5511 5512 if (kpthru->sense_len) { 5513 uint_t sense_len = SENSE_LENGTH; 5514 void *sense_ubuf = 5515 (void *)(ulong_t)kpthru->sense_buf_phys_addr_lo; 5516 if (kpthru->sense_len <= SENSE_LENGTH) { 5517 sense_len = kpthru->sense_len; 5518 } 5519 5520 for (i = 0; i < sense_len; i++) { 5521 if (ddi_copyout( 5522 (uint8_t *)cmd->sense+i, 5523 (uint8_t *)sense_ubuf+i, 1, mode)) { 5524 con_log(CL_ANN, (CE_WARN, 5525 "issue_mfi_pthru : " 5526 "copy to user space failed")); 5527 } 5528 con_log(CL_DLEVEL1, (CE_WARN, 5529 "Copying Sense info sense_buff[%d] = 0x%X", 5530 i, *((uint8_t *)cmd->sense + i))); 5531 } 5532 } 5533 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0, 5534 DDI_DMA_SYNC_FORDEV); 5535 5536 if (xferlen) { 5537 /* free kernel buffer */ 5538 if (mrsas_free_dma_obj(instance, pthru_dma_obj) != DDI_SUCCESS) 5539 return (DDI_FAILURE); 5540 } 5541 5542 return (DDI_SUCCESS); 5543 } 5544 5545 /* 5546 * issue_mfi_dcmd 5547 */ 5548 static int 5549 issue_mfi_dcmd(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 5550 struct mrsas_cmd *cmd, int mode) 5551 { 5552 void *ubuf; 5553 uint32_t kphys_addr = 0; 5554 uint32_t xferlen = 0; 5555 uint32_t new_xfer_length = 0; 5556 uint32_t model; 5557 dma_obj_t dcmd_dma_obj; 5558 struct mrsas_dcmd_frame *kdcmd; 5559 struct mrsas_dcmd_frame *dcmd; 5560 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 5561 int i; 5562 dcmd = &cmd->frame->dcmd; 5563 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0]; 5564 5565 if (instance->adapterresetinprogress) { 5566 con_log(CL_ANN1, (CE_NOTE, "Reset flag set, " 5567 "returning mfi_pkt and setting TRAN_BUSY")); 5568 return (DDI_FAILURE); 5569 } 5570 model = ddi_model_convert_from(mode & FMODELS); 5571 if (model == DDI_MODEL_ILP32) { 5572 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32")); 5573 5574 xferlen = kdcmd->sgl.sge32[0].length; 5575 5576 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 5577 } else { 5578 #ifdef _ILP32 5579 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32")); 5580 xferlen = kdcmd->sgl.sge32[0].length; 5581 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 5582 #else 5583 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_LP64")); 5584 xferlen = kdcmd->sgl.sge64[0].length; 5585 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr; 5586 #endif 5587 } 5588 if (xferlen) { 5589 /* means IOCTL requires DMA */ 5590 /* allocate the data transfer buffer */ 5591 /* dcmd_dma_obj.size = xferlen; */ 5592 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length, 5593 PAGESIZE); 5594 dcmd_dma_obj.size = new_xfer_length; 5595 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr; 5596 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 5597 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 5598 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1; 5599 dcmd_dma_obj.dma_attr.dma_attr_align = 1; 5600 5601 /* allocate kernel buffer for DMA */ 5602 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj, 5603 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 5604 con_log(CL_ANN, 5605 (CE_WARN, "issue_mfi_dcmd: could not " 5606 "allocate data transfer buffer.")); 5607 return (DDI_FAILURE); 5608 } 5609 (void) memset(dcmd_dma_obj.buffer, 0, xferlen); 5610 5611 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 5612 if (kdcmd->flags & MFI_FRAME_DIR_WRITE) { 5613 for (i = 0; i < xferlen; i++) { 5614 if (ddi_copyin((uint8_t *)ubuf + i, 5615 (uint8_t *)dcmd_dma_obj.buffer + i, 5616 1, mode)) { 5617 con_log(CL_ANN, (CE_WARN, 5618 "issue_mfi_dcmd : " 5619 "copy from user space failed")); 5620 return (DDI_FAILURE); 5621 } 5622 } 5623 } 5624 5625 kphys_addr = dcmd_dma_obj.dma_cookie[0].dmac_address; 5626 } 5627 5628 ddi_put8(acc_handle, &dcmd->cmd, kdcmd->cmd); 5629 ddi_put8(acc_handle, &dcmd->cmd_status, 0); 5630 ddi_put8(acc_handle, &dcmd->sge_count, kdcmd->sge_count); 5631 ddi_put16(acc_handle, &dcmd->timeout, kdcmd->timeout); 5632 ddi_put32(acc_handle, &dcmd->data_xfer_len, kdcmd->data_xfer_len); 5633 ddi_put32(acc_handle, &dcmd->opcode, kdcmd->opcode); 5634 5635 ddi_rep_put8(acc_handle, (uint8_t *)kdcmd->mbox.b, 5636 (uint8_t *)dcmd->mbox.b, DCMD_MBOX_SZ, DDI_DEV_AUTOINCR); 5637 5638 ddi_put16(acc_handle, &dcmd->flags, kdcmd->flags & ~MFI_FRAME_SGL64); 5639 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].length, xferlen); 5640 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].phys_addr, kphys_addr); 5641 5642 cmd->sync_cmd = MRSAS_TRUE; 5643 cmd->frame_count = 1; 5644 5645 if (instance->tbolt) { 5646 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 5647 } 5648 5649 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 5650 con_log(CL_ANN, (CE_WARN, "issue_mfi_dcmd: fw_ioctl failed")); 5651 } else { 5652 if (xferlen && (kdcmd->flags & MFI_FRAME_DIR_READ)) { 5653 for (i = 0; i < xferlen; i++) { 5654 if (ddi_copyout( 5655 (uint8_t *)dcmd_dma_obj.buffer + i, 5656 (uint8_t *)ubuf + i, 5657 1, mode)) { 5658 con_log(CL_ANN, (CE_WARN, 5659 "issue_mfi_dcmd : " 5660 "copy to user space failed")); 5661 return (DDI_FAILURE); 5662 } 5663 } 5664 } 5665 } 5666 5667 kdcmd->cmd_status = ddi_get8(acc_handle, &dcmd->cmd_status); 5668 con_log(CL_ANN, 5669 (CE_CONT, "issue_mfi_dcmd: cmd_status %x", kdcmd->cmd_status)); 5670 DTRACE_PROBE3(issue_dcmd, uint32_t, kdcmd->opcode, uint8_t, 5671 kdcmd->cmd, uint8_t, kdcmd->cmd_status); 5672 5673 if (xferlen) { 5674 /* free kernel buffer */ 5675 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS) 5676 return (DDI_FAILURE); 5677 } 5678 5679 return (DDI_SUCCESS); 5680 } 5681 5682 /* 5683 * issue_mfi_smp 5684 */ 5685 static int 5686 issue_mfi_smp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 5687 struct mrsas_cmd *cmd, int mode) 5688 { 5689 void *request_ubuf; 5690 void *response_ubuf; 5691 uint32_t request_xferlen = 0; 5692 uint32_t response_xferlen = 0; 5693 uint32_t new_xfer_length1 = 0; 5694 uint32_t new_xfer_length2 = 0; 5695 uint_t model; 5696 dma_obj_t request_dma_obj; 5697 dma_obj_t response_dma_obj; 5698 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 5699 struct mrsas_smp_frame *ksmp; 5700 struct mrsas_smp_frame *smp; 5701 struct mrsas_sge32 *sge32; 5702 #ifndef _ILP32 5703 struct mrsas_sge64 *sge64; 5704 #endif 5705 int i; 5706 uint64_t tmp_sas_addr; 5707 5708 smp = &cmd->frame->smp; 5709 ksmp = (struct mrsas_smp_frame *)&ioctl->frame[0]; 5710 5711 if (instance->adapterresetinprogress) { 5712 con_log(CL_ANN1, (CE_WARN, "Reset flag set, " 5713 "returning mfi_pkt and setting TRAN_BUSY\n")); 5714 return (DDI_FAILURE); 5715 } 5716 model = ddi_model_convert_from(mode & FMODELS); 5717 if (model == DDI_MODEL_ILP32) { 5718 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32")); 5719 5720 sge32 = &ksmp->sgl[0].sge32[0]; 5721 response_xferlen = sge32[0].length; 5722 request_xferlen = sge32[1].length; 5723 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: " 5724 "response_xferlen = %x, request_xferlen = %x", 5725 response_xferlen, request_xferlen)); 5726 5727 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr; 5728 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr; 5729 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: " 5730 "response_ubuf = %p, request_ubuf = %p", 5731 response_ubuf, request_ubuf)); 5732 } else { 5733 #ifdef _ILP32 5734 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32")); 5735 5736 sge32 = &ksmp->sgl[0].sge32[0]; 5737 response_xferlen = sge32[0].length; 5738 request_xferlen = sge32[1].length; 5739 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: " 5740 "response_xferlen = %x, request_xferlen = %x", 5741 response_xferlen, request_xferlen)); 5742 5743 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr; 5744 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr; 5745 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: " 5746 "response_ubuf = %p, request_ubuf = %p", 5747 response_ubuf, request_ubuf)); 5748 #else 5749 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_LP64")); 5750 5751 sge64 = &ksmp->sgl[0].sge64[0]; 5752 response_xferlen = sge64[0].length; 5753 request_xferlen = sge64[1].length; 5754 5755 response_ubuf = (void *)(ulong_t)sge64[0].phys_addr; 5756 request_ubuf = (void *)(ulong_t)sge64[1].phys_addr; 5757 #endif 5758 } 5759 if (request_xferlen) { 5760 /* means IOCTL requires DMA */ 5761 /* allocate the data transfer buffer */ 5762 /* request_dma_obj.size = request_xferlen; */ 5763 MRSAS_GET_BOUNDARY_ALIGNED_LEN(request_xferlen, 5764 new_xfer_length1, PAGESIZE); 5765 request_dma_obj.size = new_xfer_length1; 5766 request_dma_obj.dma_attr = mrsas_generic_dma_attr; 5767 request_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 5768 request_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 5769 request_dma_obj.dma_attr.dma_attr_sgllen = 1; 5770 request_dma_obj.dma_attr.dma_attr_align = 1; 5771 5772 /* allocate kernel buffer for DMA */ 5773 if (mrsas_alloc_dma_obj(instance, &request_dma_obj, 5774 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 5775 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 5776 "could not allocate data transfer buffer.")); 5777 return (DDI_FAILURE); 5778 } 5779 (void) memset(request_dma_obj.buffer, 0, request_xferlen); 5780 5781 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 5782 for (i = 0; i < request_xferlen; i++) { 5783 if (ddi_copyin((uint8_t *)request_ubuf + i, 5784 (uint8_t *)request_dma_obj.buffer + i, 5785 1, mode)) { 5786 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 5787 "copy from user space failed")); 5788 return (DDI_FAILURE); 5789 } 5790 } 5791 } 5792 5793 if (response_xferlen) { 5794 /* means IOCTL requires DMA */ 5795 /* allocate the data transfer buffer */ 5796 /* response_dma_obj.size = response_xferlen; */ 5797 MRSAS_GET_BOUNDARY_ALIGNED_LEN(response_xferlen, 5798 new_xfer_length2, PAGESIZE); 5799 response_dma_obj.size = new_xfer_length2; 5800 response_dma_obj.dma_attr = mrsas_generic_dma_attr; 5801 response_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 5802 response_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 5803 response_dma_obj.dma_attr.dma_attr_sgllen = 1; 5804 response_dma_obj.dma_attr.dma_attr_align = 1; 5805 5806 /* allocate kernel buffer for DMA */ 5807 if (mrsas_alloc_dma_obj(instance, &response_dma_obj, 5808 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 5809 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 5810 "could not allocate data transfer buffer.")); 5811 return (DDI_FAILURE); 5812 } 5813 (void) memset(response_dma_obj.buffer, 0, response_xferlen); 5814 5815 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 5816 for (i = 0; i < response_xferlen; i++) { 5817 if (ddi_copyin((uint8_t *)response_ubuf + i, 5818 (uint8_t *)response_dma_obj.buffer + i, 5819 1, mode)) { 5820 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 5821 "copy from user space failed")); 5822 return (DDI_FAILURE); 5823 } 5824 } 5825 } 5826 5827 ddi_put8(acc_handle, &smp->cmd, ksmp->cmd); 5828 ddi_put8(acc_handle, &smp->cmd_status, 0); 5829 ddi_put8(acc_handle, &smp->connection_status, 0); 5830 ddi_put8(acc_handle, &smp->sge_count, ksmp->sge_count); 5831 /* smp->context = ksmp->context; */ 5832 ddi_put16(acc_handle, &smp->timeout, ksmp->timeout); 5833 ddi_put32(acc_handle, &smp->data_xfer_len, ksmp->data_xfer_len); 5834 5835 bcopy((void *)&ksmp->sas_addr, (void *)&tmp_sas_addr, 5836 sizeof (uint64_t)); 5837 ddi_put64(acc_handle, &smp->sas_addr, tmp_sas_addr); 5838 5839 ddi_put16(acc_handle, &smp->flags, ksmp->flags & ~MFI_FRAME_SGL64); 5840 5841 model = ddi_model_convert_from(mode & FMODELS); 5842 if (model == DDI_MODEL_ILP32) { 5843 con_log(CL_ANN1, (CE_CONT, 5844 "issue_mfi_smp: DDI_MODEL_ILP32")); 5845 5846 sge32 = &smp->sgl[0].sge32[0]; 5847 ddi_put32(acc_handle, &sge32[0].length, response_xferlen); 5848 ddi_put32(acc_handle, &sge32[0].phys_addr, 5849 response_dma_obj.dma_cookie[0].dmac_address); 5850 ddi_put32(acc_handle, &sge32[1].length, request_xferlen); 5851 ddi_put32(acc_handle, &sge32[1].phys_addr, 5852 request_dma_obj.dma_cookie[0].dmac_address); 5853 } else { 5854 #ifdef _ILP32 5855 con_log(CL_ANN1, (CE_CONT, 5856 "issue_mfi_smp: DDI_MODEL_ILP32")); 5857 sge32 = &smp->sgl[0].sge32[0]; 5858 ddi_put32(acc_handle, &sge32[0].length, response_xferlen); 5859 ddi_put32(acc_handle, &sge32[0].phys_addr, 5860 response_dma_obj.dma_cookie[0].dmac_address); 5861 ddi_put32(acc_handle, &sge32[1].length, request_xferlen); 5862 ddi_put32(acc_handle, &sge32[1].phys_addr, 5863 request_dma_obj.dma_cookie[0].dmac_address); 5864 #else 5865 con_log(CL_ANN1, (CE_CONT, 5866 "issue_mfi_smp: DDI_MODEL_LP64")); 5867 sge64 = &smp->sgl[0].sge64[0]; 5868 ddi_put32(acc_handle, &sge64[0].length, response_xferlen); 5869 ddi_put64(acc_handle, &sge64[0].phys_addr, 5870 response_dma_obj.dma_cookie[0].dmac_address); 5871 ddi_put32(acc_handle, &sge64[1].length, request_xferlen); 5872 ddi_put64(acc_handle, &sge64[1].phys_addr, 5873 request_dma_obj.dma_cookie[0].dmac_address); 5874 #endif 5875 } 5876 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp : " 5877 "smp->response_xferlen = %d, smp->request_xferlen = %d " 5878 "smp->data_xfer_len = %d", ddi_get32(acc_handle, &sge32[0].length), 5879 ddi_get32(acc_handle, &sge32[1].length), 5880 ddi_get32(acc_handle, &smp->data_xfer_len))); 5881 5882 cmd->sync_cmd = MRSAS_TRUE; 5883 cmd->frame_count = 1; 5884 5885 if (instance->tbolt) { 5886 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 5887 } 5888 5889 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 5890 con_log(CL_ANN, (CE_WARN, 5891 "issue_mfi_smp: fw_ioctl failed")); 5892 } else { 5893 con_log(CL_ANN1, (CE_CONT, 5894 "issue_mfi_smp: copy to user space")); 5895 5896 if (request_xferlen) { 5897 for (i = 0; i < request_xferlen; i++) { 5898 if (ddi_copyout( 5899 (uint8_t *)request_dma_obj.buffer + 5900 i, (uint8_t *)request_ubuf + i, 5901 1, mode)) { 5902 con_log(CL_ANN, (CE_WARN, 5903 "issue_mfi_smp : copy to user space" 5904 " failed")); 5905 return (DDI_FAILURE); 5906 } 5907 } 5908 } 5909 5910 if (response_xferlen) { 5911 for (i = 0; i < response_xferlen; i++) { 5912 if (ddi_copyout( 5913 (uint8_t *)response_dma_obj.buffer 5914 + i, (uint8_t *)response_ubuf 5915 + i, 1, mode)) { 5916 con_log(CL_ANN, (CE_WARN, 5917 "issue_mfi_smp : copy to " 5918 "user space failed")); 5919 return (DDI_FAILURE); 5920 } 5921 } 5922 } 5923 } 5924 5925 ksmp->cmd_status = ddi_get8(acc_handle, &smp->cmd_status); 5926 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: smp->cmd_status = %d", 5927 ksmp->cmd_status)); 5928 DTRACE_PROBE2(issue_smp, uint8_t, ksmp->cmd, uint8_t, ksmp->cmd_status); 5929 5930 if (request_xferlen) { 5931 /* free kernel buffer */ 5932 if (mrsas_free_dma_obj(instance, request_dma_obj) != 5933 DDI_SUCCESS) 5934 return (DDI_FAILURE); 5935 } 5936 5937 if (response_xferlen) { 5938 /* free kernel buffer */ 5939 if (mrsas_free_dma_obj(instance, response_dma_obj) != 5940 DDI_SUCCESS) 5941 return (DDI_FAILURE); 5942 } 5943 5944 return (DDI_SUCCESS); 5945 } 5946 5947 /* 5948 * issue_mfi_stp 5949 */ 5950 static int 5951 issue_mfi_stp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 5952 struct mrsas_cmd *cmd, int mode) 5953 { 5954 void *fis_ubuf; 5955 void *data_ubuf; 5956 uint32_t fis_xferlen = 0; 5957 uint32_t new_xfer_length1 = 0; 5958 uint32_t new_xfer_length2 = 0; 5959 uint32_t data_xferlen = 0; 5960 uint_t model; 5961 dma_obj_t fis_dma_obj; 5962 dma_obj_t data_dma_obj; 5963 struct mrsas_stp_frame *kstp; 5964 struct mrsas_stp_frame *stp; 5965 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 5966 int i; 5967 5968 stp = &cmd->frame->stp; 5969 kstp = (struct mrsas_stp_frame *)&ioctl->frame[0]; 5970 5971 if (instance->adapterresetinprogress) { 5972 con_log(CL_ANN1, (CE_WARN, "Reset flag set, " 5973 "returning mfi_pkt and setting TRAN_BUSY\n")); 5974 return (DDI_FAILURE); 5975 } 5976 model = ddi_model_convert_from(mode & FMODELS); 5977 if (model == DDI_MODEL_ILP32) { 5978 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32")); 5979 5980 fis_xferlen = kstp->sgl.sge32[0].length; 5981 data_xferlen = kstp->sgl.sge32[1].length; 5982 5983 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr; 5984 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr; 5985 } else { 5986 #ifdef _ILP32 5987 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32")); 5988 5989 fis_xferlen = kstp->sgl.sge32[0].length; 5990 data_xferlen = kstp->sgl.sge32[1].length; 5991 5992 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr; 5993 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr; 5994 #else 5995 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_LP64")); 5996 5997 fis_xferlen = kstp->sgl.sge64[0].length; 5998 data_xferlen = kstp->sgl.sge64[1].length; 5999 6000 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge64[0].phys_addr; 6001 data_ubuf = (void *)(ulong_t)kstp->sgl.sge64[1].phys_addr; 6002 #endif 6003 } 6004 6005 6006 if (fis_xferlen) { 6007 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: " 6008 "fis_ubuf = %p fis_xferlen = %x", fis_ubuf, fis_xferlen)); 6009 6010 /* means IOCTL requires DMA */ 6011 /* allocate the data transfer buffer */ 6012 /* fis_dma_obj.size = fis_xferlen; */ 6013 MRSAS_GET_BOUNDARY_ALIGNED_LEN(fis_xferlen, 6014 new_xfer_length1, PAGESIZE); 6015 fis_dma_obj.size = new_xfer_length1; 6016 fis_dma_obj.dma_attr = mrsas_generic_dma_attr; 6017 fis_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 6018 fis_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 6019 fis_dma_obj.dma_attr.dma_attr_sgllen = 1; 6020 fis_dma_obj.dma_attr.dma_attr_align = 1; 6021 6022 /* allocate kernel buffer for DMA */ 6023 if (mrsas_alloc_dma_obj(instance, &fis_dma_obj, 6024 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 6025 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp : " 6026 "could not allocate data transfer buffer.")); 6027 return (DDI_FAILURE); 6028 } 6029 (void) memset(fis_dma_obj.buffer, 0, fis_xferlen); 6030 6031 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 6032 for (i = 0; i < fis_xferlen; i++) { 6033 if (ddi_copyin((uint8_t *)fis_ubuf + i, 6034 (uint8_t *)fis_dma_obj.buffer + i, 1, mode)) { 6035 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: " 6036 "copy from user space failed")); 6037 return (DDI_FAILURE); 6038 } 6039 } 6040 } 6041 6042 if (data_xferlen) { 6043 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: data_ubuf = %p " 6044 "data_xferlen = %x", data_ubuf, data_xferlen)); 6045 6046 /* means IOCTL requires DMA */ 6047 /* allocate the data transfer buffer */ 6048 /* data_dma_obj.size = data_xferlen; */ 6049 MRSAS_GET_BOUNDARY_ALIGNED_LEN(data_xferlen, new_xfer_length2, 6050 PAGESIZE); 6051 data_dma_obj.size = new_xfer_length2; 6052 data_dma_obj.dma_attr = mrsas_generic_dma_attr; 6053 data_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 6054 data_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 6055 data_dma_obj.dma_attr.dma_attr_sgllen = 1; 6056 data_dma_obj.dma_attr.dma_attr_align = 1; 6057 6058 /* allocate kernel buffer for DMA */ 6059 if (mrsas_alloc_dma_obj(instance, &data_dma_obj, 6060 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 6061 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: " 6062 "could not allocate data transfer buffer.")); 6063 return (DDI_FAILURE); 6064 } 6065 (void) memset(data_dma_obj.buffer, 0, data_xferlen); 6066 6067 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 6068 for (i = 0; i < data_xferlen; i++) { 6069 if (ddi_copyin((uint8_t *)data_ubuf + i, 6070 (uint8_t *)data_dma_obj.buffer + i, 1, mode)) { 6071 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: " 6072 "copy from user space failed")); 6073 return (DDI_FAILURE); 6074 } 6075 } 6076 } 6077 6078 ddi_put8(acc_handle, &stp->cmd, kstp->cmd); 6079 ddi_put8(acc_handle, &stp->cmd_status, 0); 6080 ddi_put8(acc_handle, &stp->connection_status, 0); 6081 ddi_put8(acc_handle, &stp->target_id, kstp->target_id); 6082 ddi_put8(acc_handle, &stp->sge_count, kstp->sge_count); 6083 6084 ddi_put16(acc_handle, &stp->timeout, kstp->timeout); 6085 ddi_put32(acc_handle, &stp->data_xfer_len, kstp->data_xfer_len); 6086 6087 ddi_rep_put8(acc_handle, (uint8_t *)kstp->fis, (uint8_t *)stp->fis, 10, 6088 DDI_DEV_AUTOINCR); 6089 6090 ddi_put16(acc_handle, &stp->flags, kstp->flags & ~MFI_FRAME_SGL64); 6091 ddi_put32(acc_handle, &stp->stp_flags, kstp->stp_flags); 6092 ddi_put32(acc_handle, &stp->sgl.sge32[0].length, fis_xferlen); 6093 ddi_put32(acc_handle, &stp->sgl.sge32[0].phys_addr, 6094 fis_dma_obj.dma_cookie[0].dmac_address); 6095 ddi_put32(acc_handle, &stp->sgl.sge32[1].length, data_xferlen); 6096 ddi_put32(acc_handle, &stp->sgl.sge32[1].phys_addr, 6097 data_dma_obj.dma_cookie[0].dmac_address); 6098 6099 cmd->sync_cmd = MRSAS_TRUE; 6100 cmd->frame_count = 1; 6101 6102 if (instance->tbolt) { 6103 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 6104 } 6105 6106 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 6107 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: fw_ioctl failed")); 6108 } else { 6109 6110 if (fis_xferlen) { 6111 for (i = 0; i < fis_xferlen; i++) { 6112 if (ddi_copyout( 6113 (uint8_t *)fis_dma_obj.buffer + i, 6114 (uint8_t *)fis_ubuf + i, 1, mode)) { 6115 con_log(CL_ANN, (CE_WARN, 6116 "issue_mfi_stp : copy to " 6117 "user space failed")); 6118 return (DDI_FAILURE); 6119 } 6120 } 6121 } 6122 } 6123 if (data_xferlen) { 6124 for (i = 0; i < data_xferlen; i++) { 6125 if (ddi_copyout( 6126 (uint8_t *)data_dma_obj.buffer + i, 6127 (uint8_t *)data_ubuf + i, 1, mode)) { 6128 con_log(CL_ANN, (CE_WARN, 6129 "issue_mfi_stp : copy to" 6130 " user space failed")); 6131 return (DDI_FAILURE); 6132 } 6133 } 6134 } 6135 6136 kstp->cmd_status = ddi_get8(acc_handle, &stp->cmd_status); 6137 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_stp: stp->cmd_status = %d", 6138 kstp->cmd_status)); 6139 DTRACE_PROBE2(issue_stp, uint8_t, kstp->cmd, uint8_t, kstp->cmd_status); 6140 6141 if (fis_xferlen) { 6142 /* free kernel buffer */ 6143 if (mrsas_free_dma_obj(instance, fis_dma_obj) != DDI_SUCCESS) 6144 return (DDI_FAILURE); 6145 } 6146 6147 if (data_xferlen) { 6148 /* free kernel buffer */ 6149 if (mrsas_free_dma_obj(instance, data_dma_obj) != DDI_SUCCESS) 6150 return (DDI_FAILURE); 6151 } 6152 6153 return (DDI_SUCCESS); 6154 } 6155 6156 /* 6157 * fill_up_drv_ver 6158 */ 6159 void 6160 fill_up_drv_ver(struct mrsas_drv_ver *dv) 6161 { 6162 (void) memset(dv, 0, sizeof (struct mrsas_drv_ver)); 6163 6164 (void) memcpy(dv->signature, "$LSI LOGIC$", strlen("$LSI LOGIC$")); 6165 (void) memcpy(dv->os_name, "Solaris", strlen("Solaris")); 6166 (void) memcpy(dv->drv_name, "mr_sas", strlen("mr_sas")); 6167 (void) memcpy(dv->drv_ver, MRSAS_VERSION, strlen(MRSAS_VERSION)); 6168 (void) memcpy(dv->drv_rel_date, MRSAS_RELDATE, 6169 strlen(MRSAS_RELDATE)); 6170 6171 } 6172 6173 /* 6174 * handle_drv_ioctl 6175 */ 6176 static int 6177 handle_drv_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 6178 int mode) 6179 { 6180 int i; 6181 int rval = DDI_SUCCESS; 6182 int *props = NULL; 6183 void *ubuf; 6184 6185 uint8_t *pci_conf_buf; 6186 uint32_t xferlen; 6187 uint32_t num_props; 6188 uint_t model; 6189 struct mrsas_dcmd_frame *kdcmd; 6190 struct mrsas_drv_ver dv; 6191 struct mrsas_pci_information pi; 6192 6193 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0]; 6194 6195 model = ddi_model_convert_from(mode & FMODELS); 6196 if (model == DDI_MODEL_ILP32) { 6197 con_log(CL_ANN1, (CE_CONT, 6198 "handle_drv_ioctl: DDI_MODEL_ILP32")); 6199 6200 xferlen = kdcmd->sgl.sge32[0].length; 6201 6202 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 6203 } else { 6204 #ifdef _ILP32 6205 con_log(CL_ANN1, (CE_CONT, 6206 "handle_drv_ioctl: DDI_MODEL_ILP32")); 6207 xferlen = kdcmd->sgl.sge32[0].length; 6208 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 6209 #else 6210 con_log(CL_ANN1, (CE_CONT, 6211 "handle_drv_ioctl: DDI_MODEL_LP64")); 6212 xferlen = kdcmd->sgl.sge64[0].length; 6213 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr; 6214 #endif 6215 } 6216 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: " 6217 "dataBuf=%p size=%d bytes", ubuf, xferlen)); 6218 6219 switch (kdcmd->opcode) { 6220 case MRSAS_DRIVER_IOCTL_DRIVER_VERSION: 6221 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: " 6222 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION")); 6223 6224 fill_up_drv_ver(&dv); 6225 6226 if (ddi_copyout(&dv, ubuf, xferlen, mode)) { 6227 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 6228 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION : " 6229 "copy to user space failed")); 6230 kdcmd->cmd_status = 1; 6231 rval = 1; 6232 } else { 6233 kdcmd->cmd_status = 0; 6234 } 6235 break; 6236 case MRSAS_DRIVER_IOCTL_PCI_INFORMATION: 6237 con_log(CL_ANN1, (CE_NOTE, "handle_drv_ioctl: " 6238 "MRSAS_DRIVER_IOCTL_PCI_INFORMAITON")); 6239 6240 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, instance->dip, 6241 0, "reg", &props, &num_props)) { 6242 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 6243 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : " 6244 "ddi_prop_look_int_array failed")); 6245 rval = DDI_FAILURE; 6246 } else { 6247 6248 pi.busNumber = (props[0] >> 16) & 0xFF; 6249 pi.deviceNumber = (props[0] >> 11) & 0x1f; 6250 pi.functionNumber = (props[0] >> 8) & 0x7; 6251 ddi_prop_free((void *)props); 6252 } 6253 6254 pci_conf_buf = (uint8_t *)&pi.pciHeaderInfo; 6255 6256 for (i = 0; i < (sizeof (struct mrsas_pci_information) - 6257 offsetof(struct mrsas_pci_information, pciHeaderInfo)); 6258 i++) { 6259 pci_conf_buf[i] = 6260 pci_config_get8(instance->pci_handle, i); 6261 } 6262 6263 if (ddi_copyout(&pi, ubuf, xferlen, mode)) { 6264 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 6265 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : " 6266 "copy to user space failed")); 6267 kdcmd->cmd_status = 1; 6268 rval = 1; 6269 } else { 6270 kdcmd->cmd_status = 0; 6271 } 6272 break; 6273 default: 6274 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 6275 "invalid driver specific IOCTL opcode = 0x%x", 6276 kdcmd->opcode)); 6277 kdcmd->cmd_status = 1; 6278 rval = DDI_FAILURE; 6279 break; 6280 } 6281 6282 return (rval); 6283 } 6284 6285 /* 6286 * handle_mfi_ioctl 6287 */ 6288 static int 6289 handle_mfi_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 6290 int mode) 6291 { 6292 int rval = DDI_SUCCESS; 6293 6294 struct mrsas_header *hdr; 6295 struct mrsas_cmd *cmd; 6296 6297 if (instance->tbolt) { 6298 cmd = get_raid_msg_mfi_pkt(instance); 6299 } else { 6300 cmd = mrsas_get_mfi_pkt(instance); 6301 } 6302 if (!cmd) { 6303 con_log(CL_ANN, (CE_WARN, "mr_sas: " 6304 "failed to get a cmd packet")); 6305 DTRACE_PROBE2(mfi_ioctl_err, uint16_t, 6306 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 6307 return (DDI_FAILURE); 6308 } 6309 6310 /* Clear the frame buffer and assign back the context id */ 6311 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 6312 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 6313 cmd->index); 6314 6315 hdr = (struct mrsas_header *)&ioctl->frame[0]; 6316 6317 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) { 6318 case MFI_CMD_OP_DCMD: 6319 rval = issue_mfi_dcmd(instance, ioctl, cmd, mode); 6320 break; 6321 case MFI_CMD_OP_SMP: 6322 rval = issue_mfi_smp(instance, ioctl, cmd, mode); 6323 break; 6324 case MFI_CMD_OP_STP: 6325 rval = issue_mfi_stp(instance, ioctl, cmd, mode); 6326 break; 6327 case MFI_CMD_OP_LD_SCSI: 6328 case MFI_CMD_OP_PD_SCSI: 6329 rval = issue_mfi_pthru(instance, ioctl, cmd, mode); 6330 break; 6331 default: 6332 con_log(CL_ANN, (CE_WARN, "handle_mfi_ioctl: " 6333 "invalid mfi ioctl hdr->cmd = %d", hdr->cmd)); 6334 rval = DDI_FAILURE; 6335 break; 6336 } 6337 6338 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) 6339 rval = DDI_FAILURE; 6340 6341 if (instance->tbolt) { 6342 return_raid_msg_mfi_pkt(instance, cmd); 6343 } else { 6344 mrsas_return_mfi_pkt(instance, cmd); 6345 } 6346 6347 return (rval); 6348 } 6349 6350 /* 6351 * AEN 6352 */ 6353 static int 6354 handle_mfi_aen(struct mrsas_instance *instance, struct mrsas_aen *aen) 6355 { 6356 int rval = 0; 6357 6358 rval = register_mfi_aen(instance, instance->aen_seq_num, 6359 aen->class_locale_word); 6360 6361 aen->cmd_status = (uint8_t)rval; 6362 6363 return (rval); 6364 } 6365 6366 static int 6367 register_mfi_aen(struct mrsas_instance *instance, uint32_t seq_num, 6368 uint32_t class_locale_word) 6369 { 6370 int ret_val; 6371 6372 struct mrsas_cmd *cmd, *aen_cmd; 6373 struct mrsas_dcmd_frame *dcmd; 6374 union mrsas_evt_class_locale curr_aen; 6375 union mrsas_evt_class_locale prev_aen; 6376 6377 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 6378 /* 6379 * If there an AEN pending already (aen_cmd), check if the 6380 * class_locale of that pending AEN is inclusive of the new 6381 * AEN request we currently have. If it is, then we don't have 6382 * to do anything. In other words, whichever events the current 6383 * AEN request is subscribing to, have already been subscribed 6384 * to. 6385 * 6386 * If the old_cmd is _not_ inclusive, then we have to abort 6387 * that command, form a class_locale that is superset of both 6388 * old and current and re-issue to the FW 6389 */ 6390 6391 curr_aen.word = LE_32(class_locale_word); 6392 curr_aen.members.locale = LE_16(curr_aen.members.locale); 6393 aen_cmd = instance->aen_cmd; 6394 if (aen_cmd) { 6395 prev_aen.word = ddi_get32(aen_cmd->frame_dma_obj.acc_handle, 6396 &aen_cmd->frame->dcmd.mbox.w[1]); 6397 prev_aen.word = LE_32(prev_aen.word); 6398 prev_aen.members.locale = LE_16(prev_aen.members.locale); 6399 /* 6400 * A class whose enum value is smaller is inclusive of all 6401 * higher values. If a PROGRESS (= -1) was previously 6402 * registered, then a new registration requests for higher 6403 * classes need not be sent to FW. They are automatically 6404 * included. 6405 * 6406 * Locale numbers don't have such hierarchy. They are bitmap 6407 * values 6408 */ 6409 if ((prev_aen.members.class <= curr_aen.members.class) && 6410 !((prev_aen.members.locale & curr_aen.members.locale) ^ 6411 curr_aen.members.locale)) { 6412 /* 6413 * Previously issued event registration includes 6414 * current request. Nothing to do. 6415 */ 6416 6417 return (0); 6418 } else { 6419 curr_aen.members.locale |= prev_aen.members.locale; 6420 6421 if (prev_aen.members.class < curr_aen.members.class) 6422 curr_aen.members.class = prev_aen.members.class; 6423 6424 ret_val = abort_aen_cmd(instance, aen_cmd); 6425 6426 if (ret_val) { 6427 con_log(CL_ANN, (CE_WARN, "register_mfi_aen: " 6428 "failed to abort prevous AEN command")); 6429 6430 return (ret_val); 6431 } 6432 } 6433 } else { 6434 curr_aen.word = LE_32(class_locale_word); 6435 curr_aen.members.locale = LE_16(curr_aen.members.locale); 6436 } 6437 6438 if (instance->tbolt) { 6439 cmd = get_raid_msg_mfi_pkt(instance); 6440 } else { 6441 cmd = mrsas_get_mfi_pkt(instance); 6442 } 6443 6444 if (!cmd) { 6445 DTRACE_PROBE2(mfi_aen_err, uint16_t, instance->fw_outstanding, 6446 uint16_t, instance->max_fw_cmds); 6447 return (ENOMEM); 6448 } 6449 6450 /* Clear the frame buffer and assign back the context id */ 6451 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 6452 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 6453 cmd->index); 6454 6455 dcmd = &cmd->frame->dcmd; 6456 6457 /* for(i = 0; i < DCMD_MBOX_SZ; i++) dcmd->mbox.b[i] = 0; */ 6458 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 6459 6460 (void) memset(instance->mfi_evt_detail_obj.buffer, 0, 6461 sizeof (struct mrsas_evt_detail)); 6462 6463 /* Prepare DCMD for aen registration */ 6464 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 6465 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0); 6466 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1); 6467 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 6468 MFI_FRAME_DIR_READ); 6469 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 6470 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 6471 sizeof (struct mrsas_evt_detail)); 6472 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 6473 MR_DCMD_CTRL_EVENT_WAIT); 6474 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[0], seq_num); 6475 curr_aen.members.locale = LE_16(curr_aen.members.locale); 6476 curr_aen.word = LE_32(curr_aen.word); 6477 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[1], 6478 curr_aen.word); 6479 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr, 6480 instance->mfi_evt_detail_obj.dma_cookie[0].dmac_address); 6481 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length, 6482 sizeof (struct mrsas_evt_detail)); 6483 6484 instance->aen_seq_num = seq_num; 6485 6486 6487 /* 6488 * Store reference to the cmd used to register for AEN. When an 6489 * application wants us to register for AEN, we have to abort this 6490 * cmd and re-register with a new EVENT LOCALE supplied by that app 6491 */ 6492 instance->aen_cmd = cmd; 6493 6494 cmd->frame_count = 1; 6495 6496 /* Issue the aen registration frame */ 6497 /* atomic_add_16 (&instance->fw_outstanding, 1); */ 6498 if (instance->tbolt) { 6499 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 6500 } 6501 instance->func_ptr->issue_cmd(cmd, instance); 6502 6503 return (0); 6504 } 6505 6506 void 6507 display_scsi_inquiry(caddr_t scsi_inq) 6508 { 6509 #define MAX_SCSI_DEVICE_CODE 14 6510 int i; 6511 char inquiry_buf[256] = {0}; 6512 int len; 6513 const char *const scsi_device_types[] = { 6514 "Direct-Access ", 6515 "Sequential-Access", 6516 "Printer ", 6517 "Processor ", 6518 "WORM ", 6519 "CD-ROM ", 6520 "Scanner ", 6521 "Optical Device ", 6522 "Medium Changer ", 6523 "Communications ", 6524 "Unknown ", 6525 "Unknown ", 6526 "Unknown ", 6527 "Enclosure ", 6528 }; 6529 6530 len = 0; 6531 6532 len += snprintf(inquiry_buf + len, 265 - len, " Vendor: "); 6533 for (i = 8; i < 16; i++) { 6534 len += snprintf(inquiry_buf + len, 265 - len, "%c", 6535 scsi_inq[i]); 6536 } 6537 6538 len += snprintf(inquiry_buf + len, 265 - len, " Model: "); 6539 6540 for (i = 16; i < 32; i++) { 6541 len += snprintf(inquiry_buf + len, 265 - len, "%c", 6542 scsi_inq[i]); 6543 } 6544 6545 len += snprintf(inquiry_buf + len, 265 - len, " Rev: "); 6546 6547 for (i = 32; i < 36; i++) { 6548 len += snprintf(inquiry_buf + len, 265 - len, "%c", 6549 scsi_inq[i]); 6550 } 6551 6552 len += snprintf(inquiry_buf + len, 265 - len, "\n"); 6553 6554 6555 i = scsi_inq[0] & 0x1f; 6556 6557 6558 len += snprintf(inquiry_buf + len, 265 - len, " Type: %s ", 6559 i < MAX_SCSI_DEVICE_CODE ? scsi_device_types[i] : 6560 "Unknown "); 6561 6562 6563 len += snprintf(inquiry_buf + len, 265 - len, 6564 " ANSI SCSI revision: %02x", scsi_inq[2] & 0x07); 6565 6566 if ((scsi_inq[2] & 0x07) == 1 && (scsi_inq[3] & 0x0f) == 1) { 6567 len += snprintf(inquiry_buf + len, 265 - len, " CCS\n"); 6568 } else { 6569 len += snprintf(inquiry_buf + len, 265 - len, "\n"); 6570 } 6571 6572 con_log(CL_DLEVEL2, (CE_CONT, inquiry_buf)); 6573 } 6574 6575 static void 6576 io_timeout_checker(void *arg) 6577 { 6578 struct scsi_pkt *pkt; 6579 struct mrsas_instance *instance = arg; 6580 struct mrsas_cmd *cmd = NULL; 6581 struct mrsas_header *hdr; 6582 int time = 0; 6583 int counter = 0; 6584 struct mlist_head *pos, *next; 6585 mlist_t process_list; 6586 6587 if (instance->adapterresetinprogress == 1) { 6588 con_log(CL_ANN, (CE_NOTE, "io_timeout_checker:" 6589 " reset in progress")); 6590 6591 instance->timeout_id = timeout(io_timeout_checker, 6592 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 6593 return; 6594 } 6595 6596 /* See if this check needs to be in the beginning or last in ISR */ 6597 if (mrsas_initiate_ocr_if_fw_is_faulty(instance) == 1) { 6598 dev_err(instance->dip, CE_WARN, "io_timeout_checker: " 6599 "FW Fault, calling reset adapter"); 6600 dev_err(instance->dip, CE_CONT, "io_timeout_checker: " 6601 "fw_outstanding 0x%X max_fw_cmds 0x%X", 6602 instance->fw_outstanding, instance->max_fw_cmds); 6603 if (instance->adapterresetinprogress == 0) { 6604 instance->adapterresetinprogress = 1; 6605 if (instance->tbolt) 6606 (void) mrsas_tbolt_reset_ppc(instance); 6607 else 6608 (void) mrsas_reset_ppc(instance); 6609 instance->adapterresetinprogress = 0; 6610 } 6611 instance->timeout_id = timeout(io_timeout_checker, 6612 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 6613 return; 6614 } 6615 6616 INIT_LIST_HEAD(&process_list); 6617 6618 mutex_enter(&instance->cmd_pend_mtx); 6619 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) { 6620 cmd = mlist_entry(pos, struct mrsas_cmd, list); 6621 6622 if (cmd == NULL) { 6623 continue; 6624 } 6625 6626 if (cmd->sync_cmd == MRSAS_TRUE) { 6627 hdr = (struct mrsas_header *)&cmd->frame->hdr; 6628 if (hdr == NULL) { 6629 continue; 6630 } 6631 time = --cmd->drv_pkt_time; 6632 } else { 6633 pkt = cmd->pkt; 6634 if (pkt == NULL) { 6635 continue; 6636 } 6637 time = --cmd->drv_pkt_time; 6638 } 6639 if (time <= 0) { 6640 dev_err(instance->dip, CE_WARN, "%llx: " 6641 "io_timeout_checker: TIMING OUT: pkt: %p, " 6642 "cmd %p fw_outstanding 0x%X max_fw_cmds 0x%X", 6643 gethrtime(), (void *)pkt, (void *)cmd, 6644 instance->fw_outstanding, instance->max_fw_cmds); 6645 6646 counter++; 6647 break; 6648 } 6649 } 6650 mutex_exit(&instance->cmd_pend_mtx); 6651 6652 if (counter) { 6653 if (instance->disable_online_ctrl_reset == 1) { 6654 dev_err(instance->dip, CE_WARN, "%s(): OCR is NOT " 6655 "supported by Firmware, KILL adapter!!!", 6656 __func__); 6657 6658 if (instance->tbolt) 6659 mrsas_tbolt_kill_adapter(instance); 6660 else 6661 (void) mrsas_kill_adapter(instance); 6662 6663 return; 6664 } else { 6665 if (cmd->retry_count_for_ocr <= IO_RETRY_COUNT) { 6666 if (instance->adapterresetinprogress == 0) { 6667 if (instance->tbolt) { 6668 (void) mrsas_tbolt_reset_ppc( 6669 instance); 6670 } else { 6671 (void) mrsas_reset_ppc( 6672 instance); 6673 } 6674 } 6675 } else { 6676 dev_err(instance->dip, CE_WARN, 6677 "io_timeout_checker: " 6678 "cmd %p cmd->index %d " 6679 "timed out even after 3 resets: " 6680 "so KILL adapter", (void *)cmd, cmd->index); 6681 6682 mrsas_print_cmd_details(instance, cmd, 0xDD); 6683 6684 if (instance->tbolt) 6685 mrsas_tbolt_kill_adapter(instance); 6686 else 6687 (void) mrsas_kill_adapter(instance); 6688 return; 6689 } 6690 } 6691 } 6692 con_log(CL_ANN, (CE_NOTE, "mrsas: " 6693 "schedule next timeout check: " 6694 "do timeout \n")); 6695 instance->timeout_id = 6696 timeout(io_timeout_checker, (void *)instance, 6697 drv_usectohz(MRSAS_1_SECOND)); 6698 } 6699 6700 static uint32_t 6701 read_fw_status_reg_ppc(struct mrsas_instance *instance) 6702 { 6703 return ((uint32_t)RD_OB_SCRATCH_PAD_0(instance)); 6704 } 6705 6706 static void 6707 issue_cmd_ppc(struct mrsas_cmd *cmd, struct mrsas_instance *instance) 6708 { 6709 struct scsi_pkt *pkt; 6710 atomic_inc_16(&instance->fw_outstanding); 6711 6712 pkt = cmd->pkt; 6713 if (pkt) { 6714 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:" 6715 "ISSUED CMD TO FW : called : cmd:" 6716 ": %p instance : %p pkt : %p pkt_time : %x\n", 6717 gethrtime(), (void *)cmd, (void *)instance, 6718 (void *)pkt, cmd->drv_pkt_time)); 6719 if (instance->adapterresetinprogress) { 6720 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 6721 con_log(CL_ANN1, (CE_NOTE, "Reset the scsi_pkt timer")); 6722 } else { 6723 push_pending_mfi_pkt(instance, cmd); 6724 } 6725 6726 } else { 6727 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:" 6728 "ISSUED CMD TO FW : called : cmd : %p, instance: %p" 6729 "(NO PKT)\n", gethrtime(), (void *)cmd, (void *)instance)); 6730 } 6731 6732 mutex_enter(&instance->reg_write_mtx); 6733 /* Issue the command to the FW */ 6734 WR_IB_PICK_QPORT((cmd->frame_phys_addr) | 6735 (((cmd->frame_count - 1) << 1) | 1), instance); 6736 mutex_exit(&instance->reg_write_mtx); 6737 6738 } 6739 6740 /* 6741 * issue_cmd_in_sync_mode 6742 */ 6743 static int 6744 issue_cmd_in_sync_mode_ppc(struct mrsas_instance *instance, 6745 struct mrsas_cmd *cmd) 6746 { 6747 int i; 6748 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC; 6749 struct mrsas_header *hdr = &cmd->frame->hdr; 6750 6751 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: called")); 6752 6753 if (instance->adapterresetinprogress) { 6754 cmd->drv_pkt_time = ddi_get16( 6755 cmd->frame_dma_obj.acc_handle, &hdr->timeout); 6756 if (cmd->drv_pkt_time < debug_timeout_g) 6757 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 6758 6759 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: " 6760 "issue and return in reset case\n")); 6761 WR_IB_PICK_QPORT((cmd->frame_phys_addr) | 6762 (((cmd->frame_count - 1) << 1) | 1), instance); 6763 6764 return (DDI_SUCCESS); 6765 } else { 6766 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: pushing the pkt\n")); 6767 push_pending_mfi_pkt(instance, cmd); 6768 } 6769 6770 cmd->cmd_status = ENODATA; 6771 6772 mutex_enter(&instance->reg_write_mtx); 6773 /* Issue the command to the FW */ 6774 WR_IB_PICK_QPORT((cmd->frame_phys_addr) | 6775 (((cmd->frame_count - 1) << 1) | 1), instance); 6776 mutex_exit(&instance->reg_write_mtx); 6777 6778 mutex_enter(&instance->int_cmd_mtx); 6779 for (i = 0; i < msecs && (cmd->cmd_status == ENODATA); i++) { 6780 cv_wait(&instance->int_cmd_cv, &instance->int_cmd_mtx); 6781 } 6782 mutex_exit(&instance->int_cmd_mtx); 6783 6784 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: done")); 6785 6786 if (i < (msecs -1)) { 6787 return (DDI_SUCCESS); 6788 } else { 6789 return (DDI_FAILURE); 6790 } 6791 } 6792 6793 /* 6794 * issue_cmd_in_poll_mode 6795 */ 6796 static int 6797 issue_cmd_in_poll_mode_ppc(struct mrsas_instance *instance, 6798 struct mrsas_cmd *cmd) 6799 { 6800 int i; 6801 uint16_t flags; 6802 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC; 6803 struct mrsas_header *frame_hdr; 6804 6805 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_poll_mode_ppc: called")); 6806 6807 frame_hdr = (struct mrsas_header *)cmd->frame; 6808 ddi_put8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status, 6809 MFI_CMD_STATUS_POLL_MODE); 6810 flags = ddi_get16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags); 6811 flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 6812 6813 ddi_put16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags, flags); 6814 6815 /* issue the frame using inbound queue port */ 6816 WR_IB_PICK_QPORT((cmd->frame_phys_addr) | 6817 (((cmd->frame_count - 1) << 1) | 1), instance); 6818 6819 /* wait for cmd_status to change from 0xFF */ 6820 for (i = 0; i < msecs && ( 6821 ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status) 6822 == MFI_CMD_STATUS_POLL_MODE); i++) { 6823 drv_usecwait(MILLISEC); /* wait for 1000 usecs */ 6824 } 6825 6826 if (ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status) 6827 == MFI_CMD_STATUS_POLL_MODE) { 6828 con_log(CL_ANN, (CE_NOTE, "issue_cmd_in_poll_mode: " 6829 "cmd polling timed out")); 6830 return (DDI_FAILURE); 6831 } 6832 6833 return (DDI_SUCCESS); 6834 } 6835 6836 static void 6837 enable_intr_ppc(struct mrsas_instance *instance) 6838 { 6839 uint32_t mask; 6840 6841 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: called")); 6842 6843 if (instance->skinny) { 6844 /* For SKINNY, write ~0x1, from BSD's mfi driver. */ 6845 WR_OB_INTR_MASK(0xfffffffe, instance); 6846 } else { 6847 /* WR_OB_DOORBELL_CLEAR(0xFFFFFFFF, instance); */ 6848 WR_OB_DOORBELL_CLEAR(OB_DOORBELL_CLEAR_MASK, instance); 6849 6850 /* WR_OB_INTR_MASK(~0x80000000, instance); */ 6851 WR_OB_INTR_MASK(~(MFI_REPLY_2108_MESSAGE_INTR_MASK), instance); 6852 } 6853 6854 /* dummy read to force PCI flush */ 6855 mask = RD_OB_INTR_MASK(instance); 6856 6857 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: " 6858 "outbound_intr_mask = 0x%x", mask)); 6859 } 6860 6861 static void 6862 disable_intr_ppc(struct mrsas_instance *instance) 6863 { 6864 uint32_t mask; 6865 6866 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: called")); 6867 6868 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: before : " 6869 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance))); 6870 6871 /* For now, assume there are no extras needed for Skinny support. */ 6872 6873 WR_OB_INTR_MASK(OB_INTR_MASK, instance); 6874 6875 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: after : " 6876 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance))); 6877 6878 /* dummy read to force PCI flush */ 6879 mask = RD_OB_INTR_MASK(instance); 6880 #ifdef lint 6881 mask = mask; 6882 #endif 6883 } 6884 6885 static int 6886 intr_ack_ppc(struct mrsas_instance *instance) 6887 { 6888 uint32_t status; 6889 int ret = DDI_INTR_CLAIMED; 6890 6891 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: called")); 6892 6893 /* check if it is our interrupt */ 6894 status = RD_OB_INTR_STATUS(instance); 6895 6896 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: status = 0x%x", status)); 6897 6898 /* 6899 * NOTE: Some drivers call out SKINNY here, but the return is the same 6900 * for SKINNY and 2108. 6901 */ 6902 if (!(status & MFI_REPLY_2108_MESSAGE_INTR)) { 6903 ret = DDI_INTR_UNCLAIMED; 6904 } 6905 6906 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) { 6907 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 6908 ret = DDI_INTR_UNCLAIMED; 6909 } 6910 6911 if (ret == DDI_INTR_UNCLAIMED) { 6912 return (ret); 6913 } 6914 6915 /* 6916 * Clear the interrupt by writing back the same value. 6917 * Another case where SKINNY is slightly different. 6918 */ 6919 if (instance->skinny) { 6920 WR_OB_INTR_STATUS(status, instance); 6921 } else { 6922 WR_OB_DOORBELL_CLEAR(status, instance); 6923 } 6924 6925 /* dummy READ */ 6926 status = RD_OB_INTR_STATUS(instance); 6927 6928 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: interrupt cleared")); 6929 6930 return (ret); 6931 } 6932 6933 /* 6934 * Marks HBA as bad. This will be called either when an 6935 * IO packet times out even after 3 FW resets 6936 * or FW is found to be fault even after 3 continuous resets. 6937 */ 6938 6939 static int 6940 mrsas_kill_adapter(struct mrsas_instance *instance) 6941 { 6942 if (instance->deadadapter == 1) 6943 return (DDI_FAILURE); 6944 6945 con_log(CL_ANN1, (CE_NOTE, "mrsas_kill_adapter: " 6946 "Writing to doorbell with MFI_STOP_ADP ")); 6947 mutex_enter(&instance->ocr_flags_mtx); 6948 instance->deadadapter = 1; 6949 mutex_exit(&instance->ocr_flags_mtx); 6950 instance->func_ptr->disable_intr(instance); 6951 WR_IB_DOORBELL(MFI_STOP_ADP, instance); 6952 (void) mrsas_complete_pending_cmds(instance); 6953 return (DDI_SUCCESS); 6954 } 6955 6956 6957 static int 6958 mrsas_reset_ppc(struct mrsas_instance *instance) 6959 { 6960 uint32_t status; 6961 uint32_t retry = 0; 6962 uint32_t cur_abs_reg_val; 6963 uint32_t fw_state; 6964 6965 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 6966 6967 if (instance->deadadapter == 1) { 6968 dev_err(instance->dip, CE_WARN, "mrsas_reset_ppc: " 6969 "no more resets as HBA has been marked dead "); 6970 return (DDI_FAILURE); 6971 } 6972 mutex_enter(&instance->ocr_flags_mtx); 6973 instance->adapterresetinprogress = 1; 6974 mutex_exit(&instance->ocr_flags_mtx); 6975 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: adpterresetinprogress " 6976 "flag set, time %llx", gethrtime())); 6977 6978 instance->func_ptr->disable_intr(instance); 6979 retry_reset: 6980 WR_IB_WRITE_SEQ(0, instance); 6981 WR_IB_WRITE_SEQ(4, instance); 6982 WR_IB_WRITE_SEQ(0xb, instance); 6983 WR_IB_WRITE_SEQ(2, instance); 6984 WR_IB_WRITE_SEQ(7, instance); 6985 WR_IB_WRITE_SEQ(0xd, instance); 6986 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: magic number written " 6987 "to write sequence register\n")); 6988 delay(100 * drv_usectohz(MILLISEC)); 6989 status = RD_OB_DRWE(instance); 6990 6991 while (!(status & DIAG_WRITE_ENABLE)) { 6992 delay(100 * drv_usectohz(MILLISEC)); 6993 status = RD_OB_DRWE(instance); 6994 if (retry++ == 100) { 6995 dev_err(instance->dip, CE_WARN, 6996 "mrsas_reset_ppc: DRWE bit " 6997 "check retry count %d", retry); 6998 return (DDI_FAILURE); 6999 } 7000 } 7001 WR_IB_DRWE(status | DIAG_RESET_ADAPTER, instance); 7002 delay(100 * drv_usectohz(MILLISEC)); 7003 status = RD_OB_DRWE(instance); 7004 while (status & DIAG_RESET_ADAPTER) { 7005 delay(100 * drv_usectohz(MILLISEC)); 7006 status = RD_OB_DRWE(instance); 7007 if (retry++ == 100) { 7008 dev_err(instance->dip, CE_WARN, "mrsas_reset_ppc: " 7009 "RESET FAILED. KILL adapter called."); 7010 7011 (void) mrsas_kill_adapter(instance); 7012 return (DDI_FAILURE); 7013 } 7014 } 7015 con_log(CL_ANN, (CE_NOTE, "mrsas_reset_ppc: Adapter reset complete")); 7016 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7017 "Calling mfi_state_transition_to_ready")); 7018 7019 /* Mark HBA as bad, if FW is fault after 3 continuous resets */ 7020 if (mfi_state_transition_to_ready(instance) || 7021 debug_fw_faults_after_ocr_g == 1) { 7022 cur_abs_reg_val = 7023 instance->func_ptr->read_fw_status_reg(instance); 7024 fw_state = cur_abs_reg_val & MFI_STATE_MASK; 7025 7026 #ifdef OCRDEBUG 7027 con_log(CL_ANN1, (CE_NOTE, 7028 "mrsas_reset_ppc :before fake: FW is not ready " 7029 "FW state = 0x%x", fw_state)); 7030 if (debug_fw_faults_after_ocr_g == 1) 7031 fw_state = MFI_STATE_FAULT; 7032 #endif 7033 7034 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc : FW is not ready " 7035 "FW state = 0x%x", fw_state)); 7036 7037 if (fw_state == MFI_STATE_FAULT) { 7038 /* increment the count */ 7039 instance->fw_fault_count_after_ocr++; 7040 if (instance->fw_fault_count_after_ocr 7041 < MAX_FW_RESET_COUNT) { 7042 dev_err(instance->dip, CE_WARN, 7043 "mrsas_reset_ppc: " 7044 "FW is in fault after OCR count %d " 7045 "Retry Reset", 7046 instance->fw_fault_count_after_ocr); 7047 goto retry_reset; 7048 7049 } else { 7050 dev_err(instance->dip, CE_WARN, 7051 "mrsas_reset_ppc: " 7052 "Max Reset Count exceeded >%d" 7053 "Mark HBA as bad, KILL adapter", 7054 MAX_FW_RESET_COUNT); 7055 7056 (void) mrsas_kill_adapter(instance); 7057 return (DDI_FAILURE); 7058 } 7059 } 7060 } 7061 /* reset the counter as FW is up after OCR */ 7062 instance->fw_fault_count_after_ocr = 0; 7063 7064 7065 ddi_put32(instance->mfi_internal_dma_obj.acc_handle, 7066 instance->producer, 0); 7067 7068 ddi_put32(instance->mfi_internal_dma_obj.acc_handle, 7069 instance->consumer, 0); 7070 7071 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7072 " after resetting produconsumer chck indexs:" 7073 "producer %x consumer %x", *instance->producer, 7074 *instance->consumer)); 7075 7076 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7077 "Calling mrsas_issue_init_mfi")); 7078 (void) mrsas_issue_init_mfi(instance); 7079 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7080 "mrsas_issue_init_mfi Done")); 7081 7082 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7083 "Calling mrsas_print_pending_cmd\n")); 7084 (void) mrsas_print_pending_cmds(instance); 7085 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7086 "mrsas_print_pending_cmd done\n")); 7087 7088 instance->func_ptr->enable_intr(instance); 7089 instance->fw_outstanding = 0; 7090 7091 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7092 "Calling mrsas_issue_pending_cmds")); 7093 (void) mrsas_issue_pending_cmds(instance); 7094 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7095 "issue_pending_cmds done.\n")); 7096 7097 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7098 "Calling aen registration")); 7099 7100 7101 instance->aen_cmd->retry_count_for_ocr = 0; 7102 instance->aen_cmd->drv_pkt_time = 0; 7103 7104 instance->func_ptr->issue_cmd(instance->aen_cmd, instance); 7105 con_log(CL_ANN1, (CE_NOTE, "Unsetting adpresetinprogress flag.\n")); 7106 7107 mutex_enter(&instance->ocr_flags_mtx); 7108 instance->adapterresetinprogress = 0; 7109 mutex_exit(&instance->ocr_flags_mtx); 7110 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7111 "adpterresetinprogress flag unset")); 7112 7113 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc done\n")); 7114 return (DDI_SUCCESS); 7115 } 7116 7117 /* 7118 * FMA functions. 7119 */ 7120 int 7121 mrsas_common_check(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 7122 { 7123 int ret = DDI_SUCCESS; 7124 7125 if (cmd != NULL && 7126 mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) != 7127 DDI_SUCCESS) { 7128 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 7129 if (cmd->pkt != NULL) { 7130 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 7131 cmd->pkt->pkt_statistics = 0; 7132 } 7133 ret = DDI_FAILURE; 7134 } 7135 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle) 7136 != DDI_SUCCESS) { 7137 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 7138 if (cmd != NULL && cmd->pkt != NULL) { 7139 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 7140 cmd->pkt->pkt_statistics = 0; 7141 } 7142 ret = DDI_FAILURE; 7143 } 7144 if (mrsas_check_dma_handle(instance->mfi_evt_detail_obj.dma_handle) != 7145 DDI_SUCCESS) { 7146 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 7147 if (cmd != NULL && cmd->pkt != NULL) { 7148 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 7149 cmd->pkt->pkt_statistics = 0; 7150 } 7151 ret = DDI_FAILURE; 7152 } 7153 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) { 7154 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 7155 7156 ddi_fm_acc_err_clear(instance->regmap_handle, DDI_FME_VER0); 7157 7158 if (cmd != NULL && cmd->pkt != NULL) { 7159 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 7160 cmd->pkt->pkt_statistics = 0; 7161 } 7162 ret = DDI_FAILURE; 7163 } 7164 7165 return (ret); 7166 } 7167 7168 /*ARGSUSED*/ 7169 static int 7170 mrsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 7171 { 7172 /* 7173 * as the driver can always deal with an error in any dma or 7174 * access handle, we can just return the fme_status value. 7175 */ 7176 pci_ereport_post(dip, err, NULL); 7177 return (err->fme_status); 7178 } 7179 7180 static void 7181 mrsas_fm_init(struct mrsas_instance *instance) 7182 { 7183 /* Need to change iblock to priority for new MSI intr */ 7184 ddi_iblock_cookie_t fm_ibc; 7185 7186 /* Only register with IO Fault Services if we have some capability */ 7187 if (instance->fm_capabilities) { 7188 /* Adjust access and dma attributes for FMA */ 7189 endian_attr.devacc_attr_access = DDI_FLAGERR_ACC; 7190 mrsas_generic_dma_attr.dma_attr_flags = DDI_DMA_FLAGERR; 7191 7192 /* 7193 * Register capabilities with IO Fault Services. 7194 * fm_capabilities will be updated to indicate 7195 * capabilities actually supported (not requested.) 7196 */ 7197 7198 ddi_fm_init(instance->dip, &instance->fm_capabilities, &fm_ibc); 7199 7200 /* 7201 * Initialize pci ereport capabilities if ereport 7202 * capable (should always be.) 7203 */ 7204 7205 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) || 7206 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 7207 pci_ereport_setup(instance->dip); 7208 } 7209 7210 /* 7211 * Register error callback if error callback capable. 7212 */ 7213 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 7214 ddi_fm_handler_register(instance->dip, 7215 mrsas_fm_error_cb, (void*) instance); 7216 } 7217 } else { 7218 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC; 7219 mrsas_generic_dma_attr.dma_attr_flags = 0; 7220 } 7221 } 7222 7223 static void 7224 mrsas_fm_fini(struct mrsas_instance *instance) 7225 { 7226 /* Only unregister FMA capabilities if registered */ 7227 if (instance->fm_capabilities) { 7228 /* 7229 * Un-register error callback if error callback capable. 7230 */ 7231 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 7232 ddi_fm_handler_unregister(instance->dip); 7233 } 7234 7235 /* 7236 * Release any resources allocated by pci_ereport_setup() 7237 */ 7238 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) || 7239 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 7240 pci_ereport_teardown(instance->dip); 7241 } 7242 7243 /* Unregister from IO Fault Services */ 7244 ddi_fm_fini(instance->dip); 7245 7246 /* Adjust access and dma attributes for FMA */ 7247 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC; 7248 mrsas_generic_dma_attr.dma_attr_flags = 0; 7249 } 7250 } 7251 7252 int 7253 mrsas_check_acc_handle(ddi_acc_handle_t handle) 7254 { 7255 ddi_fm_error_t de; 7256 7257 if (handle == NULL) { 7258 return (DDI_FAILURE); 7259 } 7260 7261 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 7262 7263 return (de.fme_status); 7264 } 7265 7266 int 7267 mrsas_check_dma_handle(ddi_dma_handle_t handle) 7268 { 7269 ddi_fm_error_t de; 7270 7271 if (handle == NULL) { 7272 return (DDI_FAILURE); 7273 } 7274 7275 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 7276 7277 return (de.fme_status); 7278 } 7279 7280 void 7281 mrsas_fm_ereport(struct mrsas_instance *instance, char *detail) 7282 { 7283 uint64_t ena; 7284 char buf[FM_MAX_CLASS]; 7285 7286 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 7287 ena = fm_ena_generate(0, FM_ENA_FMT1); 7288 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities)) { 7289 ddi_fm_ereport_post(instance->dip, buf, ena, DDI_NOSLEEP, 7290 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERSION, NULL); 7291 } 7292 } 7293 7294 static int 7295 mrsas_add_intrs(struct mrsas_instance *instance, int intr_type) 7296 { 7297 7298 dev_info_t *dip = instance->dip; 7299 int avail, actual, count; 7300 int i, flag, ret; 7301 7302 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_type = %x", 7303 intr_type)); 7304 7305 /* Get number of interrupts */ 7306 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 7307 if ((ret != DDI_SUCCESS) || (count == 0)) { 7308 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_nintrs() failed:" 7309 "ret %d count %d", ret, count)); 7310 7311 return (DDI_FAILURE); 7312 } 7313 7314 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: count = %d ", count)); 7315 7316 /* Get number of available interrupts */ 7317 ret = ddi_intr_get_navail(dip, intr_type, &avail); 7318 if ((ret != DDI_SUCCESS) || (avail == 0)) { 7319 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_navail() failed:" 7320 "ret %d avail %d", ret, avail)); 7321 7322 return (DDI_FAILURE); 7323 } 7324 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: avail = %d ", avail)); 7325 7326 /* Only one interrupt routine. So limit the count to 1 */ 7327 if (count > 1) { 7328 count = 1; 7329 } 7330 7331 /* 7332 * Allocate an array of interrupt handlers. Currently we support 7333 * only one interrupt. The framework can be extended later. 7334 */ 7335 instance->intr_htable_size = count * sizeof (ddi_intr_handle_t); 7336 instance->intr_htable = kmem_zalloc(instance->intr_htable_size, 7337 KM_SLEEP); 7338 ASSERT(instance->intr_htable); 7339 7340 flag = ((intr_type == DDI_INTR_TYPE_MSI) || 7341 (intr_type == DDI_INTR_TYPE_MSIX)) ? 7342 DDI_INTR_ALLOC_STRICT : DDI_INTR_ALLOC_NORMAL; 7343 7344 /* Allocate interrupt */ 7345 ret = ddi_intr_alloc(dip, instance->intr_htable, intr_type, 0, 7346 count, &actual, flag); 7347 7348 if ((ret != DDI_SUCCESS) || (actual == 0)) { 7349 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 7350 "avail = %d", avail)); 7351 goto mrsas_free_htable; 7352 } 7353 7354 if (actual < count) { 7355 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 7356 "Requested = %d Received = %d", count, actual)); 7357 } 7358 instance->intr_cnt = actual; 7359 7360 /* 7361 * Get the priority of the interrupt allocated. 7362 */ 7363 if ((ret = ddi_intr_get_pri(instance->intr_htable[0], 7364 &instance->intr_pri)) != DDI_SUCCESS) { 7365 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 7366 "get priority call failed")); 7367 goto mrsas_free_handles; 7368 } 7369 7370 /* 7371 * Test for high level mutex. we don't support them. 7372 */ 7373 if (instance->intr_pri >= ddi_intr_get_hilevel_pri()) { 7374 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 7375 "High level interrupts not supported.")); 7376 goto mrsas_free_handles; 7377 } 7378 7379 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_pri = 0x%x ", 7380 instance->intr_pri)); 7381 7382 /* Call ddi_intr_add_handler() */ 7383 for (i = 0; i < actual; i++) { 7384 ret = ddi_intr_add_handler(instance->intr_htable[i], 7385 (ddi_intr_handler_t *)mrsas_isr, (caddr_t)instance, 7386 (caddr_t)(uintptr_t)i); 7387 7388 if (ret != DDI_SUCCESS) { 7389 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs:" 7390 "failed %d", ret)); 7391 goto mrsas_free_handles; 7392 } 7393 7394 } 7395 7396 con_log(CL_DLEVEL1, (CE_NOTE, " ddi_intr_add_handler done")); 7397 7398 if ((ret = ddi_intr_get_cap(instance->intr_htable[0], 7399 &instance->intr_cap)) != DDI_SUCCESS) { 7400 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_cap() failed %d", 7401 ret)); 7402 goto mrsas_free_handlers; 7403 } 7404 7405 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) { 7406 con_log(CL_ANN, (CE_WARN, "Calling ddi_intr_block _enable")); 7407 7408 (void) ddi_intr_block_enable(instance->intr_htable, 7409 instance->intr_cnt); 7410 } else { 7411 con_log(CL_ANN, (CE_NOTE, " calling ddi_intr_enable")); 7412 7413 for (i = 0; i < instance->intr_cnt; i++) { 7414 (void) ddi_intr_enable(instance->intr_htable[i]); 7415 con_log(CL_ANN, (CE_NOTE, "ddi intr enable returns " 7416 "%d", i)); 7417 } 7418 } 7419 7420 return (DDI_SUCCESS); 7421 7422 mrsas_free_handlers: 7423 for (i = 0; i < actual; i++) 7424 (void) ddi_intr_remove_handler(instance->intr_htable[i]); 7425 7426 mrsas_free_handles: 7427 for (i = 0; i < actual; i++) 7428 (void) ddi_intr_free(instance->intr_htable[i]); 7429 7430 mrsas_free_htable: 7431 if (instance->intr_htable != NULL) 7432 kmem_free(instance->intr_htable, instance->intr_htable_size); 7433 7434 instance->intr_htable = NULL; 7435 instance->intr_htable_size = 0; 7436 7437 return (DDI_FAILURE); 7438 7439 } 7440 7441 7442 static void 7443 mrsas_rem_intrs(struct mrsas_instance *instance) 7444 { 7445 int i; 7446 7447 con_log(CL_ANN, (CE_NOTE, "mrsas_rem_intrs called")); 7448 7449 /* Disable all interrupts first */ 7450 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) { 7451 (void) ddi_intr_block_disable(instance->intr_htable, 7452 instance->intr_cnt); 7453 } else { 7454 for (i = 0; i < instance->intr_cnt; i++) { 7455 (void) ddi_intr_disable(instance->intr_htable[i]); 7456 } 7457 } 7458 7459 /* Remove all the handlers */ 7460 7461 for (i = 0; i < instance->intr_cnt; i++) { 7462 (void) ddi_intr_remove_handler(instance->intr_htable[i]); 7463 (void) ddi_intr_free(instance->intr_htable[i]); 7464 } 7465 7466 if (instance->intr_htable != NULL) 7467 kmem_free(instance->intr_htable, instance->intr_htable_size); 7468 7469 instance->intr_htable = NULL; 7470 instance->intr_htable_size = 0; 7471 7472 } 7473 7474 static int 7475 mrsas_tran_bus_config(dev_info_t *parent, uint_t flags, 7476 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 7477 { 7478 struct mrsas_instance *instance; 7479 int config; 7480 int rval = NDI_SUCCESS; 7481 7482 char *ptr = NULL; 7483 int tgt, lun; 7484 7485 con_log(CL_ANN1, (CE_NOTE, "Bus config called for op = %x", op)); 7486 7487 if ((instance = ddi_get_soft_state(mrsas_state, 7488 ddi_get_instance(parent))) == NULL) { 7489 return (NDI_FAILURE); 7490 } 7491 7492 /* Hold nexus during bus_config */ 7493 ndi_devi_enter(parent, &config); 7494 switch (op) { 7495 case BUS_CONFIG_ONE: { 7496 7497 /* parse wwid/target name out of name given */ 7498 if ((ptr = strchr((char *)arg, '@')) == NULL) { 7499 rval = NDI_FAILURE; 7500 break; 7501 } 7502 ptr++; 7503 7504 if (mrsas_parse_devname(arg, &tgt, &lun) != 0) { 7505 rval = NDI_FAILURE; 7506 break; 7507 } 7508 7509 if (lun == 0) { 7510 rval = mrsas_config_ld(instance, tgt, lun, childp); 7511 #ifdef PDSUPPORT 7512 } else if ((instance->tbolt || instance->skinny) && lun != 0) { 7513 rval = mrsas_tbolt_config_pd(instance, 7514 tgt, lun, childp); 7515 #endif 7516 } else { 7517 rval = NDI_FAILURE; 7518 } 7519 7520 break; 7521 } 7522 case BUS_CONFIG_DRIVER: 7523 case BUS_CONFIG_ALL: { 7524 7525 rval = mrsas_config_all_devices(instance); 7526 7527 rval = NDI_SUCCESS; 7528 break; 7529 } 7530 } 7531 7532 if (rval == NDI_SUCCESS) { 7533 rval = ndi_busop_bus_config(parent, flags, op, arg, childp, 0); 7534 7535 } 7536 ndi_devi_exit(parent, config); 7537 7538 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_bus_config: rval = %x", 7539 rval)); 7540 return (rval); 7541 } 7542 7543 static int 7544 mrsas_config_all_devices(struct mrsas_instance *instance) 7545 { 7546 int rval, tgt; 7547 7548 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) { 7549 (void) mrsas_config_ld(instance, tgt, 0, NULL); 7550 7551 } 7552 7553 #ifdef PDSUPPORT 7554 /* Config PD devices connected to the card */ 7555 if (instance->tbolt || instance->skinny) { 7556 for (tgt = 0; tgt < instance->mr_tbolt_pd_max; tgt++) { 7557 (void) mrsas_tbolt_config_pd(instance, tgt, 1, NULL); 7558 } 7559 } 7560 #endif 7561 7562 rval = NDI_SUCCESS; 7563 return (rval); 7564 } 7565 7566 static int 7567 mrsas_parse_devname(char *devnm, int *tgt, int *lun) 7568 { 7569 char devbuf[SCSI_MAXNAMELEN]; 7570 char *addr; 7571 char *p, *tp, *lp; 7572 long num; 7573 7574 /* Parse dev name and address */ 7575 (void) strcpy(devbuf, devnm); 7576 addr = ""; 7577 for (p = devbuf; *p != '\0'; p++) { 7578 if (*p == '@') { 7579 addr = p + 1; 7580 *p = '\0'; 7581 } else if (*p == ':') { 7582 *p = '\0'; 7583 break; 7584 } 7585 } 7586 7587 /* Parse target and lun */ 7588 for (p = tp = addr, lp = NULL; *p != '\0'; p++) { 7589 if (*p == ',') { 7590 lp = p + 1; 7591 *p = '\0'; 7592 break; 7593 } 7594 } 7595 if (tgt && tp) { 7596 if (ddi_strtol(tp, NULL, 0x10, &num)) { 7597 return (DDI_FAILURE); /* Can declare this as constant */ 7598 } 7599 *tgt = (int)num; 7600 } 7601 if (lun && lp) { 7602 if (ddi_strtol(lp, NULL, 0x10, &num)) { 7603 return (DDI_FAILURE); 7604 } 7605 *lun = (int)num; 7606 } 7607 return (DDI_SUCCESS); /* Success case */ 7608 } 7609 7610 static int 7611 mrsas_config_ld(struct mrsas_instance *instance, uint16_t tgt, 7612 uint8_t lun, dev_info_t **ldip) 7613 { 7614 struct scsi_device *sd; 7615 dev_info_t *child; 7616 int rval; 7617 7618 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: t = %d l = %d", 7619 tgt, lun)); 7620 7621 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) { 7622 if (ldip) { 7623 *ldip = child; 7624 } 7625 if (instance->mr_ld_list[tgt].flag != MRDRV_TGT_VALID) { 7626 rval = mrsas_service_evt(instance, tgt, 0, 7627 MRSAS_EVT_UNCONFIG_TGT, NULL); 7628 con_log(CL_ANN1, (CE_WARN, 7629 "mr_sas: DELETING STALE ENTRY rval = %d " 7630 "tgt id = %d ", rval, tgt)); 7631 return (NDI_FAILURE); 7632 } 7633 return (NDI_SUCCESS); 7634 } 7635 7636 sd = kmem_zalloc(sizeof (struct scsi_device), KM_SLEEP); 7637 sd->sd_address.a_hba_tran = instance->tran; 7638 sd->sd_address.a_target = (uint16_t)tgt; 7639 sd->sd_address.a_lun = (uint8_t)lun; 7640 7641 if (scsi_hba_probe(sd, NULL) == SCSIPROBE_EXISTS) 7642 rval = mrsas_config_scsi_device(instance, sd, ldip); 7643 else 7644 rval = NDI_FAILURE; 7645 7646 /* sd_unprobe is blank now. Free buffer manually */ 7647 if (sd->sd_inq) { 7648 kmem_free(sd->sd_inq, SUN_INQSIZE); 7649 sd->sd_inq = (struct scsi_inquiry *)NULL; 7650 } 7651 7652 kmem_free(sd, sizeof (struct scsi_device)); 7653 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: return rval = %d", 7654 rval)); 7655 return (rval); 7656 } 7657 7658 int 7659 mrsas_config_scsi_device(struct mrsas_instance *instance, 7660 struct scsi_device *sd, dev_info_t **dipp) 7661 { 7662 char *nodename = NULL; 7663 char **compatible = NULL; 7664 int ncompatible = 0; 7665 char *childname; 7666 dev_info_t *ldip = NULL; 7667 int tgt = sd->sd_address.a_target; 7668 int lun = sd->sd_address.a_lun; 7669 int dtype = sd->sd_inq->inq_dtype & DTYPE_MASK; 7670 int rval; 7671 7672 con_log(CL_DLEVEL1, (CE_NOTE, "mr_sas: scsi_device t%dL%d", tgt, lun)); 7673 scsi_hba_nodename_compatible_get(sd->sd_inq, NULL, dtype, 7674 NULL, &nodename, &compatible, &ncompatible); 7675 7676 if (nodename == NULL) { 7677 con_log(CL_ANN1, (CE_WARN, "mr_sas: Found no compatible driver " 7678 "for t%dL%d", tgt, lun)); 7679 rval = NDI_FAILURE; 7680 goto finish; 7681 } 7682 7683 childname = (dtype == DTYPE_DIRECT) ? "sd" : nodename; 7684 con_log(CL_DLEVEL1, (CE_NOTE, 7685 "mr_sas: Childname = %2s nodename = %s", childname, nodename)); 7686 7687 /* Create a dev node */ 7688 rval = ndi_devi_alloc(instance->dip, childname, DEVI_SID_NODEID, &ldip); 7689 con_log(CL_DLEVEL1, (CE_NOTE, 7690 "mr_sas_config_scsi_device: ndi_devi_alloc rval = %x", rval)); 7691 if (rval == NDI_SUCCESS) { 7692 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "target", tgt) != 7693 DDI_PROP_SUCCESS) { 7694 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create " 7695 "property for t%dl%d target", tgt, lun)); 7696 rval = NDI_FAILURE; 7697 goto finish; 7698 } 7699 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "lun", lun) != 7700 DDI_PROP_SUCCESS) { 7701 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create " 7702 "property for t%dl%d lun", tgt, lun)); 7703 rval = NDI_FAILURE; 7704 goto finish; 7705 } 7706 7707 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, ldip, 7708 "compatible", compatible, ncompatible) != 7709 DDI_PROP_SUCCESS) { 7710 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create " 7711 "property for t%dl%d compatible", tgt, lun)); 7712 rval = NDI_FAILURE; 7713 goto finish; 7714 } 7715 7716 rval = ndi_devi_online(ldip, NDI_ONLINE_ATTACH); 7717 if (rval != NDI_SUCCESS) { 7718 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to online " 7719 "t%dl%d", tgt, lun)); 7720 ndi_prop_remove_all(ldip); 7721 (void) ndi_devi_free(ldip); 7722 } else { 7723 con_log(CL_ANN1, (CE_CONT, "mr_sas: online Done :" 7724 "0 t%dl%d", tgt, lun)); 7725 } 7726 7727 } 7728 finish: 7729 if (dipp) { 7730 *dipp = ldip; 7731 } 7732 7733 con_log(CL_DLEVEL1, (CE_NOTE, 7734 "mr_sas: config_scsi_device rval = %d t%dL%d", 7735 rval, tgt, lun)); 7736 scsi_hba_nodename_compatible_free(nodename, compatible); 7737 return (rval); 7738 } 7739 7740 /*ARGSUSED*/ 7741 int 7742 mrsas_service_evt(struct mrsas_instance *instance, int tgt, int lun, int event, 7743 uint64_t wwn) 7744 { 7745 struct mrsas_eventinfo *mrevt = NULL; 7746 7747 con_log(CL_ANN1, (CE_NOTE, 7748 "mrsas_service_evt called for t%dl%d event = %d", 7749 tgt, lun, event)); 7750 7751 if ((instance->taskq == NULL) || (mrevt = 7752 kmem_zalloc(sizeof (struct mrsas_eventinfo), KM_NOSLEEP)) == NULL) { 7753 return (ENOMEM); 7754 } 7755 7756 mrevt->instance = instance; 7757 mrevt->tgt = tgt; 7758 mrevt->lun = lun; 7759 mrevt->event = event; 7760 mrevt->wwn = wwn; 7761 7762 if ((ddi_taskq_dispatch(instance->taskq, 7763 (void (*)(void *))mrsas_issue_evt_taskq, mrevt, DDI_NOSLEEP)) != 7764 DDI_SUCCESS) { 7765 con_log(CL_ANN1, (CE_NOTE, 7766 "mr_sas: Event task failed for t%dl%d event = %d", 7767 tgt, lun, event)); 7768 kmem_free(mrevt, sizeof (struct mrsas_eventinfo)); 7769 return (DDI_FAILURE); 7770 } 7771 DTRACE_PROBE3(service_evt, int, tgt, int, lun, int, event); 7772 return (DDI_SUCCESS); 7773 } 7774 7775 static void 7776 mrsas_issue_evt_taskq(struct mrsas_eventinfo *mrevt) 7777 { 7778 struct mrsas_instance *instance = mrevt->instance; 7779 dev_info_t *dip, *pdip; 7780 int circ1 = 0; 7781 char *devname; 7782 7783 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_evt_taskq: called for" 7784 " tgt %d lun %d event %d", 7785 mrevt->tgt, mrevt->lun, mrevt->event)); 7786 7787 if (mrevt->tgt < MRDRV_MAX_LD && mrevt->lun == 0) { 7788 mutex_enter(&instance->config_dev_mtx); 7789 dip = instance->mr_ld_list[mrevt->tgt].dip; 7790 mutex_exit(&instance->config_dev_mtx); 7791 #ifdef PDSUPPORT 7792 } else { 7793 mutex_enter(&instance->config_dev_mtx); 7794 dip = instance->mr_tbolt_pd_list[mrevt->tgt].dip; 7795 mutex_exit(&instance->config_dev_mtx); 7796 #endif 7797 } 7798 7799 7800 ndi_devi_enter(instance->dip, &circ1); 7801 switch (mrevt->event) { 7802 case MRSAS_EVT_CONFIG_TGT: 7803 if (dip == NULL) { 7804 7805 if (mrevt->lun == 0) { 7806 (void) mrsas_config_ld(instance, mrevt->tgt, 7807 0, NULL); 7808 #ifdef PDSUPPORT 7809 } else if (instance->tbolt || instance->skinny) { 7810 (void) mrsas_tbolt_config_pd(instance, 7811 mrevt->tgt, 7812 1, NULL); 7813 #endif 7814 } 7815 con_log(CL_ANN1, (CE_NOTE, 7816 "mr_sas: EVT_CONFIG_TGT called:" 7817 " for tgt %d lun %d event %d", 7818 mrevt->tgt, mrevt->lun, mrevt->event)); 7819 7820 } else { 7821 con_log(CL_ANN1, (CE_NOTE, 7822 "mr_sas: EVT_CONFIG_TGT dip != NULL:" 7823 " for tgt %d lun %d event %d", 7824 mrevt->tgt, mrevt->lun, mrevt->event)); 7825 } 7826 break; 7827 case MRSAS_EVT_UNCONFIG_TGT: 7828 if (dip) { 7829 if (i_ddi_devi_attached(dip)) { 7830 7831 pdip = ddi_get_parent(dip); 7832 7833 devname = kmem_zalloc(MAXNAMELEN + 1, KM_SLEEP); 7834 (void) ddi_deviname(dip, devname); 7835 7836 (void) devfs_clean(pdip, devname + 1, 7837 DV_CLEAN_FORCE); 7838 kmem_free(devname, MAXNAMELEN + 1); 7839 } 7840 (void) ndi_devi_offline(dip, NDI_DEVI_REMOVE); 7841 con_log(CL_ANN1, (CE_NOTE, 7842 "mr_sas: EVT_UNCONFIG_TGT called:" 7843 " for tgt %d lun %d event %d", 7844 mrevt->tgt, mrevt->lun, mrevt->event)); 7845 } else { 7846 con_log(CL_ANN1, (CE_NOTE, 7847 "mr_sas: EVT_UNCONFIG_TGT dip == NULL:" 7848 " for tgt %d lun %d event %d", 7849 mrevt->tgt, mrevt->lun, mrevt->event)); 7850 } 7851 break; 7852 } 7853 kmem_free(mrevt, sizeof (struct mrsas_eventinfo)); 7854 ndi_devi_exit(instance->dip, circ1); 7855 } 7856 7857 7858 int 7859 mrsas_mode_sense_build(struct scsi_pkt *pkt) 7860 { 7861 union scsi_cdb *cdbp; 7862 uint16_t page_code; 7863 struct scsa_cmd *acmd; 7864 struct buf *bp; 7865 struct mode_header *modehdrp; 7866 7867 cdbp = (void *)pkt->pkt_cdbp; 7868 page_code = cdbp->cdb_un.sg.scsi[0]; 7869 acmd = PKT2CMD(pkt); 7870 bp = acmd->cmd_buf; 7871 if ((!bp) && bp->b_un.b_addr && bp->b_bcount && acmd->cmd_dmacount) { 7872 con_log(CL_ANN1, (CE_WARN, "Failing MODESENSE Command")); 7873 /* ADD pkt statistics as Command failed. */ 7874 return (NULL); 7875 } 7876 7877 bp_mapin(bp); 7878 bzero(bp->b_un.b_addr, bp->b_bcount); 7879 7880 switch (page_code) { 7881 case 0x3: { 7882 struct mode_format *page3p = NULL; 7883 modehdrp = (struct mode_header *)(bp->b_un.b_addr); 7884 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH; 7885 7886 page3p = (void *)((caddr_t)modehdrp + 7887 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH); 7888 page3p->mode_page.code = 0x3; 7889 page3p->mode_page.length = 7890 (uchar_t)(sizeof (struct mode_format)); 7891 page3p->data_bytes_sect = 512; 7892 page3p->sect_track = 63; 7893 break; 7894 } 7895 case 0x4: { 7896 struct mode_geometry *page4p = NULL; 7897 modehdrp = (struct mode_header *)(bp->b_un.b_addr); 7898 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH; 7899 7900 page4p = (void *)((caddr_t)modehdrp + 7901 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH); 7902 page4p->mode_page.code = 0x4; 7903 page4p->mode_page.length = 7904 (uchar_t)(sizeof (struct mode_geometry)); 7905 page4p->heads = 255; 7906 page4p->rpm = 10000; 7907 break; 7908 } 7909 default: 7910 break; 7911 } 7912 return (NULL); 7913 } 7914