1 /* 2 * mr_sas.c: source for mr_sas driver 3 * 4 * MegaRAID device driver for SAS2.0 controllers 5 * Copyright (c) 2008-2010, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Version: 9 * Author: 10 * Arun Chandrashekhar 11 * Manju R 12 * Rajesh Prabhakaran 13 * Seokmann Ju 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions are met: 17 * 18 * 1. Redistributions of source code must retain the above copyright notice, 19 * this list of conditions and the following disclaimer. 20 * 21 * 2. Redistributions in binary form must reproduce the above copyright notice, 22 * this list of conditions and the following disclaimer in the documentation 23 * and/or other materials provided with the distribution. 24 * 25 * 3. Neither the name of the author nor the names of its contributors may be 26 * used to endorse or promote products derived from this software without 27 * specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 32 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 33 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 37 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 39 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 40 * DAMAGE. 41 */ 42 43 /* 44 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/file.h> 50 #include <sys/errno.h> 51 #include <sys/open.h> 52 #include <sys/cred.h> 53 #include <sys/modctl.h> 54 #include <sys/conf.h> 55 #include <sys/devops.h> 56 #include <sys/cmn_err.h> 57 #include <sys/kmem.h> 58 #include <sys/stat.h> 59 #include <sys/mkdev.h> 60 #include <sys/pci.h> 61 #include <sys/scsi/scsi.h> 62 #include <sys/ddi.h> 63 #include <sys/sunddi.h> 64 #include <sys/atomic.h> 65 #include <sys/signal.h> 66 #include <sys/byteorder.h> 67 #include <sys/sdt.h> 68 #include <sys/fs/dv_node.h> /* devfs_clean */ 69 70 #include "mr_sas.h" 71 72 /* 73 * FMA header files 74 */ 75 #include <sys/ddifm.h> 76 #include <sys/fm/protocol.h> 77 #include <sys/fm/util.h> 78 #include <sys/fm/io/ddi.h> 79 80 /* 81 * Local static data 82 */ 83 static void *mrsas_state = NULL; 84 static volatile boolean_t mrsas_relaxed_ordering = B_TRUE; 85 static volatile int debug_level_g = CL_NONE; 86 static volatile int msi_enable = 1; 87 static volatile int ctio_enable = 1; 88 89 /* Default Timeout value to issue online controller reset */ 90 static volatile int debug_timeout_g = 0x12C; 91 /* Simulate consecutive firmware fault */ 92 static volatile int debug_fw_faults_after_ocr_g = 0; 93 94 #ifdef OCRDEBUG 95 /* Simulate three consecutive timeout for an IO */ 96 static volatile int debug_consecutive_timeout_after_ocr_g = 0; 97 #endif 98 99 #pragma weak scsi_hba_open 100 #pragma weak scsi_hba_close 101 #pragma weak scsi_hba_ioctl 102 103 static ddi_dma_attr_t mrsas_generic_dma_attr = { 104 DMA_ATTR_V0, /* dma_attr_version */ 105 0, /* low DMA address range */ 106 0xFFFFFFFFU, /* high DMA address range */ 107 0xFFFFFFFFU, /* DMA counter register */ 108 8, /* DMA address alignment */ 109 0x07, /* DMA burstsizes */ 110 1, /* min DMA size */ 111 0xFFFFFFFFU, /* max DMA size */ 112 0xFFFFFFFFU, /* segment boundary */ 113 MRSAS_MAX_SGE_CNT, /* dma_attr_sglen */ 114 512, /* granularity of device */ 115 0 /* bus specific DMA flags */ 116 }; 117 118 int32_t mrsas_max_cap_maxxfer = 0x1000000; 119 120 /* 121 * cb_ops contains base level routines 122 */ 123 static struct cb_ops mrsas_cb_ops = { 124 mrsas_open, /* open */ 125 mrsas_close, /* close */ 126 nodev, /* strategy */ 127 nodev, /* print */ 128 nodev, /* dump */ 129 nodev, /* read */ 130 nodev, /* write */ 131 mrsas_ioctl, /* ioctl */ 132 nodev, /* devmap */ 133 nodev, /* mmap */ 134 nodev, /* segmap */ 135 nochpoll, /* poll */ 136 nodev, /* cb_prop_op */ 137 0, /* streamtab */ 138 D_NEW | D_HOTPLUG, /* cb_flag */ 139 CB_REV, /* cb_rev */ 140 nodev, /* cb_aread */ 141 nodev /* cb_awrite */ 142 }; 143 144 /* 145 * dev_ops contains configuration routines 146 */ 147 static struct dev_ops mrsas_ops = { 148 DEVO_REV, /* rev, */ 149 0, /* refcnt */ 150 mrsas_getinfo, /* getinfo */ 151 nulldev, /* identify */ 152 nulldev, /* probe */ 153 mrsas_attach, /* attach */ 154 mrsas_detach, /* detach */ 155 mrsas_reset, /* reset */ 156 &mrsas_cb_ops, /* char/block ops */ 157 NULL, /* bus ops */ 158 NULL, /* power */ 159 ddi_quiesce_not_supported, /* quiesce */ 160 }; 161 162 char _depends_on[] = "misc/scsi"; 163 164 static struct modldrv modldrv = { 165 &mod_driverops, /* module type - driver */ 166 MRSAS_VERSION, 167 &mrsas_ops, /* driver ops */ 168 }; 169 170 static struct modlinkage modlinkage = { 171 MODREV_1, /* ml_rev - must be MODREV_1 */ 172 &modldrv, /* ml_linkage */ 173 NULL /* end of driver linkage */ 174 }; 175 176 static struct ddi_device_acc_attr endian_attr = { 177 DDI_DEVICE_ATTR_V1, 178 DDI_STRUCTURE_LE_ACC, 179 DDI_STRICTORDER_ACC, 180 DDI_DEFAULT_ACC 181 }; 182 183 184 /* 185 * ************************************************************************** * 186 * * 187 * common entry points - for loadable kernel modules * 188 * * 189 * ************************************************************************** * 190 */ 191 192 int 193 _init(void) 194 { 195 int ret; 196 197 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 198 199 ret = ddi_soft_state_init(&mrsas_state, 200 sizeof (struct mrsas_instance), 0); 201 202 if (ret != DDI_SUCCESS) { 203 con_log(CL_ANN, (CE_WARN, "mr_sas: could not init state")); 204 return (ret); 205 } 206 207 if ((ret = scsi_hba_init(&modlinkage)) != DDI_SUCCESS) { 208 con_log(CL_ANN, (CE_WARN, "mr_sas: could not init scsi hba")); 209 ddi_soft_state_fini(&mrsas_state); 210 return (ret); 211 } 212 213 ret = mod_install(&modlinkage); 214 215 if (ret != DDI_SUCCESS) { 216 con_log(CL_ANN, (CE_WARN, "mr_sas: mod_install failed")); 217 scsi_hba_fini(&modlinkage); 218 ddi_soft_state_fini(&mrsas_state); 219 } 220 221 return (ret); 222 } 223 224 int 225 _info(struct modinfo *modinfop) 226 { 227 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 228 229 return (mod_info(&modlinkage, modinfop)); 230 } 231 232 int 233 _fini(void) 234 { 235 int ret; 236 237 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 238 239 if ((ret = mod_remove(&modlinkage)) != DDI_SUCCESS) 240 return (ret); 241 242 scsi_hba_fini(&modlinkage); 243 244 ddi_soft_state_fini(&mrsas_state); 245 246 return (ret); 247 } 248 249 250 /* 251 * ************************************************************************** * 252 * * 253 * common entry points - for autoconfiguration * 254 * * 255 * ************************************************************************** * 256 */ 257 258 static int 259 mrsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 260 { 261 int instance_no; 262 int nregs; 263 uint8_t added_isr_f = 0; 264 uint8_t added_soft_isr_f = 0; 265 uint8_t create_devctl_node_f = 0; 266 uint8_t create_scsi_node_f = 0; 267 uint8_t create_ioc_node_f = 0; 268 uint8_t tran_alloc_f = 0; 269 uint8_t irq; 270 uint16_t vendor_id; 271 uint16_t device_id; 272 uint16_t subsysvid; 273 uint16_t subsysid; 274 uint16_t command; 275 off_t reglength = 0; 276 int intr_types = 0; 277 char *data; 278 279 scsi_hba_tran_t *tran; 280 ddi_dma_attr_t tran_dma_attr; 281 struct mrsas_instance *instance; 282 283 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 284 285 /* CONSTCOND */ 286 ASSERT(NO_COMPETING_THREADS); 287 288 instance_no = ddi_get_instance(dip); 289 290 /* 291 * check to see whether this device is in a DMA-capable slot. 292 */ 293 if (ddi_slaveonly(dip) == DDI_SUCCESS) { 294 con_log(CL_ANN, (CE_WARN, 295 "mr_sas%d: Device in slave-only slot, unused", 296 instance_no)); 297 return (DDI_FAILURE); 298 } 299 300 switch (cmd) { 301 case DDI_ATTACH: 302 con_log(CL_DLEVEL1, (CE_NOTE, "mr_sas: DDI_ATTACH")); 303 /* allocate the soft state for the instance */ 304 if (ddi_soft_state_zalloc(mrsas_state, instance_no) 305 != DDI_SUCCESS) { 306 con_log(CL_ANN, (CE_WARN, 307 "mr_sas%d: Failed to allocate soft state", 308 instance_no)); 309 310 return (DDI_FAILURE); 311 } 312 313 instance = (struct mrsas_instance *)ddi_get_soft_state 314 (mrsas_state, instance_no); 315 316 if (instance == NULL) { 317 con_log(CL_ANN, (CE_WARN, 318 "mr_sas%d: Bad soft state", instance_no)); 319 320 ddi_soft_state_free(mrsas_state, instance_no); 321 322 return (DDI_FAILURE); 323 } 324 325 bzero((caddr_t)instance, 326 sizeof (struct mrsas_instance)); 327 328 instance->func_ptr = kmem_zalloc( 329 sizeof (struct mrsas_func_ptr), KM_SLEEP); 330 ASSERT(instance->func_ptr); 331 332 /* Setup the PCI configuration space handles */ 333 if (pci_config_setup(dip, &instance->pci_handle) != 334 DDI_SUCCESS) { 335 con_log(CL_ANN, (CE_WARN, 336 "mr_sas%d: pci config setup failed ", 337 instance_no)); 338 339 kmem_free(instance->func_ptr, 340 sizeof (struct mrsas_func_ptr)); 341 ddi_soft_state_free(mrsas_state, instance_no); 342 343 return (DDI_FAILURE); 344 } 345 346 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) { 347 con_log(CL_ANN, (CE_WARN, 348 "mr_sas: failed to get registers.")); 349 350 pci_config_teardown(&instance->pci_handle); 351 kmem_free(instance->func_ptr, 352 sizeof (struct mrsas_func_ptr)); 353 ddi_soft_state_free(mrsas_state, instance_no); 354 355 return (DDI_FAILURE); 356 } 357 358 vendor_id = pci_config_get16(instance->pci_handle, 359 PCI_CONF_VENID); 360 device_id = pci_config_get16(instance->pci_handle, 361 PCI_CONF_DEVID); 362 363 subsysvid = pci_config_get16(instance->pci_handle, 364 PCI_CONF_SUBVENID); 365 subsysid = pci_config_get16(instance->pci_handle, 366 PCI_CONF_SUBSYSID); 367 368 pci_config_put16(instance->pci_handle, PCI_CONF_COMM, 369 (pci_config_get16(instance->pci_handle, 370 PCI_CONF_COMM) | PCI_COMM_ME)); 371 irq = pci_config_get8(instance->pci_handle, 372 PCI_CONF_ILINE); 373 374 con_log(CL_DLEVEL1, (CE_CONT, "mr_sas%d: " 375 "0x%x:0x%x 0x%x:0x%x, irq:%d drv-ver:%s", 376 instance_no, vendor_id, device_id, subsysvid, 377 subsysid, irq, MRSAS_VERSION)); 378 379 /* enable bus-mastering */ 380 command = pci_config_get16(instance->pci_handle, 381 PCI_CONF_COMM); 382 383 if (!(command & PCI_COMM_ME)) { 384 command |= PCI_COMM_ME; 385 386 pci_config_put16(instance->pci_handle, 387 PCI_CONF_COMM, command); 388 389 con_log(CL_ANN, (CE_CONT, "mr_sas%d: " 390 "enable bus-mastering", instance_no)); 391 } else { 392 con_log(CL_DLEVEL1, (CE_CONT, "mr_sas%d: " 393 "bus-mastering already set", instance_no)); 394 } 395 396 /* initialize function pointers */ 397 if ((device_id == PCI_DEVICE_ID_LSI_2108VDE) || 398 (device_id == PCI_DEVICE_ID_LSI_2108V)) { 399 con_log(CL_DLEVEL1, (CE_CONT, "mr_sas%d: " 400 "2108V/DE detected", instance_no)); 401 instance->func_ptr->read_fw_status_reg = 402 read_fw_status_reg_ppc; 403 instance->func_ptr->issue_cmd = issue_cmd_ppc; 404 instance->func_ptr->issue_cmd_in_sync_mode = 405 issue_cmd_in_sync_mode_ppc; 406 instance->func_ptr->issue_cmd_in_poll_mode = 407 issue_cmd_in_poll_mode_ppc; 408 instance->func_ptr->enable_intr = 409 enable_intr_ppc; 410 instance->func_ptr->disable_intr = 411 disable_intr_ppc; 412 instance->func_ptr->intr_ack = intr_ack_ppc; 413 } else { 414 con_log(CL_ANN, (CE_WARN, 415 "mr_sas: Invalid device detected")); 416 417 pci_config_teardown(&instance->pci_handle); 418 kmem_free(instance->func_ptr, 419 sizeof (struct mrsas_func_ptr)); 420 ddi_soft_state_free(mrsas_state, instance_no); 421 422 return (DDI_FAILURE); 423 } 424 425 instance->baseaddress = pci_config_get32( 426 instance->pci_handle, PCI_CONF_BASE0); 427 instance->baseaddress &= 0x0fffc; 428 429 instance->dip = dip; 430 instance->vendor_id = vendor_id; 431 instance->device_id = device_id; 432 instance->subsysvid = subsysvid; 433 instance->subsysid = subsysid; 434 instance->instance = instance_no; 435 436 /* Initialize FMA */ 437 instance->fm_capabilities = ddi_prop_get_int( 438 DDI_DEV_T_ANY, instance->dip, DDI_PROP_DONTPASS, 439 "fm-capable", DDI_FM_EREPORT_CAPABLE | 440 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE 441 | DDI_FM_ERRCB_CAPABLE); 442 443 mrsas_fm_init(instance); 444 445 /* Initialize Interrupts */ 446 if ((ddi_dev_regsize(instance->dip, 447 REGISTER_SET_IO_2108, ®length) != DDI_SUCCESS) || 448 reglength < MINIMUM_MFI_MEM_SZ) { 449 return (DDI_FAILURE); 450 } 451 if (reglength > DEFAULT_MFI_MEM_SZ) { 452 reglength = DEFAULT_MFI_MEM_SZ; 453 con_log(CL_DLEVEL1, (CE_NOTE, 454 "mr_sas: register length to map is " 455 "0x%lx bytes", reglength)); 456 } 457 if (ddi_regs_map_setup(instance->dip, 458 REGISTER_SET_IO_2108, &instance->regmap, 0, 459 reglength, &endian_attr, &instance->regmap_handle) 460 != DDI_SUCCESS) { 461 con_log(CL_ANN, (CE_NOTE, 462 "mr_sas: couldn't map control registers")); 463 goto fail_attach; 464 } 465 466 /* 467 * Disable Interrupt Now. 468 * Setup Software interrupt 469 */ 470 instance->func_ptr->disable_intr(instance); 471 472 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 473 "mrsas-enable-msi", &data) == DDI_SUCCESS) { 474 if (strncmp(data, "no", 3) == 0) { 475 msi_enable = 0; 476 con_log(CL_ANN1, (CE_WARN, 477 "msi_enable = %d disabled", 478 msi_enable)); 479 } 480 ddi_prop_free(data); 481 } 482 483 con_log(CL_DLEVEL1, (CE_WARN, "msi_enable = %d", 484 msi_enable)); 485 486 /* Check for all supported interrupt types */ 487 if (ddi_intr_get_supported_types( 488 dip, &intr_types) != DDI_SUCCESS) { 489 con_log(CL_ANN, (CE_WARN, 490 "ddi_intr_get_supported_types() failed")); 491 goto fail_attach; 492 } 493 494 con_log(CL_DLEVEL1, (CE_NOTE, 495 "ddi_intr_get_supported_types() ret: 0x%x", 496 intr_types)); 497 498 /* Initialize and Setup Interrupt handler */ 499 if (msi_enable && (intr_types & DDI_INTR_TYPE_MSIX)) { 500 if (mrsas_add_intrs(instance, 501 DDI_INTR_TYPE_MSIX) != DDI_SUCCESS) { 502 con_log(CL_ANN, (CE_WARN, 503 "MSIX interrupt query failed")); 504 goto fail_attach; 505 } 506 instance->intr_type = DDI_INTR_TYPE_MSIX; 507 } else if (msi_enable && (intr_types & 508 DDI_INTR_TYPE_MSI)) { 509 if (mrsas_add_intrs(instance, 510 DDI_INTR_TYPE_MSI) != DDI_SUCCESS) { 511 con_log(CL_ANN, (CE_WARN, 512 "MSI interrupt query failed")); 513 goto fail_attach; 514 } 515 instance->intr_type = DDI_INTR_TYPE_MSI; 516 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 517 msi_enable = 0; 518 if (mrsas_add_intrs(instance, 519 DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) { 520 con_log(CL_ANN, (CE_WARN, 521 "FIXED interrupt query failed")); 522 goto fail_attach; 523 } 524 instance->intr_type = DDI_INTR_TYPE_FIXED; 525 } else { 526 con_log(CL_ANN, (CE_WARN, "Device cannot " 527 "suppport either FIXED or MSI/X " 528 "interrupts")); 529 goto fail_attach; 530 } 531 532 added_isr_f = 1; 533 534 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 535 "mrsas-enable-ctio", &data) == DDI_SUCCESS) { 536 if (strncmp(data, "no", 3) == 0) { 537 ctio_enable = 0; 538 con_log(CL_ANN1, (CE_WARN, 539 "ctio_enable = %d disabled", 540 ctio_enable)); 541 } 542 ddi_prop_free(data); 543 } 544 545 con_log(CL_DLEVEL1, (CE_WARN, "ctio_enable = %d", 546 ctio_enable)); 547 548 /* setup the mfi based low level driver */ 549 if (init_mfi(instance) != DDI_SUCCESS) { 550 con_log(CL_ANN, (CE_WARN, "mr_sas: " 551 "could not initialize the low level driver")); 552 553 goto fail_attach; 554 } 555 556 /* Initialize all Mutex */ 557 INIT_LIST_HEAD(&instance->completed_pool_list); 558 mutex_init(&instance->completed_pool_mtx, 559 "completed_pool_mtx", MUTEX_DRIVER, 560 DDI_INTR_PRI(instance->intr_pri)); 561 562 mutex_init(&instance->app_cmd_pool_mtx, 563 "app_cmd_pool_mtx", MUTEX_DRIVER, 564 DDI_INTR_PRI(instance->intr_pri)); 565 566 mutex_init(&instance->cmd_pend_mtx, "cmd_pend_mtx", 567 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 568 569 mutex_init(&instance->ocr_flags_mtx, "ocr_flags_mtx", 570 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 571 572 mutex_init(&instance->int_cmd_mtx, "int_cmd_mtx", 573 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 574 cv_init(&instance->int_cmd_cv, NULL, CV_DRIVER, NULL); 575 576 mutex_init(&instance->cmd_pool_mtx, "cmd_pool_mtx", 577 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 578 579 instance->timeout_id = (timeout_id_t)-1; 580 581 /* Register our soft-isr for highlevel interrupts. */ 582 instance->isr_level = instance->intr_pri; 583 if (instance->isr_level == HIGH_LEVEL_INTR) { 584 if (ddi_add_softintr(dip, DDI_SOFTINT_HIGH, 585 &instance->soft_intr_id, NULL, NULL, 586 mrsas_softintr, (caddr_t)instance) != 587 DDI_SUCCESS) { 588 con_log(CL_ANN, (CE_WARN, 589 " Software ISR did not register")); 590 591 goto fail_attach; 592 } 593 594 added_soft_isr_f = 1; 595 } 596 597 /* Allocate a transport structure */ 598 tran = scsi_hba_tran_alloc(dip, SCSI_HBA_CANSLEEP); 599 600 if (tran == NULL) { 601 con_log(CL_ANN, (CE_WARN, 602 "scsi_hba_tran_alloc failed")); 603 goto fail_attach; 604 } 605 606 tran_alloc_f = 1; 607 608 instance->tran = tran; 609 610 tran->tran_hba_private = instance; 611 tran->tran_tgt_init = mrsas_tran_tgt_init; 612 tran->tran_tgt_probe = scsi_hba_probe; 613 tran->tran_tgt_free = mrsas_tran_tgt_free; 614 tran->tran_init_pkt = mrsas_tran_init_pkt; 615 tran->tran_start = mrsas_tran_start; 616 tran->tran_abort = mrsas_tran_abort; 617 tran->tran_reset = mrsas_tran_reset; 618 tran->tran_getcap = mrsas_tran_getcap; 619 tran->tran_setcap = mrsas_tran_setcap; 620 tran->tran_destroy_pkt = mrsas_tran_destroy_pkt; 621 tran->tran_dmafree = mrsas_tran_dmafree; 622 tran->tran_sync_pkt = mrsas_tran_sync_pkt; 623 tran->tran_bus_config = mrsas_tran_bus_config; 624 625 if (mrsas_relaxed_ordering) 626 mrsas_generic_dma_attr.dma_attr_flags |= 627 DDI_DMA_RELAXED_ORDERING; 628 629 630 tran_dma_attr = mrsas_generic_dma_attr; 631 tran_dma_attr.dma_attr_sgllen = instance->max_num_sge; 632 633 /* Attach this instance of the hba */ 634 if (scsi_hba_attach_setup(dip, &tran_dma_attr, tran, 0) 635 != DDI_SUCCESS) { 636 con_log(CL_ANN, (CE_WARN, 637 "scsi_hba_attach failed")); 638 639 goto fail_attach; 640 } 641 642 /* create devctl node for cfgadm command */ 643 if (ddi_create_minor_node(dip, "devctl", 644 S_IFCHR, INST2DEVCTL(instance_no), 645 DDI_NT_SCSI_NEXUS, 0) == DDI_FAILURE) { 646 con_log(CL_ANN, (CE_WARN, 647 "mr_sas: failed to create devctl node.")); 648 649 goto fail_attach; 650 } 651 652 create_devctl_node_f = 1; 653 654 /* create scsi node for cfgadm command */ 655 if (ddi_create_minor_node(dip, "scsi", S_IFCHR, 656 INST2SCSI(instance_no), 657 DDI_NT_SCSI_ATTACHMENT_POINT, 0) == 658 DDI_FAILURE) { 659 con_log(CL_ANN, (CE_WARN, 660 "mr_sas: failed to create scsi node.")); 661 662 goto fail_attach; 663 } 664 665 create_scsi_node_f = 1; 666 667 (void) sprintf(instance->iocnode, "%d:lsirdctl", 668 instance_no); 669 670 /* 671 * Create a node for applications 672 * for issuing ioctl to the driver. 673 */ 674 if (ddi_create_minor_node(dip, instance->iocnode, 675 S_IFCHR, INST2LSIRDCTL(instance_no), 676 DDI_PSEUDO, 0) == DDI_FAILURE) { 677 con_log(CL_ANN, (CE_WARN, 678 "mr_sas: failed to create ioctl node.")); 679 680 goto fail_attach; 681 } 682 683 create_ioc_node_f = 1; 684 685 /* Create a taskq to handle dr events */ 686 if ((instance->taskq = ddi_taskq_create(dip, 687 "mrsas_dr_taskq", 1, 688 TASKQ_DEFAULTPRI, 0)) == NULL) { 689 con_log(CL_ANN, (CE_WARN, 690 "mr_sas: failed to create taskq ")); 691 instance->taskq = NULL; 692 goto fail_attach; 693 } 694 695 /* enable interrupt */ 696 instance->func_ptr->enable_intr(instance); 697 698 /* initiate AEN */ 699 if (start_mfi_aen(instance)) { 700 con_log(CL_ANN, (CE_WARN, 701 "mr_sas: failed to initiate AEN.")); 702 goto fail_initiate_aen; 703 } 704 705 con_log(CL_DLEVEL1, (CE_NOTE, 706 "AEN started for instance %d.", instance_no)); 707 708 /* Finally! We are on the air. */ 709 ddi_report_dev(dip); 710 711 if (mrsas_check_acc_handle(instance->regmap_handle) != 712 DDI_SUCCESS) { 713 goto fail_attach; 714 } 715 if (mrsas_check_acc_handle(instance->pci_handle) != 716 DDI_SUCCESS) { 717 goto fail_attach; 718 } 719 instance->mr_ld_list = 720 kmem_zalloc(MRDRV_MAX_LD * sizeof (struct mrsas_ld), 721 KM_SLEEP); 722 break; 723 case DDI_PM_RESUME: 724 con_log(CL_ANN, (CE_NOTE, 725 "mr_sas: DDI_PM_RESUME")); 726 break; 727 case DDI_RESUME: 728 con_log(CL_ANN, (CE_NOTE, 729 "mr_sas: DDI_RESUME")); 730 break; 731 default: 732 con_log(CL_ANN, (CE_WARN, 733 "mr_sas: invalid attach cmd=%x", cmd)); 734 return (DDI_FAILURE); 735 } 736 737 return (DDI_SUCCESS); 738 739 fail_initiate_aen: 740 fail_attach: 741 if (create_devctl_node_f) { 742 ddi_remove_minor_node(dip, "devctl"); 743 } 744 745 if (create_scsi_node_f) { 746 ddi_remove_minor_node(dip, "scsi"); 747 } 748 749 if (create_ioc_node_f) { 750 ddi_remove_minor_node(dip, instance->iocnode); 751 } 752 753 if (tran_alloc_f) { 754 scsi_hba_tran_free(tran); 755 } 756 757 758 if (added_soft_isr_f) { 759 ddi_remove_softintr(instance->soft_intr_id); 760 } 761 762 if (added_isr_f) { 763 mrsas_rem_intrs(instance); 764 } 765 766 if (instance && instance->taskq) { 767 ddi_taskq_destroy(instance->taskq); 768 } 769 770 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 771 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 772 773 mrsas_fm_fini(instance); 774 775 pci_config_teardown(&instance->pci_handle); 776 777 ddi_soft_state_free(mrsas_state, instance_no); 778 779 con_log(CL_ANN, (CE_NOTE, 780 "mr_sas: return failure from mrsas_attach")); 781 782 return (DDI_FAILURE); 783 } 784 785 /*ARGSUSED*/ 786 static int 787 mrsas_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **resultp) 788 { 789 int rval; 790 int mrsas_minor = getminor((dev_t)arg); 791 792 struct mrsas_instance *instance; 793 794 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 795 796 switch (cmd) { 797 case DDI_INFO_DEVT2DEVINFO: 798 instance = (struct mrsas_instance *) 799 ddi_get_soft_state(mrsas_state, 800 MINOR2INST(mrsas_minor)); 801 802 if (instance == NULL) { 803 *resultp = NULL; 804 rval = DDI_FAILURE; 805 } else { 806 *resultp = instance->dip; 807 rval = DDI_SUCCESS; 808 } 809 break; 810 case DDI_INFO_DEVT2INSTANCE: 811 *resultp = (void *)(intptr_t) 812 (MINOR2INST(getminor((dev_t)arg))); 813 rval = DDI_SUCCESS; 814 break; 815 default: 816 *resultp = NULL; 817 rval = DDI_FAILURE; 818 } 819 820 return (rval); 821 } 822 823 static int 824 mrsas_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 825 { 826 int instance_no; 827 828 struct mrsas_instance *instance; 829 830 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 831 832 /* CONSTCOND */ 833 ASSERT(NO_COMPETING_THREADS); 834 835 instance_no = ddi_get_instance(dip); 836 837 instance = (struct mrsas_instance *)ddi_get_soft_state(mrsas_state, 838 instance_no); 839 840 if (!instance) { 841 con_log(CL_ANN, (CE_WARN, 842 "mr_sas:%d could not get instance in detach", 843 instance_no)); 844 845 return (DDI_FAILURE); 846 } 847 848 con_log(CL_ANN, (CE_NOTE, 849 "mr_sas%d: detaching device 0x%4x:0x%4x:0x%4x:0x%4x", 850 instance_no, instance->vendor_id, instance->device_id, 851 instance->subsysvid, instance->subsysid)); 852 853 switch (cmd) { 854 case DDI_DETACH: 855 con_log(CL_ANN, (CE_NOTE, 856 "mrsas_detach: DDI_DETACH")); 857 858 if (scsi_hba_detach(dip) != DDI_SUCCESS) { 859 con_log(CL_ANN, (CE_WARN, 860 "mr_sas:%d failed to detach", 861 instance_no)); 862 863 return (DDI_FAILURE); 864 } 865 866 scsi_hba_tran_free(instance->tran); 867 868 flush_cache(instance); 869 870 if (abort_aen_cmd(instance, instance->aen_cmd)) { 871 con_log(CL_ANN, (CE_WARN, "mrsas_detach: " 872 "failed to abort prevous AEN command")); 873 874 return (DDI_FAILURE); 875 } 876 877 instance->func_ptr->disable_intr(instance); 878 879 if (instance->isr_level == HIGH_LEVEL_INTR) { 880 ddi_remove_softintr(instance->soft_intr_id); 881 } 882 883 mrsas_rem_intrs(instance); 884 885 if (instance->taskq) { 886 ddi_taskq_destroy(instance->taskq); 887 } 888 kmem_free(instance->mr_ld_list, MRDRV_MAX_LD 889 * sizeof (struct mrsas_ld)); 890 free_space_for_mfi(instance); 891 892 mrsas_fm_fini(instance); 893 894 pci_config_teardown(&instance->pci_handle); 895 896 kmem_free(instance->func_ptr, 897 sizeof (struct mrsas_func_ptr)); 898 899 if (instance->timeout_id != (timeout_id_t)-1) { 900 (void) untimeout(instance->timeout_id); 901 instance->timeout_id = (timeout_id_t)-1; 902 } 903 ddi_soft_state_free(mrsas_state, instance_no); 904 break; 905 case DDI_PM_SUSPEND: 906 con_log(CL_ANN, (CE_NOTE, 907 "mrsas_detach: DDI_PM_SUSPEND")); 908 909 break; 910 case DDI_SUSPEND: 911 con_log(CL_ANN, (CE_NOTE, 912 "mrsas_detach: DDI_SUSPEND")); 913 914 break; 915 default: 916 con_log(CL_ANN, (CE_WARN, 917 "invalid detach command:0x%x", cmd)); 918 return (DDI_FAILURE); 919 } 920 921 return (DDI_SUCCESS); 922 } 923 924 /* 925 * ************************************************************************** * 926 * * 927 * common entry points - for character driver types * 928 * * 929 * ************************************************************************** * 930 */ 931 static int 932 mrsas_open(dev_t *dev, int openflags, int otyp, cred_t *credp) 933 { 934 int rval = 0; 935 936 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 937 938 /* Check root permissions */ 939 if (drv_priv(credp) != 0) { 940 con_log(CL_ANN, (CE_WARN, 941 "mr_sas: Non-root ioctl access denied!")); 942 return (EPERM); 943 } 944 945 /* Verify we are being opened as a character device */ 946 if (otyp != OTYP_CHR) { 947 con_log(CL_ANN, (CE_WARN, 948 "mr_sas: ioctl node must be a char node")); 949 return (EINVAL); 950 } 951 952 if (ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(*dev))) 953 == NULL) { 954 return (ENXIO); 955 } 956 957 if (scsi_hba_open) { 958 rval = scsi_hba_open(dev, openflags, otyp, credp); 959 } 960 961 return (rval); 962 } 963 964 static int 965 mrsas_close(dev_t dev, int openflags, int otyp, cred_t *credp) 966 { 967 int rval = 0; 968 969 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 970 971 /* no need for locks! */ 972 973 if (scsi_hba_close) { 974 rval = scsi_hba_close(dev, openflags, otyp, credp); 975 } 976 977 return (rval); 978 } 979 980 static int 981 mrsas_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 982 int *rvalp) 983 { 984 int rval = 0; 985 986 struct mrsas_instance *instance; 987 struct mrsas_ioctl *ioctl; 988 struct mrsas_aen aen; 989 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 990 991 instance = ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(dev))); 992 993 if (instance == NULL) { 994 /* invalid minor number */ 995 con_log(CL_ANN, (CE_WARN, "mr_sas: adapter not found.")); 996 return (ENXIO); 997 } 998 999 ioctl = (struct mrsas_ioctl *)kmem_zalloc(sizeof (struct mrsas_ioctl), 1000 KM_SLEEP); 1001 ASSERT(ioctl); 1002 1003 switch ((uint_t)cmd) { 1004 case MRSAS_IOCTL_FIRMWARE: 1005 if (ddi_copyin((void *)arg, ioctl, 1006 sizeof (struct mrsas_ioctl), mode)) { 1007 con_log(CL_ANN, (CE_WARN, "mrsas_ioctl: " 1008 "ERROR IOCTL copyin")); 1009 kmem_free(ioctl, sizeof (struct mrsas_ioctl)); 1010 return (EFAULT); 1011 } 1012 1013 if (ioctl->control_code == MRSAS_DRIVER_IOCTL_COMMON) { 1014 rval = handle_drv_ioctl(instance, ioctl, mode); 1015 } else { 1016 rval = handle_mfi_ioctl(instance, ioctl, mode); 1017 } 1018 1019 if (ddi_copyout((void *)ioctl, (void *)arg, 1020 (sizeof (struct mrsas_ioctl) - 1), mode)) { 1021 con_log(CL_ANN, (CE_WARN, 1022 "mrsas_ioctl: copy_to_user failed")); 1023 rval = 1; 1024 } 1025 1026 break; 1027 case MRSAS_IOCTL_AEN: 1028 if (ddi_copyin((void *) arg, &aen, 1029 sizeof (struct mrsas_aen), mode)) { 1030 con_log(CL_ANN, (CE_WARN, 1031 "mrsas_ioctl: ERROR AEN copyin")); 1032 kmem_free(ioctl, sizeof (struct mrsas_ioctl)); 1033 return (EFAULT); 1034 } 1035 1036 rval = handle_mfi_aen(instance, &aen); 1037 1038 if (ddi_copyout((void *) &aen, (void *)arg, 1039 sizeof (struct mrsas_aen), mode)) { 1040 con_log(CL_ANN, (CE_WARN, 1041 "mrsas_ioctl: copy_to_user failed")); 1042 rval = 1; 1043 } 1044 1045 break; 1046 default: 1047 rval = scsi_hba_ioctl(dev, cmd, arg, 1048 mode, credp, rvalp); 1049 1050 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_ioctl: " 1051 "scsi_hba_ioctl called, ret = %x.", rval)); 1052 } 1053 1054 kmem_free(ioctl, sizeof (struct mrsas_ioctl)); 1055 return (rval); 1056 } 1057 1058 /* 1059 * ************************************************************************** * 1060 * * 1061 * common entry points - for block driver types * 1062 * * 1063 * ************************************************************************** * 1064 */ 1065 /*ARGSUSED*/ 1066 static int 1067 mrsas_reset(dev_info_t *dip, ddi_reset_cmd_t cmd) 1068 { 1069 int instance_no; 1070 1071 struct mrsas_instance *instance; 1072 1073 instance_no = ddi_get_instance(dip); 1074 instance = (struct mrsas_instance *)ddi_get_soft_state 1075 (mrsas_state, instance_no); 1076 1077 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1078 1079 if (!instance) { 1080 con_log(CL_ANN, (CE_WARN, "mr_sas:%d could not get adapter " 1081 "in reset", instance_no)); 1082 return (DDI_FAILURE); 1083 } 1084 1085 instance->func_ptr->disable_intr(instance); 1086 1087 con_log(CL_ANN1, (CE_NOTE, "flushing cache for instance %d", 1088 instance_no)); 1089 1090 flush_cache(instance); 1091 1092 return (DDI_SUCCESS); 1093 } 1094 1095 1096 /* 1097 * ************************************************************************** * 1098 * * 1099 * entry points (SCSI HBA) * 1100 * * 1101 * ************************************************************************** * 1102 */ 1103 /*ARGSUSED*/ 1104 static int 1105 mrsas_tran_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 1106 scsi_hba_tran_t *tran, struct scsi_device *sd) 1107 { 1108 struct mrsas_instance *instance; 1109 uint16_t tgt = sd->sd_address.a_target; 1110 uint8_t lun = sd->sd_address.a_lun; 1111 1112 con_log(CL_ANN1, (CE_NOTE, "mrsas_tgt_init target %d lun %d", 1113 tgt, lun)); 1114 1115 instance = ADDR2MR(&sd->sd_address); 1116 1117 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 1118 (void) ndi_merge_node(tgt_dip, mrsas_name_node); 1119 ddi_set_name_addr(tgt_dip, NULL); 1120 1121 con_log(CL_ANN1, (CE_NOTE, "mrsas_tgt_init in " 1122 "ndi_dev_is_persistent_node DDI_FAILURE t = %d l = %d", 1123 tgt, lun)); 1124 return (DDI_FAILURE); 1125 } 1126 1127 con_log(CL_ANN1, (CE_NOTE, "mrsas_tgt_init dev_dip %p tgt_dip %p", 1128 (void *)instance->mr_ld_list[tgt].dip, (void *)tgt_dip)); 1129 1130 if (tgt < MRDRV_MAX_LD && lun == 0) { 1131 if (instance->mr_ld_list[tgt].dip == NULL && 1132 strcmp(ddi_driver_name(sd->sd_dev), "sd") == 0) { 1133 instance->mr_ld_list[tgt].dip = tgt_dip; 1134 instance->mr_ld_list[tgt].lun_type = MRSAS_LD_LUN; 1135 } 1136 } 1137 return (DDI_SUCCESS); 1138 } 1139 1140 /*ARGSUSED*/ 1141 static void 1142 mrsas_tran_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 1143 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 1144 { 1145 struct mrsas_instance *instance; 1146 int tgt = sd->sd_address.a_target; 1147 int lun = sd->sd_address.a_lun; 1148 1149 instance = ADDR2MR(&sd->sd_address); 1150 1151 con_log(CL_ANN1, (CE_NOTE, "tgt_free t = %d l = %d", tgt, lun)); 1152 1153 if (tgt < MRDRV_MAX_LD && lun == 0) { 1154 if (instance->mr_ld_list[tgt].dip == tgt_dip) { 1155 instance->mr_ld_list[tgt].dip = NULL; 1156 } 1157 } 1158 } 1159 1160 static dev_info_t * 1161 mrsas_find_child(struct mrsas_instance *instance, uint16_t tgt, uint8_t lun) 1162 { 1163 dev_info_t *child = NULL; 1164 char addr[SCSI_MAXNAMELEN]; 1165 char tmp[MAXNAMELEN]; 1166 1167 (void) sprintf(addr, "%x,%x", tgt, lun); 1168 for (child = ddi_get_child(instance->dip); child; 1169 child = ddi_get_next_sibling(child)) { 1170 1171 if (mrsas_name_node(child, tmp, MAXNAMELEN) != 1172 DDI_SUCCESS) { 1173 continue; 1174 } 1175 1176 if (strcmp(addr, tmp) == 0) { 1177 break; 1178 } 1179 } 1180 con_log(CL_ANN1, (CE_NOTE, "mrsas_find_child: return child = %p", 1181 (void *)child)); 1182 return (child); 1183 } 1184 1185 static int 1186 mrsas_name_node(dev_info_t *dip, char *name, int len) 1187 { 1188 int tgt, lun; 1189 1190 tgt = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1191 DDI_PROP_DONTPASS, "target", -1); 1192 con_log(CL_ANN1, (CE_NOTE, 1193 "mrsas_name_node: dip %p tgt %d", (void *)dip, tgt)); 1194 if (tgt == -1) { 1195 return (DDI_FAILURE); 1196 } 1197 lun = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1198 "lun", -1); 1199 con_log(CL_ANN1, 1200 (CE_NOTE, "mrsas_name_node: tgt %d lun %d", tgt, lun)); 1201 if (lun == -1) { 1202 return (DDI_FAILURE); 1203 } 1204 (void) snprintf(name, len, "%x,%x", tgt, lun); 1205 return (DDI_SUCCESS); 1206 } 1207 1208 static struct scsi_pkt * 1209 mrsas_tran_init_pkt(struct scsi_address *ap, register struct scsi_pkt *pkt, 1210 struct buf *bp, int cmdlen, int statuslen, int tgtlen, 1211 int flags, int (*callback)(), caddr_t arg) 1212 { 1213 struct scsa_cmd *acmd; 1214 struct mrsas_instance *instance; 1215 struct scsi_pkt *new_pkt; 1216 1217 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1218 1219 instance = ADDR2MR(ap); 1220 1221 /* step #1 : pkt allocation */ 1222 if (pkt == NULL) { 1223 pkt = scsi_hba_pkt_alloc(instance->dip, ap, cmdlen, statuslen, 1224 tgtlen, sizeof (struct scsa_cmd), callback, arg); 1225 if (pkt == NULL) { 1226 return (NULL); 1227 } 1228 1229 acmd = PKT2CMD(pkt); 1230 1231 /* 1232 * Initialize the new pkt - we redundantly initialize 1233 * all the fields for illustrative purposes. 1234 */ 1235 acmd->cmd_pkt = pkt; 1236 acmd->cmd_flags = 0; 1237 acmd->cmd_scblen = statuslen; 1238 acmd->cmd_cdblen = cmdlen; 1239 acmd->cmd_dmahandle = NULL; 1240 acmd->cmd_ncookies = 0; 1241 acmd->cmd_cookie = 0; 1242 acmd->cmd_cookiecnt = 0; 1243 acmd->cmd_nwin = 0; 1244 1245 pkt->pkt_address = *ap; 1246 pkt->pkt_comp = (void (*)())NULL; 1247 pkt->pkt_flags = 0; 1248 pkt->pkt_time = 0; 1249 pkt->pkt_resid = 0; 1250 pkt->pkt_state = 0; 1251 pkt->pkt_statistics = 0; 1252 pkt->pkt_reason = 0; 1253 new_pkt = pkt; 1254 } else { 1255 acmd = PKT2CMD(pkt); 1256 new_pkt = NULL; 1257 } 1258 1259 /* step #2 : dma allocation/move */ 1260 if (bp && bp->b_bcount != 0) { 1261 if (acmd->cmd_dmahandle == NULL) { 1262 if (mrsas_dma_alloc(instance, pkt, bp, flags, 1263 callback) == DDI_FAILURE) { 1264 if (new_pkt) { 1265 scsi_hba_pkt_free(ap, new_pkt); 1266 } 1267 return ((struct scsi_pkt *)NULL); 1268 } 1269 } else { 1270 if (mrsas_dma_move(instance, pkt, bp) == DDI_FAILURE) { 1271 return ((struct scsi_pkt *)NULL); 1272 } 1273 } 1274 } 1275 1276 return (pkt); 1277 } 1278 1279 static int 1280 mrsas_tran_start(struct scsi_address *ap, register struct scsi_pkt *pkt) 1281 { 1282 uchar_t cmd_done = 0; 1283 1284 struct mrsas_instance *instance = ADDR2MR(ap); 1285 struct mrsas_cmd *cmd; 1286 1287 if (instance->deadadapter == 1) { 1288 con_log(CL_ANN1, (CE_WARN, 1289 "mrsas_tran_start: return TRAN_FATAL_ERROR " 1290 "for IO, as the HBA doesnt take any more IOs")); 1291 if (pkt) { 1292 pkt->pkt_reason = CMD_DEV_GONE; 1293 pkt->pkt_statistics = STAT_DISCON; 1294 } 1295 return (TRAN_FATAL_ERROR); 1296 } 1297 1298 if (instance->adapterresetinprogress) { 1299 con_log(CL_ANN1, (CE_NOTE, "Reset flag set, " 1300 "returning mfi_pkt and setting TRAN_BUSY\n")); 1301 return (TRAN_BUSY); 1302 } 1303 1304 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d:SCSI CDB[0]=0x%x time:%x", 1305 __func__, __LINE__, pkt->pkt_cdbp[0], pkt->pkt_time)); 1306 1307 pkt->pkt_reason = CMD_CMPLT; 1308 *pkt->pkt_scbp = STATUS_GOOD; /* clear arq scsi_status */ 1309 1310 cmd = build_cmd(instance, ap, pkt, &cmd_done); 1311 1312 /* 1313 * Check if the command is already completed by the mrsas_build_cmd() 1314 * routine. In which case the busy_flag would be clear and scb will be 1315 * NULL and appropriate reason provided in pkt_reason field 1316 */ 1317 if (cmd_done) { 1318 pkt->pkt_reason = CMD_CMPLT; 1319 pkt->pkt_scbp[0] = STATUS_GOOD; 1320 pkt->pkt_state |= STATE_GOT_BUS | STATE_GOT_TARGET 1321 | STATE_SENT_CMD; 1322 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && pkt->pkt_comp) { 1323 (*pkt->pkt_comp)(pkt); 1324 } 1325 1326 return (TRAN_ACCEPT); 1327 } 1328 1329 if (cmd == NULL) { 1330 return (TRAN_BUSY); 1331 } 1332 1333 if ((pkt->pkt_flags & FLAG_NOINTR) == 0) { 1334 if (instance->fw_outstanding > instance->max_fw_cmds) { 1335 con_log(CL_ANN, (CE_CONT, "mr_sas:Firmware busy")); 1336 DTRACE_PROBE2(start_tran_err, 1337 uint16_t, instance->fw_outstanding, 1338 uint16_t, instance->max_fw_cmds); 1339 return_mfi_pkt(instance, cmd); 1340 return (TRAN_BUSY); 1341 } 1342 1343 /* Synchronize the Cmd frame for the controller */ 1344 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0, 1345 DDI_DMA_SYNC_FORDEV); 1346 con_log(CL_ANN1, (CE_NOTE, "Push SCSI CDB[0]=0x%x" 1347 "cmd->index:%x\n", pkt->pkt_cdbp[0], cmd->index)); 1348 instance->func_ptr->issue_cmd(cmd, instance); 1349 1350 } else { 1351 struct mrsas_header *hdr = &cmd->frame->hdr; 1352 1353 cmd->sync_cmd = MRSAS_TRUE; 1354 1355 instance->func_ptr-> issue_cmd_in_poll_mode(instance, cmd); 1356 1357 pkt->pkt_reason = CMD_CMPLT; 1358 pkt->pkt_statistics = 0; 1359 pkt->pkt_state |= STATE_XFERRED_DATA | STATE_GOT_STATUS; 1360 1361 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, 1362 &hdr->cmd_status)) { 1363 case MFI_STAT_OK: 1364 pkt->pkt_scbp[0] = STATUS_GOOD; 1365 break; 1366 1367 case MFI_STAT_SCSI_DONE_WITH_ERROR: 1368 1369 pkt->pkt_reason = CMD_CMPLT; 1370 pkt->pkt_statistics = 0; 1371 1372 ((struct scsi_status *)pkt->pkt_scbp)->sts_chk = 1; 1373 break; 1374 1375 case MFI_STAT_DEVICE_NOT_FOUND: 1376 pkt->pkt_reason = CMD_DEV_GONE; 1377 pkt->pkt_statistics = STAT_DISCON; 1378 break; 1379 1380 default: 1381 ((struct scsi_status *)pkt->pkt_scbp)->sts_busy = 1; 1382 } 1383 1384 (void) mrsas_common_check(instance, cmd); 1385 DTRACE_PROBE2(start_nointr_done, uint8_t, hdr->cmd, 1386 uint8_t, hdr->cmd_status); 1387 return_mfi_pkt(instance, cmd); 1388 1389 if (pkt->pkt_comp) { 1390 (*pkt->pkt_comp)(pkt); 1391 } 1392 1393 } 1394 1395 return (TRAN_ACCEPT); 1396 } 1397 1398 /*ARGSUSED*/ 1399 static int 1400 mrsas_tran_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 1401 { 1402 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1403 1404 /* abort command not supported by H/W */ 1405 1406 return (DDI_FAILURE); 1407 } 1408 1409 /*ARGSUSED*/ 1410 static int 1411 mrsas_tran_reset(struct scsi_address *ap, int level) 1412 { 1413 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1414 1415 /* reset command not supported by H/W */ 1416 1417 return (DDI_FAILURE); 1418 1419 } 1420 1421 /*ARGSUSED*/ 1422 static int 1423 mrsas_tran_getcap(struct scsi_address *ap, char *cap, int whom) 1424 { 1425 int rval = 0; 1426 1427 struct mrsas_instance *instance = ADDR2MR(ap); 1428 1429 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1430 1431 /* we do allow inquiring about capabilities for other targets */ 1432 if (cap == NULL) { 1433 return (-1); 1434 } 1435 1436 switch (scsi_hba_lookup_capstr(cap)) { 1437 case SCSI_CAP_DMA_MAX: 1438 /* Limit to 16MB max transfer */ 1439 rval = mrsas_max_cap_maxxfer; 1440 break; 1441 case SCSI_CAP_MSG_OUT: 1442 rval = 1; 1443 break; 1444 case SCSI_CAP_DISCONNECT: 1445 rval = 0; 1446 break; 1447 case SCSI_CAP_SYNCHRONOUS: 1448 rval = 0; 1449 break; 1450 case SCSI_CAP_WIDE_XFER: 1451 rval = 1; 1452 break; 1453 case SCSI_CAP_TAGGED_QING: 1454 rval = 1; 1455 break; 1456 case SCSI_CAP_UNTAGGED_QING: 1457 rval = 1; 1458 break; 1459 case SCSI_CAP_PARITY: 1460 rval = 1; 1461 break; 1462 case SCSI_CAP_INITIATOR_ID: 1463 rval = instance->init_id; 1464 break; 1465 case SCSI_CAP_ARQ: 1466 rval = 1; 1467 break; 1468 case SCSI_CAP_LINKED_CMDS: 1469 rval = 0; 1470 break; 1471 case SCSI_CAP_RESET_NOTIFICATION: 1472 rval = 1; 1473 break; 1474 case SCSI_CAP_GEOMETRY: 1475 rval = -1; 1476 1477 break; 1478 default: 1479 con_log(CL_DLEVEL2, (CE_NOTE, "Default cap coming 0x%x", 1480 scsi_hba_lookup_capstr(cap))); 1481 rval = -1; 1482 break; 1483 } 1484 1485 return (rval); 1486 } 1487 1488 /*ARGSUSED*/ 1489 static int 1490 mrsas_tran_setcap(struct scsi_address *ap, char *cap, int value, int whom) 1491 { 1492 int rval = 1; 1493 1494 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1495 1496 /* We don't allow setting capabilities for other targets */ 1497 if (cap == NULL || whom == 0) { 1498 return (-1); 1499 } 1500 1501 switch (scsi_hba_lookup_capstr(cap)) { 1502 case SCSI_CAP_DMA_MAX: 1503 case SCSI_CAP_MSG_OUT: 1504 case SCSI_CAP_PARITY: 1505 case SCSI_CAP_LINKED_CMDS: 1506 case SCSI_CAP_RESET_NOTIFICATION: 1507 case SCSI_CAP_DISCONNECT: 1508 case SCSI_CAP_SYNCHRONOUS: 1509 case SCSI_CAP_UNTAGGED_QING: 1510 case SCSI_CAP_WIDE_XFER: 1511 case SCSI_CAP_INITIATOR_ID: 1512 case SCSI_CAP_ARQ: 1513 /* 1514 * None of these are settable via 1515 * the capability interface. 1516 */ 1517 break; 1518 case SCSI_CAP_TAGGED_QING: 1519 rval = 1; 1520 break; 1521 case SCSI_CAP_SECTOR_SIZE: 1522 rval = 1; 1523 break; 1524 1525 case SCSI_CAP_TOTAL_SECTORS: 1526 rval = 1; 1527 break; 1528 default: 1529 rval = -1; 1530 break; 1531 } 1532 1533 return (rval); 1534 } 1535 1536 static void 1537 mrsas_tran_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 1538 { 1539 struct scsa_cmd *acmd = PKT2CMD(pkt); 1540 1541 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1542 1543 if (acmd->cmd_flags & CFLAG_DMAVALID) { 1544 acmd->cmd_flags &= ~CFLAG_DMAVALID; 1545 1546 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle); 1547 1548 ddi_dma_free_handle(&acmd->cmd_dmahandle); 1549 1550 acmd->cmd_dmahandle = NULL; 1551 } 1552 1553 /* free the pkt */ 1554 scsi_hba_pkt_free(ap, pkt); 1555 } 1556 1557 /*ARGSUSED*/ 1558 static void 1559 mrsas_tran_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 1560 { 1561 register struct scsa_cmd *acmd = PKT2CMD(pkt); 1562 1563 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1564 1565 if (acmd->cmd_flags & CFLAG_DMAVALID) { 1566 acmd->cmd_flags &= ~CFLAG_DMAVALID; 1567 1568 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle); 1569 1570 ddi_dma_free_handle(&acmd->cmd_dmahandle); 1571 1572 acmd->cmd_dmahandle = NULL; 1573 } 1574 } 1575 1576 /*ARGSUSED*/ 1577 static void 1578 mrsas_tran_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 1579 { 1580 register struct scsa_cmd *acmd = PKT2CMD(pkt); 1581 1582 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1583 1584 if (acmd->cmd_flags & CFLAG_DMAVALID) { 1585 (void) ddi_dma_sync(acmd->cmd_dmahandle, acmd->cmd_dma_offset, 1586 acmd->cmd_dma_len, (acmd->cmd_flags & CFLAG_DMASEND) ? 1587 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 1588 } 1589 } 1590 1591 /* 1592 * mrsas_isr(caddr_t) 1593 * 1594 * The Interrupt Service Routine 1595 * 1596 * Collect status for all completed commands and do callback 1597 * 1598 */ 1599 static uint_t 1600 mrsas_isr(struct mrsas_instance *instance) 1601 { 1602 int need_softintr; 1603 uint32_t producer; 1604 uint32_t consumer; 1605 uint32_t context; 1606 1607 struct mrsas_cmd *cmd; 1608 struct mrsas_header *hdr; 1609 struct scsi_pkt *pkt; 1610 1611 ASSERT(instance); 1612 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) && 1613 !instance->func_ptr->intr_ack(instance)) { 1614 return (DDI_INTR_UNCLAIMED); 1615 } 1616 1617 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle, 1618 0, 0, DDI_DMA_SYNC_FORCPU); 1619 1620 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle) 1621 != DDI_SUCCESS) { 1622 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 1623 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 1624 con_log(CL_ANN1, (CE_WARN, 1625 "mr_sas_isr(): FMA check, returning DDI_INTR_UNCLAIMED")); 1626 return (DDI_INTR_CLAIMED); 1627 } 1628 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1629 1630 producer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle, 1631 instance->producer); 1632 consumer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle, 1633 instance->consumer); 1634 1635 con_log(CL_ANN1, (CE_NOTE, " producer %x consumer %x ", 1636 producer, consumer)); 1637 if (producer == consumer) { 1638 con_log(CL_ANN1, (CE_WARN, "producer = consumer case")); 1639 DTRACE_PROBE2(isr_pc_err, uint32_t, producer, 1640 uint32_t, consumer); 1641 return (DDI_INTR_CLAIMED); 1642 } 1643 1644 #ifdef OCRDEBUG 1645 if (debug_consecutive_timeout_after_ocr_g == 1) { 1646 con_log(CL_ANN1, (CE_NOTE, 1647 "simulating consecutive timeout after ocr")); 1648 return (DDI_INTR_CLAIMED); 1649 } 1650 #endif 1651 1652 if (mrsas_initiate_ocr_if_fw_is_faulty(instance) == 1) { 1653 con_log(CL_ANN1, (CE_NOTE, "Fw Fault State Detected ")); 1654 if (instance->timeout_id == (timeout_id_t)-1) { 1655 con_log(CL_ANN1, (CE_NOTE, 1656 "Trigger timeout in NON IO Case")); 1657 instance->timeout_id = 1658 timeout(io_timeout_checker, (void *)instance, 1659 drv_usectohz(MRSAS_1_SECOND)); 1660 } 1661 return (DDI_INTR_CLAIMED); 1662 } 1663 1664 mutex_enter(&instance->completed_pool_mtx); 1665 mutex_enter(&instance->cmd_pend_mtx); 1666 1667 while (consumer != producer) { 1668 context = ddi_get32(instance->mfi_internal_dma_obj.acc_handle, 1669 &instance->reply_queue[consumer]); 1670 cmd = instance->cmd_list[context]; 1671 1672 if (cmd->sync_cmd == MRSAS_TRUE) { 1673 hdr = (struct mrsas_header *)&cmd->frame->hdr; 1674 if (hdr) { 1675 mlist_del_init(&cmd->list); 1676 } 1677 } else { 1678 pkt = cmd->pkt; 1679 if (pkt) { 1680 mlist_del_init(&cmd->list); 1681 } 1682 } 1683 1684 mlist_add_tail(&cmd->list, &instance->completed_pool_list); 1685 1686 consumer++; 1687 if (consumer == (instance->max_fw_cmds + 1)) { 1688 consumer = 0; 1689 } 1690 } 1691 mutex_exit(&instance->cmd_pend_mtx); 1692 mutex_exit(&instance->completed_pool_mtx); 1693 1694 ddi_put32(instance->mfi_internal_dma_obj.acc_handle, 1695 instance->consumer, consumer); 1696 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle, 1697 0, 0, DDI_DMA_SYNC_FORDEV); 1698 1699 if (instance->softint_running) { 1700 need_softintr = 0; 1701 } else { 1702 need_softintr = 1; 1703 } 1704 1705 if (instance->isr_level == HIGH_LEVEL_INTR) { 1706 if (need_softintr) { 1707 ddi_trigger_softintr(instance->soft_intr_id); 1708 } 1709 } else { 1710 /* 1711 * Not a high-level interrupt, therefore call the soft level 1712 * interrupt explicitly 1713 */ 1714 (void) mrsas_softintr(instance); 1715 } 1716 1717 return (DDI_INTR_CLAIMED); 1718 } 1719 1720 1721 /* 1722 * ************************************************************************** * 1723 * * 1724 * libraries * 1725 * * 1726 * ************************************************************************** * 1727 */ 1728 /* 1729 * get_mfi_pkt : Get a command from the free pool 1730 * After successful allocation, the caller of this routine 1731 * must clear the frame buffer (memset to zero) before 1732 * using the packet further. 1733 * 1734 * ***** Note ***** 1735 * After clearing the frame buffer the context id of the 1736 * frame buffer SHOULD be restored back. 1737 */ 1738 static struct mrsas_cmd * 1739 get_mfi_pkt(struct mrsas_instance *instance) 1740 { 1741 mlist_t *head = &instance->cmd_pool_list; 1742 struct mrsas_cmd *cmd = NULL; 1743 1744 mutex_enter(&instance->cmd_pool_mtx); 1745 ASSERT(mutex_owned(&instance->cmd_pool_mtx)); 1746 1747 if (!mlist_empty(head)) { 1748 cmd = mlist_entry(head->next, struct mrsas_cmd, list); 1749 mlist_del_init(head->next); 1750 } 1751 if (cmd != NULL) { 1752 cmd->pkt = NULL; 1753 cmd->retry_count_for_ocr = 0; 1754 cmd->drv_pkt_time = 0; 1755 } 1756 mutex_exit(&instance->cmd_pool_mtx); 1757 1758 return (cmd); 1759 } 1760 1761 static struct mrsas_cmd * 1762 get_mfi_app_pkt(struct mrsas_instance *instance) 1763 { 1764 mlist_t *head = &instance->app_cmd_pool_list; 1765 struct mrsas_cmd *cmd = NULL; 1766 1767 mutex_enter(&instance->app_cmd_pool_mtx); 1768 ASSERT(mutex_owned(&instance->app_cmd_pool_mtx)); 1769 1770 if (!mlist_empty(head)) { 1771 cmd = mlist_entry(head->next, struct mrsas_cmd, list); 1772 mlist_del_init(head->next); 1773 } 1774 if (cmd != NULL) 1775 cmd->pkt = NULL; 1776 mutex_exit(&instance->app_cmd_pool_mtx); 1777 1778 return (cmd); 1779 } 1780 /* 1781 * return_mfi_pkt : Return a cmd to free command pool 1782 */ 1783 static void 1784 return_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 1785 { 1786 mutex_enter(&instance->cmd_pool_mtx); 1787 ASSERT(mutex_owned(&instance->cmd_pool_mtx)); 1788 1789 mlist_add(&cmd->list, &instance->cmd_pool_list); 1790 1791 mutex_exit(&instance->cmd_pool_mtx); 1792 } 1793 1794 static void 1795 return_mfi_app_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 1796 { 1797 mutex_enter(&instance->app_cmd_pool_mtx); 1798 ASSERT(mutex_owned(&instance->app_cmd_pool_mtx)); 1799 1800 mlist_add(&cmd->list, &instance->app_cmd_pool_list); 1801 1802 mutex_exit(&instance->app_cmd_pool_mtx); 1803 } 1804 static void 1805 push_pending_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 1806 { 1807 struct scsi_pkt *pkt; 1808 struct mrsas_header *hdr; 1809 con_log(CL_ANN1, (CE_NOTE, "push_pending_pkt(): Called\n")); 1810 mutex_enter(&instance->cmd_pend_mtx); 1811 ASSERT(mutex_owned(&instance->cmd_pend_mtx)); 1812 mlist_del_init(&cmd->list); 1813 mlist_add_tail(&cmd->list, &instance->cmd_pend_list); 1814 if (cmd->sync_cmd == MRSAS_TRUE) { 1815 hdr = (struct mrsas_header *)&cmd->frame->hdr; 1816 if (hdr) { 1817 con_log(CL_ANN1, (CE_CONT, 1818 "push_pending_mfi_pkt: " 1819 "cmd %p index %x " 1820 "time %llx", 1821 (void *)cmd, cmd->index, 1822 gethrtime())); 1823 /* Wait for specified interval */ 1824 hdr->timeout = (unsigned int)debug_timeout_g; 1825 con_log(CL_ANN1, (CE_CONT, 1826 "push_pending_pkt(): " 1827 "Called IO Timeout Value %x\n", 1828 hdr->timeout)); 1829 } 1830 if (hdr && instance->timeout_id == (timeout_id_t)-1) { 1831 instance->timeout_id = timeout(io_timeout_checker, 1832 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 1833 } 1834 } else { 1835 pkt = cmd->pkt; 1836 if (pkt) { 1837 con_log(CL_ANN1, (CE_CONT, 1838 "push_pending_mfi_pkt: " 1839 "cmd %p index %x pkt %p, " 1840 "time %llx", 1841 (void *)cmd, cmd->index, (void *)pkt, 1842 gethrtime())); 1843 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 1844 } 1845 if (pkt && instance->timeout_id == (timeout_id_t)-1) { 1846 instance->timeout_id = timeout(io_timeout_checker, 1847 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 1848 } 1849 } 1850 1851 mutex_exit(&instance->cmd_pend_mtx); 1852 } 1853 1854 static int 1855 mrsas_print_pending_cmds(struct mrsas_instance *instance) 1856 { 1857 mlist_t *head = &instance->cmd_pend_list; 1858 mlist_t *tmp = head; 1859 struct mrsas_cmd *cmd = NULL; 1860 struct mrsas_header *hdr; 1861 unsigned int flag = 1; 1862 1863 struct scsi_pkt *pkt; 1864 con_log(CL_ANN1, (CE_NOTE, 1865 "mrsas_print_pending_cmds(): Called")); 1866 while (flag) { 1867 mutex_enter(&instance->cmd_pend_mtx); 1868 tmp = tmp->next; 1869 if (tmp == head) { 1870 mutex_exit(&instance->cmd_pend_mtx); 1871 flag = 0; 1872 break; 1873 } else { 1874 cmd = mlist_entry(tmp, struct mrsas_cmd, list); 1875 mutex_exit(&instance->cmd_pend_mtx); 1876 if (cmd) { 1877 if (cmd->sync_cmd == MRSAS_TRUE) { 1878 hdr = (struct mrsas_header *)&cmd->frame->hdr; 1879 if (hdr) { 1880 hdr->timeout = 1881 (unsigned int)debug_timeout_g; 1882 con_log(CL_ANN1, (CE_CONT, 1883 "print: cmd %p index %x hdr %p", 1884 (void *)cmd, cmd->index, 1885 (void *)hdr)); 1886 } 1887 } else { 1888 pkt = cmd->pkt; 1889 if (pkt) { 1890 cmd->drv_pkt_time = 1891 (uint16_t)debug_timeout_g; 1892 con_log(CL_ANN1, (CE_CONT, 1893 "print: cmd %p index %x " 1894 "pkt %p", (void *)cmd, cmd->index, 1895 (void *)pkt)); 1896 } 1897 } 1898 } 1899 } 1900 } 1901 con_log(CL_ANN1, (CE_NOTE, "mrsas_print_pending_cmds(): Done\n")); 1902 return (DDI_SUCCESS); 1903 } 1904 1905 1906 static int 1907 mrsas_complete_pending_cmds(struct mrsas_instance *instance) 1908 { 1909 1910 struct mrsas_cmd *cmd = NULL; 1911 struct scsi_pkt *pkt; 1912 struct mrsas_header *hdr; 1913 1914 struct mlist_head *pos, *next; 1915 1916 con_log(CL_ANN1, (CE_NOTE, 1917 "mrsas_complete_pending_cmds(): Called")); 1918 1919 mutex_enter(&instance->cmd_pend_mtx); 1920 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) { 1921 cmd = mlist_entry(pos, struct mrsas_cmd, list); 1922 if (cmd) { 1923 pkt = cmd->pkt; 1924 if (pkt) { // for IO 1925 if (((pkt->pkt_flags & FLAG_NOINTR) 1926 == 0) && pkt->pkt_comp) { 1927 pkt->pkt_reason 1928 = CMD_DEV_GONE; 1929 pkt->pkt_statistics 1930 = STAT_DISCON; 1931 con_log(CL_ANN1, (CE_NOTE, 1932 "fail and posting to scsa " 1933 "cmd %p index %x" 1934 " pkt %p " 1935 "time : %llx", 1936 (void *)cmd, cmd->index, 1937 (void *)pkt, gethrtime())); 1938 (*pkt->pkt_comp)(pkt); 1939 } 1940 } else { /* for DCMDS */ 1941 if (cmd->sync_cmd == MRSAS_TRUE) { 1942 hdr = (struct mrsas_header *)&cmd->frame->hdr; 1943 con_log(CL_ANN1, (CE_NOTE, 1944 "posting invalid status to application " 1945 "cmd %p index %x" 1946 " hdr %p " 1947 "time : %llx", 1948 (void *)cmd, cmd->index, 1949 (void *)hdr, gethrtime())); 1950 hdr->cmd_status = MFI_STAT_INVALID_STATUS; 1951 complete_cmd_in_sync_mode(instance, cmd); 1952 } 1953 } 1954 mlist_del_init(&cmd->list); 1955 } else { 1956 con_log(CL_ANN1, (CE_NOTE, 1957 "mrsas_complete_pending_cmds:" 1958 "NULL command\n")); 1959 } 1960 con_log(CL_ANN1, (CE_NOTE, 1961 "mrsas_complete_pending_cmds:" 1962 "looping for more commands\n")); 1963 } 1964 mutex_exit(&instance->cmd_pend_mtx); 1965 1966 con_log(CL_ANN1, (CE_NOTE, "mrsas_complete_pending_cmds(): DONE\n")); 1967 return (DDI_SUCCESS); 1968 } 1969 1970 1971 static int 1972 mrsas_issue_pending_cmds(struct mrsas_instance *instance) 1973 { 1974 mlist_t *head = &instance->cmd_pend_list; 1975 mlist_t *tmp = head->next; 1976 struct mrsas_cmd *cmd = NULL; 1977 struct scsi_pkt *pkt; 1978 1979 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_pending_cmds(): Called")); 1980 while (tmp != head) { 1981 mutex_enter(&instance->cmd_pend_mtx); 1982 cmd = mlist_entry(tmp, struct mrsas_cmd, list); 1983 tmp = tmp->next; 1984 mutex_exit(&instance->cmd_pend_mtx); 1985 if (cmd) { 1986 con_log(CL_ANN1, (CE_NOTE, 1987 "mrsas_issue_pending_cmds(): " 1988 "Got a cmd: cmd:%p\n", (void *)cmd)); 1989 cmd->retry_count_for_ocr++; 1990 con_log(CL_ANN1, (CE_NOTE, 1991 "mrsas_issue_pending_cmds(): " 1992 "cmd retry count = %d\n", 1993 cmd->retry_count_for_ocr)); 1994 if (cmd->retry_count_for_ocr > IO_RETRY_COUNT) { 1995 con_log(CL_ANN1, (CE_NOTE, 1996 "mrsas_issue_pending_cmds():" 1997 "Calling Kill Adapter\n")); 1998 (void) mrsas_kill_adapter(instance); 1999 return (DDI_FAILURE); 2000 } 2001 pkt = cmd->pkt; 2002 if (pkt) { 2003 con_log(CL_ANN1, (CE_NOTE, 2004 "PENDING ISSUE: cmd %p index %x " 2005 "pkt %p time %llx", 2006 (void *)cmd, cmd->index, 2007 (void *)pkt, 2008 gethrtime())); 2009 2010 } 2011 if (cmd->sync_cmd == MRSAS_TRUE) { 2012 instance->func_ptr->issue_cmd_in_sync_mode( 2013 instance, cmd); 2014 } else { 2015 instance->func_ptr->issue_cmd(cmd, instance); 2016 } 2017 } else { 2018 con_log(CL_ANN1, (CE_NOTE, 2019 "mrsas_issue_pending_cmds: NULL command\n")); 2020 } 2021 con_log(CL_ANN1, (CE_NOTE, 2022 "mrsas_issue_pending_cmds:" 2023 "looping for more commands")); 2024 } 2025 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_pending_cmds(): DONE\n")); 2026 return (DDI_SUCCESS); 2027 } 2028 2029 /* 2030 * destroy_mfi_frame_pool 2031 */ 2032 static void 2033 destroy_mfi_frame_pool(struct mrsas_instance *instance) 2034 { 2035 int i; 2036 uint32_t max_cmd = instance->max_fw_cmds; 2037 2038 struct mrsas_cmd *cmd; 2039 2040 /* return all frames to pool */ 2041 for (i = 0; i < max_cmd+1; i++) { 2042 2043 cmd = instance->cmd_list[i]; 2044 2045 if (cmd->frame_dma_obj_status == DMA_OBJ_ALLOCATED) 2046 (void) mrsas_free_dma_obj(instance, cmd->frame_dma_obj); 2047 2048 cmd->frame_dma_obj_status = DMA_OBJ_FREED; 2049 } 2050 2051 } 2052 2053 /* 2054 * create_mfi_frame_pool 2055 */ 2056 static int 2057 create_mfi_frame_pool(struct mrsas_instance *instance) 2058 { 2059 int i = 0; 2060 int cookie_cnt; 2061 uint16_t max_cmd; 2062 uint16_t sge_sz; 2063 uint32_t sgl_sz; 2064 uint32_t tot_frame_size; 2065 struct mrsas_cmd *cmd; 2066 2067 max_cmd = instance->max_fw_cmds; 2068 2069 sge_sz = sizeof (struct mrsas_sge_ieee); 2070 2071 /* calculated the number of 64byte frames required for SGL */ 2072 sgl_sz = sge_sz * instance->max_num_sge; 2073 tot_frame_size = sgl_sz + MRMFI_FRAME_SIZE + SENSE_LENGTH; 2074 2075 con_log(CL_DLEVEL3, (CE_NOTE, "create_mfi_frame_pool: " 2076 "sgl_sz %x tot_frame_size %x", sgl_sz, tot_frame_size)); 2077 2078 while (i < max_cmd+1) { 2079 cmd = instance->cmd_list[i]; 2080 2081 cmd->frame_dma_obj.size = tot_frame_size; 2082 cmd->frame_dma_obj.dma_attr = mrsas_generic_dma_attr; 2083 cmd->frame_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 2084 cmd->frame_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 2085 cmd->frame_dma_obj.dma_attr.dma_attr_sgllen = 1; 2086 cmd->frame_dma_obj.dma_attr.dma_attr_align = 64; 2087 2088 2089 cookie_cnt = mrsas_alloc_dma_obj(instance, &cmd->frame_dma_obj, 2090 (uchar_t)DDI_STRUCTURE_LE_ACC); 2091 2092 if (cookie_cnt == -1 || cookie_cnt > 1) { 2093 con_log(CL_ANN, (CE_WARN, 2094 "create_mfi_frame_pool: could not alloc.")); 2095 return (DDI_FAILURE); 2096 } 2097 2098 bzero(cmd->frame_dma_obj.buffer, tot_frame_size); 2099 2100 cmd->frame_dma_obj_status = DMA_OBJ_ALLOCATED; 2101 cmd->frame = (union mrsas_frame *)cmd->frame_dma_obj.buffer; 2102 cmd->frame_phys_addr = 2103 cmd->frame_dma_obj.dma_cookie[0].dmac_address; 2104 2105 cmd->sense = (uint8_t *)(((unsigned long) 2106 cmd->frame_dma_obj.buffer) + 2107 tot_frame_size - SENSE_LENGTH); 2108 cmd->sense_phys_addr = 2109 cmd->frame_dma_obj.dma_cookie[0].dmac_address + 2110 tot_frame_size - SENSE_LENGTH; 2111 2112 if (!cmd->frame || !cmd->sense) { 2113 con_log(CL_ANN, (CE_NOTE, 2114 "mr_sas: pci_pool_alloc failed")); 2115 2116 return (ENOMEM); 2117 } 2118 2119 ddi_put32(cmd->frame_dma_obj.acc_handle, 2120 &cmd->frame->io.context, cmd->index); 2121 i++; 2122 2123 con_log(CL_DLEVEL3, (CE_NOTE, "[%x]-%x", 2124 cmd->index, cmd->frame_phys_addr)); 2125 } 2126 2127 return (DDI_SUCCESS); 2128 } 2129 2130 /* 2131 * free_additional_dma_buffer 2132 */ 2133 static void 2134 free_additional_dma_buffer(struct mrsas_instance *instance) 2135 { 2136 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) { 2137 (void) mrsas_free_dma_obj(instance, 2138 instance->mfi_internal_dma_obj); 2139 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED; 2140 } 2141 2142 if (instance->mfi_evt_detail_obj.status == DMA_OBJ_ALLOCATED) { 2143 (void) mrsas_free_dma_obj(instance, 2144 instance->mfi_evt_detail_obj); 2145 instance->mfi_evt_detail_obj.status = DMA_OBJ_FREED; 2146 } 2147 } 2148 2149 /* 2150 * alloc_additional_dma_buffer 2151 */ 2152 static int 2153 alloc_additional_dma_buffer(struct mrsas_instance *instance) 2154 { 2155 uint32_t reply_q_sz; 2156 uint32_t internal_buf_size = PAGESIZE*2; 2157 2158 /* max cmds plus 1 + producer & consumer */ 2159 reply_q_sz = sizeof (uint32_t) * (instance->max_fw_cmds + 1 + 2); 2160 2161 instance->mfi_internal_dma_obj.size = internal_buf_size; 2162 instance->mfi_internal_dma_obj.dma_attr = mrsas_generic_dma_attr; 2163 instance->mfi_internal_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 2164 instance->mfi_internal_dma_obj.dma_attr.dma_attr_count_max = 2165 0xFFFFFFFFU; 2166 instance->mfi_internal_dma_obj.dma_attr.dma_attr_sgllen = 1; 2167 2168 if (mrsas_alloc_dma_obj(instance, &instance->mfi_internal_dma_obj, 2169 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 2170 con_log(CL_ANN, (CE_WARN, 2171 "mr_sas: could not alloc reply queue")); 2172 return (DDI_FAILURE); 2173 } 2174 2175 bzero(instance->mfi_internal_dma_obj.buffer, internal_buf_size); 2176 2177 instance->mfi_internal_dma_obj.status |= DMA_OBJ_ALLOCATED; 2178 2179 instance->producer = (uint32_t *)((unsigned long) 2180 instance->mfi_internal_dma_obj.buffer); 2181 instance->consumer = (uint32_t *)((unsigned long) 2182 instance->mfi_internal_dma_obj.buffer + 4); 2183 instance->reply_queue = (uint32_t *)((unsigned long) 2184 instance->mfi_internal_dma_obj.buffer + 8); 2185 instance->internal_buf = (caddr_t)(((unsigned long) 2186 instance->mfi_internal_dma_obj.buffer) + reply_q_sz + 8); 2187 instance->internal_buf_dmac_add = 2188 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 2189 (reply_q_sz + 8); 2190 instance->internal_buf_size = internal_buf_size - 2191 (reply_q_sz + 8); 2192 2193 /* allocate evt_detail */ 2194 instance->mfi_evt_detail_obj.size = sizeof (struct mrsas_evt_detail); 2195 instance->mfi_evt_detail_obj.dma_attr = mrsas_generic_dma_attr; 2196 instance->mfi_evt_detail_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 2197 instance->mfi_evt_detail_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 2198 instance->mfi_evt_detail_obj.dma_attr.dma_attr_sgllen = 1; 2199 instance->mfi_evt_detail_obj.dma_attr.dma_attr_align = 1; 2200 2201 if (mrsas_alloc_dma_obj(instance, &instance->mfi_evt_detail_obj, 2202 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 2203 con_log(CL_ANN, (CE_WARN, "alloc_additional_dma_buffer: " 2204 "could not allocate data transfer buffer.")); 2205 return (DDI_FAILURE); 2206 } 2207 2208 bzero(instance->mfi_evt_detail_obj.buffer, 2209 sizeof (struct mrsas_evt_detail)); 2210 2211 instance->mfi_evt_detail_obj.status |= DMA_OBJ_ALLOCATED; 2212 2213 return (DDI_SUCCESS); 2214 } 2215 2216 /* 2217 * free_space_for_mfi 2218 */ 2219 static void 2220 free_space_for_mfi(struct mrsas_instance *instance) 2221 { 2222 int i; 2223 uint32_t max_cmd = instance->max_fw_cmds; 2224 2225 /* already freed */ 2226 if (instance->cmd_list == NULL) { 2227 return; 2228 } 2229 2230 free_additional_dma_buffer(instance); 2231 2232 /* first free the MFI frame pool */ 2233 destroy_mfi_frame_pool(instance); 2234 2235 /* free all the commands in the cmd_list */ 2236 for (i = 0; i < instance->max_fw_cmds+1; i++) { 2237 kmem_free(instance->cmd_list[i], 2238 sizeof (struct mrsas_cmd)); 2239 2240 instance->cmd_list[i] = NULL; 2241 } 2242 2243 /* free the cmd_list buffer itself */ 2244 kmem_free(instance->cmd_list, 2245 sizeof (struct mrsas_cmd *) * (max_cmd+1)); 2246 2247 instance->cmd_list = NULL; 2248 2249 INIT_LIST_HEAD(&instance->cmd_pool_list); 2250 INIT_LIST_HEAD(&instance->app_cmd_pool_list); 2251 INIT_LIST_HEAD(&instance->cmd_pend_list); 2252 } 2253 2254 /* 2255 * alloc_space_for_mfi 2256 */ 2257 static int 2258 alloc_space_for_mfi(struct mrsas_instance *instance) 2259 { 2260 int i; 2261 uint32_t max_cmd; 2262 uint32_t reserve_cmd; 2263 size_t sz; 2264 2265 struct mrsas_cmd *cmd; 2266 2267 max_cmd = instance->max_fw_cmds; 2268 2269 /* reserve 1 more slot for flush_cache */ 2270 sz = sizeof (struct mrsas_cmd *) * (max_cmd+1); 2271 2272 /* 2273 * instance->cmd_list is an array of struct mrsas_cmd pointers. 2274 * Allocate the dynamic array first and then allocate individual 2275 * commands. 2276 */ 2277 instance->cmd_list = kmem_zalloc(sz, KM_SLEEP); 2278 ASSERT(instance->cmd_list); 2279 2280 for (i = 0; i < max_cmd+1; i++) { 2281 instance->cmd_list[i] = kmem_zalloc(sizeof (struct mrsas_cmd), 2282 KM_SLEEP); 2283 ASSERT(instance->cmd_list[i]); 2284 } 2285 2286 INIT_LIST_HEAD(&instance->cmd_pool_list); 2287 INIT_LIST_HEAD(&instance->cmd_pend_list); 2288 /* add all the commands to command pool (instance->cmd_pool) */ 2289 reserve_cmd = APP_RESERVE_CMDS; 2290 INIT_LIST_HEAD(&instance->app_cmd_pool_list); 2291 for (i = 0; i < reserve_cmd; i++) { 2292 cmd = instance->cmd_list[i]; 2293 cmd->index = i; 2294 mlist_add_tail(&cmd->list, &instance->app_cmd_pool_list); 2295 } 2296 for (i = reserve_cmd; i < max_cmd; i++) { 2297 cmd = instance->cmd_list[i]; 2298 cmd->index = i; 2299 mlist_add_tail(&cmd->list, &instance->cmd_pool_list); 2300 } 2301 2302 /* single slot for flush_cache won't be added in command pool */ 2303 cmd = instance->cmd_list[max_cmd]; 2304 cmd->index = i; 2305 2306 /* create a frame pool and assign one frame to each cmd */ 2307 if (create_mfi_frame_pool(instance)) { 2308 con_log(CL_ANN, (CE_NOTE, "error creating frame DMA pool")); 2309 return (DDI_FAILURE); 2310 } 2311 2312 /* create a frame pool and assign one frame to each cmd */ 2313 if (alloc_additional_dma_buffer(instance)) { 2314 con_log(CL_ANN, (CE_NOTE, "error creating frame DMA pool")); 2315 return (DDI_FAILURE); 2316 } 2317 2318 return (DDI_SUCCESS); 2319 } 2320 2321 2322 /* 2323 * get_ctrl_info 2324 */ 2325 static int 2326 get_ctrl_info(struct mrsas_instance *instance, 2327 struct mrsas_ctrl_info *ctrl_info) 2328 { 2329 int ret = 0; 2330 2331 struct mrsas_cmd *cmd; 2332 struct mrsas_dcmd_frame *dcmd; 2333 struct mrsas_ctrl_info *ci; 2334 2335 cmd = get_mfi_pkt(instance); 2336 2337 if (!cmd) { 2338 con_log(CL_ANN, (CE_WARN, 2339 "Failed to get a cmd for ctrl info")); 2340 DTRACE_PROBE2(info_mfi_err, uint16_t, instance->fw_outstanding, 2341 uint16_t, instance->max_fw_cmds); 2342 return (DDI_FAILURE); 2343 } 2344 cmd->retry_count_for_ocr = 0; 2345 /* Clear the frame buffer and assign back the context id */ 2346 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 2347 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 2348 cmd->index); 2349 2350 dcmd = &cmd->frame->dcmd; 2351 2352 ci = (struct mrsas_ctrl_info *)instance->internal_buf; 2353 2354 if (!ci) { 2355 con_log(CL_ANN, (CE_WARN, 2356 "Failed to alloc mem for ctrl info")); 2357 return_mfi_pkt(instance, cmd); 2358 return (DDI_FAILURE); 2359 } 2360 2361 (void) memset(ci, 0, sizeof (struct mrsas_ctrl_info)); 2362 2363 /* for( i = 0; i < DCMD_MBOX_SZ; i++ ) dcmd->mbox.b[i] = 0; */ 2364 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 2365 2366 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 2367 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 2368 MFI_CMD_STATUS_POLL_MODE); 2369 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1); 2370 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 2371 MFI_FRAME_DIR_READ); 2372 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 2373 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 2374 sizeof (struct mrsas_ctrl_info)); 2375 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 2376 MR_DCMD_CTRL_GET_INFO); 2377 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr, 2378 instance->internal_buf_dmac_add); 2379 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length, 2380 sizeof (struct mrsas_ctrl_info)); 2381 2382 cmd->frame_count = 1; 2383 2384 if (!instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 2385 ret = 0; 2386 2387 ctrl_info->max_request_size = ddi_get32( 2388 cmd->frame_dma_obj.acc_handle, &ci->max_request_size); 2389 2390 ctrl_info->ld_present_count = ddi_get16( 2391 cmd->frame_dma_obj.acc_handle, &ci->ld_present_count); 2392 2393 /* 2394 * ctrl_info->properties.on_off_properties.disable_online_ctrl_reset = 2395 * ci->properties.on_off_properties.disable_online_ctrl_reset; 2396 */ 2397 ddi_rep_get8(cmd->frame_dma_obj.acc_handle, 2398 (uint8_t *)(ctrl_info->product_name), 2399 (uint8_t *)(ci->product_name), 80 * sizeof (char), 2400 DDI_DEV_AUTOINCR); 2401 /* should get more members of ci with ddi_get when needed */ 2402 } else { 2403 con_log(CL_ANN, (CE_WARN, "get_ctrl_info: Ctrl info failed")); 2404 ret = -1; 2405 } 2406 2407 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) { 2408 ret = -1; 2409 } 2410 return_mfi_pkt(instance, cmd); 2411 2412 return (ret); 2413 } 2414 2415 /* 2416 * abort_aen_cmd 2417 */ 2418 static int 2419 abort_aen_cmd(struct mrsas_instance *instance, 2420 struct mrsas_cmd *cmd_to_abort) 2421 { 2422 int ret = 0; 2423 2424 struct mrsas_cmd *cmd; 2425 struct mrsas_abort_frame *abort_fr; 2426 2427 cmd = get_mfi_pkt(instance); 2428 2429 if (!cmd) { 2430 con_log(CL_ANN, (CE_WARN, 2431 "abort_aen_cmd():Failed to get a cmd for ctrl info")); 2432 DTRACE_PROBE2(abort_mfi_err, uint16_t, instance->fw_outstanding, 2433 uint16_t, instance->max_fw_cmds); 2434 return (DDI_FAILURE); 2435 } 2436 cmd->retry_count_for_ocr = 0; 2437 /* Clear the frame buffer and assign back the context id */ 2438 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 2439 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 2440 cmd->index); 2441 2442 abort_fr = &cmd->frame->abort; 2443 2444 /* prepare and issue the abort frame */ 2445 ddi_put8(cmd->frame_dma_obj.acc_handle, 2446 &abort_fr->cmd, MFI_CMD_OP_ABORT); 2447 ddi_put8(cmd->frame_dma_obj.acc_handle, &abort_fr->cmd_status, 2448 MFI_CMD_STATUS_SYNC_MODE); 2449 ddi_put16(cmd->frame_dma_obj.acc_handle, &abort_fr->flags, 0); 2450 ddi_put32(cmd->frame_dma_obj.acc_handle, &abort_fr->abort_context, 2451 cmd_to_abort->index); 2452 ddi_put32(cmd->frame_dma_obj.acc_handle, 2453 &abort_fr->abort_mfi_phys_addr_lo, cmd_to_abort->frame_phys_addr); 2454 ddi_put32(cmd->frame_dma_obj.acc_handle, 2455 &abort_fr->abort_mfi_phys_addr_hi, 0); 2456 2457 instance->aen_cmd->abort_aen = 1; 2458 2459 cmd->sync_cmd = MRSAS_TRUE; 2460 cmd->frame_count = 1; 2461 2462 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 2463 con_log(CL_ANN, (CE_WARN, 2464 "abort_aen_cmd: issue_cmd_in_sync_mode failed")); 2465 ret = -1; 2466 } else { 2467 ret = 0; 2468 } 2469 2470 instance->aen_cmd->abort_aen = 1; 2471 instance->aen_cmd = 0; 2472 2473 (void) mrsas_common_check(instance, cmd); 2474 2475 return_mfi_pkt(instance, cmd); 2476 2477 return (ret); 2478 } 2479 2480 2481 /* 2482 * init_mfi 2483 */ 2484 static int 2485 init_mfi(struct mrsas_instance *instance) 2486 { 2487 struct mrsas_cmd *cmd; 2488 struct mrsas_ctrl_info ctrl_info; 2489 struct mrsas_init_frame *init_frame; 2490 struct mrsas_init_queue_info *initq_info; 2491 2492 /* we expect the FW state to be READY */ 2493 if (mfi_state_transition_to_ready(instance)) { 2494 con_log(CL_ANN, (CE_WARN, "mr_sas: F/W is not ready")); 2495 goto fail_ready_state; 2496 } 2497 2498 /* get various operational parameters from status register */ 2499 instance->max_num_sge = 2500 (instance->func_ptr->read_fw_status_reg(instance) & 2501 0xFF0000) >> 0x10; 2502 /* 2503 * Reduce the max supported cmds by 1. This is to ensure that the 2504 * reply_q_sz (1 more than the max cmd that driver may send) 2505 * does not exceed max cmds that the FW can support 2506 */ 2507 instance->max_fw_cmds = 2508 instance->func_ptr->read_fw_status_reg(instance) & 0xFFFF; 2509 instance->max_fw_cmds = instance->max_fw_cmds - 1; 2510 2511 instance->max_num_sge = 2512 (instance->max_num_sge > MRSAS_MAX_SGE_CNT) ? 2513 MRSAS_MAX_SGE_CNT : instance->max_num_sge; 2514 2515 /* create a pool of commands */ 2516 if (alloc_space_for_mfi(instance) != DDI_SUCCESS) 2517 goto fail_alloc_fw_space; 2518 2519 /* 2520 * Prepare a init frame. Note the init frame points to queue info 2521 * structure. Each frame has SGL allocated after first 64 bytes. For 2522 * this frame - since we don't need any SGL - we use SGL's space as 2523 * queue info structure 2524 */ 2525 cmd = get_mfi_pkt(instance); 2526 cmd->retry_count_for_ocr = 0; 2527 2528 /* Clear the frame buffer and assign back the context id */ 2529 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 2530 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 2531 cmd->index); 2532 2533 init_frame = (struct mrsas_init_frame *)cmd->frame; 2534 initq_info = (struct mrsas_init_queue_info *) 2535 ((unsigned long)init_frame + 64); 2536 2537 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE); 2538 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info)); 2539 2540 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0); 2541 2542 ddi_put32(cmd->frame_dma_obj.acc_handle, 2543 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1); 2544 2545 ddi_put32(cmd->frame_dma_obj.acc_handle, 2546 &initq_info->producer_index_phys_addr_hi, 0); 2547 ddi_put32(cmd->frame_dma_obj.acc_handle, 2548 &initq_info->producer_index_phys_addr_lo, 2549 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address); 2550 2551 ddi_put32(cmd->frame_dma_obj.acc_handle, 2552 &initq_info->consumer_index_phys_addr_hi, 0); 2553 ddi_put32(cmd->frame_dma_obj.acc_handle, 2554 &initq_info->consumer_index_phys_addr_lo, 2555 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4); 2556 2557 ddi_put32(cmd->frame_dma_obj.acc_handle, 2558 &initq_info->reply_queue_start_phys_addr_hi, 0); 2559 ddi_put32(cmd->frame_dma_obj.acc_handle, 2560 &initq_info->reply_queue_start_phys_addr_lo, 2561 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8); 2562 2563 ddi_put8(cmd->frame_dma_obj.acc_handle, 2564 &init_frame->cmd, MFI_CMD_OP_INIT); 2565 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status, 2566 MFI_CMD_STATUS_POLL_MODE); 2567 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0); 2568 ddi_put32(cmd->frame_dma_obj.acc_handle, 2569 &init_frame->queue_info_new_phys_addr_lo, 2570 cmd->frame_phys_addr + 64); 2571 ddi_put32(cmd->frame_dma_obj.acc_handle, 2572 &init_frame->queue_info_new_phys_addr_hi, 0); 2573 2574 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len, 2575 sizeof (struct mrsas_init_queue_info)); 2576 2577 cmd->frame_count = 1; 2578 2579 /* issue the init frame in polled mode */ 2580 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 2581 con_log(CL_ANN, (CE_WARN, "failed to init firmware")); 2582 return_mfi_pkt(instance, cmd); 2583 goto fail_fw_init; 2584 } 2585 2586 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) { 2587 return_mfi_pkt(instance, cmd); 2588 goto fail_fw_init; 2589 } 2590 return_mfi_pkt(instance, cmd); 2591 2592 if (ctio_enable && 2593 (instance->func_ptr->read_fw_status_reg(instance) & 0x04000000)) { 2594 con_log(CL_ANN, (CE_NOTE, "mr_sas: IEEE SGL's supported")); 2595 instance->flag_ieee = 1; 2596 } else { 2597 instance->flag_ieee = 0; 2598 } 2599 2600 instance->disable_online_ctrl_reset = 0; 2601 /* gather misc FW related information */ 2602 if (!get_ctrl_info(instance, &ctrl_info)) { 2603 instance->max_sectors_per_req = ctrl_info.max_request_size; 2604 con_log(CL_ANN1, (CE_NOTE, 2605 "product name %s ld present %d", 2606 ctrl_info.product_name, ctrl_info.ld_present_count)); 2607 } else { 2608 instance->max_sectors_per_req = instance->max_num_sge * 2609 PAGESIZE / 512; 2610 } 2611 /* 2612 * instance->disable_online_ctrl_reset = 2613 * ctrl_info.properties.on_off_properties.disable_online_ctrl_reset; 2614 */ 2615 return (DDI_SUCCESS); 2616 2617 fail_fw_init: 2618 fail_alloc_fw_space: 2619 2620 free_space_for_mfi(instance); 2621 2622 fail_ready_state: 2623 ddi_regs_map_free(&instance->regmap_handle); 2624 2625 fail_mfi_reg_setup: 2626 return (DDI_FAILURE); 2627 } 2628 2629 2630 2631 2632 2633 2634 static int 2635 mrsas_issue_init_mfi(struct mrsas_instance *instance) 2636 { 2637 struct mrsas_cmd *cmd; 2638 struct mrsas_init_frame *init_frame; 2639 struct mrsas_init_queue_info *initq_info; 2640 2641 /* 2642 * Prepare a init frame. Note the init frame points to queue info 2643 * structure. Each frame has SGL allocated after first 64 bytes. For 2644 * this frame - since we don't need any SGL - we use SGL's space as 2645 * queue info structure 2646 */ 2647 con_log(CL_ANN1, (CE_NOTE, 2648 "mrsas_issue_init_mfi: entry\n")); 2649 cmd = get_mfi_app_pkt(instance); 2650 2651 if (!cmd) { 2652 con_log(CL_ANN1, (CE_NOTE, 2653 "mrsas_issue_init_mfi: get_pkt failed\n")); 2654 return (DDI_FAILURE); 2655 } 2656 2657 /* Clear the frame buffer and assign back the context id */ 2658 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 2659 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 2660 cmd->index); 2661 2662 init_frame = (struct mrsas_init_frame *)cmd->frame; 2663 initq_info = (struct mrsas_init_queue_info *) 2664 ((unsigned long)init_frame + 64); 2665 2666 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE); 2667 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info)); 2668 2669 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0); 2670 2671 ddi_put32(cmd->frame_dma_obj.acc_handle, 2672 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1); 2673 ddi_put32(cmd->frame_dma_obj.acc_handle, 2674 &initq_info->producer_index_phys_addr_hi, 0); 2675 ddi_put32(cmd->frame_dma_obj.acc_handle, 2676 &initq_info->producer_index_phys_addr_lo, 2677 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address); 2678 ddi_put32(cmd->frame_dma_obj.acc_handle, 2679 &initq_info->consumer_index_phys_addr_hi, 0); 2680 ddi_put32(cmd->frame_dma_obj.acc_handle, 2681 &initq_info->consumer_index_phys_addr_lo, 2682 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4); 2683 2684 ddi_put32(cmd->frame_dma_obj.acc_handle, 2685 &initq_info->reply_queue_start_phys_addr_hi, 0); 2686 ddi_put32(cmd->frame_dma_obj.acc_handle, 2687 &initq_info->reply_queue_start_phys_addr_lo, 2688 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8); 2689 2690 ddi_put8(cmd->frame_dma_obj.acc_handle, 2691 &init_frame->cmd, MFI_CMD_OP_INIT); 2692 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status, 2693 MFI_CMD_STATUS_POLL_MODE); 2694 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0); 2695 ddi_put32(cmd->frame_dma_obj.acc_handle, 2696 &init_frame->queue_info_new_phys_addr_lo, 2697 cmd->frame_phys_addr + 64); 2698 ddi_put32(cmd->frame_dma_obj.acc_handle, 2699 &init_frame->queue_info_new_phys_addr_hi, 0); 2700 2701 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len, 2702 sizeof (struct mrsas_init_queue_info)); 2703 2704 cmd->frame_count = 1; 2705 2706 /* issue the init frame in polled mode */ 2707 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 2708 con_log(CL_ANN1, (CE_WARN, 2709 "mrsas_issue_init_mfi():failed to " 2710 "init firmware")); 2711 return_mfi_app_pkt(instance, cmd); 2712 return (DDI_FAILURE); 2713 } 2714 return_mfi_app_pkt(instance, cmd); 2715 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_init_mfi: Done")); 2716 return (DDI_SUCCESS); 2717 } 2718 /* 2719 * mfi_state_transition_to_ready : Move the FW to READY state 2720 * 2721 * @reg_set : MFI register set 2722 */ 2723 static int 2724 mfi_state_transition_to_ready(struct mrsas_instance *instance) 2725 { 2726 int i; 2727 uint8_t max_wait; 2728 uint32_t fw_ctrl; 2729 uint32_t fw_state; 2730 uint32_t cur_state; 2731 uint32_t cur_abs_reg_val; 2732 uint32_t prev_abs_reg_val; 2733 2734 cur_abs_reg_val = 2735 instance->func_ptr->read_fw_status_reg(instance); 2736 fw_state = 2737 cur_abs_reg_val & MFI_STATE_MASK; 2738 con_log(CL_ANN1, (CE_NOTE, 2739 "mfi_state_transition_to_ready:FW state = 0x%x", fw_state)); 2740 2741 while (fw_state != MFI_STATE_READY) { 2742 con_log(CL_ANN, (CE_NOTE, 2743 "mfi_state_transition_to_ready:FW state%x", fw_state)); 2744 2745 switch (fw_state) { 2746 case MFI_STATE_FAULT: 2747 con_log(CL_ANN1, (CE_NOTE, 2748 "mr_sas: FW in FAULT state!!")); 2749 2750 return (ENODEV); 2751 case MFI_STATE_WAIT_HANDSHAKE: 2752 /* set the CLR bit in IMR0 */ 2753 con_log(CL_ANN1, (CE_NOTE, 2754 "mr_sas: FW waiting for HANDSHAKE")); 2755 /* 2756 * PCI_Hot Plug: MFI F/W requires 2757 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG) 2758 * to be set 2759 */ 2760 /* WR_IB_MSG_0(MFI_INIT_CLEAR_HANDSHAKE, instance); */ 2761 WR_IB_DOORBELL(MFI_INIT_CLEAR_HANDSHAKE | 2762 MFI_INIT_HOTPLUG, instance); 2763 2764 max_wait = 2; 2765 cur_state = MFI_STATE_WAIT_HANDSHAKE; 2766 break; 2767 case MFI_STATE_BOOT_MESSAGE_PENDING: 2768 /* set the CLR bit in IMR0 */ 2769 con_log(CL_ANN1, (CE_NOTE, 2770 "mr_sas: FW state boot message pending")); 2771 /* 2772 * PCI_Hot Plug: MFI F/W requires 2773 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG) 2774 * to be set 2775 */ 2776 WR_IB_DOORBELL(MFI_INIT_HOTPLUG, instance); 2777 2778 max_wait = 10; 2779 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING; 2780 break; 2781 case MFI_STATE_OPERATIONAL: 2782 /* bring it to READY state; assuming max wait 2 secs */ 2783 instance->func_ptr->disable_intr(instance); 2784 con_log(CL_ANN1, (CE_NOTE, 2785 "mr_sas: FW in OPERATIONAL state")); 2786 /* 2787 * PCI_Hot Plug: MFI F/W requires 2788 * (MFI_INIT_READY | MFI_INIT_MFIMODE | MFI_INIT_ABORT) 2789 * to be set 2790 */ 2791 /* WR_IB_DOORBELL(MFI_INIT_READY, instance); */ 2792 WR_IB_DOORBELL(MFI_RESET_FLAGS, instance); 2793 2794 max_wait = 10; 2795 cur_state = MFI_STATE_OPERATIONAL; 2796 break; 2797 case MFI_STATE_UNDEFINED: 2798 /* this state should not last for more than 2 seconds */ 2799 con_log(CL_ANN1, (CE_NOTE, "FW state undefined")); 2800 2801 max_wait = 2; 2802 cur_state = MFI_STATE_UNDEFINED; 2803 break; 2804 case MFI_STATE_BB_INIT: 2805 max_wait = 2; 2806 cur_state = MFI_STATE_BB_INIT; 2807 break; 2808 case MFI_STATE_FW_INIT: 2809 max_wait = 2; 2810 cur_state = MFI_STATE_FW_INIT; 2811 break; 2812 case MFI_STATE_DEVICE_SCAN: 2813 max_wait = 180; 2814 cur_state = MFI_STATE_DEVICE_SCAN; 2815 prev_abs_reg_val = cur_abs_reg_val; 2816 con_log(CL_NONE, (CE_NOTE, 2817 "Device scan in progress ...\n")); 2818 break; 2819 default: 2820 con_log(CL_ANN1, (CE_NOTE, 2821 "mr_sas: Unknown state 0x%x", fw_state)); 2822 return (ENODEV); 2823 } 2824 2825 /* the cur_state should not last for more than max_wait secs */ 2826 for (i = 0; i < (max_wait * MILLISEC); i++) { 2827 /* fw_state = RD_OB_MSG_0(instance) & MFI_STATE_MASK; */ 2828 cur_abs_reg_val = 2829 instance->func_ptr->read_fw_status_reg(instance); 2830 fw_state = cur_abs_reg_val & MFI_STATE_MASK; 2831 2832 if (fw_state == cur_state) { 2833 delay(1 * drv_usectohz(MILLISEC)); 2834 } else { 2835 break; 2836 } 2837 } 2838 if (fw_state == MFI_STATE_DEVICE_SCAN) { 2839 if (prev_abs_reg_val != cur_abs_reg_val) { 2840 continue; 2841 } 2842 } 2843 2844 /* return error if fw_state hasn't changed after max_wait */ 2845 if (fw_state == cur_state) { 2846 con_log(CL_ANN1, (CE_NOTE, 2847 "FW state hasn't changed in %d secs", max_wait)); 2848 return (ENODEV); 2849 } 2850 }; 2851 2852 fw_ctrl = RD_IB_DOORBELL(instance); 2853 2854 con_log(CL_ANN1, (CE_NOTE, 2855 "mfi_state_transition_to_ready:FW ctrl = 0x%x", fw_ctrl)); 2856 2857 /* 2858 * Write 0xF to the doorbell register to do the following. 2859 * - Abort all outstanding commands (bit 0). 2860 * - Transition from OPERATIONAL to READY state (bit 1). 2861 * - Discard (possible) low MFA posted in 64-bit mode (bit-2). 2862 * - Set to release FW to continue running (i.e. BIOS handshake 2863 * (bit 3). 2864 */ 2865 WR_IB_DOORBELL(0xF, instance); 2866 2867 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) { 2868 return (ENODEV); 2869 } 2870 return (DDI_SUCCESS); 2871 } 2872 2873 /* 2874 * get_seq_num 2875 */ 2876 static int 2877 get_seq_num(struct mrsas_instance *instance, 2878 struct mrsas_evt_log_info *eli) 2879 { 2880 int ret = DDI_SUCCESS; 2881 2882 dma_obj_t dcmd_dma_obj; 2883 struct mrsas_cmd *cmd; 2884 struct mrsas_dcmd_frame *dcmd; 2885 struct mrsas_evt_log_info *eli_tmp; 2886 cmd = get_mfi_pkt(instance); 2887 2888 if (!cmd) { 2889 cmn_err(CE_WARN, "mr_sas: failed to get a cmd"); 2890 DTRACE_PROBE2(seq_num_mfi_err, uint16_t, 2891 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 2892 return (ENOMEM); 2893 } 2894 cmd->retry_count_for_ocr = 0; 2895 /* Clear the frame buffer and assign back the context id */ 2896 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 2897 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 2898 cmd->index); 2899 2900 dcmd = &cmd->frame->dcmd; 2901 2902 /* allocate the data transfer buffer */ 2903 dcmd_dma_obj.size = sizeof (struct mrsas_evt_log_info); 2904 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr; 2905 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 2906 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 2907 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1; 2908 dcmd_dma_obj.dma_attr.dma_attr_align = 1; 2909 2910 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj, 2911 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 2912 con_log(CL_ANN, (CE_WARN, 2913 "get_seq_num: could not allocate data transfer buffer.")); 2914 return (DDI_FAILURE); 2915 } 2916 2917 (void) memset(dcmd_dma_obj.buffer, 0, 2918 sizeof (struct mrsas_evt_log_info)); 2919 2920 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 2921 2922 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 2923 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0); 2924 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1); 2925 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 2926 MFI_FRAME_DIR_READ); 2927 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 2928 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 2929 sizeof (struct mrsas_evt_log_info)); 2930 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 2931 MR_DCMD_CTRL_EVENT_GET_INFO); 2932 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length, 2933 sizeof (struct mrsas_evt_log_info)); 2934 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr, 2935 dcmd_dma_obj.dma_cookie[0].dmac_address); 2936 2937 cmd->sync_cmd = MRSAS_TRUE; 2938 cmd->frame_count = 1; 2939 2940 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 2941 cmn_err(CE_WARN, "get_seq_num: " 2942 "failed to issue MRSAS_DCMD_CTRL_EVENT_GET_INFO"); 2943 ret = DDI_FAILURE; 2944 } else { 2945 eli_tmp = (struct mrsas_evt_log_info *)dcmd_dma_obj.buffer; 2946 eli->newest_seq_num = ddi_get32(cmd->frame_dma_obj.acc_handle, 2947 &eli_tmp->newest_seq_num); 2948 ret = DDI_SUCCESS; 2949 } 2950 2951 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS) 2952 ret = DDI_FAILURE; 2953 2954 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) { 2955 ret = DDI_FAILURE; 2956 } 2957 2958 return_mfi_pkt(instance, cmd); 2959 2960 return (ret); 2961 } 2962 2963 /* 2964 * start_mfi_aen 2965 */ 2966 static int 2967 start_mfi_aen(struct mrsas_instance *instance) 2968 { 2969 int ret = 0; 2970 2971 struct mrsas_evt_log_info eli; 2972 union mrsas_evt_class_locale class_locale; 2973 2974 /* get the latest sequence number from FW */ 2975 (void) memset(&eli, 0, sizeof (struct mrsas_evt_log_info)); 2976 2977 if (get_seq_num(instance, &eli)) { 2978 cmn_err(CE_WARN, "start_mfi_aen: failed to get seq num"); 2979 return (-1); 2980 } 2981 2982 /* register AEN with FW for latest sequence number plus 1 */ 2983 class_locale.members.reserved = 0; 2984 class_locale.members.locale = LE_16(MR_EVT_LOCALE_ALL); 2985 class_locale.members.class = MR_EVT_CLASS_INFO; 2986 class_locale.word = LE_32(class_locale.word); 2987 ret = register_mfi_aen(instance, eli.newest_seq_num + 1, 2988 class_locale.word); 2989 2990 if (ret) { 2991 cmn_err(CE_WARN, "start_mfi_aen: aen registration failed"); 2992 return (-1); 2993 } 2994 2995 return (ret); 2996 } 2997 2998 /* 2999 * flush_cache 3000 */ 3001 static void 3002 flush_cache(struct mrsas_instance *instance) 3003 { 3004 struct mrsas_cmd *cmd = NULL; 3005 struct mrsas_dcmd_frame *dcmd; 3006 uint32_t max_cmd = instance->max_fw_cmds; 3007 3008 cmd = instance->cmd_list[max_cmd]; 3009 3010 if (cmd == NULL) 3011 return; 3012 3013 dcmd = &cmd->frame->dcmd; 3014 3015 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 3016 3017 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 3018 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0); 3019 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 0); 3020 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 3021 MFI_FRAME_DIR_NONE); 3022 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 3023 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 0); 3024 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 3025 MR_DCMD_CTRL_CACHE_FLUSH); 3026 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.b[0], 3027 MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE); 3028 3029 cmd->frame_count = 1; 3030 3031 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 3032 con_log(CL_ANN1, (CE_WARN, 3033 "flush_cache: failed to issue MFI_DCMD_CTRL_CACHE_FLUSH")); 3034 } 3035 con_log(CL_ANN1, (CE_NOTE, "flush_cache done")); 3036 } 3037 3038 /* 3039 * service_mfi_aen- Completes an AEN command 3040 * @instance: Adapter soft state 3041 * @cmd: Command to be completed 3042 * 3043 */ 3044 static void 3045 service_mfi_aen(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 3046 { 3047 uint32_t seq_num; 3048 struct mrsas_evt_detail *evt_detail = 3049 (struct mrsas_evt_detail *)instance->mfi_evt_detail_obj.buffer; 3050 int rval = 0; 3051 int tgt = 0; 3052 ddi_acc_handle_t acc_handle; 3053 3054 acc_handle = cmd->frame_dma_obj.acc_handle; 3055 3056 cmd->cmd_status = ddi_get8(acc_handle, &cmd->frame->io.cmd_status); 3057 3058 if (cmd->cmd_status == ENODATA) { 3059 cmd->cmd_status = 0; 3060 } 3061 3062 /* 3063 * log the MFI AEN event to the sysevent queue so that 3064 * application will get noticed 3065 */ 3066 if (ddi_log_sysevent(instance->dip, DDI_VENDOR_LSI, "LSIMEGA", "SAS", 3067 NULL, NULL, DDI_NOSLEEP) != DDI_SUCCESS) { 3068 int instance_no = ddi_get_instance(instance->dip); 3069 con_log(CL_ANN, (CE_WARN, 3070 "mr_sas%d: Failed to log AEN event", instance_no)); 3071 } 3072 /* 3073 * Check for any ld devices that has changed state. i.e. online 3074 * or offline. 3075 */ 3076 con_log(CL_ANN1, (CE_NOTE, 3077 "AEN: code = %x class = %x locale = %x args = %x", 3078 ddi_get32(acc_handle, &evt_detail->code), 3079 evt_detail->cl.members.class, 3080 ddi_get16(acc_handle, &evt_detail->cl.members.locale), 3081 ddi_get8(acc_handle, &evt_detail->arg_type))); 3082 3083 switch (ddi_get32(acc_handle, &evt_detail->code)) { 3084 case MR_EVT_CFG_CLEARED: { 3085 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) { 3086 if (instance->mr_ld_list[tgt].dip != NULL) { 3087 rval = mrsas_service_evt(instance, tgt, 0, 3088 MRSAS_EVT_UNCONFIG_TGT, NULL); 3089 con_log(CL_ANN1, (CE_WARN, 3090 "mr_sas: CFG CLEARED AEN rval = %d " 3091 "tgt id = %d", rval, tgt)); 3092 } 3093 } 3094 break; 3095 } 3096 3097 case MR_EVT_LD_DELETED: { 3098 rval = mrsas_service_evt(instance, 3099 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0, 3100 MRSAS_EVT_UNCONFIG_TGT, NULL); 3101 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD DELETED AEN rval = %d " 3102 "tgt id = %d index = %d", rval, 3103 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 3104 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index))); 3105 break; 3106 } /* End of MR_EVT_LD_DELETED */ 3107 3108 case MR_EVT_LD_CREATED: { 3109 rval = mrsas_service_evt(instance, 3110 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0, 3111 MRSAS_EVT_CONFIG_TGT, NULL); 3112 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD CREATED AEN rval = %d " 3113 "tgt id = %d index = %d", rval, 3114 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 3115 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index))); 3116 break; 3117 } /* End of MR_EVT_LD_CREATED */ 3118 } /* End of Main Switch */ 3119 3120 /* get copy of seq_num and class/locale for re-registration */ 3121 seq_num = ddi_get32(acc_handle, &evt_detail->seq_num); 3122 seq_num++; 3123 (void) memset(instance->mfi_evt_detail_obj.buffer, 0, 3124 sizeof (struct mrsas_evt_detail)); 3125 3126 ddi_put8(acc_handle, &cmd->frame->dcmd.cmd_status, 0x0); 3127 ddi_put32(acc_handle, &cmd->frame->dcmd.mbox.w[0], seq_num); 3128 3129 instance->aen_seq_num = seq_num; 3130 3131 cmd->frame_count = 1; 3132 3133 /* Issue the aen registration frame */ 3134 instance->func_ptr->issue_cmd(cmd, instance); 3135 } 3136 3137 /* 3138 * complete_cmd_in_sync_mode - Completes an internal command 3139 * @instance: Adapter soft state 3140 * @cmd: Command to be completed 3141 * 3142 * The issue_cmd_in_sync_mode() function waits for a command to complete 3143 * after it issues a command. This function wakes up that waiting routine by 3144 * calling wake_up() on the wait queue. 3145 */ 3146 static void 3147 complete_cmd_in_sync_mode(struct mrsas_instance *instance, 3148 struct mrsas_cmd *cmd) 3149 { 3150 cmd->cmd_status = ddi_get8(cmd->frame_dma_obj.acc_handle, 3151 &cmd->frame->io.cmd_status); 3152 3153 cmd->sync_cmd = MRSAS_FALSE; 3154 3155 if (cmd->cmd_status == ENODATA) { 3156 cmd->cmd_status = 0; 3157 } 3158 3159 con_log(CL_ANN1, (CE_NOTE, "complete_cmd_in_sync_mode called %p \n", 3160 (void *)cmd)); 3161 3162 cv_broadcast(&instance->int_cmd_cv); 3163 } 3164 3165 /* 3166 * Call this function inside mrsas_softintr. 3167 * mrsas_initiate_ocr_if_fw_is_faulty - Initiates OCR if FW status is faulty 3168 * @instance: Adapter soft state 3169 */ 3170 3171 static uint32_t 3172 mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *instance) 3173 { 3174 uint32_t cur_abs_reg_val; 3175 uint32_t fw_state; 3176 3177 cur_abs_reg_val = instance->func_ptr->read_fw_status_reg(instance); 3178 fw_state = cur_abs_reg_val & MFI_STATE_MASK; 3179 if (fw_state == MFI_STATE_FAULT) { 3180 3181 if (instance->disable_online_ctrl_reset == 1) { 3182 con_log(CL_ANN1, (CE_NOTE, 3183 "mrsas_initiate_ocr_if_fw_is_faulty: " 3184 "FW in Fault state, detected in ISR: " 3185 "FW doesn't support ocr ")); 3186 return (ADAPTER_RESET_NOT_REQUIRED); 3187 } else { 3188 con_log(CL_ANN1, (CE_NOTE, 3189 "mrsas_initiate_ocr_if_fw_is_faulty: " 3190 "FW in Fault state, detected in ISR: FW supports ocr ")); 3191 return (ADAPTER_RESET_REQUIRED); 3192 } 3193 } 3194 return (ADAPTER_RESET_NOT_REQUIRED); 3195 } 3196 3197 /* 3198 * mrsas_softintr - The Software ISR 3199 * @param arg : HBA soft state 3200 * 3201 * called from high-level interrupt if hi-level interrupt are not there, 3202 * otherwise triggered as a soft interrupt 3203 */ 3204 static uint_t 3205 mrsas_softintr(struct mrsas_instance *instance) 3206 { 3207 struct scsi_pkt *pkt; 3208 struct scsa_cmd *acmd; 3209 struct mrsas_cmd *cmd; 3210 struct mlist_head *pos, *next; 3211 mlist_t process_list; 3212 struct mrsas_header *hdr; 3213 struct scsi_arq_status *arqstat; 3214 3215 con_log(CL_ANN1, (CE_CONT, "mrsas_softintr called")); 3216 3217 ASSERT(instance); 3218 3219 mutex_enter(&instance->completed_pool_mtx); 3220 3221 if (mlist_empty(&instance->completed_pool_list)) { 3222 mutex_exit(&instance->completed_pool_mtx); 3223 return (DDI_INTR_CLAIMED); 3224 } 3225 3226 instance->softint_running = 1; 3227 3228 INIT_LIST_HEAD(&process_list); 3229 mlist_splice(&instance->completed_pool_list, &process_list); 3230 INIT_LIST_HEAD(&instance->completed_pool_list); 3231 3232 mutex_exit(&instance->completed_pool_mtx); 3233 3234 /* perform all callbacks first, before releasing the SCBs */ 3235 mlist_for_each_safe(pos, next, &process_list) { 3236 cmd = mlist_entry(pos, struct mrsas_cmd, list); 3237 3238 /* syncronize the Cmd frame for the controller */ 3239 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 3240 0, 0, DDI_DMA_SYNC_FORCPU); 3241 3242 if (mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) != 3243 DDI_SUCCESS) { 3244 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 3245 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 3246 con_log(CL_ANN1, (CE_WARN, 3247 "mrsas_softintr: " 3248 "FMA check reports DMA handle failure")); 3249 return (DDI_INTR_CLAIMED); 3250 } 3251 3252 hdr = &cmd->frame->hdr; 3253 3254 /* remove the internal command from the process list */ 3255 mlist_del_init(&cmd->list); 3256 3257 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) { 3258 case MFI_CMD_OP_PD_SCSI: 3259 case MFI_CMD_OP_LD_SCSI: 3260 case MFI_CMD_OP_LD_READ: 3261 case MFI_CMD_OP_LD_WRITE: 3262 /* 3263 * MFI_CMD_OP_PD_SCSI and MFI_CMD_OP_LD_SCSI 3264 * could have been issued either through an 3265 * IO path or an IOCTL path. If it was via IOCTL, 3266 * we will send it to internal completion. 3267 */ 3268 if (cmd->sync_cmd == MRSAS_TRUE) { 3269 complete_cmd_in_sync_mode(instance, cmd); 3270 break; 3271 } 3272 3273 /* regular commands */ 3274 acmd = cmd->cmd; 3275 pkt = CMD2PKT(acmd); 3276 3277 if (acmd->cmd_flags & CFLAG_DMAVALID) { 3278 if (acmd->cmd_flags & CFLAG_CONSISTENT) { 3279 (void) ddi_dma_sync(acmd->cmd_dmahandle, 3280 acmd->cmd_dma_offset, 3281 acmd->cmd_dma_len, 3282 DDI_DMA_SYNC_FORCPU); 3283 } 3284 } 3285 3286 pkt->pkt_reason = CMD_CMPLT; 3287 pkt->pkt_statistics = 0; 3288 pkt->pkt_state = STATE_GOT_BUS 3289 | STATE_GOT_TARGET | STATE_SENT_CMD 3290 | STATE_XFERRED_DATA | STATE_GOT_STATUS; 3291 3292 con_log(CL_ANN1, (CE_CONT, 3293 "CDB[0] = %x completed for %s: size %lx context %x", 3294 pkt->pkt_cdbp[0], ((acmd->islogical) ? "LD" : "PD"), 3295 acmd->cmd_dmacount, hdr->context)); 3296 DTRACE_PROBE3(softintr_cdb, uint8_t, pkt->pkt_cdbp[0], 3297 uint_t, acmd->cmd_cdblen, ulong_t, 3298 acmd->cmd_dmacount); 3299 3300 if (pkt->pkt_cdbp[0] == SCMD_INQUIRY) { 3301 struct scsi_inquiry *inq; 3302 3303 if (acmd->cmd_dmacount != 0) { 3304 bp_mapin(acmd->cmd_buf); 3305 inq = (struct scsi_inquiry *) 3306 acmd->cmd_buf->b_un.b_addr; 3307 3308 /* don't expose physical drives to OS */ 3309 if (acmd->islogical && 3310 (hdr->cmd_status == MFI_STAT_OK)) { 3311 display_scsi_inquiry( 3312 (caddr_t)inq); 3313 } else if ((hdr->cmd_status == 3314 MFI_STAT_OK) && inq->inq_dtype == 3315 DTYPE_DIRECT) { 3316 3317 display_scsi_inquiry( 3318 (caddr_t)inq); 3319 3320 /* for physical disk */ 3321 hdr->cmd_status = 3322 MFI_STAT_DEVICE_NOT_FOUND; 3323 } 3324 } 3325 } 3326 3327 DTRACE_PROBE2(softintr_done, uint8_t, hdr->cmd, 3328 uint8_t, hdr->cmd_status); 3329 3330 switch (hdr->cmd_status) { 3331 case MFI_STAT_OK: 3332 pkt->pkt_scbp[0] = STATUS_GOOD; 3333 break; 3334 case MFI_STAT_LD_CC_IN_PROGRESS: 3335 case MFI_STAT_LD_RECON_IN_PROGRESS: 3336 pkt->pkt_scbp[0] = STATUS_GOOD; 3337 break; 3338 case MFI_STAT_LD_INIT_IN_PROGRESS: 3339 con_log(CL_ANN, 3340 (CE_WARN, "Initialization in Progress")); 3341 pkt->pkt_reason = CMD_TRAN_ERR; 3342 3343 break; 3344 case MFI_STAT_SCSI_DONE_WITH_ERROR: 3345 con_log(CL_ANN1, (CE_CONT, "scsi_done error")); 3346 3347 pkt->pkt_reason = CMD_CMPLT; 3348 ((struct scsi_status *) 3349 pkt->pkt_scbp)->sts_chk = 1; 3350 3351 if (pkt->pkt_cdbp[0] == SCMD_TEST_UNIT_READY) { 3352 3353 con_log(CL_ANN, 3354 (CE_WARN, "TEST_UNIT_READY fail")); 3355 3356 } else { 3357 pkt->pkt_state |= STATE_ARQ_DONE; 3358 arqstat = (void *)(pkt->pkt_scbp); 3359 arqstat->sts_rqpkt_reason = CMD_CMPLT; 3360 arqstat->sts_rqpkt_resid = 0; 3361 arqstat->sts_rqpkt_state |= 3362 STATE_GOT_BUS | STATE_GOT_TARGET 3363 | STATE_SENT_CMD 3364 | STATE_XFERRED_DATA; 3365 *(uint8_t *)&arqstat->sts_rqpkt_status = 3366 STATUS_GOOD; 3367 ddi_rep_get8( 3368 cmd->frame_dma_obj.acc_handle, 3369 (uint8_t *) 3370 &(arqstat->sts_sensedata), 3371 cmd->sense, 3372 acmd->cmd_scblen - 3373 offsetof(struct scsi_arq_status, 3374 sts_sensedata), DDI_DEV_AUTOINCR); 3375 } 3376 break; 3377 case MFI_STAT_LD_OFFLINE: 3378 case MFI_STAT_DEVICE_NOT_FOUND: 3379 con_log(CL_ANN1, (CE_CONT, 3380 "mrsas_softintr:device not found error")); 3381 pkt->pkt_reason = CMD_DEV_GONE; 3382 pkt->pkt_statistics = STAT_DISCON; 3383 break; 3384 case MFI_STAT_LD_LBA_OUT_OF_RANGE: 3385 pkt->pkt_state |= STATE_ARQ_DONE; 3386 pkt->pkt_reason = CMD_CMPLT; 3387 ((struct scsi_status *) 3388 pkt->pkt_scbp)->sts_chk = 1; 3389 3390 arqstat = (void *)(pkt->pkt_scbp); 3391 arqstat->sts_rqpkt_reason = CMD_CMPLT; 3392 arqstat->sts_rqpkt_resid = 0; 3393 arqstat->sts_rqpkt_state |= STATE_GOT_BUS 3394 | STATE_GOT_TARGET | STATE_SENT_CMD 3395 | STATE_XFERRED_DATA; 3396 *(uint8_t *)&arqstat->sts_rqpkt_status = 3397 STATUS_GOOD; 3398 3399 arqstat->sts_sensedata.es_valid = 1; 3400 arqstat->sts_sensedata.es_key = 3401 KEY_ILLEGAL_REQUEST; 3402 arqstat->sts_sensedata.es_class = 3403 CLASS_EXTENDED_SENSE; 3404 3405 /* 3406 * LOGICAL BLOCK ADDRESS OUT OF RANGE: 3407 * ASC: 0x21h; ASCQ: 0x00h; 3408 */ 3409 arqstat->sts_sensedata.es_add_code = 0x21; 3410 arqstat->sts_sensedata.es_qual_code = 0x00; 3411 3412 break; 3413 3414 default: 3415 con_log(CL_ANN, (CE_CONT, "Unknown status!")); 3416 pkt->pkt_reason = CMD_TRAN_ERR; 3417 3418 break; 3419 } 3420 3421 atomic_add_16(&instance->fw_outstanding, (-1)); 3422 3423 (void) mrsas_common_check(instance, cmd); 3424 3425 if (acmd->cmd_dmahandle) { 3426 if (mrsas_check_dma_handle( 3427 acmd->cmd_dmahandle) != DDI_SUCCESS) { 3428 ddi_fm_service_impact(instance->dip, 3429 DDI_SERVICE_UNAFFECTED); 3430 pkt->pkt_reason = CMD_TRAN_ERR; 3431 pkt->pkt_statistics = 0; 3432 } 3433 } 3434 3435 /* Call the callback routine */ 3436 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && 3437 pkt->pkt_comp) { 3438 3439 con_log(CL_ANN1, (CE_NOTE, "mrsas_softintr: " 3440 "posting to scsa cmd %p index %x pkt %p " 3441 "time %llx", (void *)cmd, cmd->index, 3442 (void *)pkt, gethrtime())); 3443 (*pkt->pkt_comp)(pkt); 3444 3445 } 3446 return_mfi_pkt(instance, cmd); 3447 break; 3448 case MFI_CMD_OP_SMP: 3449 case MFI_CMD_OP_STP: 3450 complete_cmd_in_sync_mode(instance, cmd); 3451 break; 3452 case MFI_CMD_OP_DCMD: 3453 /* see if got an event notification */ 3454 if (ddi_get32(cmd->frame_dma_obj.acc_handle, 3455 &cmd->frame->dcmd.opcode) == 3456 MR_DCMD_CTRL_EVENT_WAIT) { 3457 if ((instance->aen_cmd == cmd) && 3458 (instance->aen_cmd->abort_aen)) { 3459 con_log(CL_ANN, (CE_WARN, 3460 "mrsas_softintr: " 3461 "aborted_aen returned")); 3462 } else { 3463 atomic_add_16(&instance->fw_outstanding, 3464 (-1)); 3465 service_mfi_aen(instance, cmd); 3466 } 3467 } else { 3468 complete_cmd_in_sync_mode(instance, cmd); 3469 } 3470 3471 break; 3472 case MFI_CMD_OP_ABORT: 3473 con_log(CL_ANN, (CE_WARN, "MFI_CMD_OP_ABORT complete")); 3474 /* 3475 * MFI_CMD_OP_ABORT successfully completed 3476 * in the synchronous mode 3477 */ 3478 complete_cmd_in_sync_mode(instance, cmd); 3479 break; 3480 default: 3481 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 3482 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 3483 3484 if (cmd->pkt != NULL) { 3485 pkt = cmd->pkt; 3486 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && 3487 pkt->pkt_comp) { 3488 3489 con_log(CL_ANN1, (CE_CONT, "posting to " 3490 "scsa cmd %p index %x pkt %p" 3491 "time %llx, default ", (void *)cmd, 3492 cmd->index, (void *)pkt, 3493 gethrtime())); 3494 3495 (*pkt->pkt_comp)(pkt); 3496 3497 } 3498 } 3499 con_log(CL_ANN, (CE_WARN, "Cmd type unknown !")); 3500 break; 3501 } 3502 } 3503 3504 instance->softint_running = 0; 3505 3506 return (DDI_INTR_CLAIMED); 3507 } 3508 3509 /* 3510 * mrsas_alloc_dma_obj 3511 * 3512 * Allocate the memory and other resources for an dma object. 3513 */ 3514 static int 3515 mrsas_alloc_dma_obj(struct mrsas_instance *instance, dma_obj_t *obj, 3516 uchar_t endian_flags) 3517 { 3518 int i; 3519 size_t alen = 0; 3520 uint_t cookie_cnt; 3521 struct ddi_device_acc_attr tmp_endian_attr; 3522 3523 tmp_endian_attr = endian_attr; 3524 tmp_endian_attr.devacc_attr_endian_flags = endian_flags; 3525 tmp_endian_attr.devacc_attr_access = DDI_DEFAULT_ACC; 3526 3527 i = ddi_dma_alloc_handle(instance->dip, &obj->dma_attr, 3528 DDI_DMA_SLEEP, NULL, &obj->dma_handle); 3529 if (i != DDI_SUCCESS) { 3530 3531 switch (i) { 3532 case DDI_DMA_BADATTR : 3533 con_log(CL_ANN, (CE_WARN, 3534 "Failed ddi_dma_alloc_handle- Bad attribute")); 3535 break; 3536 case DDI_DMA_NORESOURCES : 3537 con_log(CL_ANN, (CE_WARN, 3538 "Failed ddi_dma_alloc_handle- No Resources")); 3539 break; 3540 default : 3541 con_log(CL_ANN, (CE_WARN, 3542 "Failed ddi_dma_alloc_handle: " 3543 "unknown status %d", i)); 3544 break; 3545 } 3546 3547 return (-1); 3548 } 3549 3550 if ((ddi_dma_mem_alloc(obj->dma_handle, obj->size, &tmp_endian_attr, 3551 DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, 3552 &obj->buffer, &alen, &obj->acc_handle) != DDI_SUCCESS) || 3553 alen < obj->size) { 3554 3555 ddi_dma_free_handle(&obj->dma_handle); 3556 3557 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_mem_alloc")); 3558 3559 return (-1); 3560 } 3561 3562 if (ddi_dma_addr_bind_handle(obj->dma_handle, NULL, obj->buffer, 3563 obj->size, DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP, 3564 NULL, &obj->dma_cookie[0], &cookie_cnt) != DDI_SUCCESS) { 3565 3566 ddi_dma_mem_free(&obj->acc_handle); 3567 ddi_dma_free_handle(&obj->dma_handle); 3568 3569 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_addr_bind_handle")); 3570 3571 return (-1); 3572 } 3573 3574 if (mrsas_check_dma_handle(obj->dma_handle) != DDI_SUCCESS) { 3575 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 3576 return (-1); 3577 } 3578 3579 if (mrsas_check_acc_handle(obj->acc_handle) != DDI_SUCCESS) { 3580 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 3581 return (-1); 3582 } 3583 3584 return (cookie_cnt); 3585 } 3586 3587 /* 3588 * mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t) 3589 * 3590 * De-allocate the memory and other resources for an dma object, which must 3591 * have been alloated by a previous call to mrsas_alloc_dma_obj() 3592 */ 3593 static int 3594 mrsas_free_dma_obj(struct mrsas_instance *instance, dma_obj_t obj) 3595 { 3596 3597 if (mrsas_check_dma_handle(obj.dma_handle) != DDI_SUCCESS) { 3598 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 3599 return (DDI_FAILURE); 3600 } 3601 3602 if (mrsas_check_acc_handle(obj.acc_handle) != DDI_SUCCESS) { 3603 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 3604 return (DDI_FAILURE); 3605 } 3606 3607 (void) ddi_dma_unbind_handle(obj.dma_handle); 3608 ddi_dma_mem_free(&obj.acc_handle); 3609 ddi_dma_free_handle(&obj.dma_handle); 3610 3611 return (DDI_SUCCESS); 3612 } 3613 3614 /* 3615 * mrsas_dma_alloc(instance_t *, struct scsi_pkt *, struct buf *, 3616 * int, int (*)()) 3617 * 3618 * Allocate dma resources for a new scsi command 3619 */ 3620 static int 3621 mrsas_dma_alloc(struct mrsas_instance *instance, struct scsi_pkt *pkt, 3622 struct buf *bp, int flags, int (*callback)()) 3623 { 3624 int dma_flags; 3625 int (*cb)(caddr_t); 3626 int i; 3627 3628 ddi_dma_attr_t tmp_dma_attr = mrsas_generic_dma_attr; 3629 struct scsa_cmd *acmd = PKT2CMD(pkt); 3630 3631 acmd->cmd_buf = bp; 3632 3633 if (bp->b_flags & B_READ) { 3634 acmd->cmd_flags &= ~CFLAG_DMASEND; 3635 dma_flags = DDI_DMA_READ; 3636 } else { 3637 acmd->cmd_flags |= CFLAG_DMASEND; 3638 dma_flags = DDI_DMA_WRITE; 3639 } 3640 3641 if (flags & PKT_CONSISTENT) { 3642 acmd->cmd_flags |= CFLAG_CONSISTENT; 3643 dma_flags |= DDI_DMA_CONSISTENT; 3644 } 3645 3646 if (flags & PKT_DMA_PARTIAL) { 3647 dma_flags |= DDI_DMA_PARTIAL; 3648 } 3649 3650 dma_flags |= DDI_DMA_REDZONE; 3651 3652 cb = (callback == NULL_FUNC) ? DDI_DMA_DONTWAIT : DDI_DMA_SLEEP; 3653 3654 tmp_dma_attr.dma_attr_sgllen = instance->max_num_sge; 3655 tmp_dma_attr.dma_attr_addr_hi = 0xffffffffffffffffull; 3656 3657 if ((i = ddi_dma_alloc_handle(instance->dip, &tmp_dma_attr, 3658 cb, 0, &acmd->cmd_dmahandle)) != DDI_SUCCESS) { 3659 switch (i) { 3660 case DDI_DMA_BADATTR: 3661 bioerror(bp, EFAULT); 3662 return (DDI_FAILURE); 3663 3664 case DDI_DMA_NORESOURCES: 3665 bioerror(bp, 0); 3666 return (DDI_FAILURE); 3667 3668 default: 3669 con_log(CL_ANN, (CE_PANIC, "ddi_dma_alloc_handle: " 3670 "impossible result (0x%x)", i)); 3671 bioerror(bp, EFAULT); 3672 return (DDI_FAILURE); 3673 } 3674 } 3675 3676 i = ddi_dma_buf_bind_handle(acmd->cmd_dmahandle, bp, dma_flags, 3677 cb, 0, &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies); 3678 3679 switch (i) { 3680 case DDI_DMA_PARTIAL_MAP: 3681 if ((dma_flags & DDI_DMA_PARTIAL) == 0) { 3682 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: " 3683 "DDI_DMA_PARTIAL_MAP impossible")); 3684 goto no_dma_cookies; 3685 } 3686 3687 if (ddi_dma_numwin(acmd->cmd_dmahandle, &acmd->cmd_nwin) == 3688 DDI_FAILURE) { 3689 con_log(CL_ANN, (CE_PANIC, "ddi_dma_numwin failed")); 3690 goto no_dma_cookies; 3691 } 3692 3693 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin, 3694 &acmd->cmd_dma_offset, &acmd->cmd_dma_len, 3695 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) == 3696 DDI_FAILURE) { 3697 3698 con_log(CL_ANN, (CE_PANIC, "ddi_dma_getwin failed")); 3699 goto no_dma_cookies; 3700 } 3701 3702 goto get_dma_cookies; 3703 case DDI_DMA_MAPPED: 3704 acmd->cmd_nwin = 1; 3705 acmd->cmd_dma_len = 0; 3706 acmd->cmd_dma_offset = 0; 3707 3708 get_dma_cookies: 3709 i = 0; 3710 acmd->cmd_dmacount = 0; 3711 for (;;) { 3712 acmd->cmd_dmacount += 3713 acmd->cmd_dmacookies[i++].dmac_size; 3714 3715 if (i == instance->max_num_sge || 3716 i == acmd->cmd_ncookies) 3717 break; 3718 3719 ddi_dma_nextcookie(acmd->cmd_dmahandle, 3720 &acmd->cmd_dmacookies[i]); 3721 } 3722 3723 acmd->cmd_cookie = i; 3724 acmd->cmd_cookiecnt = i; 3725 3726 acmd->cmd_flags |= CFLAG_DMAVALID; 3727 3728 if (bp->b_bcount >= acmd->cmd_dmacount) { 3729 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount; 3730 } else { 3731 pkt->pkt_resid = 0; 3732 } 3733 3734 return (DDI_SUCCESS); 3735 case DDI_DMA_NORESOURCES: 3736 bioerror(bp, 0); 3737 break; 3738 case DDI_DMA_NOMAPPING: 3739 bioerror(bp, EFAULT); 3740 break; 3741 case DDI_DMA_TOOBIG: 3742 bioerror(bp, EINVAL); 3743 break; 3744 case DDI_DMA_INUSE: 3745 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle:" 3746 " DDI_DMA_INUSE impossible")); 3747 break; 3748 default: 3749 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: " 3750 "impossible result (0x%x)", i)); 3751 break; 3752 } 3753 3754 no_dma_cookies: 3755 ddi_dma_free_handle(&acmd->cmd_dmahandle); 3756 acmd->cmd_dmahandle = NULL; 3757 acmd->cmd_flags &= ~CFLAG_DMAVALID; 3758 return (DDI_FAILURE); 3759 } 3760 3761 /* 3762 * mrsas_dma_move(struct mrsas_instance *, struct scsi_pkt *, struct buf *) 3763 * 3764 * move dma resources to next dma window 3765 * 3766 */ 3767 static int 3768 mrsas_dma_move(struct mrsas_instance *instance, struct scsi_pkt *pkt, 3769 struct buf *bp) 3770 { 3771 int i = 0; 3772 3773 struct scsa_cmd *acmd = PKT2CMD(pkt); 3774 3775 /* 3776 * If there are no more cookies remaining in this window, 3777 * must move to the next window first. 3778 */ 3779 if (acmd->cmd_cookie == acmd->cmd_ncookies) { 3780 if (acmd->cmd_curwin == acmd->cmd_nwin && acmd->cmd_nwin == 1) { 3781 return (DDI_SUCCESS); 3782 } 3783 3784 /* at last window, cannot move */ 3785 if (++acmd->cmd_curwin >= acmd->cmd_nwin) { 3786 return (DDI_FAILURE); 3787 } 3788 3789 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin, 3790 &acmd->cmd_dma_offset, &acmd->cmd_dma_len, 3791 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) == 3792 DDI_FAILURE) { 3793 return (DDI_FAILURE); 3794 } 3795 3796 acmd->cmd_cookie = 0; 3797 } else { 3798 /* still more cookies in this window - get the next one */ 3799 ddi_dma_nextcookie(acmd->cmd_dmahandle, 3800 &acmd->cmd_dmacookies[0]); 3801 } 3802 3803 /* get remaining cookies in this window, up to our maximum */ 3804 for (;;) { 3805 acmd->cmd_dmacount += acmd->cmd_dmacookies[i++].dmac_size; 3806 acmd->cmd_cookie++; 3807 3808 if (i == instance->max_num_sge || 3809 acmd->cmd_cookie == acmd->cmd_ncookies) { 3810 break; 3811 } 3812 3813 ddi_dma_nextcookie(acmd->cmd_dmahandle, 3814 &acmd->cmd_dmacookies[i]); 3815 } 3816 3817 acmd->cmd_cookiecnt = i; 3818 3819 if (bp->b_bcount >= acmd->cmd_dmacount) { 3820 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount; 3821 } else { 3822 pkt->pkt_resid = 0; 3823 } 3824 3825 return (DDI_SUCCESS); 3826 } 3827 3828 /* 3829 * build_cmd 3830 */ 3831 static struct mrsas_cmd * 3832 build_cmd(struct mrsas_instance *instance, struct scsi_address *ap, 3833 struct scsi_pkt *pkt, uchar_t *cmd_done) 3834 { 3835 uint16_t flags = 0; 3836 uint32_t i; 3837 uint32_t context; 3838 uint32_t sge_bytes; 3839 ddi_acc_handle_t acc_handle; 3840 struct mrsas_cmd *cmd; 3841 struct mrsas_sge64 *mfi_sgl; 3842 struct mrsas_sge_ieee *mfi_sgl_ieee; 3843 struct scsa_cmd *acmd = PKT2CMD(pkt); 3844 struct mrsas_pthru_frame *pthru; 3845 struct mrsas_io_frame *ldio; 3846 3847 /* find out if this is logical or physical drive command. */ 3848 acmd->islogical = MRDRV_IS_LOGICAL(ap); 3849 acmd->device_id = MAP_DEVICE_ID(instance, ap); 3850 *cmd_done = 0; 3851 3852 /* get the command packet */ 3853 if (!(cmd = get_mfi_pkt(instance))) { 3854 DTRACE_PROBE2(build_cmd_mfi_err, uint16_t, 3855 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 3856 return (NULL); 3857 } 3858 3859 cmd->retry_count_for_ocr = 0; 3860 3861 acc_handle = cmd->frame_dma_obj.acc_handle; 3862 3863 /* Clear the frame buffer and assign back the context id */ 3864 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3865 ddi_put32(acc_handle, &cmd->frame->hdr.context, cmd->index); 3866 3867 cmd->pkt = pkt; 3868 cmd->cmd = acmd; 3869 DTRACE_PROBE3(build_cmds, uint8_t, pkt->pkt_cdbp[0], 3870 ulong_t, acmd->cmd_dmacount, ulong_t, acmd->cmd_dma_len); 3871 3872 /* lets get the command directions */ 3873 if (acmd->cmd_flags & CFLAG_DMASEND) { 3874 flags = MFI_FRAME_DIR_WRITE; 3875 3876 if (acmd->cmd_flags & CFLAG_CONSISTENT) { 3877 (void) ddi_dma_sync(acmd->cmd_dmahandle, 3878 acmd->cmd_dma_offset, acmd->cmd_dma_len, 3879 DDI_DMA_SYNC_FORDEV); 3880 } 3881 } else if (acmd->cmd_flags & ~CFLAG_DMASEND) { 3882 flags = MFI_FRAME_DIR_READ; 3883 3884 if (acmd->cmd_flags & CFLAG_CONSISTENT) { 3885 (void) ddi_dma_sync(acmd->cmd_dmahandle, 3886 acmd->cmd_dma_offset, acmd->cmd_dma_len, 3887 DDI_DMA_SYNC_FORCPU); 3888 } 3889 } else { 3890 flags = MFI_FRAME_DIR_NONE; 3891 } 3892 3893 if (instance->flag_ieee) { 3894 flags |= MFI_FRAME_IEEE; 3895 } 3896 flags |= MFI_FRAME_SGL64; 3897 3898 switch (pkt->pkt_cdbp[0]) { 3899 3900 /* 3901 * case SCMD_SYNCHRONIZE_CACHE: 3902 * flush_cache(instance); 3903 * return_mfi_pkt(instance, cmd); 3904 * *cmd_done = 1; 3905 * 3906 * return (NULL); 3907 */ 3908 3909 case SCMD_READ: 3910 case SCMD_WRITE: 3911 case SCMD_READ_G1: 3912 case SCMD_WRITE_G1: 3913 if (acmd->islogical) { 3914 ldio = (struct mrsas_io_frame *)cmd->frame; 3915 3916 /* 3917 * preare the Logical IO frame: 3918 * 2nd bit is zero for all read cmds 3919 */ 3920 ddi_put8(acc_handle, &ldio->cmd, 3921 (pkt->pkt_cdbp[0] & 0x02) ? MFI_CMD_OP_LD_WRITE 3922 : MFI_CMD_OP_LD_READ); 3923 ddi_put8(acc_handle, &ldio->cmd_status, 0x0); 3924 ddi_put8(acc_handle, &ldio->scsi_status, 0x0); 3925 ddi_put8(acc_handle, &ldio->target_id, acmd->device_id); 3926 ddi_put16(acc_handle, &ldio->timeout, 0); 3927 ddi_put8(acc_handle, &ldio->reserved_0, 0); 3928 ddi_put16(acc_handle, &ldio->pad_0, 0); 3929 ddi_put16(acc_handle, &ldio->flags, flags); 3930 3931 /* Initialize sense Information */ 3932 bzero(cmd->sense, SENSE_LENGTH); 3933 ddi_put8(acc_handle, &ldio->sense_len, SENSE_LENGTH); 3934 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_hi, 0); 3935 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_lo, 3936 cmd->sense_phys_addr); 3937 ddi_put32(acc_handle, &ldio->start_lba_hi, 0); 3938 ddi_put8(acc_handle, &ldio->access_byte, 3939 (acmd->cmd_cdblen != 6) ? pkt->pkt_cdbp[1] : 0); 3940 ddi_put8(acc_handle, &ldio->sge_count, 3941 acmd->cmd_cookiecnt); 3942 if (instance->flag_ieee) { 3943 mfi_sgl_ieee = 3944 (struct mrsas_sge_ieee *)&ldio->sgl; 3945 } else { 3946 mfi_sgl = (struct mrsas_sge64 *)&ldio->sgl; 3947 } 3948 3949 context = ddi_get32(acc_handle, &ldio->context); 3950 3951 if (acmd->cmd_cdblen == CDB_GROUP0) { 3952 ddi_put32(acc_handle, &ldio->lba_count, ( 3953 (uint16_t)(pkt->pkt_cdbp[4]))); 3954 3955 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 3956 ((uint32_t)(pkt->pkt_cdbp[3])) | 3957 ((uint32_t)(pkt->pkt_cdbp[2]) << 8) | 3958 ((uint32_t)((pkt->pkt_cdbp[1]) & 0x1F) 3959 << 16))); 3960 } else if (acmd->cmd_cdblen == CDB_GROUP1) { 3961 ddi_put32(acc_handle, &ldio->lba_count, ( 3962 ((uint16_t)(pkt->pkt_cdbp[8])) | 3963 ((uint16_t)(pkt->pkt_cdbp[7]) << 8))); 3964 3965 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 3966 ((uint32_t)(pkt->pkt_cdbp[5])) | 3967 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) | 3968 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) | 3969 ((uint32_t)(pkt->pkt_cdbp[2]) << 24))); 3970 } else if (acmd->cmd_cdblen == CDB_GROUP2) { 3971 ddi_put32(acc_handle, &ldio->lba_count, ( 3972 ((uint16_t)(pkt->pkt_cdbp[9])) | 3973 ((uint16_t)(pkt->pkt_cdbp[8]) << 8) | 3974 ((uint16_t)(pkt->pkt_cdbp[7]) << 16) | 3975 ((uint16_t)(pkt->pkt_cdbp[6]) << 24))); 3976 3977 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 3978 ((uint32_t)(pkt->pkt_cdbp[5])) | 3979 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) | 3980 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) | 3981 ((uint32_t)(pkt->pkt_cdbp[2]) << 24))); 3982 } else if (acmd->cmd_cdblen == CDB_GROUP3) { 3983 ddi_put32(acc_handle, &ldio->lba_count, ( 3984 ((uint16_t)(pkt->pkt_cdbp[13])) | 3985 ((uint16_t)(pkt->pkt_cdbp[12]) << 8) | 3986 ((uint16_t)(pkt->pkt_cdbp[11]) << 16) | 3987 ((uint16_t)(pkt->pkt_cdbp[10]) << 24))); 3988 3989 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 3990 ((uint32_t)(pkt->pkt_cdbp[9])) | 3991 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) | 3992 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) | 3993 ((uint32_t)(pkt->pkt_cdbp[6]) << 24))); 3994 3995 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 3996 ((uint32_t)(pkt->pkt_cdbp[5])) | 3997 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) | 3998 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) | 3999 ((uint32_t)(pkt->pkt_cdbp[2]) << 24))); 4000 } 4001 4002 break; 4003 } 4004 /* fall through For all non-rd/wr cmds */ 4005 default: 4006 4007 switch (pkt->pkt_cdbp[0]) { 4008 case SCMD_MODE_SENSE: 4009 case SCMD_MODE_SENSE_G1: { 4010 union scsi_cdb *cdbp; 4011 uint16_t page_code; 4012 4013 cdbp = (void *)pkt->pkt_cdbp; 4014 page_code = (uint16_t)cdbp->cdb_un.sg.scsi[0]; 4015 switch (page_code) { 4016 case 0x3: 4017 case 0x4: 4018 (void) mrsas_mode_sense_build(pkt); 4019 return_mfi_pkt(instance, cmd); 4020 *cmd_done = 1; 4021 return (NULL); 4022 } 4023 break; 4024 } 4025 default: 4026 break; 4027 } 4028 4029 pthru = (struct mrsas_pthru_frame *)cmd->frame; 4030 4031 /* prepare the DCDB frame */ 4032 ddi_put8(acc_handle, &pthru->cmd, (acmd->islogical) ? 4033 MFI_CMD_OP_LD_SCSI : MFI_CMD_OP_PD_SCSI); 4034 ddi_put8(acc_handle, &pthru->cmd_status, 0x0); 4035 ddi_put8(acc_handle, &pthru->scsi_status, 0x0); 4036 ddi_put8(acc_handle, &pthru->target_id, acmd->device_id); 4037 ddi_put8(acc_handle, &pthru->lun, 0); 4038 ddi_put8(acc_handle, &pthru->cdb_len, acmd->cmd_cdblen); 4039 ddi_put16(acc_handle, &pthru->timeout, 0); 4040 ddi_put16(acc_handle, &pthru->flags, flags); 4041 ddi_put32(acc_handle, &pthru->data_xfer_len, 4042 acmd->cmd_dmacount); 4043 ddi_put8(acc_handle, &pthru->sge_count, acmd->cmd_cookiecnt); 4044 if (instance->flag_ieee) { 4045 mfi_sgl_ieee = (struct mrsas_sge_ieee *)&pthru->sgl; 4046 } else { 4047 mfi_sgl = (struct mrsas_sge64 *)&pthru->sgl; 4048 } 4049 4050 bzero(cmd->sense, SENSE_LENGTH); 4051 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH); 4052 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0); 4053 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo, 4054 cmd->sense_phys_addr); 4055 4056 context = ddi_get32(acc_handle, &pthru->context); 4057 ddi_rep_put8(acc_handle, (uint8_t *)pkt->pkt_cdbp, 4058 (uint8_t *)pthru->cdb, acmd->cmd_cdblen, DDI_DEV_AUTOINCR); 4059 4060 break; 4061 } 4062 #ifdef lint 4063 context = context; 4064 #endif 4065 /* prepare the scatter-gather list for the firmware */ 4066 if (instance->flag_ieee) { 4067 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl_ieee++) { 4068 ddi_put64(acc_handle, &mfi_sgl_ieee->phys_addr, 4069 acmd->cmd_dmacookies[i].dmac_laddress); 4070 ddi_put32(acc_handle, &mfi_sgl_ieee->length, 4071 acmd->cmd_dmacookies[i].dmac_size); 4072 } 4073 sge_bytes = sizeof (struct mrsas_sge_ieee)*acmd->cmd_cookiecnt; 4074 } else { 4075 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl++) { 4076 ddi_put64(acc_handle, &mfi_sgl->phys_addr, 4077 acmd->cmd_dmacookies[i].dmac_laddress); 4078 ddi_put32(acc_handle, &mfi_sgl->length, 4079 acmd->cmd_dmacookies[i].dmac_size); 4080 } 4081 sge_bytes = sizeof (struct mrsas_sge64)*acmd->cmd_cookiecnt; 4082 } 4083 4084 cmd->frame_count = (sge_bytes / MRMFI_FRAME_SIZE) + 4085 ((sge_bytes % MRMFI_FRAME_SIZE) ? 1 : 0) + 1; 4086 4087 if (cmd->frame_count >= 8) { 4088 cmd->frame_count = 8; 4089 } 4090 4091 return (cmd); 4092 } 4093 4094 /* 4095 * issue_mfi_pthru 4096 */ 4097 static int 4098 issue_mfi_pthru(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 4099 struct mrsas_cmd *cmd, int mode) 4100 { 4101 void *ubuf; 4102 uint32_t kphys_addr = 0; 4103 uint32_t xferlen = 0; 4104 uint_t model; 4105 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 4106 dma_obj_t pthru_dma_obj; 4107 struct mrsas_pthru_frame *kpthru; 4108 struct mrsas_pthru_frame *pthru; 4109 int i; 4110 pthru = &cmd->frame->pthru; 4111 kpthru = (struct mrsas_pthru_frame *)&ioctl->frame[0]; 4112 4113 if (instance->adapterresetinprogress) { 4114 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_pthru: Reset flag set, " 4115 "returning mfi_pkt and setting TRAN_BUSY\n")); 4116 return (DDI_FAILURE); 4117 } 4118 model = ddi_model_convert_from(mode & FMODELS); 4119 if (model == DDI_MODEL_ILP32) { 4120 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_pthru: DDI_MODEL_LP32")); 4121 4122 xferlen = kpthru->sgl.sge32[0].length; 4123 4124 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr; 4125 } else { 4126 #ifdef _ILP32 4127 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_pthru: DDI_MODEL_LP32")); 4128 xferlen = kpthru->sgl.sge32[0].length; 4129 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr; 4130 #else 4131 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_pthru: DDI_MODEL_LP64")); 4132 xferlen = kpthru->sgl.sge64[0].length; 4133 ubuf = (void *)(ulong_t)kpthru->sgl.sge64[0].phys_addr; 4134 #endif 4135 } 4136 4137 if (xferlen) { 4138 /* means IOCTL requires DMA */ 4139 /* allocate the data transfer buffer */ 4140 pthru_dma_obj.size = xferlen; 4141 pthru_dma_obj.dma_attr = mrsas_generic_dma_attr; 4142 pthru_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 4143 pthru_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 4144 pthru_dma_obj.dma_attr.dma_attr_sgllen = 1; 4145 pthru_dma_obj.dma_attr.dma_attr_align = 1; 4146 4147 /* allocate kernel buffer for DMA */ 4148 if (mrsas_alloc_dma_obj(instance, &pthru_dma_obj, 4149 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 4150 con_log(CL_ANN, (CE_WARN, "issue_mfi_pthru: " 4151 "could not allocate data transfer buffer.")); 4152 return (DDI_FAILURE); 4153 } 4154 (void) memset(pthru_dma_obj.buffer, 0, xferlen); 4155 4156 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 4157 if (kpthru->flags & MFI_FRAME_DIR_WRITE) { 4158 for (i = 0; i < xferlen; i++) { 4159 if (ddi_copyin((uint8_t *)ubuf+i, 4160 (uint8_t *)pthru_dma_obj.buffer+i, 4161 1, mode)) { 4162 con_log(CL_ANN, (CE_WARN, 4163 "issue_mfi_pthru : " 4164 "copy from user space failed")); 4165 return (DDI_FAILURE); 4166 } 4167 } 4168 } 4169 4170 kphys_addr = pthru_dma_obj.dma_cookie[0].dmac_address; 4171 } 4172 4173 ddi_put8(acc_handle, &pthru->cmd, kpthru->cmd); 4174 ddi_put8(acc_handle, &pthru->sense_len, 0); 4175 ddi_put8(acc_handle, &pthru->cmd_status, 0); 4176 ddi_put8(acc_handle, &pthru->scsi_status, 0); 4177 ddi_put8(acc_handle, &pthru->target_id, kpthru->target_id); 4178 ddi_put8(acc_handle, &pthru->lun, kpthru->lun); 4179 ddi_put8(acc_handle, &pthru->cdb_len, kpthru->cdb_len); 4180 ddi_put8(acc_handle, &pthru->sge_count, kpthru->sge_count); 4181 ddi_put16(acc_handle, &pthru->timeout, kpthru->timeout); 4182 ddi_put32(acc_handle, &pthru->data_xfer_len, kpthru->data_xfer_len); 4183 4184 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0); 4185 /* pthru->sense_buf_phys_addr_lo = cmd->sense_phys_addr; */ 4186 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo, 0); 4187 4188 ddi_rep_put8(acc_handle, (uint8_t *)kpthru->cdb, (uint8_t *)pthru->cdb, 4189 pthru->cdb_len, DDI_DEV_AUTOINCR); 4190 4191 ddi_put16(acc_handle, &pthru->flags, kpthru->flags & ~MFI_FRAME_SGL64); 4192 ddi_put32(acc_handle, &pthru->sgl.sge32[0].length, xferlen); 4193 ddi_put32(acc_handle, &pthru->sgl.sge32[0].phys_addr, kphys_addr); 4194 4195 cmd->sync_cmd = MRSAS_TRUE; 4196 cmd->frame_count = 1; 4197 4198 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 4199 con_log(CL_ANN, (CE_WARN, 4200 "issue_mfi_pthru: fw_ioctl failed")); 4201 } else { 4202 if (xferlen && kpthru->flags & MFI_FRAME_DIR_READ) { 4203 for (i = 0; i < xferlen; i++) { 4204 if (ddi_copyout( 4205 (uint8_t *)pthru_dma_obj.buffer+i, 4206 (uint8_t *)ubuf+i, 1, mode)) { 4207 con_log(CL_ANN, (CE_WARN, 4208 "issue_mfi_pthru : " 4209 "copy to user space failed")); 4210 return (DDI_FAILURE); 4211 } 4212 } 4213 } 4214 } 4215 4216 kpthru->cmd_status = ddi_get8(acc_handle, &pthru->cmd_status); 4217 kpthru->scsi_status = ddi_get8(acc_handle, &pthru->scsi_status); 4218 4219 con_log(CL_ANN, (CE_NOTE, "issue_mfi_pthru: cmd_status %x, " 4220 "scsi_status %x", kpthru->cmd_status, kpthru->scsi_status)); 4221 DTRACE_PROBE3(issue_pthru, uint8_t, kpthru->cmd, uint8_t, 4222 kpthru->cmd_status, uint8_t, kpthru->scsi_status); 4223 4224 if (xferlen) { 4225 /* free kernel buffer */ 4226 if (mrsas_free_dma_obj(instance, pthru_dma_obj) != DDI_SUCCESS) 4227 return (DDI_FAILURE); 4228 } 4229 4230 return (DDI_SUCCESS); 4231 } 4232 4233 /* 4234 * issue_mfi_dcmd 4235 */ 4236 static int 4237 issue_mfi_dcmd(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 4238 struct mrsas_cmd *cmd, int mode) 4239 { 4240 void *ubuf; 4241 uint32_t kphys_addr = 0; 4242 uint32_t xferlen = 0; 4243 uint32_t model; 4244 dma_obj_t dcmd_dma_obj; 4245 struct mrsas_dcmd_frame *kdcmd; 4246 struct mrsas_dcmd_frame *dcmd; 4247 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 4248 int i; 4249 dcmd = &cmd->frame->dcmd; 4250 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0]; 4251 if (instance->adapterresetinprogress) { 4252 con_log(CL_ANN1, (CE_NOTE, "Reset flag set, " 4253 "returning mfi_pkt and setting TRAN_BUSY\n")); 4254 return (DDI_FAILURE); 4255 } 4256 model = ddi_model_convert_from(mode & FMODELS); 4257 if (model == DDI_MODEL_ILP32) { 4258 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_dcmd: DDI_MODEL_ILP32")); 4259 4260 xferlen = kdcmd->sgl.sge32[0].length; 4261 4262 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 4263 } else { 4264 #ifdef _ILP32 4265 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_dcmd: DDI_MODEL_ILP32")); 4266 xferlen = kdcmd->sgl.sge32[0].length; 4267 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 4268 #else 4269 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_dcmd: DDI_MODEL_LP64")); 4270 xferlen = kdcmd->sgl.sge64[0].length; 4271 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr; 4272 #endif 4273 } 4274 if (xferlen) { 4275 /* means IOCTL requires DMA */ 4276 /* allocate the data transfer buffer */ 4277 dcmd_dma_obj.size = xferlen; 4278 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr; 4279 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 4280 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 4281 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1; 4282 dcmd_dma_obj.dma_attr.dma_attr_align = 1; 4283 4284 /* allocate kernel buffer for DMA */ 4285 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj, 4286 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 4287 con_log(CL_ANN, (CE_WARN, "issue_mfi_dcmd: " 4288 "could not allocate data transfer buffer.")); 4289 return (DDI_FAILURE); 4290 } 4291 (void) memset(dcmd_dma_obj.buffer, 0, xferlen); 4292 4293 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 4294 if (kdcmd->flags & MFI_FRAME_DIR_WRITE) { 4295 for (i = 0; i < xferlen; i++) { 4296 if (ddi_copyin((uint8_t *)ubuf + i, 4297 (uint8_t *)dcmd_dma_obj.buffer + i, 4298 1, mode)) { 4299 con_log(CL_ANN, (CE_WARN, 4300 "issue_mfi_dcmd : " 4301 "copy from user space failed")); 4302 return (DDI_FAILURE); 4303 } 4304 } 4305 } 4306 4307 kphys_addr = dcmd_dma_obj.dma_cookie[0].dmac_address; 4308 } 4309 4310 ddi_put8(acc_handle, &dcmd->cmd, kdcmd->cmd); 4311 ddi_put8(acc_handle, &dcmd->cmd_status, 0); 4312 ddi_put8(acc_handle, &dcmd->sge_count, kdcmd->sge_count); 4313 ddi_put16(acc_handle, &dcmd->timeout, kdcmd->timeout); 4314 ddi_put32(acc_handle, &dcmd->data_xfer_len, kdcmd->data_xfer_len); 4315 ddi_put32(acc_handle, &dcmd->opcode, kdcmd->opcode); 4316 4317 ddi_rep_put8(acc_handle, (uint8_t *)kdcmd->mbox.b, 4318 (uint8_t *)dcmd->mbox.b, DCMD_MBOX_SZ, DDI_DEV_AUTOINCR); 4319 4320 ddi_put16(acc_handle, &dcmd->flags, kdcmd->flags & ~MFI_FRAME_SGL64); 4321 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].length, xferlen); 4322 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].phys_addr, kphys_addr); 4323 4324 cmd->sync_cmd = MRSAS_TRUE; 4325 cmd->frame_count = 1; 4326 4327 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 4328 con_log(CL_ANN, (CE_WARN, "issue_mfi_dcmd: fw_ioctl failed")); 4329 } else { 4330 if (xferlen && (kdcmd->flags & MFI_FRAME_DIR_READ)) { 4331 for (i = 0; i < xferlen; i++) { 4332 if (ddi_copyout( 4333 (uint8_t *)dcmd_dma_obj.buffer + i, 4334 (uint8_t *)ubuf + i, 4335 1, mode)) { 4336 con_log(CL_ANN, (CE_WARN, 4337 "issue_mfi_dcmd : " 4338 "copy to user space failed")); 4339 return (DDI_FAILURE); 4340 } 4341 } 4342 } 4343 } 4344 4345 kdcmd->cmd_status = ddi_get8(acc_handle, &dcmd->cmd_status); 4346 DTRACE_PROBE3(issue_dcmd, uint32_t, kdcmd->opcode, uint8_t, 4347 kdcmd->cmd, uint8_t, kdcmd->cmd_status); 4348 4349 if (xferlen) { 4350 /* free kernel buffer */ 4351 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS) 4352 return (DDI_FAILURE); 4353 } 4354 4355 return (DDI_SUCCESS); 4356 } 4357 4358 /* 4359 * issue_mfi_smp 4360 */ 4361 static int 4362 issue_mfi_smp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 4363 struct mrsas_cmd *cmd, int mode) 4364 { 4365 void *request_ubuf; 4366 void *response_ubuf; 4367 uint32_t request_xferlen = 0; 4368 uint32_t response_xferlen = 0; 4369 uint_t model; 4370 dma_obj_t request_dma_obj; 4371 dma_obj_t response_dma_obj; 4372 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 4373 struct mrsas_smp_frame *ksmp; 4374 struct mrsas_smp_frame *smp; 4375 struct mrsas_sge32 *sge32; 4376 #ifndef _ILP32 4377 struct mrsas_sge64 *sge64; 4378 #endif 4379 int i; 4380 uint64_t tmp_sas_addr; 4381 4382 smp = &cmd->frame->smp; 4383 ksmp = (struct mrsas_smp_frame *)&ioctl->frame[0]; 4384 4385 if (instance->adapterresetinprogress) { 4386 con_log(CL_ANN1, (CE_NOTE, "Reset flag set, " 4387 "returning mfi_pkt and setting TRAN_BUSY\n")); 4388 return (DDI_FAILURE); 4389 } 4390 model = ddi_model_convert_from(mode & FMODELS); 4391 if (model == DDI_MODEL_ILP32) { 4392 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: DDI_MODEL_ILP32")); 4393 4394 sge32 = &ksmp->sgl[0].sge32[0]; 4395 response_xferlen = sge32[0].length; 4396 request_xferlen = sge32[1].length; 4397 con_log(CL_ANN, (CE_NOTE, "issue_mfi_smp: " 4398 "response_xferlen = %x, request_xferlen = %x", 4399 response_xferlen, request_xferlen)); 4400 4401 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr; 4402 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr; 4403 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: " 4404 "response_ubuf = %p, request_ubuf = %p", 4405 response_ubuf, request_ubuf)); 4406 } else { 4407 #ifdef _ILP32 4408 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: DDI_MODEL_ILP32")); 4409 4410 sge32 = &ksmp->sgl[0].sge32[0]; 4411 response_xferlen = sge32[0].length; 4412 request_xferlen = sge32[1].length; 4413 con_log(CL_ANN, (CE_NOTE, "issue_mfi_smp: " 4414 "response_xferlen = %x, request_xferlen = %x", 4415 response_xferlen, request_xferlen)); 4416 4417 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr; 4418 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr; 4419 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: " 4420 "response_ubuf = %p, request_ubuf = %p", 4421 response_ubuf, request_ubuf)); 4422 #else 4423 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: DDI_MODEL_LP64")); 4424 4425 sge64 = &ksmp->sgl[0].sge64[0]; 4426 response_xferlen = sge64[0].length; 4427 request_xferlen = sge64[1].length; 4428 4429 response_ubuf = (void *)(ulong_t)sge64[0].phys_addr; 4430 request_ubuf = (void *)(ulong_t)sge64[1].phys_addr; 4431 #endif 4432 } 4433 if (request_xferlen) { 4434 /* means IOCTL requires DMA */ 4435 /* allocate the data transfer buffer */ 4436 request_dma_obj.size = request_xferlen; 4437 request_dma_obj.dma_attr = mrsas_generic_dma_attr; 4438 request_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 4439 request_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 4440 request_dma_obj.dma_attr.dma_attr_sgllen = 1; 4441 request_dma_obj.dma_attr.dma_attr_align = 1; 4442 4443 /* allocate kernel buffer for DMA */ 4444 if (mrsas_alloc_dma_obj(instance, &request_dma_obj, 4445 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 4446 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 4447 "could not allocate data transfer buffer.")); 4448 return (DDI_FAILURE); 4449 } 4450 (void) memset(request_dma_obj.buffer, 0, request_xferlen); 4451 4452 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 4453 for (i = 0; i < request_xferlen; i++) { 4454 if (ddi_copyin((uint8_t *)request_ubuf + i, 4455 (uint8_t *)request_dma_obj.buffer + i, 4456 1, mode)) { 4457 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 4458 "copy from user space failed")); 4459 return (DDI_FAILURE); 4460 } 4461 } 4462 } 4463 4464 if (response_xferlen) { 4465 /* means IOCTL requires DMA */ 4466 /* allocate the data transfer buffer */ 4467 response_dma_obj.size = response_xferlen; 4468 response_dma_obj.dma_attr = mrsas_generic_dma_attr; 4469 response_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 4470 response_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 4471 response_dma_obj.dma_attr.dma_attr_sgllen = 1; 4472 response_dma_obj.dma_attr.dma_attr_align = 1; 4473 4474 /* allocate kernel buffer for DMA */ 4475 if (mrsas_alloc_dma_obj(instance, &response_dma_obj, 4476 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 4477 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 4478 "could not allocate data transfer buffer.")); 4479 return (DDI_FAILURE); 4480 } 4481 (void) memset(response_dma_obj.buffer, 0, response_xferlen); 4482 4483 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 4484 for (i = 0; i < response_xferlen; i++) { 4485 if (ddi_copyin((uint8_t *)response_ubuf + i, 4486 (uint8_t *)response_dma_obj.buffer + i, 4487 1, mode)) { 4488 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 4489 "copy from user space failed")); 4490 return (DDI_FAILURE); 4491 } 4492 } 4493 } 4494 4495 ddi_put8(acc_handle, &smp->cmd, ksmp->cmd); 4496 ddi_put8(acc_handle, &smp->cmd_status, 0); 4497 ddi_put8(acc_handle, &smp->connection_status, 0); 4498 ddi_put8(acc_handle, &smp->sge_count, ksmp->sge_count); 4499 /* smp->context = ksmp->context; */ 4500 ddi_put16(acc_handle, &smp->timeout, ksmp->timeout); 4501 ddi_put32(acc_handle, &smp->data_xfer_len, ksmp->data_xfer_len); 4502 4503 bcopy((void *)&ksmp->sas_addr, (void *)&tmp_sas_addr, 4504 sizeof (uint64_t)); 4505 ddi_put64(acc_handle, &smp->sas_addr, tmp_sas_addr); 4506 4507 ddi_put16(acc_handle, &smp->flags, ksmp->flags & ~MFI_FRAME_SGL64); 4508 4509 model = ddi_model_convert_from(mode & FMODELS); 4510 if (model == DDI_MODEL_ILP32) { 4511 con_log(CL_ANN1, (CE_NOTE, 4512 "issue_mfi_smp: DDI_MODEL_ILP32")); 4513 4514 sge32 = &smp->sgl[0].sge32[0]; 4515 ddi_put32(acc_handle, &sge32[0].length, response_xferlen); 4516 ddi_put32(acc_handle, &sge32[0].phys_addr, 4517 response_dma_obj.dma_cookie[0].dmac_address); 4518 ddi_put32(acc_handle, &sge32[1].length, request_xferlen); 4519 ddi_put32(acc_handle, &sge32[1].phys_addr, 4520 request_dma_obj.dma_cookie[0].dmac_address); 4521 } else { 4522 #ifdef _ILP32 4523 con_log(CL_ANN1, (CE_NOTE, 4524 "issue_mfi_smp: DDI_MODEL_ILP32")); 4525 sge32 = &smp->sgl[0].sge32[0]; 4526 ddi_put32(acc_handle, &sge32[0].length, response_xferlen); 4527 ddi_put32(acc_handle, &sge32[0].phys_addr, 4528 response_dma_obj.dma_cookie[0].dmac_address); 4529 ddi_put32(acc_handle, &sge32[1].length, request_xferlen); 4530 ddi_put32(acc_handle, &sge32[1].phys_addr, 4531 request_dma_obj.dma_cookie[0].dmac_address); 4532 #else 4533 con_log(CL_ANN1, (CE_NOTE, 4534 "issue_mfi_smp: DDI_MODEL_LP64")); 4535 sge64 = &smp->sgl[0].sge64[0]; 4536 ddi_put32(acc_handle, &sge64[0].length, response_xferlen); 4537 ddi_put64(acc_handle, &sge64[0].phys_addr, 4538 response_dma_obj.dma_cookie[0].dmac_address); 4539 ddi_put32(acc_handle, &sge64[1].length, request_xferlen); 4540 ddi_put64(acc_handle, &sge64[1].phys_addr, 4541 request_dma_obj.dma_cookie[0].dmac_address); 4542 #endif 4543 } 4544 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp : " 4545 "smp->response_xferlen = %d, smp->request_xferlen = %d " 4546 "smp->data_xfer_len = %d", ddi_get32(acc_handle, &sge32[0].length), 4547 ddi_get32(acc_handle, &sge32[1].length), 4548 ddi_get32(acc_handle, &smp->data_xfer_len))); 4549 4550 cmd->sync_cmd = MRSAS_TRUE; 4551 cmd->frame_count = 1; 4552 4553 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 4554 con_log(CL_ANN, (CE_WARN, 4555 "issue_mfi_smp: fw_ioctl failed")); 4556 } else { 4557 con_log(CL_ANN1, (CE_NOTE, 4558 "issue_mfi_smp: copy to user space")); 4559 4560 if (request_xferlen) { 4561 for (i = 0; i < request_xferlen; i++) { 4562 if (ddi_copyout( 4563 (uint8_t *)request_dma_obj.buffer + 4564 i, (uint8_t *)request_ubuf + i, 4565 1, mode)) { 4566 con_log(CL_ANN, (CE_WARN, 4567 "issue_mfi_smp : copy to user space" 4568 " failed")); 4569 return (DDI_FAILURE); 4570 } 4571 } 4572 } 4573 4574 if (response_xferlen) { 4575 for (i = 0; i < response_xferlen; i++) { 4576 if (ddi_copyout( 4577 (uint8_t *)response_dma_obj.buffer 4578 + i, (uint8_t *)response_ubuf 4579 + i, 1, mode)) { 4580 con_log(CL_ANN, (CE_WARN, 4581 "issue_mfi_smp : copy to " 4582 "user space failed")); 4583 return (DDI_FAILURE); 4584 } 4585 } 4586 } 4587 } 4588 4589 ksmp->cmd_status = ddi_get8(acc_handle, &smp->cmd_status); 4590 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: smp->cmd_status = %d", 4591 ddi_get8(acc_handle, &smp->cmd_status))); 4592 DTRACE_PROBE2(issue_smp, uint8_t, ksmp->cmd, uint8_t, ksmp->cmd_status); 4593 4594 if (request_xferlen) { 4595 /* free kernel buffer */ 4596 if (mrsas_free_dma_obj(instance, request_dma_obj) != 4597 DDI_SUCCESS) 4598 return (DDI_FAILURE); 4599 } 4600 4601 if (response_xferlen) { 4602 /* free kernel buffer */ 4603 if (mrsas_free_dma_obj(instance, response_dma_obj) != 4604 DDI_SUCCESS) 4605 return (DDI_FAILURE); 4606 } 4607 4608 return (DDI_SUCCESS); 4609 } 4610 4611 /* 4612 * issue_mfi_stp 4613 */ 4614 static int 4615 issue_mfi_stp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 4616 struct mrsas_cmd *cmd, int mode) 4617 { 4618 void *fis_ubuf; 4619 void *data_ubuf; 4620 uint32_t fis_xferlen = 0; 4621 uint32_t data_xferlen = 0; 4622 uint_t model; 4623 dma_obj_t fis_dma_obj; 4624 dma_obj_t data_dma_obj; 4625 struct mrsas_stp_frame *kstp; 4626 struct mrsas_stp_frame *stp; 4627 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 4628 int i; 4629 4630 stp = &cmd->frame->stp; 4631 kstp = (struct mrsas_stp_frame *)&ioctl->frame[0]; 4632 4633 if (instance->adapterresetinprogress) { 4634 con_log(CL_ANN1, (CE_NOTE, "Reset flag set, " 4635 "returning mfi_pkt and setting TRAN_BUSY\n")); 4636 return (DDI_FAILURE); 4637 } 4638 model = ddi_model_convert_from(mode & FMODELS); 4639 if (model == DDI_MODEL_ILP32) { 4640 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_stp: DDI_MODEL_ILP32")); 4641 4642 fis_xferlen = kstp->sgl.sge32[0].length; 4643 data_xferlen = kstp->sgl.sge32[1].length; 4644 4645 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr; 4646 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr; 4647 } 4648 else 4649 { 4650 #ifdef _ILP32 4651 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_stp: DDI_MODEL_ILP32")); 4652 4653 fis_xferlen = kstp->sgl.sge32[0].length; 4654 data_xferlen = kstp->sgl.sge32[1].length; 4655 4656 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr; 4657 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr; 4658 #else 4659 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_stp: DDI_MODEL_LP64")); 4660 4661 fis_xferlen = kstp->sgl.sge64[0].length; 4662 data_xferlen = kstp->sgl.sge64[1].length; 4663 4664 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge64[0].phys_addr; 4665 data_ubuf = (void *)(ulong_t)kstp->sgl.sge64[1].phys_addr; 4666 #endif 4667 } 4668 4669 4670 if (fis_xferlen) { 4671 con_log(CL_ANN, (CE_NOTE, "issue_mfi_stp: " 4672 "fis_ubuf = %p fis_xferlen = %x", fis_ubuf, fis_xferlen)); 4673 4674 /* means IOCTL requires DMA */ 4675 /* allocate the data transfer buffer */ 4676 fis_dma_obj.size = fis_xferlen; 4677 fis_dma_obj.dma_attr = mrsas_generic_dma_attr; 4678 fis_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 4679 fis_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 4680 fis_dma_obj.dma_attr.dma_attr_sgllen = 1; 4681 fis_dma_obj.dma_attr.dma_attr_align = 1; 4682 4683 /* allocate kernel buffer for DMA */ 4684 if (mrsas_alloc_dma_obj(instance, &fis_dma_obj, 4685 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 4686 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp : " 4687 "could not allocate data transfer buffer.")); 4688 return (DDI_FAILURE); 4689 } 4690 (void) memset(fis_dma_obj.buffer, 0, fis_xferlen); 4691 4692 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 4693 for (i = 0; i < fis_xferlen; i++) { 4694 if (ddi_copyin((uint8_t *)fis_ubuf + i, 4695 (uint8_t *)fis_dma_obj.buffer + i, 1, mode)) { 4696 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: " 4697 "copy from user space failed")); 4698 return (DDI_FAILURE); 4699 } 4700 } 4701 } 4702 4703 if (data_xferlen) { 4704 con_log(CL_ANN, (CE_NOTE, "issue_mfi_stp: data_ubuf = %p " 4705 "data_xferlen = %x", data_ubuf, data_xferlen)); 4706 4707 /* means IOCTL requires DMA */ 4708 /* allocate the data transfer buffer */ 4709 data_dma_obj.size = data_xferlen; 4710 data_dma_obj.dma_attr = mrsas_generic_dma_attr; 4711 data_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 4712 data_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 4713 data_dma_obj.dma_attr.dma_attr_sgllen = 1; 4714 data_dma_obj.dma_attr.dma_attr_align = 1; 4715 4716 /* allocate kernel buffer for DMA */ 4717 if (mrsas_alloc_dma_obj(instance, &data_dma_obj, 4718 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 4719 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: " 4720 "could not allocate data transfer buffer.")); 4721 return (DDI_FAILURE); 4722 } 4723 (void) memset(data_dma_obj.buffer, 0, data_xferlen); 4724 4725 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 4726 for (i = 0; i < data_xferlen; i++) { 4727 if (ddi_copyin((uint8_t *)data_ubuf + i, 4728 (uint8_t *)data_dma_obj.buffer + i, 1, mode)) { 4729 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: " 4730 "copy from user space failed")); 4731 return (DDI_FAILURE); 4732 } 4733 } 4734 } 4735 4736 ddi_put8(acc_handle, &stp->cmd, kstp->cmd); 4737 ddi_put8(acc_handle, &stp->cmd_status, 0); 4738 ddi_put8(acc_handle, &stp->connection_status, 0); 4739 ddi_put8(acc_handle, &stp->target_id, kstp->target_id); 4740 ddi_put8(acc_handle, &stp->sge_count, kstp->sge_count); 4741 4742 ddi_put16(acc_handle, &stp->timeout, kstp->timeout); 4743 ddi_put32(acc_handle, &stp->data_xfer_len, kstp->data_xfer_len); 4744 4745 ddi_rep_put8(acc_handle, (uint8_t *)kstp->fis, (uint8_t *)stp->fis, 10, 4746 DDI_DEV_AUTOINCR); 4747 4748 ddi_put16(acc_handle, &stp->flags, kstp->flags & ~MFI_FRAME_SGL64); 4749 ddi_put32(acc_handle, &stp->stp_flags, kstp->stp_flags); 4750 ddi_put32(acc_handle, &stp->sgl.sge32[0].length, fis_xferlen); 4751 ddi_put32(acc_handle, &stp->sgl.sge32[0].phys_addr, 4752 fis_dma_obj.dma_cookie[0].dmac_address); 4753 ddi_put32(acc_handle, &stp->sgl.sge32[1].length, data_xferlen); 4754 ddi_put32(acc_handle, &stp->sgl.sge32[1].phys_addr, 4755 data_dma_obj.dma_cookie[0].dmac_address); 4756 4757 cmd->sync_cmd = MRSAS_TRUE; 4758 cmd->frame_count = 1; 4759 4760 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 4761 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: fw_ioctl failed")); 4762 } else { 4763 4764 if (fis_xferlen) { 4765 for (i = 0; i < fis_xferlen; i++) { 4766 if (ddi_copyout( 4767 (uint8_t *)fis_dma_obj.buffer + i, 4768 (uint8_t *)fis_ubuf + i, 1, mode)) { 4769 con_log(CL_ANN, (CE_WARN, 4770 "issue_mfi_stp : copy to " 4771 "user space failed")); 4772 return (DDI_FAILURE); 4773 } 4774 } 4775 } 4776 } 4777 if (data_xferlen) { 4778 for (i = 0; i < data_xferlen; i++) { 4779 if (ddi_copyout( 4780 (uint8_t *)data_dma_obj.buffer + i, 4781 (uint8_t *)data_ubuf + i, 1, mode)) { 4782 con_log(CL_ANN, (CE_WARN, 4783 "issue_mfi_stp : copy to" 4784 " user space failed")); 4785 return (DDI_FAILURE); 4786 } 4787 } 4788 } 4789 4790 kstp->cmd_status = ddi_get8(acc_handle, &stp->cmd_status); 4791 DTRACE_PROBE2(issue_stp, uint8_t, kstp->cmd, uint8_t, kstp->cmd_status); 4792 4793 if (fis_xferlen) { 4794 /* free kernel buffer */ 4795 if (mrsas_free_dma_obj(instance, fis_dma_obj) != DDI_SUCCESS) 4796 return (DDI_FAILURE); 4797 } 4798 4799 if (data_xferlen) { 4800 /* free kernel buffer */ 4801 if (mrsas_free_dma_obj(instance, data_dma_obj) != DDI_SUCCESS) 4802 return (DDI_FAILURE); 4803 } 4804 4805 return (DDI_SUCCESS); 4806 } 4807 4808 /* 4809 * fill_up_drv_ver 4810 */ 4811 static void 4812 fill_up_drv_ver(struct mrsas_drv_ver *dv) 4813 { 4814 (void) memset(dv, 0, sizeof (struct mrsas_drv_ver)); 4815 4816 (void) memcpy(dv->signature, "$LSI LOGIC$", strlen("$LSI LOGIC$")); 4817 (void) memcpy(dv->os_name, "Solaris", strlen("Solaris")); 4818 (void) memcpy(dv->drv_name, "mr_sas", strlen("mr_sas")); 4819 (void) memcpy(dv->drv_ver, MRSAS_VERSION, strlen(MRSAS_VERSION)); 4820 (void) memcpy(dv->drv_rel_date, MRSAS_RELDATE, 4821 strlen(MRSAS_RELDATE)); 4822 } 4823 4824 /* 4825 * handle_drv_ioctl 4826 */ 4827 static int 4828 handle_drv_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 4829 int mode) 4830 { 4831 int i; 4832 int rval = DDI_SUCCESS; 4833 int *props = NULL; 4834 void *ubuf; 4835 4836 uint8_t *pci_conf_buf; 4837 uint32_t xferlen; 4838 uint32_t num_props; 4839 uint_t model; 4840 struct mrsas_dcmd_frame *kdcmd; 4841 struct mrsas_drv_ver dv; 4842 struct mrsas_pci_information pi; 4843 4844 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0]; 4845 4846 model = ddi_model_convert_from(mode & FMODELS); 4847 if (model == DDI_MODEL_ILP32) { 4848 con_log(CL_ANN1, (CE_NOTE, 4849 "handle_drv_ioctl: DDI_MODEL_ILP32")); 4850 4851 xferlen = kdcmd->sgl.sge32[0].length; 4852 4853 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 4854 } else { 4855 #ifdef _ILP32 4856 con_log(CL_ANN1, (CE_NOTE, 4857 "handle_drv_ioctl: DDI_MODEL_ILP32")); 4858 xferlen = kdcmd->sgl.sge32[0].length; 4859 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 4860 #else 4861 con_log(CL_ANN1, (CE_NOTE, 4862 "handle_drv_ioctl: DDI_MODEL_LP64")); 4863 xferlen = kdcmd->sgl.sge64[0].length; 4864 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr; 4865 #endif 4866 } 4867 con_log(CL_ANN1, (CE_NOTE, "handle_drv_ioctl: " 4868 "dataBuf=%p size=%d bytes", ubuf, xferlen)); 4869 4870 switch (kdcmd->opcode) { 4871 case MRSAS_DRIVER_IOCTL_DRIVER_VERSION: 4872 con_log(CL_ANN1, (CE_NOTE, "handle_drv_ioctl: " 4873 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION")); 4874 4875 fill_up_drv_ver(&dv); 4876 4877 if (ddi_copyout(&dv, ubuf, xferlen, mode)) { 4878 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 4879 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION : " 4880 "copy to user space failed")); 4881 kdcmd->cmd_status = 1; 4882 rval = 1; 4883 } else { 4884 kdcmd->cmd_status = 0; 4885 } 4886 break; 4887 case MRSAS_DRIVER_IOCTL_PCI_INFORMATION: 4888 con_log(CL_ANN1, (CE_NOTE, "handle_drv_ioctl: " 4889 "MRSAS_DRIVER_IOCTL_PCI_INFORMAITON")); 4890 4891 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, instance->dip, 4892 0, "reg", &props, &num_props)) { 4893 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 4894 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : " 4895 "ddi_prop_look_int_array failed")); 4896 rval = DDI_FAILURE; 4897 } else { 4898 4899 pi.busNumber = (props[0] >> 16) & 0xFF; 4900 pi.deviceNumber = (props[0] >> 11) & 0x1f; 4901 pi.functionNumber = (props[0] >> 8) & 0x7; 4902 ddi_prop_free((void *)props); 4903 } 4904 4905 pci_conf_buf = (uint8_t *)&pi.pciHeaderInfo; 4906 4907 for (i = 0; i < (sizeof (struct mrsas_pci_information) - 4908 offsetof(struct mrsas_pci_information, pciHeaderInfo)); 4909 i++) { 4910 pci_conf_buf[i] = 4911 pci_config_get8(instance->pci_handle, i); 4912 } 4913 4914 if (ddi_copyout(&pi, ubuf, xferlen, mode)) { 4915 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 4916 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : " 4917 "copy to user space failed")); 4918 kdcmd->cmd_status = 1; 4919 rval = 1; 4920 } else { 4921 kdcmd->cmd_status = 0; 4922 } 4923 break; 4924 default: 4925 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 4926 "invalid driver specific IOCTL opcode = 0x%x", 4927 kdcmd->opcode)); 4928 kdcmd->cmd_status = 1; 4929 rval = DDI_FAILURE; 4930 break; 4931 } 4932 4933 return (rval); 4934 } 4935 4936 /* 4937 * handle_mfi_ioctl 4938 */ 4939 static int 4940 handle_mfi_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 4941 int mode) 4942 { 4943 int rval = DDI_SUCCESS; 4944 4945 struct mrsas_header *hdr; 4946 struct mrsas_cmd *cmd; 4947 4948 cmd = get_mfi_pkt(instance); 4949 4950 if (!cmd) { 4951 con_log(CL_ANN, (CE_WARN, "mr_sas: " 4952 "failed to get a cmd packet")); 4953 DTRACE_PROBE2(mfi_ioctl_err, uint16_t, 4954 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 4955 return (DDI_FAILURE); 4956 } 4957 cmd->retry_count_for_ocr = 0; 4958 4959 /* Clear the frame buffer and assign back the context id */ 4960 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 4961 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 4962 cmd->index); 4963 4964 hdr = (struct mrsas_header *)&ioctl->frame[0]; 4965 4966 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) { 4967 case MFI_CMD_OP_DCMD: 4968 rval = issue_mfi_dcmd(instance, ioctl, cmd, mode); 4969 break; 4970 case MFI_CMD_OP_SMP: 4971 rval = issue_mfi_smp(instance, ioctl, cmd, mode); 4972 break; 4973 case MFI_CMD_OP_STP: 4974 rval = issue_mfi_stp(instance, ioctl, cmd, mode); 4975 break; 4976 case MFI_CMD_OP_LD_SCSI: 4977 case MFI_CMD_OP_PD_SCSI: 4978 rval = issue_mfi_pthru(instance, ioctl, cmd, mode); 4979 break; 4980 default: 4981 con_log(CL_ANN, (CE_WARN, "handle_mfi_ioctl: " 4982 "invalid mfi ioctl hdr->cmd = %d", hdr->cmd)); 4983 rval = DDI_FAILURE; 4984 break; 4985 } 4986 4987 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) 4988 rval = DDI_FAILURE; 4989 4990 return_mfi_pkt(instance, cmd); 4991 4992 return (rval); 4993 } 4994 4995 /* 4996 * AEN 4997 */ 4998 static int 4999 handle_mfi_aen(struct mrsas_instance *instance, struct mrsas_aen *aen) 5000 { 5001 int rval = 0; 5002 5003 rval = register_mfi_aen(instance, instance->aen_seq_num, 5004 aen->class_locale_word); 5005 5006 aen->cmd_status = (uint8_t)rval; 5007 5008 return (rval); 5009 } 5010 5011 static int 5012 register_mfi_aen(struct mrsas_instance *instance, uint32_t seq_num, 5013 uint32_t class_locale_word) 5014 { 5015 int ret_val; 5016 5017 struct mrsas_cmd *cmd, *aen_cmd; 5018 struct mrsas_dcmd_frame *dcmd; 5019 union mrsas_evt_class_locale curr_aen; 5020 union mrsas_evt_class_locale prev_aen; 5021 5022 /* 5023 * If there an AEN pending already (aen_cmd), check if the 5024 * class_locale of that pending AEN is inclusive of the new 5025 * AEN request we currently have. If it is, then we don't have 5026 * to do anything. In other words, whichever events the current 5027 * AEN request is subscribing to, have already been subscribed 5028 * to. 5029 * 5030 * If the old_cmd is _not_ inclusive, then we have to abort 5031 * that command, form a class_locale that is superset of both 5032 * old and current and re-issue to the FW 5033 */ 5034 5035 curr_aen.word = LE_32(class_locale_word); 5036 curr_aen.members.locale = LE_16(curr_aen.members.locale); 5037 aen_cmd = instance->aen_cmd; 5038 if (aen_cmd) { 5039 prev_aen.word = ddi_get32(aen_cmd->frame_dma_obj.acc_handle, 5040 &aen_cmd->frame->dcmd.mbox.w[1]); 5041 prev_aen.word = LE_32(prev_aen.word); 5042 prev_aen.members.locale = LE_16(prev_aen.members.locale); 5043 /* 5044 * A class whose enum value is smaller is inclusive of all 5045 * higher values. If a PROGRESS (= -1) was previously 5046 * registered, then a new registration requests for higher 5047 * classes need not be sent to FW. They are automatically 5048 * included. 5049 * 5050 * Locale numbers don't have such hierarchy. They are bitmap 5051 * values 5052 */ 5053 if ((prev_aen.members.class <= curr_aen.members.class) && 5054 !((prev_aen.members.locale & curr_aen.members.locale) ^ 5055 curr_aen.members.locale)) { 5056 /* 5057 * Previously issued event registration includes 5058 * current request. Nothing to do. 5059 */ 5060 5061 return (0); 5062 } else { 5063 curr_aen.members.locale |= prev_aen.members.locale; 5064 5065 if (prev_aen.members.class < curr_aen.members.class) 5066 curr_aen.members.class = prev_aen.members.class; 5067 5068 ret_val = abort_aen_cmd(instance, aen_cmd); 5069 5070 if (ret_val) { 5071 con_log(CL_ANN, (CE_WARN, "register_mfi_aen: " 5072 "failed to abort prevous AEN command")); 5073 5074 return (ret_val); 5075 } 5076 } 5077 } else { 5078 curr_aen.word = LE_32(class_locale_word); 5079 curr_aen.members.locale = LE_16(curr_aen.members.locale); 5080 } 5081 5082 cmd = get_mfi_pkt(instance); 5083 5084 if (!cmd) { 5085 DTRACE_PROBE2(mfi_aen_err, uint16_t, instance->fw_outstanding, 5086 uint16_t, instance->max_fw_cmds); 5087 return (ENOMEM); 5088 } 5089 cmd->retry_count_for_ocr = 0; 5090 /* Clear the frame buffer and assign back the context id */ 5091 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 5092 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 5093 cmd->index); 5094 5095 dcmd = &cmd->frame->dcmd; 5096 5097 /* for(i = 0; i < DCMD_MBOX_SZ; i++) dcmd->mbox.b[i] = 0; */ 5098 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 5099 5100 (void) memset(instance->mfi_evt_detail_obj.buffer, 0, 5101 sizeof (struct mrsas_evt_detail)); 5102 5103 /* Prepare DCMD for aen registration */ 5104 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 5105 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0); 5106 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1); 5107 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 5108 MFI_FRAME_DIR_READ); 5109 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 5110 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 5111 sizeof (struct mrsas_evt_detail)); 5112 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 5113 MR_DCMD_CTRL_EVENT_WAIT); 5114 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[0], seq_num); 5115 curr_aen.members.locale = LE_16(curr_aen.members.locale); 5116 curr_aen.word = LE_32(curr_aen.word); 5117 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[1], 5118 curr_aen.word); 5119 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr, 5120 instance->mfi_evt_detail_obj.dma_cookie[0].dmac_address); 5121 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length, 5122 sizeof (struct mrsas_evt_detail)); 5123 5124 instance->aen_seq_num = seq_num; 5125 5126 5127 /* 5128 * Store reference to the cmd used to register for AEN. When an 5129 * application wants us to register for AEN, we have to abort this 5130 * cmd and re-register with a new EVENT LOCALE supplied by that app 5131 */ 5132 instance->aen_cmd = cmd; 5133 5134 cmd->frame_count = 1; 5135 5136 /* Issue the aen registration frame */ 5137 /* atomic_add_16 (&instance->fw_outstanding, 1); */ 5138 instance->func_ptr->issue_cmd(cmd, instance); 5139 5140 return (0); 5141 } 5142 5143 static void 5144 display_scsi_inquiry(caddr_t scsi_inq) 5145 { 5146 #define MAX_SCSI_DEVICE_CODE 14 5147 int i; 5148 char inquiry_buf[256] = {0}; 5149 int len; 5150 const char *const scsi_device_types[] = { 5151 "Direct-Access ", 5152 "Sequential-Access", 5153 "Printer ", 5154 "Processor ", 5155 "WORM ", 5156 "CD-ROM ", 5157 "Scanner ", 5158 "Optical Device ", 5159 "Medium Changer ", 5160 "Communications ", 5161 "Unknown ", 5162 "Unknown ", 5163 "Unknown ", 5164 "Enclosure ", 5165 }; 5166 5167 len = 0; 5168 5169 len += snprintf(inquiry_buf + len, 265 - len, " Vendor: "); 5170 for (i = 8; i < 16; i++) { 5171 len += snprintf(inquiry_buf + len, 265 - len, "%c", 5172 scsi_inq[i]); 5173 } 5174 5175 len += snprintf(inquiry_buf + len, 265 - len, " Model: "); 5176 5177 for (i = 16; i < 32; i++) { 5178 len += snprintf(inquiry_buf + len, 265 - len, "%c", 5179 scsi_inq[i]); 5180 } 5181 5182 len += snprintf(inquiry_buf + len, 265 - len, " Rev: "); 5183 5184 for (i = 32; i < 36; i++) { 5185 len += snprintf(inquiry_buf + len, 265 - len, "%c", 5186 scsi_inq[i]); 5187 } 5188 5189 len += snprintf(inquiry_buf + len, 265 - len, "\n"); 5190 5191 5192 i = scsi_inq[0] & 0x1f; 5193 5194 5195 len += snprintf(inquiry_buf + len, 265 - len, " Type: %s ", 5196 i < MAX_SCSI_DEVICE_CODE ? scsi_device_types[i] : 5197 "Unknown "); 5198 5199 5200 len += snprintf(inquiry_buf + len, 265 - len, 5201 " ANSI SCSI revision: %02x", scsi_inq[2] & 0x07); 5202 5203 if ((scsi_inq[2] & 0x07) == 1 && (scsi_inq[3] & 0x0f) == 1) { 5204 len += snprintf(inquiry_buf + len, 265 - len, " CCS\n"); 5205 } else { 5206 len += snprintf(inquiry_buf + len, 265 - len, "\n"); 5207 } 5208 5209 con_log(CL_ANN1, (CE_CONT, inquiry_buf)); 5210 } 5211 5212 static void 5213 io_timeout_checker(void *arg) 5214 { 5215 struct scsi_pkt *pkt; 5216 struct mrsas_instance *instance = arg; 5217 struct mrsas_cmd *cmd = NULL; 5218 struct mrsas_header *hdr; 5219 int time = 0; 5220 int counter = 0; 5221 struct mlist_head *pos, *next; 5222 mlist_t process_list; 5223 5224 instance->timeout_id = (timeout_id_t)-1; 5225 if (instance->adapterresetinprogress == 1) { 5226 con_log(CL_ANN1, (CE_NOTE, "io_timeout_checker" 5227 " reset in progress")); 5228 instance->timeout_id = timeout(io_timeout_checker, 5229 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 5230 return; 5231 } 5232 5233 /* See if this check needs to be in the beginning or last in ISR */ 5234 if (mrsas_initiate_ocr_if_fw_is_faulty(instance) == 1) { 5235 con_log(CL_ANN1, (CE_NOTE, 5236 "Fw Fault state Handling in io_timeout_checker")); 5237 if (instance->adapterresetinprogress == 0) { 5238 (void) mrsas_reset_ppc(instance); 5239 } 5240 instance->timeout_id = timeout(io_timeout_checker, 5241 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 5242 return; 5243 } 5244 5245 INIT_LIST_HEAD(&process_list); 5246 5247 mutex_enter(&instance->cmd_pend_mtx); 5248 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) { 5249 cmd = mlist_entry(pos, struct mrsas_cmd, list); 5250 5251 if (cmd == NULL) { 5252 continue; 5253 } 5254 5255 if (cmd->sync_cmd == MRSAS_TRUE) { 5256 hdr = (struct mrsas_header *)&cmd->frame->hdr; 5257 if (hdr == NULL) { 5258 continue; 5259 } 5260 time = --hdr->timeout; 5261 } else { 5262 pkt = cmd->pkt; 5263 if (pkt == NULL) { 5264 continue; 5265 } 5266 time = --cmd->drv_pkt_time; 5267 } 5268 if (time <= 0) { 5269 con_log(CL_ANN1, (CE_NOTE, "%llx: " 5270 "io_timeout_checker: TIMING OUT: pkt " 5271 ": %p, cmd %p", gethrtime(), (void *)pkt, 5272 (void *)cmd)); 5273 counter++; 5274 break; 5275 } 5276 } 5277 mutex_exit(&instance->cmd_pend_mtx); 5278 5279 if (counter) { 5280 con_log(CL_ANN1, (CE_NOTE, 5281 "io_timeout_checker " 5282 "cmd->retrycount_for_ocr %d, " 5283 "cmd index %d , cmd address %p ", 5284 cmd->retry_count_for_ocr+1, cmd->index, (void *)cmd)); 5285 5286 if (instance->disable_online_ctrl_reset == 1) { 5287 con_log(CL_ANN1, (CE_NOTE, "mrsas: " 5288 "OCR is not supported by the Firmware " 5289 "Failing all the queued packets \n")); 5290 5291 (void) mrsas_kill_adapter(instance); 5292 } else { 5293 if (cmd->retry_count_for_ocr <= IO_RETRY_COUNT) { 5294 if (instance->adapterresetinprogress == 0) { 5295 con_log(CL_ANN1, (CE_NOTE, "mrsas: " 5296 "OCR is supported by FW " 5297 "triggering mrsas_reset_ppc")); 5298 (void) mrsas_reset_ppc(instance); 5299 } 5300 } else { 5301 con_log(CL_ANN1, (CE_NOTE, 5302 "io_timeout_checker:" 5303 " cmdindex: %d,cmd address: %p " 5304 "timed out even after 3 resets: " 5305 "so kill adapter", cmd->index, 5306 (void *)cmd)); 5307 (void) mrsas_kill_adapter(instance); 5308 return; 5309 } 5310 } 5311 } 5312 5313 5314 if (!mlist_empty(&instance->cmd_pend_list)) { 5315 con_log(CL_ANN1, (CE_NOTE, "mrsas: " 5316 "schedule next timeout check: " 5317 "do timeout \n")); 5318 if (instance->timeout_id == (timeout_id_t)-1) { 5319 instance->timeout_id = 5320 timeout(io_timeout_checker, (void *)instance, 5321 drv_usectohz(MRSAS_1_SECOND)); 5322 } 5323 } 5324 5325 } 5326 static int 5327 read_fw_status_reg_ppc(struct mrsas_instance *instance) 5328 { 5329 return ((int)RD_OB_SCRATCH_PAD_0(instance)); 5330 } 5331 5332 static void 5333 issue_cmd_ppc(struct mrsas_cmd *cmd, struct mrsas_instance *instance) 5334 { 5335 struct scsi_pkt *pkt; 5336 atomic_add_16(&instance->fw_outstanding, 1); 5337 5338 pkt = cmd->pkt; 5339 if (pkt) { 5340 con_log(CL_ANN1, (CE_CONT, "%llx : issue_cmd_ppc:" 5341 "ISSUED CMD TO FW : called : cmd:" 5342 ": %p instance : %p pkt : %p pkt_time : %x\n", 5343 gethrtime(), (void *)cmd, (void *)instance, 5344 (void *)pkt, cmd->drv_pkt_time)); 5345 if (instance->adapterresetinprogress) { 5346 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 5347 con_log(CL_ANN1, (CE_NOTE, "Reset the scsi_pkt timer")); 5348 } else { 5349 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 5350 push_pending_mfi_pkt(instance, cmd); 5351 } 5352 5353 if (pkt) { 5354 con_log(CL_ANN1, (CE_NOTE, 5355 "TO ISSUE: cmd %p index %x " 5356 "pkt %p time %llx", 5357 (void *)cmd, cmd->index, (void *)pkt, 5358 gethrtime())); 5359 } 5360 } else { 5361 con_log(CL_ANN1, (CE_CONT, "%llx : issue_cmd_ppc:" 5362 "ISSUED CMD TO FW : called : cmd : %p, instance: %p" 5363 "(NO PKT)\n", gethrtime(), (void *)cmd, (void *)instance)); 5364 } 5365 /* Issue the command to the FW */ 5366 WR_IB_QPORT((cmd->frame_phys_addr) | 5367 (((cmd->frame_count - 1) << 1) | 1), instance); 5368 } 5369 5370 /* 5371 * issue_cmd_in_sync_mode 5372 */ 5373 static int 5374 issue_cmd_in_sync_mode_ppc(struct mrsas_instance *instance, 5375 struct mrsas_cmd *cmd) 5376 { 5377 int i; 5378 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * (10 * MILLISEC); 5379 5380 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: called")); 5381 5382 if (instance->adapterresetinprogress) { 5383 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: " 5384 "issue and return in reset case\n")); 5385 WR_IB_QPORT((cmd->frame_phys_addr) | 5386 (((cmd->frame_count - 1) << 1) | 1), instance); 5387 return (DDI_SUCCESS); 5388 } else { 5389 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: pushing the pkt\n")); 5390 push_pending_mfi_pkt(instance, cmd); 5391 } 5392 5393 cmd->cmd_status = ENODATA; 5394 5395 WR_IB_QPORT((cmd->frame_phys_addr) | 5396 (((cmd->frame_count - 1) << 1) | 1), instance); 5397 5398 mutex_enter(&instance->int_cmd_mtx); 5399 5400 for (i = 0; i < msecs && (cmd->cmd_status == ENODATA); i++) { 5401 cv_wait(&instance->int_cmd_cv, &instance->int_cmd_mtx); 5402 } 5403 5404 mutex_exit(&instance->int_cmd_mtx); 5405 5406 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: done")); 5407 5408 if (i < (msecs -1)) { 5409 return (DDI_SUCCESS); 5410 } else { 5411 return (DDI_FAILURE); 5412 } 5413 } 5414 5415 /* 5416 * issue_cmd_in_poll_mode 5417 */ 5418 static int 5419 issue_cmd_in_poll_mode_ppc(struct mrsas_instance *instance, 5420 struct mrsas_cmd *cmd) 5421 { 5422 int i; 5423 uint16_t flags; 5424 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC; 5425 struct mrsas_header *frame_hdr; 5426 5427 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_poll_mode_ppc: called")); 5428 5429 frame_hdr = (struct mrsas_header *)cmd->frame; 5430 ddi_put8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status, 5431 MFI_CMD_STATUS_POLL_MODE); 5432 flags = ddi_get16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags); 5433 flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 5434 5435 ddi_put16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags, flags); 5436 5437 /* issue the frame using inbound queue port */ 5438 WR_IB_QPORT((cmd->frame_phys_addr) | 5439 (((cmd->frame_count - 1) << 1) | 1), instance); 5440 5441 /* wait for cmd_status to change from 0xFF */ 5442 for (i = 0; i < msecs && ( 5443 ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status) 5444 == MFI_CMD_STATUS_POLL_MODE); i++) { 5445 drv_usecwait(MILLISEC); /* wait for 1000 usecs */ 5446 } 5447 5448 if (ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status) 5449 == MFI_CMD_STATUS_POLL_MODE) { 5450 con_log(CL_ANN, (CE_NOTE, "issue_cmd_in_poll_mode: " 5451 "cmd polling timed out")); 5452 return (DDI_FAILURE); 5453 } 5454 5455 return (DDI_SUCCESS); 5456 } 5457 5458 static void 5459 enable_intr_ppc(struct mrsas_instance *instance) 5460 { 5461 uint32_t mask; 5462 5463 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: called")); 5464 5465 /* WR_OB_DOORBELL_CLEAR(0xFFFFFFFF, instance); */ 5466 WR_OB_DOORBELL_CLEAR(OB_DOORBELL_CLEAR_MASK, instance); 5467 5468 /* WR_OB_INTR_MASK(~0x80000000, instance); */ 5469 WR_OB_INTR_MASK(~(MFI_REPLY_2108_MESSAGE_INTR_MASK), instance); 5470 5471 /* dummy read to force PCI flush */ 5472 mask = RD_OB_INTR_MASK(instance); 5473 5474 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: " 5475 "outbound_intr_mask = 0x%x", mask)); 5476 } 5477 5478 static void 5479 disable_intr_ppc(struct mrsas_instance *instance) 5480 { 5481 uint32_t mask; 5482 5483 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: called")); 5484 5485 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: before : " 5486 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance))); 5487 5488 /* WR_OB_INTR_MASK(0xFFFFFFFF, instance); */ 5489 WR_OB_INTR_MASK(OB_INTR_MASK, instance); 5490 5491 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: after : " 5492 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance))); 5493 5494 /* dummy read to force PCI flush */ 5495 mask = RD_OB_INTR_MASK(instance); 5496 #ifdef lint 5497 mask = mask; 5498 #endif 5499 } 5500 5501 static int 5502 intr_ack_ppc(struct mrsas_instance *instance) 5503 { 5504 uint32_t status; 5505 int ret = DDI_INTR_CLAIMED; 5506 5507 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: called")); 5508 5509 /* check if it is our interrupt */ 5510 status = RD_OB_INTR_STATUS(instance); 5511 5512 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: status = 0x%x", status)); 5513 5514 if (!(status & MFI_REPLY_2108_MESSAGE_INTR)) { 5515 ret = DDI_INTR_UNCLAIMED; 5516 } 5517 5518 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) { 5519 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 5520 ret = DDI_INTR_UNCLAIMED; 5521 } 5522 5523 if (ret == DDI_INTR_UNCLAIMED) { 5524 return (ret); 5525 } 5526 /* clear the interrupt by writing back the same value */ 5527 WR_OB_DOORBELL_CLEAR(status, instance); 5528 5529 /* dummy READ */ 5530 status = RD_OB_INTR_STATUS(instance); 5531 5532 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: interrupt cleared")); 5533 5534 return (ret); 5535 } 5536 5537 /* 5538 * Marks HBA as bad. This will be called either when an 5539 * IO packet times out even after 3 FW resets 5540 * or FW is found to be fault even after 3 continuous resets. 5541 */ 5542 5543 static int 5544 mrsas_kill_adapter(struct mrsas_instance *instance) 5545 { 5546 if (instance->deadadapter == 1) 5547 return (DDI_FAILURE); 5548 5549 con_log(CL_ANN1, (CE_NOTE, "mrsas_kill_adapter: " 5550 "Writing to doorbell with MFI_STOP_ADP ")); 5551 mutex_enter(&instance->ocr_flags_mtx); 5552 instance->deadadapter = 1; 5553 mutex_exit(&instance->ocr_flags_mtx); 5554 instance->func_ptr->disable_intr(instance); 5555 WR_IB_DOORBELL(MFI_STOP_ADP, instance); 5556 (void) mrsas_complete_pending_cmds(instance); 5557 return (DDI_SUCCESS); 5558 } 5559 5560 5561 static int 5562 mrsas_reset_ppc(struct mrsas_instance *instance) 5563 { 5564 uint32_t status; 5565 uint32_t retry = 0; 5566 uint32_t cur_abs_reg_val; 5567 uint32_t fw_state; 5568 5569 if (instance->deadadapter == 1) { 5570 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5571 "no more resets as HBA has been marked dead ")); 5572 return (DDI_FAILURE); 5573 } 5574 mutex_enter(&instance->ocr_flags_mtx); 5575 instance->adapterresetinprogress = 1; 5576 mutex_exit(&instance->ocr_flags_mtx); 5577 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: adpterresetinprogress " 5578 "flag set, time %llx", gethrtime())); 5579 instance->func_ptr->disable_intr(instance); 5580 retry_reset: 5581 WR_IB_WRITE_SEQ(0, instance); 5582 WR_IB_WRITE_SEQ(4, instance); 5583 WR_IB_WRITE_SEQ(0xb, instance); 5584 WR_IB_WRITE_SEQ(2, instance); 5585 WR_IB_WRITE_SEQ(7, instance); 5586 WR_IB_WRITE_SEQ(0xd, instance); 5587 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: magic number written " 5588 "to write sequence register\n")); 5589 delay(100 * drv_usectohz(MILLISEC)); 5590 status = RD_OB_DRWE(instance); 5591 5592 while (!(status & DIAG_WRITE_ENABLE)) { 5593 delay(100 * drv_usectohz(MILLISEC)); 5594 status = RD_OB_DRWE(instance); 5595 if (retry++ == 100) { 5596 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: DRWE bit " 5597 "check retry count %d\n", retry)); 5598 return (DDI_FAILURE); 5599 } 5600 } 5601 WR_IB_DRWE(status | DIAG_RESET_ADAPTER, instance); 5602 delay(100 * drv_usectohz(MILLISEC)); 5603 status = RD_OB_DRWE(instance); 5604 while (status & DIAG_RESET_ADAPTER) { 5605 delay(100 * drv_usectohz(MILLISEC)); 5606 status = RD_OB_DRWE(instance); 5607 if (retry++ == 100) { 5608 (void) mrsas_kill_adapter(instance); 5609 return (DDI_FAILURE); 5610 } 5611 } 5612 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: Adapter reset complete")); 5613 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5614 "Calling mfi_state_transition_to_ready")); 5615 5616 /* Mark HBA as bad, if FW is fault after 3 continuous resets */ 5617 if (mfi_state_transition_to_ready(instance) || 5618 debug_fw_faults_after_ocr_g == 1) { 5619 cur_abs_reg_val = 5620 instance->func_ptr->read_fw_status_reg(instance); 5621 fw_state = cur_abs_reg_val & MFI_STATE_MASK; 5622 5623 #ifdef OCRDEBUG 5624 con_log(CL_ANN1, (CE_NOTE, 5625 "mrsas_reset_ppc :before fake: FW is not ready " 5626 "FW state = 0x%x", fw_state)); 5627 if (debug_fw_faults_after_ocr_g == 1) 5628 fw_state = MFI_STATE_FAULT; 5629 #endif 5630 5631 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc : FW is not ready " 5632 "FW state = 0x%x", fw_state)); 5633 5634 if (fw_state == MFI_STATE_FAULT) { 5635 // increment the count 5636 instance->fw_fault_count_after_ocr++; 5637 if (instance->fw_fault_count_after_ocr 5638 < MAX_FW_RESET_COUNT) { 5639 con_log(CL_ANN1, (CE_WARN, "mrsas_reset_ppc: " 5640 "FW is in fault after OCR count %d ", 5641 instance->fw_fault_count_after_ocr)); 5642 goto retry_reset; 5643 5644 } else { 5645 con_log(CL_ANN1, (CE_WARN, "mrsas_reset_ppc: " 5646 "Max Reset Count exceeded " 5647 "Mark HBA as bad")); 5648 (void) mrsas_kill_adapter(instance); 5649 return (DDI_FAILURE); 5650 } 5651 } 5652 } 5653 // reset the counter as FW is up after OCR 5654 instance->fw_fault_count_after_ocr = 0; 5655 5656 5657 ddi_put32(instance->mfi_internal_dma_obj.acc_handle, 5658 instance->producer, 0); 5659 5660 ddi_put32(instance->mfi_internal_dma_obj.acc_handle, 5661 instance->consumer, 0); 5662 5663 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5664 " after resetting produconsumer chck indexs:" 5665 "producer %x consumer %x", *instance->producer, 5666 *instance->consumer)); 5667 5668 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5669 "Calling mrsas_issue_init_mfi")); 5670 (void) mrsas_issue_init_mfi(instance); 5671 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5672 "mrsas_issue_init_mfi Done")); 5673 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5674 "Calling mrsas_print_pending_cmd\n")); 5675 (void) mrsas_print_pending_cmds(instance); 5676 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5677 "mrsas_print_pending_cmd done\n")); 5678 instance->func_ptr->enable_intr(instance); 5679 instance->fw_outstanding = 0; 5680 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5681 "Calling mrsas_issue_pending_cmds")); 5682 (void) mrsas_issue_pending_cmds(instance); 5683 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5684 "Complete")); 5685 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5686 "Calling aen registration")); 5687 instance->func_ptr->issue_cmd(instance->aen_cmd, instance); 5688 con_log(CL_ANN1, (CE_NOTE, "Unsetting adpresetinprogress flag.\n")); 5689 mutex_enter(&instance->ocr_flags_mtx); 5690 instance->adapterresetinprogress = 0; 5691 mutex_exit(&instance->ocr_flags_mtx); 5692 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 5693 "adpterresetinprogress flag unset")); 5694 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc done\n")); 5695 return (DDI_SUCCESS); 5696 } 5697 static int 5698 mrsas_common_check(struct mrsas_instance *instance, 5699 struct mrsas_cmd *cmd) 5700 { 5701 int ret = DDI_SUCCESS; 5702 5703 if (mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) != 5704 DDI_SUCCESS) { 5705 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 5706 if (cmd->pkt != NULL) { 5707 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 5708 cmd->pkt->pkt_statistics = 0; 5709 } 5710 ret = DDI_FAILURE; 5711 } 5712 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle) 5713 != DDI_SUCCESS) { 5714 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 5715 if (cmd->pkt != NULL) { 5716 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 5717 cmd->pkt->pkt_statistics = 0; 5718 } 5719 ret = DDI_FAILURE; 5720 } 5721 if (mrsas_check_dma_handle(instance->mfi_evt_detail_obj.dma_handle) != 5722 DDI_SUCCESS) { 5723 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 5724 if (cmd->pkt != NULL) { 5725 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 5726 cmd->pkt->pkt_statistics = 0; 5727 } 5728 ret = DDI_FAILURE; 5729 } 5730 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) { 5731 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 5732 5733 ddi_fm_acc_err_clear(instance->regmap_handle, DDI_FME_VER0); 5734 5735 if (cmd->pkt != NULL) { 5736 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 5737 cmd->pkt->pkt_statistics = 0; 5738 } 5739 ret = DDI_FAILURE; 5740 } 5741 5742 return (ret); 5743 } 5744 5745 /*ARGSUSED*/ 5746 static int 5747 mrsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5748 { 5749 /* 5750 * as the driver can always deal with an error in any dma or 5751 * access handle, we can just return the fme_status value. 5752 */ 5753 pci_ereport_post(dip, err, NULL); 5754 return (err->fme_status); 5755 } 5756 5757 static void 5758 mrsas_fm_init(struct mrsas_instance *instance) 5759 { 5760 /* Need to change iblock to priority for new MSI intr */ 5761 ddi_iblock_cookie_t fm_ibc; 5762 5763 /* Only register with IO Fault Services if we have some capability */ 5764 if (instance->fm_capabilities) { 5765 /* Adjust access and dma attributes for FMA */ 5766 endian_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5767 mrsas_generic_dma_attr.dma_attr_flags = DDI_DMA_FLAGERR; 5768 5769 /* 5770 * Register capabilities with IO Fault Services. 5771 * fm_capabilities will be updated to indicate 5772 * capabilities actually supported (not requested.) 5773 */ 5774 5775 ddi_fm_init(instance->dip, &instance->fm_capabilities, &fm_ibc); 5776 5777 /* 5778 * Initialize pci ereport capabilities if ereport 5779 * capable (should always be.) 5780 */ 5781 5782 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) || 5783 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 5784 pci_ereport_setup(instance->dip); 5785 } 5786 5787 /* 5788 * Register error callback if error callback capable. 5789 */ 5790 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 5791 ddi_fm_handler_register(instance->dip, 5792 mrsas_fm_error_cb, (void*) instance); 5793 } 5794 } else { 5795 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5796 mrsas_generic_dma_attr.dma_attr_flags = 0; 5797 } 5798 } 5799 5800 static void 5801 mrsas_fm_fini(struct mrsas_instance *instance) 5802 { 5803 /* Only unregister FMA capabilities if registered */ 5804 if (instance->fm_capabilities) { 5805 /* 5806 * Un-register error callback if error callback capable. 5807 */ 5808 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 5809 ddi_fm_handler_unregister(instance->dip); 5810 } 5811 5812 /* 5813 * Release any resources allocated by pci_ereport_setup() 5814 */ 5815 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) || 5816 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 5817 pci_ereport_teardown(instance->dip); 5818 } 5819 5820 /* Unregister from IO Fault Services */ 5821 ddi_fm_fini(instance->dip); 5822 5823 /* Adjust access and dma attributes for FMA */ 5824 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5825 mrsas_generic_dma_attr.dma_attr_flags = 0; 5826 } 5827 } 5828 5829 int 5830 mrsas_check_acc_handle(ddi_acc_handle_t handle) 5831 { 5832 ddi_fm_error_t de; 5833 5834 if (handle == NULL) { 5835 return (DDI_FAILURE); 5836 } 5837 5838 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5839 5840 return (de.fme_status); 5841 } 5842 5843 int 5844 mrsas_check_dma_handle(ddi_dma_handle_t handle) 5845 { 5846 ddi_fm_error_t de; 5847 5848 if (handle == NULL) { 5849 return (DDI_FAILURE); 5850 } 5851 5852 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5853 5854 return (de.fme_status); 5855 } 5856 5857 void 5858 mrsas_fm_ereport(struct mrsas_instance *instance, char *detail) 5859 { 5860 uint64_t ena; 5861 char buf[FM_MAX_CLASS]; 5862 5863 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5864 ena = fm_ena_generate(0, FM_ENA_FMT1); 5865 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities)) { 5866 ddi_fm_ereport_post(instance->dip, buf, ena, DDI_NOSLEEP, 5867 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERSION, NULL); 5868 } 5869 } 5870 5871 static int 5872 mrsas_add_intrs(struct mrsas_instance *instance, int intr_type) 5873 { 5874 5875 dev_info_t *dip = instance->dip; 5876 int avail, actual, count; 5877 int i, flag, ret; 5878 5879 con_log(CL_DLEVEL1, (CE_WARN, "mrsas_add_intrs: intr_type = %x", 5880 intr_type)); 5881 5882 /* Get number of interrupts */ 5883 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 5884 if ((ret != DDI_SUCCESS) || (count == 0)) { 5885 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_nintrs() failed:" 5886 "ret %d count %d", ret, count)); 5887 5888 return (DDI_FAILURE); 5889 } 5890 5891 con_log(CL_DLEVEL1, (CE_WARN, "mrsas_add_intrs: count = %d ", count)); 5892 5893 /* Get number of available interrupts */ 5894 ret = ddi_intr_get_navail(dip, intr_type, &avail); 5895 if ((ret != DDI_SUCCESS) || (avail == 0)) { 5896 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_navail() failed:" 5897 "ret %d avail %d", ret, avail)); 5898 5899 return (DDI_FAILURE); 5900 } 5901 con_log(CL_DLEVEL1, (CE_WARN, "mrsas_add_intrs: avail = %d ", avail)); 5902 5903 /* Only one interrupt routine. So limit the count to 1 */ 5904 if (count > 1) { 5905 count = 1; 5906 } 5907 5908 /* 5909 * Allocate an array of interrupt handlers. Currently we support 5910 * only one interrupt. The framework can be extended later. 5911 */ 5912 instance->intr_size = count * sizeof (ddi_intr_handle_t); 5913 instance->intr_htable = kmem_zalloc(instance->intr_size, KM_SLEEP); 5914 ASSERT(instance->intr_htable); 5915 5916 flag = ((intr_type == DDI_INTR_TYPE_MSI) || (intr_type == 5917 DDI_INTR_TYPE_MSIX)) ? DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 5918 5919 /* Allocate interrupt */ 5920 ret = ddi_intr_alloc(dip, instance->intr_htable, intr_type, 0, 5921 count, &actual, flag); 5922 5923 if ((ret != DDI_SUCCESS) || (actual == 0)) { 5924 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 5925 "avail = %d", avail)); 5926 kmem_free(instance->intr_htable, instance->intr_size); 5927 return (DDI_FAILURE); 5928 } 5929 if (actual < count) { 5930 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 5931 "Requested = %d Received = %d", count, actual)); 5932 } 5933 instance->intr_cnt = actual; 5934 5935 /* 5936 * Get the priority of the interrupt allocated. 5937 */ 5938 if ((ret = ddi_intr_get_pri(instance->intr_htable[0], 5939 &instance->intr_pri)) != DDI_SUCCESS) { 5940 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 5941 "get priority call failed")); 5942 5943 for (i = 0; i < actual; i++) { 5944 (void) ddi_intr_free(instance->intr_htable[i]); 5945 } 5946 kmem_free(instance->intr_htable, instance->intr_size); 5947 return (DDI_FAILURE); 5948 } 5949 5950 /* 5951 * Test for high level mutex. we don't support them. 5952 */ 5953 if (instance->intr_pri >= ddi_intr_get_hilevel_pri()) { 5954 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 5955 "High level interrupts not supported.")); 5956 5957 for (i = 0; i < actual; i++) { 5958 (void) ddi_intr_free(instance->intr_htable[i]); 5959 } 5960 kmem_free(instance->intr_htable, instance->intr_size); 5961 return (DDI_FAILURE); 5962 } 5963 5964 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_pri = 0x%x ", 5965 instance->intr_pri)); 5966 5967 /* Call ddi_intr_add_handler() */ 5968 for (i = 0; i < actual; i++) { 5969 ret = ddi_intr_add_handler(instance->intr_htable[i], 5970 (ddi_intr_handler_t *)mrsas_isr, (caddr_t)instance, 5971 (caddr_t)(uintptr_t)i); 5972 5973 if (ret != DDI_SUCCESS) { 5974 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs:" 5975 "failed %d", ret)); 5976 5977 for (i = 0; i < actual; i++) { 5978 (void) ddi_intr_free(instance->intr_htable[i]); 5979 } 5980 kmem_free(instance->intr_htable, instance->intr_size); 5981 return (DDI_FAILURE); 5982 } 5983 5984 } 5985 5986 con_log(CL_DLEVEL1, (CE_WARN, " ddi_intr_add_handler done")); 5987 5988 if ((ret = ddi_intr_get_cap(instance->intr_htable[0], 5989 &instance->intr_cap)) != DDI_SUCCESS) { 5990 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_cap() failed %d", 5991 ret)); 5992 5993 /* Free already allocated intr */ 5994 for (i = 0; i < actual; i++) { 5995 (void) ddi_intr_remove_handler( 5996 instance->intr_htable[i]); 5997 (void) ddi_intr_free(instance->intr_htable[i]); 5998 } 5999 kmem_free(instance->intr_htable, instance->intr_size); 6000 return (DDI_FAILURE); 6001 } 6002 6003 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) { 6004 con_log(CL_ANN, (CE_WARN, "Calling ddi_intr_block _enable")); 6005 6006 (void) ddi_intr_block_enable(instance->intr_htable, 6007 instance->intr_cnt); 6008 } else { 6009 con_log(CL_ANN, (CE_NOTE, " calling ddi_intr_enable")); 6010 6011 for (i = 0; i < instance->intr_cnt; i++) { 6012 (void) ddi_intr_enable(instance->intr_htable[i]); 6013 con_log(CL_ANN, (CE_NOTE, "ddi intr enable returns " 6014 "%d", i)); 6015 } 6016 } 6017 6018 return (DDI_SUCCESS); 6019 6020 } 6021 6022 6023 static void 6024 mrsas_rem_intrs(struct mrsas_instance *instance) 6025 { 6026 int i; 6027 6028 con_log(CL_ANN, (CE_NOTE, "mrsas_rem_intrs called")); 6029 6030 /* Disable all interrupts first */ 6031 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) { 6032 (void) ddi_intr_block_disable(instance->intr_htable, 6033 instance->intr_cnt); 6034 } else { 6035 for (i = 0; i < instance->intr_cnt; i++) { 6036 (void) ddi_intr_disable(instance->intr_htable[i]); 6037 } 6038 } 6039 6040 /* Remove all the handlers */ 6041 6042 for (i = 0; i < instance->intr_cnt; i++) { 6043 (void) ddi_intr_remove_handler(instance->intr_htable[i]); 6044 (void) ddi_intr_free(instance->intr_htable[i]); 6045 } 6046 6047 kmem_free(instance->intr_htable, instance->intr_size); 6048 } 6049 6050 static int 6051 mrsas_tran_bus_config(dev_info_t *parent, uint_t flags, 6052 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 6053 { 6054 struct mrsas_instance *instance; 6055 int config; 6056 int rval; 6057 6058 char *ptr = NULL; 6059 int tgt, lun; 6060 6061 con_log(CL_ANN1, (CE_NOTE, "Bus config called for op = %x", op)); 6062 6063 if ((instance = ddi_get_soft_state(mrsas_state, 6064 ddi_get_instance(parent))) == NULL) { 6065 return (NDI_FAILURE); 6066 } 6067 6068 /* Hold nexus during bus_config */ 6069 ndi_devi_enter(parent, &config); 6070 switch (op) { 6071 case BUS_CONFIG_ONE: { 6072 6073 /* parse wwid/target name out of name given */ 6074 if ((ptr = strchr((char *)arg, '@')) == NULL) { 6075 rval = NDI_FAILURE; 6076 break; 6077 } 6078 ptr++; 6079 6080 if (mrsas_parse_devname(arg, &tgt, &lun) != 0) { 6081 rval = NDI_FAILURE; 6082 break; 6083 } 6084 6085 if (lun == 0) { 6086 rval = mrsas_config_ld(instance, tgt, lun, childp); 6087 } else { 6088 rval = NDI_FAILURE; 6089 } 6090 6091 break; 6092 } 6093 case BUS_CONFIG_DRIVER: 6094 case BUS_CONFIG_ALL: { 6095 6096 rval = mrsas_config_all_devices(instance); 6097 6098 rval = NDI_SUCCESS; 6099 break; 6100 } 6101 } 6102 6103 if (rval == NDI_SUCCESS) { 6104 rval = ndi_busop_bus_config(parent, flags, op, arg, childp, 0); 6105 6106 } 6107 ndi_devi_exit(parent, config); 6108 6109 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_bus_config: rval = %x", 6110 rval)); 6111 return (rval); 6112 } 6113 6114 static int 6115 mrsas_config_all_devices(struct mrsas_instance *instance) 6116 { 6117 int rval, tgt; 6118 6119 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) { 6120 (void) mrsas_config_ld(instance, tgt, 0, NULL); 6121 6122 } 6123 6124 rval = NDI_SUCCESS; 6125 return (rval); 6126 } 6127 6128 static int 6129 mrsas_parse_devname(char *devnm, int *tgt, int *lun) 6130 { 6131 char devbuf[SCSI_MAXNAMELEN]; 6132 char *addr; 6133 char *p, *tp, *lp; 6134 long num; 6135 6136 /* Parse dev name and address */ 6137 (void) strcpy(devbuf, devnm); 6138 addr = ""; 6139 for (p = devbuf; *p != '\0'; p++) { 6140 if (*p == '@') { 6141 addr = p + 1; 6142 *p = '\0'; 6143 } else if (*p == ':') { 6144 *p = '\0'; 6145 break; 6146 } 6147 } 6148 6149 /* Parse target and lun */ 6150 for (p = tp = addr, lp = NULL; *p != '\0'; p++) { 6151 if (*p == ',') { 6152 lp = p + 1; 6153 *p = '\0'; 6154 break; 6155 } 6156 } 6157 if (tgt && tp) { 6158 if (ddi_strtol(tp, NULL, 0x10, &num)) { 6159 return (DDI_FAILURE); /* Can declare this as constant */ 6160 } 6161 *tgt = (int)num; 6162 } 6163 if (lun && lp) { 6164 if (ddi_strtol(lp, NULL, 0x10, &num)) { 6165 return (DDI_FAILURE); 6166 } 6167 *lun = (int)num; 6168 } 6169 return (DDI_SUCCESS); /* Success case */ 6170 } 6171 6172 static int 6173 mrsas_config_ld(struct mrsas_instance *instance, uint16_t tgt, 6174 uint8_t lun, dev_info_t **ldip) 6175 { 6176 struct scsi_device *sd; 6177 dev_info_t *child; 6178 int rval; 6179 6180 con_log(CL_ANN1, (CE_NOTE, "mrsas_config_ld: t = %d l = %d", 6181 tgt, lun)); 6182 6183 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) { 6184 if (ldip) { 6185 *ldip = child; 6186 } 6187 con_log(CL_ANN1, (CE_NOTE, 6188 "mrsas_config_ld: Child = %p found t = %d l = %d", 6189 (void *)child, tgt, lun)); 6190 return (NDI_SUCCESS); 6191 } 6192 6193 sd = kmem_zalloc(sizeof (struct scsi_device), KM_SLEEP); 6194 sd->sd_address.a_hba_tran = instance->tran; 6195 sd->sd_address.a_target = (uint16_t)tgt; 6196 sd->sd_address.a_lun = (uint8_t)lun; 6197 6198 if (scsi_hba_probe(sd, NULL) == SCSIPROBE_EXISTS) 6199 rval = mrsas_config_scsi_device(instance, sd, ldip); 6200 else 6201 rval = NDI_FAILURE; 6202 6203 /* sd_unprobe is blank now. Free buffer manually */ 6204 if (sd->sd_inq) { 6205 kmem_free(sd->sd_inq, SUN_INQSIZE); 6206 sd->sd_inq = (struct scsi_inquiry *)NULL; 6207 } 6208 6209 kmem_free(sd, sizeof (struct scsi_device)); 6210 con_log(CL_ANN1, (CE_NOTE, "mrsas_config_ld: return rval = %d", 6211 rval)); 6212 return (rval); 6213 } 6214 6215 static int 6216 mrsas_config_scsi_device(struct mrsas_instance *instance, 6217 struct scsi_device *sd, dev_info_t **dipp) 6218 { 6219 char *nodename = NULL; 6220 char **compatible = NULL; 6221 int ncompatible = 0; 6222 char *childname; 6223 dev_info_t *ldip = NULL; 6224 int tgt = sd->sd_address.a_target; 6225 int lun = sd->sd_address.a_lun; 6226 int dtype = sd->sd_inq->inq_dtype & DTYPE_MASK; 6227 int rval; 6228 6229 con_log(CL_ANN1, (CE_WARN, "mr_sas: scsi_device t%dL%d", tgt, lun)); 6230 scsi_hba_nodename_compatible_get(sd->sd_inq, NULL, dtype, 6231 NULL, &nodename, &compatible, &ncompatible); 6232 6233 if (nodename == NULL) { 6234 con_log(CL_ANN1, (CE_WARN, "mr_sas: Found no compatible driver " 6235 "for t%dL%d", tgt, lun)); 6236 rval = NDI_FAILURE; 6237 goto finish; 6238 } 6239 6240 childname = (dtype == DTYPE_DIRECT) ? "sd" : nodename; 6241 con_log(CL_ANN1, (CE_WARN, 6242 "mr_sas: Childname = %2s nodename = %s", childname, nodename)); 6243 6244 /* Create a dev node */ 6245 rval = ndi_devi_alloc(instance->dip, childname, DEVI_SID_NODEID, &ldip); 6246 con_log(CL_ANN1, (CE_WARN, 6247 "mr_sas_config_scsi_device: ndi_devi_alloc rval = %x", rval)); 6248 if (rval == NDI_SUCCESS) { 6249 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "target", tgt) != 6250 DDI_PROP_SUCCESS) { 6251 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create " 6252 "property for t%dl%d target", tgt, lun)); 6253 rval = NDI_FAILURE; 6254 goto finish; 6255 } 6256 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "lun", lun) != 6257 DDI_PROP_SUCCESS) { 6258 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create " 6259 "property for t%dl%d lun", tgt, lun)); 6260 rval = NDI_FAILURE; 6261 goto finish; 6262 } 6263 6264 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, ldip, 6265 "compatible", compatible, ncompatible) != 6266 DDI_PROP_SUCCESS) { 6267 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create " 6268 "property for t%dl%d compatible", tgt, lun)); 6269 rval = NDI_FAILURE; 6270 goto finish; 6271 } 6272 6273 rval = ndi_devi_online(ldip, NDI_ONLINE_ATTACH); 6274 if (rval != NDI_SUCCESS) { 6275 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to online " 6276 "t%dl%d", tgt, lun)); 6277 ndi_prop_remove_all(ldip); 6278 (void) ndi_devi_free(ldip); 6279 } else { 6280 con_log(CL_ANN1, (CE_WARN, "mr_sas: online Done :" 6281 "0 t%dl%d", tgt, lun)); 6282 } 6283 6284 } 6285 finish: 6286 if (dipp) { 6287 *dipp = ldip; 6288 } 6289 6290 con_log(CL_DLEVEL1, (CE_WARN, 6291 "mr_sas: config_scsi_device rval = %d t%dL%d", 6292 rval, tgt, lun)); 6293 scsi_hba_nodename_compatible_free(nodename, compatible); 6294 return (rval); 6295 } 6296 6297 /*ARGSUSED*/ 6298 static int 6299 mrsas_service_evt(struct mrsas_instance *instance, int tgt, int lun, int event, 6300 uint64_t wwn) 6301 { 6302 struct mrsas_eventinfo *mrevt = NULL; 6303 6304 con_log(CL_ANN1, (CE_NOTE, 6305 "mrsas_service_evt called for t%dl%d event = %d", 6306 tgt, lun, event)); 6307 6308 if ((instance->taskq == NULL) || (mrevt = 6309 kmem_zalloc(sizeof (struct mrsas_eventinfo), KM_NOSLEEP)) == NULL) { 6310 return (ENOMEM); 6311 } 6312 6313 mrevt->instance = instance; 6314 mrevt->tgt = tgt; 6315 mrevt->lun = lun; 6316 mrevt->event = event; 6317 6318 if ((ddi_taskq_dispatch(instance->taskq, 6319 (void (*)(void *))mrsas_issue_evt_taskq, mrevt, DDI_NOSLEEP)) != 6320 DDI_SUCCESS) { 6321 con_log(CL_ANN1, (CE_NOTE, 6322 "mr_sas: Event task failed for t%dl%d event = %d", 6323 tgt, lun, event)); 6324 kmem_free(mrevt, sizeof (struct mrsas_eventinfo)); 6325 return (DDI_FAILURE); 6326 } 6327 DTRACE_PROBE3(service_evt, int, tgt, int, lun, int, event); 6328 return (DDI_SUCCESS); 6329 } 6330 6331 static void 6332 mrsas_issue_evt_taskq(struct mrsas_eventinfo *mrevt) 6333 { 6334 struct mrsas_instance *instance = mrevt->instance; 6335 dev_info_t *dip, *pdip; 6336 int circ1 = 0; 6337 char *devname; 6338 6339 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_evt_taskq: called for" 6340 " tgt %d lun %d event %d", 6341 mrevt->tgt, mrevt->lun, mrevt->event)); 6342 6343 if (mrevt->tgt < MRDRV_MAX_LD && mrevt->lun == 0) { 6344 dip = instance->mr_ld_list[mrevt->tgt].dip; 6345 } else { 6346 return; 6347 } 6348 6349 ndi_devi_enter(instance->dip, &circ1); 6350 switch (mrevt->event) { 6351 case MRSAS_EVT_CONFIG_TGT: 6352 if (dip == NULL) { 6353 6354 if (mrevt->lun == 0) { 6355 (void) mrsas_config_ld(instance, mrevt->tgt, 6356 0, NULL); 6357 } 6358 con_log(CL_ANN1, (CE_NOTE, 6359 "mr_sas: EVT_CONFIG_TGT called:" 6360 " for tgt %d lun %d event %d", 6361 mrevt->tgt, mrevt->lun, mrevt->event)); 6362 6363 } else { 6364 con_log(CL_ANN1, (CE_NOTE, 6365 "mr_sas: EVT_CONFIG_TGT dip != NULL:" 6366 " for tgt %d lun %d event %d", 6367 mrevt->tgt, mrevt->lun, mrevt->event)); 6368 } 6369 break; 6370 case MRSAS_EVT_UNCONFIG_TGT: 6371 if (dip) { 6372 if (i_ddi_devi_attached(dip)) { 6373 6374 pdip = ddi_get_parent(dip); 6375 6376 devname = kmem_zalloc(MAXNAMELEN + 1, KM_SLEEP); 6377 (void) ddi_deviname(dip, devname); 6378 6379 (void) devfs_clean(pdip, devname + 1, 6380 DV_CLEAN_FORCE); 6381 kmem_free(devname, MAXNAMELEN + 1); 6382 } 6383 (void) ndi_devi_offline(dip, NDI_DEVI_REMOVE); 6384 con_log(CL_ANN1, (CE_NOTE, 6385 "mr_sas: EVT_UNCONFIG_TGT called:" 6386 " for tgt %d lun %d event %d", 6387 mrevt->tgt, mrevt->lun, mrevt->event)); 6388 } else { 6389 con_log(CL_ANN1, (CE_NOTE, 6390 "mr_sas: EVT_UNCONFIG_TGT dip == NULL:" 6391 " for tgt %d lun %d event %d", 6392 mrevt->tgt, mrevt->lun, mrevt->event)); 6393 } 6394 break; 6395 } 6396 kmem_free(mrevt, sizeof (struct mrsas_eventinfo)); 6397 ndi_devi_exit(instance->dip, circ1); 6398 } 6399 6400 static int 6401 mrsas_mode_sense_build(struct scsi_pkt *pkt) 6402 { 6403 union scsi_cdb *cdbp; 6404 uint16_t page_code; 6405 struct scsa_cmd *acmd; 6406 struct buf *bp; 6407 struct mode_header *modehdrp; 6408 6409 cdbp = (void *)pkt->pkt_cdbp; 6410 page_code = cdbp->cdb_un.sg.scsi[0]; 6411 acmd = PKT2CMD(pkt); 6412 bp = acmd->cmd_buf; 6413 if ((!bp) && bp->b_un.b_addr && bp->b_bcount && acmd->cmd_dmacount) { 6414 con_log(CL_ANN1, (CE_WARN, "Failing MODESENSE Command")); 6415 /* ADD pkt statistics as Command failed. */ 6416 return (NULL); 6417 } 6418 6419 bp_mapin(bp); 6420 bzero(bp->b_un.b_addr, bp->b_bcount); 6421 6422 switch (page_code) { 6423 case 0x3: { 6424 struct mode_format *page3p = NULL; 6425 modehdrp = (struct mode_header *)(bp->b_un.b_addr); 6426 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH; 6427 6428 page3p = (void *)((caddr_t)modehdrp + 6429 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH); 6430 page3p->mode_page.code = 0x3; 6431 page3p->mode_page.length = 6432 (uchar_t)(sizeof (struct mode_format)); 6433 page3p->data_bytes_sect = 512; 6434 page3p->sect_track = 63; 6435 break; 6436 } 6437 case 0x4: { 6438 struct mode_geometry *page4p = NULL; 6439 modehdrp = (struct mode_header *)(bp->b_un.b_addr); 6440 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH; 6441 6442 page4p = (void *)((caddr_t)modehdrp + 6443 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH); 6444 page4p->mode_page.code = 0x4; 6445 page4p->mode_page.length = 6446 (uchar_t)(sizeof (struct mode_geometry)); 6447 page4p->heads = 255; 6448 page4p->rpm = 10000; 6449 break; 6450 } 6451 default: 6452 break; 6453 } 6454 return (NULL); 6455 } 6456