1 /* 2 * mr_sas.c: source for mr_sas driver 3 * 4 * Solaris MegaRAID device driver for SAS2.0 controllers 5 * Copyright (c) 2008-2012, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Version: 9 * Author: 10 * Swaminathan K S 11 * Arun Chandrashekhar 12 * Manju R 13 * Rasheed 14 * Shakeel Bukhari 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions are met: 18 * 19 * 1. Redistributions of source code must retain the above copyright notice, 20 * this list of conditions and the following disclaimer. 21 * 22 * 2. Redistributions in binary form must reproduce the above copyright notice, 23 * this list of conditions and the following disclaimer in the documentation 24 * and/or other materials provided with the distribution. 25 * 26 * 3. Neither the name of the author nor the names of its contributors may be 27 * used to endorse or promote products derived from this software without 28 * specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 41 * DAMAGE. 42 */ 43 44 /* 45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 46 * Copyright (c) 2011 Bayard G. Bell. All rights reserved. 47 * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 48 * Copyright 2015, 2017 Citrus IT Limited. All rights reserved. 49 * Copyright 2015 Garrett D'Amore <garrett@damore.org> 50 */ 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/file.h> 55 #include <sys/errno.h> 56 #include <sys/open.h> 57 #include <sys/cred.h> 58 #include <sys/modctl.h> 59 #include <sys/conf.h> 60 #include <sys/devops.h> 61 #include <sys/cmn_err.h> 62 #include <sys/kmem.h> 63 #include <sys/stat.h> 64 #include <sys/mkdev.h> 65 #include <sys/pci.h> 66 #include <sys/scsi/scsi.h> 67 #include <sys/ddi.h> 68 #include <sys/sunddi.h> 69 #include <sys/atomic.h> 70 #include <sys/signal.h> 71 #include <sys/byteorder.h> 72 #include <sys/sdt.h> 73 #include <sys/fs/dv_node.h> /* devfs_clean */ 74 75 #include "mr_sas.h" 76 77 /* 78 * FMA header files 79 */ 80 #include <sys/ddifm.h> 81 #include <sys/fm/protocol.h> 82 #include <sys/fm/util.h> 83 #include <sys/fm/io/ddi.h> 84 85 /* Macros to help Skinny and stock 2108/MFI live together. */ 86 #define WR_IB_PICK_QPORT(addr, instance) \ 87 if ((instance)->skinny) { \ 88 WR_IB_LOW_QPORT((addr), (instance)); \ 89 WR_IB_HIGH_QPORT(0, (instance)); \ 90 } else { \ 91 WR_IB_QPORT((addr), (instance)); \ 92 } 93 94 /* 95 * Local static data 96 */ 97 static void *mrsas_state = NULL; 98 static volatile boolean_t mrsas_relaxed_ordering = B_TRUE; 99 volatile int debug_level_g = CL_NONE; 100 static volatile int msi_enable = 1; 101 static volatile int ctio_enable = 1; 102 103 /* Default Timeout value to issue online controller reset */ 104 volatile int debug_timeout_g = 0xF0; /* 0xB4; */ 105 /* Simulate consecutive firmware fault */ 106 static volatile int debug_fw_faults_after_ocr_g = 0; 107 #ifdef OCRDEBUG 108 /* Simulate three consecutive timeout for an IO */ 109 static volatile int debug_consecutive_timeout_after_ocr_g = 0; 110 #endif 111 112 #pragma weak scsi_hba_open 113 #pragma weak scsi_hba_close 114 #pragma weak scsi_hba_ioctl 115 116 /* Local static prototypes. */ 117 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 118 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t); 119 #ifdef __sparc 120 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t); 121 #else 122 static int mrsas_quiesce(dev_info_t *); 123 #endif 124 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t); 125 static int mrsas_open(dev_t *, int, int, cred_t *); 126 static int mrsas_close(dev_t, int, int, cred_t *); 127 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 128 129 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *, 130 scsi_hba_tran_t *, struct scsi_device *); 131 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register 132 struct scsi_pkt *, struct buf *, int, int, int, int, 133 int (*)(), caddr_t); 134 static int mrsas_tran_start(struct scsi_address *, 135 register struct scsi_pkt *); 136 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *); 137 static int mrsas_tran_reset(struct scsi_address *, int); 138 static int mrsas_tran_getcap(struct scsi_address *, char *, int); 139 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int); 140 static void mrsas_tran_destroy_pkt(struct scsi_address *, 141 struct scsi_pkt *); 142 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *); 143 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *); 144 static int mrsas_tran_quiesce(dev_info_t *dip); 145 static int mrsas_tran_unquiesce(dev_info_t *dip); 146 static uint_t mrsas_isr(); 147 static uint_t mrsas_softintr(); 148 static void mrsas_undo_resources(dev_info_t *, struct mrsas_instance *); 149 150 static void free_space_for_mfi(struct mrsas_instance *); 151 static uint32_t read_fw_status_reg_ppc(struct mrsas_instance *); 152 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *); 153 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *, 154 struct mrsas_cmd *); 155 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *, 156 struct mrsas_cmd *); 157 static void enable_intr_ppc(struct mrsas_instance *); 158 static void disable_intr_ppc(struct mrsas_instance *); 159 static int intr_ack_ppc(struct mrsas_instance *); 160 static void flush_cache(struct mrsas_instance *instance); 161 void display_scsi_inquiry(caddr_t); 162 static int start_mfi_aen(struct mrsas_instance *instance); 163 static int handle_drv_ioctl(struct mrsas_instance *instance, 164 struct mrsas_ioctl *ioctl, int mode); 165 static int handle_mfi_ioctl(struct mrsas_instance *instance, 166 struct mrsas_ioctl *ioctl, int mode); 167 static int handle_mfi_aen(struct mrsas_instance *instance, 168 struct mrsas_aen *aen); 169 static struct mrsas_cmd *build_cmd(struct mrsas_instance *, 170 struct scsi_address *, struct scsi_pkt *, uchar_t *); 171 static int alloc_additional_dma_buffer(struct mrsas_instance *); 172 static void complete_cmd_in_sync_mode(struct mrsas_instance *, 173 struct mrsas_cmd *); 174 static int mrsas_kill_adapter(struct mrsas_instance *); 175 static int mrsas_issue_init_mfi(struct mrsas_instance *); 176 static int mrsas_reset_ppc(struct mrsas_instance *); 177 static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *); 178 static int wait_for_outstanding(struct mrsas_instance *instance); 179 static int register_mfi_aen(struct mrsas_instance *instance, 180 uint32_t seq_num, uint32_t class_locale_word); 181 static int issue_mfi_pthru(struct mrsas_instance *instance, struct 182 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 183 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct 184 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 185 static int issue_mfi_smp(struct mrsas_instance *instance, struct 186 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 187 static int issue_mfi_stp(struct mrsas_instance *instance, struct 188 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode); 189 static int abort_aen_cmd(struct mrsas_instance *instance, 190 struct mrsas_cmd *cmd_to_abort); 191 192 static void mrsas_rem_intrs(struct mrsas_instance *instance); 193 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type); 194 195 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *, 196 scsi_hba_tran_t *, struct scsi_device *); 197 static int mrsas_tran_bus_config(dev_info_t *, uint_t, 198 ddi_bus_config_op_t, void *, dev_info_t **); 199 static int mrsas_parse_devname(char *, int *, int *); 200 static int mrsas_config_all_devices(struct mrsas_instance *); 201 static int mrsas_config_ld(struct mrsas_instance *, uint16_t, 202 uint8_t, dev_info_t **); 203 static int mrsas_name_node(dev_info_t *, char *, int); 204 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *); 205 static void free_additional_dma_buffer(struct mrsas_instance *); 206 static void io_timeout_checker(void *); 207 static void mrsas_fm_init(struct mrsas_instance *); 208 static void mrsas_fm_fini(struct mrsas_instance *); 209 210 static struct mrsas_function_template mrsas_function_template_ppc = { 211 .read_fw_status_reg = read_fw_status_reg_ppc, 212 .issue_cmd = issue_cmd_ppc, 213 .issue_cmd_in_sync_mode = issue_cmd_in_sync_mode_ppc, 214 .issue_cmd_in_poll_mode = issue_cmd_in_poll_mode_ppc, 215 .enable_intr = enable_intr_ppc, 216 .disable_intr = disable_intr_ppc, 217 .intr_ack = intr_ack_ppc, 218 .init_adapter = mrsas_init_adapter_ppc 219 }; 220 221 222 static struct mrsas_function_template mrsas_function_template_fusion = { 223 .read_fw_status_reg = tbolt_read_fw_status_reg, 224 .issue_cmd = tbolt_issue_cmd, 225 .issue_cmd_in_sync_mode = tbolt_issue_cmd_in_sync_mode, 226 .issue_cmd_in_poll_mode = tbolt_issue_cmd_in_poll_mode, 227 .enable_intr = tbolt_enable_intr, 228 .disable_intr = tbolt_disable_intr, 229 .intr_ack = tbolt_intr_ack, 230 .init_adapter = mrsas_init_adapter_tbolt 231 }; 232 233 234 ddi_dma_attr_t mrsas_generic_dma_attr = { 235 DMA_ATTR_V0, /* dma_attr_version */ 236 0, /* low DMA address range */ 237 0xFFFFFFFFU, /* high DMA address range */ 238 0xFFFFFFFFU, /* DMA counter register */ 239 8, /* DMA address alignment */ 240 0x07, /* DMA burstsizes */ 241 1, /* min DMA size */ 242 0xFFFFFFFFU, /* max DMA size */ 243 0xFFFFFFFFU, /* segment boundary */ 244 MRSAS_MAX_SGE_CNT, /* dma_attr_sglen */ 245 512, /* granularity of device */ 246 0 /* bus specific DMA flags */ 247 }; 248 249 int32_t mrsas_max_cap_maxxfer = 0x1000000; 250 251 /* 252 * Fix for: Thunderbolt controller IO timeout when IO write size is 1MEG, 253 * Limit size to 256K 254 */ 255 uint32_t mrsas_tbolt_max_cap_maxxfer = (512 * 512); 256 257 /* 258 * cb_ops contains base level routines 259 */ 260 static struct cb_ops mrsas_cb_ops = { 261 mrsas_open, /* open */ 262 mrsas_close, /* close */ 263 nodev, /* strategy */ 264 nodev, /* print */ 265 nodev, /* dump */ 266 nodev, /* read */ 267 nodev, /* write */ 268 mrsas_ioctl, /* ioctl */ 269 nodev, /* devmap */ 270 nodev, /* mmap */ 271 nodev, /* segmap */ 272 nochpoll, /* poll */ 273 nodev, /* cb_prop_op */ 274 0, /* streamtab */ 275 D_NEW | D_HOTPLUG, /* cb_flag */ 276 CB_REV, /* cb_rev */ 277 nodev, /* cb_aread */ 278 nodev /* cb_awrite */ 279 }; 280 281 /* 282 * dev_ops contains configuration routines 283 */ 284 static struct dev_ops mrsas_ops = { 285 DEVO_REV, /* rev, */ 286 0, /* refcnt */ 287 mrsas_getinfo, /* getinfo */ 288 nulldev, /* identify */ 289 nulldev, /* probe */ 290 mrsas_attach, /* attach */ 291 mrsas_detach, /* detach */ 292 #ifdef __sparc 293 mrsas_reset, /* reset */ 294 #else /* __sparc */ 295 nodev, 296 #endif /* __sparc */ 297 &mrsas_cb_ops, /* char/block ops */ 298 NULL, /* bus ops */ 299 NULL, /* power */ 300 #ifdef __sparc 301 ddi_quiesce_not_needed 302 #else /* __sparc */ 303 mrsas_quiesce /* quiesce */ 304 #endif /* __sparc */ 305 }; 306 307 static struct modldrv modldrv = { 308 &mod_driverops, /* module type - driver */ 309 MRSAS_VERSION, 310 &mrsas_ops, /* driver ops */ 311 }; 312 313 static struct modlinkage modlinkage = { 314 MODREV_1, /* ml_rev - must be MODREV_1 */ 315 &modldrv, /* ml_linkage */ 316 NULL /* end of driver linkage */ 317 }; 318 319 static struct ddi_device_acc_attr endian_attr = { 320 DDI_DEVICE_ATTR_V1, 321 DDI_STRUCTURE_LE_ACC, 322 DDI_STRICTORDER_ACC, 323 DDI_DEFAULT_ACC 324 }; 325 326 /* Use the LSI Fast Path for the 2208 (tbolt) commands. */ 327 unsigned int enable_fp = 1; 328 329 330 /* 331 * ************************************************************************** * 332 * * 333 * common entry points - for loadable kernel modules * 334 * * 335 * ************************************************************************** * 336 */ 337 338 /* 339 * _init - initialize a loadable module 340 * @void 341 * 342 * The driver should perform any one-time resource allocation or data 343 * initialization during driver loading in _init(). For example, the driver 344 * should initialize any mutexes global to the driver in this routine. 345 * The driver should not, however, use _init() to allocate or initialize 346 * anything that has to do with a particular instance of the device. 347 * Per-instance initialization must be done in attach(). 348 */ 349 int 350 _init(void) 351 { 352 int ret; 353 354 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 355 356 ret = ddi_soft_state_init(&mrsas_state, 357 sizeof (struct mrsas_instance), 0); 358 359 if (ret != DDI_SUCCESS) { 360 cmn_err(CE_WARN, "mr_sas: could not init state"); 361 return (ret); 362 } 363 364 if ((ret = scsi_hba_init(&modlinkage)) != DDI_SUCCESS) { 365 cmn_err(CE_WARN, "mr_sas: could not init scsi hba"); 366 ddi_soft_state_fini(&mrsas_state); 367 return (ret); 368 } 369 370 ret = mod_install(&modlinkage); 371 372 if (ret != DDI_SUCCESS) { 373 cmn_err(CE_WARN, "mr_sas: mod_install failed"); 374 scsi_hba_fini(&modlinkage); 375 ddi_soft_state_fini(&mrsas_state); 376 } 377 378 return (ret); 379 } 380 381 /* 382 * _info - returns information about a loadable module. 383 * @void 384 * 385 * _info() is called to return module information. This is a typical entry 386 * point that does predefined role. It simply calls mod_info(). 387 */ 388 int 389 _info(struct modinfo *modinfop) 390 { 391 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 392 393 return (mod_info(&modlinkage, modinfop)); 394 } 395 396 /* 397 * _fini - prepare a loadable module for unloading 398 * @void 399 * 400 * In _fini(), the driver should release any resources that were allocated in 401 * _init(). The driver must remove itself from the system module list. 402 */ 403 int 404 _fini(void) 405 { 406 int ret; 407 408 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 409 410 if ((ret = mod_remove(&modlinkage)) != DDI_SUCCESS) { 411 con_log(CL_ANN1, 412 (CE_WARN, "_fini: mod_remove() failed, error 0x%X", ret)); 413 return (ret); 414 } 415 416 scsi_hba_fini(&modlinkage); 417 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: scsi_hba_fini() done.")); 418 419 ddi_soft_state_fini(&mrsas_state); 420 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: ddi_soft_state_fini() done.")); 421 422 return (ret); 423 } 424 425 426 /* 427 * ************************************************************************** * 428 * * 429 * common entry points - for autoconfiguration * 430 * * 431 * ************************************************************************** * 432 */ 433 /* 434 * attach - adds a device to the system as part of initialization 435 * @dip: 436 * @cmd: 437 * 438 * The kernel calls a driver's attach() entry point to attach an instance of 439 * a device (for MegaRAID, it is instance of a controller) or to resume 440 * operation for an instance of a device that has been suspended or has been 441 * shut down by the power management framework 442 * The attach() entry point typically includes the following types of 443 * processing: 444 * - allocate a soft-state structure for the device instance (for MegaRAID, 445 * controller instance) 446 * - initialize per-instance mutexes 447 * - initialize condition variables 448 * - register the device's interrupts (for MegaRAID, controller's interrupts) 449 * - map the registers and memory of the device instance (for MegaRAID, 450 * controller instance) 451 * - create minor device nodes for the device instance (for MegaRAID, 452 * controller instance) 453 * - report that the device instance (for MegaRAID, controller instance) has 454 * attached 455 */ 456 static int 457 mrsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 458 { 459 int instance_no; 460 int nregs; 461 int i = 0; 462 uint8_t irq; 463 uint16_t vendor_id; 464 uint16_t device_id; 465 uint16_t subsysvid; 466 uint16_t subsysid; 467 uint16_t command; 468 off_t reglength = 0; 469 int intr_types = 0; 470 char *data; 471 472 scsi_hba_tran_t *tran; 473 ddi_dma_attr_t tran_dma_attr; 474 struct mrsas_instance *instance; 475 476 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 477 478 /* CONSTCOND */ 479 ASSERT(NO_COMPETING_THREADS); 480 481 instance_no = ddi_get_instance(dip); 482 483 /* 484 * check to see whether this device is in a DMA-capable slot. 485 */ 486 if (ddi_slaveonly(dip) == DDI_SUCCESS) { 487 dev_err(dip, CE_WARN, "Device in slave-only slot, unused"); 488 return (DDI_FAILURE); 489 } 490 491 switch (cmd) { 492 case DDI_ATTACH: 493 /* allocate the soft state for the instance */ 494 if (ddi_soft_state_zalloc(mrsas_state, instance_no) 495 != DDI_SUCCESS) { 496 dev_err(dip, CE_WARN, "Failed to allocate soft state"); 497 return (DDI_FAILURE); 498 } 499 500 instance = (struct mrsas_instance *)ddi_get_soft_state 501 (mrsas_state, instance_no); 502 503 if (instance == NULL) { 504 dev_err(dip, CE_WARN, "Bad soft state"); 505 ddi_soft_state_free(mrsas_state, instance_no); 506 return (DDI_FAILURE); 507 } 508 509 instance->unroll.softs = 1; 510 511 /* Setup the PCI configuration space handles */ 512 if (pci_config_setup(dip, &instance->pci_handle) != 513 DDI_SUCCESS) { 514 dev_err(dip, CE_WARN, "pci config setup failed"); 515 516 ddi_soft_state_free(mrsas_state, instance_no); 517 return (DDI_FAILURE); 518 } 519 520 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) { 521 dev_err(dip, CE_WARN, "Failed to get registers"); 522 523 pci_config_teardown(&instance->pci_handle); 524 ddi_soft_state_free(mrsas_state, instance_no); 525 return (DDI_FAILURE); 526 } 527 528 vendor_id = pci_config_get16(instance->pci_handle, 529 PCI_CONF_VENID); 530 device_id = pci_config_get16(instance->pci_handle, 531 PCI_CONF_DEVID); 532 533 subsysvid = pci_config_get16(instance->pci_handle, 534 PCI_CONF_SUBVENID); 535 subsysid = pci_config_get16(instance->pci_handle, 536 PCI_CONF_SUBSYSID); 537 538 pci_config_put16(instance->pci_handle, PCI_CONF_COMM, 539 (pci_config_get16(instance->pci_handle, 540 PCI_CONF_COMM) | PCI_COMM_ME)); 541 irq = pci_config_get8(instance->pci_handle, 542 PCI_CONF_ILINE); 543 544 dev_err(dip, CE_CONT, 545 "?0x%x:0x%x 0x%x:0x%x, irq:%d drv-ver:%s\n", 546 vendor_id, device_id, subsysvid, 547 subsysid, irq, MRSAS_VERSION); 548 549 /* enable bus-mastering */ 550 command = pci_config_get16(instance->pci_handle, 551 PCI_CONF_COMM); 552 553 if (!(command & PCI_COMM_ME)) { 554 command |= PCI_COMM_ME; 555 556 pci_config_put16(instance->pci_handle, 557 PCI_CONF_COMM, command); 558 559 con_log(CL_ANN, (CE_CONT, "mr_sas%d: " 560 "enable bus-mastering", instance_no)); 561 } else { 562 con_log(CL_DLEVEL1, (CE_CONT, "mr_sas%d: " 563 "bus-mastering already set", instance_no)); 564 } 565 566 /* initialize function pointers */ 567 switch (device_id) { 568 case PCI_DEVICE_ID_LSI_INVADER: 569 case PCI_DEVICE_ID_LSI_FURY: 570 case PCI_DEVICE_ID_LSI_INTRUDER: 571 case PCI_DEVICE_ID_LSI_INTRUDER_24: 572 case PCI_DEVICE_ID_LSI_CUTLASS_52: 573 case PCI_DEVICE_ID_LSI_CUTLASS_53: 574 dev_err(dip, CE_CONT, "?Gen3 device detected\n"); 575 instance->gen3 = 1; 576 /* FALLTHROUGH */ 577 case PCI_DEVICE_ID_LSI_TBOLT: 578 dev_err(dip, CE_CONT, "?TBOLT device detected\n"); 579 580 instance->func_ptr = 581 &mrsas_function_template_fusion; 582 instance->tbolt = 1; 583 break; 584 585 case PCI_DEVICE_ID_LSI_SKINNY: 586 case PCI_DEVICE_ID_LSI_SKINNY_NEW: 587 /* 588 * FALLTHRU to PPC-style functions, but mark this 589 * instance as Skinny, because the register set is 590 * slightly different (See WR_IB_PICK_QPORT), and 591 * certain other features are available to a Skinny 592 * HBA. 593 */ 594 dev_err(dip, CE_CONT, "?Skinny device detected\n"); 595 instance->skinny = 1; 596 /* FALLTHRU */ 597 598 case PCI_DEVICE_ID_LSI_2108VDE: 599 case PCI_DEVICE_ID_LSI_2108V: 600 dev_err(dip, CE_CONT, 601 "?2108 Liberator device detected\n"); 602 603 instance->func_ptr = 604 &mrsas_function_template_ppc; 605 break; 606 607 default: 608 dev_err(dip, CE_WARN, "Invalid device detected"); 609 610 pci_config_teardown(&instance->pci_handle); 611 ddi_soft_state_free(mrsas_state, instance_no); 612 return (DDI_FAILURE); 613 } 614 615 instance->baseaddress = pci_config_get32( 616 instance->pci_handle, PCI_CONF_BASE0); 617 instance->baseaddress &= 0x0fffc; 618 619 instance->dip = dip; 620 instance->vendor_id = vendor_id; 621 instance->device_id = device_id; 622 instance->subsysvid = subsysvid; 623 instance->subsysid = subsysid; 624 instance->instance = instance_no; 625 626 /* Initialize FMA */ 627 instance->fm_capabilities = ddi_prop_get_int( 628 DDI_DEV_T_ANY, instance->dip, DDI_PROP_DONTPASS, 629 "fm-capable", DDI_FM_EREPORT_CAPABLE | 630 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE 631 | DDI_FM_ERRCB_CAPABLE); 632 633 mrsas_fm_init(instance); 634 635 /* Setup register map */ 636 if ((ddi_dev_regsize(instance->dip, 637 REGISTER_SET_IO_2108, ®length) != DDI_SUCCESS) || 638 reglength < MINIMUM_MFI_MEM_SZ) { 639 goto fail_attach; 640 } 641 if (reglength > DEFAULT_MFI_MEM_SZ) { 642 reglength = DEFAULT_MFI_MEM_SZ; 643 con_log(CL_DLEVEL1, (CE_NOTE, 644 "mr_sas: register length to map is 0x%lx bytes", 645 reglength)); 646 } 647 if (ddi_regs_map_setup(instance->dip, 648 REGISTER_SET_IO_2108, &instance->regmap, 0, 649 reglength, &endian_attr, &instance->regmap_handle) 650 != DDI_SUCCESS) { 651 dev_err(dip, CE_WARN, "couldn't map control registers"); 652 goto fail_attach; 653 } 654 655 instance->unroll.regs = 1; 656 657 /* 658 * Disable Interrupt Now. 659 * Setup Software interrupt 660 */ 661 instance->func_ptr->disable_intr(instance); 662 663 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 664 "mrsas-enable-msi", &data) == DDI_SUCCESS) { 665 if (strncmp(data, "no", 3) == 0) { 666 msi_enable = 0; 667 con_log(CL_ANN1, (CE_WARN, 668 "msi_enable = %d disabled", msi_enable)); 669 } 670 ddi_prop_free(data); 671 } 672 673 dev_err(dip, CE_CONT, "?msi_enable = %d\n", msi_enable); 674 675 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 676 "mrsas-enable-fp", &data) == DDI_SUCCESS) { 677 if (strncmp(data, "no", 3) == 0) { 678 enable_fp = 0; 679 dev_err(dip, CE_NOTE, 680 "enable_fp = %d, Fast-Path disabled.\n", 681 enable_fp); 682 } 683 684 ddi_prop_free(data); 685 } 686 687 dev_err(dip, CE_CONT, "?enable_fp = %d\n", enable_fp); 688 689 /* Check for all supported interrupt types */ 690 if (ddi_intr_get_supported_types( 691 dip, &intr_types) != DDI_SUCCESS) { 692 dev_err(dip, CE_WARN, 693 "ddi_intr_get_supported_types() failed"); 694 goto fail_attach; 695 } 696 697 con_log(CL_DLEVEL1, (CE_NOTE, 698 "ddi_intr_get_supported_types() ret: 0x%x", intr_types)); 699 700 /* Initialize and Setup Interrupt handler */ 701 if (msi_enable && (intr_types & DDI_INTR_TYPE_MSIX)) { 702 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSIX) != 703 DDI_SUCCESS) { 704 dev_err(dip, CE_WARN, 705 "MSIX interrupt query failed"); 706 goto fail_attach; 707 } 708 instance->intr_type = DDI_INTR_TYPE_MSIX; 709 } else if (msi_enable && (intr_types & DDI_INTR_TYPE_MSI)) { 710 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSI) != 711 DDI_SUCCESS) { 712 dev_err(dip, CE_WARN, 713 "MSI interrupt query failed"); 714 goto fail_attach; 715 } 716 instance->intr_type = DDI_INTR_TYPE_MSI; 717 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 718 msi_enable = 0; 719 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_FIXED) != 720 DDI_SUCCESS) { 721 dev_err(dip, CE_WARN, 722 "FIXED interrupt query failed"); 723 goto fail_attach; 724 } 725 instance->intr_type = DDI_INTR_TYPE_FIXED; 726 } else { 727 dev_err(dip, CE_WARN, "Device cannot " 728 "suppport either FIXED or MSI/X " 729 "interrupts"); 730 goto fail_attach; 731 } 732 733 instance->unroll.intr = 1; 734 735 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 736 "mrsas-enable-ctio", &data) == DDI_SUCCESS) { 737 if (strncmp(data, "no", 3) == 0) { 738 ctio_enable = 0; 739 con_log(CL_ANN1, (CE_WARN, 740 "ctio_enable = %d disabled", ctio_enable)); 741 } 742 ddi_prop_free(data); 743 } 744 745 dev_err(dip, CE_CONT, "?ctio_enable = %d\n", ctio_enable); 746 747 /* setup the mfi based low level driver */ 748 if (mrsas_init_adapter(instance) != DDI_SUCCESS) { 749 dev_err(dip, CE_WARN, 750 "could not initialize the low level driver"); 751 752 goto fail_attach; 753 } 754 755 /* Initialize all Mutex */ 756 INIT_LIST_HEAD(&instance->completed_pool_list); 757 mutex_init(&instance->completed_pool_mtx, NULL, 758 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 759 760 mutex_init(&instance->sync_map_mtx, NULL, 761 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 762 763 mutex_init(&instance->app_cmd_pool_mtx, NULL, 764 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 765 766 mutex_init(&instance->config_dev_mtx, NULL, 767 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 768 769 mutex_init(&instance->cmd_pend_mtx, NULL, 770 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 771 772 mutex_init(&instance->ocr_flags_mtx, NULL, 773 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 774 775 mutex_init(&instance->int_cmd_mtx, NULL, 776 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 777 cv_init(&instance->int_cmd_cv, NULL, CV_DRIVER, NULL); 778 779 mutex_init(&instance->cmd_pool_mtx, NULL, 780 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 781 782 mutex_init(&instance->reg_write_mtx, NULL, 783 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 784 785 if (instance->tbolt) { 786 mutex_init(&instance->cmd_app_pool_mtx, NULL, 787 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 788 789 mutex_init(&instance->chip_mtx, NULL, 790 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri)); 791 792 } 793 794 instance->unroll.mutexs = 1; 795 796 instance->timeout_id = (timeout_id_t)-1; 797 798 /* Register our soft-isr for highlevel interrupts. */ 799 instance->isr_level = instance->intr_pri; 800 if (!(instance->tbolt)) { 801 if (instance->isr_level == HIGH_LEVEL_INTR) { 802 if (ddi_add_softintr(dip, 803 DDI_SOFTINT_HIGH, 804 &instance->soft_intr_id, NULL, NULL, 805 mrsas_softintr, (caddr_t)instance) != 806 DDI_SUCCESS) { 807 dev_err(dip, CE_WARN, 808 "Software ISR did not register"); 809 810 goto fail_attach; 811 } 812 813 instance->unroll.soft_isr = 1; 814 815 } 816 } 817 818 instance->softint_running = 0; 819 820 /* Allocate a transport structure */ 821 tran = scsi_hba_tran_alloc(dip, SCSI_HBA_CANSLEEP); 822 823 if (tran == NULL) { 824 dev_err(dip, CE_WARN, 825 "scsi_hba_tran_alloc failed"); 826 goto fail_attach; 827 } 828 829 instance->tran = tran; 830 instance->unroll.tran = 1; 831 832 tran->tran_hba_private = instance; 833 tran->tran_tgt_init = mrsas_tran_tgt_init; 834 tran->tran_tgt_probe = scsi_hba_probe; 835 tran->tran_tgt_free = mrsas_tran_tgt_free; 836 tran->tran_init_pkt = mrsas_tran_init_pkt; 837 if (instance->tbolt) 838 tran->tran_start = mrsas_tbolt_tran_start; 839 else 840 tran->tran_start = mrsas_tran_start; 841 tran->tran_abort = mrsas_tran_abort; 842 tran->tran_reset = mrsas_tran_reset; 843 tran->tran_getcap = mrsas_tran_getcap; 844 tran->tran_setcap = mrsas_tran_setcap; 845 tran->tran_destroy_pkt = mrsas_tran_destroy_pkt; 846 tran->tran_dmafree = mrsas_tran_dmafree; 847 tran->tran_sync_pkt = mrsas_tran_sync_pkt; 848 tran->tran_quiesce = mrsas_tran_quiesce; 849 tran->tran_unquiesce = mrsas_tran_unquiesce; 850 tran->tran_bus_config = mrsas_tran_bus_config; 851 852 if (mrsas_relaxed_ordering) 853 mrsas_generic_dma_attr.dma_attr_flags |= 854 DDI_DMA_RELAXED_ORDERING; 855 856 857 tran_dma_attr = mrsas_generic_dma_attr; 858 tran_dma_attr.dma_attr_sgllen = instance->max_num_sge; 859 860 /* Attach this instance of the hba */ 861 if (scsi_hba_attach_setup(dip, &tran_dma_attr, tran, 0) 862 != DDI_SUCCESS) { 863 dev_err(dip, CE_WARN, 864 "scsi_hba_attach failed"); 865 866 goto fail_attach; 867 } 868 instance->unroll.tranSetup = 1; 869 con_log(CL_ANN1, 870 (CE_CONT, "scsi_hba_attach_setup() done.")); 871 872 /* create devctl node for cfgadm command */ 873 if (ddi_create_minor_node(dip, "devctl", 874 S_IFCHR, INST2DEVCTL(instance_no), 875 DDI_NT_SCSI_NEXUS, 0) == DDI_FAILURE) { 876 dev_err(dip, CE_WARN, "failed to create devctl node."); 877 878 goto fail_attach; 879 } 880 881 instance->unroll.devctl = 1; 882 883 /* create scsi node for cfgadm command */ 884 if (ddi_create_minor_node(dip, "scsi", S_IFCHR, 885 INST2SCSI(instance_no), DDI_NT_SCSI_ATTACHMENT_POINT, 0) == 886 DDI_FAILURE) { 887 dev_err(dip, CE_WARN, "failed to create scsi node."); 888 889 goto fail_attach; 890 } 891 892 instance->unroll.scsictl = 1; 893 894 (void) snprintf(instance->iocnode, sizeof (instance->iocnode), 895 "%d:lsirdctl", instance_no); 896 897 /* 898 * Create a node for applications 899 * for issuing ioctl to the driver. 900 */ 901 if (ddi_create_minor_node(dip, instance->iocnode, 902 S_IFCHR, INST2LSIRDCTL(instance_no), DDI_PSEUDO, 0) == 903 DDI_FAILURE) { 904 dev_err(dip, CE_WARN, "failed to create ioctl node."); 905 906 goto fail_attach; 907 } 908 909 instance->unroll.ioctl = 1; 910 911 /* Create a taskq to handle dr events */ 912 if ((instance->taskq = ddi_taskq_create(dip, 913 "mrsas_dr_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 914 dev_err(dip, CE_WARN, "failed to create taskq."); 915 instance->taskq = NULL; 916 goto fail_attach; 917 } 918 instance->unroll.taskq = 1; 919 con_log(CL_ANN1, (CE_CONT, "ddi_taskq_create() done.")); 920 921 /* enable interrupt */ 922 instance->func_ptr->enable_intr(instance); 923 924 /* initiate AEN */ 925 if (start_mfi_aen(instance)) { 926 dev_err(dip, CE_WARN, "failed to initiate AEN."); 927 goto fail_attach; 928 } 929 instance->unroll.aenPend = 1; 930 con_log(CL_ANN1, 931 (CE_CONT, "AEN started for instance %d.", instance_no)); 932 933 /* Finally! We are on the air. */ 934 ddi_report_dev(dip); 935 936 /* FMA handle checking. */ 937 if (mrsas_check_acc_handle(instance->regmap_handle) != 938 DDI_SUCCESS) { 939 goto fail_attach; 940 } 941 if (mrsas_check_acc_handle(instance->pci_handle) != 942 DDI_SUCCESS) { 943 goto fail_attach; 944 } 945 946 instance->mr_ld_list = 947 kmem_zalloc(MRDRV_MAX_LD * sizeof (struct mrsas_ld), 948 KM_SLEEP); 949 instance->unroll.ldlist_buff = 1; 950 951 #ifdef PDSUPPORT 952 if (instance->tbolt || instance->skinny) { 953 instance->mr_tbolt_pd_max = MRSAS_TBOLT_PD_TGT_MAX; 954 instance->mr_tbolt_pd_list = 955 kmem_zalloc(MRSAS_TBOLT_GET_PD_MAX(instance) * 956 sizeof (struct mrsas_tbolt_pd), KM_SLEEP); 957 ASSERT(instance->mr_tbolt_pd_list); 958 for (i = 0; i < instance->mr_tbolt_pd_max; i++) { 959 instance->mr_tbolt_pd_list[i].lun_type = 960 MRSAS_TBOLT_PD_LUN; 961 instance->mr_tbolt_pd_list[i].dev_id = 962 (uint8_t)i; 963 } 964 965 instance->unroll.pdlist_buff = 1; 966 } 967 #endif 968 break; 969 case DDI_PM_RESUME: 970 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_PM_RESUME")); 971 break; 972 case DDI_RESUME: 973 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_RESUME")); 974 break; 975 default: 976 con_log(CL_ANN, 977 (CE_WARN, "mr_sas: invalid attach cmd=%x", cmd)); 978 return (DDI_FAILURE); 979 } 980 981 982 con_log(CL_DLEVEL1, 983 (CE_NOTE, "mrsas_attach() return SUCCESS instance_num %d", 984 instance_no)); 985 return (DDI_SUCCESS); 986 987 fail_attach: 988 989 mrsas_undo_resources(dip, instance); 990 991 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 992 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 993 994 mrsas_fm_fini(instance); 995 996 pci_config_teardown(&instance->pci_handle); 997 ddi_soft_state_free(mrsas_state, instance_no); 998 999 return (DDI_FAILURE); 1000 } 1001 1002 /* 1003 * getinfo - gets device information 1004 * @dip: 1005 * @cmd: 1006 * @arg: 1007 * @resultp: 1008 * 1009 * The system calls getinfo() to obtain configuration information that only 1010 * the driver knows. The mapping of minor numbers to device instance is 1011 * entirely under the control of the driver. The system sometimes needs to ask 1012 * the driver which device a particular dev_t represents. 1013 * Given the device number return the devinfo pointer from the scsi_device 1014 * structure. 1015 */ 1016 /*ARGSUSED*/ 1017 static int 1018 mrsas_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **resultp) 1019 { 1020 int rval; 1021 int mrsas_minor = getminor((dev_t)arg); 1022 1023 struct mrsas_instance *instance; 1024 1025 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1026 1027 switch (cmd) { 1028 case DDI_INFO_DEVT2DEVINFO: 1029 instance = (struct mrsas_instance *) 1030 ddi_get_soft_state(mrsas_state, 1031 MINOR2INST(mrsas_minor)); 1032 1033 if (instance == NULL) { 1034 *resultp = NULL; 1035 rval = DDI_FAILURE; 1036 } else { 1037 *resultp = instance->dip; 1038 rval = DDI_SUCCESS; 1039 } 1040 break; 1041 case DDI_INFO_DEVT2INSTANCE: 1042 *resultp = (void *)(intptr_t) 1043 (MINOR2INST(getminor((dev_t)arg))); 1044 rval = DDI_SUCCESS; 1045 break; 1046 default: 1047 *resultp = NULL; 1048 rval = DDI_FAILURE; 1049 } 1050 1051 return (rval); 1052 } 1053 1054 /* 1055 * detach - detaches a device from the system 1056 * @dip: pointer to the device's dev_info structure 1057 * @cmd: type of detach 1058 * 1059 * A driver's detach() entry point is called to detach an instance of a device 1060 * that is bound to the driver. The entry point is called with the instance of 1061 * the device node to be detached and with DDI_DETACH, which is specified as 1062 * the cmd argument to the entry point. 1063 * This routine is called during driver unload. We free all the allocated 1064 * resources and call the corresponding LLD so that it can also release all 1065 * its resources. 1066 */ 1067 static int 1068 mrsas_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1069 { 1070 int instance_no; 1071 1072 struct mrsas_instance *instance; 1073 1074 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1075 1076 1077 /* CONSTCOND */ 1078 ASSERT(NO_COMPETING_THREADS); 1079 1080 instance_no = ddi_get_instance(dip); 1081 1082 instance = (struct mrsas_instance *)ddi_get_soft_state(mrsas_state, 1083 instance_no); 1084 1085 if (!instance) { 1086 dev_err(dip, CE_WARN, "could not get instance in detach"); 1087 1088 return (DDI_FAILURE); 1089 } 1090 1091 switch (cmd) { 1092 case DDI_DETACH: 1093 con_log(CL_ANN, (CE_NOTE, 1094 "mrsas_detach: DDI_DETACH")); 1095 1096 mutex_enter(&instance->config_dev_mtx); 1097 if (instance->timeout_id != (timeout_id_t)-1) { 1098 mutex_exit(&instance->config_dev_mtx); 1099 (void) untimeout(instance->timeout_id); 1100 instance->timeout_id = (timeout_id_t)-1; 1101 mutex_enter(&instance->config_dev_mtx); 1102 instance->unroll.timer = 0; 1103 } 1104 mutex_exit(&instance->config_dev_mtx); 1105 1106 if (instance->unroll.tranSetup == 1) { 1107 if (scsi_hba_detach(dip) != DDI_SUCCESS) { 1108 dev_err(dip, CE_WARN, 1109 "failed to detach"); 1110 return (DDI_FAILURE); 1111 } 1112 instance->unroll.tranSetup = 0; 1113 con_log(CL_ANN1, 1114 (CE_CONT, "scsi_hba_dettach() done.")); 1115 } 1116 1117 flush_cache(instance); 1118 1119 mrsas_undo_resources(dip, instance); 1120 1121 mrsas_fm_fini(instance); 1122 1123 pci_config_teardown(&instance->pci_handle); 1124 ddi_soft_state_free(mrsas_state, instance_no); 1125 break; 1126 1127 case DDI_PM_SUSPEND: 1128 con_log(CL_ANN, (CE_NOTE, 1129 "mrsas_detach: DDI_PM_SUSPEND")); 1130 1131 break; 1132 case DDI_SUSPEND: 1133 con_log(CL_ANN, (CE_NOTE, 1134 "mrsas_detach: DDI_SUSPEND")); 1135 1136 break; 1137 default: 1138 con_log(CL_ANN, (CE_WARN, 1139 "invalid detach command:0x%x", cmd)); 1140 return (DDI_FAILURE); 1141 } 1142 1143 return (DDI_SUCCESS); 1144 } 1145 1146 1147 static void 1148 mrsas_undo_resources(dev_info_t *dip, struct mrsas_instance *instance) 1149 { 1150 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1151 1152 if (instance->unroll.ioctl == 1) { 1153 ddi_remove_minor_node(dip, instance->iocnode); 1154 instance->unroll.ioctl = 0; 1155 } 1156 1157 if (instance->unroll.scsictl == 1) { 1158 ddi_remove_minor_node(dip, "scsi"); 1159 instance->unroll.scsictl = 0; 1160 } 1161 1162 if (instance->unroll.devctl == 1) { 1163 ddi_remove_minor_node(dip, "devctl"); 1164 instance->unroll.devctl = 0; 1165 } 1166 1167 if (instance->unroll.tranSetup == 1) { 1168 if (scsi_hba_detach(dip) != DDI_SUCCESS) { 1169 dev_err(dip, CE_WARN, "failed to detach"); 1170 return; /* DDI_FAILURE */ 1171 } 1172 instance->unroll.tranSetup = 0; 1173 con_log(CL_ANN1, (CE_CONT, "scsi_hba_dettach() done.")); 1174 } 1175 1176 if (instance->unroll.tran == 1) { 1177 scsi_hba_tran_free(instance->tran); 1178 instance->unroll.tran = 0; 1179 con_log(CL_ANN1, (CE_CONT, "scsi_hba_tran_free() done.")); 1180 } 1181 1182 if (instance->unroll.syncCmd == 1) { 1183 if (instance->tbolt) { 1184 if (abort_syncmap_cmd(instance, 1185 instance->map_update_cmd)) { 1186 dev_err(dip, CE_WARN, "mrsas_detach: " 1187 "failed to abort previous syncmap command"); 1188 } 1189 1190 instance->unroll.syncCmd = 0; 1191 con_log(CL_ANN1, (CE_CONT, "sync cmd aborted, done.")); 1192 } 1193 } 1194 1195 if (instance->unroll.aenPend == 1) { 1196 if (abort_aen_cmd(instance, instance->aen_cmd)) 1197 dev_err(dip, CE_WARN, "mrsas_detach: " 1198 "failed to abort prevous AEN command"); 1199 1200 instance->unroll.aenPend = 0; 1201 con_log(CL_ANN1, (CE_CONT, "aen cmd aborted, done.")); 1202 /* This means the controller is fully initialized and running */ 1203 /* Shutdown should be a last command to controller. */ 1204 /* shutdown_controller(); */ 1205 } 1206 1207 1208 if (instance->unroll.timer == 1) { 1209 if (instance->timeout_id != (timeout_id_t)-1) { 1210 (void) untimeout(instance->timeout_id); 1211 instance->timeout_id = (timeout_id_t)-1; 1212 1213 instance->unroll.timer = 0; 1214 } 1215 } 1216 1217 instance->func_ptr->disable_intr(instance); 1218 1219 1220 if (instance->unroll.mutexs == 1) { 1221 mutex_destroy(&instance->cmd_pool_mtx); 1222 mutex_destroy(&instance->app_cmd_pool_mtx); 1223 mutex_destroy(&instance->cmd_pend_mtx); 1224 mutex_destroy(&instance->completed_pool_mtx); 1225 mutex_destroy(&instance->sync_map_mtx); 1226 mutex_destroy(&instance->int_cmd_mtx); 1227 cv_destroy(&instance->int_cmd_cv); 1228 mutex_destroy(&instance->config_dev_mtx); 1229 mutex_destroy(&instance->ocr_flags_mtx); 1230 mutex_destroy(&instance->reg_write_mtx); 1231 1232 if (instance->tbolt) { 1233 mutex_destroy(&instance->cmd_app_pool_mtx); 1234 mutex_destroy(&instance->chip_mtx); 1235 } 1236 1237 instance->unroll.mutexs = 0; 1238 con_log(CL_ANN1, (CE_CONT, "Destroy mutex & cv, done.")); 1239 } 1240 1241 1242 if (instance->unroll.soft_isr == 1) { 1243 ddi_remove_softintr(instance->soft_intr_id); 1244 instance->unroll.soft_isr = 0; 1245 } 1246 1247 if (instance->unroll.intr == 1) { 1248 mrsas_rem_intrs(instance); 1249 instance->unroll.intr = 0; 1250 } 1251 1252 1253 if (instance->unroll.taskq == 1) { 1254 if (instance->taskq) { 1255 ddi_taskq_destroy(instance->taskq); 1256 instance->unroll.taskq = 0; 1257 } 1258 1259 } 1260 1261 /* 1262 * free dma memory allocated for 1263 * cmds/frames/queues/driver version etc 1264 */ 1265 if (instance->unroll.verBuff == 1) { 1266 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj); 1267 instance->unroll.verBuff = 0; 1268 } 1269 1270 if (instance->unroll.pdlist_buff == 1) { 1271 if (instance->mr_tbolt_pd_list != NULL) { 1272 kmem_free(instance->mr_tbolt_pd_list, 1273 MRSAS_TBOLT_GET_PD_MAX(instance) * 1274 sizeof (struct mrsas_tbolt_pd)); 1275 } 1276 1277 instance->mr_tbolt_pd_list = NULL; 1278 instance->unroll.pdlist_buff = 0; 1279 } 1280 1281 if (instance->unroll.ldlist_buff == 1) { 1282 if (instance->mr_ld_list != NULL) { 1283 kmem_free(instance->mr_ld_list, MRDRV_MAX_LD 1284 * sizeof (struct mrsas_ld)); 1285 } 1286 1287 instance->mr_ld_list = NULL; 1288 instance->unroll.ldlist_buff = 0; 1289 } 1290 1291 if (instance->tbolt) { 1292 if (instance->unroll.alloc_space_mpi2 == 1) { 1293 free_space_for_mpi2(instance); 1294 instance->unroll.alloc_space_mpi2 = 0; 1295 } 1296 } else { 1297 if (instance->unroll.alloc_space_mfi == 1) { 1298 free_space_for_mfi(instance); 1299 instance->unroll.alloc_space_mfi = 0; 1300 } 1301 } 1302 1303 if (instance->unroll.regs == 1) { 1304 ddi_regs_map_free(&instance->regmap_handle); 1305 instance->unroll.regs = 0; 1306 con_log(CL_ANN1, (CE_CONT, "ddi_regs_map_free() done.")); 1307 } 1308 } 1309 1310 1311 1312 /* 1313 * ************************************************************************** * 1314 * * 1315 * common entry points - for character driver types * 1316 * * 1317 * ************************************************************************** * 1318 */ 1319 /* 1320 * open - gets access to a device 1321 * @dev: 1322 * @openflags: 1323 * @otyp: 1324 * @credp: 1325 * 1326 * Access to a device by one or more application programs is controlled 1327 * through the open() and close() entry points. The primary function of 1328 * open() is to verify that the open request is allowed. 1329 */ 1330 static int 1331 mrsas_open(dev_t *dev, int openflags, int otyp, cred_t *credp) 1332 { 1333 int rval = 0; 1334 1335 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1336 1337 /* Check root permissions */ 1338 if (drv_priv(credp) != 0) { 1339 con_log(CL_ANN, (CE_WARN, 1340 "mr_sas: Non-root ioctl access denied!")); 1341 return (EPERM); 1342 } 1343 1344 /* Verify we are being opened as a character device */ 1345 if (otyp != OTYP_CHR) { 1346 con_log(CL_ANN, (CE_WARN, 1347 "mr_sas: ioctl node must be a char node")); 1348 return (EINVAL); 1349 } 1350 1351 if (ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(*dev))) 1352 == NULL) { 1353 return (ENXIO); 1354 } 1355 1356 if (scsi_hba_open) { 1357 rval = scsi_hba_open(dev, openflags, otyp, credp); 1358 } 1359 1360 return (rval); 1361 } 1362 1363 /* 1364 * close - gives up access to a device 1365 * @dev: 1366 * @openflags: 1367 * @otyp: 1368 * @credp: 1369 * 1370 * close() should perform any cleanup necessary to finish using the minor 1371 * device, and prepare the device (and driver) to be opened again. 1372 */ 1373 static int 1374 mrsas_close(dev_t dev, int openflags, int otyp, cred_t *credp) 1375 { 1376 int rval = 0; 1377 1378 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1379 1380 /* no need for locks! */ 1381 1382 if (scsi_hba_close) { 1383 rval = scsi_hba_close(dev, openflags, otyp, credp); 1384 } 1385 1386 return (rval); 1387 } 1388 1389 /* 1390 * ioctl - performs a range of I/O commands for character drivers 1391 * @dev: 1392 * @cmd: 1393 * @arg: 1394 * @mode: 1395 * @credp: 1396 * @rvalp: 1397 * 1398 * ioctl() routine must make sure that user data is copied into or out of the 1399 * kernel address space explicitly using copyin(), copyout(), ddi_copyin(), 1400 * and ddi_copyout(), as appropriate. 1401 * This is a wrapper routine to serialize access to the actual ioctl routine. 1402 * ioctl() should return 0 on success, or the appropriate error number. The 1403 * driver may also set the value returned to the calling process through rvalp. 1404 */ 1405 1406 static int 1407 mrsas_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1408 int *rvalp) 1409 { 1410 int rval = 0; 1411 1412 struct mrsas_instance *instance; 1413 struct mrsas_ioctl *ioctl; 1414 struct mrsas_aen aen; 1415 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1416 1417 instance = ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(dev))); 1418 1419 if (instance == NULL) { 1420 /* invalid minor number */ 1421 con_log(CL_ANN, (CE_WARN, "mr_sas: adapter not found.")); 1422 return (ENXIO); 1423 } 1424 1425 ioctl = (struct mrsas_ioctl *)kmem_zalloc(sizeof (struct mrsas_ioctl), 1426 KM_SLEEP); 1427 ASSERT(ioctl); 1428 1429 switch ((uint_t)cmd) { 1430 case MRSAS_IOCTL_FIRMWARE: 1431 if (ddi_copyin((void *)arg, ioctl, 1432 sizeof (struct mrsas_ioctl), mode)) { 1433 con_log(CL_ANN, (CE_WARN, "mrsas_ioctl: " 1434 "ERROR IOCTL copyin")); 1435 kmem_free(ioctl, sizeof (struct mrsas_ioctl)); 1436 return (EFAULT); 1437 } 1438 1439 if (ioctl->control_code == MRSAS_DRIVER_IOCTL_COMMON) { 1440 rval = handle_drv_ioctl(instance, ioctl, mode); 1441 } else { 1442 rval = handle_mfi_ioctl(instance, ioctl, mode); 1443 } 1444 1445 if (ddi_copyout((void *)ioctl, (void *)arg, 1446 (sizeof (struct mrsas_ioctl) - 1), mode)) { 1447 con_log(CL_ANN, (CE_WARN, 1448 "mrsas_ioctl: copy_to_user failed")); 1449 rval = 1; 1450 } 1451 1452 break; 1453 case MRSAS_IOCTL_AEN: 1454 if (ddi_copyin((void *) arg, &aen, 1455 sizeof (struct mrsas_aen), mode)) { 1456 con_log(CL_ANN, (CE_WARN, 1457 "mrsas_ioctl: ERROR AEN copyin")); 1458 kmem_free(ioctl, sizeof (struct mrsas_ioctl)); 1459 return (EFAULT); 1460 } 1461 1462 rval = handle_mfi_aen(instance, &aen); 1463 1464 if (ddi_copyout((void *) &aen, (void *)arg, 1465 sizeof (struct mrsas_aen), mode)) { 1466 con_log(CL_ANN, (CE_WARN, 1467 "mrsas_ioctl: copy_to_user failed")); 1468 rval = 1; 1469 } 1470 1471 break; 1472 default: 1473 rval = scsi_hba_ioctl(dev, cmd, arg, 1474 mode, credp, rvalp); 1475 1476 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_ioctl: " 1477 "scsi_hba_ioctl called, ret = %x.", rval)); 1478 } 1479 1480 kmem_free(ioctl, sizeof (struct mrsas_ioctl)); 1481 return (rval); 1482 } 1483 1484 /* 1485 * ************************************************************************** * 1486 * * 1487 * common entry points - for block driver types * 1488 * * 1489 * ************************************************************************** * 1490 */ 1491 #ifdef __sparc 1492 /* 1493 * reset - TBD 1494 * @dip: 1495 * @cmd: 1496 * 1497 * TBD 1498 */ 1499 /*ARGSUSED*/ 1500 static int 1501 mrsas_reset(dev_info_t *dip, ddi_reset_cmd_t cmd) 1502 { 1503 int instance_no; 1504 1505 struct mrsas_instance *instance; 1506 1507 instance_no = ddi_get_instance(dip); 1508 instance = (struct mrsas_instance *)ddi_get_soft_state 1509 (mrsas_state, instance_no); 1510 1511 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1512 1513 if (!instance) { 1514 con_log(CL_ANN, (CE_WARN, "mr_sas:%d could not get adapter " 1515 "in reset", instance_no)); 1516 return (DDI_FAILURE); 1517 } 1518 1519 instance->func_ptr->disable_intr(instance); 1520 1521 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d", 1522 instance_no)); 1523 1524 flush_cache(instance); 1525 1526 return (DDI_SUCCESS); 1527 } 1528 #else /* __sparc */ 1529 /*ARGSUSED*/ 1530 static int 1531 mrsas_quiesce(dev_info_t *dip) 1532 { 1533 int instance_no; 1534 1535 struct mrsas_instance *instance; 1536 1537 instance_no = ddi_get_instance(dip); 1538 instance = (struct mrsas_instance *)ddi_get_soft_state 1539 (mrsas_state, instance_no); 1540 1541 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1542 1543 if (!instance) { 1544 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d could not get adapter " 1545 "in quiesce", instance_no)); 1546 return (DDI_FAILURE); 1547 } 1548 if (instance->deadadapter || instance->adapterresetinprogress) { 1549 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d adapter is not in " 1550 "healthy state", instance_no)); 1551 return (DDI_FAILURE); 1552 } 1553 1554 if (abort_aen_cmd(instance, instance->aen_cmd)) { 1555 con_log(CL_ANN1, (CE_WARN, "mrsas_quiesce: " 1556 "failed to abort prevous AEN command QUIESCE")); 1557 } 1558 1559 if (instance->tbolt) { 1560 if (abort_syncmap_cmd(instance, 1561 instance->map_update_cmd)) { 1562 dev_err(dip, CE_WARN, 1563 "mrsas_detach: failed to abort " 1564 "previous syncmap command"); 1565 return (DDI_FAILURE); 1566 } 1567 } 1568 1569 instance->func_ptr->disable_intr(instance); 1570 1571 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d", 1572 instance_no)); 1573 1574 flush_cache(instance); 1575 1576 if (wait_for_outstanding(instance)) { 1577 con_log(CL_ANN1, 1578 (CE_CONT, "wait_for_outstanding: return FAIL.\n")); 1579 return (DDI_FAILURE); 1580 } 1581 return (DDI_SUCCESS); 1582 } 1583 #endif /* __sparc */ 1584 1585 /* 1586 * ************************************************************************** * 1587 * * 1588 * entry points (SCSI HBA) * 1589 * * 1590 * ************************************************************************** * 1591 */ 1592 /* 1593 * tran_tgt_init - initialize a target device instance 1594 * @hba_dip: 1595 * @tgt_dip: 1596 * @tran: 1597 * @sd: 1598 * 1599 * The tran_tgt_init() entry point enables the HBA to allocate and initialize 1600 * any per-target resources. tran_tgt_init() also enables the HBA to qualify 1601 * the device's address as valid and supportable for that particular HBA. 1602 * By returning DDI_FAILURE, the instance of the target driver for that device 1603 * is not probed or attached. 1604 */ 1605 /*ARGSUSED*/ 1606 static int 1607 mrsas_tran_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 1608 scsi_hba_tran_t *tran, struct scsi_device *sd) 1609 { 1610 struct mrsas_instance *instance; 1611 uint16_t tgt = sd->sd_address.a_target; 1612 uint8_t lun = sd->sd_address.a_lun; 1613 dev_info_t *child = NULL; 1614 1615 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init target %d lun %d", 1616 tgt, lun)); 1617 1618 instance = ADDR2MR(&sd->sd_address); 1619 1620 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 1621 /* 1622 * If no persistent node exists, we don't allow .conf node 1623 * to be created. 1624 */ 1625 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) { 1626 con_log(CL_DLEVEL2, 1627 (CE_NOTE, "mrsas_tgt_init find child =" 1628 " %p t = %d l = %d", (void *)child, tgt, lun)); 1629 if (ndi_merge_node(tgt_dip, mrsas_name_node) != 1630 DDI_SUCCESS) 1631 /* Create this .conf node */ 1632 return (DDI_SUCCESS); 1633 } 1634 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init in ndi_per " 1635 "DDI_FAILURE t = %d l = %d", tgt, lun)); 1636 return (DDI_FAILURE); 1637 1638 } 1639 1640 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init dev_dip %p tgt_dip %p", 1641 (void *)instance->mr_ld_list[tgt].dip, (void *)tgt_dip)); 1642 1643 if (tgt < MRDRV_MAX_LD && lun == 0) { 1644 if (instance->mr_ld_list[tgt].dip == NULL && 1645 strcmp(ddi_driver_name(sd->sd_dev), "sd") == 0) { 1646 mutex_enter(&instance->config_dev_mtx); 1647 instance->mr_ld_list[tgt].dip = tgt_dip; 1648 instance->mr_ld_list[tgt].lun_type = MRSAS_LD_LUN; 1649 instance->mr_ld_list[tgt].flag = MRDRV_TGT_VALID; 1650 mutex_exit(&instance->config_dev_mtx); 1651 } 1652 } 1653 1654 #ifdef PDSUPPORT 1655 else if (instance->tbolt || instance->skinny) { 1656 if (instance->mr_tbolt_pd_list[tgt].dip == NULL) { 1657 mutex_enter(&instance->config_dev_mtx); 1658 instance->mr_tbolt_pd_list[tgt].dip = tgt_dip; 1659 instance->mr_tbolt_pd_list[tgt].flag = 1660 MRDRV_TGT_VALID; 1661 mutex_exit(&instance->config_dev_mtx); 1662 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_tgt_init:" 1663 "t%xl%x", tgt, lun)); 1664 } 1665 } 1666 #endif 1667 1668 return (DDI_SUCCESS); 1669 } 1670 1671 /*ARGSUSED*/ 1672 static void 1673 mrsas_tran_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 1674 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 1675 { 1676 struct mrsas_instance *instance; 1677 int tgt = sd->sd_address.a_target; 1678 int lun = sd->sd_address.a_lun; 1679 1680 instance = ADDR2MR(&sd->sd_address); 1681 1682 con_log(CL_DLEVEL2, (CE_NOTE, "tgt_free t = %d l = %d", tgt, lun)); 1683 1684 if (tgt < MRDRV_MAX_LD && lun == 0) { 1685 if (instance->mr_ld_list[tgt].dip == tgt_dip) { 1686 mutex_enter(&instance->config_dev_mtx); 1687 instance->mr_ld_list[tgt].dip = NULL; 1688 mutex_exit(&instance->config_dev_mtx); 1689 } 1690 } 1691 1692 #ifdef PDSUPPORT 1693 else if (instance->tbolt || instance->skinny) { 1694 mutex_enter(&instance->config_dev_mtx); 1695 instance->mr_tbolt_pd_list[tgt].dip = NULL; 1696 mutex_exit(&instance->config_dev_mtx); 1697 con_log(CL_ANN1, (CE_NOTE, "tgt_free: Setting dip = NULL" 1698 "for tgt:%x", tgt)); 1699 } 1700 #endif 1701 1702 } 1703 1704 dev_info_t * 1705 mrsas_find_child(struct mrsas_instance *instance, uint16_t tgt, uint8_t lun) 1706 { 1707 dev_info_t *child = NULL; 1708 char addr[SCSI_MAXNAMELEN]; 1709 char tmp[MAXNAMELEN]; 1710 1711 (void) snprintf(addr, sizeof (addr), "%x,%x", tgt, lun); 1712 for (child = ddi_get_child(instance->dip); child; 1713 child = ddi_get_next_sibling(child)) { 1714 1715 if (ndi_dev_is_persistent_node(child) == 0) { 1716 continue; 1717 } 1718 1719 if (mrsas_name_node(child, tmp, MAXNAMELEN) != 1720 DDI_SUCCESS) { 1721 continue; 1722 } 1723 1724 if (strcmp(addr, tmp) == 0) { 1725 break; 1726 } 1727 } 1728 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_find_child: return child = %p", 1729 (void *)child)); 1730 return (child); 1731 } 1732 1733 /* 1734 * mrsas_name_node - 1735 * @dip: 1736 * @name: 1737 * @len: 1738 */ 1739 static int 1740 mrsas_name_node(dev_info_t *dip, char *name, int len) 1741 { 1742 int tgt, lun; 1743 1744 tgt = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1745 DDI_PROP_DONTPASS, "target", -1); 1746 con_log(CL_DLEVEL2, (CE_NOTE, 1747 "mrsas_name_node: dip %p tgt %d", (void *)dip, tgt)); 1748 if (tgt == -1) { 1749 return (DDI_FAILURE); 1750 } 1751 lun = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1752 "lun", -1); 1753 con_log(CL_DLEVEL2, 1754 (CE_NOTE, "mrsas_name_node: tgt %d lun %d", tgt, lun)); 1755 if (lun == -1) { 1756 return (DDI_FAILURE); 1757 } 1758 (void) snprintf(name, len, "%x,%x", tgt, lun); 1759 return (DDI_SUCCESS); 1760 } 1761 1762 /* 1763 * tran_init_pkt - allocate & initialize a scsi_pkt structure 1764 * @ap: 1765 * @pkt: 1766 * @bp: 1767 * @cmdlen: 1768 * @statuslen: 1769 * @tgtlen: 1770 * @flags: 1771 * @callback: 1772 * 1773 * The tran_init_pkt() entry point allocates and initializes a scsi_pkt 1774 * structure and DMA resources for a target driver request. The 1775 * tran_init_pkt() entry point is called when the target driver calls the 1776 * SCSA function scsi_init_pkt(). Each call of the tran_init_pkt() entry point 1777 * is a request to perform one or more of three possible services: 1778 * - allocation and initialization of a scsi_pkt structure 1779 * - allocation of DMA resources for data transfer 1780 * - reallocation of DMA resources for the next portion of the data transfer 1781 */ 1782 static struct scsi_pkt * 1783 mrsas_tran_init_pkt(struct scsi_address *ap, register struct scsi_pkt *pkt, 1784 struct buf *bp, int cmdlen, int statuslen, int tgtlen, 1785 int flags, int (*callback)(), caddr_t arg) 1786 { 1787 struct scsa_cmd *acmd; 1788 struct mrsas_instance *instance; 1789 struct scsi_pkt *new_pkt; 1790 1791 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1792 1793 instance = ADDR2MR(ap); 1794 1795 /* step #1 : pkt allocation */ 1796 if (pkt == NULL) { 1797 pkt = scsi_hba_pkt_alloc(instance->dip, ap, cmdlen, statuslen, 1798 tgtlen, sizeof (struct scsa_cmd), callback, arg); 1799 if (pkt == NULL) { 1800 return (NULL); 1801 } 1802 1803 acmd = PKT2CMD(pkt); 1804 1805 /* 1806 * Initialize the new pkt - we redundantly initialize 1807 * all the fields for illustrative purposes. 1808 */ 1809 acmd->cmd_pkt = pkt; 1810 acmd->cmd_flags = 0; 1811 acmd->cmd_scblen = statuslen; 1812 acmd->cmd_cdblen = cmdlen; 1813 acmd->cmd_dmahandle = NULL; 1814 acmd->cmd_ncookies = 0; 1815 acmd->cmd_cookie = 0; 1816 acmd->cmd_cookiecnt = 0; 1817 acmd->cmd_nwin = 0; 1818 1819 pkt->pkt_address = *ap; 1820 pkt->pkt_comp = (void (*)())NULL; 1821 pkt->pkt_flags = 0; 1822 pkt->pkt_time = 0; 1823 pkt->pkt_resid = 0; 1824 pkt->pkt_state = 0; 1825 pkt->pkt_statistics = 0; 1826 pkt->pkt_reason = 0; 1827 new_pkt = pkt; 1828 } else { 1829 acmd = PKT2CMD(pkt); 1830 new_pkt = NULL; 1831 } 1832 1833 /* step #2 : dma allocation/move */ 1834 if (bp && bp->b_bcount != 0) { 1835 if (acmd->cmd_dmahandle == NULL) { 1836 if (mrsas_dma_alloc(instance, pkt, bp, flags, 1837 callback) == DDI_FAILURE) { 1838 if (new_pkt) { 1839 scsi_hba_pkt_free(ap, new_pkt); 1840 } 1841 return ((struct scsi_pkt *)NULL); 1842 } 1843 } else { 1844 if (mrsas_dma_move(instance, pkt, bp) == DDI_FAILURE) { 1845 return ((struct scsi_pkt *)NULL); 1846 } 1847 } 1848 } 1849 1850 return (pkt); 1851 } 1852 1853 /* 1854 * tran_start - transport a SCSI command to the addressed target 1855 * @ap: 1856 * @pkt: 1857 * 1858 * The tran_start() entry point for a SCSI HBA driver is called to transport a 1859 * SCSI command to the addressed target. The SCSI command is described 1860 * entirely within the scsi_pkt structure, which the target driver allocated 1861 * through the HBA driver's tran_init_pkt() entry point. If the command 1862 * involves a data transfer, DMA resources must also have been allocated for 1863 * the scsi_pkt structure. 1864 * 1865 * Return Values : 1866 * TRAN_BUSY - request queue is full, no more free scbs 1867 * TRAN_ACCEPT - pkt has been submitted to the instance 1868 */ 1869 static int 1870 mrsas_tran_start(struct scsi_address *ap, register struct scsi_pkt *pkt) 1871 { 1872 uchar_t cmd_done = 0; 1873 1874 struct mrsas_instance *instance = ADDR2MR(ap); 1875 struct mrsas_cmd *cmd; 1876 1877 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 1878 if (instance->deadadapter == 1) { 1879 con_log(CL_ANN1, (CE_WARN, 1880 "mrsas_tran_start: return TRAN_FATAL_ERROR " 1881 "for IO, as the HBA doesnt take any more IOs")); 1882 if (pkt) { 1883 pkt->pkt_reason = CMD_DEV_GONE; 1884 pkt->pkt_statistics = STAT_DISCON; 1885 } 1886 return (TRAN_FATAL_ERROR); 1887 } 1888 1889 if (instance->adapterresetinprogress) { 1890 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_start: Reset flag set, " 1891 "returning mfi_pkt and setting TRAN_BUSY\n")); 1892 return (TRAN_BUSY); 1893 } 1894 1895 con_log(CL_ANN1, (CE_CONT, "chkpnt:%s:%d:SCSI CDB[0]=0x%x time:%x", 1896 __func__, __LINE__, pkt->pkt_cdbp[0], pkt->pkt_time)); 1897 1898 pkt->pkt_reason = CMD_CMPLT; 1899 *pkt->pkt_scbp = STATUS_GOOD; /* clear arq scsi_status */ 1900 1901 cmd = build_cmd(instance, ap, pkt, &cmd_done); 1902 1903 /* 1904 * Check if the command is already completed by the mrsas_build_cmd() 1905 * routine. In which case the busy_flag would be clear and scb will be 1906 * NULL and appropriate reason provided in pkt_reason field 1907 */ 1908 if (cmd_done) { 1909 pkt->pkt_reason = CMD_CMPLT; 1910 pkt->pkt_scbp[0] = STATUS_GOOD; 1911 pkt->pkt_state |= STATE_GOT_BUS | STATE_GOT_TARGET 1912 | STATE_SENT_CMD; 1913 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && pkt->pkt_comp) { 1914 (*pkt->pkt_comp)(pkt); 1915 } 1916 1917 return (TRAN_ACCEPT); 1918 } 1919 1920 if (cmd == NULL) { 1921 return (TRAN_BUSY); 1922 } 1923 1924 if ((pkt->pkt_flags & FLAG_NOINTR) == 0) { 1925 if (instance->fw_outstanding > instance->max_fw_cmds) { 1926 con_log(CL_ANN, (CE_CONT, "mr_sas:Firmware busy")); 1927 DTRACE_PROBE2(start_tran_err, 1928 uint16_t, instance->fw_outstanding, 1929 uint16_t, instance->max_fw_cmds); 1930 mrsas_return_mfi_pkt(instance, cmd); 1931 return (TRAN_BUSY); 1932 } 1933 1934 /* Synchronize the Cmd frame for the controller */ 1935 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0, 1936 DDI_DMA_SYNC_FORDEV); 1937 con_log(CL_ANN, (CE_CONT, "issue_cmd_ppc: SCSI CDB[0]=0x%x" 1938 "cmd->index:%x\n", pkt->pkt_cdbp[0], cmd->index)); 1939 instance->func_ptr->issue_cmd(cmd, instance); 1940 1941 } else { 1942 struct mrsas_header *hdr = &cmd->frame->hdr; 1943 1944 instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd); 1945 1946 pkt->pkt_reason = CMD_CMPLT; 1947 pkt->pkt_statistics = 0; 1948 pkt->pkt_state |= STATE_XFERRED_DATA | STATE_GOT_STATUS; 1949 1950 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, 1951 &hdr->cmd_status)) { 1952 case MFI_STAT_OK: 1953 pkt->pkt_scbp[0] = STATUS_GOOD; 1954 break; 1955 1956 case MFI_STAT_SCSI_DONE_WITH_ERROR: 1957 con_log(CL_ANN, (CE_CONT, 1958 "mrsas_tran_start: scsi done with error")); 1959 pkt->pkt_reason = CMD_CMPLT; 1960 pkt->pkt_statistics = 0; 1961 1962 ((struct scsi_status *)pkt->pkt_scbp)->sts_chk = 1; 1963 break; 1964 1965 case MFI_STAT_DEVICE_NOT_FOUND: 1966 con_log(CL_ANN, (CE_CONT, 1967 "mrsas_tran_start: device not found error")); 1968 pkt->pkt_reason = CMD_DEV_GONE; 1969 pkt->pkt_statistics = STAT_DISCON; 1970 break; 1971 1972 default: 1973 ((struct scsi_status *)pkt->pkt_scbp)->sts_busy = 1; 1974 } 1975 1976 (void) mrsas_common_check(instance, cmd); 1977 DTRACE_PROBE2(start_nointr_done, uint8_t, hdr->cmd, 1978 uint8_t, hdr->cmd_status); 1979 mrsas_return_mfi_pkt(instance, cmd); 1980 1981 if (pkt->pkt_comp) { 1982 (*pkt->pkt_comp)(pkt); 1983 } 1984 1985 } 1986 1987 return (TRAN_ACCEPT); 1988 } 1989 1990 /* 1991 * tran_abort - Abort any commands that are currently in transport 1992 * @ap: 1993 * @pkt: 1994 * 1995 * The tran_abort() entry point for a SCSI HBA driver is called to abort any 1996 * commands that are currently in transport for a particular target. This entry 1997 * point is called when a target driver calls scsi_abort(). The tran_abort() 1998 * entry point should attempt to abort the command denoted by the pkt 1999 * parameter. If the pkt parameter is NULL, tran_abort() should attempt to 2000 * abort all outstanding commands in the transport layer for the particular 2001 * target or logical unit. 2002 */ 2003 /*ARGSUSED*/ 2004 static int 2005 mrsas_tran_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 2006 { 2007 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2008 2009 /* abort command not supported by H/W */ 2010 2011 return (DDI_FAILURE); 2012 } 2013 2014 /* 2015 * tran_reset - reset either the SCSI bus or target 2016 * @ap: 2017 * @level: 2018 * 2019 * The tran_reset() entry point for a SCSI HBA driver is called to reset either 2020 * the SCSI bus or a particular SCSI target device. This entry point is called 2021 * when a target driver calls scsi_reset(). The tran_reset() entry point must 2022 * reset the SCSI bus if level is RESET_ALL. If level is RESET_TARGET, just the 2023 * particular target or logical unit must be reset. 2024 */ 2025 /*ARGSUSED*/ 2026 static int 2027 mrsas_tran_reset(struct scsi_address *ap, int level) 2028 { 2029 struct mrsas_instance *instance = ADDR2MR(ap); 2030 2031 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2032 2033 if (wait_for_outstanding(instance)) { 2034 con_log(CL_ANN1, 2035 (CE_CONT, "wait_for_outstanding: return FAIL.\n")); 2036 return (DDI_FAILURE); 2037 } else { 2038 return (DDI_SUCCESS); 2039 } 2040 } 2041 2042 /* 2043 * tran_getcap - get one of a set of SCSA-defined capabilities 2044 * @ap: 2045 * @cap: 2046 * @whom: 2047 * 2048 * The target driver can request the current setting of the capability for a 2049 * particular target by setting the whom parameter to nonzero. A whom value of 2050 * zero indicates a request for the current setting of the general capability 2051 * for the SCSI bus or for adapter hardware. The tran_getcap() should return -1 2052 * for undefined capabilities or the current value of the requested capability. 2053 */ 2054 /*ARGSUSED*/ 2055 static int 2056 mrsas_tran_getcap(struct scsi_address *ap, char *cap, int whom) 2057 { 2058 int rval = 0; 2059 2060 struct mrsas_instance *instance = ADDR2MR(ap); 2061 2062 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2063 2064 /* we do allow inquiring about capabilities for other targets */ 2065 if (cap == NULL) { 2066 return (-1); 2067 } 2068 2069 switch (scsi_hba_lookup_capstr(cap)) { 2070 case SCSI_CAP_DMA_MAX: 2071 if (instance->tbolt) { 2072 /* Limit to 256k max transfer */ 2073 rval = mrsas_tbolt_max_cap_maxxfer; 2074 } else { 2075 /* Limit to 16MB max transfer */ 2076 rval = mrsas_max_cap_maxxfer; 2077 } 2078 break; 2079 case SCSI_CAP_MSG_OUT: 2080 rval = 1; 2081 break; 2082 case SCSI_CAP_DISCONNECT: 2083 rval = 0; 2084 break; 2085 case SCSI_CAP_SYNCHRONOUS: 2086 rval = 0; 2087 break; 2088 case SCSI_CAP_WIDE_XFER: 2089 rval = 1; 2090 break; 2091 case SCSI_CAP_TAGGED_QING: 2092 rval = 1; 2093 break; 2094 case SCSI_CAP_UNTAGGED_QING: 2095 rval = 1; 2096 break; 2097 case SCSI_CAP_PARITY: 2098 rval = 1; 2099 break; 2100 case SCSI_CAP_INITIATOR_ID: 2101 rval = instance->init_id; 2102 break; 2103 case SCSI_CAP_ARQ: 2104 rval = 1; 2105 break; 2106 case SCSI_CAP_LINKED_CMDS: 2107 rval = 0; 2108 break; 2109 case SCSI_CAP_RESET_NOTIFICATION: 2110 rval = 1; 2111 break; 2112 case SCSI_CAP_GEOMETRY: 2113 rval = -1; 2114 2115 break; 2116 default: 2117 con_log(CL_DLEVEL2, (CE_NOTE, "Default cap coming 0x%x", 2118 scsi_hba_lookup_capstr(cap))); 2119 rval = -1; 2120 break; 2121 } 2122 2123 return (rval); 2124 } 2125 2126 /* 2127 * tran_setcap - set one of a set of SCSA-defined capabilities 2128 * @ap: 2129 * @cap: 2130 * @value: 2131 * @whom: 2132 * 2133 * The target driver might request that the new value be set for a particular 2134 * target by setting the whom parameter to nonzero. A whom value of zero 2135 * means that request is to set the new value for the SCSI bus or for adapter 2136 * hardware in general. 2137 * The tran_setcap() should return the following values as appropriate: 2138 * - -1 for undefined capabilities 2139 * - 0 if the HBA driver cannot set the capability to the requested value 2140 * - 1 if the HBA driver is able to set the capability to the requested value 2141 */ 2142 /*ARGSUSED*/ 2143 static int 2144 mrsas_tran_setcap(struct scsi_address *ap, char *cap, int value, int whom) 2145 { 2146 int rval = 1; 2147 2148 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2149 2150 /* We don't allow setting capabilities for other targets */ 2151 if (cap == NULL || whom == 0) { 2152 return (-1); 2153 } 2154 2155 switch (scsi_hba_lookup_capstr(cap)) { 2156 case SCSI_CAP_DMA_MAX: 2157 case SCSI_CAP_MSG_OUT: 2158 case SCSI_CAP_PARITY: 2159 case SCSI_CAP_LINKED_CMDS: 2160 case SCSI_CAP_RESET_NOTIFICATION: 2161 case SCSI_CAP_DISCONNECT: 2162 case SCSI_CAP_SYNCHRONOUS: 2163 case SCSI_CAP_UNTAGGED_QING: 2164 case SCSI_CAP_WIDE_XFER: 2165 case SCSI_CAP_INITIATOR_ID: 2166 case SCSI_CAP_ARQ: 2167 /* 2168 * None of these are settable via 2169 * the capability interface. 2170 */ 2171 break; 2172 case SCSI_CAP_TAGGED_QING: 2173 rval = 1; 2174 break; 2175 case SCSI_CAP_SECTOR_SIZE: 2176 rval = 1; 2177 break; 2178 2179 case SCSI_CAP_TOTAL_SECTORS: 2180 rval = 1; 2181 break; 2182 default: 2183 rval = -1; 2184 break; 2185 } 2186 2187 return (rval); 2188 } 2189 2190 /* 2191 * tran_destroy_pkt - deallocate scsi_pkt structure 2192 * @ap: 2193 * @pkt: 2194 * 2195 * The tran_destroy_pkt() entry point is the HBA driver function that 2196 * deallocates scsi_pkt structures. The tran_destroy_pkt() entry point is 2197 * called when the target driver calls scsi_destroy_pkt(). The 2198 * tran_destroy_pkt() entry point must free any DMA resources that have been 2199 * allocated for the packet. An implicit DMA synchronization occurs if the 2200 * DMA resources are freed and any cached data remains after the completion 2201 * of the transfer. 2202 */ 2203 static void 2204 mrsas_tran_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 2205 { 2206 struct scsa_cmd *acmd = PKT2CMD(pkt); 2207 2208 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2209 2210 if (acmd->cmd_flags & CFLAG_DMAVALID) { 2211 acmd->cmd_flags &= ~CFLAG_DMAVALID; 2212 2213 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle); 2214 2215 ddi_dma_free_handle(&acmd->cmd_dmahandle); 2216 2217 acmd->cmd_dmahandle = NULL; 2218 } 2219 2220 /* free the pkt */ 2221 scsi_hba_pkt_free(ap, pkt); 2222 } 2223 2224 /* 2225 * tran_dmafree - deallocates DMA resources 2226 * @ap: 2227 * @pkt: 2228 * 2229 * The tran_dmafree() entry point deallocates DMAQ resources that have been 2230 * allocated for a scsi_pkt structure. The tran_dmafree() entry point is 2231 * called when the target driver calls scsi_dmafree(). The tran_dmafree() must 2232 * free only DMA resources allocated for a scsi_pkt structure, not the 2233 * scsi_pkt itself. When DMA resources are freed, a DMA synchronization is 2234 * implicitly performed. 2235 */ 2236 /*ARGSUSED*/ 2237 static void 2238 mrsas_tran_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 2239 { 2240 register struct scsa_cmd *acmd = PKT2CMD(pkt); 2241 2242 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2243 2244 if (acmd->cmd_flags & CFLAG_DMAVALID) { 2245 acmd->cmd_flags &= ~CFLAG_DMAVALID; 2246 2247 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle); 2248 2249 ddi_dma_free_handle(&acmd->cmd_dmahandle); 2250 2251 acmd->cmd_dmahandle = NULL; 2252 } 2253 } 2254 2255 /* 2256 * tran_sync_pkt - synchronize the DMA object allocated 2257 * @ap: 2258 * @pkt: 2259 * 2260 * The tran_sync_pkt() entry point synchronizes the DMA object allocated for 2261 * the scsi_pkt structure before or after a DMA transfer. The tran_sync_pkt() 2262 * entry point is called when the target driver calls scsi_sync_pkt(). If the 2263 * data transfer direction is a DMA read from device to memory, tran_sync_pkt() 2264 * must synchronize the CPU's view of the data. If the data transfer direction 2265 * is a DMA write from memory to device, tran_sync_pkt() must synchronize the 2266 * device's view of the data. 2267 */ 2268 /*ARGSUSED*/ 2269 static void 2270 mrsas_tran_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 2271 { 2272 register struct scsa_cmd *acmd = PKT2CMD(pkt); 2273 2274 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2275 2276 if (acmd->cmd_flags & CFLAG_DMAVALID) { 2277 (void) ddi_dma_sync(acmd->cmd_dmahandle, acmd->cmd_dma_offset, 2278 acmd->cmd_dma_len, (acmd->cmd_flags & CFLAG_DMASEND) ? 2279 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 2280 } 2281 } 2282 2283 /*ARGSUSED*/ 2284 static int 2285 mrsas_tran_quiesce(dev_info_t *dip) 2286 { 2287 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2288 2289 return (1); 2290 } 2291 2292 /*ARGSUSED*/ 2293 static int 2294 mrsas_tran_unquiesce(dev_info_t *dip) 2295 { 2296 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2297 2298 return (1); 2299 } 2300 2301 2302 /* 2303 * mrsas_isr(caddr_t) 2304 * 2305 * The Interrupt Service Routine 2306 * 2307 * Collect status for all completed commands and do callback 2308 * 2309 */ 2310 static uint_t 2311 mrsas_isr(struct mrsas_instance *instance) 2312 { 2313 int need_softintr; 2314 uint32_t producer; 2315 uint32_t consumer; 2316 uint32_t context; 2317 int retval; 2318 2319 struct mrsas_cmd *cmd; 2320 struct mrsas_header *hdr; 2321 struct scsi_pkt *pkt; 2322 2323 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2324 ASSERT(instance); 2325 if (instance->tbolt) { 2326 mutex_enter(&instance->chip_mtx); 2327 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) && 2328 !(instance->func_ptr->intr_ack(instance))) { 2329 mutex_exit(&instance->chip_mtx); 2330 return (DDI_INTR_UNCLAIMED); 2331 } 2332 retval = mr_sas_tbolt_process_outstanding_cmd(instance); 2333 mutex_exit(&instance->chip_mtx); 2334 return (retval); 2335 } else { 2336 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) && 2337 !instance->func_ptr->intr_ack(instance)) { 2338 return (DDI_INTR_UNCLAIMED); 2339 } 2340 } 2341 2342 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle, 2343 0, 0, DDI_DMA_SYNC_FORCPU); 2344 2345 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle) 2346 != DDI_SUCCESS) { 2347 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 2348 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 2349 con_log(CL_ANN1, (CE_WARN, 2350 "mr_sas_isr(): FMA check, returning DDI_INTR_UNCLAIMED")); 2351 return (DDI_INTR_CLAIMED); 2352 } 2353 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 2354 2355 #ifdef OCRDEBUG 2356 if (debug_consecutive_timeout_after_ocr_g == 1) { 2357 con_log(CL_ANN1, (CE_NOTE, 2358 "simulating consecutive timeout after ocr")); 2359 return (DDI_INTR_CLAIMED); 2360 } 2361 #endif 2362 2363 mutex_enter(&instance->completed_pool_mtx); 2364 mutex_enter(&instance->cmd_pend_mtx); 2365 2366 producer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle, 2367 instance->producer); 2368 consumer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle, 2369 instance->consumer); 2370 2371 con_log(CL_ANN, (CE_CONT, " producer %x consumer %x ", 2372 producer, consumer)); 2373 if (producer == consumer) { 2374 con_log(CL_ANN, (CE_WARN, "producer == consumer case")); 2375 DTRACE_PROBE2(isr_pc_err, uint32_t, producer, 2376 uint32_t, consumer); 2377 mutex_exit(&instance->cmd_pend_mtx); 2378 mutex_exit(&instance->completed_pool_mtx); 2379 return (DDI_INTR_CLAIMED); 2380 } 2381 2382 while (consumer != producer) { 2383 context = ddi_get32(instance->mfi_internal_dma_obj.acc_handle, 2384 &instance->reply_queue[consumer]); 2385 cmd = instance->cmd_list[context]; 2386 2387 if (cmd->sync_cmd == MRSAS_TRUE) { 2388 hdr = (struct mrsas_header *)&cmd->frame->hdr; 2389 if (hdr) { 2390 mlist_del_init(&cmd->list); 2391 } 2392 } else { 2393 pkt = cmd->pkt; 2394 if (pkt) { 2395 mlist_del_init(&cmd->list); 2396 } 2397 } 2398 2399 mlist_add_tail(&cmd->list, &instance->completed_pool_list); 2400 2401 consumer++; 2402 if (consumer == (instance->max_fw_cmds + 1)) { 2403 consumer = 0; 2404 } 2405 } 2406 ddi_put32(instance->mfi_internal_dma_obj.acc_handle, 2407 instance->consumer, consumer); 2408 mutex_exit(&instance->cmd_pend_mtx); 2409 mutex_exit(&instance->completed_pool_mtx); 2410 2411 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle, 2412 0, 0, DDI_DMA_SYNC_FORDEV); 2413 2414 if (instance->softint_running) { 2415 need_softintr = 0; 2416 } else { 2417 need_softintr = 1; 2418 } 2419 2420 if (instance->isr_level == HIGH_LEVEL_INTR) { 2421 if (need_softintr) { 2422 ddi_trigger_softintr(instance->soft_intr_id); 2423 } 2424 } else { 2425 /* 2426 * Not a high-level interrupt, therefore call the soft level 2427 * interrupt explicitly 2428 */ 2429 (void) mrsas_softintr(instance); 2430 } 2431 2432 return (DDI_INTR_CLAIMED); 2433 } 2434 2435 2436 /* 2437 * ************************************************************************** * 2438 * * 2439 * libraries * 2440 * * 2441 * ************************************************************************** * 2442 */ 2443 /* 2444 * get_mfi_pkt : Get a command from the free pool 2445 * After successful allocation, the caller of this routine 2446 * must clear the frame buffer (memset to zero) before 2447 * using the packet further. 2448 * 2449 * ***** Note ***** 2450 * After clearing the frame buffer the context id of the 2451 * frame buffer SHOULD be restored back. 2452 */ 2453 struct mrsas_cmd * 2454 mrsas_get_mfi_pkt(struct mrsas_instance *instance) 2455 { 2456 mlist_t *head = &instance->cmd_pool_list; 2457 struct mrsas_cmd *cmd = NULL; 2458 2459 mutex_enter(&instance->cmd_pool_mtx); 2460 2461 if (!mlist_empty(head)) { 2462 cmd = mlist_entry(head->next, struct mrsas_cmd, list); 2463 mlist_del_init(head->next); 2464 } 2465 if (cmd != NULL) { 2466 cmd->pkt = NULL; 2467 cmd->retry_count_for_ocr = 0; 2468 cmd->drv_pkt_time = 0; 2469 2470 } 2471 mutex_exit(&instance->cmd_pool_mtx); 2472 2473 return (cmd); 2474 } 2475 2476 static struct mrsas_cmd * 2477 get_mfi_app_pkt(struct mrsas_instance *instance) 2478 { 2479 mlist_t *head = &instance->app_cmd_pool_list; 2480 struct mrsas_cmd *cmd = NULL; 2481 2482 mutex_enter(&instance->app_cmd_pool_mtx); 2483 2484 if (!mlist_empty(head)) { 2485 cmd = mlist_entry(head->next, struct mrsas_cmd, list); 2486 mlist_del_init(head->next); 2487 } 2488 if (cmd != NULL) { 2489 cmd->pkt = NULL; 2490 cmd->retry_count_for_ocr = 0; 2491 cmd->drv_pkt_time = 0; 2492 } 2493 2494 mutex_exit(&instance->app_cmd_pool_mtx); 2495 2496 return (cmd); 2497 } 2498 /* 2499 * return_mfi_pkt : Return a cmd to free command pool 2500 */ 2501 void 2502 mrsas_return_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 2503 { 2504 mutex_enter(&instance->cmd_pool_mtx); 2505 /* use mlist_add_tail for debug assistance */ 2506 mlist_add_tail(&cmd->list, &instance->cmd_pool_list); 2507 2508 mutex_exit(&instance->cmd_pool_mtx); 2509 } 2510 2511 static void 2512 return_mfi_app_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 2513 { 2514 mutex_enter(&instance->app_cmd_pool_mtx); 2515 2516 mlist_add(&cmd->list, &instance->app_cmd_pool_list); 2517 2518 mutex_exit(&instance->app_cmd_pool_mtx); 2519 } 2520 void 2521 push_pending_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 2522 { 2523 struct scsi_pkt *pkt; 2524 struct mrsas_header *hdr; 2525 con_log(CL_DLEVEL2, (CE_NOTE, "push_pending_pkt(): Called\n")); 2526 mutex_enter(&instance->cmd_pend_mtx); 2527 mlist_del_init(&cmd->list); 2528 mlist_add_tail(&cmd->list, &instance->cmd_pend_list); 2529 if (cmd->sync_cmd == MRSAS_TRUE) { 2530 hdr = (struct mrsas_header *)&cmd->frame->hdr; 2531 if (hdr) { 2532 con_log(CL_ANN1, (CE_CONT, 2533 "push_pending_mfi_pkt: " 2534 "cmd %p index %x " 2535 "time %llx", 2536 (void *)cmd, cmd->index, 2537 gethrtime())); 2538 /* Wait for specified interval */ 2539 cmd->drv_pkt_time = ddi_get16( 2540 cmd->frame_dma_obj.acc_handle, &hdr->timeout); 2541 if (cmd->drv_pkt_time < debug_timeout_g) 2542 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 2543 con_log(CL_ANN1, (CE_CONT, 2544 "push_pending_pkt(): " 2545 "Called IO Timeout Value %x\n", 2546 cmd->drv_pkt_time)); 2547 } 2548 if (hdr && instance->timeout_id == (timeout_id_t)-1) { 2549 instance->timeout_id = timeout(io_timeout_checker, 2550 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 2551 } 2552 } else { 2553 pkt = cmd->pkt; 2554 if (pkt) { 2555 con_log(CL_ANN1, (CE_CONT, 2556 "push_pending_mfi_pkt: " 2557 "cmd %p index %x pkt %p, " 2558 "time %llx", 2559 (void *)cmd, cmd->index, (void *)pkt, 2560 gethrtime())); 2561 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 2562 } 2563 if (pkt && instance->timeout_id == (timeout_id_t)-1) { 2564 instance->timeout_id = timeout(io_timeout_checker, 2565 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 2566 } 2567 } 2568 2569 mutex_exit(&instance->cmd_pend_mtx); 2570 2571 } 2572 2573 int 2574 mrsas_print_pending_cmds(struct mrsas_instance *instance) 2575 { 2576 mlist_t *head = &instance->cmd_pend_list; 2577 mlist_t *tmp = head; 2578 struct mrsas_cmd *cmd = NULL; 2579 struct mrsas_header *hdr; 2580 unsigned int flag = 1; 2581 struct scsi_pkt *pkt; 2582 int saved_level; 2583 int cmd_count = 0; 2584 2585 saved_level = debug_level_g; 2586 debug_level_g = CL_ANN1; 2587 2588 dev_err(instance->dip, CE_NOTE, 2589 "mrsas_print_pending_cmds(): Called"); 2590 2591 while (flag) { 2592 mutex_enter(&instance->cmd_pend_mtx); 2593 tmp = tmp->next; 2594 if (tmp == head) { 2595 mutex_exit(&instance->cmd_pend_mtx); 2596 flag = 0; 2597 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds():" 2598 " NO MORE CMDS PENDING....\n")); 2599 break; 2600 } else { 2601 cmd = mlist_entry(tmp, struct mrsas_cmd, list); 2602 mutex_exit(&instance->cmd_pend_mtx); 2603 if (cmd) { 2604 if (cmd->sync_cmd == MRSAS_TRUE) { 2605 hdr = (struct mrsas_header *) 2606 &cmd->frame->hdr; 2607 if (hdr) { 2608 con_log(CL_ANN1, (CE_CONT, 2609 "print: cmd %p index 0x%x " 2610 "drv_pkt_time 0x%x (NO-PKT)" 2611 " hdr %p\n", (void *)cmd, 2612 cmd->index, 2613 cmd->drv_pkt_time, 2614 (void *)hdr)); 2615 } 2616 } else { 2617 pkt = cmd->pkt; 2618 if (pkt) { 2619 con_log(CL_ANN1, (CE_CONT, 2620 "print: cmd %p index 0x%x " 2621 "drv_pkt_time 0x%x pkt %p \n", 2622 (void *)cmd, cmd->index, 2623 cmd->drv_pkt_time, (void *)pkt)); 2624 } 2625 } 2626 2627 if (++cmd_count == 1) { 2628 mrsas_print_cmd_details(instance, cmd, 2629 0xDD); 2630 } else { 2631 mrsas_print_cmd_details(instance, cmd, 2632 1); 2633 } 2634 2635 } 2636 } 2637 } 2638 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds(): Done\n")); 2639 2640 2641 debug_level_g = saved_level; 2642 2643 return (DDI_SUCCESS); 2644 } 2645 2646 2647 int 2648 mrsas_complete_pending_cmds(struct mrsas_instance *instance) 2649 { 2650 2651 struct mrsas_cmd *cmd = NULL; 2652 struct scsi_pkt *pkt; 2653 struct mrsas_header *hdr; 2654 2655 struct mlist_head *pos, *next; 2656 2657 con_log(CL_ANN1, (CE_NOTE, 2658 "mrsas_complete_pending_cmds(): Called")); 2659 2660 mutex_enter(&instance->cmd_pend_mtx); 2661 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) { 2662 cmd = mlist_entry(pos, struct mrsas_cmd, list); 2663 if (cmd) { 2664 pkt = cmd->pkt; 2665 if (pkt) { /* for IO */ 2666 if (((pkt->pkt_flags & FLAG_NOINTR) 2667 == 0) && pkt->pkt_comp) { 2668 pkt->pkt_reason 2669 = CMD_DEV_GONE; 2670 pkt->pkt_statistics 2671 = STAT_DISCON; 2672 con_log(CL_ANN1, (CE_CONT, 2673 "fail and posting to scsa " 2674 "cmd %p index %x" 2675 " pkt %p " 2676 "time : %llx", 2677 (void *)cmd, cmd->index, 2678 (void *)pkt, gethrtime())); 2679 (*pkt->pkt_comp)(pkt); 2680 } 2681 } else { /* for DCMDS */ 2682 if (cmd->sync_cmd == MRSAS_TRUE) { 2683 hdr = (struct mrsas_header *)&cmd->frame->hdr; 2684 con_log(CL_ANN1, (CE_CONT, 2685 "posting invalid status to application " 2686 "cmd %p index %x" 2687 " hdr %p " 2688 "time : %llx", 2689 (void *)cmd, cmd->index, 2690 (void *)hdr, gethrtime())); 2691 hdr->cmd_status = MFI_STAT_INVALID_STATUS; 2692 complete_cmd_in_sync_mode(instance, cmd); 2693 } 2694 } 2695 mlist_del_init(&cmd->list); 2696 } else { 2697 con_log(CL_ANN1, (CE_CONT, 2698 "mrsas_complete_pending_cmds:" 2699 "NULL command\n")); 2700 } 2701 con_log(CL_ANN1, (CE_CONT, 2702 "mrsas_complete_pending_cmds:" 2703 "looping for more commands\n")); 2704 } 2705 mutex_exit(&instance->cmd_pend_mtx); 2706 2707 con_log(CL_ANN1, (CE_CONT, "mrsas_complete_pending_cmds(): DONE\n")); 2708 return (DDI_SUCCESS); 2709 } 2710 2711 void 2712 mrsas_print_cmd_details(struct mrsas_instance *instance, struct mrsas_cmd *cmd, 2713 int detail) 2714 { 2715 struct scsi_pkt *pkt = cmd->pkt; 2716 Mpi2RaidSCSIIORequest_t *scsi_io = cmd->scsi_io_request; 2717 int i; 2718 int saved_level; 2719 ddi_acc_handle_t acc_handle = 2720 instance->mpi2_frame_pool_dma_obj.acc_handle; 2721 2722 if (detail == 0xDD) { 2723 saved_level = debug_level_g; 2724 debug_level_g = CL_ANN1; 2725 } 2726 2727 2728 if (instance->tbolt) { 2729 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p " 2730 "cmd->index 0x%x SMID 0x%x timer 0x%x sec\n", 2731 (void *)cmd, cmd->index, cmd->SMID, cmd->drv_pkt_time)); 2732 } else { 2733 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p " 2734 "cmd->index 0x%x timer 0x%x sec\n", 2735 (void *)cmd, cmd->index, cmd->drv_pkt_time)); 2736 } 2737 2738 if (pkt) { 2739 con_log(CL_ANN1, (CE_CONT, "scsi_pkt CDB[0]=0x%x", 2740 pkt->pkt_cdbp[0])); 2741 } else { 2742 con_log(CL_ANN1, (CE_CONT, "NO-PKT")); 2743 } 2744 2745 if ((detail == 0xDD) && instance->tbolt) { 2746 con_log(CL_ANN1, (CE_CONT, "RAID_SCSI_IO_REQUEST\n")); 2747 con_log(CL_ANN1, (CE_CONT, "DevHandle=0x%X Function=0x%X " 2748 "IoFlags=0x%X SGLFlags=0x%X DataLength=0x%X\n", 2749 ddi_get16(acc_handle, &scsi_io->DevHandle), 2750 ddi_get8(acc_handle, &scsi_io->Function), 2751 ddi_get16(acc_handle, &scsi_io->IoFlags), 2752 ddi_get16(acc_handle, &scsi_io->SGLFlags), 2753 ddi_get32(acc_handle, &scsi_io->DataLength))); 2754 2755 for (i = 0; i < 32; i++) { 2756 con_log(CL_ANN1, (CE_CONT, "CDB[%d]=0x%x ", i, 2757 ddi_get8(acc_handle, &scsi_io->CDB.CDB32[i]))); 2758 } 2759 2760 con_log(CL_ANN1, (CE_CONT, "RAID-CONTEXT\n")); 2761 con_log(CL_ANN1, (CE_CONT, "status=0x%X extStatus=0x%X " 2762 "ldTargetId=0x%X timeoutValue=0x%X regLockFlags=0x%X " 2763 "RAIDFlags=0x%X regLockRowLBA=0x%" PRIu64 2764 " regLockLength=0x%X spanArm=0x%X\n", 2765 ddi_get8(acc_handle, &scsi_io->RaidContext.status), 2766 ddi_get8(acc_handle, &scsi_io->RaidContext.extStatus), 2767 ddi_get16(acc_handle, &scsi_io->RaidContext.ldTargetId), 2768 ddi_get16(acc_handle, &scsi_io->RaidContext.timeoutValue), 2769 ddi_get8(acc_handle, &scsi_io->RaidContext.regLockFlags), 2770 ddi_get8(acc_handle, &scsi_io->RaidContext.RAIDFlags), 2771 ddi_get64(acc_handle, &scsi_io->RaidContext.regLockRowLBA), 2772 ddi_get32(acc_handle, &scsi_io->RaidContext.regLockLength), 2773 ddi_get8(acc_handle, &scsi_io->RaidContext.spanArm))); 2774 } 2775 2776 if (detail == 0xDD) { 2777 debug_level_g = saved_level; 2778 } 2779 } 2780 2781 2782 int 2783 mrsas_issue_pending_cmds(struct mrsas_instance *instance) 2784 { 2785 mlist_t *head = &instance->cmd_pend_list; 2786 mlist_t *tmp = head->next; 2787 struct mrsas_cmd *cmd = NULL; 2788 struct scsi_pkt *pkt; 2789 2790 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_pending_cmds(): Called")); 2791 while (tmp != head) { 2792 mutex_enter(&instance->cmd_pend_mtx); 2793 cmd = mlist_entry(tmp, struct mrsas_cmd, list); 2794 tmp = tmp->next; 2795 mutex_exit(&instance->cmd_pend_mtx); 2796 if (cmd) { 2797 con_log(CL_ANN1, (CE_CONT, 2798 "mrsas_issue_pending_cmds(): " 2799 "Got a cmd: cmd %p index 0x%x drv_pkt_time 0x%x ", 2800 (void *)cmd, cmd->index, cmd->drv_pkt_time)); 2801 2802 /* Reset command timeout value */ 2803 if (cmd->drv_pkt_time < debug_timeout_g) 2804 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 2805 2806 cmd->retry_count_for_ocr++; 2807 2808 dev_err(instance->dip, CE_CONT, 2809 "cmd retry count = %d\n", 2810 cmd->retry_count_for_ocr); 2811 2812 if (cmd->retry_count_for_ocr > IO_RETRY_COUNT) { 2813 dev_err(instance->dip, 2814 CE_WARN, "mrsas_issue_pending_cmds(): " 2815 "cmd->retry_count exceeded limit >%d\n", 2816 IO_RETRY_COUNT); 2817 mrsas_print_cmd_details(instance, cmd, 0xDD); 2818 2819 dev_err(instance->dip, CE_WARN, 2820 "mrsas_issue_pending_cmds():" 2821 "Calling KILL Adapter"); 2822 if (instance->tbolt) 2823 mrsas_tbolt_kill_adapter(instance); 2824 else 2825 (void) mrsas_kill_adapter(instance); 2826 return (DDI_FAILURE); 2827 } 2828 2829 pkt = cmd->pkt; 2830 if (pkt) { 2831 con_log(CL_ANN1, (CE_CONT, 2832 "PENDING PKT-CMD ISSUE: cmd %p index %x " 2833 "pkt %p time %llx", 2834 (void *)cmd, cmd->index, 2835 (void *)pkt, 2836 gethrtime())); 2837 2838 } else { 2839 dev_err(instance->dip, CE_CONT, 2840 "mrsas_issue_pending_cmds(): NO-PKT, " 2841 "cmd %p index 0x%x drv_pkt_time 0x%x", 2842 (void *)cmd, cmd->index, cmd->drv_pkt_time); 2843 } 2844 2845 2846 if (cmd->sync_cmd == MRSAS_TRUE) { 2847 dev_err(instance->dip, CE_CONT, 2848 "mrsas_issue_pending_cmds(): " 2849 "SYNC_CMD == TRUE \n"); 2850 instance->func_ptr->issue_cmd_in_sync_mode( 2851 instance, cmd); 2852 } else { 2853 instance->func_ptr->issue_cmd(cmd, instance); 2854 } 2855 } else { 2856 con_log(CL_ANN1, (CE_CONT, 2857 "mrsas_issue_pending_cmds: NULL command\n")); 2858 } 2859 con_log(CL_ANN1, (CE_CONT, 2860 "mrsas_issue_pending_cmds:" 2861 "looping for more commands")); 2862 } 2863 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_pending_cmds(): DONE\n")); 2864 return (DDI_SUCCESS); 2865 } 2866 2867 2868 2869 /* 2870 * destroy_mfi_frame_pool 2871 */ 2872 void 2873 destroy_mfi_frame_pool(struct mrsas_instance *instance) 2874 { 2875 int i; 2876 uint32_t max_cmd = instance->max_fw_cmds; 2877 2878 struct mrsas_cmd *cmd; 2879 2880 /* return all frames to pool */ 2881 2882 for (i = 0; i < max_cmd; i++) { 2883 2884 cmd = instance->cmd_list[i]; 2885 2886 if (cmd->frame_dma_obj_status == DMA_OBJ_ALLOCATED) 2887 (void) mrsas_free_dma_obj(instance, cmd->frame_dma_obj); 2888 2889 cmd->frame_dma_obj_status = DMA_OBJ_FREED; 2890 } 2891 2892 } 2893 2894 /* 2895 * create_mfi_frame_pool 2896 */ 2897 int 2898 create_mfi_frame_pool(struct mrsas_instance *instance) 2899 { 2900 int i = 0; 2901 int cookie_cnt; 2902 uint16_t max_cmd; 2903 uint16_t sge_sz; 2904 uint32_t sgl_sz; 2905 uint32_t tot_frame_size; 2906 struct mrsas_cmd *cmd; 2907 int retval = DDI_SUCCESS; 2908 2909 max_cmd = instance->max_fw_cmds; 2910 sge_sz = sizeof (struct mrsas_sge_ieee); 2911 /* calculated the number of 64byte frames required for SGL */ 2912 sgl_sz = sge_sz * instance->max_num_sge; 2913 tot_frame_size = sgl_sz + MRMFI_FRAME_SIZE + SENSE_LENGTH; 2914 2915 con_log(CL_DLEVEL3, (CE_NOTE, "create_mfi_frame_pool: " 2916 "sgl_sz %x tot_frame_size %x", sgl_sz, tot_frame_size)); 2917 2918 while (i < max_cmd) { 2919 cmd = instance->cmd_list[i]; 2920 2921 cmd->frame_dma_obj.size = tot_frame_size; 2922 cmd->frame_dma_obj.dma_attr = mrsas_generic_dma_attr; 2923 cmd->frame_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 2924 cmd->frame_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 2925 cmd->frame_dma_obj.dma_attr.dma_attr_sgllen = 1; 2926 cmd->frame_dma_obj.dma_attr.dma_attr_align = 64; 2927 2928 cookie_cnt = mrsas_alloc_dma_obj(instance, &cmd->frame_dma_obj, 2929 (uchar_t)DDI_STRUCTURE_LE_ACC); 2930 2931 if (cookie_cnt == -1 || cookie_cnt > 1) { 2932 dev_err(instance->dip, CE_WARN, 2933 "create_mfi_frame_pool: could not alloc."); 2934 retval = DDI_FAILURE; 2935 goto mrsas_undo_frame_pool; 2936 } 2937 2938 bzero(cmd->frame_dma_obj.buffer, tot_frame_size); 2939 2940 cmd->frame_dma_obj_status = DMA_OBJ_ALLOCATED; 2941 cmd->frame = (union mrsas_frame *)cmd->frame_dma_obj.buffer; 2942 cmd->frame_phys_addr = 2943 cmd->frame_dma_obj.dma_cookie[0].dmac_address; 2944 2945 cmd->sense = (uint8_t *)(((unsigned long) 2946 cmd->frame_dma_obj.buffer) + 2947 tot_frame_size - SENSE_LENGTH); 2948 cmd->sense_phys_addr = 2949 cmd->frame_dma_obj.dma_cookie[0].dmac_address + 2950 tot_frame_size - SENSE_LENGTH; 2951 2952 if (!cmd->frame || !cmd->sense) { 2953 dev_err(instance->dip, CE_WARN, 2954 "pci_pool_alloc failed"); 2955 retval = ENOMEM; 2956 goto mrsas_undo_frame_pool; 2957 } 2958 2959 ddi_put32(cmd->frame_dma_obj.acc_handle, 2960 &cmd->frame->io.context, cmd->index); 2961 i++; 2962 2963 con_log(CL_DLEVEL3, (CE_NOTE, "[%x]-%x", 2964 cmd->index, cmd->frame_phys_addr)); 2965 } 2966 2967 return (DDI_SUCCESS); 2968 2969 mrsas_undo_frame_pool: 2970 if (i > 0) 2971 destroy_mfi_frame_pool(instance); 2972 2973 return (retval); 2974 } 2975 2976 /* 2977 * free_additional_dma_buffer 2978 */ 2979 static void 2980 free_additional_dma_buffer(struct mrsas_instance *instance) 2981 { 2982 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) { 2983 (void) mrsas_free_dma_obj(instance, 2984 instance->mfi_internal_dma_obj); 2985 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED; 2986 } 2987 2988 if (instance->mfi_evt_detail_obj.status == DMA_OBJ_ALLOCATED) { 2989 (void) mrsas_free_dma_obj(instance, 2990 instance->mfi_evt_detail_obj); 2991 instance->mfi_evt_detail_obj.status = DMA_OBJ_FREED; 2992 } 2993 } 2994 2995 /* 2996 * alloc_additional_dma_buffer 2997 */ 2998 static int 2999 alloc_additional_dma_buffer(struct mrsas_instance *instance) 3000 { 3001 uint32_t reply_q_sz; 3002 uint32_t internal_buf_size = PAGESIZE*2; 3003 3004 /* max cmds plus 1 + producer & consumer */ 3005 reply_q_sz = sizeof (uint32_t) * (instance->max_fw_cmds + 1 + 2); 3006 3007 instance->mfi_internal_dma_obj.size = internal_buf_size; 3008 instance->mfi_internal_dma_obj.dma_attr = mrsas_generic_dma_attr; 3009 instance->mfi_internal_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 3010 instance->mfi_internal_dma_obj.dma_attr.dma_attr_count_max = 3011 0xFFFFFFFFU; 3012 instance->mfi_internal_dma_obj.dma_attr.dma_attr_sgllen = 1; 3013 3014 if (mrsas_alloc_dma_obj(instance, &instance->mfi_internal_dma_obj, 3015 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 3016 dev_err(instance->dip, CE_WARN, 3017 "could not alloc reply queue"); 3018 return (DDI_FAILURE); 3019 } 3020 3021 bzero(instance->mfi_internal_dma_obj.buffer, internal_buf_size); 3022 3023 instance->mfi_internal_dma_obj.status |= DMA_OBJ_ALLOCATED; 3024 3025 instance->producer = (uint32_t *)((unsigned long) 3026 instance->mfi_internal_dma_obj.buffer); 3027 instance->consumer = (uint32_t *)((unsigned long) 3028 instance->mfi_internal_dma_obj.buffer + 4); 3029 instance->reply_queue = (uint32_t *)((unsigned long) 3030 instance->mfi_internal_dma_obj.buffer + 8); 3031 instance->internal_buf = (caddr_t)(((unsigned long) 3032 instance->mfi_internal_dma_obj.buffer) + reply_q_sz + 8); 3033 instance->internal_buf_dmac_add = 3034 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 3035 (reply_q_sz + 8); 3036 instance->internal_buf_size = internal_buf_size - 3037 (reply_q_sz + 8); 3038 3039 /* allocate evt_detail */ 3040 instance->mfi_evt_detail_obj.size = sizeof (struct mrsas_evt_detail); 3041 instance->mfi_evt_detail_obj.dma_attr = mrsas_generic_dma_attr; 3042 instance->mfi_evt_detail_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 3043 instance->mfi_evt_detail_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 3044 instance->mfi_evt_detail_obj.dma_attr.dma_attr_sgllen = 1; 3045 instance->mfi_evt_detail_obj.dma_attr.dma_attr_align = 1; 3046 3047 if (mrsas_alloc_dma_obj(instance, &instance->mfi_evt_detail_obj, 3048 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 3049 dev_err(instance->dip, CE_WARN, "alloc_additional_dma_buffer: " 3050 "could not allocate data transfer buffer."); 3051 goto mrsas_undo_internal_buff; 3052 } 3053 3054 bzero(instance->mfi_evt_detail_obj.buffer, 3055 sizeof (struct mrsas_evt_detail)); 3056 3057 instance->mfi_evt_detail_obj.status |= DMA_OBJ_ALLOCATED; 3058 3059 return (DDI_SUCCESS); 3060 3061 mrsas_undo_internal_buff: 3062 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) { 3063 (void) mrsas_free_dma_obj(instance, 3064 instance->mfi_internal_dma_obj); 3065 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED; 3066 } 3067 3068 return (DDI_FAILURE); 3069 } 3070 3071 3072 void 3073 mrsas_free_cmd_pool(struct mrsas_instance *instance) 3074 { 3075 int i; 3076 uint32_t max_cmd; 3077 size_t sz; 3078 3079 /* already freed */ 3080 if (instance->cmd_list == NULL) { 3081 return; 3082 } 3083 3084 max_cmd = instance->max_fw_cmds; 3085 3086 /* size of cmd_list array */ 3087 sz = sizeof (struct mrsas_cmd *) * max_cmd; 3088 3089 /* First free each cmd */ 3090 for (i = 0; i < max_cmd; i++) { 3091 if (instance->cmd_list[i] != NULL) { 3092 kmem_free(instance->cmd_list[i], 3093 sizeof (struct mrsas_cmd)); 3094 } 3095 3096 instance->cmd_list[i] = NULL; 3097 } 3098 3099 /* Now, free cmd_list array */ 3100 if (instance->cmd_list != NULL) 3101 kmem_free(instance->cmd_list, sz); 3102 3103 instance->cmd_list = NULL; 3104 3105 INIT_LIST_HEAD(&instance->cmd_pool_list); 3106 INIT_LIST_HEAD(&instance->cmd_pend_list); 3107 if (instance->tbolt) { 3108 INIT_LIST_HEAD(&instance->cmd_app_pool_list); 3109 } else { 3110 INIT_LIST_HEAD(&instance->app_cmd_pool_list); 3111 } 3112 3113 } 3114 3115 3116 /* 3117 * mrsas_alloc_cmd_pool 3118 */ 3119 int 3120 mrsas_alloc_cmd_pool(struct mrsas_instance *instance) 3121 { 3122 int i; 3123 int count; 3124 uint32_t max_cmd; 3125 uint32_t reserve_cmd; 3126 size_t sz; 3127 3128 struct mrsas_cmd *cmd; 3129 3130 max_cmd = instance->max_fw_cmds; 3131 con_log(CL_ANN1, (CE_NOTE, "mrsas_alloc_cmd_pool: " 3132 "max_cmd %x", max_cmd)); 3133 3134 3135 sz = sizeof (struct mrsas_cmd *) * max_cmd; 3136 3137 /* 3138 * instance->cmd_list is an array of struct mrsas_cmd pointers. 3139 * Allocate the dynamic array first and then allocate individual 3140 * commands. 3141 */ 3142 instance->cmd_list = kmem_zalloc(sz, KM_SLEEP); 3143 ASSERT(instance->cmd_list); 3144 3145 /* create a frame pool and assign one frame to each cmd */ 3146 for (count = 0; count < max_cmd; count++) { 3147 instance->cmd_list[count] = 3148 kmem_zalloc(sizeof (struct mrsas_cmd), KM_SLEEP); 3149 ASSERT(instance->cmd_list[count]); 3150 } 3151 3152 /* add all the commands to command pool */ 3153 3154 INIT_LIST_HEAD(&instance->cmd_pool_list); 3155 INIT_LIST_HEAD(&instance->cmd_pend_list); 3156 INIT_LIST_HEAD(&instance->app_cmd_pool_list); 3157 3158 /* 3159 * When max_cmd is lower than MRSAS_APP_RESERVED_CMDS, how do I split 3160 * into app_cmd and regular cmd? For now, just take 3161 * max(1/8th of max, 4); 3162 */ 3163 reserve_cmd = min(MRSAS_APP_RESERVED_CMDS, 3164 max(max_cmd >> 3, MRSAS_APP_MIN_RESERVED_CMDS)); 3165 3166 for (i = 0; i < reserve_cmd; i++) { 3167 cmd = instance->cmd_list[i]; 3168 cmd->index = i; 3169 mlist_add_tail(&cmd->list, &instance->app_cmd_pool_list); 3170 } 3171 3172 3173 for (i = reserve_cmd; i < max_cmd; i++) { 3174 cmd = instance->cmd_list[i]; 3175 cmd->index = i; 3176 mlist_add_tail(&cmd->list, &instance->cmd_pool_list); 3177 } 3178 3179 return (DDI_SUCCESS); 3180 3181 mrsas_undo_cmds: 3182 if (count > 0) { 3183 /* free each cmd */ 3184 for (i = 0; i < count; i++) { 3185 if (instance->cmd_list[i] != NULL) { 3186 kmem_free(instance->cmd_list[i], 3187 sizeof (struct mrsas_cmd)); 3188 } 3189 instance->cmd_list[i] = NULL; 3190 } 3191 } 3192 3193 mrsas_undo_cmd_list: 3194 if (instance->cmd_list != NULL) 3195 kmem_free(instance->cmd_list, sz); 3196 instance->cmd_list = NULL; 3197 3198 return (DDI_FAILURE); 3199 } 3200 3201 3202 /* 3203 * free_space_for_mfi 3204 */ 3205 static void 3206 free_space_for_mfi(struct mrsas_instance *instance) 3207 { 3208 3209 /* already freed */ 3210 if (instance->cmd_list == NULL) { 3211 return; 3212 } 3213 3214 /* Free additional dma buffer */ 3215 free_additional_dma_buffer(instance); 3216 3217 /* Free the MFI frame pool */ 3218 destroy_mfi_frame_pool(instance); 3219 3220 /* Free all the commands in the cmd_list */ 3221 /* Free the cmd_list buffer itself */ 3222 mrsas_free_cmd_pool(instance); 3223 } 3224 3225 /* 3226 * alloc_space_for_mfi 3227 */ 3228 static int 3229 alloc_space_for_mfi(struct mrsas_instance *instance) 3230 { 3231 /* Allocate command pool (memory for cmd_list & individual commands) */ 3232 if (mrsas_alloc_cmd_pool(instance)) { 3233 dev_err(instance->dip, CE_WARN, "error creating cmd pool"); 3234 return (DDI_FAILURE); 3235 } 3236 3237 /* Allocate MFI Frame pool */ 3238 if (create_mfi_frame_pool(instance)) { 3239 dev_err(instance->dip, CE_WARN, 3240 "error creating frame DMA pool"); 3241 goto mfi_undo_cmd_pool; 3242 } 3243 3244 /* Allocate additional DMA buffer */ 3245 if (alloc_additional_dma_buffer(instance)) { 3246 dev_err(instance->dip, CE_WARN, 3247 "error creating frame DMA pool"); 3248 goto mfi_undo_frame_pool; 3249 } 3250 3251 return (DDI_SUCCESS); 3252 3253 mfi_undo_frame_pool: 3254 destroy_mfi_frame_pool(instance); 3255 3256 mfi_undo_cmd_pool: 3257 mrsas_free_cmd_pool(instance); 3258 3259 return (DDI_FAILURE); 3260 } 3261 3262 3263 3264 /* 3265 * get_ctrl_info 3266 */ 3267 static int 3268 get_ctrl_info(struct mrsas_instance *instance, 3269 struct mrsas_ctrl_info *ctrl_info) 3270 { 3271 int ret = 0; 3272 3273 struct mrsas_cmd *cmd; 3274 struct mrsas_dcmd_frame *dcmd; 3275 struct mrsas_ctrl_info *ci; 3276 3277 if (instance->tbolt) { 3278 cmd = get_raid_msg_mfi_pkt(instance); 3279 } else { 3280 cmd = mrsas_get_mfi_pkt(instance); 3281 } 3282 3283 if (!cmd) { 3284 con_log(CL_ANN, (CE_WARN, 3285 "Failed to get a cmd for ctrl info")); 3286 DTRACE_PROBE2(info_mfi_err, uint16_t, instance->fw_outstanding, 3287 uint16_t, instance->max_fw_cmds); 3288 return (DDI_FAILURE); 3289 } 3290 3291 /* Clear the frame buffer and assign back the context id */ 3292 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3293 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 3294 cmd->index); 3295 3296 dcmd = &cmd->frame->dcmd; 3297 3298 ci = (struct mrsas_ctrl_info *)instance->internal_buf; 3299 3300 if (!ci) { 3301 dev_err(instance->dip, CE_WARN, 3302 "Failed to alloc mem for ctrl info"); 3303 mrsas_return_mfi_pkt(instance, cmd); 3304 return (DDI_FAILURE); 3305 } 3306 3307 (void) memset(ci, 0, sizeof (struct mrsas_ctrl_info)); 3308 3309 /* for( i = 0; i < DCMD_MBOX_SZ; i++ ) dcmd->mbox.b[i] = 0; */ 3310 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 3311 3312 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 3313 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 3314 MFI_CMD_STATUS_POLL_MODE); 3315 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1); 3316 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 3317 MFI_FRAME_DIR_READ); 3318 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 3319 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 3320 sizeof (struct mrsas_ctrl_info)); 3321 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 3322 MR_DCMD_CTRL_GET_INFO); 3323 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr, 3324 instance->internal_buf_dmac_add); 3325 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length, 3326 sizeof (struct mrsas_ctrl_info)); 3327 3328 cmd->frame_count = 1; 3329 3330 if (instance->tbolt) { 3331 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 3332 } 3333 3334 if (!instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 3335 ret = 0; 3336 3337 ctrl_info->max_request_size = ddi_get32( 3338 cmd->frame_dma_obj.acc_handle, &ci->max_request_size); 3339 3340 ctrl_info->ld_present_count = ddi_get16( 3341 cmd->frame_dma_obj.acc_handle, &ci->ld_present_count); 3342 3343 ctrl_info->properties.on_off_properties = ddi_get32( 3344 cmd->frame_dma_obj.acc_handle, 3345 &ci->properties.on_off_properties); 3346 ddi_rep_get8(cmd->frame_dma_obj.acc_handle, 3347 (uint8_t *)(ctrl_info->product_name), 3348 (uint8_t *)(ci->product_name), 80 * sizeof (char), 3349 DDI_DEV_AUTOINCR); 3350 /* should get more members of ci with ddi_get when needed */ 3351 } else { 3352 dev_err(instance->dip, CE_WARN, 3353 "get_ctrl_info: Ctrl info failed"); 3354 ret = -1; 3355 } 3356 3357 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) { 3358 ret = -1; 3359 } 3360 if (instance->tbolt) { 3361 return_raid_msg_mfi_pkt(instance, cmd); 3362 } else { 3363 mrsas_return_mfi_pkt(instance, cmd); 3364 } 3365 3366 return (ret); 3367 } 3368 3369 /* 3370 * abort_aen_cmd 3371 */ 3372 static int 3373 abort_aen_cmd(struct mrsas_instance *instance, 3374 struct mrsas_cmd *cmd_to_abort) 3375 { 3376 int ret = 0; 3377 3378 struct mrsas_cmd *cmd; 3379 struct mrsas_abort_frame *abort_fr; 3380 3381 con_log(CL_ANN1, (CE_NOTE, "chkpnt: abort_aen:%d", __LINE__)); 3382 3383 if (instance->tbolt) { 3384 cmd = get_raid_msg_mfi_pkt(instance); 3385 } else { 3386 cmd = mrsas_get_mfi_pkt(instance); 3387 } 3388 3389 if (!cmd) { 3390 con_log(CL_ANN1, (CE_WARN, 3391 "abort_aen_cmd():Failed to get a cmd for abort_aen_cmd")); 3392 DTRACE_PROBE2(abort_mfi_err, uint16_t, instance->fw_outstanding, 3393 uint16_t, instance->max_fw_cmds); 3394 return (DDI_FAILURE); 3395 } 3396 3397 /* Clear the frame buffer and assign back the context id */ 3398 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3399 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 3400 cmd->index); 3401 3402 abort_fr = &cmd->frame->abort; 3403 3404 /* prepare and issue the abort frame */ 3405 ddi_put8(cmd->frame_dma_obj.acc_handle, 3406 &abort_fr->cmd, MFI_CMD_OP_ABORT); 3407 ddi_put8(cmd->frame_dma_obj.acc_handle, &abort_fr->cmd_status, 3408 MFI_CMD_STATUS_SYNC_MODE); 3409 ddi_put16(cmd->frame_dma_obj.acc_handle, &abort_fr->flags, 0); 3410 ddi_put32(cmd->frame_dma_obj.acc_handle, &abort_fr->abort_context, 3411 cmd_to_abort->index); 3412 ddi_put32(cmd->frame_dma_obj.acc_handle, 3413 &abort_fr->abort_mfi_phys_addr_lo, cmd_to_abort->frame_phys_addr); 3414 ddi_put32(cmd->frame_dma_obj.acc_handle, 3415 &abort_fr->abort_mfi_phys_addr_hi, 0); 3416 3417 instance->aen_cmd->abort_aen = 1; 3418 3419 cmd->frame_count = 1; 3420 3421 if (instance->tbolt) { 3422 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 3423 } 3424 3425 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 3426 con_log(CL_ANN1, (CE_WARN, 3427 "abort_aen_cmd: issue_cmd_in_poll_mode failed")); 3428 ret = -1; 3429 } else { 3430 ret = 0; 3431 } 3432 3433 instance->aen_cmd->abort_aen = 1; 3434 instance->aen_cmd = 0; 3435 3436 if (instance->tbolt) { 3437 return_raid_msg_mfi_pkt(instance, cmd); 3438 } else { 3439 mrsas_return_mfi_pkt(instance, cmd); 3440 } 3441 3442 atomic_add_16(&instance->fw_outstanding, (-1)); 3443 3444 return (ret); 3445 } 3446 3447 3448 static int 3449 mrsas_build_init_cmd(struct mrsas_instance *instance, 3450 struct mrsas_cmd **cmd_ptr) 3451 { 3452 struct mrsas_cmd *cmd; 3453 struct mrsas_init_frame *init_frame; 3454 struct mrsas_init_queue_info *initq_info; 3455 struct mrsas_drv_ver drv_ver_info; 3456 3457 3458 /* 3459 * Prepare a init frame. Note the init frame points to queue info 3460 * structure. Each frame has SGL allocated after first 64 bytes. For 3461 * this frame - since we don't need any SGL - we use SGL's space as 3462 * queue info structure 3463 */ 3464 cmd = *cmd_ptr; 3465 3466 3467 /* Clear the frame buffer and assign back the context id */ 3468 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3469 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 3470 cmd->index); 3471 3472 init_frame = (struct mrsas_init_frame *)cmd->frame; 3473 initq_info = (struct mrsas_init_queue_info *) 3474 ((unsigned long)init_frame + 64); 3475 3476 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE); 3477 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info)); 3478 3479 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0); 3480 3481 ddi_put32(cmd->frame_dma_obj.acc_handle, 3482 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1); 3483 3484 ddi_put32(cmd->frame_dma_obj.acc_handle, 3485 &initq_info->producer_index_phys_addr_hi, 0); 3486 ddi_put32(cmd->frame_dma_obj.acc_handle, 3487 &initq_info->producer_index_phys_addr_lo, 3488 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address); 3489 3490 ddi_put32(cmd->frame_dma_obj.acc_handle, 3491 &initq_info->consumer_index_phys_addr_hi, 0); 3492 ddi_put32(cmd->frame_dma_obj.acc_handle, 3493 &initq_info->consumer_index_phys_addr_lo, 3494 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4); 3495 3496 ddi_put32(cmd->frame_dma_obj.acc_handle, 3497 &initq_info->reply_queue_start_phys_addr_hi, 0); 3498 ddi_put32(cmd->frame_dma_obj.acc_handle, 3499 &initq_info->reply_queue_start_phys_addr_lo, 3500 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8); 3501 3502 ddi_put8(cmd->frame_dma_obj.acc_handle, 3503 &init_frame->cmd, MFI_CMD_OP_INIT); 3504 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status, 3505 MFI_CMD_STATUS_POLL_MODE); 3506 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0); 3507 ddi_put32(cmd->frame_dma_obj.acc_handle, 3508 &init_frame->queue_info_new_phys_addr_lo, 3509 cmd->frame_phys_addr + 64); 3510 ddi_put32(cmd->frame_dma_obj.acc_handle, 3511 &init_frame->queue_info_new_phys_addr_hi, 0); 3512 3513 3514 /* fill driver version information */ 3515 fill_up_drv_ver(&drv_ver_info); 3516 3517 /* allocate the driver version data transfer buffer */ 3518 instance->drv_ver_dma_obj.size = sizeof (drv_ver_info.drv_ver); 3519 instance->drv_ver_dma_obj.dma_attr = mrsas_generic_dma_attr; 3520 instance->drv_ver_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 3521 instance->drv_ver_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 3522 instance->drv_ver_dma_obj.dma_attr.dma_attr_sgllen = 1; 3523 instance->drv_ver_dma_obj.dma_attr.dma_attr_align = 1; 3524 3525 if (mrsas_alloc_dma_obj(instance, &instance->drv_ver_dma_obj, 3526 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 3527 con_log(CL_ANN, (CE_WARN, 3528 "init_mfi : Could not allocate driver version buffer.")); 3529 return (DDI_FAILURE); 3530 } 3531 /* copy driver version to dma buffer */ 3532 (void) memset(instance->drv_ver_dma_obj.buffer, 0, 3533 sizeof (drv_ver_info.drv_ver)); 3534 ddi_rep_put8(cmd->frame_dma_obj.acc_handle, 3535 (uint8_t *)drv_ver_info.drv_ver, 3536 (uint8_t *)instance->drv_ver_dma_obj.buffer, 3537 sizeof (drv_ver_info.drv_ver), DDI_DEV_AUTOINCR); 3538 3539 3540 /* copy driver version physical address to init frame */ 3541 ddi_put64(cmd->frame_dma_obj.acc_handle, &init_frame->driverversion, 3542 instance->drv_ver_dma_obj.dma_cookie[0].dmac_address); 3543 3544 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len, 3545 sizeof (struct mrsas_init_queue_info)); 3546 3547 cmd->frame_count = 1; 3548 3549 *cmd_ptr = cmd; 3550 3551 return (DDI_SUCCESS); 3552 } 3553 3554 3555 /* 3556 * mrsas_init_adapter_ppc - Initialize MFI interface adapter. 3557 */ 3558 int 3559 mrsas_init_adapter_ppc(struct mrsas_instance *instance) 3560 { 3561 struct mrsas_cmd *cmd; 3562 3563 /* 3564 * allocate memory for mfi adapter(cmd pool, individual commands, mfi 3565 * frames etc 3566 */ 3567 if (alloc_space_for_mfi(instance) != DDI_SUCCESS) { 3568 con_log(CL_ANN, (CE_NOTE, 3569 "Error, failed to allocate memory for MFI adapter")); 3570 return (DDI_FAILURE); 3571 } 3572 3573 /* Build INIT command */ 3574 cmd = mrsas_get_mfi_pkt(instance); 3575 if (cmd == NULL) { 3576 DTRACE_PROBE2(init_adapter_mfi_err, uint16_t, 3577 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 3578 return (DDI_FAILURE); 3579 } 3580 3581 if (mrsas_build_init_cmd(instance, &cmd) != DDI_SUCCESS) { 3582 con_log(CL_ANN, 3583 (CE_NOTE, "Error, failed to build INIT command")); 3584 3585 goto fail_undo_alloc_mfi_space; 3586 } 3587 3588 /* 3589 * Disable interrupt before sending init frame ( see linux driver code) 3590 * send INIT MFI frame in polled mode 3591 */ 3592 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 3593 con_log(CL_ANN, (CE_WARN, "failed to init firmware")); 3594 goto fail_fw_init; 3595 } 3596 3597 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) 3598 goto fail_fw_init; 3599 mrsas_return_mfi_pkt(instance, cmd); 3600 3601 if (ctio_enable && 3602 (instance->func_ptr->read_fw_status_reg(instance) & 0x04000000)) { 3603 con_log(CL_ANN, (CE_NOTE, "mr_sas: IEEE SGL's supported")); 3604 instance->flag_ieee = 1; 3605 } else { 3606 instance->flag_ieee = 0; 3607 } 3608 3609 ASSERT(!instance->skinny || instance->flag_ieee); 3610 3611 instance->unroll.alloc_space_mfi = 1; 3612 instance->unroll.verBuff = 1; 3613 3614 return (DDI_SUCCESS); 3615 3616 3617 fail_fw_init: 3618 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj); 3619 3620 fail_undo_alloc_mfi_space: 3621 mrsas_return_mfi_pkt(instance, cmd); 3622 free_space_for_mfi(instance); 3623 3624 return (DDI_FAILURE); 3625 3626 } 3627 3628 /* 3629 * mrsas_init_adapter - Initialize adapter. 3630 */ 3631 int 3632 mrsas_init_adapter(struct mrsas_instance *instance) 3633 { 3634 struct mrsas_ctrl_info ctrl_info; 3635 3636 3637 /* we expect the FW state to be READY */ 3638 if (mfi_state_transition_to_ready(instance)) { 3639 con_log(CL_ANN, (CE_WARN, "mr_sas: F/W is not ready")); 3640 return (DDI_FAILURE); 3641 } 3642 3643 /* get various operational parameters from status register */ 3644 instance->max_num_sge = 3645 (instance->func_ptr->read_fw_status_reg(instance) & 3646 0xFF0000) >> 0x10; 3647 instance->max_num_sge = 3648 (instance->max_num_sge > MRSAS_MAX_SGE_CNT) ? 3649 MRSAS_MAX_SGE_CNT : instance->max_num_sge; 3650 3651 /* 3652 * Reduce the max supported cmds by 1. This is to ensure that the 3653 * reply_q_sz (1 more than the max cmd that driver may send) 3654 * does not exceed max cmds that the FW can support 3655 */ 3656 instance->max_fw_cmds = 3657 instance->func_ptr->read_fw_status_reg(instance) & 0xFFFF; 3658 instance->max_fw_cmds = instance->max_fw_cmds - 1; 3659 3660 3661 3662 /* Initialize adapter */ 3663 if (instance->func_ptr->init_adapter(instance) != DDI_SUCCESS) { 3664 con_log(CL_ANN, 3665 (CE_WARN, "mr_sas: could not initialize adapter")); 3666 return (DDI_FAILURE); 3667 } 3668 3669 /* gather misc FW related information */ 3670 instance->disable_online_ctrl_reset = 0; 3671 3672 if (!get_ctrl_info(instance, &ctrl_info)) { 3673 instance->max_sectors_per_req = ctrl_info.max_request_size; 3674 con_log(CL_ANN1, (CE_NOTE, 3675 "product name %s ld present %d", 3676 ctrl_info.product_name, ctrl_info.ld_present_count)); 3677 } else { 3678 instance->max_sectors_per_req = instance->max_num_sge * 3679 PAGESIZE / 512; 3680 } 3681 3682 if (ctrl_info.properties.on_off_properties & DISABLE_OCR_PROP_FLAG) 3683 instance->disable_online_ctrl_reset = 1; 3684 3685 return (DDI_SUCCESS); 3686 3687 } 3688 3689 3690 3691 static int 3692 mrsas_issue_init_mfi(struct mrsas_instance *instance) 3693 { 3694 struct mrsas_cmd *cmd; 3695 struct mrsas_init_frame *init_frame; 3696 struct mrsas_init_queue_info *initq_info; 3697 3698 /* 3699 * Prepare a init frame. Note the init frame points to queue info 3700 * structure. Each frame has SGL allocated after first 64 bytes. For 3701 * this frame - since we don't need any SGL - we use SGL's space as 3702 * queue info structure 3703 */ 3704 con_log(CL_ANN1, (CE_NOTE, 3705 "mrsas_issue_init_mfi: entry\n")); 3706 cmd = get_mfi_app_pkt(instance); 3707 3708 if (!cmd) { 3709 con_log(CL_ANN1, (CE_WARN, 3710 "mrsas_issue_init_mfi: get_pkt failed\n")); 3711 return (DDI_FAILURE); 3712 } 3713 3714 /* Clear the frame buffer and assign back the context id */ 3715 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 3716 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 3717 cmd->index); 3718 3719 init_frame = (struct mrsas_init_frame *)cmd->frame; 3720 initq_info = (struct mrsas_init_queue_info *) 3721 ((unsigned long)init_frame + 64); 3722 3723 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE); 3724 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info)); 3725 3726 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0); 3727 3728 ddi_put32(cmd->frame_dma_obj.acc_handle, 3729 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1); 3730 ddi_put32(cmd->frame_dma_obj.acc_handle, 3731 &initq_info->producer_index_phys_addr_hi, 0); 3732 ddi_put32(cmd->frame_dma_obj.acc_handle, 3733 &initq_info->producer_index_phys_addr_lo, 3734 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address); 3735 ddi_put32(cmd->frame_dma_obj.acc_handle, 3736 &initq_info->consumer_index_phys_addr_hi, 0); 3737 ddi_put32(cmd->frame_dma_obj.acc_handle, 3738 &initq_info->consumer_index_phys_addr_lo, 3739 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4); 3740 3741 ddi_put32(cmd->frame_dma_obj.acc_handle, 3742 &initq_info->reply_queue_start_phys_addr_hi, 0); 3743 ddi_put32(cmd->frame_dma_obj.acc_handle, 3744 &initq_info->reply_queue_start_phys_addr_lo, 3745 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8); 3746 3747 ddi_put8(cmd->frame_dma_obj.acc_handle, 3748 &init_frame->cmd, MFI_CMD_OP_INIT); 3749 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status, 3750 MFI_CMD_STATUS_POLL_MODE); 3751 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0); 3752 ddi_put32(cmd->frame_dma_obj.acc_handle, 3753 &init_frame->queue_info_new_phys_addr_lo, 3754 cmd->frame_phys_addr + 64); 3755 ddi_put32(cmd->frame_dma_obj.acc_handle, 3756 &init_frame->queue_info_new_phys_addr_hi, 0); 3757 3758 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len, 3759 sizeof (struct mrsas_init_queue_info)); 3760 3761 cmd->frame_count = 1; 3762 3763 /* issue the init frame in polled mode */ 3764 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 3765 con_log(CL_ANN1, (CE_WARN, 3766 "mrsas_issue_init_mfi():failed to " 3767 "init firmware")); 3768 return_mfi_app_pkt(instance, cmd); 3769 return (DDI_FAILURE); 3770 } 3771 3772 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) { 3773 return_mfi_app_pkt(instance, cmd); 3774 return (DDI_FAILURE); 3775 } 3776 3777 return_mfi_app_pkt(instance, cmd); 3778 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_init_mfi: Done")); 3779 3780 return (DDI_SUCCESS); 3781 } 3782 /* 3783 * mfi_state_transition_to_ready : Move the FW to READY state 3784 * 3785 * @reg_set : MFI register set 3786 */ 3787 int 3788 mfi_state_transition_to_ready(struct mrsas_instance *instance) 3789 { 3790 int i; 3791 uint8_t max_wait; 3792 uint32_t fw_ctrl = 0; 3793 uint32_t fw_state; 3794 uint32_t cur_state; 3795 uint32_t cur_abs_reg_val; 3796 uint32_t prev_abs_reg_val; 3797 uint32_t status; 3798 3799 cur_abs_reg_val = 3800 instance->func_ptr->read_fw_status_reg(instance); 3801 fw_state = 3802 cur_abs_reg_val & MFI_STATE_MASK; 3803 con_log(CL_ANN1, (CE_CONT, 3804 "mfi_state_transition_to_ready:FW state = 0x%x", fw_state)); 3805 3806 while (fw_state != MFI_STATE_READY) { 3807 con_log(CL_ANN, (CE_CONT, 3808 "mfi_state_transition_to_ready:FW state%x", fw_state)); 3809 3810 switch (fw_state) { 3811 case MFI_STATE_FAULT: 3812 con_log(CL_ANN, (CE_NOTE, 3813 "mr_sas: FW in FAULT state!!")); 3814 3815 return (ENODEV); 3816 case MFI_STATE_WAIT_HANDSHAKE: 3817 /* set the CLR bit in IMR0 */ 3818 con_log(CL_ANN1, (CE_NOTE, 3819 "mr_sas: FW waiting for HANDSHAKE")); 3820 /* 3821 * PCI_Hot Plug: MFI F/W requires 3822 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG) 3823 * to be set 3824 */ 3825 /* WR_IB_MSG_0(MFI_INIT_CLEAR_HANDSHAKE, instance); */ 3826 if (!instance->tbolt && !instance->skinny) { 3827 WR_IB_DOORBELL(MFI_INIT_CLEAR_HANDSHAKE | 3828 MFI_INIT_HOTPLUG, instance); 3829 } else { 3830 WR_RESERVED0_REGISTER(MFI_INIT_CLEAR_HANDSHAKE | 3831 MFI_INIT_HOTPLUG, instance); 3832 } 3833 max_wait = (instance->tbolt == 1) ? 180 : 2; 3834 cur_state = MFI_STATE_WAIT_HANDSHAKE; 3835 break; 3836 case MFI_STATE_BOOT_MESSAGE_PENDING: 3837 /* set the CLR bit in IMR0 */ 3838 con_log(CL_ANN1, (CE_NOTE, 3839 "mr_sas: FW state boot message pending")); 3840 /* 3841 * PCI_Hot Plug: MFI F/W requires 3842 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG) 3843 * to be set 3844 */ 3845 if (!instance->tbolt && !instance->skinny) { 3846 WR_IB_DOORBELL(MFI_INIT_HOTPLUG, instance); 3847 } else { 3848 WR_RESERVED0_REGISTER(MFI_INIT_HOTPLUG, 3849 instance); 3850 } 3851 max_wait = (instance->tbolt == 1) ? 180 : 10; 3852 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING; 3853 break; 3854 case MFI_STATE_OPERATIONAL: 3855 /* bring it to READY state; assuming max wait 2 secs */ 3856 instance->func_ptr->disable_intr(instance); 3857 con_log(CL_ANN1, (CE_NOTE, 3858 "mr_sas: FW in OPERATIONAL state")); 3859 /* 3860 * PCI_Hot Plug: MFI F/W requires 3861 * (MFI_INIT_READY | MFI_INIT_MFIMODE | MFI_INIT_ABORT) 3862 * to be set 3863 */ 3864 /* WR_IB_DOORBELL(MFI_INIT_READY, instance); */ 3865 if (!instance->tbolt && !instance->skinny) { 3866 WR_IB_DOORBELL(MFI_RESET_FLAGS, instance); 3867 } else { 3868 WR_RESERVED0_REGISTER(MFI_RESET_FLAGS, 3869 instance); 3870 3871 for (i = 0; i < (10 * 1000); i++) { 3872 status = 3873 RD_RESERVED0_REGISTER(instance); 3874 if (status & 1) { 3875 delay(1 * 3876 drv_usectohz(MILLISEC)); 3877 } else { 3878 break; 3879 } 3880 } 3881 3882 } 3883 max_wait = (instance->tbolt == 1) ? 180 : 10; 3884 cur_state = MFI_STATE_OPERATIONAL; 3885 break; 3886 case MFI_STATE_UNDEFINED: 3887 /* this state should not last for more than 2 seconds */ 3888 con_log(CL_ANN1, (CE_NOTE, "FW state undefined")); 3889 3890 max_wait = (instance->tbolt == 1) ? 180 : 2; 3891 cur_state = MFI_STATE_UNDEFINED; 3892 break; 3893 case MFI_STATE_BB_INIT: 3894 max_wait = (instance->tbolt == 1) ? 180 : 2; 3895 cur_state = MFI_STATE_BB_INIT; 3896 break; 3897 case MFI_STATE_FW_INIT: 3898 max_wait = (instance->tbolt == 1) ? 180 : 2; 3899 cur_state = MFI_STATE_FW_INIT; 3900 break; 3901 case MFI_STATE_FW_INIT_2: 3902 max_wait = 180; 3903 cur_state = MFI_STATE_FW_INIT_2; 3904 break; 3905 case MFI_STATE_DEVICE_SCAN: 3906 max_wait = 180; 3907 cur_state = MFI_STATE_DEVICE_SCAN; 3908 prev_abs_reg_val = cur_abs_reg_val; 3909 con_log(CL_NONE, (CE_NOTE, 3910 "Device scan in progress ...\n")); 3911 break; 3912 case MFI_STATE_FLUSH_CACHE: 3913 max_wait = 180; 3914 cur_state = MFI_STATE_FLUSH_CACHE; 3915 break; 3916 default: 3917 con_log(CL_ANN1, (CE_NOTE, 3918 "mr_sas: Unknown state 0x%x", fw_state)); 3919 return (ENODEV); 3920 } 3921 3922 /* the cur_state should not last for more than max_wait secs */ 3923 for (i = 0; i < (max_wait * MILLISEC); i++) { 3924 /* fw_state = RD_OB_MSG_0(instance) & MFI_STATE_MASK; */ 3925 cur_abs_reg_val = 3926 instance->func_ptr->read_fw_status_reg(instance); 3927 fw_state = cur_abs_reg_val & MFI_STATE_MASK; 3928 3929 if (fw_state == cur_state) { 3930 delay(1 * drv_usectohz(MILLISEC)); 3931 } else { 3932 break; 3933 } 3934 } 3935 if (fw_state == MFI_STATE_DEVICE_SCAN) { 3936 if (prev_abs_reg_val != cur_abs_reg_val) { 3937 continue; 3938 } 3939 } 3940 3941 /* return error if fw_state hasn't changed after max_wait */ 3942 if (fw_state == cur_state) { 3943 con_log(CL_ANN1, (CE_WARN, 3944 "FW state hasn't changed in %d secs", max_wait)); 3945 return (ENODEV); 3946 } 3947 }; 3948 3949 /* This may also need to apply to Skinny, but for now, don't worry. */ 3950 if (!instance->tbolt && !instance->skinny) { 3951 fw_ctrl = RD_IB_DOORBELL(instance); 3952 con_log(CL_ANN1, (CE_CONT, 3953 "mfi_state_transition_to_ready:FW ctrl = 0x%x", fw_ctrl)); 3954 3955 /* 3956 * Write 0xF to the doorbell register to do the following. 3957 * - Abort all outstanding commands (bit 0). 3958 * - Transition from OPERATIONAL to READY state (bit 1). 3959 * - Discard (possible) low MFA posted in 64-bit mode (bit-2). 3960 * - Set to release FW to continue running (i.e. BIOS handshake 3961 * (bit 3). 3962 */ 3963 WR_IB_DOORBELL(0xF, instance); 3964 } 3965 3966 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) { 3967 return (EIO); 3968 } 3969 3970 return (DDI_SUCCESS); 3971 } 3972 3973 /* 3974 * get_seq_num 3975 */ 3976 static int 3977 get_seq_num(struct mrsas_instance *instance, 3978 struct mrsas_evt_log_info *eli) 3979 { 3980 int ret = DDI_SUCCESS; 3981 3982 dma_obj_t dcmd_dma_obj; 3983 struct mrsas_cmd *cmd; 3984 struct mrsas_dcmd_frame *dcmd; 3985 struct mrsas_evt_log_info *eli_tmp; 3986 if (instance->tbolt) { 3987 cmd = get_raid_msg_mfi_pkt(instance); 3988 } else { 3989 cmd = mrsas_get_mfi_pkt(instance); 3990 } 3991 3992 if (!cmd) { 3993 dev_err(instance->dip, CE_WARN, "failed to get a cmd"); 3994 DTRACE_PROBE2(seq_num_mfi_err, uint16_t, 3995 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 3996 return (ENOMEM); 3997 } 3998 3999 /* Clear the frame buffer and assign back the context id */ 4000 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 4001 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 4002 cmd->index); 4003 4004 dcmd = &cmd->frame->dcmd; 4005 4006 /* allocate the data transfer buffer */ 4007 dcmd_dma_obj.size = sizeof (struct mrsas_evt_log_info); 4008 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr; 4009 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 4010 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 4011 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1; 4012 dcmd_dma_obj.dma_attr.dma_attr_align = 1; 4013 4014 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj, 4015 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 4016 dev_err(instance->dip, CE_WARN, 4017 "get_seq_num: could not allocate data transfer buffer."); 4018 return (DDI_FAILURE); 4019 } 4020 4021 (void) memset(dcmd_dma_obj.buffer, 0, 4022 sizeof (struct mrsas_evt_log_info)); 4023 4024 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 4025 4026 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 4027 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0); 4028 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1); 4029 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 4030 MFI_FRAME_DIR_READ); 4031 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 4032 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 4033 sizeof (struct mrsas_evt_log_info)); 4034 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 4035 MR_DCMD_CTRL_EVENT_GET_INFO); 4036 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length, 4037 sizeof (struct mrsas_evt_log_info)); 4038 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr, 4039 dcmd_dma_obj.dma_cookie[0].dmac_address); 4040 4041 cmd->sync_cmd = MRSAS_TRUE; 4042 cmd->frame_count = 1; 4043 4044 if (instance->tbolt) { 4045 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 4046 } 4047 4048 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 4049 dev_err(instance->dip, CE_WARN, "get_seq_num: " 4050 "failed to issue MRSAS_DCMD_CTRL_EVENT_GET_INFO"); 4051 ret = DDI_FAILURE; 4052 } else { 4053 eli_tmp = (struct mrsas_evt_log_info *)dcmd_dma_obj.buffer; 4054 eli->newest_seq_num = ddi_get32(cmd->frame_dma_obj.acc_handle, 4055 &eli_tmp->newest_seq_num); 4056 ret = DDI_SUCCESS; 4057 } 4058 4059 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS) 4060 ret = DDI_FAILURE; 4061 4062 if (instance->tbolt) { 4063 return_raid_msg_mfi_pkt(instance, cmd); 4064 } else { 4065 mrsas_return_mfi_pkt(instance, cmd); 4066 } 4067 4068 return (ret); 4069 } 4070 4071 /* 4072 * start_mfi_aen 4073 */ 4074 static int 4075 start_mfi_aen(struct mrsas_instance *instance) 4076 { 4077 int ret = 0; 4078 4079 struct mrsas_evt_log_info eli; 4080 union mrsas_evt_class_locale class_locale; 4081 4082 /* get the latest sequence number from FW */ 4083 (void) memset(&eli, 0, sizeof (struct mrsas_evt_log_info)); 4084 4085 if (get_seq_num(instance, &eli)) { 4086 dev_err(instance->dip, CE_WARN, 4087 "start_mfi_aen: failed to get seq num"); 4088 return (-1); 4089 } 4090 4091 /* register AEN with FW for latest sequence number plus 1 */ 4092 class_locale.members.reserved = 0; 4093 class_locale.members.locale = LE_16(MR_EVT_LOCALE_ALL); 4094 class_locale.members.class = MR_EVT_CLASS_INFO; 4095 class_locale.word = LE_32(class_locale.word); 4096 ret = register_mfi_aen(instance, eli.newest_seq_num + 1, 4097 class_locale.word); 4098 4099 if (ret) { 4100 dev_err(instance->dip, CE_WARN, 4101 "start_mfi_aen: aen registration failed"); 4102 return (-1); 4103 } 4104 4105 4106 return (ret); 4107 } 4108 4109 /* 4110 * flush_cache 4111 */ 4112 static void 4113 flush_cache(struct mrsas_instance *instance) 4114 { 4115 struct mrsas_cmd *cmd = NULL; 4116 struct mrsas_dcmd_frame *dcmd; 4117 if (instance->tbolt) { 4118 cmd = get_raid_msg_mfi_pkt(instance); 4119 } else { 4120 cmd = mrsas_get_mfi_pkt(instance); 4121 } 4122 4123 if (!cmd) { 4124 con_log(CL_ANN1, (CE_WARN, 4125 "flush_cache():Failed to get a cmd for flush_cache")); 4126 DTRACE_PROBE2(flush_cache_err, uint16_t, 4127 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 4128 return; 4129 } 4130 4131 /* Clear the frame buffer and assign back the context id */ 4132 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 4133 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 4134 cmd->index); 4135 4136 dcmd = &cmd->frame->dcmd; 4137 4138 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 4139 4140 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 4141 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0); 4142 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 0); 4143 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 4144 MFI_FRAME_DIR_NONE); 4145 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 4146 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 0); 4147 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 4148 MR_DCMD_CTRL_CACHE_FLUSH); 4149 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.b[0], 4150 MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE); 4151 4152 cmd->frame_count = 1; 4153 4154 if (instance->tbolt) { 4155 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 4156 } 4157 4158 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) { 4159 con_log(CL_ANN1, (CE_WARN, 4160 "flush_cache: failed to issue MFI_DCMD_CTRL_CACHE_FLUSH")); 4161 } 4162 con_log(CL_ANN1, (CE_CONT, "flush_cache done")); 4163 if (instance->tbolt) { 4164 return_raid_msg_mfi_pkt(instance, cmd); 4165 } else { 4166 mrsas_return_mfi_pkt(instance, cmd); 4167 } 4168 4169 } 4170 4171 /* 4172 * service_mfi_aen- Completes an AEN command 4173 * @instance: Adapter soft state 4174 * @cmd: Command to be completed 4175 * 4176 */ 4177 void 4178 service_mfi_aen(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 4179 { 4180 uint32_t seq_num; 4181 struct mrsas_evt_detail *evt_detail = 4182 (struct mrsas_evt_detail *)instance->mfi_evt_detail_obj.buffer; 4183 int rval = 0; 4184 int tgt = 0; 4185 uint8_t dtype; 4186 #ifdef PDSUPPORT 4187 mrsas_pd_address_t *pd_addr; 4188 #endif 4189 ddi_acc_handle_t acc_handle; 4190 4191 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 4192 4193 acc_handle = cmd->frame_dma_obj.acc_handle; 4194 cmd->cmd_status = ddi_get8(acc_handle, &cmd->frame->io.cmd_status); 4195 if (cmd->cmd_status == ENODATA) { 4196 cmd->cmd_status = 0; 4197 } 4198 4199 /* 4200 * log the MFI AEN event to the sysevent queue so that 4201 * application will get noticed 4202 */ 4203 if (ddi_log_sysevent(instance->dip, DDI_VENDOR_LSI, "LSIMEGA", "SAS", 4204 NULL, NULL, DDI_NOSLEEP) != DDI_SUCCESS) { 4205 int instance_no = ddi_get_instance(instance->dip); 4206 con_log(CL_ANN, (CE_WARN, 4207 "mr_sas%d: Failed to log AEN event", instance_no)); 4208 } 4209 /* 4210 * Check for any ld devices that has changed state. i.e. online 4211 * or offline. 4212 */ 4213 con_log(CL_ANN1, (CE_CONT, 4214 "AEN: code = %x class = %x locale = %x args = %x", 4215 ddi_get32(acc_handle, &evt_detail->code), 4216 evt_detail->cl.members.class, 4217 ddi_get16(acc_handle, &evt_detail->cl.members.locale), 4218 ddi_get8(acc_handle, &evt_detail->arg_type))); 4219 4220 switch (ddi_get32(acc_handle, &evt_detail->code)) { 4221 case MR_EVT_CFG_CLEARED: { 4222 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) { 4223 if (instance->mr_ld_list[tgt].dip != NULL) { 4224 mutex_enter(&instance->config_dev_mtx); 4225 instance->mr_ld_list[tgt].flag = 4226 (uint8_t)~MRDRV_TGT_VALID; 4227 mutex_exit(&instance->config_dev_mtx); 4228 rval = mrsas_service_evt(instance, tgt, 0, 4229 MRSAS_EVT_UNCONFIG_TGT, NULL); 4230 con_log(CL_ANN1, (CE_WARN, 4231 "mr_sas: CFG CLEARED AEN rval = %d " 4232 "tgt id = %d", rval, tgt)); 4233 } 4234 } 4235 break; 4236 } 4237 4238 case MR_EVT_LD_DELETED: { 4239 tgt = ddi_get16(acc_handle, &evt_detail->args.ld.target_id); 4240 mutex_enter(&instance->config_dev_mtx); 4241 instance->mr_ld_list[tgt].flag = (uint8_t)~MRDRV_TGT_VALID; 4242 mutex_exit(&instance->config_dev_mtx); 4243 rval = mrsas_service_evt(instance, 4244 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0, 4245 MRSAS_EVT_UNCONFIG_TGT, NULL); 4246 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD DELETED AEN rval = %d " 4247 "tgt id = %d index = %d", rval, 4248 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 4249 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index))); 4250 break; 4251 } /* End of MR_EVT_LD_DELETED */ 4252 4253 case MR_EVT_LD_CREATED: { 4254 rval = mrsas_service_evt(instance, 4255 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0, 4256 MRSAS_EVT_CONFIG_TGT, NULL); 4257 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD CREATED AEN rval = %d " 4258 "tgt id = %d index = %d", rval, 4259 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 4260 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index))); 4261 break; 4262 } /* End of MR_EVT_LD_CREATED */ 4263 4264 #ifdef PDSUPPORT 4265 case MR_EVT_PD_REMOVED_EXT: { 4266 if (instance->tbolt || instance->skinny) { 4267 pd_addr = &evt_detail->args.pd_addr; 4268 dtype = pd_addr->scsi_dev_type; 4269 con_log(CL_DLEVEL1, (CE_NOTE, 4270 " MR_EVT_PD_REMOVED_EXT: dtype = %x," 4271 " arg_type = %d ", dtype, evt_detail->arg_type)); 4272 tgt = ddi_get16(acc_handle, 4273 &evt_detail->args.pd.device_id); 4274 mutex_enter(&instance->config_dev_mtx); 4275 instance->mr_tbolt_pd_list[tgt].flag = 4276 (uint8_t)~MRDRV_TGT_VALID; 4277 mutex_exit(&instance->config_dev_mtx); 4278 rval = mrsas_service_evt(instance, ddi_get16( 4279 acc_handle, &evt_detail->args.pd.device_id), 4280 1, MRSAS_EVT_UNCONFIG_TGT, NULL); 4281 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:" 4282 "rval = %d tgt id = %d ", rval, 4283 ddi_get16(acc_handle, 4284 &evt_detail->args.pd.device_id))); 4285 } 4286 break; 4287 } /* End of MR_EVT_PD_REMOVED_EXT */ 4288 4289 case MR_EVT_PD_INSERTED_EXT: { 4290 if (instance->tbolt || instance->skinny) { 4291 rval = mrsas_service_evt(instance, 4292 ddi_get16(acc_handle, 4293 &evt_detail->args.pd.device_id), 4294 1, MRSAS_EVT_CONFIG_TGT, NULL); 4295 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_INSERTEDi_EXT:" 4296 "rval = %d tgt id = %d ", rval, 4297 ddi_get16(acc_handle, 4298 &evt_detail->args.pd.device_id))); 4299 } 4300 break; 4301 } /* End of MR_EVT_PD_INSERTED_EXT */ 4302 4303 case MR_EVT_PD_STATE_CHANGE: { 4304 if (instance->tbolt || instance->skinny) { 4305 tgt = ddi_get16(acc_handle, 4306 &evt_detail->args.pd.device_id); 4307 if ((evt_detail->args.pd_state.prevState == 4308 PD_SYSTEM) && 4309 (evt_detail->args.pd_state.newState != PD_SYSTEM)) { 4310 mutex_enter(&instance->config_dev_mtx); 4311 instance->mr_tbolt_pd_list[tgt].flag = 4312 (uint8_t)~MRDRV_TGT_VALID; 4313 mutex_exit(&instance->config_dev_mtx); 4314 rval = mrsas_service_evt(instance, 4315 ddi_get16(acc_handle, 4316 &evt_detail->args.pd.device_id), 4317 1, MRSAS_EVT_UNCONFIG_TGT, NULL); 4318 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:" 4319 "rval = %d tgt id = %d ", rval, 4320 ddi_get16(acc_handle, 4321 &evt_detail->args.pd.device_id))); 4322 break; 4323 } 4324 if ((evt_detail->args.pd_state.prevState 4325 == UNCONFIGURED_GOOD) && 4326 (evt_detail->args.pd_state.newState == PD_SYSTEM)) { 4327 rval = mrsas_service_evt(instance, 4328 ddi_get16(acc_handle, 4329 &evt_detail->args.pd.device_id), 4330 1, MRSAS_EVT_CONFIG_TGT, NULL); 4331 con_log(CL_ANN1, (CE_WARN, 4332 "mr_sas: PD_INSERTED: rval = %d " 4333 " tgt id = %d ", rval, 4334 ddi_get16(acc_handle, 4335 &evt_detail->args.pd.device_id))); 4336 break; 4337 } 4338 } 4339 break; 4340 } 4341 #endif 4342 4343 } /* End of Main Switch */ 4344 4345 /* get copy of seq_num and class/locale for re-registration */ 4346 seq_num = ddi_get32(acc_handle, &evt_detail->seq_num); 4347 seq_num++; 4348 (void) memset(instance->mfi_evt_detail_obj.buffer, 0, 4349 sizeof (struct mrsas_evt_detail)); 4350 4351 ddi_put8(acc_handle, &cmd->frame->dcmd.cmd_status, 0x0); 4352 ddi_put32(acc_handle, &cmd->frame->dcmd.mbox.w[0], seq_num); 4353 4354 instance->aen_seq_num = seq_num; 4355 4356 cmd->frame_count = 1; 4357 4358 cmd->retry_count_for_ocr = 0; 4359 cmd->drv_pkt_time = 0; 4360 4361 /* Issue the aen registration frame */ 4362 instance->func_ptr->issue_cmd(cmd, instance); 4363 } 4364 4365 /* 4366 * complete_cmd_in_sync_mode - Completes an internal command 4367 * @instance: Adapter soft state 4368 * @cmd: Command to be completed 4369 * 4370 * The issue_cmd_in_sync_mode() function waits for a command to complete 4371 * after it issues a command. This function wakes up that waiting routine by 4372 * calling wake_up() on the wait queue. 4373 */ 4374 static void 4375 complete_cmd_in_sync_mode(struct mrsas_instance *instance, 4376 struct mrsas_cmd *cmd) 4377 { 4378 cmd->cmd_status = ddi_get8(cmd->frame_dma_obj.acc_handle, 4379 &cmd->frame->io.cmd_status); 4380 4381 cmd->sync_cmd = MRSAS_FALSE; 4382 4383 con_log(CL_ANN1, (CE_NOTE, "complete_cmd_in_sync_mode called %p \n", 4384 (void *)cmd)); 4385 4386 mutex_enter(&instance->int_cmd_mtx); 4387 if (cmd->cmd_status == ENODATA) { 4388 cmd->cmd_status = 0; 4389 } 4390 cv_broadcast(&instance->int_cmd_cv); 4391 mutex_exit(&instance->int_cmd_mtx); 4392 4393 } 4394 4395 /* 4396 * Call this function inside mrsas_softintr. 4397 * mrsas_initiate_ocr_if_fw_is_faulty - Initiates OCR if FW status is faulty 4398 * @instance: Adapter soft state 4399 */ 4400 4401 static uint32_t 4402 mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *instance) 4403 { 4404 uint32_t cur_abs_reg_val; 4405 uint32_t fw_state; 4406 4407 cur_abs_reg_val = instance->func_ptr->read_fw_status_reg(instance); 4408 fw_state = cur_abs_reg_val & MFI_STATE_MASK; 4409 if (fw_state == MFI_STATE_FAULT) { 4410 if (instance->disable_online_ctrl_reset == 1) { 4411 dev_err(instance->dip, CE_WARN, 4412 "mrsas_initiate_ocr_if_fw_is_faulty: " 4413 "FW in Fault state, detected in ISR: " 4414 "FW doesn't support ocr "); 4415 4416 return (ADAPTER_RESET_NOT_REQUIRED); 4417 } else { 4418 con_log(CL_ANN, (CE_NOTE, 4419 "mrsas_initiate_ocr_if_fw_is_faulty: FW in Fault " 4420 "state, detected in ISR: FW supports ocr ")); 4421 4422 return (ADAPTER_RESET_REQUIRED); 4423 } 4424 } 4425 4426 return (ADAPTER_RESET_NOT_REQUIRED); 4427 } 4428 4429 /* 4430 * mrsas_softintr - The Software ISR 4431 * @param arg : HBA soft state 4432 * 4433 * called from high-level interrupt if hi-level interrupt are not there, 4434 * otherwise triggered as a soft interrupt 4435 */ 4436 static uint_t 4437 mrsas_softintr(struct mrsas_instance *instance) 4438 { 4439 struct scsi_pkt *pkt; 4440 struct scsa_cmd *acmd; 4441 struct mrsas_cmd *cmd; 4442 struct mlist_head *pos, *next; 4443 mlist_t process_list; 4444 struct mrsas_header *hdr; 4445 struct scsi_arq_status *arqstat; 4446 4447 con_log(CL_ANN1, (CE_NOTE, "mrsas_softintr() called.")); 4448 4449 ASSERT(instance); 4450 4451 mutex_enter(&instance->completed_pool_mtx); 4452 4453 if (mlist_empty(&instance->completed_pool_list)) { 4454 mutex_exit(&instance->completed_pool_mtx); 4455 return (DDI_INTR_CLAIMED); 4456 } 4457 4458 instance->softint_running = 1; 4459 4460 INIT_LIST_HEAD(&process_list); 4461 mlist_splice(&instance->completed_pool_list, &process_list); 4462 INIT_LIST_HEAD(&instance->completed_pool_list); 4463 4464 mutex_exit(&instance->completed_pool_mtx); 4465 4466 /* perform all callbacks first, before releasing the SCBs */ 4467 mlist_for_each_safe(pos, next, &process_list) { 4468 cmd = mlist_entry(pos, struct mrsas_cmd, list); 4469 4470 /* syncronize the Cmd frame for the controller */ 4471 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 4472 0, 0, DDI_DMA_SYNC_FORCPU); 4473 4474 if (mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) != 4475 DDI_SUCCESS) { 4476 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 4477 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 4478 con_log(CL_ANN1, (CE_WARN, 4479 "mrsas_softintr: " 4480 "FMA check reports DMA handle failure")); 4481 return (DDI_INTR_CLAIMED); 4482 } 4483 4484 hdr = &cmd->frame->hdr; 4485 4486 /* remove the internal command from the process list */ 4487 mlist_del_init(&cmd->list); 4488 4489 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) { 4490 case MFI_CMD_OP_PD_SCSI: 4491 case MFI_CMD_OP_LD_SCSI: 4492 case MFI_CMD_OP_LD_READ: 4493 case MFI_CMD_OP_LD_WRITE: 4494 /* 4495 * MFI_CMD_OP_PD_SCSI and MFI_CMD_OP_LD_SCSI 4496 * could have been issued either through an 4497 * IO path or an IOCTL path. If it was via IOCTL, 4498 * we will send it to internal completion. 4499 */ 4500 if (cmd->sync_cmd == MRSAS_TRUE) { 4501 complete_cmd_in_sync_mode(instance, cmd); 4502 break; 4503 } 4504 4505 /* regular commands */ 4506 acmd = cmd->cmd; 4507 pkt = CMD2PKT(acmd); 4508 4509 if (acmd->cmd_flags & CFLAG_DMAVALID) { 4510 if (acmd->cmd_flags & CFLAG_CONSISTENT) { 4511 (void) ddi_dma_sync(acmd->cmd_dmahandle, 4512 acmd->cmd_dma_offset, 4513 acmd->cmd_dma_len, 4514 DDI_DMA_SYNC_FORCPU); 4515 } 4516 } 4517 4518 pkt->pkt_reason = CMD_CMPLT; 4519 pkt->pkt_statistics = 0; 4520 pkt->pkt_state = STATE_GOT_BUS 4521 | STATE_GOT_TARGET | STATE_SENT_CMD 4522 | STATE_XFERRED_DATA | STATE_GOT_STATUS; 4523 4524 con_log(CL_ANN, (CE_CONT, 4525 "CDB[0] = %x completed for %s: size %lx context %x", 4526 pkt->pkt_cdbp[0], ((acmd->islogical) ? "LD" : "PD"), 4527 acmd->cmd_dmacount, hdr->context)); 4528 DTRACE_PROBE3(softintr_cdb, uint8_t, pkt->pkt_cdbp[0], 4529 uint_t, acmd->cmd_cdblen, ulong_t, 4530 acmd->cmd_dmacount); 4531 4532 if (pkt->pkt_cdbp[0] == SCMD_INQUIRY) { 4533 struct scsi_inquiry *inq; 4534 4535 if (acmd->cmd_dmacount != 0) { 4536 bp_mapin(acmd->cmd_buf); 4537 inq = (struct scsi_inquiry *) 4538 acmd->cmd_buf->b_un.b_addr; 4539 4540 #ifdef PDSUPPORT 4541 if (hdr->cmd_status == MFI_STAT_OK) { 4542 display_scsi_inquiry( 4543 (caddr_t)inq); 4544 } 4545 #else 4546 /* don't expose physical drives to OS */ 4547 if (acmd->islogical && 4548 (hdr->cmd_status == MFI_STAT_OK)) { 4549 display_scsi_inquiry( 4550 (caddr_t)inq); 4551 } else if ((hdr->cmd_status == 4552 MFI_STAT_OK) && inq->inq_dtype == 4553 DTYPE_DIRECT) { 4554 4555 display_scsi_inquiry( 4556 (caddr_t)inq); 4557 4558 /* for physical disk */ 4559 hdr->cmd_status = 4560 MFI_STAT_DEVICE_NOT_FOUND; 4561 } 4562 #endif /* PDSUPPORT */ 4563 } 4564 } 4565 4566 DTRACE_PROBE2(softintr_done, uint8_t, hdr->cmd, 4567 uint8_t, hdr->cmd_status); 4568 4569 switch (hdr->cmd_status) { 4570 case MFI_STAT_OK: 4571 pkt->pkt_scbp[0] = STATUS_GOOD; 4572 break; 4573 case MFI_STAT_LD_CC_IN_PROGRESS: 4574 case MFI_STAT_LD_RECON_IN_PROGRESS: 4575 pkt->pkt_scbp[0] = STATUS_GOOD; 4576 break; 4577 case MFI_STAT_LD_INIT_IN_PROGRESS: 4578 con_log(CL_ANN, 4579 (CE_WARN, "Initialization in Progress")); 4580 pkt->pkt_reason = CMD_TRAN_ERR; 4581 4582 break; 4583 case MFI_STAT_SCSI_DONE_WITH_ERROR: 4584 con_log(CL_ANN, (CE_CONT, "scsi_done error")); 4585 4586 pkt->pkt_reason = CMD_CMPLT; 4587 ((struct scsi_status *) 4588 pkt->pkt_scbp)->sts_chk = 1; 4589 4590 if (pkt->pkt_cdbp[0] == SCMD_TEST_UNIT_READY) { 4591 con_log(CL_ANN, 4592 (CE_WARN, "TEST_UNIT_READY fail")); 4593 } else { 4594 pkt->pkt_state |= STATE_ARQ_DONE; 4595 arqstat = (void *)(pkt->pkt_scbp); 4596 arqstat->sts_rqpkt_reason = CMD_CMPLT; 4597 arqstat->sts_rqpkt_resid = 0; 4598 arqstat->sts_rqpkt_state |= 4599 STATE_GOT_BUS | STATE_GOT_TARGET 4600 | STATE_SENT_CMD 4601 | STATE_XFERRED_DATA; 4602 *(uint8_t *)&arqstat->sts_rqpkt_status = 4603 STATUS_GOOD; 4604 ddi_rep_get8( 4605 cmd->frame_dma_obj.acc_handle, 4606 (uint8_t *) 4607 &(arqstat->sts_sensedata), 4608 cmd->sense, 4609 sizeof (struct scsi_extended_sense), 4610 DDI_DEV_AUTOINCR); 4611 } 4612 break; 4613 case MFI_STAT_LD_OFFLINE: 4614 case MFI_STAT_DEVICE_NOT_FOUND: 4615 con_log(CL_ANN, (CE_CONT, 4616 "mrsas_softintr:device not found error")); 4617 pkt->pkt_reason = CMD_DEV_GONE; 4618 pkt->pkt_statistics = STAT_DISCON; 4619 break; 4620 case MFI_STAT_LD_LBA_OUT_OF_RANGE: 4621 pkt->pkt_state |= STATE_ARQ_DONE; 4622 pkt->pkt_reason = CMD_CMPLT; 4623 ((struct scsi_status *) 4624 pkt->pkt_scbp)->sts_chk = 1; 4625 4626 arqstat = (void *)(pkt->pkt_scbp); 4627 arqstat->sts_rqpkt_reason = CMD_CMPLT; 4628 arqstat->sts_rqpkt_resid = 0; 4629 arqstat->sts_rqpkt_state |= STATE_GOT_BUS 4630 | STATE_GOT_TARGET | STATE_SENT_CMD 4631 | STATE_XFERRED_DATA; 4632 *(uint8_t *)&arqstat->sts_rqpkt_status = 4633 STATUS_GOOD; 4634 4635 arqstat->sts_sensedata.es_valid = 1; 4636 arqstat->sts_sensedata.es_key = 4637 KEY_ILLEGAL_REQUEST; 4638 arqstat->sts_sensedata.es_class = 4639 CLASS_EXTENDED_SENSE; 4640 4641 /* 4642 * LOGICAL BLOCK ADDRESS OUT OF RANGE: 4643 * ASC: 0x21h; ASCQ: 0x00h; 4644 */ 4645 arqstat->sts_sensedata.es_add_code = 0x21; 4646 arqstat->sts_sensedata.es_qual_code = 0x00; 4647 4648 break; 4649 4650 default: 4651 con_log(CL_ANN, (CE_CONT, "Unknown status!")); 4652 pkt->pkt_reason = CMD_TRAN_ERR; 4653 4654 break; 4655 } 4656 4657 atomic_add_16(&instance->fw_outstanding, (-1)); 4658 4659 (void) mrsas_common_check(instance, cmd); 4660 4661 if (acmd->cmd_dmahandle) { 4662 if (mrsas_check_dma_handle( 4663 acmd->cmd_dmahandle) != DDI_SUCCESS) { 4664 ddi_fm_service_impact(instance->dip, 4665 DDI_SERVICE_UNAFFECTED); 4666 pkt->pkt_reason = CMD_TRAN_ERR; 4667 pkt->pkt_statistics = 0; 4668 } 4669 } 4670 4671 mrsas_return_mfi_pkt(instance, cmd); 4672 4673 /* Call the callback routine */ 4674 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && 4675 pkt->pkt_comp) { 4676 (*pkt->pkt_comp)(pkt); 4677 } 4678 4679 break; 4680 4681 case MFI_CMD_OP_SMP: 4682 case MFI_CMD_OP_STP: 4683 complete_cmd_in_sync_mode(instance, cmd); 4684 break; 4685 4686 case MFI_CMD_OP_DCMD: 4687 /* see if got an event notification */ 4688 if (ddi_get32(cmd->frame_dma_obj.acc_handle, 4689 &cmd->frame->dcmd.opcode) == 4690 MR_DCMD_CTRL_EVENT_WAIT) { 4691 if ((instance->aen_cmd == cmd) && 4692 (instance->aen_cmd->abort_aen)) { 4693 con_log(CL_ANN, (CE_WARN, 4694 "mrsas_softintr: " 4695 "aborted_aen returned")); 4696 } else { 4697 atomic_add_16(&instance->fw_outstanding, 4698 (-1)); 4699 service_mfi_aen(instance, cmd); 4700 } 4701 } else { 4702 complete_cmd_in_sync_mode(instance, cmd); 4703 } 4704 4705 break; 4706 4707 case MFI_CMD_OP_ABORT: 4708 con_log(CL_ANN, (CE_NOTE, "MFI_CMD_OP_ABORT complete")); 4709 /* 4710 * MFI_CMD_OP_ABORT successfully completed 4711 * in the synchronous mode 4712 */ 4713 complete_cmd_in_sync_mode(instance, cmd); 4714 break; 4715 4716 default: 4717 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE); 4718 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 4719 4720 if (cmd->pkt != NULL) { 4721 pkt = cmd->pkt; 4722 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && 4723 pkt->pkt_comp) { 4724 4725 con_log(CL_ANN1, (CE_CONT, "posting to " 4726 "scsa cmd %p index %x pkt %p" 4727 "time %llx, default ", (void *)cmd, 4728 cmd->index, (void *)pkt, 4729 gethrtime())); 4730 4731 (*pkt->pkt_comp)(pkt); 4732 4733 } 4734 } 4735 con_log(CL_ANN, (CE_WARN, "Cmd type unknown !")); 4736 break; 4737 } 4738 } 4739 4740 instance->softint_running = 0; 4741 4742 return (DDI_INTR_CLAIMED); 4743 } 4744 4745 /* 4746 * mrsas_alloc_dma_obj 4747 * 4748 * Allocate the memory and other resources for an dma object. 4749 */ 4750 int 4751 mrsas_alloc_dma_obj(struct mrsas_instance *instance, dma_obj_t *obj, 4752 uchar_t endian_flags) 4753 { 4754 int i; 4755 size_t alen = 0; 4756 uint_t cookie_cnt; 4757 struct ddi_device_acc_attr tmp_endian_attr; 4758 4759 tmp_endian_attr = endian_attr; 4760 tmp_endian_attr.devacc_attr_endian_flags = endian_flags; 4761 tmp_endian_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4762 4763 i = ddi_dma_alloc_handle(instance->dip, &obj->dma_attr, 4764 DDI_DMA_SLEEP, NULL, &obj->dma_handle); 4765 if (i != DDI_SUCCESS) { 4766 4767 switch (i) { 4768 case DDI_DMA_BADATTR : 4769 con_log(CL_ANN, (CE_WARN, 4770 "Failed ddi_dma_alloc_handle- Bad attribute")); 4771 break; 4772 case DDI_DMA_NORESOURCES : 4773 con_log(CL_ANN, (CE_WARN, 4774 "Failed ddi_dma_alloc_handle- No Resources")); 4775 break; 4776 default : 4777 con_log(CL_ANN, (CE_WARN, 4778 "Failed ddi_dma_alloc_handle: " 4779 "unknown status %d", i)); 4780 break; 4781 } 4782 4783 return (-1); 4784 } 4785 4786 if ((ddi_dma_mem_alloc(obj->dma_handle, obj->size, &tmp_endian_attr, 4787 DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL, 4788 &obj->buffer, &alen, &obj->acc_handle) != DDI_SUCCESS) || 4789 alen < obj->size) { 4790 4791 ddi_dma_free_handle(&obj->dma_handle); 4792 4793 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_mem_alloc")); 4794 4795 return (-1); 4796 } 4797 4798 if (ddi_dma_addr_bind_handle(obj->dma_handle, NULL, obj->buffer, 4799 obj->size, DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP, 4800 NULL, &obj->dma_cookie[0], &cookie_cnt) != DDI_SUCCESS) { 4801 4802 ddi_dma_mem_free(&obj->acc_handle); 4803 ddi_dma_free_handle(&obj->dma_handle); 4804 4805 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_addr_bind_handle")); 4806 4807 return (-1); 4808 } 4809 4810 if (mrsas_check_dma_handle(obj->dma_handle) != DDI_SUCCESS) { 4811 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 4812 return (-1); 4813 } 4814 4815 if (mrsas_check_acc_handle(obj->acc_handle) != DDI_SUCCESS) { 4816 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 4817 return (-1); 4818 } 4819 4820 return (cookie_cnt); 4821 } 4822 4823 /* 4824 * mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t) 4825 * 4826 * De-allocate the memory and other resources for an dma object, which must 4827 * have been alloated by a previous call to mrsas_alloc_dma_obj() 4828 */ 4829 int 4830 mrsas_free_dma_obj(struct mrsas_instance *instance, dma_obj_t obj) 4831 { 4832 4833 if ((obj.dma_handle == NULL) || (obj.acc_handle == NULL)) { 4834 return (DDI_SUCCESS); 4835 } 4836 4837 /* 4838 * NOTE: These check-handle functions fail if *_handle == NULL, but 4839 * this function succeeds because of the previous check. 4840 */ 4841 if (mrsas_check_dma_handle(obj.dma_handle) != DDI_SUCCESS) { 4842 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 4843 return (DDI_FAILURE); 4844 } 4845 4846 if (mrsas_check_acc_handle(obj.acc_handle) != DDI_SUCCESS) { 4847 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 4848 return (DDI_FAILURE); 4849 } 4850 4851 (void) ddi_dma_unbind_handle(obj.dma_handle); 4852 ddi_dma_mem_free(&obj.acc_handle); 4853 ddi_dma_free_handle(&obj.dma_handle); 4854 obj.acc_handle = NULL; 4855 return (DDI_SUCCESS); 4856 } 4857 4858 /* 4859 * mrsas_dma_alloc(instance_t *, struct scsi_pkt *, struct buf *, 4860 * int, int (*)()) 4861 * 4862 * Allocate dma resources for a new scsi command 4863 */ 4864 int 4865 mrsas_dma_alloc(struct mrsas_instance *instance, struct scsi_pkt *pkt, 4866 struct buf *bp, int flags, int (*callback)()) 4867 { 4868 int dma_flags; 4869 int (*cb)(caddr_t); 4870 int i; 4871 4872 ddi_dma_attr_t tmp_dma_attr = mrsas_generic_dma_attr; 4873 struct scsa_cmd *acmd = PKT2CMD(pkt); 4874 4875 acmd->cmd_buf = bp; 4876 4877 if (bp->b_flags & B_READ) { 4878 acmd->cmd_flags &= ~CFLAG_DMASEND; 4879 dma_flags = DDI_DMA_READ; 4880 } else { 4881 acmd->cmd_flags |= CFLAG_DMASEND; 4882 dma_flags = DDI_DMA_WRITE; 4883 } 4884 4885 if (flags & PKT_CONSISTENT) { 4886 acmd->cmd_flags |= CFLAG_CONSISTENT; 4887 dma_flags |= DDI_DMA_CONSISTENT; 4888 } 4889 4890 if (flags & PKT_DMA_PARTIAL) { 4891 dma_flags |= DDI_DMA_PARTIAL; 4892 } 4893 4894 dma_flags |= DDI_DMA_REDZONE; 4895 4896 cb = (callback == NULL_FUNC) ? DDI_DMA_DONTWAIT : DDI_DMA_SLEEP; 4897 4898 tmp_dma_attr.dma_attr_sgllen = instance->max_num_sge; 4899 tmp_dma_attr.dma_attr_addr_hi = 0xffffffffffffffffull; 4900 if (instance->tbolt) { 4901 /* OCR-RESET FIX */ 4902 tmp_dma_attr.dma_attr_count_max = 4903 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */ 4904 tmp_dma_attr.dma_attr_maxxfer = 4905 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */ 4906 } 4907 4908 if ((i = ddi_dma_alloc_handle(instance->dip, &tmp_dma_attr, 4909 cb, 0, &acmd->cmd_dmahandle)) != DDI_SUCCESS) { 4910 switch (i) { 4911 case DDI_DMA_BADATTR: 4912 bioerror(bp, EFAULT); 4913 return (DDI_FAILURE); 4914 4915 case DDI_DMA_NORESOURCES: 4916 bioerror(bp, 0); 4917 return (DDI_FAILURE); 4918 4919 default: 4920 con_log(CL_ANN, (CE_PANIC, "ddi_dma_alloc_handle: " 4921 "impossible result (0x%x)", i)); 4922 bioerror(bp, EFAULT); 4923 return (DDI_FAILURE); 4924 } 4925 } 4926 4927 i = ddi_dma_buf_bind_handle(acmd->cmd_dmahandle, bp, dma_flags, 4928 cb, 0, &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies); 4929 4930 switch (i) { 4931 case DDI_DMA_PARTIAL_MAP: 4932 if ((dma_flags & DDI_DMA_PARTIAL) == 0) { 4933 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: " 4934 "DDI_DMA_PARTIAL_MAP impossible")); 4935 goto no_dma_cookies; 4936 } 4937 4938 if (ddi_dma_numwin(acmd->cmd_dmahandle, &acmd->cmd_nwin) == 4939 DDI_FAILURE) { 4940 con_log(CL_ANN, (CE_PANIC, "ddi_dma_numwin failed")); 4941 goto no_dma_cookies; 4942 } 4943 4944 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin, 4945 &acmd->cmd_dma_offset, &acmd->cmd_dma_len, 4946 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) == 4947 DDI_FAILURE) { 4948 4949 con_log(CL_ANN, (CE_PANIC, "ddi_dma_getwin failed")); 4950 goto no_dma_cookies; 4951 } 4952 4953 goto get_dma_cookies; 4954 case DDI_DMA_MAPPED: 4955 acmd->cmd_nwin = 1; 4956 acmd->cmd_dma_len = 0; 4957 acmd->cmd_dma_offset = 0; 4958 4959 get_dma_cookies: 4960 i = 0; 4961 acmd->cmd_dmacount = 0; 4962 for (;;) { 4963 acmd->cmd_dmacount += 4964 acmd->cmd_dmacookies[i++].dmac_size; 4965 4966 if (i == instance->max_num_sge || 4967 i == acmd->cmd_ncookies) 4968 break; 4969 4970 ddi_dma_nextcookie(acmd->cmd_dmahandle, 4971 &acmd->cmd_dmacookies[i]); 4972 } 4973 4974 acmd->cmd_cookie = i; 4975 acmd->cmd_cookiecnt = i; 4976 4977 acmd->cmd_flags |= CFLAG_DMAVALID; 4978 4979 if (bp->b_bcount >= acmd->cmd_dmacount) { 4980 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount; 4981 } else { 4982 pkt->pkt_resid = 0; 4983 } 4984 4985 return (DDI_SUCCESS); 4986 case DDI_DMA_NORESOURCES: 4987 bioerror(bp, 0); 4988 break; 4989 case DDI_DMA_NOMAPPING: 4990 bioerror(bp, EFAULT); 4991 break; 4992 case DDI_DMA_TOOBIG: 4993 bioerror(bp, EINVAL); 4994 break; 4995 case DDI_DMA_INUSE: 4996 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle:" 4997 " DDI_DMA_INUSE impossible")); 4998 break; 4999 default: 5000 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: " 5001 "impossible result (0x%x)", i)); 5002 break; 5003 } 5004 5005 no_dma_cookies: 5006 ddi_dma_free_handle(&acmd->cmd_dmahandle); 5007 acmd->cmd_dmahandle = NULL; 5008 acmd->cmd_flags &= ~CFLAG_DMAVALID; 5009 return (DDI_FAILURE); 5010 } 5011 5012 /* 5013 * mrsas_dma_move(struct mrsas_instance *, struct scsi_pkt *, struct buf *) 5014 * 5015 * move dma resources to next dma window 5016 * 5017 */ 5018 int 5019 mrsas_dma_move(struct mrsas_instance *instance, struct scsi_pkt *pkt, 5020 struct buf *bp) 5021 { 5022 int i = 0; 5023 5024 struct scsa_cmd *acmd = PKT2CMD(pkt); 5025 5026 /* 5027 * If there are no more cookies remaining in this window, 5028 * must move to the next window first. 5029 */ 5030 if (acmd->cmd_cookie == acmd->cmd_ncookies) { 5031 if (acmd->cmd_curwin == acmd->cmd_nwin && acmd->cmd_nwin == 1) { 5032 return (DDI_SUCCESS); 5033 } 5034 5035 /* at last window, cannot move */ 5036 if (++acmd->cmd_curwin >= acmd->cmd_nwin) { 5037 return (DDI_FAILURE); 5038 } 5039 5040 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin, 5041 &acmd->cmd_dma_offset, &acmd->cmd_dma_len, 5042 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) == 5043 DDI_FAILURE) { 5044 return (DDI_FAILURE); 5045 } 5046 5047 acmd->cmd_cookie = 0; 5048 } else { 5049 /* still more cookies in this window - get the next one */ 5050 ddi_dma_nextcookie(acmd->cmd_dmahandle, 5051 &acmd->cmd_dmacookies[0]); 5052 } 5053 5054 /* get remaining cookies in this window, up to our maximum */ 5055 for (;;) { 5056 acmd->cmd_dmacount += acmd->cmd_dmacookies[i++].dmac_size; 5057 acmd->cmd_cookie++; 5058 5059 if (i == instance->max_num_sge || 5060 acmd->cmd_cookie == acmd->cmd_ncookies) { 5061 break; 5062 } 5063 5064 ddi_dma_nextcookie(acmd->cmd_dmahandle, 5065 &acmd->cmd_dmacookies[i]); 5066 } 5067 5068 acmd->cmd_cookiecnt = i; 5069 5070 if (bp->b_bcount >= acmd->cmd_dmacount) { 5071 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount; 5072 } else { 5073 pkt->pkt_resid = 0; 5074 } 5075 5076 return (DDI_SUCCESS); 5077 } 5078 5079 /* 5080 * build_cmd 5081 */ 5082 static struct mrsas_cmd * 5083 build_cmd(struct mrsas_instance *instance, struct scsi_address *ap, 5084 struct scsi_pkt *pkt, uchar_t *cmd_done) 5085 { 5086 uint16_t flags = 0; 5087 uint32_t i; 5088 uint32_t context; 5089 uint32_t sge_bytes; 5090 uint32_t tmp_data_xfer_len; 5091 ddi_acc_handle_t acc_handle; 5092 struct mrsas_cmd *cmd; 5093 struct mrsas_sge64 *mfi_sgl; 5094 struct mrsas_sge_ieee *mfi_sgl_ieee; 5095 struct scsa_cmd *acmd = PKT2CMD(pkt); 5096 struct mrsas_pthru_frame *pthru; 5097 struct mrsas_io_frame *ldio; 5098 5099 /* find out if this is logical or physical drive command. */ 5100 acmd->islogical = MRDRV_IS_LOGICAL(ap); 5101 acmd->device_id = MAP_DEVICE_ID(instance, ap); 5102 *cmd_done = 0; 5103 5104 /* get the command packet */ 5105 if (!(cmd = mrsas_get_mfi_pkt(instance))) { 5106 DTRACE_PROBE2(build_cmd_mfi_err, uint16_t, 5107 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 5108 return (NULL); 5109 } 5110 5111 acc_handle = cmd->frame_dma_obj.acc_handle; 5112 5113 /* Clear the frame buffer and assign back the context id */ 5114 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 5115 ddi_put32(acc_handle, &cmd->frame->hdr.context, cmd->index); 5116 5117 cmd->pkt = pkt; 5118 cmd->cmd = acmd; 5119 DTRACE_PROBE3(build_cmds, uint8_t, pkt->pkt_cdbp[0], 5120 ulong_t, acmd->cmd_dmacount, ulong_t, acmd->cmd_dma_len); 5121 5122 /* lets get the command directions */ 5123 if (acmd->cmd_flags & CFLAG_DMASEND) { 5124 flags = MFI_FRAME_DIR_WRITE; 5125 5126 if (acmd->cmd_flags & CFLAG_CONSISTENT) { 5127 (void) ddi_dma_sync(acmd->cmd_dmahandle, 5128 acmd->cmd_dma_offset, acmd->cmd_dma_len, 5129 DDI_DMA_SYNC_FORDEV); 5130 } 5131 } else if (acmd->cmd_flags & ~CFLAG_DMASEND) { 5132 flags = MFI_FRAME_DIR_READ; 5133 5134 if (acmd->cmd_flags & CFLAG_CONSISTENT) { 5135 (void) ddi_dma_sync(acmd->cmd_dmahandle, 5136 acmd->cmd_dma_offset, acmd->cmd_dma_len, 5137 DDI_DMA_SYNC_FORCPU); 5138 } 5139 } else { 5140 flags = MFI_FRAME_DIR_NONE; 5141 } 5142 5143 if (instance->flag_ieee) { 5144 flags |= MFI_FRAME_IEEE; 5145 } 5146 flags |= MFI_FRAME_SGL64; 5147 5148 switch (pkt->pkt_cdbp[0]) { 5149 5150 /* 5151 * case SCMD_SYNCHRONIZE_CACHE: 5152 * flush_cache(instance); 5153 * mrsas_return_mfi_pkt(instance, cmd); 5154 * *cmd_done = 1; 5155 * 5156 * return (NULL); 5157 */ 5158 5159 case SCMD_READ: 5160 case SCMD_WRITE: 5161 case SCMD_READ_G1: 5162 case SCMD_WRITE_G1: 5163 case SCMD_READ_G4: 5164 case SCMD_WRITE_G4: 5165 case SCMD_READ_G5: 5166 case SCMD_WRITE_G5: 5167 if (acmd->islogical) { 5168 ldio = (struct mrsas_io_frame *)cmd->frame; 5169 5170 /* 5171 * preare the Logical IO frame: 5172 * 2nd bit is zero for all read cmds 5173 */ 5174 ddi_put8(acc_handle, &ldio->cmd, 5175 (pkt->pkt_cdbp[0] & 0x02) ? MFI_CMD_OP_LD_WRITE 5176 : MFI_CMD_OP_LD_READ); 5177 ddi_put8(acc_handle, &ldio->cmd_status, 0x0); 5178 ddi_put8(acc_handle, &ldio->scsi_status, 0x0); 5179 ddi_put8(acc_handle, &ldio->target_id, acmd->device_id); 5180 ddi_put16(acc_handle, &ldio->timeout, 0); 5181 ddi_put8(acc_handle, &ldio->reserved_0, 0); 5182 ddi_put16(acc_handle, &ldio->pad_0, 0); 5183 ddi_put16(acc_handle, &ldio->flags, flags); 5184 5185 /* Initialize sense Information */ 5186 bzero(cmd->sense, SENSE_LENGTH); 5187 ddi_put8(acc_handle, &ldio->sense_len, SENSE_LENGTH); 5188 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_hi, 0); 5189 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_lo, 5190 cmd->sense_phys_addr); 5191 ddi_put32(acc_handle, &ldio->start_lba_hi, 0); 5192 ddi_put8(acc_handle, &ldio->access_byte, 5193 (acmd->cmd_cdblen != 6) ? pkt->pkt_cdbp[1] : 0); 5194 ddi_put8(acc_handle, &ldio->sge_count, 5195 acmd->cmd_cookiecnt); 5196 if (instance->flag_ieee) { 5197 mfi_sgl_ieee = 5198 (struct mrsas_sge_ieee *)&ldio->sgl; 5199 } else { 5200 mfi_sgl = (struct mrsas_sge64 *)&ldio->sgl; 5201 } 5202 5203 context = ddi_get32(acc_handle, &ldio->context); 5204 5205 if (acmd->cmd_cdblen == CDB_GROUP0) { 5206 /* 6-byte cdb */ 5207 ddi_put32(acc_handle, &ldio->lba_count, ( 5208 (uint16_t)(pkt->pkt_cdbp[4]))); 5209 5210 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 5211 ((uint32_t)(pkt->pkt_cdbp[3])) | 5212 ((uint32_t)(pkt->pkt_cdbp[2]) << 8) | 5213 ((uint32_t)((pkt->pkt_cdbp[1]) & 0x1F) 5214 << 16))); 5215 } else if (acmd->cmd_cdblen == CDB_GROUP1) { 5216 /* 10-byte cdb */ 5217 ddi_put32(acc_handle, &ldio->lba_count, ( 5218 ((uint16_t)(pkt->pkt_cdbp[8])) | 5219 ((uint16_t)(pkt->pkt_cdbp[7]) << 8))); 5220 5221 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 5222 ((uint32_t)(pkt->pkt_cdbp[5])) | 5223 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) | 5224 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) | 5225 ((uint32_t)(pkt->pkt_cdbp[2]) << 24))); 5226 } else if (acmd->cmd_cdblen == CDB_GROUP5) { 5227 /* 12-byte cdb */ 5228 ddi_put32(acc_handle, &ldio->lba_count, ( 5229 ((uint32_t)(pkt->pkt_cdbp[9])) | 5230 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) | 5231 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) | 5232 ((uint32_t)(pkt->pkt_cdbp[6]) << 24))); 5233 5234 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 5235 ((uint32_t)(pkt->pkt_cdbp[5])) | 5236 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) | 5237 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) | 5238 ((uint32_t)(pkt->pkt_cdbp[2]) << 24))); 5239 } else if (acmd->cmd_cdblen == CDB_GROUP4) { 5240 /* 16-byte cdb */ 5241 ddi_put32(acc_handle, &ldio->lba_count, ( 5242 ((uint32_t)(pkt->pkt_cdbp[13])) | 5243 ((uint32_t)(pkt->pkt_cdbp[12]) << 8) | 5244 ((uint32_t)(pkt->pkt_cdbp[11]) << 16) | 5245 ((uint32_t)(pkt->pkt_cdbp[10]) << 24))); 5246 5247 ddi_put32(acc_handle, &ldio->start_lba_lo, ( 5248 ((uint32_t)(pkt->pkt_cdbp[9])) | 5249 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) | 5250 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) | 5251 ((uint32_t)(pkt->pkt_cdbp[6]) << 24))); 5252 5253 ddi_put32(acc_handle, &ldio->start_lba_hi, ( 5254 ((uint32_t)(pkt->pkt_cdbp[5])) | 5255 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) | 5256 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) | 5257 ((uint32_t)(pkt->pkt_cdbp[2]) << 24))); 5258 } 5259 5260 break; 5261 } 5262 /* fall through For all non-rd/wr and physical disk cmds */ 5263 default: 5264 5265 switch (pkt->pkt_cdbp[0]) { 5266 case SCMD_MODE_SENSE: 5267 case SCMD_MODE_SENSE_G1: { 5268 union scsi_cdb *cdbp; 5269 uint16_t page_code; 5270 5271 cdbp = (void *)pkt->pkt_cdbp; 5272 page_code = (uint16_t)cdbp->cdb_un.sg.scsi[0]; 5273 switch (page_code) { 5274 case 0x3: 5275 case 0x4: 5276 (void) mrsas_mode_sense_build(pkt); 5277 mrsas_return_mfi_pkt(instance, cmd); 5278 *cmd_done = 1; 5279 return (NULL); 5280 } 5281 break; 5282 } 5283 default: 5284 break; 5285 } 5286 5287 pthru = (struct mrsas_pthru_frame *)cmd->frame; 5288 5289 /* prepare the DCDB frame */ 5290 ddi_put8(acc_handle, &pthru->cmd, (acmd->islogical) ? 5291 MFI_CMD_OP_LD_SCSI : MFI_CMD_OP_PD_SCSI); 5292 ddi_put8(acc_handle, &pthru->cmd_status, 0x0); 5293 ddi_put8(acc_handle, &pthru->scsi_status, 0x0); 5294 ddi_put8(acc_handle, &pthru->target_id, acmd->device_id); 5295 ddi_put8(acc_handle, &pthru->lun, 0); 5296 ddi_put8(acc_handle, &pthru->cdb_len, acmd->cmd_cdblen); 5297 ddi_put16(acc_handle, &pthru->timeout, 0); 5298 ddi_put16(acc_handle, &pthru->flags, flags); 5299 tmp_data_xfer_len = 0; 5300 for (i = 0; i < acmd->cmd_cookiecnt; i++) { 5301 tmp_data_xfer_len += acmd->cmd_dmacookies[i].dmac_size; 5302 } 5303 ddi_put32(acc_handle, &pthru->data_xfer_len, 5304 tmp_data_xfer_len); 5305 ddi_put8(acc_handle, &pthru->sge_count, acmd->cmd_cookiecnt); 5306 if (instance->flag_ieee) { 5307 mfi_sgl_ieee = (struct mrsas_sge_ieee *)&pthru->sgl; 5308 } else { 5309 mfi_sgl = (struct mrsas_sge64 *)&pthru->sgl; 5310 } 5311 5312 bzero(cmd->sense, SENSE_LENGTH); 5313 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH); 5314 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0); 5315 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo, 5316 cmd->sense_phys_addr); 5317 5318 context = ddi_get32(acc_handle, &pthru->context); 5319 ddi_rep_put8(acc_handle, (uint8_t *)pkt->pkt_cdbp, 5320 (uint8_t *)pthru->cdb, acmd->cmd_cdblen, DDI_DEV_AUTOINCR); 5321 5322 break; 5323 } 5324 #ifdef lint 5325 context = context; 5326 #endif 5327 /* prepare the scatter-gather list for the firmware */ 5328 if (instance->flag_ieee) { 5329 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl_ieee++) { 5330 ddi_put64(acc_handle, &mfi_sgl_ieee->phys_addr, 5331 acmd->cmd_dmacookies[i].dmac_laddress); 5332 ddi_put32(acc_handle, &mfi_sgl_ieee->length, 5333 acmd->cmd_dmacookies[i].dmac_size); 5334 } 5335 sge_bytes = sizeof (struct mrsas_sge_ieee)*acmd->cmd_cookiecnt; 5336 } else { 5337 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl++) { 5338 ddi_put64(acc_handle, &mfi_sgl->phys_addr, 5339 acmd->cmd_dmacookies[i].dmac_laddress); 5340 ddi_put32(acc_handle, &mfi_sgl->length, 5341 acmd->cmd_dmacookies[i].dmac_size); 5342 } 5343 sge_bytes = sizeof (struct mrsas_sge64)*acmd->cmd_cookiecnt; 5344 } 5345 5346 cmd->frame_count = (sge_bytes / MRMFI_FRAME_SIZE) + 5347 ((sge_bytes % MRMFI_FRAME_SIZE) ? 1 : 0) + 1; 5348 5349 if (cmd->frame_count >= 8) { 5350 cmd->frame_count = 8; 5351 } 5352 5353 return (cmd); 5354 } 5355 5356 /* 5357 * wait_for_outstanding - Wait for all outstanding cmds 5358 * @instance: Adapter soft state 5359 * 5360 * This function waits for upto MRDRV_RESET_WAIT_TIME seconds for FW to 5361 * complete all its outstanding commands. Returns error if one or more IOs 5362 * are pending after this time period. 5363 */ 5364 static int 5365 wait_for_outstanding(struct mrsas_instance *instance) 5366 { 5367 int i; 5368 uint32_t wait_time = 90; 5369 5370 for (i = 0; i < wait_time; i++) { 5371 if (!instance->fw_outstanding) { 5372 break; 5373 } 5374 5375 drv_usecwait(MILLISEC); /* wait for 1000 usecs */; 5376 } 5377 5378 if (instance->fw_outstanding) { 5379 return (1); 5380 } 5381 5382 return (0); 5383 } 5384 5385 /* 5386 * issue_mfi_pthru 5387 */ 5388 static int 5389 issue_mfi_pthru(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 5390 struct mrsas_cmd *cmd, int mode) 5391 { 5392 void *ubuf; 5393 uint32_t kphys_addr = 0; 5394 uint32_t xferlen = 0; 5395 uint32_t new_xfer_length = 0; 5396 uint_t model; 5397 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 5398 dma_obj_t pthru_dma_obj; 5399 struct mrsas_pthru_frame *kpthru; 5400 struct mrsas_pthru_frame *pthru; 5401 int i; 5402 pthru = &cmd->frame->pthru; 5403 kpthru = (struct mrsas_pthru_frame *)&ioctl->frame[0]; 5404 5405 if (instance->adapterresetinprogress) { 5406 con_log(CL_ANN1, (CE_WARN, "issue_mfi_pthru: Reset flag set, " 5407 "returning mfi_pkt and setting TRAN_BUSY\n")); 5408 return (DDI_FAILURE); 5409 } 5410 model = ddi_model_convert_from(mode & FMODELS); 5411 if (model == DDI_MODEL_ILP32) { 5412 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32")); 5413 5414 xferlen = kpthru->sgl.sge32[0].length; 5415 5416 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr; 5417 } else { 5418 #ifdef _ILP32 5419 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32")); 5420 xferlen = kpthru->sgl.sge32[0].length; 5421 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr; 5422 #else 5423 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP64")); 5424 xferlen = kpthru->sgl.sge64[0].length; 5425 ubuf = (void *)(ulong_t)kpthru->sgl.sge64[0].phys_addr; 5426 #endif 5427 } 5428 5429 if (xferlen) { 5430 /* means IOCTL requires DMA */ 5431 /* allocate the data transfer buffer */ 5432 /* pthru_dma_obj.size = xferlen; */ 5433 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length, 5434 PAGESIZE); 5435 pthru_dma_obj.size = new_xfer_length; 5436 pthru_dma_obj.dma_attr = mrsas_generic_dma_attr; 5437 pthru_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 5438 pthru_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 5439 pthru_dma_obj.dma_attr.dma_attr_sgllen = 1; 5440 pthru_dma_obj.dma_attr.dma_attr_align = 1; 5441 5442 /* allocate kernel buffer for DMA */ 5443 if (mrsas_alloc_dma_obj(instance, &pthru_dma_obj, 5444 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 5445 con_log(CL_ANN, (CE_WARN, "issue_mfi_pthru: " 5446 "could not allocate data transfer buffer.")); 5447 return (DDI_FAILURE); 5448 } 5449 (void) memset(pthru_dma_obj.buffer, 0, xferlen); 5450 5451 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 5452 if (kpthru->flags & MFI_FRAME_DIR_WRITE) { 5453 for (i = 0; i < xferlen; i++) { 5454 if (ddi_copyin((uint8_t *)ubuf+i, 5455 (uint8_t *)pthru_dma_obj.buffer+i, 5456 1, mode)) { 5457 con_log(CL_ANN, (CE_WARN, 5458 "issue_mfi_pthru : " 5459 "copy from user space failed")); 5460 return (DDI_FAILURE); 5461 } 5462 } 5463 } 5464 5465 kphys_addr = pthru_dma_obj.dma_cookie[0].dmac_address; 5466 } 5467 5468 ddi_put8(acc_handle, &pthru->cmd, kpthru->cmd); 5469 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH); 5470 ddi_put8(acc_handle, &pthru->cmd_status, 0); 5471 ddi_put8(acc_handle, &pthru->scsi_status, 0); 5472 ddi_put8(acc_handle, &pthru->target_id, kpthru->target_id); 5473 ddi_put8(acc_handle, &pthru->lun, kpthru->lun); 5474 ddi_put8(acc_handle, &pthru->cdb_len, kpthru->cdb_len); 5475 ddi_put8(acc_handle, &pthru->sge_count, kpthru->sge_count); 5476 ddi_put16(acc_handle, &pthru->timeout, kpthru->timeout); 5477 ddi_put32(acc_handle, &pthru->data_xfer_len, kpthru->data_xfer_len); 5478 5479 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0); 5480 pthru->sense_buf_phys_addr_lo = cmd->sense_phys_addr; 5481 /* ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo, 0); */ 5482 5483 ddi_rep_put8(acc_handle, (uint8_t *)kpthru->cdb, (uint8_t *)pthru->cdb, 5484 pthru->cdb_len, DDI_DEV_AUTOINCR); 5485 5486 ddi_put16(acc_handle, &pthru->flags, kpthru->flags & ~MFI_FRAME_SGL64); 5487 ddi_put32(acc_handle, &pthru->sgl.sge32[0].length, xferlen); 5488 ddi_put32(acc_handle, &pthru->sgl.sge32[0].phys_addr, kphys_addr); 5489 5490 cmd->sync_cmd = MRSAS_TRUE; 5491 cmd->frame_count = 1; 5492 5493 if (instance->tbolt) { 5494 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 5495 } 5496 5497 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 5498 con_log(CL_ANN, (CE_WARN, 5499 "issue_mfi_pthru: fw_ioctl failed")); 5500 } else { 5501 if (xferlen && kpthru->flags & MFI_FRAME_DIR_READ) { 5502 for (i = 0; i < xferlen; i++) { 5503 if (ddi_copyout( 5504 (uint8_t *)pthru_dma_obj.buffer+i, 5505 (uint8_t *)ubuf+i, 1, mode)) { 5506 con_log(CL_ANN, (CE_WARN, 5507 "issue_mfi_pthru : " 5508 "copy to user space failed")); 5509 return (DDI_FAILURE); 5510 } 5511 } 5512 } 5513 } 5514 5515 kpthru->cmd_status = ddi_get8(acc_handle, &pthru->cmd_status); 5516 kpthru->scsi_status = ddi_get8(acc_handle, &pthru->scsi_status); 5517 5518 con_log(CL_ANN, (CE_CONT, "issue_mfi_pthru: cmd_status %x, " 5519 "scsi_status %x", kpthru->cmd_status, kpthru->scsi_status)); 5520 DTRACE_PROBE3(issue_pthru, uint8_t, kpthru->cmd, uint8_t, 5521 kpthru->cmd_status, uint8_t, kpthru->scsi_status); 5522 5523 if (kpthru->sense_len) { 5524 uint_t sense_len = SENSE_LENGTH; 5525 void *sense_ubuf = 5526 (void *)(ulong_t)kpthru->sense_buf_phys_addr_lo; 5527 if (kpthru->sense_len <= SENSE_LENGTH) { 5528 sense_len = kpthru->sense_len; 5529 } 5530 5531 for (i = 0; i < sense_len; i++) { 5532 if (ddi_copyout( 5533 (uint8_t *)cmd->sense+i, 5534 (uint8_t *)sense_ubuf+i, 1, mode)) { 5535 con_log(CL_ANN, (CE_WARN, 5536 "issue_mfi_pthru : " 5537 "copy to user space failed")); 5538 } 5539 con_log(CL_DLEVEL1, (CE_WARN, 5540 "Copying Sense info sense_buff[%d] = 0x%X", 5541 i, *((uint8_t *)cmd->sense + i))); 5542 } 5543 } 5544 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0, 5545 DDI_DMA_SYNC_FORDEV); 5546 5547 if (xferlen) { 5548 /* free kernel buffer */ 5549 if (mrsas_free_dma_obj(instance, pthru_dma_obj) != DDI_SUCCESS) 5550 return (DDI_FAILURE); 5551 } 5552 5553 return (DDI_SUCCESS); 5554 } 5555 5556 /* 5557 * issue_mfi_dcmd 5558 */ 5559 static int 5560 issue_mfi_dcmd(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 5561 struct mrsas_cmd *cmd, int mode) 5562 { 5563 void *ubuf; 5564 uint32_t kphys_addr = 0; 5565 uint32_t xferlen = 0; 5566 uint32_t new_xfer_length = 0; 5567 uint32_t model; 5568 dma_obj_t dcmd_dma_obj; 5569 struct mrsas_dcmd_frame *kdcmd; 5570 struct mrsas_dcmd_frame *dcmd; 5571 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 5572 int i; 5573 dcmd = &cmd->frame->dcmd; 5574 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0]; 5575 5576 if (instance->adapterresetinprogress) { 5577 con_log(CL_ANN1, (CE_NOTE, "Reset flag set, " 5578 "returning mfi_pkt and setting TRAN_BUSY")); 5579 return (DDI_FAILURE); 5580 } 5581 model = ddi_model_convert_from(mode & FMODELS); 5582 if (model == DDI_MODEL_ILP32) { 5583 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32")); 5584 5585 xferlen = kdcmd->sgl.sge32[0].length; 5586 5587 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 5588 } else { 5589 #ifdef _ILP32 5590 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32")); 5591 xferlen = kdcmd->sgl.sge32[0].length; 5592 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 5593 #else 5594 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_LP64")); 5595 xferlen = kdcmd->sgl.sge64[0].length; 5596 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr; 5597 #endif 5598 } 5599 if (xferlen) { 5600 /* means IOCTL requires DMA */ 5601 /* allocate the data transfer buffer */ 5602 /* dcmd_dma_obj.size = xferlen; */ 5603 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length, 5604 PAGESIZE); 5605 dcmd_dma_obj.size = new_xfer_length; 5606 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr; 5607 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 5608 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 5609 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1; 5610 dcmd_dma_obj.dma_attr.dma_attr_align = 1; 5611 5612 /* allocate kernel buffer for DMA */ 5613 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj, 5614 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 5615 con_log(CL_ANN, 5616 (CE_WARN, "issue_mfi_dcmd: could not " 5617 "allocate data transfer buffer.")); 5618 return (DDI_FAILURE); 5619 } 5620 (void) memset(dcmd_dma_obj.buffer, 0, xferlen); 5621 5622 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 5623 if (kdcmd->flags & MFI_FRAME_DIR_WRITE) { 5624 for (i = 0; i < xferlen; i++) { 5625 if (ddi_copyin((uint8_t *)ubuf + i, 5626 (uint8_t *)dcmd_dma_obj.buffer + i, 5627 1, mode)) { 5628 con_log(CL_ANN, (CE_WARN, 5629 "issue_mfi_dcmd : " 5630 "copy from user space failed")); 5631 return (DDI_FAILURE); 5632 } 5633 } 5634 } 5635 5636 kphys_addr = dcmd_dma_obj.dma_cookie[0].dmac_address; 5637 } 5638 5639 ddi_put8(acc_handle, &dcmd->cmd, kdcmd->cmd); 5640 ddi_put8(acc_handle, &dcmd->cmd_status, 0); 5641 ddi_put8(acc_handle, &dcmd->sge_count, kdcmd->sge_count); 5642 ddi_put16(acc_handle, &dcmd->timeout, kdcmd->timeout); 5643 ddi_put32(acc_handle, &dcmd->data_xfer_len, kdcmd->data_xfer_len); 5644 ddi_put32(acc_handle, &dcmd->opcode, kdcmd->opcode); 5645 5646 ddi_rep_put8(acc_handle, (uint8_t *)kdcmd->mbox.b, 5647 (uint8_t *)dcmd->mbox.b, DCMD_MBOX_SZ, DDI_DEV_AUTOINCR); 5648 5649 ddi_put16(acc_handle, &dcmd->flags, kdcmd->flags & ~MFI_FRAME_SGL64); 5650 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].length, xferlen); 5651 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].phys_addr, kphys_addr); 5652 5653 cmd->sync_cmd = MRSAS_TRUE; 5654 cmd->frame_count = 1; 5655 5656 if (instance->tbolt) { 5657 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 5658 } 5659 5660 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 5661 con_log(CL_ANN, (CE_WARN, "issue_mfi_dcmd: fw_ioctl failed")); 5662 } else { 5663 if (xferlen && (kdcmd->flags & MFI_FRAME_DIR_READ)) { 5664 for (i = 0; i < xferlen; i++) { 5665 if (ddi_copyout( 5666 (uint8_t *)dcmd_dma_obj.buffer + i, 5667 (uint8_t *)ubuf + i, 5668 1, mode)) { 5669 con_log(CL_ANN, (CE_WARN, 5670 "issue_mfi_dcmd : " 5671 "copy to user space failed")); 5672 return (DDI_FAILURE); 5673 } 5674 } 5675 } 5676 } 5677 5678 kdcmd->cmd_status = ddi_get8(acc_handle, &dcmd->cmd_status); 5679 con_log(CL_ANN, 5680 (CE_CONT, "issue_mfi_dcmd: cmd_status %x", kdcmd->cmd_status)); 5681 DTRACE_PROBE3(issue_dcmd, uint32_t, kdcmd->opcode, uint8_t, 5682 kdcmd->cmd, uint8_t, kdcmd->cmd_status); 5683 5684 if (xferlen) { 5685 /* free kernel buffer */ 5686 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS) 5687 return (DDI_FAILURE); 5688 } 5689 5690 return (DDI_SUCCESS); 5691 } 5692 5693 /* 5694 * issue_mfi_smp 5695 */ 5696 static int 5697 issue_mfi_smp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 5698 struct mrsas_cmd *cmd, int mode) 5699 { 5700 void *request_ubuf; 5701 void *response_ubuf; 5702 uint32_t request_xferlen = 0; 5703 uint32_t response_xferlen = 0; 5704 uint32_t new_xfer_length1 = 0; 5705 uint32_t new_xfer_length2 = 0; 5706 uint_t model; 5707 dma_obj_t request_dma_obj; 5708 dma_obj_t response_dma_obj; 5709 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 5710 struct mrsas_smp_frame *ksmp; 5711 struct mrsas_smp_frame *smp; 5712 struct mrsas_sge32 *sge32; 5713 #ifndef _ILP32 5714 struct mrsas_sge64 *sge64; 5715 #endif 5716 int i; 5717 uint64_t tmp_sas_addr; 5718 5719 smp = &cmd->frame->smp; 5720 ksmp = (struct mrsas_smp_frame *)&ioctl->frame[0]; 5721 5722 if (instance->adapterresetinprogress) { 5723 con_log(CL_ANN1, (CE_WARN, "Reset flag set, " 5724 "returning mfi_pkt and setting TRAN_BUSY\n")); 5725 return (DDI_FAILURE); 5726 } 5727 model = ddi_model_convert_from(mode & FMODELS); 5728 if (model == DDI_MODEL_ILP32) { 5729 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32")); 5730 5731 sge32 = &ksmp->sgl[0].sge32[0]; 5732 response_xferlen = sge32[0].length; 5733 request_xferlen = sge32[1].length; 5734 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: " 5735 "response_xferlen = %x, request_xferlen = %x", 5736 response_xferlen, request_xferlen)); 5737 5738 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr; 5739 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr; 5740 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: " 5741 "response_ubuf = %p, request_ubuf = %p", 5742 response_ubuf, request_ubuf)); 5743 } else { 5744 #ifdef _ILP32 5745 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32")); 5746 5747 sge32 = &ksmp->sgl[0].sge32[0]; 5748 response_xferlen = sge32[0].length; 5749 request_xferlen = sge32[1].length; 5750 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: " 5751 "response_xferlen = %x, request_xferlen = %x", 5752 response_xferlen, request_xferlen)); 5753 5754 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr; 5755 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr; 5756 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: " 5757 "response_ubuf = %p, request_ubuf = %p", 5758 response_ubuf, request_ubuf)); 5759 #else 5760 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_LP64")); 5761 5762 sge64 = &ksmp->sgl[0].sge64[0]; 5763 response_xferlen = sge64[0].length; 5764 request_xferlen = sge64[1].length; 5765 5766 response_ubuf = (void *)(ulong_t)sge64[0].phys_addr; 5767 request_ubuf = (void *)(ulong_t)sge64[1].phys_addr; 5768 #endif 5769 } 5770 if (request_xferlen) { 5771 /* means IOCTL requires DMA */ 5772 /* allocate the data transfer buffer */ 5773 /* request_dma_obj.size = request_xferlen; */ 5774 MRSAS_GET_BOUNDARY_ALIGNED_LEN(request_xferlen, 5775 new_xfer_length1, PAGESIZE); 5776 request_dma_obj.size = new_xfer_length1; 5777 request_dma_obj.dma_attr = mrsas_generic_dma_attr; 5778 request_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 5779 request_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 5780 request_dma_obj.dma_attr.dma_attr_sgllen = 1; 5781 request_dma_obj.dma_attr.dma_attr_align = 1; 5782 5783 /* allocate kernel buffer for DMA */ 5784 if (mrsas_alloc_dma_obj(instance, &request_dma_obj, 5785 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 5786 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 5787 "could not allocate data transfer buffer.")); 5788 return (DDI_FAILURE); 5789 } 5790 (void) memset(request_dma_obj.buffer, 0, request_xferlen); 5791 5792 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 5793 for (i = 0; i < request_xferlen; i++) { 5794 if (ddi_copyin((uint8_t *)request_ubuf + i, 5795 (uint8_t *)request_dma_obj.buffer + i, 5796 1, mode)) { 5797 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 5798 "copy from user space failed")); 5799 return (DDI_FAILURE); 5800 } 5801 } 5802 } 5803 5804 if (response_xferlen) { 5805 /* means IOCTL requires DMA */ 5806 /* allocate the data transfer buffer */ 5807 /* response_dma_obj.size = response_xferlen; */ 5808 MRSAS_GET_BOUNDARY_ALIGNED_LEN(response_xferlen, 5809 new_xfer_length2, PAGESIZE); 5810 response_dma_obj.size = new_xfer_length2; 5811 response_dma_obj.dma_attr = mrsas_generic_dma_attr; 5812 response_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 5813 response_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 5814 response_dma_obj.dma_attr.dma_attr_sgllen = 1; 5815 response_dma_obj.dma_attr.dma_attr_align = 1; 5816 5817 /* allocate kernel buffer for DMA */ 5818 if (mrsas_alloc_dma_obj(instance, &response_dma_obj, 5819 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 5820 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 5821 "could not allocate data transfer buffer.")); 5822 return (DDI_FAILURE); 5823 } 5824 (void) memset(response_dma_obj.buffer, 0, response_xferlen); 5825 5826 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 5827 for (i = 0; i < response_xferlen; i++) { 5828 if (ddi_copyin((uint8_t *)response_ubuf + i, 5829 (uint8_t *)response_dma_obj.buffer + i, 5830 1, mode)) { 5831 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: " 5832 "copy from user space failed")); 5833 return (DDI_FAILURE); 5834 } 5835 } 5836 } 5837 5838 ddi_put8(acc_handle, &smp->cmd, ksmp->cmd); 5839 ddi_put8(acc_handle, &smp->cmd_status, 0); 5840 ddi_put8(acc_handle, &smp->connection_status, 0); 5841 ddi_put8(acc_handle, &smp->sge_count, ksmp->sge_count); 5842 /* smp->context = ksmp->context; */ 5843 ddi_put16(acc_handle, &smp->timeout, ksmp->timeout); 5844 ddi_put32(acc_handle, &smp->data_xfer_len, ksmp->data_xfer_len); 5845 5846 bcopy((void *)&ksmp->sas_addr, (void *)&tmp_sas_addr, 5847 sizeof (uint64_t)); 5848 ddi_put64(acc_handle, &smp->sas_addr, tmp_sas_addr); 5849 5850 ddi_put16(acc_handle, &smp->flags, ksmp->flags & ~MFI_FRAME_SGL64); 5851 5852 model = ddi_model_convert_from(mode & FMODELS); 5853 if (model == DDI_MODEL_ILP32) { 5854 con_log(CL_ANN1, (CE_CONT, 5855 "issue_mfi_smp: DDI_MODEL_ILP32")); 5856 5857 sge32 = &smp->sgl[0].sge32[0]; 5858 ddi_put32(acc_handle, &sge32[0].length, response_xferlen); 5859 ddi_put32(acc_handle, &sge32[0].phys_addr, 5860 response_dma_obj.dma_cookie[0].dmac_address); 5861 ddi_put32(acc_handle, &sge32[1].length, request_xferlen); 5862 ddi_put32(acc_handle, &sge32[1].phys_addr, 5863 request_dma_obj.dma_cookie[0].dmac_address); 5864 } else { 5865 #ifdef _ILP32 5866 con_log(CL_ANN1, (CE_CONT, 5867 "issue_mfi_smp: DDI_MODEL_ILP32")); 5868 sge32 = &smp->sgl[0].sge32[0]; 5869 ddi_put32(acc_handle, &sge32[0].length, response_xferlen); 5870 ddi_put32(acc_handle, &sge32[0].phys_addr, 5871 response_dma_obj.dma_cookie[0].dmac_address); 5872 ddi_put32(acc_handle, &sge32[1].length, request_xferlen); 5873 ddi_put32(acc_handle, &sge32[1].phys_addr, 5874 request_dma_obj.dma_cookie[0].dmac_address); 5875 #else 5876 con_log(CL_ANN1, (CE_CONT, 5877 "issue_mfi_smp: DDI_MODEL_LP64")); 5878 sge64 = &smp->sgl[0].sge64[0]; 5879 ddi_put32(acc_handle, &sge64[0].length, response_xferlen); 5880 ddi_put64(acc_handle, &sge64[0].phys_addr, 5881 response_dma_obj.dma_cookie[0].dmac_address); 5882 ddi_put32(acc_handle, &sge64[1].length, request_xferlen); 5883 ddi_put64(acc_handle, &sge64[1].phys_addr, 5884 request_dma_obj.dma_cookie[0].dmac_address); 5885 #endif 5886 } 5887 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp : " 5888 "smp->response_xferlen = %d, smp->request_xferlen = %d " 5889 "smp->data_xfer_len = %d", ddi_get32(acc_handle, &sge32[0].length), 5890 ddi_get32(acc_handle, &sge32[1].length), 5891 ddi_get32(acc_handle, &smp->data_xfer_len))); 5892 5893 cmd->sync_cmd = MRSAS_TRUE; 5894 cmd->frame_count = 1; 5895 5896 if (instance->tbolt) { 5897 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 5898 } 5899 5900 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 5901 con_log(CL_ANN, (CE_WARN, 5902 "issue_mfi_smp: fw_ioctl failed")); 5903 } else { 5904 con_log(CL_ANN1, (CE_CONT, 5905 "issue_mfi_smp: copy to user space")); 5906 5907 if (request_xferlen) { 5908 for (i = 0; i < request_xferlen; i++) { 5909 if (ddi_copyout( 5910 (uint8_t *)request_dma_obj.buffer + 5911 i, (uint8_t *)request_ubuf + i, 5912 1, mode)) { 5913 con_log(CL_ANN, (CE_WARN, 5914 "issue_mfi_smp : copy to user space" 5915 " failed")); 5916 return (DDI_FAILURE); 5917 } 5918 } 5919 } 5920 5921 if (response_xferlen) { 5922 for (i = 0; i < response_xferlen; i++) { 5923 if (ddi_copyout( 5924 (uint8_t *)response_dma_obj.buffer 5925 + i, (uint8_t *)response_ubuf 5926 + i, 1, mode)) { 5927 con_log(CL_ANN, (CE_WARN, 5928 "issue_mfi_smp : copy to " 5929 "user space failed")); 5930 return (DDI_FAILURE); 5931 } 5932 } 5933 } 5934 } 5935 5936 ksmp->cmd_status = ddi_get8(acc_handle, &smp->cmd_status); 5937 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: smp->cmd_status = %d", 5938 ksmp->cmd_status)); 5939 DTRACE_PROBE2(issue_smp, uint8_t, ksmp->cmd, uint8_t, ksmp->cmd_status); 5940 5941 if (request_xferlen) { 5942 /* free kernel buffer */ 5943 if (mrsas_free_dma_obj(instance, request_dma_obj) != 5944 DDI_SUCCESS) 5945 return (DDI_FAILURE); 5946 } 5947 5948 if (response_xferlen) { 5949 /* free kernel buffer */ 5950 if (mrsas_free_dma_obj(instance, response_dma_obj) != 5951 DDI_SUCCESS) 5952 return (DDI_FAILURE); 5953 } 5954 5955 return (DDI_SUCCESS); 5956 } 5957 5958 /* 5959 * issue_mfi_stp 5960 */ 5961 static int 5962 issue_mfi_stp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 5963 struct mrsas_cmd *cmd, int mode) 5964 { 5965 void *fis_ubuf; 5966 void *data_ubuf; 5967 uint32_t fis_xferlen = 0; 5968 uint32_t new_xfer_length1 = 0; 5969 uint32_t new_xfer_length2 = 0; 5970 uint32_t data_xferlen = 0; 5971 uint_t model; 5972 dma_obj_t fis_dma_obj; 5973 dma_obj_t data_dma_obj; 5974 struct mrsas_stp_frame *kstp; 5975 struct mrsas_stp_frame *stp; 5976 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle; 5977 int i; 5978 5979 stp = &cmd->frame->stp; 5980 kstp = (struct mrsas_stp_frame *)&ioctl->frame[0]; 5981 5982 if (instance->adapterresetinprogress) { 5983 con_log(CL_ANN1, (CE_WARN, "Reset flag set, " 5984 "returning mfi_pkt and setting TRAN_BUSY\n")); 5985 return (DDI_FAILURE); 5986 } 5987 model = ddi_model_convert_from(mode & FMODELS); 5988 if (model == DDI_MODEL_ILP32) { 5989 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32")); 5990 5991 fis_xferlen = kstp->sgl.sge32[0].length; 5992 data_xferlen = kstp->sgl.sge32[1].length; 5993 5994 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr; 5995 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr; 5996 } else { 5997 #ifdef _ILP32 5998 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32")); 5999 6000 fis_xferlen = kstp->sgl.sge32[0].length; 6001 data_xferlen = kstp->sgl.sge32[1].length; 6002 6003 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr; 6004 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr; 6005 #else 6006 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_LP64")); 6007 6008 fis_xferlen = kstp->sgl.sge64[0].length; 6009 data_xferlen = kstp->sgl.sge64[1].length; 6010 6011 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge64[0].phys_addr; 6012 data_ubuf = (void *)(ulong_t)kstp->sgl.sge64[1].phys_addr; 6013 #endif 6014 } 6015 6016 6017 if (fis_xferlen) { 6018 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: " 6019 "fis_ubuf = %p fis_xferlen = %x", fis_ubuf, fis_xferlen)); 6020 6021 /* means IOCTL requires DMA */ 6022 /* allocate the data transfer buffer */ 6023 /* fis_dma_obj.size = fis_xferlen; */ 6024 MRSAS_GET_BOUNDARY_ALIGNED_LEN(fis_xferlen, 6025 new_xfer_length1, PAGESIZE); 6026 fis_dma_obj.size = new_xfer_length1; 6027 fis_dma_obj.dma_attr = mrsas_generic_dma_attr; 6028 fis_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 6029 fis_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 6030 fis_dma_obj.dma_attr.dma_attr_sgllen = 1; 6031 fis_dma_obj.dma_attr.dma_attr_align = 1; 6032 6033 /* allocate kernel buffer for DMA */ 6034 if (mrsas_alloc_dma_obj(instance, &fis_dma_obj, 6035 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 6036 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp : " 6037 "could not allocate data transfer buffer.")); 6038 return (DDI_FAILURE); 6039 } 6040 (void) memset(fis_dma_obj.buffer, 0, fis_xferlen); 6041 6042 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 6043 for (i = 0; i < fis_xferlen; i++) { 6044 if (ddi_copyin((uint8_t *)fis_ubuf + i, 6045 (uint8_t *)fis_dma_obj.buffer + i, 1, mode)) { 6046 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: " 6047 "copy from user space failed")); 6048 return (DDI_FAILURE); 6049 } 6050 } 6051 } 6052 6053 if (data_xferlen) { 6054 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: data_ubuf = %p " 6055 "data_xferlen = %x", data_ubuf, data_xferlen)); 6056 6057 /* means IOCTL requires DMA */ 6058 /* allocate the data transfer buffer */ 6059 /* data_dma_obj.size = data_xferlen; */ 6060 MRSAS_GET_BOUNDARY_ALIGNED_LEN(data_xferlen, new_xfer_length2, 6061 PAGESIZE); 6062 data_dma_obj.size = new_xfer_length2; 6063 data_dma_obj.dma_attr = mrsas_generic_dma_attr; 6064 data_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU; 6065 data_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU; 6066 data_dma_obj.dma_attr.dma_attr_sgllen = 1; 6067 data_dma_obj.dma_attr.dma_attr_align = 1; 6068 6069 /* allocate kernel buffer for DMA */ 6070 if (mrsas_alloc_dma_obj(instance, &data_dma_obj, 6071 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) { 6072 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: " 6073 "could not allocate data transfer buffer.")); 6074 return (DDI_FAILURE); 6075 } 6076 (void) memset(data_dma_obj.buffer, 0, data_xferlen); 6077 6078 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */ 6079 for (i = 0; i < data_xferlen; i++) { 6080 if (ddi_copyin((uint8_t *)data_ubuf + i, 6081 (uint8_t *)data_dma_obj.buffer + i, 1, mode)) { 6082 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: " 6083 "copy from user space failed")); 6084 return (DDI_FAILURE); 6085 } 6086 } 6087 } 6088 6089 ddi_put8(acc_handle, &stp->cmd, kstp->cmd); 6090 ddi_put8(acc_handle, &stp->cmd_status, 0); 6091 ddi_put8(acc_handle, &stp->connection_status, 0); 6092 ddi_put8(acc_handle, &stp->target_id, kstp->target_id); 6093 ddi_put8(acc_handle, &stp->sge_count, kstp->sge_count); 6094 6095 ddi_put16(acc_handle, &stp->timeout, kstp->timeout); 6096 ddi_put32(acc_handle, &stp->data_xfer_len, kstp->data_xfer_len); 6097 6098 ddi_rep_put8(acc_handle, (uint8_t *)kstp->fis, (uint8_t *)stp->fis, 10, 6099 DDI_DEV_AUTOINCR); 6100 6101 ddi_put16(acc_handle, &stp->flags, kstp->flags & ~MFI_FRAME_SGL64); 6102 ddi_put32(acc_handle, &stp->stp_flags, kstp->stp_flags); 6103 ddi_put32(acc_handle, &stp->sgl.sge32[0].length, fis_xferlen); 6104 ddi_put32(acc_handle, &stp->sgl.sge32[0].phys_addr, 6105 fis_dma_obj.dma_cookie[0].dmac_address); 6106 ddi_put32(acc_handle, &stp->sgl.sge32[1].length, data_xferlen); 6107 ddi_put32(acc_handle, &stp->sgl.sge32[1].phys_addr, 6108 data_dma_obj.dma_cookie[0].dmac_address); 6109 6110 cmd->sync_cmd = MRSAS_TRUE; 6111 cmd->frame_count = 1; 6112 6113 if (instance->tbolt) { 6114 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 6115 } 6116 6117 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) { 6118 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: fw_ioctl failed")); 6119 } else { 6120 6121 if (fis_xferlen) { 6122 for (i = 0; i < fis_xferlen; i++) { 6123 if (ddi_copyout( 6124 (uint8_t *)fis_dma_obj.buffer + i, 6125 (uint8_t *)fis_ubuf + i, 1, mode)) { 6126 con_log(CL_ANN, (CE_WARN, 6127 "issue_mfi_stp : copy to " 6128 "user space failed")); 6129 return (DDI_FAILURE); 6130 } 6131 } 6132 } 6133 } 6134 if (data_xferlen) { 6135 for (i = 0; i < data_xferlen; i++) { 6136 if (ddi_copyout( 6137 (uint8_t *)data_dma_obj.buffer + i, 6138 (uint8_t *)data_ubuf + i, 1, mode)) { 6139 con_log(CL_ANN, (CE_WARN, 6140 "issue_mfi_stp : copy to" 6141 " user space failed")); 6142 return (DDI_FAILURE); 6143 } 6144 } 6145 } 6146 6147 kstp->cmd_status = ddi_get8(acc_handle, &stp->cmd_status); 6148 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_stp: stp->cmd_status = %d", 6149 kstp->cmd_status)); 6150 DTRACE_PROBE2(issue_stp, uint8_t, kstp->cmd, uint8_t, kstp->cmd_status); 6151 6152 if (fis_xferlen) { 6153 /* free kernel buffer */ 6154 if (mrsas_free_dma_obj(instance, fis_dma_obj) != DDI_SUCCESS) 6155 return (DDI_FAILURE); 6156 } 6157 6158 if (data_xferlen) { 6159 /* free kernel buffer */ 6160 if (mrsas_free_dma_obj(instance, data_dma_obj) != DDI_SUCCESS) 6161 return (DDI_FAILURE); 6162 } 6163 6164 return (DDI_SUCCESS); 6165 } 6166 6167 /* 6168 * fill_up_drv_ver 6169 */ 6170 void 6171 fill_up_drv_ver(struct mrsas_drv_ver *dv) 6172 { 6173 (void) memset(dv, 0, sizeof (struct mrsas_drv_ver)); 6174 6175 (void) memcpy(dv->signature, "$LSI LOGIC$", strlen("$LSI LOGIC$")); 6176 (void) memcpy(dv->os_name, "Solaris", strlen("Solaris")); 6177 (void) memcpy(dv->drv_name, "mr_sas", strlen("mr_sas")); 6178 (void) memcpy(dv->drv_ver, MRSAS_VERSION, strlen(MRSAS_VERSION)); 6179 (void) memcpy(dv->drv_rel_date, MRSAS_RELDATE, 6180 strlen(MRSAS_RELDATE)); 6181 6182 } 6183 6184 /* 6185 * handle_drv_ioctl 6186 */ 6187 static int 6188 handle_drv_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 6189 int mode) 6190 { 6191 int i; 6192 int rval = DDI_SUCCESS; 6193 int *props = NULL; 6194 void *ubuf; 6195 6196 uint8_t *pci_conf_buf; 6197 uint32_t xferlen; 6198 uint32_t num_props; 6199 uint_t model; 6200 struct mrsas_dcmd_frame *kdcmd; 6201 struct mrsas_drv_ver dv; 6202 struct mrsas_pci_information pi; 6203 6204 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0]; 6205 6206 model = ddi_model_convert_from(mode & FMODELS); 6207 if (model == DDI_MODEL_ILP32) { 6208 con_log(CL_ANN1, (CE_CONT, 6209 "handle_drv_ioctl: DDI_MODEL_ILP32")); 6210 6211 xferlen = kdcmd->sgl.sge32[0].length; 6212 6213 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 6214 } else { 6215 #ifdef _ILP32 6216 con_log(CL_ANN1, (CE_CONT, 6217 "handle_drv_ioctl: DDI_MODEL_ILP32")); 6218 xferlen = kdcmd->sgl.sge32[0].length; 6219 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr; 6220 #else 6221 con_log(CL_ANN1, (CE_CONT, 6222 "handle_drv_ioctl: DDI_MODEL_LP64")); 6223 xferlen = kdcmd->sgl.sge64[0].length; 6224 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr; 6225 #endif 6226 } 6227 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: " 6228 "dataBuf=%p size=%d bytes", ubuf, xferlen)); 6229 6230 switch (kdcmd->opcode) { 6231 case MRSAS_DRIVER_IOCTL_DRIVER_VERSION: 6232 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: " 6233 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION")); 6234 6235 fill_up_drv_ver(&dv); 6236 6237 if (ddi_copyout(&dv, ubuf, xferlen, mode)) { 6238 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 6239 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION : " 6240 "copy to user space failed")); 6241 kdcmd->cmd_status = 1; 6242 rval = 1; 6243 } else { 6244 kdcmd->cmd_status = 0; 6245 } 6246 break; 6247 case MRSAS_DRIVER_IOCTL_PCI_INFORMATION: 6248 con_log(CL_ANN1, (CE_NOTE, "handle_drv_ioctl: " 6249 "MRSAS_DRIVER_IOCTL_PCI_INFORMAITON")); 6250 6251 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, instance->dip, 6252 0, "reg", &props, &num_props)) { 6253 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 6254 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : " 6255 "ddi_prop_look_int_array failed")); 6256 rval = DDI_FAILURE; 6257 } else { 6258 6259 pi.busNumber = (props[0] >> 16) & 0xFF; 6260 pi.deviceNumber = (props[0] >> 11) & 0x1f; 6261 pi.functionNumber = (props[0] >> 8) & 0x7; 6262 ddi_prop_free((void *)props); 6263 } 6264 6265 pci_conf_buf = (uint8_t *)&pi.pciHeaderInfo; 6266 6267 for (i = 0; i < (sizeof (struct mrsas_pci_information) - 6268 offsetof(struct mrsas_pci_information, pciHeaderInfo)); 6269 i++) { 6270 pci_conf_buf[i] = 6271 pci_config_get8(instance->pci_handle, i); 6272 } 6273 6274 if (ddi_copyout(&pi, ubuf, xferlen, mode)) { 6275 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 6276 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : " 6277 "copy to user space failed")); 6278 kdcmd->cmd_status = 1; 6279 rval = 1; 6280 } else { 6281 kdcmd->cmd_status = 0; 6282 } 6283 break; 6284 default: 6285 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: " 6286 "invalid driver specific IOCTL opcode = 0x%x", 6287 kdcmd->opcode)); 6288 kdcmd->cmd_status = 1; 6289 rval = DDI_FAILURE; 6290 break; 6291 } 6292 6293 return (rval); 6294 } 6295 6296 /* 6297 * handle_mfi_ioctl 6298 */ 6299 static int 6300 handle_mfi_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl, 6301 int mode) 6302 { 6303 int rval = DDI_SUCCESS; 6304 6305 struct mrsas_header *hdr; 6306 struct mrsas_cmd *cmd; 6307 6308 if (instance->tbolt) { 6309 cmd = get_raid_msg_mfi_pkt(instance); 6310 } else { 6311 cmd = mrsas_get_mfi_pkt(instance); 6312 } 6313 if (!cmd) { 6314 con_log(CL_ANN, (CE_WARN, "mr_sas: " 6315 "failed to get a cmd packet")); 6316 DTRACE_PROBE2(mfi_ioctl_err, uint16_t, 6317 instance->fw_outstanding, uint16_t, instance->max_fw_cmds); 6318 return (DDI_FAILURE); 6319 } 6320 6321 /* Clear the frame buffer and assign back the context id */ 6322 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 6323 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 6324 cmd->index); 6325 6326 hdr = (struct mrsas_header *)&ioctl->frame[0]; 6327 6328 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) { 6329 case MFI_CMD_OP_DCMD: 6330 rval = issue_mfi_dcmd(instance, ioctl, cmd, mode); 6331 break; 6332 case MFI_CMD_OP_SMP: 6333 rval = issue_mfi_smp(instance, ioctl, cmd, mode); 6334 break; 6335 case MFI_CMD_OP_STP: 6336 rval = issue_mfi_stp(instance, ioctl, cmd, mode); 6337 break; 6338 case MFI_CMD_OP_LD_SCSI: 6339 case MFI_CMD_OP_PD_SCSI: 6340 rval = issue_mfi_pthru(instance, ioctl, cmd, mode); 6341 break; 6342 default: 6343 con_log(CL_ANN, (CE_WARN, "handle_mfi_ioctl: " 6344 "invalid mfi ioctl hdr->cmd = %d", hdr->cmd)); 6345 rval = DDI_FAILURE; 6346 break; 6347 } 6348 6349 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) 6350 rval = DDI_FAILURE; 6351 6352 if (instance->tbolt) { 6353 return_raid_msg_mfi_pkt(instance, cmd); 6354 } else { 6355 mrsas_return_mfi_pkt(instance, cmd); 6356 } 6357 6358 return (rval); 6359 } 6360 6361 /* 6362 * AEN 6363 */ 6364 static int 6365 handle_mfi_aen(struct mrsas_instance *instance, struct mrsas_aen *aen) 6366 { 6367 int rval = 0; 6368 6369 rval = register_mfi_aen(instance, instance->aen_seq_num, 6370 aen->class_locale_word); 6371 6372 aen->cmd_status = (uint8_t)rval; 6373 6374 return (rval); 6375 } 6376 6377 static int 6378 register_mfi_aen(struct mrsas_instance *instance, uint32_t seq_num, 6379 uint32_t class_locale_word) 6380 { 6381 int ret_val; 6382 6383 struct mrsas_cmd *cmd, *aen_cmd; 6384 struct mrsas_dcmd_frame *dcmd; 6385 union mrsas_evt_class_locale curr_aen; 6386 union mrsas_evt_class_locale prev_aen; 6387 6388 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 6389 /* 6390 * If there an AEN pending already (aen_cmd), check if the 6391 * class_locale of that pending AEN is inclusive of the new 6392 * AEN request we currently have. If it is, then we don't have 6393 * to do anything. In other words, whichever events the current 6394 * AEN request is subscribing to, have already been subscribed 6395 * to. 6396 * 6397 * If the old_cmd is _not_ inclusive, then we have to abort 6398 * that command, form a class_locale that is superset of both 6399 * old and current and re-issue to the FW 6400 */ 6401 6402 curr_aen.word = LE_32(class_locale_word); 6403 curr_aen.members.locale = LE_16(curr_aen.members.locale); 6404 aen_cmd = instance->aen_cmd; 6405 if (aen_cmd) { 6406 prev_aen.word = ddi_get32(aen_cmd->frame_dma_obj.acc_handle, 6407 &aen_cmd->frame->dcmd.mbox.w[1]); 6408 prev_aen.word = LE_32(prev_aen.word); 6409 prev_aen.members.locale = LE_16(prev_aen.members.locale); 6410 /* 6411 * A class whose enum value is smaller is inclusive of all 6412 * higher values. If a PROGRESS (= -1) was previously 6413 * registered, then a new registration requests for higher 6414 * classes need not be sent to FW. They are automatically 6415 * included. 6416 * 6417 * Locale numbers don't have such hierarchy. They are bitmap 6418 * values 6419 */ 6420 if ((prev_aen.members.class <= curr_aen.members.class) && 6421 !((prev_aen.members.locale & curr_aen.members.locale) ^ 6422 curr_aen.members.locale)) { 6423 /* 6424 * Previously issued event registration includes 6425 * current request. Nothing to do. 6426 */ 6427 6428 return (0); 6429 } else { 6430 curr_aen.members.locale |= prev_aen.members.locale; 6431 6432 if (prev_aen.members.class < curr_aen.members.class) 6433 curr_aen.members.class = prev_aen.members.class; 6434 6435 ret_val = abort_aen_cmd(instance, aen_cmd); 6436 6437 if (ret_val) { 6438 con_log(CL_ANN, (CE_WARN, "register_mfi_aen: " 6439 "failed to abort prevous AEN command")); 6440 6441 return (ret_val); 6442 } 6443 } 6444 } else { 6445 curr_aen.word = LE_32(class_locale_word); 6446 curr_aen.members.locale = LE_16(curr_aen.members.locale); 6447 } 6448 6449 if (instance->tbolt) { 6450 cmd = get_raid_msg_mfi_pkt(instance); 6451 } else { 6452 cmd = mrsas_get_mfi_pkt(instance); 6453 } 6454 6455 if (!cmd) { 6456 DTRACE_PROBE2(mfi_aen_err, uint16_t, instance->fw_outstanding, 6457 uint16_t, instance->max_fw_cmds); 6458 return (ENOMEM); 6459 } 6460 6461 /* Clear the frame buffer and assign back the context id */ 6462 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame)); 6463 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context, 6464 cmd->index); 6465 6466 dcmd = &cmd->frame->dcmd; 6467 6468 /* for(i = 0; i < DCMD_MBOX_SZ; i++) dcmd->mbox.b[i] = 0; */ 6469 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ); 6470 6471 (void) memset(instance->mfi_evt_detail_obj.buffer, 0, 6472 sizeof (struct mrsas_evt_detail)); 6473 6474 /* Prepare DCMD for aen registration */ 6475 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD); 6476 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0); 6477 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1); 6478 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags, 6479 MFI_FRAME_DIR_READ); 6480 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0); 6481 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 6482 sizeof (struct mrsas_evt_detail)); 6483 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode, 6484 MR_DCMD_CTRL_EVENT_WAIT); 6485 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[0], seq_num); 6486 curr_aen.members.locale = LE_16(curr_aen.members.locale); 6487 curr_aen.word = LE_32(curr_aen.word); 6488 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[1], 6489 curr_aen.word); 6490 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr, 6491 instance->mfi_evt_detail_obj.dma_cookie[0].dmac_address); 6492 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length, 6493 sizeof (struct mrsas_evt_detail)); 6494 6495 instance->aen_seq_num = seq_num; 6496 6497 6498 /* 6499 * Store reference to the cmd used to register for AEN. When an 6500 * application wants us to register for AEN, we have to abort this 6501 * cmd and re-register with a new EVENT LOCALE supplied by that app 6502 */ 6503 instance->aen_cmd = cmd; 6504 6505 cmd->frame_count = 1; 6506 6507 /* Issue the aen registration frame */ 6508 /* atomic_add_16 (&instance->fw_outstanding, 1); */ 6509 if (instance->tbolt) { 6510 mr_sas_tbolt_build_mfi_cmd(instance, cmd); 6511 } 6512 instance->func_ptr->issue_cmd(cmd, instance); 6513 6514 return (0); 6515 } 6516 6517 void 6518 display_scsi_inquiry(caddr_t scsi_inq) 6519 { 6520 #define MAX_SCSI_DEVICE_CODE 14 6521 int i; 6522 char inquiry_buf[256] = {0}; 6523 int len; 6524 const char *const scsi_device_types[] = { 6525 "Direct-Access ", 6526 "Sequential-Access", 6527 "Printer ", 6528 "Processor ", 6529 "WORM ", 6530 "CD-ROM ", 6531 "Scanner ", 6532 "Optical Device ", 6533 "Medium Changer ", 6534 "Communications ", 6535 "Unknown ", 6536 "Unknown ", 6537 "Unknown ", 6538 "Enclosure ", 6539 }; 6540 6541 len = 0; 6542 6543 len += snprintf(inquiry_buf + len, 265 - len, " Vendor: "); 6544 for (i = 8; i < 16; i++) { 6545 len += snprintf(inquiry_buf + len, 265 - len, "%c", 6546 scsi_inq[i]); 6547 } 6548 6549 len += snprintf(inquiry_buf + len, 265 - len, " Model: "); 6550 6551 for (i = 16; i < 32; i++) { 6552 len += snprintf(inquiry_buf + len, 265 - len, "%c", 6553 scsi_inq[i]); 6554 } 6555 6556 len += snprintf(inquiry_buf + len, 265 - len, " Rev: "); 6557 6558 for (i = 32; i < 36; i++) { 6559 len += snprintf(inquiry_buf + len, 265 - len, "%c", 6560 scsi_inq[i]); 6561 } 6562 6563 len += snprintf(inquiry_buf + len, 265 - len, "\n"); 6564 6565 6566 i = scsi_inq[0] & 0x1f; 6567 6568 6569 len += snprintf(inquiry_buf + len, 265 - len, " Type: %s ", 6570 i < MAX_SCSI_DEVICE_CODE ? scsi_device_types[i] : 6571 "Unknown "); 6572 6573 6574 len += snprintf(inquiry_buf + len, 265 - len, 6575 " ANSI SCSI revision: %02x", scsi_inq[2] & 0x07); 6576 6577 if ((scsi_inq[2] & 0x07) == 1 && (scsi_inq[3] & 0x0f) == 1) { 6578 len += snprintf(inquiry_buf + len, 265 - len, " CCS\n"); 6579 } else { 6580 len += snprintf(inquiry_buf + len, 265 - len, "\n"); 6581 } 6582 6583 con_log(CL_DLEVEL2, (CE_CONT, inquiry_buf)); 6584 } 6585 6586 static void 6587 io_timeout_checker(void *arg) 6588 { 6589 struct scsi_pkt *pkt; 6590 struct mrsas_instance *instance = arg; 6591 struct mrsas_cmd *cmd = NULL; 6592 struct mrsas_header *hdr; 6593 int time = 0; 6594 int counter = 0; 6595 struct mlist_head *pos, *next; 6596 mlist_t process_list; 6597 6598 if (instance->adapterresetinprogress == 1) { 6599 con_log(CL_ANN, (CE_NOTE, "io_timeout_checker:" 6600 " reset in progress")); 6601 6602 instance->timeout_id = timeout(io_timeout_checker, 6603 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 6604 return; 6605 } 6606 6607 /* See if this check needs to be in the beginning or last in ISR */ 6608 if (mrsas_initiate_ocr_if_fw_is_faulty(instance) == 1) { 6609 dev_err(instance->dip, CE_WARN, "io_timeout_checker: " 6610 "FW Fault, calling reset adapter"); 6611 dev_err(instance->dip, CE_CONT, "io_timeout_checker: " 6612 "fw_outstanding 0x%X max_fw_cmds 0x%X", 6613 instance->fw_outstanding, instance->max_fw_cmds); 6614 if (instance->adapterresetinprogress == 0) { 6615 instance->adapterresetinprogress = 1; 6616 if (instance->tbolt) 6617 (void) mrsas_tbolt_reset_ppc(instance); 6618 else 6619 (void) mrsas_reset_ppc(instance); 6620 instance->adapterresetinprogress = 0; 6621 } 6622 instance->timeout_id = timeout(io_timeout_checker, 6623 (void *) instance, drv_usectohz(MRSAS_1_SECOND)); 6624 return; 6625 } 6626 6627 INIT_LIST_HEAD(&process_list); 6628 6629 mutex_enter(&instance->cmd_pend_mtx); 6630 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) { 6631 cmd = mlist_entry(pos, struct mrsas_cmd, list); 6632 6633 if (cmd == NULL) { 6634 continue; 6635 } 6636 6637 if (cmd->sync_cmd == MRSAS_TRUE) { 6638 hdr = (struct mrsas_header *)&cmd->frame->hdr; 6639 if (hdr == NULL) { 6640 continue; 6641 } 6642 time = --cmd->drv_pkt_time; 6643 } else { 6644 pkt = cmd->pkt; 6645 if (pkt == NULL) { 6646 continue; 6647 } 6648 time = --cmd->drv_pkt_time; 6649 } 6650 if (time <= 0) { 6651 dev_err(instance->dip, CE_WARN, "%llx: " 6652 "io_timeout_checker: TIMING OUT: pkt: %p, " 6653 "cmd %p fw_outstanding 0x%X max_fw_cmds 0x%X", 6654 gethrtime(), (void *)pkt, (void *)cmd, 6655 instance->fw_outstanding, instance->max_fw_cmds); 6656 6657 counter++; 6658 break; 6659 } 6660 } 6661 mutex_exit(&instance->cmd_pend_mtx); 6662 6663 if (counter) { 6664 if (instance->disable_online_ctrl_reset == 1) { 6665 dev_err(instance->dip, CE_WARN, "%s(): OCR is NOT " 6666 "supported by Firmware, KILL adapter!!!", 6667 __func__); 6668 6669 if (instance->tbolt) 6670 mrsas_tbolt_kill_adapter(instance); 6671 else 6672 (void) mrsas_kill_adapter(instance); 6673 6674 return; 6675 } else { 6676 if (cmd->retry_count_for_ocr <= IO_RETRY_COUNT) { 6677 if (instance->adapterresetinprogress == 0) { 6678 if (instance->tbolt) { 6679 (void) mrsas_tbolt_reset_ppc( 6680 instance); 6681 } else { 6682 (void) mrsas_reset_ppc( 6683 instance); 6684 } 6685 } 6686 } else { 6687 dev_err(instance->dip, CE_WARN, 6688 "io_timeout_checker: " 6689 "cmd %p cmd->index %d " 6690 "timed out even after 3 resets: " 6691 "so KILL adapter", (void *)cmd, cmd->index); 6692 6693 mrsas_print_cmd_details(instance, cmd, 0xDD); 6694 6695 if (instance->tbolt) 6696 mrsas_tbolt_kill_adapter(instance); 6697 else 6698 (void) mrsas_kill_adapter(instance); 6699 return; 6700 } 6701 } 6702 } 6703 con_log(CL_ANN, (CE_NOTE, "mrsas: " 6704 "schedule next timeout check: " 6705 "do timeout \n")); 6706 instance->timeout_id = 6707 timeout(io_timeout_checker, (void *)instance, 6708 drv_usectohz(MRSAS_1_SECOND)); 6709 } 6710 6711 static uint32_t 6712 read_fw_status_reg_ppc(struct mrsas_instance *instance) 6713 { 6714 return ((uint32_t)RD_OB_SCRATCH_PAD_0(instance)); 6715 } 6716 6717 static void 6718 issue_cmd_ppc(struct mrsas_cmd *cmd, struct mrsas_instance *instance) 6719 { 6720 struct scsi_pkt *pkt; 6721 atomic_inc_16(&instance->fw_outstanding); 6722 6723 pkt = cmd->pkt; 6724 if (pkt) { 6725 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:" 6726 "ISSUED CMD TO FW : called : cmd:" 6727 ": %p instance : %p pkt : %p pkt_time : %x\n", 6728 gethrtime(), (void *)cmd, (void *)instance, 6729 (void *)pkt, cmd->drv_pkt_time)); 6730 if (instance->adapterresetinprogress) { 6731 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 6732 con_log(CL_ANN1, (CE_NOTE, "Reset the scsi_pkt timer")); 6733 } else { 6734 push_pending_mfi_pkt(instance, cmd); 6735 } 6736 6737 } else { 6738 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:" 6739 "ISSUED CMD TO FW : called : cmd : %p, instance: %p" 6740 "(NO PKT)\n", gethrtime(), (void *)cmd, (void *)instance)); 6741 } 6742 6743 mutex_enter(&instance->reg_write_mtx); 6744 /* Issue the command to the FW */ 6745 WR_IB_PICK_QPORT((cmd->frame_phys_addr) | 6746 (((cmd->frame_count - 1) << 1) | 1), instance); 6747 mutex_exit(&instance->reg_write_mtx); 6748 6749 } 6750 6751 /* 6752 * issue_cmd_in_sync_mode 6753 */ 6754 static int 6755 issue_cmd_in_sync_mode_ppc(struct mrsas_instance *instance, 6756 struct mrsas_cmd *cmd) 6757 { 6758 int i; 6759 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC; 6760 struct mrsas_header *hdr = &cmd->frame->hdr; 6761 6762 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: called")); 6763 6764 if (instance->adapterresetinprogress) { 6765 cmd->drv_pkt_time = ddi_get16( 6766 cmd->frame_dma_obj.acc_handle, &hdr->timeout); 6767 if (cmd->drv_pkt_time < debug_timeout_g) 6768 cmd->drv_pkt_time = (uint16_t)debug_timeout_g; 6769 6770 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: " 6771 "issue and return in reset case\n")); 6772 WR_IB_PICK_QPORT((cmd->frame_phys_addr) | 6773 (((cmd->frame_count - 1) << 1) | 1), instance); 6774 6775 return (DDI_SUCCESS); 6776 } else { 6777 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: pushing the pkt\n")); 6778 push_pending_mfi_pkt(instance, cmd); 6779 } 6780 6781 cmd->cmd_status = ENODATA; 6782 6783 mutex_enter(&instance->reg_write_mtx); 6784 /* Issue the command to the FW */ 6785 WR_IB_PICK_QPORT((cmd->frame_phys_addr) | 6786 (((cmd->frame_count - 1) << 1) | 1), instance); 6787 mutex_exit(&instance->reg_write_mtx); 6788 6789 mutex_enter(&instance->int_cmd_mtx); 6790 for (i = 0; i < msecs && (cmd->cmd_status == ENODATA); i++) { 6791 cv_wait(&instance->int_cmd_cv, &instance->int_cmd_mtx); 6792 } 6793 mutex_exit(&instance->int_cmd_mtx); 6794 6795 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: done")); 6796 6797 if (i < (msecs -1)) { 6798 return (DDI_SUCCESS); 6799 } else { 6800 return (DDI_FAILURE); 6801 } 6802 } 6803 6804 /* 6805 * issue_cmd_in_poll_mode 6806 */ 6807 static int 6808 issue_cmd_in_poll_mode_ppc(struct mrsas_instance *instance, 6809 struct mrsas_cmd *cmd) 6810 { 6811 int i; 6812 uint16_t flags; 6813 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC; 6814 struct mrsas_header *frame_hdr; 6815 6816 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_poll_mode_ppc: called")); 6817 6818 frame_hdr = (struct mrsas_header *)cmd->frame; 6819 ddi_put8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status, 6820 MFI_CMD_STATUS_POLL_MODE); 6821 flags = ddi_get16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags); 6822 flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 6823 6824 ddi_put16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags, flags); 6825 6826 /* issue the frame using inbound queue port */ 6827 WR_IB_PICK_QPORT((cmd->frame_phys_addr) | 6828 (((cmd->frame_count - 1) << 1) | 1), instance); 6829 6830 /* wait for cmd_status to change from 0xFF */ 6831 for (i = 0; i < msecs && ( 6832 ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status) 6833 == MFI_CMD_STATUS_POLL_MODE); i++) { 6834 drv_usecwait(MILLISEC); /* wait for 1000 usecs */ 6835 } 6836 6837 if (ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status) 6838 == MFI_CMD_STATUS_POLL_MODE) { 6839 con_log(CL_ANN, (CE_NOTE, "issue_cmd_in_poll_mode: " 6840 "cmd polling timed out")); 6841 return (DDI_FAILURE); 6842 } 6843 6844 return (DDI_SUCCESS); 6845 } 6846 6847 static void 6848 enable_intr_ppc(struct mrsas_instance *instance) 6849 { 6850 uint32_t mask; 6851 6852 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: called")); 6853 6854 if (instance->skinny) { 6855 /* For SKINNY, write ~0x1, from BSD's mfi driver. */ 6856 WR_OB_INTR_MASK(0xfffffffe, instance); 6857 } else { 6858 /* WR_OB_DOORBELL_CLEAR(0xFFFFFFFF, instance); */ 6859 WR_OB_DOORBELL_CLEAR(OB_DOORBELL_CLEAR_MASK, instance); 6860 6861 /* WR_OB_INTR_MASK(~0x80000000, instance); */ 6862 WR_OB_INTR_MASK(~(MFI_REPLY_2108_MESSAGE_INTR_MASK), instance); 6863 } 6864 6865 /* dummy read to force PCI flush */ 6866 mask = RD_OB_INTR_MASK(instance); 6867 6868 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: " 6869 "outbound_intr_mask = 0x%x", mask)); 6870 } 6871 6872 static void 6873 disable_intr_ppc(struct mrsas_instance *instance) 6874 { 6875 uint32_t mask; 6876 6877 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: called")); 6878 6879 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: before : " 6880 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance))); 6881 6882 /* For now, assume there are no extras needed for Skinny support. */ 6883 6884 WR_OB_INTR_MASK(OB_INTR_MASK, instance); 6885 6886 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: after : " 6887 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance))); 6888 6889 /* dummy read to force PCI flush */ 6890 mask = RD_OB_INTR_MASK(instance); 6891 #ifdef lint 6892 mask = mask; 6893 #endif 6894 } 6895 6896 static int 6897 intr_ack_ppc(struct mrsas_instance *instance) 6898 { 6899 uint32_t status; 6900 int ret = DDI_INTR_CLAIMED; 6901 6902 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: called")); 6903 6904 /* check if it is our interrupt */ 6905 status = RD_OB_INTR_STATUS(instance); 6906 6907 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: status = 0x%x", status)); 6908 6909 /* 6910 * NOTE: Some drivers call out SKINNY here, but the return is the same 6911 * for SKINNY and 2108. 6912 */ 6913 if (!(status & MFI_REPLY_2108_MESSAGE_INTR)) { 6914 ret = DDI_INTR_UNCLAIMED; 6915 } 6916 6917 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) { 6918 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST); 6919 ret = DDI_INTR_UNCLAIMED; 6920 } 6921 6922 if (ret == DDI_INTR_UNCLAIMED) { 6923 return (ret); 6924 } 6925 6926 /* 6927 * Clear the interrupt by writing back the same value. 6928 * Another case where SKINNY is slightly different. 6929 */ 6930 if (instance->skinny) { 6931 WR_OB_INTR_STATUS(status, instance); 6932 } else { 6933 WR_OB_DOORBELL_CLEAR(status, instance); 6934 } 6935 6936 /* dummy READ */ 6937 status = RD_OB_INTR_STATUS(instance); 6938 6939 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: interrupt cleared")); 6940 6941 return (ret); 6942 } 6943 6944 /* 6945 * Marks HBA as bad. This will be called either when an 6946 * IO packet times out even after 3 FW resets 6947 * or FW is found to be fault even after 3 continuous resets. 6948 */ 6949 6950 static int 6951 mrsas_kill_adapter(struct mrsas_instance *instance) 6952 { 6953 if (instance->deadadapter == 1) 6954 return (DDI_FAILURE); 6955 6956 con_log(CL_ANN1, (CE_NOTE, "mrsas_kill_adapter: " 6957 "Writing to doorbell with MFI_STOP_ADP ")); 6958 mutex_enter(&instance->ocr_flags_mtx); 6959 instance->deadadapter = 1; 6960 mutex_exit(&instance->ocr_flags_mtx); 6961 instance->func_ptr->disable_intr(instance); 6962 WR_IB_DOORBELL(MFI_STOP_ADP, instance); 6963 (void) mrsas_complete_pending_cmds(instance); 6964 return (DDI_SUCCESS); 6965 } 6966 6967 6968 static int 6969 mrsas_reset_ppc(struct mrsas_instance *instance) 6970 { 6971 uint32_t status; 6972 uint32_t retry = 0; 6973 uint32_t cur_abs_reg_val; 6974 uint32_t fw_state; 6975 6976 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__)); 6977 6978 if (instance->deadadapter == 1) { 6979 dev_err(instance->dip, CE_WARN, "mrsas_reset_ppc: " 6980 "no more resets as HBA has been marked dead "); 6981 return (DDI_FAILURE); 6982 } 6983 mutex_enter(&instance->ocr_flags_mtx); 6984 instance->adapterresetinprogress = 1; 6985 mutex_exit(&instance->ocr_flags_mtx); 6986 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: adpterresetinprogress " 6987 "flag set, time %llx", gethrtime())); 6988 6989 instance->func_ptr->disable_intr(instance); 6990 retry_reset: 6991 WR_IB_WRITE_SEQ(0, instance); 6992 WR_IB_WRITE_SEQ(4, instance); 6993 WR_IB_WRITE_SEQ(0xb, instance); 6994 WR_IB_WRITE_SEQ(2, instance); 6995 WR_IB_WRITE_SEQ(7, instance); 6996 WR_IB_WRITE_SEQ(0xd, instance); 6997 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: magic number written " 6998 "to write sequence register\n")); 6999 delay(100 * drv_usectohz(MILLISEC)); 7000 status = RD_OB_DRWE(instance); 7001 7002 while (!(status & DIAG_WRITE_ENABLE)) { 7003 delay(100 * drv_usectohz(MILLISEC)); 7004 status = RD_OB_DRWE(instance); 7005 if (retry++ == 100) { 7006 dev_err(instance->dip, CE_WARN, 7007 "mrsas_reset_ppc: DRWE bit " 7008 "check retry count %d", retry); 7009 return (DDI_FAILURE); 7010 } 7011 } 7012 WR_IB_DRWE(status | DIAG_RESET_ADAPTER, instance); 7013 delay(100 * drv_usectohz(MILLISEC)); 7014 status = RD_OB_DRWE(instance); 7015 while (status & DIAG_RESET_ADAPTER) { 7016 delay(100 * drv_usectohz(MILLISEC)); 7017 status = RD_OB_DRWE(instance); 7018 if (retry++ == 100) { 7019 dev_err(instance->dip, CE_WARN, "mrsas_reset_ppc: " 7020 "RESET FAILED. KILL adapter called."); 7021 7022 (void) mrsas_kill_adapter(instance); 7023 return (DDI_FAILURE); 7024 } 7025 } 7026 con_log(CL_ANN, (CE_NOTE, "mrsas_reset_ppc: Adapter reset complete")); 7027 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7028 "Calling mfi_state_transition_to_ready")); 7029 7030 /* Mark HBA as bad, if FW is fault after 3 continuous resets */ 7031 if (mfi_state_transition_to_ready(instance) || 7032 debug_fw_faults_after_ocr_g == 1) { 7033 cur_abs_reg_val = 7034 instance->func_ptr->read_fw_status_reg(instance); 7035 fw_state = cur_abs_reg_val & MFI_STATE_MASK; 7036 7037 #ifdef OCRDEBUG 7038 con_log(CL_ANN1, (CE_NOTE, 7039 "mrsas_reset_ppc :before fake: FW is not ready " 7040 "FW state = 0x%x", fw_state)); 7041 if (debug_fw_faults_after_ocr_g == 1) 7042 fw_state = MFI_STATE_FAULT; 7043 #endif 7044 7045 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc : FW is not ready " 7046 "FW state = 0x%x", fw_state)); 7047 7048 if (fw_state == MFI_STATE_FAULT) { 7049 /* increment the count */ 7050 instance->fw_fault_count_after_ocr++; 7051 if (instance->fw_fault_count_after_ocr 7052 < MAX_FW_RESET_COUNT) { 7053 dev_err(instance->dip, CE_WARN, 7054 "mrsas_reset_ppc: " 7055 "FW is in fault after OCR count %d " 7056 "Retry Reset", 7057 instance->fw_fault_count_after_ocr); 7058 goto retry_reset; 7059 7060 } else { 7061 dev_err(instance->dip, CE_WARN, 7062 "mrsas_reset_ppc: " 7063 "Max Reset Count exceeded >%d" 7064 "Mark HBA as bad, KILL adapter", 7065 MAX_FW_RESET_COUNT); 7066 7067 (void) mrsas_kill_adapter(instance); 7068 return (DDI_FAILURE); 7069 } 7070 } 7071 } 7072 /* reset the counter as FW is up after OCR */ 7073 instance->fw_fault_count_after_ocr = 0; 7074 7075 7076 ddi_put32(instance->mfi_internal_dma_obj.acc_handle, 7077 instance->producer, 0); 7078 7079 ddi_put32(instance->mfi_internal_dma_obj.acc_handle, 7080 instance->consumer, 0); 7081 7082 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7083 " after resetting produconsumer chck indexs:" 7084 "producer %x consumer %x", *instance->producer, 7085 *instance->consumer)); 7086 7087 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7088 "Calling mrsas_issue_init_mfi")); 7089 (void) mrsas_issue_init_mfi(instance); 7090 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7091 "mrsas_issue_init_mfi Done")); 7092 7093 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7094 "Calling mrsas_print_pending_cmd\n")); 7095 (void) mrsas_print_pending_cmds(instance); 7096 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7097 "mrsas_print_pending_cmd done\n")); 7098 7099 instance->func_ptr->enable_intr(instance); 7100 instance->fw_outstanding = 0; 7101 7102 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7103 "Calling mrsas_issue_pending_cmds")); 7104 (void) mrsas_issue_pending_cmds(instance); 7105 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7106 "issue_pending_cmds done.\n")); 7107 7108 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7109 "Calling aen registration")); 7110 7111 7112 instance->aen_cmd->retry_count_for_ocr = 0; 7113 instance->aen_cmd->drv_pkt_time = 0; 7114 7115 instance->func_ptr->issue_cmd(instance->aen_cmd, instance); 7116 con_log(CL_ANN1, (CE_NOTE, "Unsetting adpresetinprogress flag.\n")); 7117 7118 mutex_enter(&instance->ocr_flags_mtx); 7119 instance->adapterresetinprogress = 0; 7120 mutex_exit(&instance->ocr_flags_mtx); 7121 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: " 7122 "adpterresetinprogress flag unset")); 7123 7124 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc done\n")); 7125 return (DDI_SUCCESS); 7126 } 7127 7128 /* 7129 * FMA functions. 7130 */ 7131 int 7132 mrsas_common_check(struct mrsas_instance *instance, struct mrsas_cmd *cmd) 7133 { 7134 int ret = DDI_SUCCESS; 7135 7136 if (cmd != NULL && 7137 mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) != 7138 DDI_SUCCESS) { 7139 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 7140 if (cmd->pkt != NULL) { 7141 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 7142 cmd->pkt->pkt_statistics = 0; 7143 } 7144 ret = DDI_FAILURE; 7145 } 7146 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle) 7147 != DDI_SUCCESS) { 7148 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 7149 if (cmd != NULL && cmd->pkt != NULL) { 7150 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 7151 cmd->pkt->pkt_statistics = 0; 7152 } 7153 ret = DDI_FAILURE; 7154 } 7155 if (mrsas_check_dma_handle(instance->mfi_evt_detail_obj.dma_handle) != 7156 DDI_SUCCESS) { 7157 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 7158 if (cmd != NULL && cmd->pkt != NULL) { 7159 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 7160 cmd->pkt->pkt_statistics = 0; 7161 } 7162 ret = DDI_FAILURE; 7163 } 7164 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) { 7165 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED); 7166 7167 ddi_fm_acc_err_clear(instance->regmap_handle, DDI_FME_VER0); 7168 7169 if (cmd != NULL && cmd->pkt != NULL) { 7170 cmd->pkt->pkt_reason = CMD_TRAN_ERR; 7171 cmd->pkt->pkt_statistics = 0; 7172 } 7173 ret = DDI_FAILURE; 7174 } 7175 7176 return (ret); 7177 } 7178 7179 /*ARGSUSED*/ 7180 static int 7181 mrsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 7182 { 7183 /* 7184 * as the driver can always deal with an error in any dma or 7185 * access handle, we can just return the fme_status value. 7186 */ 7187 pci_ereport_post(dip, err, NULL); 7188 return (err->fme_status); 7189 } 7190 7191 static void 7192 mrsas_fm_init(struct mrsas_instance *instance) 7193 { 7194 /* Need to change iblock to priority for new MSI intr */ 7195 ddi_iblock_cookie_t fm_ibc; 7196 7197 /* Only register with IO Fault Services if we have some capability */ 7198 if (instance->fm_capabilities) { 7199 /* Adjust access and dma attributes for FMA */ 7200 endian_attr.devacc_attr_access = DDI_FLAGERR_ACC; 7201 mrsas_generic_dma_attr.dma_attr_flags = DDI_DMA_FLAGERR; 7202 7203 /* 7204 * Register capabilities with IO Fault Services. 7205 * fm_capabilities will be updated to indicate 7206 * capabilities actually supported (not requested.) 7207 */ 7208 7209 ddi_fm_init(instance->dip, &instance->fm_capabilities, &fm_ibc); 7210 7211 /* 7212 * Initialize pci ereport capabilities if ereport 7213 * capable (should always be.) 7214 */ 7215 7216 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) || 7217 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 7218 pci_ereport_setup(instance->dip); 7219 } 7220 7221 /* 7222 * Register error callback if error callback capable. 7223 */ 7224 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 7225 ddi_fm_handler_register(instance->dip, 7226 mrsas_fm_error_cb, (void*) instance); 7227 } 7228 } else { 7229 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC; 7230 mrsas_generic_dma_attr.dma_attr_flags = 0; 7231 } 7232 } 7233 7234 static void 7235 mrsas_fm_fini(struct mrsas_instance *instance) 7236 { 7237 /* Only unregister FMA capabilities if registered */ 7238 if (instance->fm_capabilities) { 7239 /* 7240 * Un-register error callback if error callback capable. 7241 */ 7242 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 7243 ddi_fm_handler_unregister(instance->dip); 7244 } 7245 7246 /* 7247 * Release any resources allocated by pci_ereport_setup() 7248 */ 7249 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) || 7250 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) { 7251 pci_ereport_teardown(instance->dip); 7252 } 7253 7254 /* Unregister from IO Fault Services */ 7255 ddi_fm_fini(instance->dip); 7256 7257 /* Adjust access and dma attributes for FMA */ 7258 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC; 7259 mrsas_generic_dma_attr.dma_attr_flags = 0; 7260 } 7261 } 7262 7263 int 7264 mrsas_check_acc_handle(ddi_acc_handle_t handle) 7265 { 7266 ddi_fm_error_t de; 7267 7268 if (handle == NULL) { 7269 return (DDI_FAILURE); 7270 } 7271 7272 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 7273 7274 return (de.fme_status); 7275 } 7276 7277 int 7278 mrsas_check_dma_handle(ddi_dma_handle_t handle) 7279 { 7280 ddi_fm_error_t de; 7281 7282 if (handle == NULL) { 7283 return (DDI_FAILURE); 7284 } 7285 7286 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 7287 7288 return (de.fme_status); 7289 } 7290 7291 void 7292 mrsas_fm_ereport(struct mrsas_instance *instance, char *detail) 7293 { 7294 uint64_t ena; 7295 char buf[FM_MAX_CLASS]; 7296 7297 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 7298 ena = fm_ena_generate(0, FM_ENA_FMT1); 7299 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities)) { 7300 ddi_fm_ereport_post(instance->dip, buf, ena, DDI_NOSLEEP, 7301 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERSION, NULL); 7302 } 7303 } 7304 7305 static int 7306 mrsas_add_intrs(struct mrsas_instance *instance, int intr_type) 7307 { 7308 7309 dev_info_t *dip = instance->dip; 7310 int avail, actual, count; 7311 int i, flag, ret; 7312 7313 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_type = %x", 7314 intr_type)); 7315 7316 /* Get number of interrupts */ 7317 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 7318 if ((ret != DDI_SUCCESS) || (count == 0)) { 7319 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_nintrs() failed:" 7320 "ret %d count %d", ret, count)); 7321 7322 return (DDI_FAILURE); 7323 } 7324 7325 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: count = %d ", count)); 7326 7327 /* Get number of available interrupts */ 7328 ret = ddi_intr_get_navail(dip, intr_type, &avail); 7329 if ((ret != DDI_SUCCESS) || (avail == 0)) { 7330 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_navail() failed:" 7331 "ret %d avail %d", ret, avail)); 7332 7333 return (DDI_FAILURE); 7334 } 7335 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: avail = %d ", avail)); 7336 7337 /* Only one interrupt routine. So limit the count to 1 */ 7338 if (count > 1) { 7339 count = 1; 7340 } 7341 7342 /* 7343 * Allocate an array of interrupt handlers. Currently we support 7344 * only one interrupt. The framework can be extended later. 7345 */ 7346 instance->intr_htable_size = count * sizeof (ddi_intr_handle_t); 7347 instance->intr_htable = kmem_zalloc(instance->intr_htable_size, 7348 KM_SLEEP); 7349 ASSERT(instance->intr_htable); 7350 7351 flag = ((intr_type == DDI_INTR_TYPE_MSI) || 7352 (intr_type == DDI_INTR_TYPE_MSIX)) ? 7353 DDI_INTR_ALLOC_STRICT : DDI_INTR_ALLOC_NORMAL; 7354 7355 /* Allocate interrupt */ 7356 ret = ddi_intr_alloc(dip, instance->intr_htable, intr_type, 0, 7357 count, &actual, flag); 7358 7359 if ((ret != DDI_SUCCESS) || (actual == 0)) { 7360 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 7361 "avail = %d", avail)); 7362 goto mrsas_free_htable; 7363 } 7364 7365 if (actual < count) { 7366 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 7367 "Requested = %d Received = %d", count, actual)); 7368 } 7369 instance->intr_cnt = actual; 7370 7371 /* 7372 * Get the priority of the interrupt allocated. 7373 */ 7374 if ((ret = ddi_intr_get_pri(instance->intr_htable[0], 7375 &instance->intr_pri)) != DDI_SUCCESS) { 7376 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 7377 "get priority call failed")); 7378 goto mrsas_free_handles; 7379 } 7380 7381 /* 7382 * Test for high level mutex. we don't support them. 7383 */ 7384 if (instance->intr_pri >= ddi_intr_get_hilevel_pri()) { 7385 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: " 7386 "High level interrupts not supported.")); 7387 goto mrsas_free_handles; 7388 } 7389 7390 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_pri = 0x%x ", 7391 instance->intr_pri)); 7392 7393 /* Call ddi_intr_add_handler() */ 7394 for (i = 0; i < actual; i++) { 7395 ret = ddi_intr_add_handler(instance->intr_htable[i], 7396 (ddi_intr_handler_t *)mrsas_isr, (caddr_t)instance, 7397 (caddr_t)(uintptr_t)i); 7398 7399 if (ret != DDI_SUCCESS) { 7400 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs:" 7401 "failed %d", ret)); 7402 goto mrsas_free_handles; 7403 } 7404 7405 } 7406 7407 con_log(CL_DLEVEL1, (CE_NOTE, " ddi_intr_add_handler done")); 7408 7409 if ((ret = ddi_intr_get_cap(instance->intr_htable[0], 7410 &instance->intr_cap)) != DDI_SUCCESS) { 7411 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_cap() failed %d", 7412 ret)); 7413 goto mrsas_free_handlers; 7414 } 7415 7416 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) { 7417 con_log(CL_ANN, (CE_WARN, "Calling ddi_intr_block _enable")); 7418 7419 (void) ddi_intr_block_enable(instance->intr_htable, 7420 instance->intr_cnt); 7421 } else { 7422 con_log(CL_ANN, (CE_NOTE, " calling ddi_intr_enable")); 7423 7424 for (i = 0; i < instance->intr_cnt; i++) { 7425 (void) ddi_intr_enable(instance->intr_htable[i]); 7426 con_log(CL_ANN, (CE_NOTE, "ddi intr enable returns " 7427 "%d", i)); 7428 } 7429 } 7430 7431 return (DDI_SUCCESS); 7432 7433 mrsas_free_handlers: 7434 for (i = 0; i < actual; i++) 7435 (void) ddi_intr_remove_handler(instance->intr_htable[i]); 7436 7437 mrsas_free_handles: 7438 for (i = 0; i < actual; i++) 7439 (void) ddi_intr_free(instance->intr_htable[i]); 7440 7441 mrsas_free_htable: 7442 if (instance->intr_htable != NULL) 7443 kmem_free(instance->intr_htable, instance->intr_htable_size); 7444 7445 instance->intr_htable = NULL; 7446 instance->intr_htable_size = 0; 7447 7448 return (DDI_FAILURE); 7449 7450 } 7451 7452 7453 static void 7454 mrsas_rem_intrs(struct mrsas_instance *instance) 7455 { 7456 int i; 7457 7458 con_log(CL_ANN, (CE_NOTE, "mrsas_rem_intrs called")); 7459 7460 /* Disable all interrupts first */ 7461 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) { 7462 (void) ddi_intr_block_disable(instance->intr_htable, 7463 instance->intr_cnt); 7464 } else { 7465 for (i = 0; i < instance->intr_cnt; i++) { 7466 (void) ddi_intr_disable(instance->intr_htable[i]); 7467 } 7468 } 7469 7470 /* Remove all the handlers */ 7471 7472 for (i = 0; i < instance->intr_cnt; i++) { 7473 (void) ddi_intr_remove_handler(instance->intr_htable[i]); 7474 (void) ddi_intr_free(instance->intr_htable[i]); 7475 } 7476 7477 if (instance->intr_htable != NULL) 7478 kmem_free(instance->intr_htable, instance->intr_htable_size); 7479 7480 instance->intr_htable = NULL; 7481 instance->intr_htable_size = 0; 7482 7483 } 7484 7485 static int 7486 mrsas_tran_bus_config(dev_info_t *parent, uint_t flags, 7487 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 7488 { 7489 struct mrsas_instance *instance; 7490 int config; 7491 int rval = NDI_SUCCESS; 7492 7493 char *ptr = NULL; 7494 int tgt, lun; 7495 7496 con_log(CL_ANN1, (CE_NOTE, "Bus config called for op = %x", op)); 7497 7498 if ((instance = ddi_get_soft_state(mrsas_state, 7499 ddi_get_instance(parent))) == NULL) { 7500 return (NDI_FAILURE); 7501 } 7502 7503 /* Hold nexus during bus_config */ 7504 ndi_devi_enter(parent, &config); 7505 switch (op) { 7506 case BUS_CONFIG_ONE: { 7507 7508 /* parse wwid/target name out of name given */ 7509 if ((ptr = strchr((char *)arg, '@')) == NULL) { 7510 rval = NDI_FAILURE; 7511 break; 7512 } 7513 ptr++; 7514 7515 if (mrsas_parse_devname(arg, &tgt, &lun) != 0) { 7516 rval = NDI_FAILURE; 7517 break; 7518 } 7519 7520 if (lun == 0) { 7521 rval = mrsas_config_ld(instance, tgt, lun, childp); 7522 #ifdef PDSUPPORT 7523 } else if ((instance->tbolt || instance->skinny) && lun != 0) { 7524 rval = mrsas_tbolt_config_pd(instance, 7525 tgt, lun, childp); 7526 #endif 7527 } else { 7528 rval = NDI_FAILURE; 7529 } 7530 7531 break; 7532 } 7533 case BUS_CONFIG_DRIVER: 7534 case BUS_CONFIG_ALL: { 7535 7536 rval = mrsas_config_all_devices(instance); 7537 7538 rval = NDI_SUCCESS; 7539 break; 7540 } 7541 } 7542 7543 if (rval == NDI_SUCCESS) { 7544 rval = ndi_busop_bus_config(parent, flags, op, arg, childp, 0); 7545 7546 } 7547 ndi_devi_exit(parent, config); 7548 7549 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_bus_config: rval = %x", 7550 rval)); 7551 return (rval); 7552 } 7553 7554 static int 7555 mrsas_config_all_devices(struct mrsas_instance *instance) 7556 { 7557 int rval, tgt; 7558 7559 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) { 7560 (void) mrsas_config_ld(instance, tgt, 0, NULL); 7561 7562 } 7563 7564 #ifdef PDSUPPORT 7565 /* Config PD devices connected to the card */ 7566 if (instance->tbolt || instance->skinny) { 7567 for (tgt = 0; tgt < instance->mr_tbolt_pd_max; tgt++) { 7568 (void) mrsas_tbolt_config_pd(instance, tgt, 1, NULL); 7569 } 7570 } 7571 #endif 7572 7573 rval = NDI_SUCCESS; 7574 return (rval); 7575 } 7576 7577 static int 7578 mrsas_parse_devname(char *devnm, int *tgt, int *lun) 7579 { 7580 char devbuf[SCSI_MAXNAMELEN]; 7581 char *addr; 7582 char *p, *tp, *lp; 7583 long num; 7584 7585 /* Parse dev name and address */ 7586 (void) strcpy(devbuf, devnm); 7587 addr = ""; 7588 for (p = devbuf; *p != '\0'; p++) { 7589 if (*p == '@') { 7590 addr = p + 1; 7591 *p = '\0'; 7592 } else if (*p == ':') { 7593 *p = '\0'; 7594 break; 7595 } 7596 } 7597 7598 /* Parse target and lun */ 7599 for (p = tp = addr, lp = NULL; *p != '\0'; p++) { 7600 if (*p == ',') { 7601 lp = p + 1; 7602 *p = '\0'; 7603 break; 7604 } 7605 } 7606 if (tgt && tp) { 7607 if (ddi_strtol(tp, NULL, 0x10, &num)) { 7608 return (DDI_FAILURE); /* Can declare this as constant */ 7609 } 7610 *tgt = (int)num; 7611 } 7612 if (lun && lp) { 7613 if (ddi_strtol(lp, NULL, 0x10, &num)) { 7614 return (DDI_FAILURE); 7615 } 7616 *lun = (int)num; 7617 } 7618 return (DDI_SUCCESS); /* Success case */ 7619 } 7620 7621 static int 7622 mrsas_config_ld(struct mrsas_instance *instance, uint16_t tgt, 7623 uint8_t lun, dev_info_t **ldip) 7624 { 7625 struct scsi_device *sd; 7626 dev_info_t *child; 7627 int rval; 7628 7629 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: t = %d l = %d", 7630 tgt, lun)); 7631 7632 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) { 7633 if (ldip) { 7634 *ldip = child; 7635 } 7636 if (instance->mr_ld_list[tgt].flag != MRDRV_TGT_VALID) { 7637 rval = mrsas_service_evt(instance, tgt, 0, 7638 MRSAS_EVT_UNCONFIG_TGT, NULL); 7639 con_log(CL_ANN1, (CE_WARN, 7640 "mr_sas: DELETING STALE ENTRY rval = %d " 7641 "tgt id = %d ", rval, tgt)); 7642 return (NDI_FAILURE); 7643 } 7644 return (NDI_SUCCESS); 7645 } 7646 7647 sd = kmem_zalloc(sizeof (struct scsi_device), KM_SLEEP); 7648 sd->sd_address.a_hba_tran = instance->tran; 7649 sd->sd_address.a_target = (uint16_t)tgt; 7650 sd->sd_address.a_lun = (uint8_t)lun; 7651 7652 if (scsi_hba_probe(sd, NULL) == SCSIPROBE_EXISTS) 7653 rval = mrsas_config_scsi_device(instance, sd, ldip); 7654 else 7655 rval = NDI_FAILURE; 7656 7657 /* sd_unprobe is blank now. Free buffer manually */ 7658 if (sd->sd_inq) { 7659 kmem_free(sd->sd_inq, SUN_INQSIZE); 7660 sd->sd_inq = (struct scsi_inquiry *)NULL; 7661 } 7662 7663 kmem_free(sd, sizeof (struct scsi_device)); 7664 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: return rval = %d", 7665 rval)); 7666 return (rval); 7667 } 7668 7669 int 7670 mrsas_config_scsi_device(struct mrsas_instance *instance, 7671 struct scsi_device *sd, dev_info_t **dipp) 7672 { 7673 char *nodename = NULL; 7674 char **compatible = NULL; 7675 int ncompatible = 0; 7676 char *childname; 7677 dev_info_t *ldip = NULL; 7678 int tgt = sd->sd_address.a_target; 7679 int lun = sd->sd_address.a_lun; 7680 int dtype = sd->sd_inq->inq_dtype & DTYPE_MASK; 7681 int rval; 7682 7683 con_log(CL_DLEVEL1, (CE_NOTE, "mr_sas: scsi_device t%dL%d", tgt, lun)); 7684 scsi_hba_nodename_compatible_get(sd->sd_inq, NULL, dtype, 7685 NULL, &nodename, &compatible, &ncompatible); 7686 7687 if (nodename == NULL) { 7688 con_log(CL_ANN1, (CE_WARN, "mr_sas: Found no compatible driver " 7689 "for t%dL%d", tgt, lun)); 7690 rval = NDI_FAILURE; 7691 goto finish; 7692 } 7693 7694 childname = (dtype == DTYPE_DIRECT) ? "sd" : nodename; 7695 con_log(CL_DLEVEL1, (CE_NOTE, 7696 "mr_sas: Childname = %2s nodename = %s", childname, nodename)); 7697 7698 /* Create a dev node */ 7699 rval = ndi_devi_alloc(instance->dip, childname, DEVI_SID_NODEID, &ldip); 7700 con_log(CL_DLEVEL1, (CE_NOTE, 7701 "mr_sas_config_scsi_device: ndi_devi_alloc rval = %x", rval)); 7702 if (rval == NDI_SUCCESS) { 7703 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "target", tgt) != 7704 DDI_PROP_SUCCESS) { 7705 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create " 7706 "property for t%dl%d target", tgt, lun)); 7707 rval = NDI_FAILURE; 7708 goto finish; 7709 } 7710 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "lun", lun) != 7711 DDI_PROP_SUCCESS) { 7712 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create " 7713 "property for t%dl%d lun", tgt, lun)); 7714 rval = NDI_FAILURE; 7715 goto finish; 7716 } 7717 7718 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, ldip, 7719 "compatible", compatible, ncompatible) != 7720 DDI_PROP_SUCCESS) { 7721 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create " 7722 "property for t%dl%d compatible", tgt, lun)); 7723 rval = NDI_FAILURE; 7724 goto finish; 7725 } 7726 7727 rval = ndi_devi_online(ldip, NDI_ONLINE_ATTACH); 7728 if (rval != NDI_SUCCESS) { 7729 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to online " 7730 "t%dl%d", tgt, lun)); 7731 ndi_prop_remove_all(ldip); 7732 (void) ndi_devi_free(ldip); 7733 } else { 7734 con_log(CL_ANN1, (CE_CONT, "mr_sas: online Done :" 7735 "0 t%dl%d", tgt, lun)); 7736 } 7737 7738 } 7739 finish: 7740 if (dipp) { 7741 *dipp = ldip; 7742 } 7743 7744 con_log(CL_DLEVEL1, (CE_NOTE, 7745 "mr_sas: config_scsi_device rval = %d t%dL%d", 7746 rval, tgt, lun)); 7747 scsi_hba_nodename_compatible_free(nodename, compatible); 7748 return (rval); 7749 } 7750 7751 /*ARGSUSED*/ 7752 int 7753 mrsas_service_evt(struct mrsas_instance *instance, int tgt, int lun, int event, 7754 uint64_t wwn) 7755 { 7756 struct mrsas_eventinfo *mrevt = NULL; 7757 7758 con_log(CL_ANN1, (CE_NOTE, 7759 "mrsas_service_evt called for t%dl%d event = %d", 7760 tgt, lun, event)); 7761 7762 if ((instance->taskq == NULL) || (mrevt = 7763 kmem_zalloc(sizeof (struct mrsas_eventinfo), KM_NOSLEEP)) == NULL) { 7764 return (ENOMEM); 7765 } 7766 7767 mrevt->instance = instance; 7768 mrevt->tgt = tgt; 7769 mrevt->lun = lun; 7770 mrevt->event = event; 7771 mrevt->wwn = wwn; 7772 7773 if ((ddi_taskq_dispatch(instance->taskq, 7774 (void (*)(void *))mrsas_issue_evt_taskq, mrevt, DDI_NOSLEEP)) != 7775 DDI_SUCCESS) { 7776 con_log(CL_ANN1, (CE_NOTE, 7777 "mr_sas: Event task failed for t%dl%d event = %d", 7778 tgt, lun, event)); 7779 kmem_free(mrevt, sizeof (struct mrsas_eventinfo)); 7780 return (DDI_FAILURE); 7781 } 7782 DTRACE_PROBE3(service_evt, int, tgt, int, lun, int, event); 7783 return (DDI_SUCCESS); 7784 } 7785 7786 static void 7787 mrsas_issue_evt_taskq(struct mrsas_eventinfo *mrevt) 7788 { 7789 struct mrsas_instance *instance = mrevt->instance; 7790 dev_info_t *dip, *pdip; 7791 int circ1 = 0; 7792 char *devname; 7793 7794 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_evt_taskq: called for" 7795 " tgt %d lun %d event %d", 7796 mrevt->tgt, mrevt->lun, mrevt->event)); 7797 7798 if (mrevt->tgt < MRDRV_MAX_LD && mrevt->lun == 0) { 7799 mutex_enter(&instance->config_dev_mtx); 7800 dip = instance->mr_ld_list[mrevt->tgt].dip; 7801 mutex_exit(&instance->config_dev_mtx); 7802 #ifdef PDSUPPORT 7803 } else { 7804 mutex_enter(&instance->config_dev_mtx); 7805 dip = instance->mr_tbolt_pd_list[mrevt->tgt].dip; 7806 mutex_exit(&instance->config_dev_mtx); 7807 #endif 7808 } 7809 7810 7811 ndi_devi_enter(instance->dip, &circ1); 7812 switch (mrevt->event) { 7813 case MRSAS_EVT_CONFIG_TGT: 7814 if (dip == NULL) { 7815 7816 if (mrevt->lun == 0) { 7817 (void) mrsas_config_ld(instance, mrevt->tgt, 7818 0, NULL); 7819 #ifdef PDSUPPORT 7820 } else if (instance->tbolt || instance->skinny) { 7821 (void) mrsas_tbolt_config_pd(instance, 7822 mrevt->tgt, 7823 1, NULL); 7824 #endif 7825 } 7826 con_log(CL_ANN1, (CE_NOTE, 7827 "mr_sas: EVT_CONFIG_TGT called:" 7828 " for tgt %d lun %d event %d", 7829 mrevt->tgt, mrevt->lun, mrevt->event)); 7830 7831 } else { 7832 con_log(CL_ANN1, (CE_NOTE, 7833 "mr_sas: EVT_CONFIG_TGT dip != NULL:" 7834 " for tgt %d lun %d event %d", 7835 mrevt->tgt, mrevt->lun, mrevt->event)); 7836 } 7837 break; 7838 case MRSAS_EVT_UNCONFIG_TGT: 7839 if (dip) { 7840 if (i_ddi_devi_attached(dip)) { 7841 7842 pdip = ddi_get_parent(dip); 7843 7844 devname = kmem_zalloc(MAXNAMELEN + 1, KM_SLEEP); 7845 (void) ddi_deviname(dip, devname); 7846 7847 (void) devfs_clean(pdip, devname + 1, 7848 DV_CLEAN_FORCE); 7849 kmem_free(devname, MAXNAMELEN + 1); 7850 } 7851 (void) ndi_devi_offline(dip, NDI_DEVI_REMOVE); 7852 con_log(CL_ANN1, (CE_NOTE, 7853 "mr_sas: EVT_UNCONFIG_TGT called:" 7854 " for tgt %d lun %d event %d", 7855 mrevt->tgt, mrevt->lun, mrevt->event)); 7856 } else { 7857 con_log(CL_ANN1, (CE_NOTE, 7858 "mr_sas: EVT_UNCONFIG_TGT dip == NULL:" 7859 " for tgt %d lun %d event %d", 7860 mrevt->tgt, mrevt->lun, mrevt->event)); 7861 } 7862 break; 7863 } 7864 kmem_free(mrevt, sizeof (struct mrsas_eventinfo)); 7865 ndi_devi_exit(instance->dip, circ1); 7866 } 7867 7868 7869 int 7870 mrsas_mode_sense_build(struct scsi_pkt *pkt) 7871 { 7872 union scsi_cdb *cdbp; 7873 uint16_t page_code; 7874 struct scsa_cmd *acmd; 7875 struct buf *bp; 7876 struct mode_header *modehdrp; 7877 7878 cdbp = (void *)pkt->pkt_cdbp; 7879 page_code = cdbp->cdb_un.sg.scsi[0]; 7880 acmd = PKT2CMD(pkt); 7881 bp = acmd->cmd_buf; 7882 if ((!bp) && bp->b_un.b_addr && bp->b_bcount && acmd->cmd_dmacount) { 7883 con_log(CL_ANN1, (CE_WARN, "Failing MODESENSE Command")); 7884 /* ADD pkt statistics as Command failed. */ 7885 return (NULL); 7886 } 7887 7888 bp_mapin(bp); 7889 bzero(bp->b_un.b_addr, bp->b_bcount); 7890 7891 switch (page_code) { 7892 case 0x3: { 7893 struct mode_format *page3p = NULL; 7894 modehdrp = (struct mode_header *)(bp->b_un.b_addr); 7895 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH; 7896 7897 page3p = (void *)((caddr_t)modehdrp + 7898 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH); 7899 page3p->mode_page.code = 0x3; 7900 page3p->mode_page.length = 7901 (uchar_t)(sizeof (struct mode_format)); 7902 page3p->data_bytes_sect = 512; 7903 page3p->sect_track = 63; 7904 break; 7905 } 7906 case 0x4: { 7907 struct mode_geometry *page4p = NULL; 7908 modehdrp = (struct mode_header *)(bp->b_un.b_addr); 7909 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH; 7910 7911 page4p = (void *)((caddr_t)modehdrp + 7912 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH); 7913 page4p->mode_page.code = 0x4; 7914 page4p->mode_page.length = 7915 (uchar_t)(sizeof (struct mode_geometry)); 7916 page4p->heads = 255; 7917 page4p->rpm = 10000; 7918 break; 7919 } 7920 default: 7921 break; 7922 } 7923 return (NULL); 7924 } 7925