1 /* 2 * fusion.h 3 * 4 * Solaris MegaRAID device driver for SAS2.0 controllers 5 * Copyright (c) 2008-2012, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Version: 9 * Author: 10 * Swaminathan K S 11 * Arun Chandrashekhar 12 * Manju R 13 * Rasheed 14 * Shakeel Bukhari 15 */ 16 17 18 #ifndef _FUSION_H_ 19 #define _FUSION_H_ 20 21 #define U64 uint64_t 22 #define U32 uint32_t 23 #define U16 uint16_t 24 #define U8 uint8_t 25 #define S8 char 26 #define S16 short 27 #define S32 int 28 29 /* MPI2 defines */ 30 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x6C) 31 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 32 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 33 #define MPI2_VERSION_MAJOR (0x02) 34 #define MPI2_VERSION_MINOR (0x00) 35 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 36 #define MPI2_VERSION_MAJOR_SHIFT (8) 37 #define MPI2_VERSION_MINOR_MASK (0x00FF) 38 #define MPI2_VERSION_MINOR_SHIFT (0) 39 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 40 MPI2_VERSION_MINOR) 41 #define MPI2_HEADER_VERSION_UNIT (0x10) 42 #define MPI2_HEADER_VERSION_DEV (0x00) 43 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 44 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 45 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 46 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 47 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT \ 48 << 8) | \ 49 MPI2_HEADER_VERSION_DEV) 50 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 51 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 52 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 53 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 54 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 55 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 56 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 57 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 58 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 59 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 60 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 61 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 62 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 63 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 64 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 65 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 66 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 67 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 68 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 69 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 70 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 71 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 72 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 73 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 74 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 75 76 /* Invader defines */ 77 #define MPI2_TYPE_CUDA 0x2 78 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 79 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 80 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 81 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 82 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 83 #define MPI2_NSEG_FLAGS_SHIFT 4 84 85 86 #define MR_PD_INVALID 0xFFFF 87 #define MAX_SPAN_DEPTH 8 88 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 89 #define MAX_ROW_SIZE 32 90 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 91 #define MAX_LOGICAL_DRIVES 64 92 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 93 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 94 #define MAX_ARRAYS 128 95 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 96 #define MAX_PHYSICAL_DEVICES 256 97 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 98 99 /* get the mapping information of LD */ 100 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 101 102 #ifndef MPI2_POINTER 103 #define MPI2_POINTER * 104 #endif 105 106 #pragma pack(1) 107 108 typedef struct _MPI25_IEEE_SGE_CHAIN64 109 { 110 U64 Address; 111 U32 Length; 112 U16 Reserved1; 113 U8 NextChainOffset; 114 U8 Flags; 115 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 116 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 117 118 typedef struct _MPI2_SGE_SIMPLE_UNION 119 { 120 U32 FlagsLength; 121 union 122 { 123 U32 Address32; 124 U64 Address64; 125 } u1; 126 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 127 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 128 129 typedef struct 130 { 131 U8 CDB[20]; /* 0x00 */ 132 U32 PrimaryReferenceTag; /* 0x14 */ 133 U16 PrimaryApplicationTag; /* 0x18 */ 134 U16 PrimaryApplicationTagMask; /* 0x1A */ 135 U32 TransferLength; /* 0x1C */ 136 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 137 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 138 139 typedef struct _MPI2_SGE_CHAIN_UNION 140 { 141 U16 Length; 142 U8 NextChainOffset; 143 U8 Flags; 144 union 145 { 146 U32 Address32; 147 U64 Address64; 148 } u1; 149 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 150 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 151 152 typedef struct _MPI2_IEEE_SGE_SIMPLE32 153 { 154 U32 Address; 155 U32 FlagsLength; 156 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 157 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 158 159 typedef struct _MPI2_IEEE_SGE_SIMPLE64 160 { 161 U64 Address; 162 U32 Length; 163 U16 Reserved1; 164 U8 Reserved2; 165 U8 Flags; 166 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 167 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 168 169 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 170 { 171 MPI2_IEEE_SGE_SIMPLE32 Simple32; 172 MPI2_IEEE_SGE_SIMPLE64 Simple64; 173 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 174 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 175 176 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 177 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 178 179 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 180 { 181 MPI2_IEEE_SGE_CHAIN32 Chain32; 182 MPI2_IEEE_SGE_CHAIN64 Chain64; 183 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 184 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 185 186 typedef union _MPI2_SGE_IO_UNION 187 { 188 MPI2_SGE_SIMPLE_UNION MpiSimple; 189 MPI2_SGE_CHAIN_UNION MpiChain; 190 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 191 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 192 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 193 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 194 195 typedef union 196 { 197 U8 CDB32[32]; 198 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 199 MPI2_SGE_SIMPLE_UNION SGE; 200 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 201 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 202 203 /* Default Request Descriptor */ 204 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 205 { 206 U8 RequestFlags; /* 0x00 */ 207 U8 MSIxIndex; /* 0x01 */ 208 U16 SMID; /* 0x02 */ 209 U16 LMID; /* 0x04 */ 210 U16 DescriptorTypeDependent; /* 0x06 */ 211 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 212 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 213 Mpi2DefaultRequestDescriptor_t, 214 MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 215 216 /* High Priority Request Descriptor */ 217 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 218 { 219 U8 RequestFlags; /* 0x00 */ 220 U8 MSIxIndex; /* 0x01 */ 221 U16 SMID; /* 0x02 */ 222 U16 LMID; /* 0x04 */ 223 U16 Reserved1; /* 0x06 */ 224 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 225 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 226 Mpi2HighPriorityRequestDescriptor_t, 227 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 228 229 /* SCSI IO Request Descriptor */ 230 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 231 { 232 U8 RequestFlags; /* 0x00 */ 233 U8 MSIxIndex; /* 0x01 */ 234 U16 SMID; /* 0x02 */ 235 U16 LMID; /* 0x04 */ 236 U16 DevHandle; /* 0x06 */ 237 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 238 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 239 Mpi2SCSIIORequestDescriptor_t, 240 MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 241 242 /* SCSI Target Request Descriptor */ 243 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 244 { 245 U8 RequestFlags; /* 0x00 */ 246 U8 MSIxIndex; /* 0x01 */ 247 U16 SMID; /* 0x02 */ 248 U16 LMID; /* 0x04 */ 249 U16 IoIndex; /* 0x06 */ 250 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 251 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 252 Mpi2SCSITargetRequestDescriptor_t, 253 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 254 255 /* RAID Accelerator Request Descriptor */ 256 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 257 { 258 U8 RequestFlags; /* 0x00 */ 259 U8 MSIxIndex; /* 0x01 */ 260 U16 SMID; /* 0x02 */ 261 U16 LMID; /* 0x04 */ 262 U16 Reserved; /* 0x06 */ 263 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 264 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 265 Mpi2RAIDAcceleratorRequestDescriptor_t, 266 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 267 268 /* Default Reply Descriptor */ 269 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 270 { 271 U8 ReplyFlags; /* 0x00 */ 272 U8 MSIxIndex; /* 0x01 */ 273 U16 DescriptorTypeDependent1; /* 0x02 */ 274 U32 DescriptorTypeDependent2; /* 0x04 */ 275 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 276 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 277 278 /* Address Reply Descriptor */ 279 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 280 { 281 U8 ReplyFlags; /* 0x00 */ 282 U8 MSIxIndex; /* 0x01 */ 283 U16 SMID; /* 0x02 */ 284 U32 ReplyFrameAddress; /* 0x04 */ 285 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 286 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 287 288 /* SCSI IO Success Reply Descriptor */ 289 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 290 { 291 U8 ReplyFlags; /* 0x00 */ 292 U8 MSIxIndex; /* 0x01 */ 293 U16 SMID; /* 0x02 */ 294 U16 TaskTag; /* 0x04 */ 295 U16 Reserved1; /* 0x06 */ 296 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 297 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 298 Mpi2SCSIIOSuccessReplyDescriptor_t, 299 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 300 301 /* TargetAssist Success Reply Descriptor */ 302 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 303 { 304 U8 ReplyFlags; /* 0x00 */ 305 U8 MSIxIndex; /* 0x01 */ 306 U16 SMID; /* 0x02 */ 307 U8 SequenceNumber; /* 0x04 */ 308 U8 Reserved1; /* 0x05 */ 309 U16 IoIndex; /* 0x06 */ 310 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 311 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 312 Mpi2TargetAssistSuccessReplyDescriptor_t, 313 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 314 315 /* Target Command Buffer Reply Descriptor */ 316 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 317 { 318 U8 ReplyFlags; /* 0x00 */ 319 U8 MSIxIndex; /* 0x01 */ 320 U8 VP_ID; /* 0x02 */ 321 U8 Flags; /* 0x03 */ 322 U16 InitiatorDevHandle; /* 0x04 */ 323 U16 IoIndex; /* 0x06 */ 324 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 325 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 326 Mpi2TargetCommandBufferReplyDescriptor_t, 327 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 328 329 /* RAID Accelerator Success Reply Descriptor */ 330 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 331 { 332 U8 ReplyFlags; /* 0x00 */ 333 U8 MSIxIndex; /* 0x01 */ 334 U16 SMID; /* 0x02 */ 335 U32 Reserved; /* 0x04 */ 336 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 337 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 338 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 339 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 340 341 /* union of Reply Descriptors */ 342 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 343 { 344 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 345 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 346 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 347 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 348 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 349 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 350 U64 Words; 351 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 352 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 353 354 /* IOCInit Request message */ 355 typedef struct _MPI2_IOC_INIT_REQUEST 356 { 357 U8 WhoInit; /* 0x00 */ 358 U8 Reserved1; /* 0x01 */ 359 U8 ChainOffset; /* 0x02 */ 360 U8 Function; /* 0x03 */ 361 U16 Reserved2; /* 0x04 */ 362 U8 Reserved3; /* 0x06 */ 363 U8 MsgFlags; /* 0x07 */ 364 U8 VP_ID; /* 0x08 */ 365 U8 VF_ID; /* 0x09 */ 366 U16 Reserved4; /* 0x0A */ 367 U16 MsgVersion; /* 0x0C */ 368 U16 HeaderVersion; /* 0x0E */ 369 U32 Reserved5; /* 0x10 */ 370 U16 Reserved6; /* 0x14 */ 371 U8 Reserved7; /* 0x16 */ 372 U8 HostMSIxVectors; /* 0x17 */ 373 U16 Reserved8; /* 0x18 */ 374 U16 SystemRequestFrameSize; /* 0x1A */ 375 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 376 U16 ReplyFreeQueueDepth; /* 0x1E */ 377 U32 SenseBufferAddressHigh; /* 0x20 */ 378 U32 SystemReplyAddressHigh; /* 0x24 */ 379 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 380 U64 ReplyDescriptorPostQueueAddress; /* 0x30 */ 381 U64 ReplyFreeQueueAddress; /* 0x38 */ 382 U64 TimeStamp; /* 0x40 */ 383 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 384 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 385 386 387 typedef struct _MR_DEV_HANDLE_INFO { 388 389 /* Send bitmap of LDs that are idle with respect to FP */ 390 U16 curDevHdl; 391 392 /* bitmap of valid device handles. */ 393 U8 validHandles; 394 U8 reserved; 395 /* 0x04 dev handles for all the paths. */ 396 U16 devHandle[2]; 397 } MR_DEV_HANDLE_INFO; /* 0x08, Total Size */ 398 399 typedef struct _MR_ARRAY_INFO { 400 U16 pd[MAX_RAIDMAP_ROW_SIZE]; 401 } MR_ARRAY_INFO; /* 0x40, Total Size */ 402 403 typedef struct _MR_QUAD_ELEMENT { 404 U64 logStart; /* 0x00 */ 405 U64 logEnd; /* 0x08 */ 406 U64 offsetInSpan; /* 0x10 */ 407 U32 diff; /* 0x18 */ 408 U32 reserved1; /* 0x1C */ 409 } MR_QUAD_ELEMENT; /* 0x20, Total size */ 410 411 typedef struct _MR_SPAN_INFO { 412 U32 noElements; /* 0x00 */ 413 U32 reserved1; /* 0x04 */ 414 MR_QUAD_ELEMENT quads[MAX_RAIDMAP_SPAN_DEPTH]; /* 0x08 */ 415 } MR_SPAN_INFO; /* 0x108, Total size */ 416 417 typedef struct _MR_LD_SPAN_ { /* SPAN structure */ 418 /* 0x00, starting block number in array */ 419 U64 startBlk; 420 421 /* 0x08, number of blocks */ 422 U64 numBlks; 423 424 /* 0x10, array reference */ 425 U16 arrayRef; 426 427 U8 reserved[6]; /* 0x12 */ 428 } MR_LD_SPAN; /* 0x18, Total Size */ 429 430 typedef struct _MR_SPAN_BLOCK_INFO { 431 /* number of rows/span */ 432 U64 num_rows; 433 434 MR_LD_SPAN span; /* 0x08 */ 435 MR_SPAN_INFO block_span_info; /* 0x20 */ 436 } MR_SPAN_BLOCK_INFO; /* 0x128, Total Size */ 437 438 typedef struct _MR_LD_RAID { 439 struct { 440 U32 fpCapable :1; 441 U32 reserved5 :3; 442 U32 ldPiMode :4; 443 U32 pdPiMode :4; 444 445 /* FDE or controller encryption (MR_LD_ENCRYPTION_TYPE) */ 446 U32 encryptionType :8; 447 448 U32 fpWriteCapable :1; 449 U32 fpReadCapable :1; 450 U32 fpWriteAcrossStripe:1; 451 U32 fpReadAcrossStripe:1; 452 U32 reserved4 :8; 453 } capability; /* 0x00 */ 454 U32 reserved6; 455 U64 size; /* 0x08, LD size in blocks */ 456 U8 spanDepth; /* 0x10, Total Number of Spans */ 457 U8 level; /* 0x11, RAID level */ 458 /* 0x12, shift-count to get stripe size (0=512, 1=1K, 7=64K, etc.) */ 459 U8 stripeShift; 460 U8 rowSize; /* 0x13, number of disks in a row */ 461 /* 0x14, number of data disks in a row */ 462 U8 rowDataSize; 463 U8 writeMode; /* 0x15, WRITE_THROUGH or WRITE_BACK */ 464 465 /* 0x16, To differentiate between RAID1 and RAID1E */ 466 U8 PRL; 467 468 U8 SRL; /* 0x17 */ 469 U16 targetId; /* 0x18, ld Target Id. */ 470 471 /* 0x1a, state of ld, state corresponds to MR_LD_STATE */ 472 U8 ldState; 473 474 /* 0x1b, Pre calculate region type requests based on MFC etc.. */ 475 U8 regTypeReqOnWrite; 476 477 U8 modFactor; /* 0x1c, same as rowSize */ 478 /* 479 * 0x1d, region lock type used for read, valid only if 480 * regTypeOnReadIsValid=1 481 */ 482 U8 regTypeReqOnRead; 483 U16 seqNum; /* 0x1e, LD sequence number */ 484 485 struct { 486 /* This LD requires sync command before completing */ 487 U32 ldSyncRequired:1; 488 U32 reserved:31; 489 } flags; /* 0x20 */ 490 491 U8 reserved3[0x5C]; /* 0x24 */ 492 } MR_LD_RAID; /* 0x80, Total Size */ 493 494 typedef struct _MR_LD_SPAN_MAP { 495 MR_LD_RAID ldRaid; /* 0x00 */ 496 497 /* 0x80, needed for GET_ARM() - R0/1/5 only. */ 498 U8 dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 499 500 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; /* 0xA0 */ 501 } MR_LD_SPAN_MAP; /* 0x9E0 */ 502 503 typedef struct _MR_FW_RAID_MAP { 504 /* total size of this structure, including this field */ 505 U32 totalSize; 506 union { 507 /* Simple method of version checking variables */ 508 struct { 509 U32 maxLd; 510 U32 maxSpanDepth; 511 U32 maxRowSize; 512 U32 maxPdCount; 513 U32 maxArrays; 514 } validationInfo; 515 U32 version[5]; 516 U32 reserved1[5]; 517 } u1; 518 519 U32 ldCount; /* count of lds */ 520 U32 Reserved1; 521 522 /* 523 * 0x20 This doesn't correspond to 524 * FW Ld Tgt Id to LD, but will purge. For example: if tgt Id is 4 525 * and FW LD is 2, and there is only one LD, FW will populate the 526 * array like this. [0xFF, 0xFF, 0xFF, 0xFF, 0x0.....]. This is to 527 * help reduce the entire structure size if there are few LDs or 528 * driver is looking info for 1 LD only. 529 */ 530 U8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ \ 531 MAX_RAIDMAP_VIEWS]; /* 0x20 */ 532 /* timeout value used by driver in FP IOs */ 533 U8 fpPdIoTimeoutSec; 534 U8 reserved2[7]; 535 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; /* 0x00a8 */ 536 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 537 538 /* 0x28a8-[0 -MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS+1]; */ 539 MR_LD_SPAN_MAP ldSpanMap[1]; 540 }MR_FW_RAID_MAP; /* 0x3288, Total Size */ 541 542 typedef struct _LD_TARGET_SYNC { 543 U8 ldTargetId; 544 U8 reserved; 545 U16 seqNum; 546 } LD_TARGET_SYNC; 547 548 #pragma pack() 549 550 struct IO_REQUEST_INFO { 551 U64 ldStartBlock; 552 U32 numBlocks; 553 U16 ldTgtId; 554 U8 isRead; 555 U16 devHandle; 556 U64 pdBlock; 557 U8 fpOkForIo; 558 U8 ldPI; 559 }; 560 561 #endif /* _FUSION_H_ */ 562