1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2020, The University of Queensland 14 * Copyright (c) 2018, Joyent, Inc. 15 * Copyright 2020 RackTop Systems, Inc. 16 */ 17 18 #ifndef _MLXCX_REG_H 19 #define _MLXCX_REG_H 20 21 #include <sys/types.h> 22 #include <sys/byteorder.h> 23 24 #include <mlxcx_endint.h> 25 26 #if !defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) 27 #error "Need _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH" 28 #endif 29 30 /* 31 * Register offsets. 32 */ 33 34 #define MLXCX_ISS_FIRMWARE 0x0000 35 #define MLXCX_ISS_FW_MAJOR(x) (((x) & 0xffff)) 36 #define MLXCX_ISS_FW_MINOR(x) (((x) >> 16) & 0xffff) 37 #define MLXCX_ISS_FW_CMD 0x0004 38 #define MLXCX_ISS_FW_REV(x) (((x) & 0xffff)) 39 #define MLXCX_ISS_CMD_REV(x) (((x) >> 16) & 0xffff) 40 #define MLXCX_ISS_CMD_HIGH 0x0010 41 #define MLXCX_ISS_CMD_LOW 0x0014 42 #define MLXCX_ISS_CMDQ_SIZE(x) (((x) >> 4) & 0xf) 43 #define MLXCX_ISS_CMDQ_STRIDE(x) ((x) & 0xf) 44 45 #define MLXCX_ISS_CMD_DOORBELL 0x0018 46 #define MLXCX_ISS_INIT 0x01fc 47 #define MLXCX_ISS_INITIALIZING(x) (((x) >> 31) & 0x1) 48 #define MLXCX_ISS_HEALTH_BUF 0x0200 49 #define MLXCX_ISS_NO_DRAM_NIC 0x0240 50 #define MLXCX_ISS_TIMER 0x1000 51 #define MLXCX_ISS_HEALTH_COUNT 0x1010 52 #define MLXCX_ISS_HEALTH_SYND 0x1013 53 54 #define MLXCX_CMD_INLINE_INPUT_LEN 16 55 #define MLXCX_CMD_INLINE_OUTPUT_LEN 16 56 57 #define MLXCX_CMD_MAILBOX_LEN 512 58 59 #define MLXCX_CMD_TRANSPORT_PCI 7 60 #define MLXCX_CMD_HW_OWNED 0x01 61 #define MLXCX_CMD_STATUS(x) ((x) >> 1) 62 63 #define MLXCX_UAR_CQ_ARM 0x0020 64 #define MLXCX_UAR_EQ_ARM 0x0040 65 #define MLXCX_UAR_EQ_NOARM 0x0048 66 67 /* Number of blue flame reg pairs per UAR */ 68 #define MLXCX_BF_PER_UAR 2 69 #define MLXCX_BF_PER_UAR_MASK 0x1 70 #define MLXCX_BF_SIZE 0x100 71 #define MLXCX_BF_BASE 0x0800 72 73 /* CSTYLED */ 74 #define MLXCX_EQ_ARM_EQN (bitdef_t){24, 0xff000000} 75 /* CSTYLED */ 76 #define MLXCX_EQ_ARM_CI (bitdef_t){0, 0x00ffffff} 77 78 /* 79 * Hardware structure that is used to represent a command. 80 */ 81 #pragma pack(1) 82 typedef struct { 83 uint8_t mce_type; 84 uint8_t mce_rsvd[3]; 85 uint32be_t mce_in_length; 86 uint64be_t mce_in_mbox; 87 uint8_t mce_input[MLXCX_CMD_INLINE_INPUT_LEN]; 88 uint8_t mce_output[MLXCX_CMD_INLINE_OUTPUT_LEN]; 89 uint64be_t mce_out_mbox; 90 uint32be_t mce_out_length; 91 uint8_t mce_token; 92 uint8_t mce_sig; 93 uint8_t mce_rsvd1; 94 uint8_t mce_status; 95 } mlxcx_cmd_ent_t; 96 97 typedef struct { 98 uint8_t mlxb_data[MLXCX_CMD_MAILBOX_LEN]; 99 uint8_t mlxb_rsvd[48]; 100 uint64be_t mlxb_nextp; 101 uint32be_t mlxb_blockno; 102 uint8_t mlxb_rsvd1; 103 uint8_t mlxb_token; 104 uint8_t mlxb_ctrl_sig; 105 uint8_t mlxb_sig; 106 } mlxcx_cmd_mailbox_t; 107 108 typedef struct { 109 uint8_t mled_page_request_rsvd[2]; 110 uint16be_t mled_page_request_function_id; 111 uint32be_t mled_page_request_num_pages; 112 } mlxcx_evdata_page_request_t; 113 114 /* CSTYLED */ 115 #define MLXCX_EVENT_PORT_NUM (bitdef_t){ .bit_shift = 4, .bit_mask = 0xF0 } 116 117 typedef struct { 118 uint8_t mled_port_state_rsvd[8]; 119 bits8_t mled_port_state_port_num; 120 } mlxcx_evdata_port_state_t; 121 122 typedef enum { 123 MLXCX_MODULE_INITIALIZING = 0x0, 124 MLXCX_MODULE_PLUGGED = 0x1, 125 MLXCX_MODULE_UNPLUGGED = 0x2, 126 MLXCX_MODULE_ERROR = 0x3 127 } mlxcx_module_status_t; 128 129 typedef enum { 130 MLXCX_MODULE_ERR_POWER_BUDGET = 0x0, 131 MLXCX_MODULE_ERR_LONG_RANGE = 0x1, 132 MLXCX_MODULE_ERR_BUS_STUCK = 0x2, 133 MLXCX_MODULE_ERR_NO_EEPROM = 0x3, 134 MLXCX_MODULE_ERR_ENFORCEMENT = 0x4, 135 MLXCX_MODULE_ERR_UNKNOWN_IDENT = 0x5, 136 MLXCX_MODULE_ERR_HIGH_TEMP = 0x6, 137 MLXCX_MODULE_ERR_CABLE_SHORTED = 0x7, 138 } mlxcx_module_error_type_t; 139 140 typedef struct { 141 uint8_t mled_port_mod_rsvd; 142 uint8_t mled_port_mod_module; 143 uint8_t mled_port_mod_rsvd2; 144 uint8_t mled_port_mod_module_status; 145 uint8_t mled_port_mod_rsvd3[2]; 146 uint8_t mled_port_mod_error_type; 147 uint8_t mled_port_mod_rsvd4; 148 } mlxcx_evdata_port_mod_t; 149 150 typedef struct { 151 uint8_t mled_completion_rsvd[25]; 152 uint24be_t mled_completion_cqn; 153 } mlxcx_evdata_completion_t; 154 155 typedef enum { 156 MLXCX_EV_QUEUE_TYPE_QP = 0x0, 157 MLXCX_EV_QUEUE_TYPE_RQ = 0x1, 158 MLXCX_EV_QUEUE_TYPE_SQ = 0x2, 159 } mlxcx_evdata_queue_type_t; 160 161 typedef struct { 162 uint8_t mled_queue_rsvd[20]; 163 uint8_t mled_queue_type; 164 uint8_t mled_queue_rsvd2[4]; 165 uint24be_t mled_queue_num; 166 } mlxcx_evdata_queue_t; 167 168 #define MLXCX_EQ_OWNER_INIT 1 169 170 typedef struct { 171 uint8_t mleqe_rsvd[1]; 172 uint8_t mleqe_event_type; 173 uint8_t mleqe_rsvd2[1]; 174 uint8_t mleqe_event_sub_type; 175 uint8_t mleqe_rsvd3[28]; 176 union { 177 uint8_t mleqe_unknown_data[28]; 178 mlxcx_evdata_completion_t mleqe_completion; 179 mlxcx_evdata_page_request_t mleqe_page_request; 180 mlxcx_evdata_port_state_t mleqe_port_state; 181 mlxcx_evdata_port_mod_t mleqe_port_mod; 182 mlxcx_evdata_queue_t mleqe_queue; 183 }; 184 uint8_t mleqe_rsvd4[2]; 185 uint8_t mleqe_signature; 186 uint8_t mleqe_owner; 187 } mlxcx_eventq_ent_t; 188 189 typedef enum { 190 MLXCX_CQE_L3_HDR_NONE = 0x0, 191 MLXCX_CQE_L3_HDR_RCV_BUF = 0x1, 192 MLXCX_CQE_L3_HDR_CQE = 0x2, 193 } mlxcx_cqe_l3_hdr_placement_t; 194 195 typedef enum { 196 MLXCX_CQE_CSFLAGS_L4_OK = 1 << 2, 197 MLXCX_CQE_CSFLAGS_L3_OK = 1 << 1, 198 MLXCX_CQE_CSFLAGS_L2_OK = 1 << 0, 199 } mlxcx_cqe_csflags_t; 200 201 typedef enum { 202 MLXCX_CQE_L4_TYPE_NONE = 0, 203 MLXCX_CQE_L4_TYPE_TCP = 1, 204 MLXCX_CQE_L4_TYPE_UDP = 2, 205 MLXCX_CQE_L4_TYPE_TCP_EMPTY_ACK = 3, 206 MLXCX_CQE_L4_TYPE_TCP_ACK = 4, 207 } mlxcx_cqe_l4_hdr_type_t; 208 209 typedef enum { 210 MLXCX_CQE_L3_TYPE_NONE = 0, 211 MLXCX_CQE_L3_TYPE_IPv6 = 1, 212 MLXCX_CQE_L3_TYPE_IPv4 = 2, 213 } mlxcx_cqe_l3_hdr_type_t; 214 215 typedef enum { 216 MLXCX_CQE_RX_HASH_NONE = 0, 217 MLXCX_CQE_RX_HASH_IPv4 = 1, 218 MLXCX_CQE_RX_HASH_IPv6 = 2, 219 MLXCX_CQE_RX_HASH_IPSEC_SPI = 3, 220 } mlxcx_cqe_rx_hash_type_t; 221 /* BEGIN CSTYLED */ 222 #define MLXCX_CQE_RX_HASH_IP_SRC (bitdef_t){0, 0x3} 223 #define MLXCX_CQE_RX_HASH_IP_DEST (bitdef_t){2, (0x3 << 2)} 224 #define MLXCX_CQE_RX_HASH_L4_SRC (bitdef_t){4, (0x3 << 4)} 225 #define MLXCX_CQE_RX_HASH_L4_DEST (bitdef_t){6, (0x3 << 6)} 226 /* END CSTYLED */ 227 228 typedef enum { 229 MLXCX_CQE_OP_REQ = 0x0, 230 MLXCX_CQE_OP_RESP_RDMA = 0x1, 231 MLXCX_CQE_OP_RESP = 0x2, 232 MLXCX_CQE_OP_RESP_IMMEDIATE = 0x3, 233 MLXCX_CQE_OP_RESP_INVALIDATE = 0x4, 234 MLXCX_CQE_OP_RESIZE_CQ = 0x5, 235 MLXCX_CQE_OP_SIG_ERR = 0x12, 236 MLXCX_CQE_OP_REQ_ERR = 0xd, 237 MLXCX_CQE_OP_RESP_ERR = 0xe, 238 MLXCX_CQE_OP_INVALID = 0xf 239 } mlxcx_cqe_opcode_t; 240 241 typedef enum { 242 MLXCX_CQE_FORMAT_BASIC = 0, 243 MLXCX_CQE_FORMAT_INLINE_32 = 1, 244 MLXCX_CQE_FORMAT_INLINE_64 = 2, 245 MLXCX_CQE_FORMAT_COMPRESSED = 3, 246 } mlxcx_cqe_format_t; 247 248 typedef enum { 249 MLXCX_CQE_OWNER_INIT = 1 250 } mlxcx_cqe_owner_t; 251 252 typedef enum { 253 MLXCX_VLAN_TYPE_NONE, 254 MLXCX_VLAN_TYPE_CVLAN, 255 MLXCX_VLAN_TYPE_SVLAN, 256 } mlxcx_vlan_type_t; 257 258 typedef enum { 259 MLXCX_CQ_ERR_LOCAL_LENGTH = 0x1, 260 MLXCX_CQ_ERR_LOCAL_QP_OP = 0x2, 261 MLXCX_CQ_ERR_LOCAL_PROTECTION = 0x4, 262 MLXCX_CQ_ERR_WR_FLUSHED = 0x5, 263 MLXCX_CQ_ERR_MEM_WINDOW_BIND = 0x6, 264 MLXCX_CQ_ERR_BAD_RESPONSE = 0x10, 265 MLXCX_CQ_ERR_LOCAL_ACCESS = 0x11, 266 MLXCX_CQ_ERR_XPORT_RETRY_CTR = 0x15, 267 MLXCX_CQ_ERR_RNR_RETRY_CTR = 0x16, 268 MLXCX_CQ_ERR_ABORTED = 0x22 269 } mlxcx_cq_error_syndrome_t; 270 271 typedef struct { 272 uint8_t mlcqee_rsvd[2]; 273 uint16be_t mlcqee_wqe_id; 274 uint8_t mlcqee_rsvd2[29]; 275 uint24be_t mlcqee_user_index; 276 uint8_t mlcqee_rsvd3[8]; 277 uint32be_t mlcqee_byte_cnt; 278 uint8_t mlcqee_rsvd4[6]; 279 uint8_t mlcqee_vendor_error_syndrome; 280 uint8_t mlcqee_syndrome; 281 uint8_t mlcqee_wqe_opcode; 282 uint24be_t mlcqee_flow_tag; 283 uint16be_t mlcqee_wqe_counter; 284 uint8_t mlcqee_signature; 285 struct { 286 #if defined(_BIT_FIELDS_HTOL) 287 uint8_t mlcqe_opcode:4; 288 uint8_t mlcqe_rsvd5:3; 289 uint8_t mlcqe_owner:1; 290 #elif defined(_BIT_FIELDS_LTOH) 291 uint8_t mlcqe_owner:1; 292 uint8_t mlcqe_rsvd5:3; 293 uint8_t mlcqe_opcode:4; 294 #endif 295 }; 296 } mlxcx_completionq_error_ent_t; 297 298 typedef struct { 299 uint8_t mlcqe_tunnel_flags; 300 uint8_t mlcqe_rsvd[3]; 301 uint8_t mlcqe_lro_flags; 302 uint8_t mlcqe_lro_min_ttl; 303 uint16be_t mlcqe_lro_tcp_win; 304 uint32be_t mlcqe_lro_ack_seq_num; 305 uint32be_t mlcqe_rx_hash_result; 306 bits8_t mlcqe_rx_hash_type; 307 uint8_t mlcqe_ml_path; 308 uint8_t mlcqe_rsvd2[2]; 309 uint16be_t mlcqe_checksum; 310 uint16be_t mlcqe_slid_smac_lo; 311 struct { 312 #if defined(_BIT_FIELDS_HTOL) 313 uint8_t mlcqe_rsvd3:1; 314 uint8_t mlcqe_force_loopback:1; 315 uint8_t mlcqe_l3_hdr:2; 316 uint8_t mlcqe_sl_roce_pktype:4; 317 #elif defined(_BIT_FIELDS_LTOH) 318 uint8_t mlcqe_sl_roce_pktype:4; 319 uint8_t mlcqe_l3_hdr:2; 320 uint8_t mlcqe_force_loopback:1; 321 uint8_t mlcqe_rsvd3:1; 322 #endif 323 }; 324 uint24be_t mlcqe_rqpn; 325 bits8_t mlcqe_csflags; 326 struct { 327 #if defined(_BIT_FIELDS_HTOL) 328 uint8_t mlcqe_ip_frag:1; 329 uint8_t mlcqe_l4_hdr_type:3; 330 uint8_t mlcqe_l3_hdr_type:2; 331 uint8_t mlcqe_ip_ext_opts:1; 332 uint8_t mlcqe_cv:1; 333 #elif defined(_BIT_FIELDS_LTOH) 334 uint8_t mlcqe_cv:1; 335 uint8_t mlcqe_ip_ext_opts:1; 336 uint8_t mlcqe_l3_hdr_type:2; 337 uint8_t mlcqe_l4_hdr_type:3; 338 uint8_t mlcqe_ip_frag:1; 339 #endif 340 }; 341 uint16be_t mlcqe_up_cfi_vid; 342 uint8_t mlcqe_lro_num_seg; 343 uint24be_t mlcqe_user_index; 344 uint32be_t mlcqe_immediate; 345 uint8_t mlcqe_rsvd4[4]; 346 uint32be_t mlcqe_byte_cnt; 347 union { 348 struct { 349 uint32be_t mlcqe_lro_timestamp_value; 350 uint32be_t mlcqe_lro_timestamp_echo; 351 }; 352 uint64be_t mlcqe_timestamp; 353 }; 354 union { 355 uint8_t mlcqe_rx_drop_counter; 356 uint8_t mlcqe_send_wqe_opcode; 357 }; 358 uint24be_t mlcqe_flow_tag; 359 uint16be_t mlcqe_wqe_counter; 360 uint8_t mlcqe_signature; 361 struct { 362 #if defined(_BIT_FIELDS_HTOL) 363 uint8_t mlcqe_opcode:4; 364 uint8_t mlcqe_format:2; 365 uint8_t mlcqe_se:1; 366 uint8_t mlcqe_owner:1; 367 #elif defined(_BIT_FIELDS_LTOH) 368 uint8_t mlcqe_owner:1; 369 uint8_t mlcqe_se:1; 370 uint8_t mlcqe_format:2; 371 uint8_t mlcqe_opcode:4; 372 #endif 373 }; 374 } mlxcx_completionq_ent_t; 375 376 typedef struct { 377 uint8_t mlcqe_data[64]; 378 mlxcx_completionq_ent_t mlcqe_ent; 379 } mlxcx_completionq_ent128_t; 380 381 typedef enum { 382 MLXCX_WQE_OP_NOP = 0x00, 383 MLXCX_WQE_OP_SEND_INVALIDATE = 0x01, 384 MLXCX_WQE_OP_RDMA_W = 0x08, 385 MLXCX_WQE_OP_RDMA_W_IMMEDIATE = 0x09, 386 MLXCX_WQE_OP_SEND = 0x0A, 387 MLXCX_WQE_OP_SEND_IMMEDIATE = 0x0B, 388 MLXCX_WQE_OP_LSO = 0x0E, 389 MLXCX_WQE_OP_WAIT = 0x0F, 390 MLXCX_WQE_OP_RDMA_R = 0x10, 391 } mlxcx_wqe_opcode_t; 392 393 #define MLXCX_SQE_MAX_DS ((1 << 6) - 1) 394 #define MLXCX_SQE_MAX_PTRS 61 395 396 typedef enum { 397 MLXCX_SQE_FENCE_NONE = 0x0, 398 MLXCX_SQE_FENCE_WAIT_OTHERS = 0x1, 399 MLXCX_SQE_FENCE_START = 0x2, 400 MLXCX_SQE_FENCE_STRONG_ORDER = 0x3, 401 MLXCX_SQE_FENCE_START_WAIT = 0x4 402 } mlxcx_sqe_fence_mode_t; 403 404 typedef enum { 405 MLXCX_SQE_CQE_ON_EACH_ERROR = 0x0, 406 MLXCX_SQE_CQE_ON_FIRST_ERROR = 0x1, 407 MLXCX_SQE_CQE_ALWAYS = 0x2, 408 MLXCX_SQE_CQE_ALWAYS_PLUS_EQE = 0x3 409 } mlxcx_sqe_completion_mode_t; 410 411 #define MLXCX_SQE_SOLICITED (1 << 1) 412 /* CSTYLED */ 413 #define MLXCX_SQE_FENCE_MODE (bitdef_t){5, 0xe0} 414 /* CSTYLED */ 415 #define MLXCX_SQE_COMPLETION_MODE (bitdef_t){2, 0x0c} 416 417 typedef struct { 418 uint8_t mlcs_opcode_mod; 419 uint16be_t mlcs_wqe_index; 420 uint8_t mlcs_opcode; 421 uint24be_t mlcs_qp_or_sq; 422 uint8_t mlcs_ds; 423 uint8_t mlcs_signature; 424 uint8_t mlcs_rsvd2[2]; 425 bits8_t mlcs_flags; 426 uint32be_t mlcs_immediate; 427 } mlxcx_wqe_control_seg_t; 428 429 typedef enum { 430 MLXCX_SQE_ETH_CSFLAG_L4_CHECKSUM = 1 << 7, 431 MLXCX_SQE_ETH_CSFLAG_L3_CHECKSUM = 1 << 6, 432 MLXCX_SQE_ETH_CSFLAG_L4_INNER_CHECKSUM = 1 << 5, 433 MLXCX_SQE_ETH_CSFLAG_L3_INNER_CHECKSUM = 1 << 4, 434 } mlxcx_wqe_eth_flags_t; 435 436 /* CSTYLED */ 437 #define MLXCX_SQE_ETH_INLINE_HDR_SZ (bitdef_t){0, 0x03ff} 438 #define MLXCX_SQE_ETH_SZFLAG_VLAN (1 << 15) 439 #define MLXCX_MAX_INLINE_HEADERLEN 64 440 441 typedef struct { 442 uint8_t mles_rsvd[4]; 443 bits8_t mles_csflags; 444 uint8_t mles_rsvd2[1]; 445 uint16_t mles_mss; 446 uint8_t mles_rsvd3[4]; 447 bits16_t mles_szflags; 448 uint8_t mles_inline_headers[18]; 449 } mlxcx_wqe_eth_seg_t; 450 451 typedef struct { 452 uint32be_t mlds_byte_count; 453 uint32be_t mlds_lkey; 454 uint64be_t mlds_address; 455 } mlxcx_wqe_data_seg_t; 456 457 #define MLXCX_SENDQ_STRIDE_SHIFT 6 458 459 typedef struct { 460 mlxcx_wqe_control_seg_t mlsqe_control; 461 mlxcx_wqe_eth_seg_t mlsqe_eth; 462 mlxcx_wqe_data_seg_t mlsqe_data[1]; 463 } mlxcx_sendq_ent_t; 464 465 typedef struct { 466 uint64be_t mlsqbf_qwords[8]; 467 } mlxcx_sendq_bf_t; 468 469 typedef struct { 470 mlxcx_wqe_data_seg_t mlsqe_data[4]; 471 } mlxcx_sendq_extra_ent_t; 472 473 #define MLXCX_RECVQ_STRIDE_SHIFT 7 474 /* 475 * Each mlxcx_wqe_data_seg_t is 1<<4 bytes long (there's a CTASSERT to verify 476 * this in mlxcx_cmd.c), so the number of pointers is 1 << (shift - 4). 477 */ 478 #define MLXCX_RECVQ_MAX_PTRS (1 << (MLXCX_RECVQ_STRIDE_SHIFT - 4)) 479 typedef struct { 480 mlxcx_wqe_data_seg_t mlrqe_data[MLXCX_RECVQ_MAX_PTRS]; 481 } mlxcx_recvq_ent_t; 482 483 /* CSTYLED */ 484 #define MLXCX_CQ_ARM_CI (bitdef_t){ .bit_shift = 0, \ 485 .bit_mask = 0x00ffffff } 486 /* CSTYLED */ 487 #define MLXCX_CQ_ARM_SEQ (bitdef_t){ .bit_shift = 28, \ 488 .bit_mask = 0x30000000 } 489 #define MLXCX_CQ_ARM_SOLICITED (1 << 24) 490 491 typedef struct { 492 uint8_t mlcqd_rsvd; 493 uint24be_t mlcqd_update_ci; 494 bits32_t mlcqd_arm_ci; 495 } mlxcx_completionq_doorbell_t; 496 497 typedef struct { 498 uint16be_t mlwqd_rsvd; 499 uint16be_t mlwqd_recv_counter; 500 uint16be_t mlwqd_rsvd2; 501 uint16be_t mlwqd_send_counter; 502 } mlxcx_workq_doorbell_t; 503 504 #define MLXCX_EQ_STATUS_OK (0x0 << 4) 505 #define MLXCX_EQ_STATUS_WRITE_FAILURE (0xA << 4) 506 507 #define MLXCX_EQ_OI (1 << 1) 508 #define MLXCX_EQ_EC (1 << 2) 509 510 #define MLXCX_EQ_ST_ARMED 0x9 511 #define MLXCX_EQ_ST_FIRED 0xA 512 513 /* CSTYLED */ 514 #define MLXCX_EQ_LOG_PAGE_SIZE (bitdef_t){ .bit_shift = 24, \ 515 .bit_mask = 0x1F000000 } 516 517 typedef struct { 518 uint8_t mleqc_status; 519 uint8_t mleqc_ecoi; 520 uint8_t mleqc_state; 521 uint8_t mleqc_rsvd[7]; 522 uint16be_t mleqc_page_offset; 523 uint8_t mleqc_log_eq_size; 524 uint24be_t mleqc_uar_page; 525 uint8_t mleqc_rsvd3[7]; 526 uint8_t mleqc_intr; 527 uint32be_t mleqc_log_page; 528 uint8_t mleqc_rsvd4[13]; 529 uint24be_t mleqc_consumer_counter; 530 uint8_t mleqc_rsvd5; 531 uint24be_t mleqc_producer_counter; 532 uint8_t mleqc_rsvd6[16]; 533 } mlxcx_eventq_ctx_t; 534 535 typedef enum { 536 MLXCX_CQC_CQE_SIZE_64 = 0x0, 537 MLXCX_CQC_CQE_SIZE_128 = 0x1, 538 } mlxcx_cqc_cqe_sz_t; 539 540 typedef enum { 541 MLXCX_CQC_STATUS_OK = 0x0, 542 MLXCX_CQC_STATUS_OVERFLOW = 0x9, 543 MLXCX_CQC_STATUS_WRITE_FAIL = 0xA, 544 MLXCX_CQC_STATUS_INVALID = 0xF 545 } mlxcx_cqc_status_t; 546 547 typedef enum { 548 MLXCX_CQC_STATE_ARMED_SOLICITED = 0x6, 549 MLXCX_CQC_STATE_ARMED = 0x9, 550 MLXCX_CQC_STATE_FIRED = 0xA 551 } mlxcx_cqc_state_t; 552 553 /* CSTYLED */ 554 #define MLXCX_CQ_CTX_STATUS (bitdef_t){28, 0xf0000000} 555 /* CSTYLED */ 556 #define MLXCX_CQ_CTX_CQE_SZ (bitdef_t){21, 0x00e00000} 557 /* CSTYLED */ 558 #define MLXCX_CQ_CTX_PERIOD_MODE (bitdef_t){15, 0x00018000} 559 /* CSTYLED */ 560 #define MLXCX_CQ_CTX_MINI_CQE_FORMAT (bitdef_t){12, 0x00003000} 561 /* CSTYLED */ 562 #define MLXCX_CQ_CTX_STATE (bitdef_t){8, 0x00000f00} 563 564 typedef struct mlxcx_completionq_ctx { 565 bits32_t mlcqc_flags; 566 567 uint8_t mlcqc_rsvd4[4]; 568 569 uint8_t mlcqc_rsvd5[2]; 570 uint16be_t mlcqc_page_offset; 571 572 uint8_t mlcqc_log_cq_size; 573 uint24be_t mlcqc_uar_page; 574 575 uint16be_t mlcqc_cq_period; 576 uint16be_t mlcqc_cq_max_count; 577 578 uint8_t mlcqc_rsvd7[3]; 579 uint8_t mlcqc_eqn; 580 581 uint8_t mlcqc_log_page_size; 582 uint8_t mlcqc_rsvd8[3]; 583 584 uint8_t mlcqc_rsvd9[4]; 585 586 uint8_t mlcqc_rsvd10; 587 uint24be_t mlcqc_last_notified_index; 588 uint8_t mlcqc_rsvd11; 589 uint24be_t mlcqc_last_solicit_index; 590 uint8_t mlcqc_rsvd12; 591 uint24be_t mlcqc_consumer_counter; 592 uint8_t mlcqc_rsvd13; 593 uint24be_t mlcqc_producer_counter; 594 595 uint8_t mlcqc_rsvd14[8]; 596 597 uint64be_t mlcqc_dbr_addr; 598 } mlxcx_completionq_ctx_t; 599 600 typedef enum { 601 MLXCX_WORKQ_TYPE_LINKED_LIST = 0x0, 602 MLXCX_WORKQ_TYPE_CYCLIC = 0x1, 603 MLXCX_WORKQ_TYPE_LINKED_LIST_STRIDING = 0x2, 604 MLXCX_WORKQ_TYPE_CYCLIC_STRIDING = 0x3 605 } mlxcx_workq_ctx_type_t; 606 607 typedef enum { 608 MLXCX_WORKQ_END_PAD_NONE = 0x0, 609 MLXCX_WORKQ_END_PAD_ALIGN = 0x1 610 } mlxcx_workq_end_padding_t; 611 612 /* CSTYLED */ 613 #define MLXCX_WORKQ_CTX_TYPE (bitdef_t){ \ 614 .bit_shift = 28, \ 615 .bit_mask = 0xf0000000 } 616 #define MLXCX_WORKQ_CTX_SIGNATURE (1 << 27) 617 #define MLXCX_WORKQ_CTX_CD_SLAVE (1 << 24) 618 /* CSTYLED */ 619 #define MLXCX_WORKQ_CTX_END_PADDING (bitdef_t){ \ 620 .bit_shift = 25, \ 621 .bit_mask = 0x06000000 } 622 623 #define MLXCX_WORKQ_CTX_MAX_ADDRESSES 128 624 625 typedef struct mlxcx_workq_ctx { 626 bits32_t mlwqc_flags; 627 uint8_t mlwqc_rsvd[2]; 628 uint16be_t mlwqc_lwm; 629 uint8_t mlwqc_rsvd2; 630 uint24be_t mlwqc_pd; 631 uint8_t mlwqc_rsvd3; 632 uint24be_t mlwqc_uar_page; 633 uint64be_t mlwqc_dbr_addr; 634 uint32be_t mlwqc_hw_counter; 635 uint32be_t mlwqc_sw_counter; 636 uint8_t mlwqc_rsvd4; 637 uint8_t mlwqc_log_wq_stride; 638 uint8_t mlwqc_log_wq_pg_sz; 639 uint8_t mlwqc_log_wq_sz; 640 uint8_t mlwqc_rsvd5[2]; 641 bits16_t mlwqc_strides; 642 uint8_t mlwqc_rsvd6[152]; 643 uint64be_t mlwqc_pas[MLXCX_WORKQ_CTX_MAX_ADDRESSES]; 644 } mlxcx_workq_ctx_t; 645 646 #define MLXCX_RQ_FLAGS_RLKEY (1UL << 31) 647 #define MLXCX_RQ_FLAGS_SCATTER_FCS (1 << 29) 648 #define MLXCX_RQ_FLAGS_VLAN_STRIP_DISABLE (1 << 28) 649 #define MLXCX_RQ_FLAGS_FLUSH_IN_ERROR (1 << 18) 650 /* CSTYLED */ 651 #define MLXCX_RQ_MEM_RQ_TYPE (bitdef_t){ \ 652 .bit_shift = 24, \ 653 .bit_mask = 0x0f000000 } 654 /* CSTYLED */ 655 #define MLXCX_RQ_STATE (bitdef_t){ \ 656 .bit_shift = 20, \ 657 .bit_mask = 0x00f00000 } 658 659 typedef struct mlxcx_rq_ctx { 660 bits32_t mlrqc_flags; 661 uint8_t mlrqc_rsvd; 662 uint24be_t mlrqc_user_index; 663 uint8_t mlrqc_rsvd2; 664 uint24be_t mlrqc_cqn; 665 uint8_t mlrqc_counter_set_id; 666 uint8_t mlrqc_rsvd3[4]; 667 uint24be_t mlrqc_rmpn; 668 uint8_t mlrqc_rsvd4[28]; 669 mlxcx_workq_ctx_t mlrqc_wq; 670 } mlxcx_rq_ctx_t; 671 672 #define MLXCX_SQ_FLAGS_RLKEY (1UL << 31) 673 #define MLXCX_SQ_FLAGS_CD_MASTER (1 << 30) 674 #define MLXCX_SQ_FLAGS_FRE (1 << 29) 675 #define MLXCX_SQ_FLAGS_FLUSH_IN_ERROR (1 << 28) 676 #define MLXCX_SQ_FLAGS_ALLOW_MULTI_PKT (1 << 27) 677 #define MLXCX_SQ_FLAGS_REG_UMR (1 << 19) 678 679 typedef enum { 680 MLXCX_ETH_CAP_INLINE_REQUIRE_L2 = 0, 681 MLXCX_ETH_CAP_INLINE_VPORT_CTX = 1, 682 MLXCX_ETH_CAP_INLINE_NOT_REQUIRED = 2 683 } mlxcx_eth_cap_inline_mode_t; 684 685 typedef enum { 686 MLXCX_ETH_INLINE_NONE = 0, 687 MLXCX_ETH_INLINE_L2 = 1, 688 MLXCX_ETH_INLINE_L3 = 2, 689 MLXCX_ETH_INLINE_L4 = 3, 690 MLXCX_ETH_INLINE_INNER_L2 = 5, 691 MLXCX_ETH_INLINE_INNER_L3 = 6, 692 MLXCX_ETH_INLINE_INNER_L4 = 7 693 } mlxcx_eth_inline_mode_t; 694 695 /* CSTYLED */ 696 #define MLXCX_SQ_MIN_WQE_INLINE (bitdef_t){ \ 697 .bit_shift = 24, \ 698 .bit_mask = 0x07000000 } 699 /* CSTYLED */ 700 #define MLXCX_SQ_STATE (bitdef_t){ \ 701 .bit_shift = 20, \ 702 .bit_mask = 0x00f00000 } 703 704 typedef struct mlxcx_sq_ctx { 705 bits32_t mlsqc_flags; 706 uint8_t mlsqc_rsvd; 707 uint24be_t mlsqc_user_index; 708 uint8_t mlsqc_rsvd2; 709 uint24be_t mlsqc_cqn; 710 uint8_t mlsqc_rsvd3[18]; 711 uint16be_t mlsqc_packet_pacing_rate_limit_index; 712 uint16be_t mlsqc_tis_lst_sz; 713 uint8_t mlsqc_rsvd4[11]; 714 uint24be_t mlsqc_tis_num; 715 mlxcx_workq_ctx_t mlsqc_wq; 716 } mlxcx_sq_ctx_t; 717 718 #define MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES 64 719 720 typedef enum { 721 MLXCX_VPORT_PROMISC_UCAST = 1 << 15, 722 MLXCX_VPORT_PROMISC_MCAST = 1 << 14, 723 MLXCX_VPORT_PROMISC_ALL = 1 << 13 724 } mlxcx_nic_vport_ctx_promisc_t; 725 726 #define MLXCX_VPORT_LIST_TYPE_MASK 0x07 727 #define MLXCX_VPORT_LIST_TYPE_SHIFT 0 728 729 /* CSTYLED */ 730 #define MLXCX_VPORT_CTX_MIN_WQE_INLINE (bitdef_t){56, 0x0700000000000000} 731 732 typedef struct { 733 bits64_t mlnvc_flags; 734 uint8_t mlnvc_rsvd[28]; 735 uint8_t mlnvc_rsvd2[2]; 736 uint16be_t mlnvc_mtu; 737 uint64be_t mlnvc_system_image_guid; 738 uint64be_t mlnvc_port_guid; 739 uint64be_t mlnvc_node_guid; 740 uint8_t mlnvc_rsvd3[40]; 741 uint16be_t mlnvc_qkey_violation_counter; 742 uint8_t mlnvc_rsvd4[2]; 743 uint8_t mlnvc_rsvd5[132]; 744 bits16_t mlnvc_promisc_list_type; 745 uint16be_t mlnvc_allowed_list_size; 746 uint8_t mlnvc_rsvd6[2]; 747 uint8_t mlnvc_permanent_address[6]; 748 uint8_t mlnvc_rsvd7[4]; 749 uint64be_t mlnvc_address[MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES]; 750 } mlxcx_nic_vport_ctx_t; 751 752 typedef struct { 753 uint8_t mlftc_flags; 754 uint8_t mlftc_level; 755 uint8_t mlftc_rsvd; 756 uint8_t mlftc_log_size; 757 uint8_t mlftc_rsvd2; 758 uint24be_t mlftc_table_miss_id; 759 uint8_t mlftc_rsvd3[4]; 760 uint8_t mlftc_rsvd4[28]; 761 } mlxcx_flow_table_ctx_t; 762 763 /* CSTYLED */ 764 #define MLXCX_FLOW_HDR_FIRST_VID (bitdef_t){0, 0x07ff} 765 /* CSTYLED */ 766 #define MLXCX_FLOW_HDR_FIRST_PRIO (bitdef_t){13,0x7000} 767 #define MLXCX_FLOW_HDR_FIRST_CFI (1 << 12) 768 769 #define MLXCX_FLOW_HDR_IP_DSCP_SHIFT 18 770 #define MLXCX_FLOW_HDR_IP_DSCP_MASK 0xfc0000 771 #define MLXCX_FLOW_HDR_IP_ECN_SHIFT 16 772 #define MLXCX_FLOW_HDR_IP_ECN_MASK 0x030000 773 #define MLXCX_FLOW_HDR_CVLAN_TAG (1 << 15) 774 #define MLXCX_FLOW_HDR_SVLAN_TAG (1 << 14) 775 #define MLXCX_FLOW_HDR_FRAG (1 << 13) 776 /* CSTYLED */ 777 #define MLXCX_FLOW_HDR_IP_VERSION (bitdef_t){ \ 778 .bit_shift = 9, \ 779 .bit_mask = 0x001e00 } 780 /* CSTYLED */ 781 #define MLXCX_FLOW_HDR_TCP_FLAGS (bitdef_t){ \ 782 .bit_shift = 0, \ 783 .bit_mask = 0x0001ff } 784 785 typedef struct { 786 uint8_t mlfh_smac[6]; 787 uint16be_t mlfh_ethertype; 788 uint8_t mlfh_dmac[6]; 789 bits16_t mlfh_first_vid_flags; 790 uint8_t mlfh_ip_protocol; 791 bits24_t mlfh_tcp_ip_flags; 792 uint16be_t mlfh_tcp_sport; 793 uint16be_t mlfh_tcp_dport; 794 uint8_t mlfh_rsvd[3]; 795 uint8_t mlfh_ip_ttl_hoplimit; 796 uint16be_t mlfh_udp_sport; 797 uint16be_t mlfh_udp_dport; 798 uint8_t mlfh_src_ip[16]; 799 uint8_t mlfh_dst_ip[16]; 800 } mlxcx_flow_header_match_t; 801 802 typedef struct { 803 uint8_t mlfp_rsvd; 804 uint24be_t mlfp_source_sqn; 805 uint8_t mlfp_rsvd2[2]; 806 uint16be_t mlfp_source_port; 807 bits16_t mlfp_outer_second_vid_flags; 808 bits16_t mlfp_inner_second_vid_flags; 809 bits16_t mlfp_vlan_flags; 810 uint16be_t mlfp_gre_protocol; 811 uint32be_t mlfp_gre_key; 812 uint24be_t mlfp_vxlan_vni; 813 uint8_t mlfp_rsvd3; 814 uint8_t mlfp_rsvd4[4]; 815 uint8_t mlfp_rsvd5; 816 uint24be_t mlfp_outer_ipv6_flow_label; 817 uint8_t mlfp_rsvd6; 818 uint24be_t mlfp_inner_ipv6_flow_label; 819 uint8_t mlfp_rsvd7[28]; 820 } mlxcx_flow_params_match_t; 821 822 typedef struct { 823 mlxcx_flow_header_match_t mlfm_outer_headers; 824 mlxcx_flow_params_match_t mlfm_misc_parameters; 825 mlxcx_flow_header_match_t mlfm_inner_headers; 826 uint8_t mlfm_rsvd[320]; 827 } mlxcx_flow_match_t; 828 829 #define MLXCX_FLOW_MAX_DESTINATIONS 64 830 typedef enum { 831 MLXCX_FLOW_DEST_VPORT = 0x0, 832 MLXCX_FLOW_DEST_FLOW_TABLE = 0x1, 833 MLXCX_FLOW_DEST_TIR = 0x2, 834 MLXCX_FLOW_DEST_QP = 0x3 835 } mlxcx_flow_destination_type_t; 836 837 typedef struct { 838 uint8_t mlfd_destination_type; 839 uint24be_t mlfd_destination_id; 840 uint8_t mlfd_rsvd[4]; 841 } mlxcx_flow_dest_t; 842 843 typedef enum { 844 MLXCX_FLOW_ACTION_ALLOW = 1 << 0, 845 MLXCX_FLOW_ACTION_DROP = 1 << 1, 846 MLXCX_FLOW_ACTION_FORWARD = 1 << 2, 847 MLXCX_FLOW_ACTION_COUNT = 1 << 3, 848 MLXCX_FLOW_ACTION_ENCAP = 1 << 4, 849 MLXCX_FLOW_ACTION_DECAP = 1 << 5 850 } mlxcx_flow_action_t; 851 852 typedef struct { 853 uint8_t mlfec_rsvd[4]; 854 uint32be_t mlfec_group_id; 855 uint8_t mlfec_rsvd2; 856 uint24be_t mlfec_flow_tag; 857 uint8_t mlfec_rsvd3[2]; 858 uint16be_t mlfec_action; 859 uint8_t mlfec_rsvd4; 860 uint24be_t mlfec_destination_list_size; 861 uint8_t mlfec_rsvd5; 862 uint24be_t mlfec_flow_counter_list_size; 863 uint32be_t mlfec_encap_id; 864 uint8_t mlfec_rsvd6[36]; 865 mlxcx_flow_match_t mlfec_match_value; 866 uint8_t mlfec_rsvd7[192]; 867 mlxcx_flow_dest_t mlfec_destination[MLXCX_FLOW_MAX_DESTINATIONS]; 868 } mlxcx_flow_entry_ctx_t; 869 870 /* CSTYLED */ 871 #define MLXCX_TIR_CTX_DISP_TYPE (bitdef_t){ 4, 0xf0 } 872 typedef enum { 873 MLXCX_TIR_DIRECT = 0x0, 874 MLXCX_TIR_INDIRECT = 0x1, 875 } mlxcx_tir_type_t; 876 877 /* CSTYLED */ 878 #define MLXCX_TIR_LRO_TIMEOUT (bitdef_t){ 12, 0x0ffff000 } 879 /* CSTYLED */ 880 #define MLXCX_TIR_LRO_ENABLE_MASK (bitdef_t){ 8, 0x00000f00 } 881 /* CSTYLED */ 882 #define MLXCX_TIR_LRO_MAX_MSG_SZ (bitdef_t){ 0, 0x000000ff } 883 884 /* CSTYLED */ 885 #define MLXCX_TIR_RX_HASH_FN (bitdef_t){ 4, 0xf0 } 886 typedef enum { 887 MLXCX_TIR_HASH_NONE = 0x0, 888 MLXCX_TIR_HASH_XOR8 = 0x1, 889 MLXCX_TIR_HASH_TOEPLITZ = 0x2 890 } mlxcx_tir_hash_fn_t; 891 #define MLXCX_TIR_LB_UNICAST (1 << 24) 892 #define MLXCX_TIR_LB_MULTICAST (1 << 25) 893 894 /* CSTYLED */ 895 #define MLXCX_RX_HASH_L3_TYPE (bitdef_t){ 31, 0x80000000 } 896 typedef enum { 897 MLXCX_RX_HASH_L3_IPv4 = 0, 898 MLXCX_RX_HASH_L3_IPv6 = 1 899 } mlxcx_tir_rx_hash_l3_type_t; 900 /* CSTYLED */ 901 #define MLXCX_RX_HASH_L4_TYPE (bitdef_t){ 30, 0x40000000 } 902 typedef enum { 903 MLXCX_RX_HASH_L4_TCP = 0, 904 MLXCX_RX_HASH_L4_UDP = 1 905 } mlxcx_tir_rx_hash_l4_type_t; 906 /* CSTYLED */ 907 #define MLXCX_RX_HASH_FIELDS (bitdef_t){ 0, 0x3fffffff } 908 typedef enum { 909 MLXCX_RX_HASH_SRC_IP = 1 << 0, 910 MLXCX_RX_HASH_DST_IP = 1 << 1, 911 MLXCX_RX_HASH_L4_SPORT = 1 << 2, 912 MLXCX_RX_HASH_L4_DPORT = 1 << 3, 913 MLXCX_RX_HASH_IPSEC_SPI = 1 << 4 914 } mlxcx_tir_rx_hash_fields_t; 915 916 typedef struct { 917 uint8_t mltirc_rsvd[4]; 918 bits8_t mltirc_disp_type; 919 uint8_t mltirc_rsvd2[11]; 920 bits32_t mltirc_lro; 921 uint8_t mltirc_rsvd3[9]; 922 uint24be_t mltirc_inline_rqn; 923 bits8_t mltirc_flags; 924 uint24be_t mltirc_indirect_table; 925 bits8_t mltirc_hash_lb; 926 uint24be_t mltirc_transport_domain; 927 uint8_t mltirc_rx_hash_toeplitz_key[40]; 928 bits32_t mltirc_rx_hash_fields_outer; 929 bits32_t mltirc_rx_hash_fields_inner; 930 uint8_t mltirc_rsvd4[152]; 931 } mlxcx_tir_ctx_t; 932 933 typedef struct { 934 uint8_t mltisc_rsvd; 935 uint8_t mltisc_prio_or_sl; 936 uint8_t mltisc_rsvd2[35]; 937 uint24be_t mltisc_transport_domain; 938 uint8_t mltisc_rsvd3[120]; 939 } mlxcx_tis_ctx_t; 940 941 #define MLXCX_RQT_MAX_RQ_REFS 64 942 943 typedef struct { 944 uint8_t mlrqtr_rsvd; 945 uint24be_t mlrqtr_rqn; 946 } mlxcx_rqtable_rq_ref_t; 947 948 typedef struct { 949 uint8_t mlrqtc_rsvd[22]; 950 uint16be_t mlrqtc_max_size; 951 uint8_t mlrqtc_rsvd2[2]; 952 uint16be_t mlrqtc_actual_size; 953 uint8_t mlrqtc_rsvd3[212]; 954 mlxcx_rqtable_rq_ref_t mlrqtc_rqref[MLXCX_RQT_MAX_RQ_REFS]; 955 } mlxcx_rqtable_ctx_t; 956 957 #pragma pack() 958 959 typedef enum { 960 MLXCX_EVENT_COMPLETION = 0x00, 961 MLXCX_EVENT_PATH_MIGRATED = 0x01, 962 MLXCX_EVENT_COMM_ESTABLISH = 0x02, 963 MLXCX_EVENT_SENDQ_DRAIN = 0x03, 964 MLXCX_EVENT_LAST_WQE = 0x13, 965 MLXCX_EVENT_SRQ_LIMIT = 0x14, 966 MLXCX_EVENT_DCT_ALL_CLOSED = 0x1C, 967 MLXCX_EVENT_DCT_ACCKEY_VIOL = 0x1D, 968 MLXCX_EVENT_CQ_ERROR = 0x04, 969 MLXCX_EVENT_WQ_CATASTROPHE = 0x05, 970 MLXCX_EVENT_PATH_MIGRATE_FAIL = 0x07, 971 MLXCX_EVENT_PAGE_FAULT = 0x0C, 972 MLXCX_EVENT_WQ_INVALID_REQ = 0x10, 973 MLXCX_EVENT_WQ_ACCESS_VIOL = 0x11, 974 MLXCX_EVENT_SRQ_CATASTROPHE = 0x12, 975 MLXCX_EVENT_INTERNAL_ERROR = 0x08, 976 MLXCX_EVENT_PORT_STATE = 0x09, 977 MLXCX_EVENT_GPIO = 0x15, 978 MLXCX_EVENT_PORT_MODULE = 0x16, 979 MLXCX_EVENT_TEMP_WARNING = 0x17, 980 MLXCX_EVENT_REMOTE_CONFIG = 0x19, 981 MLXCX_EVENT_DCBX_CHANGE = 0x1E, 982 MLXCX_EVENT_DOORBELL_CONGEST = 0x1A, 983 MLXCX_EVENT_STALL_VL = 0x1B, 984 MLXCX_EVENT_CMD_COMPLETION = 0x0A, 985 MLXCX_EVENT_PAGE_REQUEST = 0x0B, 986 MLXCX_EVENT_NIC_VPORT = 0x0D, 987 MLXCX_EVENT_EC_PARAMS_CHANGE = 0x0E, 988 MLXCX_EVENT_XRQ_ERROR = 0x18 989 } mlxcx_event_t; 990 991 typedef enum { 992 MLXCX_CMD_R_OK = 0x00, 993 MLXCX_CMD_R_INTERNAL_ERR = 0x01, 994 MLXCX_CMD_R_BAD_OP = 0x02, 995 MLXCX_CMD_R_BAD_PARAM = 0x03, 996 MLXCX_CMD_R_BAD_SYS_STATE = 0x04, 997 MLXCX_CMD_R_BAD_RESOURCE = 0x05, 998 MLXCX_CMD_R_RESOURCE_BUSY = 0x06, 999 MLXCX_CMD_R_EXCEED_LIM = 0x08, 1000 MLXCX_CMD_R_BAD_RES_STATE = 0x09, 1001 MLXCX_CMD_R_BAD_INDEX = 0x0a, 1002 MLXCX_CMD_R_NO_RESOURCES = 0x0f, 1003 MLXCX_CMD_R_BAD_INPUT_LEN = 0x50, 1004 MLXCX_CMD_R_BAD_OUTPUT_LEN = 0x51, 1005 MLXCX_CMD_R_BAD_RESOURCE_STATE = 0x10, 1006 MLXCX_CMD_R_BAD_PKT = 0x30, 1007 MLXCX_CMD_R_BAD_SIZE = 0x40, 1008 MLXCX_CMD_R_TIMEOUT = 0xFF 1009 } mlxcx_cmd_ret_t; 1010 1011 typedef enum { 1012 MLXCX_OP_QUERY_HCA_CAP = 0x100, 1013 MLXCX_OP_QUERY_ADAPTER = 0x101, 1014 MLXCX_OP_INIT_HCA = 0x102, 1015 MLXCX_OP_TEARDOWN_HCA = 0x103, 1016 MLXCX_OP_ENABLE_HCA = 0x104, 1017 MLXCX_OP_DISABLE_HCA = 0x105, 1018 MLXCX_OP_QUERY_PAGES = 0x107, 1019 MLXCX_OP_MANAGE_PAGES = 0x108, 1020 MLXCX_OP_SET_HCA_CAP = 0x109, 1021 MLXCX_OP_QUERY_ISSI = 0x10A, 1022 MLXCX_OP_SET_ISSI = 0x10B, 1023 MLXCX_OP_SET_DRIVER_VERSION = 0x10D, 1024 MLXCX_OP_QUERY_OTHER_HCA_CAP = 0x10E, 1025 MLXCX_OP_MODIFY_OTHER_HCA_CAP = 0x10F, 1026 MLXCX_OP_SET_TUNNELED_OPERATIONS = 0x110, 1027 MLXCX_OP_CREATE_MKEY = 0x200, 1028 MLXCX_OP_QUERY_MKEY = 0x201, 1029 MLXCX_OP_DESTROY_MKEY = 0x202, 1030 MLXCX_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 1031 MLXCX_OP_PAGE_FAULT_RESUME = 0x204, 1032 MLXCX_OP_CREATE_EQ = 0x301, 1033 MLXCX_OP_DESTROY_EQ = 0x302, 1034 MLXCX_OP_QUERY_EQ = 0x303, 1035 MLXCX_OP_GEN_EQE = 0x304, 1036 MLXCX_OP_CREATE_CQ = 0x400, 1037 MLXCX_OP_DESTROY_CQ = 0x401, 1038 MLXCX_OP_QUERY_CQ = 0x402, 1039 MLXCX_OP_MODIFY_CQ = 0x403, 1040 MLXCX_OP_CREATE_QP = 0x500, 1041 MLXCX_OP_DESTROY_QP = 0x501, 1042 MLXCX_OP_RST2INIT_QP = 0x502, 1043 MLXCX_OP_INIT2RTR_QP = 0x503, 1044 MLXCX_OP_RTR2RTS_QP = 0x504, 1045 MLXCX_OP_RTS2RTS_QP = 0x505, 1046 MLXCX_OP_SQERR2RTS_QP = 0x506, 1047 MLXCX_OP__2ERR_QP = 0x507, 1048 MLXCX_OP__2RST_QP = 0x50A, 1049 MLXCX_OP_QUERY_QP = 0x50B, 1050 MLXCX_OP_SQD_RTS_QP = 0x50C, 1051 MLXCX_OP_INIT2INIT_QP = 0x50E, 1052 MLXCX_OP_CREATE_PSV = 0x600, 1053 MLXCX_OP_DESTROY_PSV = 0x601, 1054 MLXCX_OP_CREATE_SRQ = 0x700, 1055 MLXCX_OP_DESTROY_SRQ = 0x701, 1056 MLXCX_OP_QUERY_SRQ = 0x702, 1057 MLXCX_OP_ARM_RQ = 0x703, 1058 MLXCX_OP_CREATE_XRC_SRQ = 0x705, 1059 MLXCX_OP_DESTROY_XRC_SRQ = 0x706, 1060 MLXCX_OP_QUERY_XRC_SRQ = 0x707, 1061 MLXCX_OP_ARM_XRC_SRQ = 0x708, 1062 MLXCX_OP_CREATE_DCT = 0x710, 1063 MLXCX_OP_DESTROY_DCT = 0x711, 1064 MLXCX_OP_DRAIN_DCT = 0x712, 1065 MLXCX_OP_QUERY_DCT = 0x713, 1066 MLXCX_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 1067 MLXCX_OP_CREATE_XRQ = 0x717, 1068 MLXCX_OP_DESTROY_XRQ = 0x718, 1069 MLXCX_OP_QUERY_XRQ = 0x719, 1070 MLXCX_OP_CREATE_NVMF_BACKEND_CONTROLLER = 0x720, 1071 MLXCX_OP_DESTROY_NVMF_BACKEND_CONTROLLER = 0x721, 1072 MLXCX_OP_QUERY_NVMF_BACKEND_CONTROLLER = 0x722, 1073 MLXCX_OP_ATTACH_NVMF_NAMESPACE = 0x723, 1074 MLXCX_OP_DETACH_NVMF_NAMESPACE = 0x724, 1075 MLXCX_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 1076 MLXCX_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 1077 MLXCX_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 1078 MLXCX_OP_QUERY_VPORT_STATE = 0x750, 1079 MLXCX_OP_MODIFY_VPORT_STATE = 0x751, 1080 MLXCX_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 1081 MLXCX_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 1082 MLXCX_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1083 MLXCX_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 1084 MLXCX_OP_QUERY_ROCE_ADDRESS = 0x760, 1085 MLXCX_OP_SET_ROCE_ADDRESS = 0x761, 1086 MLXCX_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 1087 MLXCX_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 1088 MLXCX_OP_QUERY_HCA_VPORT_GID = 0x764, 1089 MLXCX_OP_QUERY_HCA_VPORT_PKEY = 0x765, 1090 MLXCX_OP_QUERY_VPORT_COUNTER = 0x770, 1091 MLXCX_OP_ALLOC_Q_COUNTER = 0x771, 1092 MLXCX_OP_DEALLOC_Q_COUNTER = 0x772, 1093 MLXCX_OP_QUERY_Q_COUNTER = 0x773, 1094 MLXCX_OP_SET_PP_RATE_LIMIT = 0x780, 1095 MLXCX_OP_QUERY_PP_RATE_LIMIT = 0x781, 1096 MLXCX_OP_ALLOC_PD = 0x800, 1097 MLXCX_OP_DEALLOC_PD = 0x801, 1098 MLXCX_OP_ALLOC_UAR = 0x802, 1099 MLXCX_OP_DEALLOC_UAR = 0x803, 1100 MLXCX_OP_CONFIG_INT_MODERATION = 0x804, 1101 MLXCX_OP_ACCESS_REG = 0x805, 1102 MLXCX_OP_ATTACH_TO_MCG = 0x806, 1103 MLXCX_OP_DETACH_FROM_MCG = 0x807, 1104 MLXCX_OP_MAD_IFC = 0x50D, 1105 MLXCX_OP_QUERY_MAD_DEMUX = 0x80B, 1106 MLXCX_OP_SET_MAD_DEMUX = 0x80C, 1107 MLXCX_OP_NOP = 0x80D, 1108 MLXCX_OP_ALLOC_XRCD = 0x80E, 1109 MLXCX_OP_DEALLOC_XRCD = 0x80F, 1110 MLXCX_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1111 MLXCX_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 1112 MLXCX_OP_QUERY_CONG_STATUS = 0x822, 1113 MLXCX_OP_MODIFY_CONG_STATUS = 0x823, 1114 MLXCX_OP_QUERY_CONG_PARAMS = 0x824, 1115 MLXCX_OP_MODIFY_CONG_PARAMS = 0x825, 1116 MLXCX_OP_QUERY_CONG_STATISTICS = 0x826, 1117 MLXCX_OP_ADD_VXLAN_UDP_DPORT = 0x827, 1118 MLXCX_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 1119 MLXCX_OP_SET_L2_TABLE_ENTRY = 0x829, 1120 MLXCX_OP_QUERY_L2_TABLE_ENTRY = 0x82A, 1121 MLXCX_OP_DELETE_L2_TABLE_ENTRY = 0x82B, 1122 MLXCX_OP_SET_WOL_ROL = 0x830, 1123 MLXCX_OP_QUERY_WOL_ROL = 0x831, 1124 MLXCX_OP_CREATE_TIR = 0x900, 1125 MLXCX_OP_MODIFY_TIR = 0x901, 1126 MLXCX_OP_DESTROY_TIR = 0x902, 1127 MLXCX_OP_QUERY_TIR = 0x903, 1128 MLXCX_OP_CREATE_SQ = 0x904, 1129 MLXCX_OP_MODIFY_SQ = 0x905, 1130 MLXCX_OP_DESTROY_SQ = 0x906, 1131 MLXCX_OP_QUERY_SQ = 0x907, 1132 MLXCX_OP_CREATE_RQ = 0x908, 1133 MLXCX_OP_MODIFY_RQ = 0x909, 1134 MLXCX_OP_DESTROY_RQ = 0x90A, 1135 MLXCX_OP_QUERY_RQ = 0x90B, 1136 MLXCX_OP_CREATE_RMP = 0x90C, 1137 MLXCX_OP_MODIFY_RMP = 0x90D, 1138 MLXCX_OP_DESTROY_RMP = 0x90E, 1139 MLXCX_OP_QUERY_RMP = 0x90F, 1140 MLXCX_OP_CREATE_TIS = 0x912, 1141 MLXCX_OP_MODIFY_TIS = 0x913, 1142 MLXCX_OP_DESTROY_TIS = 0x914, 1143 MLXCX_OP_QUERY_TIS = 0x915, 1144 MLXCX_OP_CREATE_RQT = 0x916, 1145 MLXCX_OP_MODIFY_RQT = 0x917, 1146 MLXCX_OP_DESTROY_RQT = 0x918, 1147 MLXCX_OP_QUERY_RQT = 0x919, 1148 MLXCX_OP_SET_FLOW_TABLE_ROOT = 0x92f, 1149 MLXCX_OP_CREATE_FLOW_TABLE = 0x930, 1150 MLXCX_OP_DESTROY_FLOW_TABLE = 0x931, 1151 MLXCX_OP_QUERY_FLOW_TABLE = 0x932, 1152 MLXCX_OP_CREATE_FLOW_GROUP = 0x933, 1153 MLXCX_OP_DESTROY_FLOW_GROUP = 0x934, 1154 MLXCX_OP_QUERY_FLOW_GROUP = 0x935, 1155 MLXCX_OP_SET_FLOW_TABLE_ENTRY = 0x936, 1156 MLXCX_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 1157 MLXCX_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 1158 MLXCX_OP_ALLOC_FLOW_COUNTER = 0x939, 1159 MLXCX_OP_DEALLOC_FLOW_COUNTER = 0x93a, 1160 MLXCX_OP_QUERY_FLOW_COUNTER = 0x93b, 1161 MLXCX_OP_MODIFY_FLOW_TABLE = 0x93c, 1162 MLXCX_OP_ALLOC_ENCAP_HEADER = 0x93d, 1163 MLXCX_OP_DEALLOC_ENCAP_HEADER = 0x93e, 1164 MLXCX_OP_QUERY_ENCAP_HEADER = 0x93f 1165 } mlxcx_cmd_op_t; 1166 1167 /* 1168 * Definitions for relevant commands 1169 */ 1170 #pragma pack(1) 1171 typedef struct { 1172 uint16be_t mci_opcode; 1173 uint8_t mci_rsvd[4]; 1174 uint16be_t mci_op_mod; 1175 } mlxcx_cmd_in_t; 1176 1177 typedef struct { 1178 uint8_t mco_status; 1179 uint8_t mco_rsvd[3]; 1180 uint32be_t mco_syndrome; 1181 } mlxcx_cmd_out_t; 1182 1183 typedef struct { 1184 mlxcx_cmd_in_t mlxi_enable_hca_head; 1185 uint8_t mlxi_enable_hca_rsvd[2]; 1186 uint16be_t mlxi_enable_hca_func; 1187 uint8_t mlxi_enable_hca_rsvd1[4]; 1188 } mlxcx_cmd_enable_hca_in_t; 1189 1190 typedef struct { 1191 mlxcx_cmd_out_t mlxo_enable_hca_head; 1192 uint8_t mlxo_enable_hca_rsvd[8]; 1193 } mlxcx_cmd_enable_hca_out_t; 1194 1195 typedef struct { 1196 mlxcx_cmd_in_t mlxi_disable_hca_head; 1197 uint8_t mlxi_disable_hca_rsvd[2]; 1198 uint16be_t mlxi_disable_hca_func; 1199 uint8_t mlxi_disable_hca_rsvd1[4]; 1200 } mlxcx_cmd_disable_hca_in_t; 1201 1202 typedef struct { 1203 mlxcx_cmd_out_t mlxo_disable_hca_head; 1204 uint8_t mlxo_disable_hca_rsvd[8]; 1205 } mlxcx_cmd_disable_hca_out_t; 1206 1207 typedef struct { 1208 mlxcx_cmd_in_t mlxi_query_issi_head; 1209 uint8_t mlxi_query_issi_rsvd[8]; 1210 } mlxcx_cmd_query_issi_in_t; 1211 1212 typedef struct { 1213 mlxcx_cmd_out_t mlxo_query_issi_head; 1214 uint8_t mlxo_query_issi_rsv[2]; 1215 uint16be_t mlxo_query_issi_current; 1216 uint8_t mlxo_query_issi_rsvd1[20]; 1217 /* 1218 * To date we only support version 1 of the ISSI. The last byte has the 1219 * ISSI data that we care about, therefore we phrase the struct this 1220 * way. 1221 */ 1222 uint8_t mlxo_query_issi_rsvd2[79]; 1223 uint8_t mlxo_supported_issi; 1224 } mlxcx_cmd_query_issi_out_t; 1225 1226 typedef struct { 1227 mlxcx_cmd_in_t mlxi_set_issi_head; 1228 uint8_t mlxi_set_issi_rsvd[2]; 1229 uint16be_t mlxi_set_issi_current; 1230 uint8_t mlxi_set_iss_rsvd1[4]; 1231 } mlxcx_cmd_set_issi_in_t; 1232 1233 typedef struct { 1234 mlxcx_cmd_out_t mlxo_set_issi_head; 1235 uint8_t mlxo_set_issi_rsvd[8]; 1236 } mlxcx_cmd_set_issi_out_t; 1237 1238 typedef struct { 1239 mlxcx_cmd_in_t mlxi_init_hca_head; 1240 uint8_t mlxi_init_hca_rsvd[8]; 1241 } mlxcx_cmd_init_hca_in_t; 1242 1243 typedef struct { 1244 mlxcx_cmd_out_t mlxo_init_hca_head; 1245 uint8_t mlxo_init_hca_rsvd[8]; 1246 } mlxcx_cmd_init_hca_out_t; 1247 1248 #define MLXCX_TEARDOWN_HCA_GRACEFUL 0x00 1249 #define MLXCX_TEARDOWN_HCA_FORCE 0x01 1250 1251 typedef struct { 1252 mlxcx_cmd_in_t mlxi_teardown_hca_head; 1253 uint8_t mlxi_teardown_hca_rsvd[2]; 1254 uint16be_t mlxi_teardown_hca_profile; 1255 uint8_t mlxi_teardown_hca_rsvd1[4]; 1256 } mlxcx_cmd_teardown_hca_in_t; 1257 1258 typedef struct { 1259 mlxcx_cmd_out_t mlxo_teardown_hca_head; 1260 uint8_t mlxo_teardown_hca_rsvd[7]; 1261 uint8_t mlxo_teardown_hca_state; 1262 } mlxcx_cmd_teardown_hca_out_t; 1263 1264 #define MLXCX_QUERY_PAGES_OPMOD_BOOT 0x01 1265 #define MLXCX_QUERY_PAGES_OPMOD_INIT 0x02 1266 #define MLXCX_QUERY_PAGES_OPMOD_REGULAR 0x03 1267 1268 typedef struct { 1269 mlxcx_cmd_in_t mlxi_query_pages_head; 1270 uint8_t mlxi_query_pages_rsvd[2]; 1271 uint16be_t mlxi_query_pages_func; 1272 uint8_t mlxi_query_pages_rsvd1[4]; 1273 } mlxcx_cmd_query_pages_in_t; 1274 1275 typedef struct { 1276 mlxcx_cmd_out_t mlxo_query_pages_head; 1277 uint8_t mlxo_query_pages_rsvd[2]; 1278 uint16be_t mlxo_query_pages_func; 1279 uint32be_t mlxo_query_pages_npages; 1280 } mlxcx_cmd_query_pages_out_t; 1281 1282 #define MLXCX_MANAGE_PAGES_OPMOD_ALLOC_FAIL 0x00 1283 #define MLXCX_MANAGE_PAGES_OPMOD_GIVE_PAGES 0x01 1284 #define MLXCX_MANAGE_PAGES_OPMOD_RETURN_PAGES 0x02 1285 1286 /* 1287 * This is an artificial limit that we're imposing on our actions. 1288 */ 1289 #define MLXCX_MANAGE_PAGES_MAX_PAGES 512 1290 1291 typedef struct { 1292 mlxcx_cmd_in_t mlxi_manage_pages_head; 1293 uint8_t mlxi_manage_pages_rsvd[2]; 1294 uint16be_t mlxi_manage_pages_func; 1295 uint32be_t mlxi_manage_pages_npages; 1296 uint64be_t mlxi_manage_pages_pas[MLXCX_MANAGE_PAGES_MAX_PAGES]; 1297 } mlxcx_cmd_manage_pages_in_t; 1298 1299 typedef struct { 1300 mlxcx_cmd_out_t mlxo_manage_pages_head; 1301 uint32be_t mlxo_manage_pages_npages; 1302 uint8_t mlxo_manage_pages_rsvd[4]; 1303 uint64be_t mlxo_manage_pages_pas[MLXCX_MANAGE_PAGES_MAX_PAGES]; 1304 } mlxcx_cmd_manage_pages_out_t; 1305 1306 typedef enum { 1307 MLXCX_HCA_CAP_MODE_MAX = 0x0, 1308 MLXCX_HCA_CAP_MODE_CURRENT = 0x1 1309 } mlxcx_hca_cap_mode_t; 1310 1311 typedef enum { 1312 MLXCX_HCA_CAP_GENERAL = 0x0, 1313 MLXCX_HCA_CAP_ETHERNET = 0x1, 1314 MLXCX_HCA_CAP_ODP = 0x2, 1315 MLXCX_HCA_CAP_ATOMIC = 0x3, 1316 MLXCX_HCA_CAP_ROCE = 0x4, 1317 MLXCX_HCA_CAP_IPoIB = 0x5, 1318 MLXCX_HCA_CAP_NIC_FLOW = 0x7, 1319 MLXCX_HCA_CAP_ESWITCH_FLOW = 0x8, 1320 MLXCX_HCA_CAP_ESWITCH = 0x9, 1321 MLXCX_HCA_CAP_VECTOR = 0xb, 1322 MLXCX_HCA_CAP_QoS = 0xc, 1323 MLXCX_HCA_CAP_NVMEoF = 0xe 1324 } mlxcx_hca_cap_type_t; 1325 1326 typedef enum { 1327 MLXCX_CAP_GENERAL_PORT_TYPE_IB = 0x0, 1328 MLXCX_CAP_GENERAL_PORT_TYPE_ETHERNET = 0x1, 1329 } mlxcx_hca_cap_general_port_type_t; 1330 1331 typedef enum { 1332 MLXCX_CAP_GENERAL_FLAGS_C_ESW_FLOW_TABLE = (1 << 8), 1333 MLXCX_CAP_GENERAL_FLAGS_C_NIC_FLOW_TABLE = (1 << 9), 1334 } mlxcx_hca_cap_general_flags_c_t; 1335 1336 typedef struct { 1337 uint8_t mlcap_general_access_other_hca_roce; 1338 uint8_t mlcap_general_rsvd[3]; 1339 1340 uint8_t mlcap_general_rsvd2[12]; 1341 1342 uint8_t mlcap_general_log_max_srq_sz; 1343 uint8_t mlcap_general_log_max_qp_sz; 1344 uint8_t mlcap_general_rsvd3[1]; 1345 uint8_t mlcap_general_log_max_qp; 1346 1347 uint8_t mlcap_general_rsvd4[1]; 1348 uint8_t mlcap_general_log_max_srq; 1349 uint8_t mlcap_general_rsvd5[2]; 1350 1351 uint8_t mlcap_general_rsvd6[1]; 1352 uint8_t mlcap_general_log_max_cq_sz; 1353 uint8_t mlcap_general_rsvd7[1]; 1354 uint8_t mlcap_general_log_max_cq; 1355 1356 uint8_t mlcap_general_log_max_eq_sz; 1357 uint8_t mlcap_general_log_max_mkey_flags; 1358 uint8_t mlcap_general_rsvd8[1]; 1359 uint8_t mlcap_general_log_max_eq; 1360 1361 uint8_t mlcap_general_max_indirection; 1362 uint8_t mlcap_general_log_max_mrw_sz_flags; 1363 uint8_t mlcap_general_log_max_bsf_list_size_flags; 1364 uint8_t mlcap_general_log_max_klm_list_size_flags; 1365 1366 uint8_t mlcap_general_rsvd9[1]; 1367 uint8_t mlcap_general_log_max_ra_req_dc; 1368 uint8_t mlcap_general_rsvd10[1]; 1369 uint8_t mlcap_general_log_max_ra_res_dc; 1370 1371 uint8_t mlcap_general_rsvd11[1]; 1372 uint8_t mlcap_general_log_max_ra_req_qp; 1373 uint8_t mlcap_general_rsvd12[1]; 1374 uint8_t mlcap_general_log_max_ra_res_qp; 1375 1376 uint16be_t mlcap_general_flags_a; 1377 uint16be_t mlcap_general_gid_table_size; 1378 1379 bits16_t mlcap_general_flags_b; 1380 uint16be_t mlcap_general_pkey_table_size; 1381 1382 bits16_t mlcap_general_flags_c; 1383 struct { 1384 #if defined(_BIT_FIELDS_HTOL) 1385 uint8_t mlcap_general_flags_d:6; 1386 uint8_t mlcap_general_port_type:2; 1387 #elif defined(_BIT_FIELDS_LTOH) 1388 uint8_t mlcap_general_port_type:2; 1389 uint8_t mlcap_general_flags_d:6; 1390 #endif 1391 }; 1392 uint8_t mlcap_general_num_ports; 1393 1394 struct { 1395 #if defined(_BIT_FIELDS_HTOL) 1396 uint8_t mlcap_general_rsvd13:3; 1397 uint8_t mlcap_general_log_max_msg:5; 1398 #elif defined(_BIT_FIELDS_LTOH) 1399 uint8_t mlcap_general_log_max_msg:5; 1400 uint8_t mlcap_general_rsvd13:3; 1401 #endif 1402 }; 1403 uint8_t mlcap_general_max_tc; 1404 bits16_t mlcap_general_flags_d_wol; 1405 1406 uint16be_t mlcap_general_state_rate_support; 1407 uint8_t mlcap_general_rsvd14[1]; 1408 struct { 1409 #if defined(_BIT_FIELDS_HTOL) 1410 uint8_t mlcap_general_rsvd15:4; 1411 uint8_t mlcap_general_cqe_version:4; 1412 #elif defined(_BIT_FIELDS_LTOH) 1413 uint8_t mlcap_general_cqe_version:4; 1414 uint8_t mlcap_general_rsvd15:4; 1415 #endif 1416 }; 1417 1418 uint32be_t mlcap_general_flags_e; 1419 1420 uint32be_t mlcap_general_flags_f; 1421 1422 uint8_t mlcap_general_rsvd16[1]; 1423 uint8_t mlcap_general_uar_sz; 1424 uint8_t mlcap_general_cnak; 1425 uint8_t mlcap_general_log_pg_sz; 1426 uint8_t mlcap_general_rsvd17[32]; 1427 bits8_t mlcap_general_log_max_rq_flags; 1428 uint8_t mlcap_general_log_max_sq; 1429 uint8_t mlcap_general_log_max_tir; 1430 uint8_t mlcap_general_log_max_tis; 1431 } mlxcx_hca_cap_general_caps_t; 1432 1433 typedef enum { 1434 MLXCX_ETH_CAP_TUNNEL_STATELESS_VXLAN = 1 << 0, 1435 MLXCX_ETH_CAP_TUNNEL_STATELESS_GRE = 1 << 1, 1436 MLXCX_ETH_CAP_TUNNEL_LSO_CONST_OUT_IP_ID = 1 << 4, 1437 MLXCX_ETH_CAP_SCATTER_FCS = 1 << 6, 1438 MLXCX_ETH_CAP_REG_UMR_SQ = 1 << 7, 1439 MLXCX_ETH_CAP_SELF_LB_UC = 1 << 21, 1440 MLXCX_ETH_CAP_SELF_LB_MC = 1 << 22, 1441 MLXCX_ETH_CAP_SELF_LB_EN_MODIFIABLE = 1 << 23, 1442 MLXCX_ETH_CAP_WQE_VLAN_INSERT = 1 << 24, 1443 MLXCX_ETH_CAP_LRO_TIME_STAMP = 1 << 27, 1444 MLXCX_ETH_CAP_LRO_PSH_FLAG = 1 << 28, 1445 MLXCX_ETH_CAP_LRO_CAP = 1 << 29, 1446 MLXCX_ETH_CAP_VLAN_STRIP = 1 << 30, 1447 MLXCX_ETH_CAP_CSUM_CAP = 1UL << 31 1448 } mlxcx_hca_eth_cap_flags_t; 1449 1450 /* CSTYLED */ 1451 #define MLXCX_ETH_CAP_RSS_IND_TBL_CAP (bitdef_t){8, 0x00000f00} 1452 /* CSTYLED */ 1453 #define MLXCX_ETH_CAP_WQE_INLINE_MODE (bitdef_t){12, 0x00003000} 1454 /* CSTYLED */ 1455 #define MLXCX_ETH_CAP_MULTI_PKT_SEND_WQE (bitdef_t){14, 0x0000c000} 1456 /* CSTYLED */ 1457 #define MLXCX_ETH_CAP_MAX_LSO_CAP (bitdef_t){16, 0x001f0000} 1458 /* CSTYLED */ 1459 #define MLXCX_ETH_CAP_LRO_MAX_MSG_SZ_MODE (bitdef_t){25, 0x06000000} 1460 1461 typedef struct { 1462 bits32_t mlcap_eth_flags; 1463 uint8_t mlcap_eth_rsvd[6]; 1464 uint16be_t mlcap_eth_lro_min_mss_size; 1465 uint8_t mlcap_eth_rsvd2[36]; 1466 uint32be_t mlcap_eth_lro_timer_supported_periods[4]; 1467 } mlxcx_hca_cap_eth_caps_t; 1468 1469 typedef enum { 1470 MLXCX_FLOW_CAP_PROPS_DECAP = 1 << 23, 1471 MLXCX_FLOW_CAP_PROPS_ENCAP = 1 << 24, 1472 MLXCX_FLOW_CAP_PROPS_MODIFY_TBL = 1 << 25, 1473 MLXCX_FLOW_CAP_PROPS_MISS_TABLE = 1 << 26, 1474 MLXCX_FLOW_CAP_PROPS_MODIFY_ROOT_TBL = 1 << 27, 1475 MLXCX_FLOW_CAP_PROPS_MODIFY = 1 << 28, 1476 MLXCX_FLOW_CAP_PROPS_COUNTER = 1 << 29, 1477 MLXCX_FLOW_CAP_PROPS_TAG = 1 << 30, 1478 MLXCX_FLOW_CAP_PROPS_SUPPORT = 1UL << 31 1479 } mlxcx_hca_cap_flow_cap_props_flags_t; 1480 1481 typedef struct { 1482 bits32_t mlcap_flow_prop_flags; 1483 uint8_t mlcap_flow_prop_log_max_ft_size; 1484 uint8_t mlcap_flow_prop_rsvd[2]; 1485 uint8_t mlcap_flow_prop_max_ft_level; 1486 uint8_t mlcap_flow_prop_rsvd2[7]; 1487 uint8_t mlcap_flow_prop_log_max_ft_num; 1488 uint8_t mlcap_flow_prop_rsvd3[2]; 1489 uint8_t mlcap_flow_prop_log_max_flow_counter; 1490 uint8_t mlcap_flow_prop_log_max_destination; 1491 uint8_t mlcap_flow_prop_rsvd4[3]; 1492 uint8_t mlcap_flow_prop_log_max_flow; 1493 uint8_t mlcap_flow_prop_rsvd5[8]; 1494 bits32_t mlcap_flow_prop_support[4]; 1495 bits32_t mlcap_flow_prop_bitmask[4]; 1496 } mlxcx_hca_cap_flow_cap_props_t; 1497 1498 typedef struct { 1499 bits32_t mlcap_flow_flags; 1500 uint8_t mlcap_flow_rsvd[60]; 1501 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx; 1502 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_rdma; 1503 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_sniffer; 1504 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx; 1505 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_rdma; 1506 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_sniffer; 1507 } mlxcx_hca_cap_flow_caps_t; 1508 1509 /* 1510 * Size of a buffer that is required to hold the output data. 1511 */ 1512 #define MLXCX_HCA_CAP_SIZE 0x1000 1513 1514 typedef struct { 1515 mlxcx_cmd_in_t mlxi_query_hca_cap_head; 1516 uint8_t mlxi_query_hca_cap_rsvd[8]; 1517 } mlxcx_cmd_query_hca_cap_in_t; 1518 1519 typedef struct { 1520 mlxcx_cmd_out_t mlxo_query_hca_cap_head; 1521 uint8_t mlxo_query_hca_cap_rsvd[8]; 1522 uint8_t mlxo_query_hca_cap_data[MLXCX_HCA_CAP_SIZE]; 1523 } mlxcx_cmd_query_hca_cap_out_t; 1524 1525 typedef struct { 1526 mlxcx_cmd_in_t mlxi_set_driver_version_head; 1527 uint8_t mlxi_set_driver_version_rsvd[8]; 1528 char mlxi_set_driver_version_version[64]; 1529 } mlxcx_cmd_set_driver_version_in_t; 1530 1531 typedef struct { 1532 mlxcx_cmd_out_t mlxo_set_driver_version_head; 1533 uint8_t mlxo_set_driver_version_rsvd[8]; 1534 } mlxcx_cmd_set_driver_version_out_t; 1535 1536 typedef struct { 1537 mlxcx_cmd_in_t mlxi_alloc_uar_head; 1538 uint8_t mlxi_alloc_uar_rsvd[8]; 1539 } mlxcx_cmd_alloc_uar_in_t; 1540 1541 typedef struct { 1542 mlxcx_cmd_out_t mlxo_alloc_uar_head; 1543 uint8_t mlxo_alloc_uar_rsvd; 1544 uint24be_t mlxo_alloc_uar_uar; 1545 uint8_t mlxo_alloc_uar_rsvd2[4]; 1546 } mlxcx_cmd_alloc_uar_out_t; 1547 1548 typedef struct { 1549 mlxcx_cmd_in_t mlxi_dealloc_uar_head; 1550 uint8_t mlxi_dealloc_uar_rsvd; 1551 uint24be_t mlxi_dealloc_uar_uar; 1552 uint8_t mlxi_dealloc_uar_rsvd2[4]; 1553 } mlxcx_cmd_dealloc_uar_in_t; 1554 1555 typedef struct { 1556 mlxcx_cmd_out_t mlxo_dealloc_uar_head; 1557 uint8_t mlxo_dealloc_uar_rsvd[8]; 1558 } mlxcx_cmd_dealloc_uar_out_t; 1559 1560 /* 1561 * This is an artificial limit that we're imposing on our actions. 1562 */ 1563 #define MLXCX_CREATE_QUEUE_MAX_PAGES 128 1564 1565 typedef struct { 1566 mlxcx_cmd_in_t mlxi_create_eq_head; 1567 uint8_t mlxi_create_eq_rsvd[8]; 1568 mlxcx_eventq_ctx_t mlxi_create_eq_context; 1569 uint8_t mlxi_create_eq_rsvd2[8]; 1570 uint64be_t mlxi_create_eq_event_bitmask; 1571 uint8_t mlxi_create_eq_rsvd3[176]; 1572 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1573 } mlxcx_cmd_create_eq_in_t; 1574 1575 typedef struct { 1576 mlxcx_cmd_out_t mlxo_create_eq_head; 1577 uint8_t mlxo_create_eq_rsvd[3]; 1578 uint8_t mlxo_create_eq_eqn; 1579 uint8_t mlxo_create_eq_rsvd2[4]; 1580 } mlxcx_cmd_create_eq_out_t; 1581 1582 typedef struct { 1583 mlxcx_cmd_in_t mlxi_query_eq_head; 1584 uint8_t mlxi_query_eq_rsvd[3]; 1585 uint8_t mlxi_query_eq_eqn; 1586 uint8_t mlxi_query_eq_rsvd2[4]; 1587 } mlxcx_cmd_query_eq_in_t; 1588 1589 typedef struct { 1590 mlxcx_cmd_out_t mlxo_query_eq_head; 1591 uint8_t mlxo_query_eq_rsvd[8]; 1592 mlxcx_eventq_ctx_t mlxo_query_eq_context; 1593 uint8_t mlxi_query_eq_rsvd2[8]; 1594 uint64be_t mlxi_query_eq_event_bitmask; 1595 uint8_t mlxi_query_eq_rsvd3[176]; 1596 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1597 } mlxcx_cmd_query_eq_out_t; 1598 1599 typedef struct { 1600 mlxcx_cmd_in_t mlxi_destroy_eq_head; 1601 uint8_t mlxi_destroy_eq_rsvd[3]; 1602 uint8_t mlxi_destroy_eq_eqn; 1603 uint8_t mlxi_destroy_eq_rsvd2[4]; 1604 } mlxcx_cmd_destroy_eq_in_t; 1605 1606 typedef struct { 1607 mlxcx_cmd_out_t mlxo_destroy_eq_head; 1608 uint8_t mlxo_destroy_eq_rsvd[8]; 1609 } mlxcx_cmd_destroy_eq_out_t; 1610 1611 typedef struct { 1612 mlxcx_cmd_in_t mlxi_alloc_pd_head; 1613 uint8_t mlxi_alloc_pd_rsvd[8]; 1614 } mlxcx_cmd_alloc_pd_in_t; 1615 1616 typedef struct { 1617 mlxcx_cmd_out_t mlxo_alloc_pd_head; 1618 uint8_t mlxo_alloc_pd_rsvd; 1619 uint24be_t mlxo_alloc_pd_pdn; 1620 uint8_t mlxo_alloc_pd_rsvd2[4]; 1621 } mlxcx_cmd_alloc_pd_out_t; 1622 1623 typedef struct { 1624 mlxcx_cmd_in_t mlxi_dealloc_pd_head; 1625 uint8_t mlxi_dealloc_pd_rsvd; 1626 uint24be_t mlxi_dealloc_pd_pdn; 1627 uint8_t mlxi_dealloc_pd_rsvd2[4]; 1628 } mlxcx_cmd_dealloc_pd_in_t; 1629 1630 typedef struct { 1631 mlxcx_cmd_out_t mlxo_dealloc_pd_head; 1632 uint8_t mlxo_dealloc_pd_rsvd[8]; 1633 } mlxcx_cmd_dealloc_pd_out_t; 1634 1635 typedef struct { 1636 mlxcx_cmd_in_t mlxi_alloc_tdom_head; 1637 uint8_t mlxi_alloc_tdom_rsvd[8]; 1638 } mlxcx_cmd_alloc_tdom_in_t; 1639 1640 typedef struct { 1641 mlxcx_cmd_out_t mlxo_alloc_tdom_head; 1642 uint8_t mlxo_alloc_tdom_rsvd; 1643 uint24be_t mlxo_alloc_tdom_tdomn; 1644 uint8_t mlxo_alloc_tdom_rsvd2[4]; 1645 } mlxcx_cmd_alloc_tdom_out_t; 1646 1647 typedef struct { 1648 mlxcx_cmd_in_t mlxi_dealloc_tdom_head; 1649 uint8_t mlxi_dealloc_tdom_rsvd; 1650 uint24be_t mlxi_dealloc_tdom_tdomn; 1651 uint8_t mlxi_dealloc_tdom_rsvd2[4]; 1652 } mlxcx_cmd_dealloc_tdom_in_t; 1653 1654 typedef struct { 1655 mlxcx_cmd_out_t mlxo_dealloc_tdom_head; 1656 uint8_t mlxo_dealloc_tdom_rsvd[8]; 1657 } mlxcx_cmd_dealloc_tdom_out_t; 1658 1659 typedef struct { 1660 mlxcx_cmd_in_t mlxi_create_tir_head; 1661 uint8_t mlxi_create_tir_rsvd[24]; 1662 mlxcx_tir_ctx_t mlxi_create_tir_context; 1663 } mlxcx_cmd_create_tir_in_t; 1664 1665 typedef struct { 1666 mlxcx_cmd_out_t mlxo_create_tir_head; 1667 uint8_t mlxo_create_tir_rsvd; 1668 uint24be_t mlxo_create_tir_tirn; 1669 uint8_t mlxo_create_tir_rsvd2[4]; 1670 } mlxcx_cmd_create_tir_out_t; 1671 1672 typedef struct { 1673 mlxcx_cmd_in_t mlxi_destroy_tir_head; 1674 uint8_t mlxi_destroy_tir_rsvd; 1675 uint24be_t mlxi_destroy_tir_tirn; 1676 uint8_t mlxi_destroy_tir_rsvd2[4]; 1677 } mlxcx_cmd_destroy_tir_in_t; 1678 1679 typedef struct { 1680 mlxcx_cmd_out_t mlxo_destroy_tir_head; 1681 uint8_t mlxo_destroy_tir_rsvd[8]; 1682 } mlxcx_cmd_destroy_tir_out_t; 1683 1684 typedef struct { 1685 mlxcx_cmd_in_t mlxi_create_tis_head; 1686 uint8_t mlxi_create_tis_rsvd[24]; 1687 mlxcx_tis_ctx_t mlxi_create_tis_context; 1688 } mlxcx_cmd_create_tis_in_t; 1689 1690 typedef struct { 1691 mlxcx_cmd_out_t mlxo_create_tis_head; 1692 uint8_t mlxo_create_tis_rsvd; 1693 uint24be_t mlxo_create_tis_tisn; 1694 uint8_t mlxo_create_tis_rsvd2[4]; 1695 } mlxcx_cmd_create_tis_out_t; 1696 1697 typedef struct { 1698 mlxcx_cmd_in_t mlxi_destroy_tis_head; 1699 uint8_t mlxi_destroy_tis_rsvd; 1700 uint24be_t mlxi_destroy_tis_tisn; 1701 uint8_t mlxi_destroy_tis_rsvd2[4]; 1702 } mlxcx_cmd_destroy_tis_in_t; 1703 1704 typedef struct { 1705 mlxcx_cmd_out_t mlxo_destroy_tis_head; 1706 uint8_t mlxo_destroy_tis_rsvd[8]; 1707 } mlxcx_cmd_destroy_tis_out_t; 1708 1709 typedef struct { 1710 mlxcx_cmd_in_t mlxi_query_special_ctxs_head; 1711 uint8_t mlxi_query_special_ctxs_rsvd[8]; 1712 } mlxcx_cmd_query_special_ctxs_in_t; 1713 1714 typedef struct { 1715 mlxcx_cmd_out_t mlxo_query_special_ctxs_head; 1716 uint8_t mlxo_query_special_ctxs_rsvd[4]; 1717 uint32be_t mlxo_query_special_ctxs_resd_lkey; 1718 uint32be_t mlxo_query_special_ctxs_null_mkey; 1719 uint8_t mlxo_query_special_ctxs_rsvd2[12]; 1720 } mlxcx_cmd_query_special_ctxs_out_t; 1721 1722 typedef enum { 1723 MLXCX_VPORT_TYPE_VNIC = 0x0, 1724 MLXCX_VPORT_TYPE_ESWITCH = 0x1, 1725 MLXCX_VPORT_TYPE_UPLINK = 0x2, 1726 } mlxcx_cmd_vport_op_mod_t; 1727 1728 typedef struct { 1729 mlxcx_cmd_in_t mlxi_query_nic_vport_ctx_head; 1730 uint8_t mlxi_query_nic_vport_ctx_other_vport; 1731 uint8_t mlxi_query_nic_vport_ctx_rsvd[1]; 1732 uint16be_t mlxi_query_nic_vport_ctx_vport_number; 1733 uint8_t mlxi_query_nic_vport_ctx_allowed_list_type; 1734 uint8_t mlxi_query_nic_vport_ctx_rsvd2[3]; 1735 } mlxcx_cmd_query_nic_vport_ctx_in_t; 1736 1737 typedef struct { 1738 mlxcx_cmd_out_t mlxo_query_nic_vport_ctx_head; 1739 uint8_t mlxo_query_nic_vport_ctx_rsvd[8]; 1740 mlxcx_nic_vport_ctx_t mlxo_query_nic_vport_ctx_context; 1741 } mlxcx_cmd_query_nic_vport_ctx_out_t; 1742 1743 typedef enum { 1744 MLXCX_MODIFY_NIC_VPORT_CTX_ROCE_EN = 1 << 1, 1745 MLXCX_MODIFY_NIC_VPORT_CTX_ADDR_LIST = 1 << 2, 1746 MLXCX_MODIFY_NIC_VPORT_CTX_PERM_ADDR = 1 << 3, 1747 MLXCX_MODIFY_NIC_VPORT_CTX_PROMISC = 1 << 4, 1748 MLXCX_MODIFY_NIC_VPORT_CTX_EVENT = 1 << 5, 1749 MLXCX_MODIFY_NIC_VPORT_CTX_MTU = 1 << 6, 1750 MLXCX_MODIFY_NIC_VPORT_CTX_WQE_INLINE = 1 << 7, 1751 MLXCX_MODIFY_NIC_VPORT_CTX_PORT_GUID = 1 << 8, 1752 MLXCX_MODIFY_NIC_VPORT_CTX_NODE_GUID = 1 << 9, 1753 } mlxcx_modify_nic_vport_ctx_fields_t; 1754 1755 typedef struct { 1756 mlxcx_cmd_in_t mlxi_modify_nic_vport_ctx_head; 1757 uint8_t mlxi_modify_nic_vport_ctx_other_vport; 1758 uint8_t mlxi_modify_nic_vport_ctx_rsvd[1]; 1759 uint16be_t mlxi_modify_nic_vport_ctx_vport_number; 1760 uint32be_t mlxi_modify_nic_vport_ctx_field_select; 1761 uint8_t mlxi_modify_nic_vport_ctx_rsvd2[240]; 1762 mlxcx_nic_vport_ctx_t mlxi_modify_nic_vport_ctx_context; 1763 } mlxcx_cmd_modify_nic_vport_ctx_in_t; 1764 1765 typedef struct { 1766 mlxcx_cmd_out_t mlxo_modify_nic_vport_ctx_head; 1767 uint8_t mlxo_modify_nic_vport_ctx_rsvd[8]; 1768 } mlxcx_cmd_modify_nic_vport_ctx_out_t; 1769 1770 typedef struct { 1771 mlxcx_cmd_in_t mlxi_query_vport_state_head; 1772 uint8_t mlxi_query_vport_state_other_vport; 1773 uint8_t mlxi_query_vport_state_rsvd[1]; 1774 uint16be_t mlxi_query_vport_state_vport_number; 1775 uint8_t mlxi_query_vport_state_rsvd2[4]; 1776 } mlxcx_cmd_query_vport_state_in_t; 1777 1778 /* CSTYLED */ 1779 #define MLXCX_VPORT_ADMIN_STATE (bitdef_t){4, 0xF0} 1780 /* CSTYLED */ 1781 #define MLXCX_VPORT_OPER_STATE (bitdef_t){0, 0x0F} 1782 1783 typedef enum { 1784 MLXCX_VPORT_OPER_STATE_DOWN = 0x0, 1785 MLXCX_VPORT_OPER_STATE_UP = 0x1, 1786 } mlxcx_vport_oper_state_t; 1787 1788 typedef enum { 1789 MLXCX_VPORT_ADMIN_STATE_DOWN = 0x0, 1790 MLXCX_VPORT_ADMIN_STATE_UP = 0x1, 1791 MLXCX_VPORT_ADMIN_STATE_FOLLOW = 0x2, 1792 } mlxcx_vport_admin_state_t; 1793 1794 typedef struct { 1795 mlxcx_cmd_out_t mlxo_query_vport_state_head; 1796 uint8_t mlxo_query_vport_state_rsvd[4]; 1797 uint16be_t mlxo_query_vport_state_max_tx_speed; 1798 uint8_t mlxo_query_vport_state_rsvd2[1]; 1799 uint8_t mlxo_query_vport_state_state; 1800 } mlxcx_cmd_query_vport_state_out_t; 1801 1802 typedef struct { 1803 mlxcx_cmd_in_t mlxi_create_cq_head; 1804 uint8_t mlxi_create_cq_rsvd[8]; 1805 mlxcx_completionq_ctx_t mlxi_create_cq_context; 1806 uint8_t mlxi_create_cq_rsvd2[192]; 1807 uint64be_t mlxi_create_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1808 } mlxcx_cmd_create_cq_in_t; 1809 1810 typedef struct { 1811 mlxcx_cmd_out_t mlxo_create_cq_head; 1812 uint8_t mlxo_create_cq_rsvd; 1813 uint24be_t mlxo_create_cq_cqn; 1814 uint8_t mlxo_create_cq_rsvd2[4]; 1815 } mlxcx_cmd_create_cq_out_t; 1816 1817 typedef struct { 1818 mlxcx_cmd_in_t mlxi_destroy_cq_head; 1819 uint8_t mlxi_destroy_cq_rsvd; 1820 uint24be_t mlxi_destroy_cq_cqn; 1821 uint8_t mlxi_destroy_cq_rsvd2[4]; 1822 } mlxcx_cmd_destroy_cq_in_t; 1823 1824 typedef struct { 1825 mlxcx_cmd_out_t mlxo_destroy_cq_head; 1826 uint8_t mlxo_destroy_cq_rsvd[8]; 1827 } mlxcx_cmd_destroy_cq_out_t; 1828 1829 typedef struct { 1830 mlxcx_cmd_in_t mlxi_query_cq_head; 1831 uint8_t mlxi_query_cq_rsvd; 1832 uint24be_t mlxi_query_cq_cqn; 1833 uint8_t mlxi_query_cq_rsvd2[4]; 1834 } mlxcx_cmd_query_cq_in_t; 1835 1836 typedef struct { 1837 mlxcx_cmd_out_t mlxo_query_cq_head; 1838 uint8_t mlxo_query_cq_rsvd[8]; 1839 mlxcx_completionq_ctx_t mlxo_query_cq_context; 1840 uint8_t mlxo_query_cq_rsvd2[192]; 1841 uint64be_t mlxo_query_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1842 } mlxcx_cmd_query_cq_out_t; 1843 1844 typedef struct { 1845 mlxcx_cmd_in_t mlxi_create_rq_head; 1846 uint8_t mlxi_create_rq_rsvd[24]; 1847 mlxcx_rq_ctx_t mlxi_create_rq_context; 1848 } mlxcx_cmd_create_rq_in_t; 1849 1850 typedef struct { 1851 mlxcx_cmd_out_t mlxo_create_rq_head; 1852 uint8_t mlxo_create_rq_rsvd; 1853 uint24be_t mlxo_create_rq_rqn; 1854 uint8_t mlxo_create_rq_rsvd2[4]; 1855 } mlxcx_cmd_create_rq_out_t; 1856 1857 /* CSTYLED */ 1858 #define MLXCX_CMD_MODIFY_RQ_STATE (bitdef_t){ \ 1859 .bit_shift = 4, .bit_mask = 0xF0 } 1860 1861 typedef enum { 1862 MLXCX_MODIFY_RQ_SCATTER_FCS = 1 << 2, 1863 MLXCX_MODIFY_RQ_VSD = 1 << 1, 1864 MLXCX_MODIFY_RQ_COUNTER_SET_ID = 1 << 3, 1865 MLXCX_MODIFY_RQ_LWM = 1 << 0 1866 } mlxcx_cmd_modify_rq_bitmask_t; 1867 1868 typedef enum { 1869 MLXCX_RQ_STATE_RST = 0x0, 1870 MLXCX_RQ_STATE_RDY = 0x1, 1871 MLXCX_RQ_STATE_ERR = 0x3 1872 } mlxcx_rq_state_t; 1873 1874 typedef struct { 1875 mlxcx_cmd_in_t mlxi_modify_rq_head; 1876 bits8_t mlxi_modify_rq_state; 1877 uint24be_t mlxi_modify_rq_rqn; 1878 uint8_t mlxi_modify_rq_rsvd[4]; 1879 uint64be_t mlxi_modify_rq_bitmask; 1880 uint8_t mlxi_modify_rq_rsvd2[8]; 1881 mlxcx_rq_ctx_t mlxi_modify_rq_context; 1882 } mlxcx_cmd_modify_rq_in_t; 1883 1884 typedef struct { 1885 mlxcx_cmd_out_t mlxo_modify_rq_head; 1886 uint8_t mlxo_modify_rq_rsvd[8]; 1887 } mlxcx_cmd_modify_rq_out_t; 1888 1889 typedef struct { 1890 mlxcx_cmd_in_t mlxi_query_rq_head; 1891 uint8_t mlxi_query_rq_rsvd; 1892 uint24be_t mlxi_query_rq_rqn; 1893 uint8_t mlxi_query_rq_rsvd2[4]; 1894 } mlxcx_cmd_query_rq_in_t; 1895 1896 typedef struct { 1897 mlxcx_cmd_out_t mlxo_query_rq_head; 1898 uint8_t mlxo_query_rq_rsvd[24]; 1899 mlxcx_rq_ctx_t mlxo_query_rq_context; 1900 } mlxcx_cmd_query_rq_out_t; 1901 1902 typedef struct { 1903 mlxcx_cmd_in_t mlxi_destroy_rq_head; 1904 uint8_t mlxi_destroy_rq_rsvd; 1905 uint24be_t mlxi_destroy_rq_rqn; 1906 uint8_t mlxi_destroy_rq_rsvd2[4]; 1907 } mlxcx_cmd_destroy_rq_in_t; 1908 1909 typedef struct { 1910 mlxcx_cmd_out_t mlxo_destroy_rq_head; 1911 uint8_t mlxo_destroy_rq_rsvd[8]; 1912 } mlxcx_cmd_destroy_rq_out_t; 1913 1914 typedef struct { 1915 mlxcx_cmd_in_t mlxi_create_sq_head; 1916 uint8_t mlxi_create_sq_rsvd[24]; 1917 mlxcx_sq_ctx_t mlxi_create_sq_context; 1918 } mlxcx_cmd_create_sq_in_t; 1919 1920 typedef struct { 1921 mlxcx_cmd_out_t mlxo_create_sq_head; 1922 uint8_t mlxo_create_sq_rsvd; 1923 uint24be_t mlxo_create_sq_sqn; 1924 uint8_t mlxo_create_sq_rsvd2[4]; 1925 } mlxcx_cmd_create_sq_out_t; 1926 1927 /* CSTYLED */ 1928 #define MLXCX_CMD_MODIFY_SQ_STATE (bitdef_t){ \ 1929 .bit_shift = 4, .bit_mask = 0xF0 } 1930 1931 typedef enum { 1932 MLXCX_MODIFY_SQ_PACKET_PACING_INDEX = 1 << 0, 1933 } mlxcx_cmd_modify_sq_bitmask_t; 1934 1935 typedef enum { 1936 MLXCX_SQ_STATE_RST = 0x0, 1937 MLXCX_SQ_STATE_RDY = 0x1, 1938 MLXCX_SQ_STATE_ERR = 0x3 1939 } mlxcx_sq_state_t; 1940 1941 typedef struct { 1942 mlxcx_cmd_in_t mlxi_modify_sq_head; 1943 bits8_t mlxi_modify_sq_state; 1944 uint24be_t mlxi_modify_sq_sqn; 1945 uint8_t mlxi_modify_sq_rsvd[4]; 1946 uint64be_t mlxi_modify_sq_bitmask; 1947 uint8_t mlxi_modify_sq_rsvd2[8]; 1948 mlxcx_sq_ctx_t mlxi_modify_sq_context; 1949 } mlxcx_cmd_modify_sq_in_t; 1950 1951 typedef struct { 1952 mlxcx_cmd_out_t mlxo_modify_sq_head; 1953 uint8_t mlxo_modify_sq_rsvd[8]; 1954 } mlxcx_cmd_modify_sq_out_t; 1955 1956 typedef struct { 1957 mlxcx_cmd_in_t mlxi_query_sq_head; 1958 uint8_t mlxi_query_sq_rsvd; 1959 uint24be_t mlxi_query_sq_sqn; 1960 uint8_t mlxi_query_sq_rsvd2[4]; 1961 } mlxcx_cmd_query_sq_in_t; 1962 1963 typedef struct { 1964 mlxcx_cmd_out_t mlxo_query_sq_head; 1965 uint8_t mlxo_query_sq_rsvd[24]; 1966 mlxcx_sq_ctx_t mlxo_query_sq_context; 1967 } mlxcx_cmd_query_sq_out_t; 1968 1969 typedef struct { 1970 mlxcx_cmd_in_t mlxi_destroy_sq_head; 1971 uint8_t mlxi_destroy_sq_rsvd; 1972 uint24be_t mlxi_destroy_sq_sqn; 1973 uint8_t mlxi_destroy_sq_rsvd2[4]; 1974 } mlxcx_cmd_destroy_sq_in_t; 1975 1976 typedef struct { 1977 mlxcx_cmd_out_t mlxo_destroy_sq_head; 1978 uint8_t mlxo_destroy_sq_rsvd[8]; 1979 } mlxcx_cmd_destroy_sq_out_t; 1980 1981 typedef struct { 1982 mlxcx_cmd_in_t mlxi_create_rqt_head; 1983 uint8_t mlxi_create_rqt_rsvd[24]; 1984 mlxcx_rqtable_ctx_t mlxi_create_rqt_context; 1985 } mlxcx_cmd_create_rqt_in_t; 1986 1987 typedef struct { 1988 mlxcx_cmd_out_t mlxo_create_rqt_head; 1989 uint8_t mlxo_create_rqt_rsvd; 1990 uint24be_t mlxo_create_rqt_rqtn; 1991 uint8_t mlxo_create_rqt_rsvd2[4]; 1992 } mlxcx_cmd_create_rqt_out_t; 1993 1994 typedef struct { 1995 mlxcx_cmd_in_t mlxi_destroy_rqt_head; 1996 uint8_t mlxi_destroy_rqt_rsvd; 1997 uint24be_t mlxi_destroy_rqt_rqtn; 1998 uint8_t mlxi_destroy_rqt_rsvd2[4]; 1999 } mlxcx_cmd_destroy_rqt_in_t; 2000 2001 typedef struct { 2002 mlxcx_cmd_out_t mlxo_destroy_rqt_head; 2003 uint8_t mlxo_destroy_rqt_rsvd[8]; 2004 } mlxcx_cmd_destroy_rqt_out_t; 2005 2006 typedef enum { 2007 MLXCX_FLOW_TABLE_NIC_RX = 0x0, 2008 MLXCX_FLOW_TABLE_NIC_TX = 0x1, 2009 MLXCX_FLOW_TABLE_ESW_OUT = 0x2, 2010 MLXCX_FLOW_TABLE_ESW_IN = 0x3, 2011 MLXCX_FLOW_TABLE_ESW_FDB = 0x4, 2012 MLXCX_FLOW_TABLE_NIC_RX_SNIFF = 0x5, 2013 MLXCX_FLOW_TABLE_NIC_TX_SNIFF = 0x6, 2014 MLXCX_FLOW_TABLE_NIC_RX_RDMA = 0x7, 2015 MLXCX_FLOW_TABLE_NIC_TX_RDMA = 0x8 2016 } mlxcx_flow_table_type_t; 2017 2018 typedef struct { 2019 mlxcx_cmd_in_t mlxi_create_flow_table_head; 2020 uint8_t mlxi_create_flow_table_other_vport; 2021 uint8_t mlxi_create_flow_table_rsvd; 2022 uint16be_t mlxi_create_flow_table_vport_number; 2023 uint8_t mlxi_create_flow_table_rsvd2[4]; 2024 uint8_t mlxi_create_flow_table_table_type; 2025 uint8_t mlxi_create_flow_table_rsvd3[7]; 2026 mlxcx_flow_table_ctx_t mlxi_create_flow_table_context; 2027 } mlxcx_cmd_create_flow_table_in_t; 2028 2029 typedef struct { 2030 mlxcx_cmd_out_t mlxo_create_flow_table_head; 2031 uint8_t mlxo_create_flow_table_rsvd; 2032 uint24be_t mlxo_create_flow_table_table_id; 2033 uint8_t mlxo_create_flow_table_rsvd2[4]; 2034 } mlxcx_cmd_create_flow_table_out_t; 2035 2036 typedef struct { 2037 mlxcx_cmd_in_t mlxi_destroy_flow_table_head; 2038 uint8_t mlxi_destroy_flow_table_other_vport; 2039 uint8_t mlxi_destroy_flow_table_rsvd; 2040 uint16be_t mlxi_destroy_flow_table_vport_number; 2041 uint8_t mlxi_destroy_flow_table_rsvd2[4]; 2042 uint8_t mlxi_destroy_flow_table_table_type; 2043 uint8_t mlxi_destroy_flow_table_rsvd3[4]; 2044 uint24be_t mlxi_destroy_flow_table_table_id; 2045 uint8_t mlxi_destroy_flow_table_rsvd4[4]; 2046 } mlxcx_cmd_destroy_flow_table_in_t; 2047 2048 typedef struct { 2049 mlxcx_cmd_out_t mlxo_destroy_flow_table_head; 2050 uint8_t mlxo_destroy_flow_table_rsvd[8]; 2051 } mlxcx_cmd_destroy_flow_table_out_t; 2052 2053 typedef struct { 2054 mlxcx_cmd_in_t mlxi_set_flow_table_root_head; 2055 uint8_t mlxi_set_flow_table_root_other_vport; 2056 uint8_t mlxi_set_flow_table_root_rsvd; 2057 uint16be_t mlxi_set_flow_table_root_vport_number; 2058 uint8_t mlxi_set_flow_table_root_rsvd2[4]; 2059 uint8_t mlxi_set_flow_table_root_table_type; 2060 uint8_t mlxi_set_flow_table_root_rsvd3[4]; 2061 uint24be_t mlxi_set_flow_table_root_table_id; 2062 uint8_t mlxi_set_flow_table_root_rsvd4[4]; 2063 } mlxcx_cmd_set_flow_table_root_in_t; 2064 2065 typedef struct { 2066 mlxcx_cmd_out_t mlxo_set_flow_table_root_head; 2067 uint8_t mlxo_set_flow_table_root_rsvd[8]; 2068 } mlxcx_cmd_set_flow_table_root_out_t; 2069 2070 typedef enum { 2071 MLXCX_FLOW_GROUP_MATCH_OUTER_HDRS = 1 << 0, 2072 MLXCX_FLOW_GROUP_MATCH_MISC_PARAMS = 1 << 1, 2073 MLXCX_FLOW_GROUP_MATCH_INNER_HDRS = 1 << 2, 2074 } mlxcx_flow_group_match_criteria_t; 2075 2076 typedef struct { 2077 mlxcx_cmd_in_t mlxi_create_flow_group_head; 2078 uint8_t mlxi_create_flow_group_other_vport; 2079 uint8_t mlxi_create_flow_group_rsvd; 2080 uint16be_t mlxi_create_flow_group_vport_number; 2081 uint8_t mlxi_create_flow_group_rsvd2[4]; 2082 uint8_t mlxi_create_flow_group_table_type; 2083 uint8_t mlxi_create_flow_group_rsvd3[4]; 2084 uint24be_t mlxi_create_flow_group_table_id; 2085 uint8_t mlxi_create_flow_group_rsvd4[4]; 2086 uint32be_t mlxi_create_flow_group_start_flow_index; 2087 uint8_t mlxi_create_flow_group_rsvd5[4]; 2088 uint32be_t mlxi_create_flow_group_end_flow_index; 2089 uint8_t mlxi_create_flow_group_rsvd6[23]; 2090 uint8_t mlxi_create_flow_group_match_criteria_en; 2091 mlxcx_flow_match_t mlxi_create_flow_group_match_criteria; 2092 uint8_t mlxi_create_flow_group_rsvd7[448]; 2093 } mlxcx_cmd_create_flow_group_in_t; 2094 2095 typedef struct { 2096 mlxcx_cmd_out_t mlxo_create_flow_group_head; 2097 uint8_t mlxo_create_flow_group_rsvd; 2098 uint24be_t mlxo_create_flow_group_group_id; 2099 uint8_t mlxo_create_flow_group_rsvd2[4]; 2100 } mlxcx_cmd_create_flow_group_out_t; 2101 2102 typedef struct { 2103 mlxcx_cmd_in_t mlxi_destroy_flow_group_head; 2104 uint8_t mlxi_destroy_flow_group_other_vport; 2105 uint8_t mlxi_destroy_flow_group_rsvd; 2106 uint16be_t mlxi_destroy_flow_group_vport_number; 2107 uint8_t mlxi_destroy_flow_group_rsvd2[4]; 2108 uint8_t mlxi_destroy_flow_group_table_type; 2109 uint8_t mlxi_destroy_flow_group_rsvd3[4]; 2110 uint24be_t mlxi_destroy_flow_group_table_id; 2111 uint32be_t mlxi_destroy_flow_group_group_id; 2112 uint8_t mlxi_destroy_flow_group_rsvd4[36]; 2113 } mlxcx_cmd_destroy_flow_group_in_t; 2114 2115 typedef struct { 2116 mlxcx_cmd_out_t mlxo_destroy_flow_group_head; 2117 uint8_t mlxo_destroy_flow_group_rsvd[8]; 2118 } mlxcx_cmd_destroy_flow_group_out_t; 2119 2120 typedef enum { 2121 MLXCX_CMD_FLOW_ENTRY_SET_NEW = 0, 2122 MLXCX_CMD_FLOW_ENTRY_MODIFY = 1, 2123 } mlxcx_cmd_set_flow_table_entry_opmod_t; 2124 2125 typedef enum { 2126 MLXCX_CMD_FLOW_ENTRY_SET_ACTION = 1 << 0, 2127 MLXCX_CMD_FLOW_ENTRY_SET_FLOW_TAG = 1 << 1, 2128 MLXCX_CMD_FLOW_ENTRY_SET_DESTINATION = 1 << 2, 2129 MLXCX_CMD_FLOW_ENTRY_SET_COUNTERS = 1 << 3, 2130 MLXCX_CMD_FLOW_ENTRY_SET_ENCAP = 1 << 4 2131 } mlxcx_cmd_set_flow_table_entry_bitmask_t; 2132 2133 typedef struct { 2134 mlxcx_cmd_in_t mlxi_set_flow_table_entry_head; 2135 uint8_t mlxi_set_flow_table_entry_other_vport; 2136 uint8_t mlxi_set_flow_table_entry_rsvd; 2137 uint16be_t mlxi_set_flow_table_entry_vport_number; 2138 uint8_t mlxi_set_flow_table_entry_rsvd2[4]; 2139 uint8_t mlxi_set_flow_table_entry_table_type; 2140 uint8_t mlxi_set_flow_table_entry_rsvd3[4]; 2141 uint24be_t mlxi_set_flow_table_entry_table_id; 2142 uint8_t mlxi_set_flow_table_entry_rsvd4[3]; 2143 bits8_t mlxi_set_flow_table_entry_modify_bitmask; 2144 uint8_t mlxi_set_flow_table_entry_rsvd5[4]; 2145 uint32be_t mlxi_set_flow_table_entry_flow_index; 2146 uint8_t mlxi_set_flow_table_entry_rsvd6[28]; 2147 mlxcx_flow_entry_ctx_t mlxi_set_flow_table_entry_context; 2148 } mlxcx_cmd_set_flow_table_entry_in_t; 2149 2150 typedef struct { 2151 mlxcx_cmd_out_t mlxo_set_flow_table_entry_head; 2152 uint8_t mlxo_set_flow_table_entry_rsvd[8]; 2153 } mlxcx_cmd_set_flow_table_entry_out_t; 2154 2155 typedef struct { 2156 mlxcx_cmd_in_t mlxi_delete_flow_table_entry_head; 2157 uint8_t mlxi_delete_flow_table_entry_other_vport; 2158 uint8_t mlxi_delete_flow_table_entry_rsvd; 2159 uint16be_t mlxi_delete_flow_table_entry_vport_number; 2160 uint8_t mlxi_delete_flow_table_entry_rsvd2[4]; 2161 uint8_t mlxi_delete_flow_table_entry_table_type; 2162 uint8_t mlxi_delete_flow_table_entry_rsvd3[4]; 2163 uint24be_t mlxi_delete_flow_table_entry_table_id; 2164 uint8_t mlxi_delete_flow_table_entry_rsvd4[8]; 2165 uint32be_t mlxi_delete_flow_table_entry_flow_index; 2166 uint8_t mlxi_delete_flow_table_entry_rsvd5[28]; 2167 } mlxcx_cmd_delete_flow_table_entry_in_t; 2168 2169 typedef struct { 2170 mlxcx_cmd_out_t mlxo_delete_flow_table_entry_head; 2171 uint8_t mlxo_delete_flow_table_entry_rsvd[8]; 2172 } mlxcx_cmd_delete_flow_table_entry_out_t; 2173 2174 typedef enum { 2175 MLXCX_CMD_CONFIG_INT_MOD_READ = 1, 2176 MLXCX_CMD_CONFIG_INT_MOD_WRITE = 0 2177 } mlxcx_cmd_config_int_mod_opmod_t; 2178 2179 typedef struct { 2180 mlxcx_cmd_in_t mlxi_config_int_mod_head; 2181 uint16be_t mlxi_config_int_mod_min_delay; 2182 uint16be_t mlxi_config_int_mod_int_vector; 2183 uint8_t mlxi_config_int_mod_rsvd[4]; 2184 } mlxcx_cmd_config_int_mod_in_t; 2185 2186 typedef struct { 2187 mlxcx_cmd_out_t mlxo_config_int_mod_head; 2188 uint16be_t mlxo_config_int_mod_min_delay; 2189 uint16be_t mlxo_config_int_mod_int_vector; 2190 uint8_t mlxo_config_int_mod_rsvd[4]; 2191 } mlxcx_cmd_config_int_mod_out_t; 2192 2193 typedef struct { 2194 uint8_t mlrd_pmtu_rsvd; 2195 uint8_t mlrd_pmtu_local_port; 2196 uint8_t mlrd_pmtu_rsvd2[2]; 2197 2198 uint16be_t mlrd_pmtu_max_mtu; 2199 uint8_t mlrd_pmtu_rsvd3[2]; 2200 2201 uint16be_t mlrd_pmtu_admin_mtu; 2202 uint8_t mlrd_pmtu_rsvd4[2]; 2203 2204 uint16be_t mlrd_pmtu_oper_mtu; 2205 uint8_t mlrd_pmtu_rsvd5[2]; 2206 } mlxcx_reg_pmtu_t; 2207 2208 typedef enum { 2209 MLXCX_PORT_STATUS_UP = 1, 2210 MLXCX_PORT_STATUS_DOWN = 2, 2211 MLXCX_PORT_STATUS_UP_ONCE = 3, 2212 MLXCX_PORT_STATUS_DISABLED = 4, 2213 } mlxcx_port_status_t; 2214 2215 typedef enum { 2216 MLXCX_PAOS_ADMIN_ST_EN = 1UL << 31, 2217 } mlxcx_paos_flags_t; 2218 2219 typedef struct { 2220 uint8_t mlrd_paos_swid; 2221 uint8_t mlrd_paos_local_port; 2222 uint8_t mlrd_paos_admin_status; 2223 uint8_t mlrd_paos_oper_status; 2224 bits32_t mlrd_paos_flags; 2225 uint8_t mlrd_paos_rsvd[8]; 2226 } mlxcx_reg_paos_t; 2227 2228 typedef enum { 2229 MLXCX_PROTO_SGMII = 1 << 0, 2230 MLXCX_PROTO_1000BASE_KX = 1 << 1, 2231 MLXCX_PROTO_10GBASE_CX4 = 1 << 2, 2232 MLXCX_PROTO_10GBASE_KX4 = 1 << 3, 2233 MLXCX_PROTO_10GBASE_KR = 1 << 4, 2234 MLXCX_PROTO_UNKNOWN_1 = 1 << 5, 2235 MLXCX_PROTO_40GBASE_CR4 = 1 << 6, 2236 MLXCX_PROTO_40GBASE_KR4 = 1 << 7, 2237 MLXCX_PROTO_UNKNOWN_2 = 1 << 8, 2238 MLXCX_PROTO_SGMII_100BASE = 1 << 9, 2239 MLXCX_PROTO_UNKNOWN_3 = 1 << 10, 2240 MLXCX_PROTO_UNKNOWN_4 = 1 << 11, 2241 MLXCX_PROTO_10GBASE_CR = 1 << 12, 2242 MLXCX_PROTO_10GBASE_SR = 1 << 13, 2243 MLXCX_PROTO_10GBASE_ER_LR = 1 << 14, 2244 MLXCX_PROTO_40GBASE_SR4 = 1 << 15, 2245 MLXCX_PROTO_40GBASE_LR4_ER4 = 1 << 16, 2246 MLXCX_PROTO_UNKNOWN_5 = 1 << 17, 2247 MLXCX_PROTO_50GBASE_SR2 = 1 << 18, 2248 MLXCX_PROTO_UNKNOWN_6 = 1 << 19, 2249 MLXCX_PROTO_100GBASE_CR4 = 1 << 20, 2250 MLXCX_PROTO_100GBASE_SR4 = 1 << 21, 2251 MLXCX_PROTO_100GBASE_KR4 = 1 << 22, 2252 MLXCX_PROTO_UNKNOWN_7 = 1 << 23, 2253 MLXCX_PROTO_UNKNOWN_8 = 1 << 24, 2254 MLXCX_PROTO_UNKNOWN_9 = 1 << 25, 2255 MLXCX_PROTO_UNKNOWN_10 = 1 << 26, 2256 MLXCX_PROTO_25GBASE_CR = 1 << 27, 2257 MLXCX_PROTO_25GBASE_KR = 1 << 28, 2258 MLXCX_PROTO_25GBASE_SR = 1 << 29, 2259 MLXCX_PROTO_50GBASE_CR2 = 1 << 30, 2260 MLXCX_PROTO_50GBASE_KR2 = 1UL << 31, 2261 } mlxcx_eth_proto_t; 2262 2263 #define MLXCX_PROTO_100M MLXCX_PROTO_SGMII_100BASE 2264 2265 #define MLXCX_PROTO_1G (MLXCX_PROTO_1000BASE_KX | MLXCX_PROTO_SGMII) 2266 2267 #define MLXCX_PROTO_10G (MLXCX_PROTO_10GBASE_CX4 | \ 2268 MLXCX_PROTO_10GBASE_KX4 | MLXCX_PROTO_10GBASE_KR | \ 2269 MLXCX_PROTO_10GBASE_CR | MLXCX_PROTO_10GBASE_SR | \ 2270 MLXCX_PROTO_10GBASE_ER_LR) 2271 2272 #define MLXCX_PROTO_25G (MLXCX_PROTO_25GBASE_CR | \ 2273 MLXCX_PROTO_25GBASE_KR | MLXCX_PROTO_25GBASE_SR) 2274 2275 #define MLXCX_PROTO_40G (MLXCX_PROTO_40GBASE_SR4 | \ 2276 MLXCX_PROTO_40GBASE_LR4_ER4 | MLXCX_PROTO_40GBASE_CR4 | \ 2277 MLXCX_PROTO_40GBASE_KR4) 2278 2279 #define MLXCX_PROTO_50G (MLXCX_PROTO_50GBASE_CR2 | \ 2280 MLXCX_PROTO_50GBASE_KR2 | MLXCX_PROTO_50GBASE_SR2) 2281 2282 #define MLXCX_PROTO_100G (MLXCX_PROTO_100GBASE_CR4 | \ 2283 MLXCX_PROTO_100GBASE_SR4 | MLXCX_PROTO_100GBASE_KR4) 2284 2285 typedef enum { 2286 MLXCX_AUTONEG_DISABLE_CAP = 1 << 5, 2287 MLXCX_AUTONEG_DISABLE = 1 << 6 2288 } mlxcx_autoneg_flags_t; 2289 2290 typedef enum { 2291 MLXCX_PTYS_PROTO_MASK_IB = 1 << 0, 2292 MLXCX_PTYS_PROTO_MASK_ETH = 1 << 2, 2293 } mlxcx_reg_ptys_proto_mask_t; 2294 2295 typedef struct { 2296 bits8_t mlrd_ptys_autoneg_flags; 2297 uint8_t mlrd_ptys_local_port; 2298 uint8_t mlrd_ptys_rsvd; 2299 bits8_t mlrd_ptys_proto_mask; 2300 2301 bits8_t mlrd_ptys_autoneg_status; 2302 uint8_t mlrd_ptys_rsvd2; 2303 uint16be_t mlrd_ptys_data_rate_oper; 2304 2305 uint8_t mlrd_ptys_rsvd3[4]; 2306 2307 bits32_t mlrd_ptys_proto_cap; 2308 uint8_t mlrd_ptys_rsvd4[8]; 2309 bits32_t mlrd_ptys_proto_admin; 2310 uint8_t mlrd_ptys_rsvd5[8]; 2311 bits32_t mlrd_ptys_proto_oper; 2312 uint8_t mlrd_ptys_rsvd6[8]; 2313 bits32_t mlrd_ptys_proto_partner_advert; 2314 uint8_t mlrd_ptys_rsvd7[12]; 2315 } mlxcx_reg_ptys_t; 2316 2317 typedef enum { 2318 MLXCX_LED_TYPE_BOTH = 0x0, 2319 MLXCX_LED_TYPE_UID = 0x1, 2320 MLXCX_LED_TYPE_PORT = 0x2, 2321 } mlxcx_led_type_t; 2322 2323 #define MLXCX_MLCR_INDIVIDUAL_ONLY (1 << 4) 2324 /* CSTYLED */ 2325 #define MLXCX_MLCR_LED_TYPE (bitdef_t){ 0, 0x0F } 2326 2327 typedef struct { 2328 uint8_t mlrd_mlcr_rsvd; 2329 uint8_t mlrd_mlcr_local_port; 2330 uint8_t mlrd_mlcr_rsvd2; 2331 bits8_t mlrd_mlcr_flags; 2332 uint8_t mlrd_mlcr_rsvd3[2]; 2333 uint16be_t mlrd_mlcr_beacon_duration; 2334 uint8_t mlrd_mlcr_rsvd4[2]; 2335 uint16be_t mlrd_mlcr_beacon_remain; 2336 } mlxcx_reg_mlcr_t; 2337 2338 typedef struct { 2339 uint8_t mlrd_pmaos_rsvd; 2340 uint8_t mlrd_pmaos_module; 2341 uint8_t mlrd_pmaos_admin_status; 2342 uint8_t mlrd_pmaos_oper_status; 2343 bits8_t mlrd_pmaos_flags; 2344 uint8_t mlrd_pmaos_rsvd2; 2345 uint8_t mlrd_pmaos_error_type; 2346 uint8_t mlrd_pmaos_event_en; 2347 uint8_t mlrd_pmaos_rsvd3[8]; 2348 } mlxcx_reg_pmaos_t; 2349 2350 typedef enum { 2351 MLXCX_MCIA_STATUS_OK = 0x0, 2352 MLXCX_MCIA_STATUS_NO_EEPROM = 0x1, 2353 MLXCX_MCIA_STATUS_NOT_SUPPORTED = 0x2, 2354 MLXCX_MCIA_STATUS_NOT_CONNECTED = 0x3, 2355 MLXCX_MCIA_STATUS_I2C_ERROR = 0x9, 2356 MLXCX_MCIA_STATUS_DISABLED = 0x10 2357 } mlxcx_mcia_status_t; 2358 2359 typedef struct { 2360 bits8_t mlrd_mcia_flags; 2361 uint8_t mlrd_mcia_module; 2362 uint8_t mlrd_mcia_rsvd; 2363 uint8_t mlrd_mcia_status; 2364 uint8_t mlrd_mcia_i2c_device_addr; 2365 uint8_t mlrd_mcia_page_number; 2366 uint16be_t mlrd_mcia_device_addr; 2367 uint8_t mlrd_mcia_rsvd2[2]; 2368 uint16be_t mlrd_mcia_size; 2369 uint8_t mlrd_mcia_rsvd3[4]; 2370 uint8_t mlrd_mcia_data[48]; 2371 } mlxcx_reg_mcia_t; 2372 2373 typedef struct { 2374 uint64be_t mlppc_ieee_802_3_frames_tx; 2375 uint64be_t mlppc_ieee_802_3_frames_rx; 2376 uint64be_t mlppc_ieee_802_3_fcs_err; 2377 uint64be_t mlppc_ieee_802_3_align_err; 2378 uint64be_t mlppc_ieee_802_3_bytes_tx; 2379 uint64be_t mlppc_ieee_802_3_bytes_rx; 2380 uint64be_t mlppc_ieee_802_3_mcast_tx; 2381 uint64be_t mlppc_ieee_802_3_bcast_tx; 2382 uint64be_t mlppc_ieee_802_3_mcast_rx; 2383 uint64be_t mlppc_ieee_802_3_bcast_rx; 2384 uint64be_t mlppc_ieee_802_3_in_range_len_err; 2385 uint64be_t mlppc_ieee_802_3_out_of_range_len_err; 2386 uint64be_t mlppc_ieee_802_3_frame_too_long_err; 2387 uint64be_t mlppc_ieee_802_3_symbol_err; 2388 uint64be_t mlppc_ieee_802_3_mac_ctrl_tx; 2389 uint64be_t mlppc_ieee_802_3_mac_ctrl_rx; 2390 uint64be_t mlppc_ieee_802_3_unsup_opcodes_rx; 2391 uint64be_t mlppc_ieee_802_3_pause_rx; 2392 uint64be_t mlppc_ieee_802_3_pause_tx; 2393 } mlxcx_ppcnt_ieee_802_3_t; 2394 2395 typedef struct { 2396 uint64be_t mlppc_rfc_2863_in_octets; 2397 uint64be_t mlppc_rfc_2863_in_ucast_pkts; 2398 uint64be_t mlppc_rfc_2863_in_discards; 2399 uint64be_t mlppc_rfc_2863_in_errors; 2400 uint64be_t mlppc_rfc_2863_in_unknown_protos; 2401 uint64be_t mlppc_rfc_2863_out_octets; 2402 uint64be_t mlppc_rfc_2863_out_ucast_pkts; 2403 uint64be_t mlppc_rfc_2863_out_discards; 2404 uint64be_t mlppc_rfc_2863_out_errors; 2405 uint64be_t mlppc_rfc_2863_in_mcast_pkts; 2406 uint64be_t mlppc_rfc_2863_in_bcast_pkts; 2407 uint64be_t mlppc_rfc_2863_out_mcast_pkts; 2408 uint64be_t mlppc_rfc_2863_out_bcast_pkts; 2409 } mlxcx_ppcnt_rfc_2863_t; 2410 2411 typedef struct { 2412 uint64be_t mlppc_phy_stats_time_since_last_clear; 2413 uint64be_t mlppc_phy_stats_rx_bits; 2414 uint64be_t mlppc_phy_stats_symbol_errs; 2415 uint64be_t mlppc_phy_stats_corrected_bits; 2416 uint8_t mlppc_phy_stats_rsvd[2]; 2417 uint8_t mlppc_phy_stats_raw_ber_mag; 2418 uint8_t mlppc_phy_stats_raw_ber_coef; 2419 uint8_t mlppc_phy_stats_rsvd2[2]; 2420 uint8_t mlppc_phy_stats_eff_ber_mag; 2421 uint8_t mlppc_phy_stats_eff_ber_coef; 2422 } mlxcx_ppcnt_phy_stats_t; 2423 2424 typedef enum { 2425 MLXCX_PPCNT_GRP_IEEE_802_3 = 0x0, 2426 MLXCX_PPCNT_GRP_RFC_2863 = 0x1, 2427 MLXCX_PPCNT_GRP_RFC_2819 = 0x2, 2428 MLXCX_PPCNT_GRP_RFC_3635 = 0x3, 2429 MLXCX_PPCNT_GRP_ETH_EXTD = 0x5, 2430 MLXCX_PPCNT_GRP_ETH_DISCARD = 0x6, 2431 MLXCX_PPCNT_GRP_PER_PRIO = 0x10, 2432 MLXCX_PPCNT_GRP_PER_TC = 0x11, 2433 MLXCX_PPCNT_GRP_PER_TC_CONGEST = 0x13, 2434 MLXCX_PPCNT_GRP_PHY_STATS = 0x16 2435 } mlxcx_ppcnt_grp_t; 2436 2437 typedef enum { 2438 MLXCX_PPCNT_CLEAR = (1 << 7), 2439 MLXCX_PPCNT_NO_CLEAR = 0 2440 } mlxcx_ppcnt_clear_t; 2441 2442 typedef struct { 2443 uint8_t mlrd_ppcnt_swid; 2444 uint8_t mlrd_ppcnt_local_port; 2445 uint8_t mlrd_ppcnt_pnat; 2446 uint8_t mlrd_ppcnt_grp; 2447 uint8_t mlrd_ppcnt_clear; 2448 uint8_t mlrd_ppcnt_rsvd[2]; 2449 uint8_t mlrd_ppcnt_prio_tc; 2450 union { 2451 uint8_t mlrd_ppcnt_data[248]; 2452 mlxcx_ppcnt_ieee_802_3_t mlrd_ppcnt_ieee_802_3; 2453 mlxcx_ppcnt_rfc_2863_t mlrd_ppcnt_rfc_2863; 2454 mlxcx_ppcnt_phy_stats_t mlrd_ppcnt_phy_stats; 2455 }; 2456 } mlxcx_reg_ppcnt_t; 2457 2458 typedef enum { 2459 MLXCX_REG_PMTU = 0x5003, 2460 MLXCX_REG_PTYS = 0x5004, 2461 MLXCX_REG_PAOS = 0x5006, 2462 MLXCX_REG_PMAOS = 0x5012, 2463 MLXCX_REG_MSGI = 0x9021, 2464 MLXCX_REG_MLCR = 0x902B, 2465 MLXCX_REG_MCIA = 0x9014, 2466 MLXCX_REG_PPCNT = 0x5008, 2467 } mlxcx_register_id_t; 2468 2469 typedef union { 2470 mlxcx_reg_pmtu_t mlrd_pmtu; 2471 mlxcx_reg_paos_t mlrd_paos; 2472 mlxcx_reg_ptys_t mlrd_ptys; 2473 mlxcx_reg_mlcr_t mlrd_mlcr; 2474 mlxcx_reg_pmaos_t mlrd_pmaos; 2475 mlxcx_reg_mcia_t mlrd_mcia; 2476 mlxcx_reg_ppcnt_t mlrd_ppcnt; 2477 } mlxcx_register_data_t; 2478 2479 typedef enum { 2480 MLXCX_CMD_ACCESS_REGISTER_READ = 1, 2481 MLXCX_CMD_ACCESS_REGISTER_WRITE = 0 2482 } mlxcx_cmd_reg_opmod_t; 2483 2484 typedef struct { 2485 mlxcx_cmd_in_t mlxi_access_register_head; 2486 uint8_t mlxi_access_register_rsvd[2]; 2487 uint16be_t mlxi_access_register_register_id; 2488 uint32be_t mlxi_access_register_argument; 2489 mlxcx_register_data_t mlxi_access_register_data; 2490 } mlxcx_cmd_access_register_in_t; 2491 2492 typedef struct { 2493 mlxcx_cmd_out_t mlxo_access_register_head; 2494 uint8_t mlxo_access_register_rsvd[8]; 2495 mlxcx_register_data_t mlxo_access_register_data; 2496 } mlxcx_cmd_access_register_out_t; 2497 2498 #pragma pack() 2499 2500 #ifdef __cplusplus 2501 } 2502 #endif 2503 2504 #endif /* _MLXCX_REG_H */ 2505