1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2020, The University of Queensland 14 * Copyright (c) 2018, Joyent, Inc. 15 * Copyright 2020 RackTop Systems, Inc. 16 */ 17 18 #ifndef _MLXCX_REG_H 19 #define _MLXCX_REG_H 20 21 #include <sys/types.h> 22 #include <sys/byteorder.h> 23 24 #include <mlxcx_endint.h> 25 26 #if !defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) 27 #error "Need _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH" 28 #endif 29 30 /* 31 * Register offsets. 32 */ 33 34 #define MLXCX_ISS_FIRMWARE 0x0000 35 #define MLXCX_ISS_FW_MAJOR(x) (((x) & 0xffff)) 36 #define MLXCX_ISS_FW_MINOR(x) (((x) >> 16) & 0xffff) 37 #define MLXCX_ISS_FW_CMD 0x0004 38 #define MLXCX_ISS_FW_REV(x) (((x) & 0xffff)) 39 #define MLXCX_ISS_CMD_REV(x) (((x) >> 16) & 0xffff) 40 #define MLXCX_ISS_CMD_HIGH 0x0010 41 #define MLXCX_ISS_CMD_LOW 0x0014 42 #define MLXCX_ISS_CMDQ_SIZE(x) (((x) >> 4) & 0xf) 43 #define MLXCX_ISS_CMDQ_STRIDE(x) ((x) & 0xf) 44 45 #define MLXCX_ISS_CMD_DOORBELL 0x0018 46 #define MLXCX_ISS_INIT 0x01fc 47 #define MLXCX_ISS_INITIALIZING(x) (((x) >> 31) & 0x1) 48 #define MLXCX_ISS_HEALTH_BUF 0x0200 49 #define MLXCX_ISS_NO_DRAM_NIC 0x0240 50 #define MLXCX_ISS_TIMER 0x1000 51 #define MLXCX_ISS_HEALTH_COUNT 0x1010 52 #define MLXCX_ISS_HEALTH_SYND 0x1013 53 54 #define MLXCX_CMD_INLINE_INPUT_LEN 16 55 #define MLXCX_CMD_INLINE_OUTPUT_LEN 16 56 57 #define MLXCX_CMD_MAILBOX_LEN 512 58 59 #define MLXCX_CMD_TRANSPORT_PCI 7 60 #define MLXCX_CMD_HW_OWNED 0x01 61 #define MLXCX_CMD_STATUS(x) ((x) >> 1) 62 63 /* 64 * You can't have more commands pending, than bit size of a doorbell 65 */ 66 #define MLXCX_CMD_MAX (sizeof (uint32_t) * NBBY) 67 68 #define MLXCX_UAR_CQ_ARM 0x0020 69 #define MLXCX_UAR_EQ_ARM 0x0040 70 #define MLXCX_UAR_EQ_NOARM 0x0048 71 72 /* Number of blue flame reg pairs per UAR */ 73 #define MLXCX_BF_PER_UAR 2 74 #define MLXCX_BF_PER_UAR_MASK 0x1 75 #define MLXCX_BF_SIZE 0x100 76 #define MLXCX_BF_BASE 0x0800 77 78 /* CSTYLED */ 79 #define MLXCX_EQ_ARM_EQN (bitdef_t){24, 0xff000000} 80 /* CSTYLED */ 81 #define MLXCX_EQ_ARM_CI (bitdef_t){0, 0x00ffffff} 82 83 /* 84 * Hardware structure that is used to represent a command. 85 */ 86 #pragma pack(1) 87 typedef struct { 88 uint8_t mce_type; 89 uint8_t mce_rsvd[3]; 90 uint32be_t mce_in_length; 91 uint64be_t mce_in_mbox; 92 uint8_t mce_input[MLXCX_CMD_INLINE_INPUT_LEN]; 93 uint8_t mce_output[MLXCX_CMD_INLINE_OUTPUT_LEN]; 94 uint64be_t mce_out_mbox; 95 uint32be_t mce_out_length; 96 uint8_t mce_token; 97 uint8_t mce_sig; 98 uint8_t mce_rsvd1; 99 uint8_t mce_status; 100 } mlxcx_cmd_ent_t; 101 102 typedef struct { 103 uint8_t mlxb_data[MLXCX_CMD_MAILBOX_LEN]; 104 uint8_t mlxb_rsvd[48]; 105 uint64be_t mlxb_nextp; 106 uint32be_t mlxb_blockno; 107 uint8_t mlxb_rsvd1; 108 uint8_t mlxb_token; 109 uint8_t mlxb_ctrl_sig; 110 uint8_t mlxb_sig; 111 } mlxcx_cmd_mailbox_t; 112 113 typedef struct { 114 uint8_t mled_page_request_rsvd[2]; 115 uint16be_t mled_page_request_function_id; 116 uint32be_t mled_page_request_num_pages; 117 } mlxcx_evdata_page_request_t; 118 119 /* CSTYLED */ 120 #define MLXCX_EVENT_PORT_NUM (bitdef_t){ .bit_shift = 4, .bit_mask = 0xF0 } 121 122 typedef struct { 123 uint8_t mled_port_state_rsvd[8]; 124 bits8_t mled_port_state_port_num; 125 } mlxcx_evdata_port_state_t; 126 127 typedef enum { 128 MLXCX_MODULE_INITIALIZING = 0x0, 129 MLXCX_MODULE_PLUGGED = 0x1, 130 MLXCX_MODULE_UNPLUGGED = 0x2, 131 MLXCX_MODULE_ERROR = 0x3 132 } mlxcx_module_status_t; 133 134 typedef enum { 135 MLXCX_MODULE_ERR_POWER_BUDGET = 0x0, 136 MLXCX_MODULE_ERR_LONG_RANGE = 0x1, 137 MLXCX_MODULE_ERR_BUS_STUCK = 0x2, 138 MLXCX_MODULE_ERR_NO_EEPROM = 0x3, 139 MLXCX_MODULE_ERR_ENFORCEMENT = 0x4, 140 MLXCX_MODULE_ERR_UNKNOWN_IDENT = 0x5, 141 MLXCX_MODULE_ERR_HIGH_TEMP = 0x6, 142 MLXCX_MODULE_ERR_CABLE_SHORTED = 0x7, 143 } mlxcx_module_error_type_t; 144 145 typedef struct { 146 uint8_t mled_port_mod_rsvd; 147 uint8_t mled_port_mod_module; 148 uint8_t mled_port_mod_rsvd2; 149 uint8_t mled_port_mod_module_status; 150 uint8_t mled_port_mod_rsvd3[2]; 151 uint8_t mled_port_mod_error_type; 152 uint8_t mled_port_mod_rsvd4; 153 } mlxcx_evdata_port_mod_t; 154 155 typedef struct { 156 uint8_t mled_completion_rsvd[25]; 157 uint24be_t mled_completion_cqn; 158 } mlxcx_evdata_completion_t; 159 160 typedef struct { 161 uint32be_t mled_cmd_completion_vec; 162 uint8_t mled_cmd_completion_rsvd[24]; 163 } mlxcx_evdata_cmd_completion_t; 164 165 typedef enum { 166 MLXCX_EV_QUEUE_TYPE_QP = 0x0, 167 MLXCX_EV_QUEUE_TYPE_RQ = 0x1, 168 MLXCX_EV_QUEUE_TYPE_SQ = 0x2, 169 } mlxcx_evdata_queue_type_t; 170 171 typedef struct { 172 uint8_t mled_queue_rsvd[20]; 173 uint8_t mled_queue_type; 174 uint8_t mled_queue_rsvd2[4]; 175 uint24be_t mled_queue_num; 176 } mlxcx_evdata_queue_t; 177 178 #define MLXCX_EQ_OWNER_INIT 1 179 180 typedef struct { 181 uint8_t mleqe_rsvd[1]; 182 uint8_t mleqe_event_type; 183 uint8_t mleqe_rsvd2[1]; 184 uint8_t mleqe_event_sub_type; 185 uint8_t mleqe_rsvd3[28]; 186 union { 187 uint8_t mleqe_unknown_data[28]; 188 mlxcx_evdata_cmd_completion_t mleqe_cmd_completion; 189 mlxcx_evdata_completion_t mleqe_completion; 190 mlxcx_evdata_page_request_t mleqe_page_request; 191 mlxcx_evdata_port_state_t mleqe_port_state; 192 mlxcx_evdata_port_mod_t mleqe_port_mod; 193 mlxcx_evdata_queue_t mleqe_queue; 194 }; 195 uint8_t mleqe_rsvd4[2]; 196 uint8_t mleqe_signature; 197 uint8_t mleqe_owner; 198 } mlxcx_eventq_ent_t; 199 200 typedef enum { 201 MLXCX_CQE_L3_HDR_NONE = 0x0, 202 MLXCX_CQE_L3_HDR_RCV_BUF = 0x1, 203 MLXCX_CQE_L3_HDR_CQE = 0x2, 204 } mlxcx_cqe_l3_hdr_placement_t; 205 206 typedef enum { 207 MLXCX_CQE_CSFLAGS_L4_OK = 1 << 2, 208 MLXCX_CQE_CSFLAGS_L3_OK = 1 << 1, 209 MLXCX_CQE_CSFLAGS_L2_OK = 1 << 0, 210 } mlxcx_cqe_csflags_t; 211 212 typedef enum { 213 MLXCX_CQE_L4_TYPE_NONE = 0, 214 MLXCX_CQE_L4_TYPE_TCP = 1, 215 MLXCX_CQE_L4_TYPE_UDP = 2, 216 MLXCX_CQE_L4_TYPE_TCP_EMPTY_ACK = 3, 217 MLXCX_CQE_L4_TYPE_TCP_ACK = 4, 218 } mlxcx_cqe_l4_hdr_type_t; 219 220 typedef enum { 221 MLXCX_CQE_L3_TYPE_NONE = 0, 222 MLXCX_CQE_L3_TYPE_IPv6 = 1, 223 MLXCX_CQE_L3_TYPE_IPv4 = 2, 224 } mlxcx_cqe_l3_hdr_type_t; 225 226 typedef enum { 227 MLXCX_CQE_RX_HASH_NONE = 0, 228 MLXCX_CQE_RX_HASH_IPv4 = 1, 229 MLXCX_CQE_RX_HASH_IPv6 = 2, 230 MLXCX_CQE_RX_HASH_IPSEC_SPI = 3, 231 } mlxcx_cqe_rx_hash_type_t; 232 /* BEGIN CSTYLED */ 233 #define MLXCX_CQE_RX_HASH_IP_SRC (bitdef_t){0, 0x3} 234 #define MLXCX_CQE_RX_HASH_IP_DEST (bitdef_t){2, (0x3 << 2)} 235 #define MLXCX_CQE_RX_HASH_L4_SRC (bitdef_t){4, (0x3 << 4)} 236 #define MLXCX_CQE_RX_HASH_L4_DEST (bitdef_t){6, (0x3 << 6)} 237 /* END CSTYLED */ 238 239 typedef enum { 240 MLXCX_CQE_OP_REQ = 0x0, 241 MLXCX_CQE_OP_RESP_RDMA = 0x1, 242 MLXCX_CQE_OP_RESP = 0x2, 243 MLXCX_CQE_OP_RESP_IMMEDIATE = 0x3, 244 MLXCX_CQE_OP_RESP_INVALIDATE = 0x4, 245 MLXCX_CQE_OP_RESIZE_CQ = 0x5, 246 MLXCX_CQE_OP_SIG_ERR = 0x12, 247 MLXCX_CQE_OP_REQ_ERR = 0xd, 248 MLXCX_CQE_OP_RESP_ERR = 0xe, 249 MLXCX_CQE_OP_INVALID = 0xf 250 } mlxcx_cqe_opcode_t; 251 252 typedef enum { 253 MLXCX_CQE_FORMAT_BASIC = 0, 254 MLXCX_CQE_FORMAT_INLINE_32 = 1, 255 MLXCX_CQE_FORMAT_INLINE_64 = 2, 256 MLXCX_CQE_FORMAT_COMPRESSED = 3, 257 } mlxcx_cqe_format_t; 258 259 typedef enum { 260 MLXCX_CQE_OWNER_INIT = 1 261 } mlxcx_cqe_owner_t; 262 263 typedef enum { 264 MLXCX_VLAN_TYPE_NONE, 265 MLXCX_VLAN_TYPE_CVLAN, 266 MLXCX_VLAN_TYPE_SVLAN, 267 } mlxcx_vlan_type_t; 268 269 typedef enum { 270 MLXCX_CQ_ERR_LOCAL_LENGTH = 0x1, 271 MLXCX_CQ_ERR_LOCAL_QP_OP = 0x2, 272 MLXCX_CQ_ERR_LOCAL_PROTECTION = 0x4, 273 MLXCX_CQ_ERR_WR_FLUSHED = 0x5, 274 MLXCX_CQ_ERR_MEM_WINDOW_BIND = 0x6, 275 MLXCX_CQ_ERR_BAD_RESPONSE = 0x10, 276 MLXCX_CQ_ERR_LOCAL_ACCESS = 0x11, 277 MLXCX_CQ_ERR_XPORT_RETRY_CTR = 0x15, 278 MLXCX_CQ_ERR_RNR_RETRY_CTR = 0x16, 279 MLXCX_CQ_ERR_ABORTED = 0x22 280 } mlxcx_cq_error_syndrome_t; 281 282 typedef struct { 283 uint8_t mlcqee_rsvd[2]; 284 uint16be_t mlcqee_wqe_id; 285 uint8_t mlcqee_rsvd2[29]; 286 uint24be_t mlcqee_user_index; 287 uint8_t mlcqee_rsvd3[8]; 288 uint32be_t mlcqee_byte_cnt; 289 uint8_t mlcqee_rsvd4[6]; 290 uint8_t mlcqee_vendor_error_syndrome; 291 uint8_t mlcqee_syndrome; 292 uint8_t mlcqee_wqe_opcode; 293 uint24be_t mlcqee_flow_tag; 294 uint16be_t mlcqee_wqe_counter; 295 uint8_t mlcqee_signature; 296 struct { 297 #if defined(_BIT_FIELDS_HTOL) 298 uint8_t mlcqe_opcode:4; 299 uint8_t mlcqe_rsvd5:3; 300 uint8_t mlcqe_owner:1; 301 #elif defined(_BIT_FIELDS_LTOH) 302 uint8_t mlcqe_owner:1; 303 uint8_t mlcqe_rsvd5:3; 304 uint8_t mlcqe_opcode:4; 305 #endif 306 }; 307 } mlxcx_completionq_error_ent_t; 308 309 typedef struct { 310 uint8_t mlcqe_tunnel_flags; 311 uint8_t mlcqe_rsvd[3]; 312 uint8_t mlcqe_lro_flags; 313 uint8_t mlcqe_lro_min_ttl; 314 uint16be_t mlcqe_lro_tcp_win; 315 uint32be_t mlcqe_lro_ack_seq_num; 316 uint32be_t mlcqe_rx_hash_result; 317 bits8_t mlcqe_rx_hash_type; 318 uint8_t mlcqe_ml_path; 319 uint8_t mlcqe_rsvd2[2]; 320 uint16be_t mlcqe_checksum; 321 uint16be_t mlcqe_slid_smac_lo; 322 struct { 323 #if defined(_BIT_FIELDS_HTOL) 324 uint8_t mlcqe_rsvd3:1; 325 uint8_t mlcqe_force_loopback:1; 326 uint8_t mlcqe_l3_hdr:2; 327 uint8_t mlcqe_sl_roce_pktype:4; 328 #elif defined(_BIT_FIELDS_LTOH) 329 uint8_t mlcqe_sl_roce_pktype:4; 330 uint8_t mlcqe_l3_hdr:2; 331 uint8_t mlcqe_force_loopback:1; 332 uint8_t mlcqe_rsvd3:1; 333 #endif 334 }; 335 uint24be_t mlcqe_rqpn; 336 bits8_t mlcqe_csflags; 337 struct { 338 #if defined(_BIT_FIELDS_HTOL) 339 uint8_t mlcqe_ip_frag:1; 340 uint8_t mlcqe_l4_hdr_type:3; 341 uint8_t mlcqe_l3_hdr_type:2; 342 uint8_t mlcqe_ip_ext_opts:1; 343 uint8_t mlcqe_cv:1; 344 #elif defined(_BIT_FIELDS_LTOH) 345 uint8_t mlcqe_cv:1; 346 uint8_t mlcqe_ip_ext_opts:1; 347 uint8_t mlcqe_l3_hdr_type:2; 348 uint8_t mlcqe_l4_hdr_type:3; 349 uint8_t mlcqe_ip_frag:1; 350 #endif 351 }; 352 uint16be_t mlcqe_up_cfi_vid; 353 uint8_t mlcqe_lro_num_seg; 354 uint24be_t mlcqe_user_index; 355 uint32be_t mlcqe_immediate; 356 uint8_t mlcqe_rsvd4[4]; 357 uint32be_t mlcqe_byte_cnt; 358 union { 359 struct { 360 uint32be_t mlcqe_lro_timestamp_value; 361 uint32be_t mlcqe_lro_timestamp_echo; 362 }; 363 uint64be_t mlcqe_timestamp; 364 }; 365 union { 366 uint8_t mlcqe_rx_drop_counter; 367 uint8_t mlcqe_send_wqe_opcode; 368 }; 369 uint24be_t mlcqe_flow_tag; 370 uint16be_t mlcqe_wqe_counter; 371 uint8_t mlcqe_signature; 372 struct { 373 #if defined(_BIT_FIELDS_HTOL) 374 uint8_t mlcqe_opcode:4; 375 uint8_t mlcqe_format:2; 376 uint8_t mlcqe_se:1; 377 uint8_t mlcqe_owner:1; 378 #elif defined(_BIT_FIELDS_LTOH) 379 uint8_t mlcqe_owner:1; 380 uint8_t mlcqe_se:1; 381 uint8_t mlcqe_format:2; 382 uint8_t mlcqe_opcode:4; 383 #endif 384 }; 385 } mlxcx_completionq_ent_t; 386 387 typedef struct { 388 uint8_t mlcqe_data[64]; 389 mlxcx_completionq_ent_t mlcqe_ent; 390 } mlxcx_completionq_ent128_t; 391 392 typedef enum { 393 MLXCX_WQE_OP_NOP = 0x00, 394 MLXCX_WQE_OP_SEND_INVALIDATE = 0x01, 395 MLXCX_WQE_OP_RDMA_W = 0x08, 396 MLXCX_WQE_OP_RDMA_W_IMMEDIATE = 0x09, 397 MLXCX_WQE_OP_SEND = 0x0A, 398 MLXCX_WQE_OP_SEND_IMMEDIATE = 0x0B, 399 MLXCX_WQE_OP_LSO = 0x0E, 400 MLXCX_WQE_OP_WAIT = 0x0F, 401 MLXCX_WQE_OP_RDMA_R = 0x10, 402 } mlxcx_wqe_opcode_t; 403 404 #define MLXCX_WQE_OCTOWORD 16 405 #define MLXCX_SQE_MAX_DS ((1 << 6) - 1) 406 /* 407 * Calculate the max number of address pointers in a single ethernet 408 * send message. This is the remainder from MLXCX_SQE_MAX_DS 409 * after accounting for the Control and Ethernet segements. 410 */ 411 #define MLXCX_SQE_MAX_PTRS (MLXCX_SQE_MAX_DS - \ 412 (sizeof (mlxcx_wqe_eth_seg_t) + sizeof (mlxcx_wqe_control_seg_t)) / \ 413 MLXCX_WQE_OCTOWORD) 414 415 typedef enum { 416 MLXCX_SQE_FENCE_NONE = 0x0, 417 MLXCX_SQE_FENCE_WAIT_OTHERS = 0x1, 418 MLXCX_SQE_FENCE_START = 0x2, 419 MLXCX_SQE_FENCE_STRONG_ORDER = 0x3, 420 MLXCX_SQE_FENCE_START_WAIT = 0x4 421 } mlxcx_sqe_fence_mode_t; 422 423 typedef enum { 424 MLXCX_SQE_CQE_ON_EACH_ERROR = 0x0, 425 MLXCX_SQE_CQE_ON_FIRST_ERROR = 0x1, 426 MLXCX_SQE_CQE_ALWAYS = 0x2, 427 MLXCX_SQE_CQE_ALWAYS_PLUS_EQE = 0x3 428 } mlxcx_sqe_completion_mode_t; 429 430 #define MLXCX_SQE_SOLICITED (1 << 1) 431 /* CSTYLED */ 432 #define MLXCX_SQE_FENCE_MODE (bitdef_t){5, 0xe0} 433 /* CSTYLED */ 434 #define MLXCX_SQE_COMPLETION_MODE (bitdef_t){2, 0x0c} 435 436 typedef struct { 437 uint8_t mlcs_opcode_mod; 438 uint16be_t mlcs_wqe_index; 439 uint8_t mlcs_opcode; 440 uint24be_t mlcs_qp_or_sq; 441 uint8_t mlcs_ds; 442 uint8_t mlcs_signature; 443 uint8_t mlcs_rsvd2[2]; 444 bits8_t mlcs_flags; 445 uint32be_t mlcs_immediate; 446 } mlxcx_wqe_control_seg_t; 447 448 typedef enum { 449 MLXCX_SQE_ETH_CSFLAG_L4_CHECKSUM = 1 << 7, 450 MLXCX_SQE_ETH_CSFLAG_L3_CHECKSUM = 1 << 6, 451 MLXCX_SQE_ETH_CSFLAG_L4_INNER_CHECKSUM = 1 << 5, 452 MLXCX_SQE_ETH_CSFLAG_L3_INNER_CHECKSUM = 1 << 4, 453 } mlxcx_wqe_eth_flags_t; 454 455 /* CSTYLED */ 456 #define MLXCX_SQE_ETH_INLINE_HDR_SZ (bitdef_t){0, 0x03ff} 457 #define MLXCX_SQE_ETH_SZFLAG_VLAN (1 << 15) 458 #define MLXCX_MAX_INLINE_HEADERLEN 64 459 460 typedef struct { 461 uint8_t mles_rsvd[4]; 462 bits8_t mles_csflags; 463 uint8_t mles_rsvd2[1]; 464 uint16_t mles_mss; 465 uint8_t mles_rsvd3[4]; 466 bits16_t mles_szflags; 467 uint8_t mles_inline_headers[18]; 468 } mlxcx_wqe_eth_seg_t; 469 470 typedef struct { 471 uint32be_t mlds_byte_count; 472 uint32be_t mlds_lkey; 473 uint64be_t mlds_address; 474 } mlxcx_wqe_data_seg_t; 475 476 #define MLXCX_SENDQ_STRIDE_SHIFT 6 477 478 typedef struct { 479 mlxcx_wqe_control_seg_t mlsqe_control; 480 mlxcx_wqe_eth_seg_t mlsqe_eth; 481 mlxcx_wqe_data_seg_t mlsqe_data[1]; 482 } mlxcx_sendq_ent_t; 483 484 typedef struct { 485 uint64be_t mlsqbf_qwords[8]; 486 } mlxcx_sendq_bf_t; 487 488 typedef struct { 489 mlxcx_wqe_data_seg_t mlsqe_data[4]; 490 } mlxcx_sendq_extra_ent_t; 491 492 #define MLXCX_RECVQ_STRIDE_SHIFT 7 493 /* 494 * Each mlxcx_wqe_data_seg_t is 1<<4 bytes long (there's a CTASSERT to verify 495 * this in mlxcx_cmd.c), so the number of pointers is 1 << (shift - 4). 496 */ 497 #define MLXCX_RECVQ_MAX_PTRS (1 << (MLXCX_RECVQ_STRIDE_SHIFT - 4)) 498 typedef struct { 499 mlxcx_wqe_data_seg_t mlrqe_data[MLXCX_RECVQ_MAX_PTRS]; 500 } mlxcx_recvq_ent_t; 501 502 /* CSTYLED */ 503 #define MLXCX_CQ_ARM_CI (bitdef_t){ .bit_shift = 0, \ 504 .bit_mask = 0x00ffffff } 505 /* CSTYLED */ 506 #define MLXCX_CQ_ARM_SEQ (bitdef_t){ .bit_shift = 28, \ 507 .bit_mask = 0x30000000 } 508 #define MLXCX_CQ_ARM_SOLICITED (1 << 24) 509 510 typedef struct { 511 uint8_t mlcqd_rsvd; 512 uint24be_t mlcqd_update_ci; 513 bits32_t mlcqd_arm_ci; 514 } mlxcx_completionq_doorbell_t; 515 516 typedef struct { 517 uint16be_t mlwqd_rsvd; 518 uint16be_t mlwqd_recv_counter; 519 uint16be_t mlwqd_rsvd2; 520 uint16be_t mlwqd_send_counter; 521 } mlxcx_workq_doorbell_t; 522 523 #define MLXCX_EQ_STATUS_OK (0x0 << 4) 524 #define MLXCX_EQ_STATUS_WRITE_FAILURE (0xA << 4) 525 526 #define MLXCX_EQ_OI (1 << 1) 527 #define MLXCX_EQ_EC (1 << 2) 528 529 #define MLXCX_EQ_ST_ARMED 0x9 530 #define MLXCX_EQ_ST_FIRED 0xA 531 532 /* CSTYLED */ 533 #define MLXCX_EQ_LOG_PAGE_SIZE (bitdef_t){ .bit_shift = 24, \ 534 .bit_mask = 0x1F000000 } 535 536 typedef struct { 537 uint8_t mleqc_status; 538 uint8_t mleqc_ecoi; 539 uint8_t mleqc_state; 540 uint8_t mleqc_rsvd[7]; 541 uint16be_t mleqc_page_offset; 542 uint8_t mleqc_log_eq_size; 543 uint24be_t mleqc_uar_page; 544 uint8_t mleqc_rsvd3[7]; 545 uint8_t mleqc_intr; 546 uint32be_t mleqc_log_page; 547 uint8_t mleqc_rsvd4[13]; 548 uint24be_t mleqc_consumer_counter; 549 uint8_t mleqc_rsvd5; 550 uint24be_t mleqc_producer_counter; 551 uint8_t mleqc_rsvd6[16]; 552 } mlxcx_eventq_ctx_t; 553 554 typedef enum { 555 MLXCX_CQC_CQE_SIZE_64 = 0x0, 556 MLXCX_CQC_CQE_SIZE_128 = 0x1, 557 } mlxcx_cqc_cqe_sz_t; 558 559 typedef enum { 560 MLXCX_CQC_STATUS_OK = 0x0, 561 MLXCX_CQC_STATUS_OVERFLOW = 0x9, 562 MLXCX_CQC_STATUS_WRITE_FAIL = 0xA, 563 MLXCX_CQC_STATUS_INVALID = 0xF 564 } mlxcx_cqc_status_t; 565 566 typedef enum { 567 MLXCX_CQC_STATE_ARMED_SOLICITED = 0x6, 568 MLXCX_CQC_STATE_ARMED = 0x9, 569 MLXCX_CQC_STATE_FIRED = 0xA 570 } mlxcx_cqc_state_t; 571 572 /* CSTYLED */ 573 #define MLXCX_CQ_CTX_STATUS (bitdef_t){28, 0xf0000000} 574 /* CSTYLED */ 575 #define MLXCX_CQ_CTX_CQE_SZ (bitdef_t){21, 0x00e00000} 576 /* CSTYLED */ 577 #define MLXCX_CQ_CTX_PERIOD_MODE (bitdef_t){15, 0x00018000} 578 /* CSTYLED */ 579 #define MLXCX_CQ_CTX_MINI_CQE_FORMAT (bitdef_t){12, 0x00003000} 580 /* CSTYLED */ 581 #define MLXCX_CQ_CTX_STATE (bitdef_t){8, 0x00000f00} 582 583 typedef struct mlxcx_completionq_ctx { 584 bits32_t mlcqc_flags; 585 586 uint8_t mlcqc_rsvd4[4]; 587 588 uint8_t mlcqc_rsvd5[2]; 589 uint16be_t mlcqc_page_offset; 590 591 uint8_t mlcqc_log_cq_size; 592 uint24be_t mlcqc_uar_page; 593 594 uint16be_t mlcqc_cq_period; 595 uint16be_t mlcqc_cq_max_count; 596 597 uint8_t mlcqc_rsvd7[3]; 598 uint8_t mlcqc_eqn; 599 600 uint8_t mlcqc_log_page_size; 601 uint8_t mlcqc_rsvd8[3]; 602 603 uint8_t mlcqc_rsvd9[4]; 604 605 uint8_t mlcqc_rsvd10; 606 uint24be_t mlcqc_last_notified_index; 607 uint8_t mlcqc_rsvd11; 608 uint24be_t mlcqc_last_solicit_index; 609 uint8_t mlcqc_rsvd12; 610 uint24be_t mlcqc_consumer_counter; 611 uint8_t mlcqc_rsvd13; 612 uint24be_t mlcqc_producer_counter; 613 614 uint8_t mlcqc_rsvd14[8]; 615 616 uint64be_t mlcqc_dbr_addr; 617 } mlxcx_completionq_ctx_t; 618 619 typedef enum { 620 MLXCX_WORKQ_TYPE_LINKED_LIST = 0x0, 621 MLXCX_WORKQ_TYPE_CYCLIC = 0x1, 622 MLXCX_WORKQ_TYPE_LINKED_LIST_STRIDING = 0x2, 623 MLXCX_WORKQ_TYPE_CYCLIC_STRIDING = 0x3 624 } mlxcx_workq_ctx_type_t; 625 626 typedef enum { 627 MLXCX_WORKQ_END_PAD_NONE = 0x0, 628 MLXCX_WORKQ_END_PAD_ALIGN = 0x1 629 } mlxcx_workq_end_padding_t; 630 631 /* CSTYLED */ 632 #define MLXCX_WORKQ_CTX_TYPE (bitdef_t){ \ 633 .bit_shift = 28, \ 634 .bit_mask = 0xf0000000 } 635 #define MLXCX_WORKQ_CTX_SIGNATURE (1 << 27) 636 #define MLXCX_WORKQ_CTX_CD_SLAVE (1 << 24) 637 /* CSTYLED */ 638 #define MLXCX_WORKQ_CTX_END_PADDING (bitdef_t){ \ 639 .bit_shift = 25, \ 640 .bit_mask = 0x06000000 } 641 642 #define MLXCX_WORKQ_CTX_MAX_ADDRESSES 128 643 644 typedef struct mlxcx_workq_ctx { 645 bits32_t mlwqc_flags; 646 uint8_t mlwqc_rsvd[2]; 647 uint16be_t mlwqc_lwm; 648 uint8_t mlwqc_rsvd2; 649 uint24be_t mlwqc_pd; 650 uint8_t mlwqc_rsvd3; 651 uint24be_t mlwqc_uar_page; 652 uint64be_t mlwqc_dbr_addr; 653 uint32be_t mlwqc_hw_counter; 654 uint32be_t mlwqc_sw_counter; 655 uint8_t mlwqc_rsvd4; 656 uint8_t mlwqc_log_wq_stride; 657 uint8_t mlwqc_log_wq_pg_sz; 658 uint8_t mlwqc_log_wq_sz; 659 uint8_t mlwqc_rsvd5[2]; 660 bits16_t mlwqc_strides; 661 uint8_t mlwqc_rsvd6[152]; 662 uint64be_t mlwqc_pas[MLXCX_WORKQ_CTX_MAX_ADDRESSES]; 663 } mlxcx_workq_ctx_t; 664 665 #define MLXCX_RQ_FLAGS_RLKEY (1UL << 31) 666 #define MLXCX_RQ_FLAGS_SCATTER_FCS (1 << 29) 667 #define MLXCX_RQ_FLAGS_VLAN_STRIP_DISABLE (1 << 28) 668 #define MLXCX_RQ_FLAGS_FLUSH_IN_ERROR (1 << 18) 669 /* CSTYLED */ 670 #define MLXCX_RQ_MEM_RQ_TYPE (bitdef_t){ \ 671 .bit_shift = 24, \ 672 .bit_mask = 0x0f000000 } 673 /* CSTYLED */ 674 #define MLXCX_RQ_STATE (bitdef_t){ \ 675 .bit_shift = 20, \ 676 .bit_mask = 0x00f00000 } 677 678 typedef struct mlxcx_rq_ctx { 679 bits32_t mlrqc_flags; 680 uint8_t mlrqc_rsvd; 681 uint24be_t mlrqc_user_index; 682 uint8_t mlrqc_rsvd2; 683 uint24be_t mlrqc_cqn; 684 uint8_t mlrqc_counter_set_id; 685 uint8_t mlrqc_rsvd3[4]; 686 uint24be_t mlrqc_rmpn; 687 uint8_t mlrqc_rsvd4[28]; 688 mlxcx_workq_ctx_t mlrqc_wq; 689 } mlxcx_rq_ctx_t; 690 691 #define MLXCX_SQ_FLAGS_RLKEY (1UL << 31) 692 #define MLXCX_SQ_FLAGS_CD_MASTER (1 << 30) 693 #define MLXCX_SQ_FLAGS_FRE (1 << 29) 694 #define MLXCX_SQ_FLAGS_FLUSH_IN_ERROR (1 << 28) 695 #define MLXCX_SQ_FLAGS_ALLOW_MULTI_PKT (1 << 27) 696 #define MLXCX_SQ_FLAGS_REG_UMR (1 << 19) 697 698 typedef enum { 699 MLXCX_ETH_CAP_INLINE_REQUIRE_L2 = 0, 700 MLXCX_ETH_CAP_INLINE_VPORT_CTX = 1, 701 MLXCX_ETH_CAP_INLINE_NOT_REQUIRED = 2 702 } mlxcx_eth_cap_inline_mode_t; 703 704 typedef enum { 705 MLXCX_ETH_INLINE_NONE = 0, 706 MLXCX_ETH_INLINE_L2 = 1, 707 MLXCX_ETH_INLINE_L3 = 2, 708 MLXCX_ETH_INLINE_L4 = 3, 709 MLXCX_ETH_INLINE_INNER_L2 = 5, 710 MLXCX_ETH_INLINE_INNER_L3 = 6, 711 MLXCX_ETH_INLINE_INNER_L4 = 7 712 } mlxcx_eth_inline_mode_t; 713 714 /* CSTYLED */ 715 #define MLXCX_SQ_MIN_WQE_INLINE (bitdef_t){ \ 716 .bit_shift = 24, \ 717 .bit_mask = 0x07000000 } 718 /* CSTYLED */ 719 #define MLXCX_SQ_STATE (bitdef_t){ \ 720 .bit_shift = 20, \ 721 .bit_mask = 0x00f00000 } 722 723 typedef struct mlxcx_sq_ctx { 724 bits32_t mlsqc_flags; 725 uint8_t mlsqc_rsvd; 726 uint24be_t mlsqc_user_index; 727 uint8_t mlsqc_rsvd2; 728 uint24be_t mlsqc_cqn; 729 uint8_t mlsqc_rsvd3[18]; 730 uint16be_t mlsqc_packet_pacing_rate_limit_index; 731 uint16be_t mlsqc_tis_lst_sz; 732 uint8_t mlsqc_rsvd4[11]; 733 uint24be_t mlsqc_tis_num; 734 mlxcx_workq_ctx_t mlsqc_wq; 735 } mlxcx_sq_ctx_t; 736 737 #define MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES 64 738 739 typedef enum { 740 MLXCX_VPORT_PROMISC_UCAST = 1 << 15, 741 MLXCX_VPORT_PROMISC_MCAST = 1 << 14, 742 MLXCX_VPORT_PROMISC_ALL = 1 << 13 743 } mlxcx_nic_vport_ctx_promisc_t; 744 745 #define MLXCX_VPORT_LIST_TYPE_MASK 0x07 746 #define MLXCX_VPORT_LIST_TYPE_SHIFT 0 747 748 /* CSTYLED */ 749 #define MLXCX_VPORT_CTX_MIN_WQE_INLINE (bitdef_t){56, 0x0700000000000000} 750 751 typedef struct { 752 bits64_t mlnvc_flags; 753 uint8_t mlnvc_rsvd[28]; 754 uint8_t mlnvc_rsvd2[2]; 755 uint16be_t mlnvc_mtu; 756 uint64be_t mlnvc_system_image_guid; 757 uint64be_t mlnvc_port_guid; 758 uint64be_t mlnvc_node_guid; 759 uint8_t mlnvc_rsvd3[40]; 760 uint16be_t mlnvc_qkey_violation_counter; 761 uint8_t mlnvc_rsvd4[2]; 762 uint8_t mlnvc_rsvd5[132]; 763 bits16_t mlnvc_promisc_list_type; 764 uint16be_t mlnvc_allowed_list_size; 765 uint8_t mlnvc_rsvd6[2]; 766 uint8_t mlnvc_permanent_address[6]; 767 uint8_t mlnvc_rsvd7[4]; 768 uint64be_t mlnvc_address[MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES]; 769 } mlxcx_nic_vport_ctx_t; 770 771 typedef struct { 772 uint8_t mlftc_flags; 773 uint8_t mlftc_level; 774 uint8_t mlftc_rsvd; 775 uint8_t mlftc_log_size; 776 uint8_t mlftc_rsvd2; 777 uint24be_t mlftc_table_miss_id; 778 uint8_t mlftc_rsvd3[4]; 779 uint8_t mlftc_rsvd4[28]; 780 } mlxcx_flow_table_ctx_t; 781 782 /* CSTYLED */ 783 #define MLXCX_FLOW_HDR_FIRST_VID (bitdef_t){0, 0x07ff} 784 /* CSTYLED */ 785 #define MLXCX_FLOW_HDR_FIRST_PRIO (bitdef_t){13,0x7000} 786 #define MLXCX_FLOW_HDR_FIRST_CFI (1 << 12) 787 788 #define MLXCX_FLOW_HDR_IP_DSCP_SHIFT 18 789 #define MLXCX_FLOW_HDR_IP_DSCP_MASK 0xfc0000 790 #define MLXCX_FLOW_HDR_IP_ECN_SHIFT 16 791 #define MLXCX_FLOW_HDR_IP_ECN_MASK 0x030000 792 #define MLXCX_FLOW_HDR_CVLAN_TAG (1 << 15) 793 #define MLXCX_FLOW_HDR_SVLAN_TAG (1 << 14) 794 #define MLXCX_FLOW_HDR_FRAG (1 << 13) 795 /* CSTYLED */ 796 #define MLXCX_FLOW_HDR_IP_VERSION (bitdef_t){ \ 797 .bit_shift = 9, \ 798 .bit_mask = 0x001e00 } 799 /* CSTYLED */ 800 #define MLXCX_FLOW_HDR_TCP_FLAGS (bitdef_t){ \ 801 .bit_shift = 0, \ 802 .bit_mask = 0x0001ff } 803 804 typedef struct { 805 uint8_t mlfh_smac[6]; 806 uint16be_t mlfh_ethertype; 807 uint8_t mlfh_dmac[6]; 808 bits16_t mlfh_first_vid_flags; 809 uint8_t mlfh_ip_protocol; 810 bits24_t mlfh_tcp_ip_flags; 811 uint16be_t mlfh_tcp_sport; 812 uint16be_t mlfh_tcp_dport; 813 uint8_t mlfh_rsvd[3]; 814 uint8_t mlfh_ip_ttl_hoplimit; 815 uint16be_t mlfh_udp_sport; 816 uint16be_t mlfh_udp_dport; 817 uint8_t mlfh_src_ip[16]; 818 uint8_t mlfh_dst_ip[16]; 819 } mlxcx_flow_header_match_t; 820 821 typedef struct { 822 uint8_t mlfp_rsvd; 823 uint24be_t mlfp_source_sqn; 824 uint8_t mlfp_rsvd2[2]; 825 uint16be_t mlfp_source_port; 826 bits16_t mlfp_outer_second_vid_flags; 827 bits16_t mlfp_inner_second_vid_flags; 828 bits16_t mlfp_vlan_flags; 829 uint16be_t mlfp_gre_protocol; 830 uint32be_t mlfp_gre_key; 831 uint24be_t mlfp_vxlan_vni; 832 uint8_t mlfp_rsvd3; 833 uint8_t mlfp_rsvd4[4]; 834 uint8_t mlfp_rsvd5; 835 uint24be_t mlfp_outer_ipv6_flow_label; 836 uint8_t mlfp_rsvd6; 837 uint24be_t mlfp_inner_ipv6_flow_label; 838 uint8_t mlfp_rsvd7[28]; 839 } mlxcx_flow_params_match_t; 840 841 typedef struct { 842 mlxcx_flow_header_match_t mlfm_outer_headers; 843 mlxcx_flow_params_match_t mlfm_misc_parameters; 844 mlxcx_flow_header_match_t mlfm_inner_headers; 845 uint8_t mlfm_rsvd[320]; 846 } mlxcx_flow_match_t; 847 848 #define MLXCX_FLOW_MAX_DESTINATIONS 64 849 typedef enum { 850 MLXCX_FLOW_DEST_VPORT = 0x0, 851 MLXCX_FLOW_DEST_FLOW_TABLE = 0x1, 852 MLXCX_FLOW_DEST_TIR = 0x2, 853 MLXCX_FLOW_DEST_QP = 0x3 854 } mlxcx_flow_destination_type_t; 855 856 typedef struct { 857 uint8_t mlfd_destination_type; 858 uint24be_t mlfd_destination_id; 859 uint8_t mlfd_rsvd[4]; 860 } mlxcx_flow_dest_t; 861 862 typedef enum { 863 MLXCX_FLOW_ACTION_ALLOW = 1 << 0, 864 MLXCX_FLOW_ACTION_DROP = 1 << 1, 865 MLXCX_FLOW_ACTION_FORWARD = 1 << 2, 866 MLXCX_FLOW_ACTION_COUNT = 1 << 3, 867 MLXCX_FLOW_ACTION_ENCAP = 1 << 4, 868 MLXCX_FLOW_ACTION_DECAP = 1 << 5 869 } mlxcx_flow_action_t; 870 871 typedef struct { 872 uint8_t mlfec_rsvd[4]; 873 uint32be_t mlfec_group_id; 874 uint8_t mlfec_rsvd2; 875 uint24be_t mlfec_flow_tag; 876 uint8_t mlfec_rsvd3[2]; 877 uint16be_t mlfec_action; 878 uint8_t mlfec_rsvd4; 879 uint24be_t mlfec_destination_list_size; 880 uint8_t mlfec_rsvd5; 881 uint24be_t mlfec_flow_counter_list_size; 882 uint32be_t mlfec_encap_id; 883 uint8_t mlfec_rsvd6[36]; 884 mlxcx_flow_match_t mlfec_match_value; 885 uint8_t mlfec_rsvd7[192]; 886 mlxcx_flow_dest_t mlfec_destination[MLXCX_FLOW_MAX_DESTINATIONS]; 887 } mlxcx_flow_entry_ctx_t; 888 889 /* CSTYLED */ 890 #define MLXCX_TIR_CTX_DISP_TYPE (bitdef_t){ 4, 0xf0 } 891 typedef enum { 892 MLXCX_TIR_DIRECT = 0x0, 893 MLXCX_TIR_INDIRECT = 0x1, 894 } mlxcx_tir_type_t; 895 896 /* CSTYLED */ 897 #define MLXCX_TIR_LRO_TIMEOUT (bitdef_t){ 12, 0x0ffff000 } 898 /* CSTYLED */ 899 #define MLXCX_TIR_LRO_ENABLE_MASK (bitdef_t){ 8, 0x00000f00 } 900 /* CSTYLED */ 901 #define MLXCX_TIR_LRO_MAX_MSG_SZ (bitdef_t){ 0, 0x000000ff } 902 903 /* CSTYLED */ 904 #define MLXCX_TIR_RX_HASH_FN (bitdef_t){ 4, 0xf0 } 905 typedef enum { 906 MLXCX_TIR_HASH_NONE = 0x0, 907 MLXCX_TIR_HASH_XOR8 = 0x1, 908 MLXCX_TIR_HASH_TOEPLITZ = 0x2 909 } mlxcx_tir_hash_fn_t; 910 #define MLXCX_TIR_LB_UNICAST (1 << 24) 911 #define MLXCX_TIR_LB_MULTICAST (1 << 25) 912 913 /* CSTYLED */ 914 #define MLXCX_RX_HASH_L3_TYPE (bitdef_t){ 31, 0x80000000 } 915 typedef enum { 916 MLXCX_RX_HASH_L3_IPv4 = 0, 917 MLXCX_RX_HASH_L3_IPv6 = 1 918 } mlxcx_tir_rx_hash_l3_type_t; 919 /* CSTYLED */ 920 #define MLXCX_RX_HASH_L4_TYPE (bitdef_t){ 30, 0x40000000 } 921 typedef enum { 922 MLXCX_RX_HASH_L4_TCP = 0, 923 MLXCX_RX_HASH_L4_UDP = 1 924 } mlxcx_tir_rx_hash_l4_type_t; 925 /* CSTYLED */ 926 #define MLXCX_RX_HASH_FIELDS (bitdef_t){ 0, 0x3fffffff } 927 typedef enum { 928 MLXCX_RX_HASH_SRC_IP = 1 << 0, 929 MLXCX_RX_HASH_DST_IP = 1 << 1, 930 MLXCX_RX_HASH_L4_SPORT = 1 << 2, 931 MLXCX_RX_HASH_L4_DPORT = 1 << 3, 932 MLXCX_RX_HASH_IPSEC_SPI = 1 << 4 933 } mlxcx_tir_rx_hash_fields_t; 934 935 typedef struct { 936 uint8_t mltirc_rsvd[4]; 937 bits8_t mltirc_disp_type; 938 uint8_t mltirc_rsvd2[11]; 939 bits32_t mltirc_lro; 940 uint8_t mltirc_rsvd3[9]; 941 uint24be_t mltirc_inline_rqn; 942 bits8_t mltirc_flags; 943 uint24be_t mltirc_indirect_table; 944 bits8_t mltirc_hash_lb; 945 uint24be_t mltirc_transport_domain; 946 uint8_t mltirc_rx_hash_toeplitz_key[40]; 947 bits32_t mltirc_rx_hash_fields_outer; 948 bits32_t mltirc_rx_hash_fields_inner; 949 uint8_t mltirc_rsvd4[152]; 950 } mlxcx_tir_ctx_t; 951 952 typedef struct { 953 uint8_t mltisc_rsvd; 954 uint8_t mltisc_prio_or_sl; 955 uint8_t mltisc_rsvd2[35]; 956 uint24be_t mltisc_transport_domain; 957 uint8_t mltisc_rsvd3[120]; 958 } mlxcx_tis_ctx_t; 959 960 #define MLXCX_RQT_MAX_RQ_REFS 64 961 962 typedef struct { 963 uint8_t mlrqtr_rsvd; 964 uint24be_t mlrqtr_rqn; 965 } mlxcx_rqtable_rq_ref_t; 966 967 typedef struct { 968 uint8_t mlrqtc_rsvd[22]; 969 uint16be_t mlrqtc_max_size; 970 uint8_t mlrqtc_rsvd2[2]; 971 uint16be_t mlrqtc_actual_size; 972 uint8_t mlrqtc_rsvd3[212]; 973 mlxcx_rqtable_rq_ref_t mlrqtc_rqref[MLXCX_RQT_MAX_RQ_REFS]; 974 } mlxcx_rqtable_ctx_t; 975 976 #pragma pack() 977 978 typedef enum { 979 MLXCX_EVENT_COMPLETION = 0x00, 980 MLXCX_EVENT_PATH_MIGRATED = 0x01, 981 MLXCX_EVENT_COMM_ESTABLISH = 0x02, 982 MLXCX_EVENT_SENDQ_DRAIN = 0x03, 983 MLXCX_EVENT_LAST_WQE = 0x13, 984 MLXCX_EVENT_SRQ_LIMIT = 0x14, 985 MLXCX_EVENT_DCT_ALL_CLOSED = 0x1C, 986 MLXCX_EVENT_DCT_ACCKEY_VIOL = 0x1D, 987 MLXCX_EVENT_CQ_ERROR = 0x04, 988 MLXCX_EVENT_WQ_CATASTROPHE = 0x05, 989 MLXCX_EVENT_PATH_MIGRATE_FAIL = 0x07, 990 MLXCX_EVENT_PAGE_FAULT = 0x0C, 991 MLXCX_EVENT_WQ_INVALID_REQ = 0x10, 992 MLXCX_EVENT_WQ_ACCESS_VIOL = 0x11, 993 MLXCX_EVENT_SRQ_CATASTROPHE = 0x12, 994 MLXCX_EVENT_INTERNAL_ERROR = 0x08, 995 MLXCX_EVENT_PORT_STATE = 0x09, 996 MLXCX_EVENT_GPIO = 0x15, 997 MLXCX_EVENT_PORT_MODULE = 0x16, 998 MLXCX_EVENT_TEMP_WARNING = 0x17, 999 MLXCX_EVENT_REMOTE_CONFIG = 0x19, 1000 MLXCX_EVENT_DCBX_CHANGE = 0x1E, 1001 MLXCX_EVENT_DOORBELL_CONGEST = 0x1A, 1002 MLXCX_EVENT_STALL_VL = 0x1B, 1003 MLXCX_EVENT_CMD_COMPLETION = 0x0A, 1004 MLXCX_EVENT_PAGE_REQUEST = 0x0B, 1005 MLXCX_EVENT_NIC_VPORT = 0x0D, 1006 MLXCX_EVENT_EC_PARAMS_CHANGE = 0x0E, 1007 MLXCX_EVENT_XRQ_ERROR = 0x18 1008 } mlxcx_event_t; 1009 1010 typedef enum { 1011 MLXCX_CMD_R_OK = 0x00, 1012 MLXCX_CMD_R_INTERNAL_ERR = 0x01, 1013 MLXCX_CMD_R_BAD_OP = 0x02, 1014 MLXCX_CMD_R_BAD_PARAM = 0x03, 1015 MLXCX_CMD_R_BAD_SYS_STATE = 0x04, 1016 MLXCX_CMD_R_BAD_RESOURCE = 0x05, 1017 MLXCX_CMD_R_RESOURCE_BUSY = 0x06, 1018 MLXCX_CMD_R_EXCEED_LIM = 0x08, 1019 MLXCX_CMD_R_BAD_RES_STATE = 0x09, 1020 MLXCX_CMD_R_BAD_INDEX = 0x0a, 1021 MLXCX_CMD_R_NO_RESOURCES = 0x0f, 1022 MLXCX_CMD_R_BAD_INPUT_LEN = 0x50, 1023 MLXCX_CMD_R_BAD_OUTPUT_LEN = 0x51, 1024 MLXCX_CMD_R_BAD_RESOURCE_STATE = 0x10, 1025 MLXCX_CMD_R_BAD_PKT = 0x30, 1026 MLXCX_CMD_R_BAD_SIZE = 0x40, 1027 MLXCX_CMD_R_TIMEOUT = 0xFF 1028 } mlxcx_cmd_ret_t; 1029 1030 typedef enum { 1031 MLXCX_OP_QUERY_HCA_CAP = 0x100, 1032 MLXCX_OP_QUERY_ADAPTER = 0x101, 1033 MLXCX_OP_INIT_HCA = 0x102, 1034 MLXCX_OP_TEARDOWN_HCA = 0x103, 1035 MLXCX_OP_ENABLE_HCA = 0x104, 1036 MLXCX_OP_DISABLE_HCA = 0x105, 1037 MLXCX_OP_QUERY_PAGES = 0x107, 1038 MLXCX_OP_MANAGE_PAGES = 0x108, 1039 MLXCX_OP_SET_HCA_CAP = 0x109, 1040 MLXCX_OP_QUERY_ISSI = 0x10A, 1041 MLXCX_OP_SET_ISSI = 0x10B, 1042 MLXCX_OP_SET_DRIVER_VERSION = 0x10D, 1043 MLXCX_OP_QUERY_OTHER_HCA_CAP = 0x10E, 1044 MLXCX_OP_MODIFY_OTHER_HCA_CAP = 0x10F, 1045 MLXCX_OP_SET_TUNNELED_OPERATIONS = 0x110, 1046 MLXCX_OP_CREATE_MKEY = 0x200, 1047 MLXCX_OP_QUERY_MKEY = 0x201, 1048 MLXCX_OP_DESTROY_MKEY = 0x202, 1049 MLXCX_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 1050 MLXCX_OP_PAGE_FAULT_RESUME = 0x204, 1051 MLXCX_OP_CREATE_EQ = 0x301, 1052 MLXCX_OP_DESTROY_EQ = 0x302, 1053 MLXCX_OP_QUERY_EQ = 0x303, 1054 MLXCX_OP_GEN_EQE = 0x304, 1055 MLXCX_OP_CREATE_CQ = 0x400, 1056 MLXCX_OP_DESTROY_CQ = 0x401, 1057 MLXCX_OP_QUERY_CQ = 0x402, 1058 MLXCX_OP_MODIFY_CQ = 0x403, 1059 MLXCX_OP_CREATE_QP = 0x500, 1060 MLXCX_OP_DESTROY_QP = 0x501, 1061 MLXCX_OP_RST2INIT_QP = 0x502, 1062 MLXCX_OP_INIT2RTR_QP = 0x503, 1063 MLXCX_OP_RTR2RTS_QP = 0x504, 1064 MLXCX_OP_RTS2RTS_QP = 0x505, 1065 MLXCX_OP_SQERR2RTS_QP = 0x506, 1066 MLXCX_OP__2ERR_QP = 0x507, 1067 MLXCX_OP__2RST_QP = 0x50A, 1068 MLXCX_OP_QUERY_QP = 0x50B, 1069 MLXCX_OP_SQD_RTS_QP = 0x50C, 1070 MLXCX_OP_INIT2INIT_QP = 0x50E, 1071 MLXCX_OP_CREATE_PSV = 0x600, 1072 MLXCX_OP_DESTROY_PSV = 0x601, 1073 MLXCX_OP_CREATE_SRQ = 0x700, 1074 MLXCX_OP_DESTROY_SRQ = 0x701, 1075 MLXCX_OP_QUERY_SRQ = 0x702, 1076 MLXCX_OP_ARM_RQ = 0x703, 1077 MLXCX_OP_CREATE_XRC_SRQ = 0x705, 1078 MLXCX_OP_DESTROY_XRC_SRQ = 0x706, 1079 MLXCX_OP_QUERY_XRC_SRQ = 0x707, 1080 MLXCX_OP_ARM_XRC_SRQ = 0x708, 1081 MLXCX_OP_CREATE_DCT = 0x710, 1082 MLXCX_OP_DESTROY_DCT = 0x711, 1083 MLXCX_OP_DRAIN_DCT = 0x712, 1084 MLXCX_OP_QUERY_DCT = 0x713, 1085 MLXCX_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 1086 MLXCX_OP_CREATE_XRQ = 0x717, 1087 MLXCX_OP_DESTROY_XRQ = 0x718, 1088 MLXCX_OP_QUERY_XRQ = 0x719, 1089 MLXCX_OP_CREATE_NVMF_BACKEND_CONTROLLER = 0x720, 1090 MLXCX_OP_DESTROY_NVMF_BACKEND_CONTROLLER = 0x721, 1091 MLXCX_OP_QUERY_NVMF_BACKEND_CONTROLLER = 0x722, 1092 MLXCX_OP_ATTACH_NVMF_NAMESPACE = 0x723, 1093 MLXCX_OP_DETACH_NVMF_NAMESPACE = 0x724, 1094 MLXCX_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 1095 MLXCX_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 1096 MLXCX_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 1097 MLXCX_OP_QUERY_VPORT_STATE = 0x750, 1098 MLXCX_OP_MODIFY_VPORT_STATE = 0x751, 1099 MLXCX_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 1100 MLXCX_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 1101 MLXCX_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1102 MLXCX_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 1103 MLXCX_OP_QUERY_ROCE_ADDRESS = 0x760, 1104 MLXCX_OP_SET_ROCE_ADDRESS = 0x761, 1105 MLXCX_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 1106 MLXCX_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 1107 MLXCX_OP_QUERY_HCA_VPORT_GID = 0x764, 1108 MLXCX_OP_QUERY_HCA_VPORT_PKEY = 0x765, 1109 MLXCX_OP_QUERY_VPORT_COUNTER = 0x770, 1110 MLXCX_OP_ALLOC_Q_COUNTER = 0x771, 1111 MLXCX_OP_DEALLOC_Q_COUNTER = 0x772, 1112 MLXCX_OP_QUERY_Q_COUNTER = 0x773, 1113 MLXCX_OP_SET_PP_RATE_LIMIT = 0x780, 1114 MLXCX_OP_QUERY_PP_RATE_LIMIT = 0x781, 1115 MLXCX_OP_ALLOC_PD = 0x800, 1116 MLXCX_OP_DEALLOC_PD = 0x801, 1117 MLXCX_OP_ALLOC_UAR = 0x802, 1118 MLXCX_OP_DEALLOC_UAR = 0x803, 1119 MLXCX_OP_CONFIG_INT_MODERATION = 0x804, 1120 MLXCX_OP_ACCESS_REG = 0x805, 1121 MLXCX_OP_ATTACH_TO_MCG = 0x806, 1122 MLXCX_OP_DETACH_FROM_MCG = 0x807, 1123 MLXCX_OP_MAD_IFC = 0x50D, 1124 MLXCX_OP_QUERY_MAD_DEMUX = 0x80B, 1125 MLXCX_OP_SET_MAD_DEMUX = 0x80C, 1126 MLXCX_OP_NOP = 0x80D, 1127 MLXCX_OP_ALLOC_XRCD = 0x80E, 1128 MLXCX_OP_DEALLOC_XRCD = 0x80F, 1129 MLXCX_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1130 MLXCX_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 1131 MLXCX_OP_QUERY_CONG_STATUS = 0x822, 1132 MLXCX_OP_MODIFY_CONG_STATUS = 0x823, 1133 MLXCX_OP_QUERY_CONG_PARAMS = 0x824, 1134 MLXCX_OP_MODIFY_CONG_PARAMS = 0x825, 1135 MLXCX_OP_QUERY_CONG_STATISTICS = 0x826, 1136 MLXCX_OP_ADD_VXLAN_UDP_DPORT = 0x827, 1137 MLXCX_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 1138 MLXCX_OP_SET_L2_TABLE_ENTRY = 0x829, 1139 MLXCX_OP_QUERY_L2_TABLE_ENTRY = 0x82A, 1140 MLXCX_OP_DELETE_L2_TABLE_ENTRY = 0x82B, 1141 MLXCX_OP_SET_WOL_ROL = 0x830, 1142 MLXCX_OP_QUERY_WOL_ROL = 0x831, 1143 MLXCX_OP_CREATE_TIR = 0x900, 1144 MLXCX_OP_MODIFY_TIR = 0x901, 1145 MLXCX_OP_DESTROY_TIR = 0x902, 1146 MLXCX_OP_QUERY_TIR = 0x903, 1147 MLXCX_OP_CREATE_SQ = 0x904, 1148 MLXCX_OP_MODIFY_SQ = 0x905, 1149 MLXCX_OP_DESTROY_SQ = 0x906, 1150 MLXCX_OP_QUERY_SQ = 0x907, 1151 MLXCX_OP_CREATE_RQ = 0x908, 1152 MLXCX_OP_MODIFY_RQ = 0x909, 1153 MLXCX_OP_DESTROY_RQ = 0x90A, 1154 MLXCX_OP_QUERY_RQ = 0x90B, 1155 MLXCX_OP_CREATE_RMP = 0x90C, 1156 MLXCX_OP_MODIFY_RMP = 0x90D, 1157 MLXCX_OP_DESTROY_RMP = 0x90E, 1158 MLXCX_OP_QUERY_RMP = 0x90F, 1159 MLXCX_OP_CREATE_TIS = 0x912, 1160 MLXCX_OP_MODIFY_TIS = 0x913, 1161 MLXCX_OP_DESTROY_TIS = 0x914, 1162 MLXCX_OP_QUERY_TIS = 0x915, 1163 MLXCX_OP_CREATE_RQT = 0x916, 1164 MLXCX_OP_MODIFY_RQT = 0x917, 1165 MLXCX_OP_DESTROY_RQT = 0x918, 1166 MLXCX_OP_QUERY_RQT = 0x919, 1167 MLXCX_OP_SET_FLOW_TABLE_ROOT = 0x92f, 1168 MLXCX_OP_CREATE_FLOW_TABLE = 0x930, 1169 MLXCX_OP_DESTROY_FLOW_TABLE = 0x931, 1170 MLXCX_OP_QUERY_FLOW_TABLE = 0x932, 1171 MLXCX_OP_CREATE_FLOW_GROUP = 0x933, 1172 MLXCX_OP_DESTROY_FLOW_GROUP = 0x934, 1173 MLXCX_OP_QUERY_FLOW_GROUP = 0x935, 1174 MLXCX_OP_SET_FLOW_TABLE_ENTRY = 0x936, 1175 MLXCX_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 1176 MLXCX_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 1177 MLXCX_OP_ALLOC_FLOW_COUNTER = 0x939, 1178 MLXCX_OP_DEALLOC_FLOW_COUNTER = 0x93a, 1179 MLXCX_OP_QUERY_FLOW_COUNTER = 0x93b, 1180 MLXCX_OP_MODIFY_FLOW_TABLE = 0x93c, 1181 MLXCX_OP_ALLOC_ENCAP_HEADER = 0x93d, 1182 MLXCX_OP_DEALLOC_ENCAP_HEADER = 0x93e, 1183 MLXCX_OP_QUERY_ENCAP_HEADER = 0x93f 1184 } mlxcx_cmd_op_t; 1185 1186 /* 1187 * Definitions for relevant commands 1188 */ 1189 #pragma pack(1) 1190 typedef struct { 1191 uint16be_t mci_opcode; 1192 uint8_t mci_rsvd[4]; 1193 uint16be_t mci_op_mod; 1194 } mlxcx_cmd_in_t; 1195 1196 typedef struct { 1197 uint8_t mco_status; 1198 uint8_t mco_rsvd[3]; 1199 uint32be_t mco_syndrome; 1200 } mlxcx_cmd_out_t; 1201 1202 typedef struct { 1203 mlxcx_cmd_in_t mlxi_enable_hca_head; 1204 uint8_t mlxi_enable_hca_rsvd[2]; 1205 uint16be_t mlxi_enable_hca_func; 1206 uint8_t mlxi_enable_hca_rsvd1[4]; 1207 } mlxcx_cmd_enable_hca_in_t; 1208 1209 typedef struct { 1210 mlxcx_cmd_out_t mlxo_enable_hca_head; 1211 uint8_t mlxo_enable_hca_rsvd[8]; 1212 } mlxcx_cmd_enable_hca_out_t; 1213 1214 typedef struct { 1215 mlxcx_cmd_in_t mlxi_disable_hca_head; 1216 uint8_t mlxi_disable_hca_rsvd[2]; 1217 uint16be_t mlxi_disable_hca_func; 1218 uint8_t mlxi_disable_hca_rsvd1[4]; 1219 } mlxcx_cmd_disable_hca_in_t; 1220 1221 typedef struct { 1222 mlxcx_cmd_out_t mlxo_disable_hca_head; 1223 uint8_t mlxo_disable_hca_rsvd[8]; 1224 } mlxcx_cmd_disable_hca_out_t; 1225 1226 typedef struct { 1227 mlxcx_cmd_in_t mlxi_query_issi_head; 1228 uint8_t mlxi_query_issi_rsvd[8]; 1229 } mlxcx_cmd_query_issi_in_t; 1230 1231 typedef struct { 1232 mlxcx_cmd_out_t mlxo_query_issi_head; 1233 uint8_t mlxo_query_issi_rsv[2]; 1234 uint16be_t mlxo_query_issi_current; 1235 uint8_t mlxo_query_issi_rsvd1[20]; 1236 /* 1237 * To date we only support version 1 of the ISSI. The last byte has the 1238 * ISSI data that we care about, therefore we phrase the struct this 1239 * way. 1240 */ 1241 uint8_t mlxo_query_issi_rsvd2[79]; 1242 uint8_t mlxo_supported_issi; 1243 } mlxcx_cmd_query_issi_out_t; 1244 1245 typedef struct { 1246 mlxcx_cmd_in_t mlxi_set_issi_head; 1247 uint8_t mlxi_set_issi_rsvd[2]; 1248 uint16be_t mlxi_set_issi_current; 1249 uint8_t mlxi_set_iss_rsvd1[4]; 1250 } mlxcx_cmd_set_issi_in_t; 1251 1252 typedef struct { 1253 mlxcx_cmd_out_t mlxo_set_issi_head; 1254 uint8_t mlxo_set_issi_rsvd[8]; 1255 } mlxcx_cmd_set_issi_out_t; 1256 1257 typedef struct { 1258 mlxcx_cmd_in_t mlxi_init_hca_head; 1259 uint8_t mlxi_init_hca_rsvd[8]; 1260 } mlxcx_cmd_init_hca_in_t; 1261 1262 typedef struct { 1263 mlxcx_cmd_out_t mlxo_init_hca_head; 1264 uint8_t mlxo_init_hca_rsvd[8]; 1265 } mlxcx_cmd_init_hca_out_t; 1266 1267 #define MLXCX_TEARDOWN_HCA_GRACEFUL 0x00 1268 #define MLXCX_TEARDOWN_HCA_FORCE 0x01 1269 1270 typedef struct { 1271 mlxcx_cmd_in_t mlxi_teardown_hca_head; 1272 uint8_t mlxi_teardown_hca_rsvd[2]; 1273 uint16be_t mlxi_teardown_hca_profile; 1274 uint8_t mlxi_teardown_hca_rsvd1[4]; 1275 } mlxcx_cmd_teardown_hca_in_t; 1276 1277 typedef struct { 1278 mlxcx_cmd_out_t mlxo_teardown_hca_head; 1279 uint8_t mlxo_teardown_hca_rsvd[7]; 1280 uint8_t mlxo_teardown_hca_state; 1281 } mlxcx_cmd_teardown_hca_out_t; 1282 1283 #define MLXCX_QUERY_PAGES_OPMOD_BOOT 0x01 1284 #define MLXCX_QUERY_PAGES_OPMOD_INIT 0x02 1285 #define MLXCX_QUERY_PAGES_OPMOD_REGULAR 0x03 1286 1287 typedef struct { 1288 mlxcx_cmd_in_t mlxi_query_pages_head; 1289 uint8_t mlxi_query_pages_rsvd[2]; 1290 uint16be_t mlxi_query_pages_func; 1291 uint8_t mlxi_query_pages_rsvd1[4]; 1292 } mlxcx_cmd_query_pages_in_t; 1293 1294 typedef struct { 1295 mlxcx_cmd_out_t mlxo_query_pages_head; 1296 uint8_t mlxo_query_pages_rsvd[2]; 1297 uint16be_t mlxo_query_pages_func; 1298 uint32be_t mlxo_query_pages_npages; 1299 } mlxcx_cmd_query_pages_out_t; 1300 1301 #define MLXCX_MANAGE_PAGES_OPMOD_ALLOC_FAIL 0x00 1302 #define MLXCX_MANAGE_PAGES_OPMOD_GIVE_PAGES 0x01 1303 #define MLXCX_MANAGE_PAGES_OPMOD_RETURN_PAGES 0x02 1304 1305 /* 1306 * This is an artificial limit that we're imposing on our actions. 1307 * Large enough to limit the number of manage pages calls we have to 1308 * make, but not so large that it will overflow any of the command 1309 * mailboxes. 1310 */ 1311 #define MLXCX_MANAGE_PAGES_MAX_PAGES 4096 1312 1313 typedef struct { 1314 mlxcx_cmd_in_t mlxi_manage_pages_head; 1315 uint8_t mlxi_manage_pages_rsvd[2]; 1316 uint16be_t mlxi_manage_pages_func; 1317 uint32be_t mlxi_manage_pages_npages; 1318 uint64be_t mlxi_manage_pages_pas[]; 1319 } mlxcx_cmd_manage_pages_in_t; 1320 1321 typedef struct { 1322 mlxcx_cmd_out_t mlxo_manage_pages_head; 1323 uint32be_t mlxo_manage_pages_npages; 1324 uint8_t mlxo_manage_pages_rsvd[4]; 1325 uint64be_t mlxo_manage_pages_pas[]; 1326 } mlxcx_cmd_manage_pages_out_t; 1327 1328 typedef enum { 1329 MLXCX_HCA_CAP_MODE_MAX = 0x0, 1330 MLXCX_HCA_CAP_MODE_CURRENT = 0x1 1331 } mlxcx_hca_cap_mode_t; 1332 1333 typedef enum { 1334 MLXCX_HCA_CAP_GENERAL = 0x0, 1335 MLXCX_HCA_CAP_ETHERNET = 0x1, 1336 MLXCX_HCA_CAP_ODP = 0x2, 1337 MLXCX_HCA_CAP_ATOMIC = 0x3, 1338 MLXCX_HCA_CAP_ROCE = 0x4, 1339 MLXCX_HCA_CAP_IPoIB = 0x5, 1340 MLXCX_HCA_CAP_NIC_FLOW = 0x7, 1341 MLXCX_HCA_CAP_ESWITCH_FLOW = 0x8, 1342 MLXCX_HCA_CAP_ESWITCH = 0x9, 1343 MLXCX_HCA_CAP_VECTOR = 0xb, 1344 MLXCX_HCA_CAP_QoS = 0xc, 1345 MLXCX_HCA_CAP_NVMEoF = 0xe 1346 } mlxcx_hca_cap_type_t; 1347 1348 typedef enum { 1349 MLXCX_CAP_GENERAL_PORT_TYPE_IB = 0x0, 1350 MLXCX_CAP_GENERAL_PORT_TYPE_ETHERNET = 0x1, 1351 } mlxcx_hca_cap_general_port_type_t; 1352 1353 typedef enum { 1354 MLXCX_CAP_GENERAL_FLAGS_C_ESW_FLOW_TABLE = (1 << 8), 1355 MLXCX_CAP_GENERAL_FLAGS_C_NIC_FLOW_TABLE = (1 << 9), 1356 } mlxcx_hca_cap_general_flags_c_t; 1357 1358 typedef struct { 1359 uint8_t mlcap_general_access_other_hca_roce; 1360 uint8_t mlcap_general_rsvd[3]; 1361 1362 uint8_t mlcap_general_rsvd2[12]; 1363 1364 uint8_t mlcap_general_log_max_srq_sz; 1365 uint8_t mlcap_general_log_max_qp_sz; 1366 uint8_t mlcap_general_rsvd3[1]; 1367 uint8_t mlcap_general_log_max_qp; 1368 1369 uint8_t mlcap_general_rsvd4[1]; 1370 uint8_t mlcap_general_log_max_srq; 1371 uint8_t mlcap_general_rsvd5[2]; 1372 1373 uint8_t mlcap_general_rsvd6[1]; 1374 uint8_t mlcap_general_log_max_cq_sz; 1375 uint8_t mlcap_general_rsvd7[1]; 1376 uint8_t mlcap_general_log_max_cq; 1377 1378 uint8_t mlcap_general_log_max_eq_sz; 1379 uint8_t mlcap_general_log_max_mkey_flags; 1380 uint8_t mlcap_general_rsvd8[1]; 1381 uint8_t mlcap_general_log_max_eq; 1382 1383 uint8_t mlcap_general_max_indirection; 1384 uint8_t mlcap_general_log_max_mrw_sz_flags; 1385 uint8_t mlcap_general_log_max_bsf_list_size_flags; 1386 uint8_t mlcap_general_log_max_klm_list_size_flags; 1387 1388 uint8_t mlcap_general_rsvd9[1]; 1389 uint8_t mlcap_general_log_max_ra_req_dc; 1390 uint8_t mlcap_general_rsvd10[1]; 1391 uint8_t mlcap_general_log_max_ra_res_dc; 1392 1393 uint8_t mlcap_general_rsvd11[1]; 1394 uint8_t mlcap_general_log_max_ra_req_qp; 1395 uint8_t mlcap_general_rsvd12[1]; 1396 uint8_t mlcap_general_log_max_ra_res_qp; 1397 1398 uint16be_t mlcap_general_flags_a; 1399 uint16be_t mlcap_general_gid_table_size; 1400 1401 bits16_t mlcap_general_flags_b; 1402 uint16be_t mlcap_general_pkey_table_size; 1403 1404 bits16_t mlcap_general_flags_c; 1405 struct { 1406 #if defined(_BIT_FIELDS_HTOL) 1407 uint8_t mlcap_general_flags_d:6; 1408 uint8_t mlcap_general_port_type:2; 1409 #elif defined(_BIT_FIELDS_LTOH) 1410 uint8_t mlcap_general_port_type:2; 1411 uint8_t mlcap_general_flags_d:6; 1412 #endif 1413 }; 1414 uint8_t mlcap_general_num_ports; 1415 1416 struct { 1417 #if defined(_BIT_FIELDS_HTOL) 1418 uint8_t mlcap_general_rsvd13:3; 1419 uint8_t mlcap_general_log_max_msg:5; 1420 #elif defined(_BIT_FIELDS_LTOH) 1421 uint8_t mlcap_general_log_max_msg:5; 1422 uint8_t mlcap_general_rsvd13:3; 1423 #endif 1424 }; 1425 uint8_t mlcap_general_max_tc; 1426 bits16_t mlcap_general_flags_d_wol; 1427 1428 uint16be_t mlcap_general_state_rate_support; 1429 uint8_t mlcap_general_rsvd14[1]; 1430 struct { 1431 #if defined(_BIT_FIELDS_HTOL) 1432 uint8_t mlcap_general_rsvd15:4; 1433 uint8_t mlcap_general_cqe_version:4; 1434 #elif defined(_BIT_FIELDS_LTOH) 1435 uint8_t mlcap_general_cqe_version:4; 1436 uint8_t mlcap_general_rsvd15:4; 1437 #endif 1438 }; 1439 1440 uint32be_t mlcap_general_flags_e; 1441 1442 uint32be_t mlcap_general_flags_f; 1443 1444 uint8_t mlcap_general_rsvd16[1]; 1445 uint8_t mlcap_general_uar_sz; 1446 uint8_t mlcap_general_cnak; 1447 uint8_t mlcap_general_log_pg_sz; 1448 uint8_t mlcap_general_rsvd17[32]; 1449 bits8_t mlcap_general_log_max_rq_flags; 1450 uint8_t mlcap_general_log_max_sq; 1451 uint8_t mlcap_general_log_max_tir; 1452 uint8_t mlcap_general_log_max_tis; 1453 } mlxcx_hca_cap_general_caps_t; 1454 1455 typedef enum { 1456 MLXCX_ETH_CAP_TUNNEL_STATELESS_VXLAN = 1 << 0, 1457 MLXCX_ETH_CAP_TUNNEL_STATELESS_GRE = 1 << 1, 1458 MLXCX_ETH_CAP_TUNNEL_LSO_CONST_OUT_IP_ID = 1 << 4, 1459 MLXCX_ETH_CAP_SCATTER_FCS = 1 << 6, 1460 MLXCX_ETH_CAP_REG_UMR_SQ = 1 << 7, 1461 MLXCX_ETH_CAP_SELF_LB_UC = 1 << 21, 1462 MLXCX_ETH_CAP_SELF_LB_MC = 1 << 22, 1463 MLXCX_ETH_CAP_SELF_LB_EN_MODIFIABLE = 1 << 23, 1464 MLXCX_ETH_CAP_WQE_VLAN_INSERT = 1 << 24, 1465 MLXCX_ETH_CAP_LRO_TIME_STAMP = 1 << 27, 1466 MLXCX_ETH_CAP_LRO_PSH_FLAG = 1 << 28, 1467 MLXCX_ETH_CAP_LRO_CAP = 1 << 29, 1468 MLXCX_ETH_CAP_VLAN_STRIP = 1 << 30, 1469 MLXCX_ETH_CAP_CSUM_CAP = 1UL << 31 1470 } mlxcx_hca_eth_cap_flags_t; 1471 1472 /* CSTYLED */ 1473 #define MLXCX_ETH_CAP_RSS_IND_TBL_CAP (bitdef_t){8, 0x00000f00} 1474 /* CSTYLED */ 1475 #define MLXCX_ETH_CAP_WQE_INLINE_MODE (bitdef_t){12, 0x00003000} 1476 /* CSTYLED */ 1477 #define MLXCX_ETH_CAP_MULTI_PKT_SEND_WQE (bitdef_t){14, 0x0000c000} 1478 /* CSTYLED */ 1479 #define MLXCX_ETH_CAP_MAX_LSO_CAP (bitdef_t){16, 0x001f0000} 1480 /* CSTYLED */ 1481 #define MLXCX_ETH_CAP_LRO_MAX_MSG_SZ_MODE (bitdef_t){25, 0x06000000} 1482 1483 typedef struct { 1484 bits32_t mlcap_eth_flags; 1485 uint8_t mlcap_eth_rsvd[6]; 1486 uint16be_t mlcap_eth_lro_min_mss_size; 1487 uint8_t mlcap_eth_rsvd2[36]; 1488 uint32be_t mlcap_eth_lro_timer_supported_periods[4]; 1489 } mlxcx_hca_cap_eth_caps_t; 1490 1491 typedef enum { 1492 MLXCX_FLOW_CAP_PROPS_DECAP = 1 << 23, 1493 MLXCX_FLOW_CAP_PROPS_ENCAP = 1 << 24, 1494 MLXCX_FLOW_CAP_PROPS_MODIFY_TBL = 1 << 25, 1495 MLXCX_FLOW_CAP_PROPS_MISS_TABLE = 1 << 26, 1496 MLXCX_FLOW_CAP_PROPS_MODIFY_ROOT_TBL = 1 << 27, 1497 MLXCX_FLOW_CAP_PROPS_MODIFY = 1 << 28, 1498 MLXCX_FLOW_CAP_PROPS_COUNTER = 1 << 29, 1499 MLXCX_FLOW_CAP_PROPS_TAG = 1 << 30, 1500 MLXCX_FLOW_CAP_PROPS_SUPPORT = 1UL << 31 1501 } mlxcx_hca_cap_flow_cap_props_flags_t; 1502 1503 typedef struct { 1504 bits32_t mlcap_flow_prop_flags; 1505 uint8_t mlcap_flow_prop_log_max_ft_size; 1506 uint8_t mlcap_flow_prop_rsvd[2]; 1507 uint8_t mlcap_flow_prop_max_ft_level; 1508 uint8_t mlcap_flow_prop_rsvd2[7]; 1509 uint8_t mlcap_flow_prop_log_max_ft_num; 1510 uint8_t mlcap_flow_prop_rsvd3[2]; 1511 uint8_t mlcap_flow_prop_log_max_flow_counter; 1512 uint8_t mlcap_flow_prop_log_max_destination; 1513 uint8_t mlcap_flow_prop_rsvd4[3]; 1514 uint8_t mlcap_flow_prop_log_max_flow; 1515 uint8_t mlcap_flow_prop_rsvd5[8]; 1516 bits32_t mlcap_flow_prop_support[4]; 1517 bits32_t mlcap_flow_prop_bitmask[4]; 1518 } mlxcx_hca_cap_flow_cap_props_t; 1519 1520 typedef struct { 1521 bits32_t mlcap_flow_flags; 1522 uint8_t mlcap_flow_rsvd[60]; 1523 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx; 1524 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_rdma; 1525 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_sniffer; 1526 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx; 1527 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_rdma; 1528 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_sniffer; 1529 } mlxcx_hca_cap_flow_caps_t; 1530 1531 /* 1532 * Size of a buffer that is required to hold the output data. 1533 */ 1534 #define MLXCX_HCA_CAP_SIZE 0x1000 1535 1536 typedef struct { 1537 mlxcx_cmd_in_t mlxi_query_hca_cap_head; 1538 uint8_t mlxi_query_hca_cap_rsvd[8]; 1539 } mlxcx_cmd_query_hca_cap_in_t; 1540 1541 typedef struct { 1542 mlxcx_cmd_out_t mlxo_query_hca_cap_head; 1543 uint8_t mlxo_query_hca_cap_rsvd[8]; 1544 uint8_t mlxo_query_hca_cap_data[MLXCX_HCA_CAP_SIZE]; 1545 } mlxcx_cmd_query_hca_cap_out_t; 1546 1547 typedef struct { 1548 mlxcx_cmd_in_t mlxi_set_driver_version_head; 1549 uint8_t mlxi_set_driver_version_rsvd[8]; 1550 char mlxi_set_driver_version_version[64]; 1551 } mlxcx_cmd_set_driver_version_in_t; 1552 1553 typedef struct { 1554 mlxcx_cmd_out_t mlxo_set_driver_version_head; 1555 uint8_t mlxo_set_driver_version_rsvd[8]; 1556 } mlxcx_cmd_set_driver_version_out_t; 1557 1558 typedef struct { 1559 mlxcx_cmd_in_t mlxi_alloc_uar_head; 1560 uint8_t mlxi_alloc_uar_rsvd[8]; 1561 } mlxcx_cmd_alloc_uar_in_t; 1562 1563 typedef struct { 1564 mlxcx_cmd_out_t mlxo_alloc_uar_head; 1565 uint8_t mlxo_alloc_uar_rsvd; 1566 uint24be_t mlxo_alloc_uar_uar; 1567 uint8_t mlxo_alloc_uar_rsvd2[4]; 1568 } mlxcx_cmd_alloc_uar_out_t; 1569 1570 typedef struct { 1571 mlxcx_cmd_in_t mlxi_dealloc_uar_head; 1572 uint8_t mlxi_dealloc_uar_rsvd; 1573 uint24be_t mlxi_dealloc_uar_uar; 1574 uint8_t mlxi_dealloc_uar_rsvd2[4]; 1575 } mlxcx_cmd_dealloc_uar_in_t; 1576 1577 typedef struct { 1578 mlxcx_cmd_out_t mlxo_dealloc_uar_head; 1579 uint8_t mlxo_dealloc_uar_rsvd[8]; 1580 } mlxcx_cmd_dealloc_uar_out_t; 1581 1582 /* 1583 * This is an artificial limit that we're imposing on our actions. 1584 */ 1585 #define MLXCX_CREATE_QUEUE_MAX_PAGES 128 1586 1587 typedef struct { 1588 mlxcx_cmd_in_t mlxi_create_eq_head; 1589 uint8_t mlxi_create_eq_rsvd[8]; 1590 mlxcx_eventq_ctx_t mlxi_create_eq_context; 1591 uint8_t mlxi_create_eq_rsvd2[8]; 1592 uint64be_t mlxi_create_eq_event_bitmask; 1593 uint8_t mlxi_create_eq_rsvd3[176]; 1594 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1595 } mlxcx_cmd_create_eq_in_t; 1596 1597 typedef struct { 1598 mlxcx_cmd_out_t mlxo_create_eq_head; 1599 uint8_t mlxo_create_eq_rsvd[3]; 1600 uint8_t mlxo_create_eq_eqn; 1601 uint8_t mlxo_create_eq_rsvd2[4]; 1602 } mlxcx_cmd_create_eq_out_t; 1603 1604 typedef struct { 1605 mlxcx_cmd_in_t mlxi_query_eq_head; 1606 uint8_t mlxi_query_eq_rsvd[3]; 1607 uint8_t mlxi_query_eq_eqn; 1608 uint8_t mlxi_query_eq_rsvd2[4]; 1609 } mlxcx_cmd_query_eq_in_t; 1610 1611 typedef struct { 1612 mlxcx_cmd_out_t mlxo_query_eq_head; 1613 uint8_t mlxo_query_eq_rsvd[8]; 1614 mlxcx_eventq_ctx_t mlxo_query_eq_context; 1615 uint8_t mlxi_query_eq_rsvd2[8]; 1616 uint64be_t mlxi_query_eq_event_bitmask; 1617 uint8_t mlxi_query_eq_rsvd3[176]; 1618 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1619 } mlxcx_cmd_query_eq_out_t; 1620 1621 typedef struct { 1622 mlxcx_cmd_in_t mlxi_destroy_eq_head; 1623 uint8_t mlxi_destroy_eq_rsvd[3]; 1624 uint8_t mlxi_destroy_eq_eqn; 1625 uint8_t mlxi_destroy_eq_rsvd2[4]; 1626 } mlxcx_cmd_destroy_eq_in_t; 1627 1628 typedef struct { 1629 mlxcx_cmd_out_t mlxo_destroy_eq_head; 1630 uint8_t mlxo_destroy_eq_rsvd[8]; 1631 } mlxcx_cmd_destroy_eq_out_t; 1632 1633 typedef struct { 1634 mlxcx_cmd_in_t mlxi_alloc_pd_head; 1635 uint8_t mlxi_alloc_pd_rsvd[8]; 1636 } mlxcx_cmd_alloc_pd_in_t; 1637 1638 typedef struct { 1639 mlxcx_cmd_out_t mlxo_alloc_pd_head; 1640 uint8_t mlxo_alloc_pd_rsvd; 1641 uint24be_t mlxo_alloc_pd_pdn; 1642 uint8_t mlxo_alloc_pd_rsvd2[4]; 1643 } mlxcx_cmd_alloc_pd_out_t; 1644 1645 typedef struct { 1646 mlxcx_cmd_in_t mlxi_dealloc_pd_head; 1647 uint8_t mlxi_dealloc_pd_rsvd; 1648 uint24be_t mlxi_dealloc_pd_pdn; 1649 uint8_t mlxi_dealloc_pd_rsvd2[4]; 1650 } mlxcx_cmd_dealloc_pd_in_t; 1651 1652 typedef struct { 1653 mlxcx_cmd_out_t mlxo_dealloc_pd_head; 1654 uint8_t mlxo_dealloc_pd_rsvd[8]; 1655 } mlxcx_cmd_dealloc_pd_out_t; 1656 1657 typedef struct { 1658 mlxcx_cmd_in_t mlxi_alloc_tdom_head; 1659 uint8_t mlxi_alloc_tdom_rsvd[8]; 1660 } mlxcx_cmd_alloc_tdom_in_t; 1661 1662 typedef struct { 1663 mlxcx_cmd_out_t mlxo_alloc_tdom_head; 1664 uint8_t mlxo_alloc_tdom_rsvd; 1665 uint24be_t mlxo_alloc_tdom_tdomn; 1666 uint8_t mlxo_alloc_tdom_rsvd2[4]; 1667 } mlxcx_cmd_alloc_tdom_out_t; 1668 1669 typedef struct { 1670 mlxcx_cmd_in_t mlxi_dealloc_tdom_head; 1671 uint8_t mlxi_dealloc_tdom_rsvd; 1672 uint24be_t mlxi_dealloc_tdom_tdomn; 1673 uint8_t mlxi_dealloc_tdom_rsvd2[4]; 1674 } mlxcx_cmd_dealloc_tdom_in_t; 1675 1676 typedef struct { 1677 mlxcx_cmd_out_t mlxo_dealloc_tdom_head; 1678 uint8_t mlxo_dealloc_tdom_rsvd[8]; 1679 } mlxcx_cmd_dealloc_tdom_out_t; 1680 1681 typedef struct { 1682 mlxcx_cmd_in_t mlxi_create_tir_head; 1683 uint8_t mlxi_create_tir_rsvd[24]; 1684 mlxcx_tir_ctx_t mlxi_create_tir_context; 1685 } mlxcx_cmd_create_tir_in_t; 1686 1687 typedef struct { 1688 mlxcx_cmd_out_t mlxo_create_tir_head; 1689 uint8_t mlxo_create_tir_rsvd; 1690 uint24be_t mlxo_create_tir_tirn; 1691 uint8_t mlxo_create_tir_rsvd2[4]; 1692 } mlxcx_cmd_create_tir_out_t; 1693 1694 typedef struct { 1695 mlxcx_cmd_in_t mlxi_destroy_tir_head; 1696 uint8_t mlxi_destroy_tir_rsvd; 1697 uint24be_t mlxi_destroy_tir_tirn; 1698 uint8_t mlxi_destroy_tir_rsvd2[4]; 1699 } mlxcx_cmd_destroy_tir_in_t; 1700 1701 typedef struct { 1702 mlxcx_cmd_out_t mlxo_destroy_tir_head; 1703 uint8_t mlxo_destroy_tir_rsvd[8]; 1704 } mlxcx_cmd_destroy_tir_out_t; 1705 1706 typedef struct { 1707 mlxcx_cmd_in_t mlxi_create_tis_head; 1708 uint8_t mlxi_create_tis_rsvd[24]; 1709 mlxcx_tis_ctx_t mlxi_create_tis_context; 1710 } mlxcx_cmd_create_tis_in_t; 1711 1712 typedef struct { 1713 mlxcx_cmd_out_t mlxo_create_tis_head; 1714 uint8_t mlxo_create_tis_rsvd; 1715 uint24be_t mlxo_create_tis_tisn; 1716 uint8_t mlxo_create_tis_rsvd2[4]; 1717 } mlxcx_cmd_create_tis_out_t; 1718 1719 typedef struct { 1720 mlxcx_cmd_in_t mlxi_destroy_tis_head; 1721 uint8_t mlxi_destroy_tis_rsvd; 1722 uint24be_t mlxi_destroy_tis_tisn; 1723 uint8_t mlxi_destroy_tis_rsvd2[4]; 1724 } mlxcx_cmd_destroy_tis_in_t; 1725 1726 typedef struct { 1727 mlxcx_cmd_out_t mlxo_destroy_tis_head; 1728 uint8_t mlxo_destroy_tis_rsvd[8]; 1729 } mlxcx_cmd_destroy_tis_out_t; 1730 1731 typedef struct { 1732 mlxcx_cmd_in_t mlxi_query_special_ctxs_head; 1733 uint8_t mlxi_query_special_ctxs_rsvd[8]; 1734 } mlxcx_cmd_query_special_ctxs_in_t; 1735 1736 typedef struct { 1737 mlxcx_cmd_out_t mlxo_query_special_ctxs_head; 1738 uint8_t mlxo_query_special_ctxs_rsvd[4]; 1739 uint32be_t mlxo_query_special_ctxs_resd_lkey; 1740 uint32be_t mlxo_query_special_ctxs_null_mkey; 1741 uint8_t mlxo_query_special_ctxs_rsvd2[12]; 1742 } mlxcx_cmd_query_special_ctxs_out_t; 1743 1744 typedef enum { 1745 MLXCX_VPORT_TYPE_VNIC = 0x0, 1746 MLXCX_VPORT_TYPE_ESWITCH = 0x1, 1747 MLXCX_VPORT_TYPE_UPLINK = 0x2, 1748 } mlxcx_cmd_vport_op_mod_t; 1749 1750 typedef struct { 1751 mlxcx_cmd_in_t mlxi_query_nic_vport_ctx_head; 1752 uint8_t mlxi_query_nic_vport_ctx_other_vport; 1753 uint8_t mlxi_query_nic_vport_ctx_rsvd[1]; 1754 uint16be_t mlxi_query_nic_vport_ctx_vport_number; 1755 uint8_t mlxi_query_nic_vport_ctx_allowed_list_type; 1756 uint8_t mlxi_query_nic_vport_ctx_rsvd2[3]; 1757 } mlxcx_cmd_query_nic_vport_ctx_in_t; 1758 1759 typedef struct { 1760 mlxcx_cmd_out_t mlxo_query_nic_vport_ctx_head; 1761 uint8_t mlxo_query_nic_vport_ctx_rsvd[8]; 1762 mlxcx_nic_vport_ctx_t mlxo_query_nic_vport_ctx_context; 1763 } mlxcx_cmd_query_nic_vport_ctx_out_t; 1764 1765 typedef enum { 1766 MLXCX_MODIFY_NIC_VPORT_CTX_ROCE_EN = 1 << 1, 1767 MLXCX_MODIFY_NIC_VPORT_CTX_ADDR_LIST = 1 << 2, 1768 MLXCX_MODIFY_NIC_VPORT_CTX_PERM_ADDR = 1 << 3, 1769 MLXCX_MODIFY_NIC_VPORT_CTX_PROMISC = 1 << 4, 1770 MLXCX_MODIFY_NIC_VPORT_CTX_EVENT = 1 << 5, 1771 MLXCX_MODIFY_NIC_VPORT_CTX_MTU = 1 << 6, 1772 MLXCX_MODIFY_NIC_VPORT_CTX_WQE_INLINE = 1 << 7, 1773 MLXCX_MODIFY_NIC_VPORT_CTX_PORT_GUID = 1 << 8, 1774 MLXCX_MODIFY_NIC_VPORT_CTX_NODE_GUID = 1 << 9, 1775 } mlxcx_modify_nic_vport_ctx_fields_t; 1776 1777 typedef struct { 1778 mlxcx_cmd_in_t mlxi_modify_nic_vport_ctx_head; 1779 uint8_t mlxi_modify_nic_vport_ctx_other_vport; 1780 uint8_t mlxi_modify_nic_vport_ctx_rsvd[1]; 1781 uint16be_t mlxi_modify_nic_vport_ctx_vport_number; 1782 uint32be_t mlxi_modify_nic_vport_ctx_field_select; 1783 uint8_t mlxi_modify_nic_vport_ctx_rsvd2[240]; 1784 mlxcx_nic_vport_ctx_t mlxi_modify_nic_vport_ctx_context; 1785 } mlxcx_cmd_modify_nic_vport_ctx_in_t; 1786 1787 typedef struct { 1788 mlxcx_cmd_out_t mlxo_modify_nic_vport_ctx_head; 1789 uint8_t mlxo_modify_nic_vport_ctx_rsvd[8]; 1790 } mlxcx_cmd_modify_nic_vport_ctx_out_t; 1791 1792 typedef struct { 1793 mlxcx_cmd_in_t mlxi_query_vport_state_head; 1794 uint8_t mlxi_query_vport_state_other_vport; 1795 uint8_t mlxi_query_vport_state_rsvd[1]; 1796 uint16be_t mlxi_query_vport_state_vport_number; 1797 uint8_t mlxi_query_vport_state_rsvd2[4]; 1798 } mlxcx_cmd_query_vport_state_in_t; 1799 1800 /* CSTYLED */ 1801 #define MLXCX_VPORT_ADMIN_STATE (bitdef_t){4, 0xF0} 1802 /* CSTYLED */ 1803 #define MLXCX_VPORT_OPER_STATE (bitdef_t){0, 0x0F} 1804 1805 typedef enum { 1806 MLXCX_VPORT_OPER_STATE_DOWN = 0x0, 1807 MLXCX_VPORT_OPER_STATE_UP = 0x1, 1808 } mlxcx_vport_oper_state_t; 1809 1810 typedef enum { 1811 MLXCX_VPORT_ADMIN_STATE_DOWN = 0x0, 1812 MLXCX_VPORT_ADMIN_STATE_UP = 0x1, 1813 MLXCX_VPORT_ADMIN_STATE_FOLLOW = 0x2, 1814 } mlxcx_vport_admin_state_t; 1815 1816 typedef struct { 1817 mlxcx_cmd_out_t mlxo_query_vport_state_head; 1818 uint8_t mlxo_query_vport_state_rsvd[4]; 1819 uint16be_t mlxo_query_vport_state_max_tx_speed; 1820 uint8_t mlxo_query_vport_state_rsvd2[1]; 1821 uint8_t mlxo_query_vport_state_state; 1822 } mlxcx_cmd_query_vport_state_out_t; 1823 1824 typedef struct { 1825 mlxcx_cmd_in_t mlxi_create_cq_head; 1826 uint8_t mlxi_create_cq_rsvd[8]; 1827 mlxcx_completionq_ctx_t mlxi_create_cq_context; 1828 uint8_t mlxi_create_cq_rsvd2[192]; 1829 uint64be_t mlxi_create_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1830 } mlxcx_cmd_create_cq_in_t; 1831 1832 typedef struct { 1833 mlxcx_cmd_out_t mlxo_create_cq_head; 1834 uint8_t mlxo_create_cq_rsvd; 1835 uint24be_t mlxo_create_cq_cqn; 1836 uint8_t mlxo_create_cq_rsvd2[4]; 1837 } mlxcx_cmd_create_cq_out_t; 1838 1839 typedef struct { 1840 mlxcx_cmd_in_t mlxi_destroy_cq_head; 1841 uint8_t mlxi_destroy_cq_rsvd; 1842 uint24be_t mlxi_destroy_cq_cqn; 1843 uint8_t mlxi_destroy_cq_rsvd2[4]; 1844 } mlxcx_cmd_destroy_cq_in_t; 1845 1846 typedef struct { 1847 mlxcx_cmd_out_t mlxo_destroy_cq_head; 1848 uint8_t mlxo_destroy_cq_rsvd[8]; 1849 } mlxcx_cmd_destroy_cq_out_t; 1850 1851 typedef struct { 1852 mlxcx_cmd_in_t mlxi_query_cq_head; 1853 uint8_t mlxi_query_cq_rsvd; 1854 uint24be_t mlxi_query_cq_cqn; 1855 uint8_t mlxi_query_cq_rsvd2[4]; 1856 } mlxcx_cmd_query_cq_in_t; 1857 1858 typedef struct { 1859 mlxcx_cmd_out_t mlxo_query_cq_head; 1860 uint8_t mlxo_query_cq_rsvd[8]; 1861 mlxcx_completionq_ctx_t mlxo_query_cq_context; 1862 uint8_t mlxo_query_cq_rsvd2[192]; 1863 uint64be_t mlxo_query_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1864 } mlxcx_cmd_query_cq_out_t; 1865 1866 typedef struct { 1867 mlxcx_cmd_in_t mlxi_create_rq_head; 1868 uint8_t mlxi_create_rq_rsvd[24]; 1869 mlxcx_rq_ctx_t mlxi_create_rq_context; 1870 } mlxcx_cmd_create_rq_in_t; 1871 1872 typedef struct { 1873 mlxcx_cmd_out_t mlxo_create_rq_head; 1874 uint8_t mlxo_create_rq_rsvd; 1875 uint24be_t mlxo_create_rq_rqn; 1876 uint8_t mlxo_create_rq_rsvd2[4]; 1877 } mlxcx_cmd_create_rq_out_t; 1878 1879 /* CSTYLED */ 1880 #define MLXCX_CMD_MODIFY_RQ_STATE (bitdef_t){ \ 1881 .bit_shift = 4, .bit_mask = 0xF0 } 1882 1883 typedef enum { 1884 MLXCX_MODIFY_RQ_SCATTER_FCS = 1 << 2, 1885 MLXCX_MODIFY_RQ_VSD = 1 << 1, 1886 MLXCX_MODIFY_RQ_COUNTER_SET_ID = 1 << 3, 1887 MLXCX_MODIFY_RQ_LWM = 1 << 0 1888 } mlxcx_cmd_modify_rq_bitmask_t; 1889 1890 typedef enum { 1891 MLXCX_RQ_STATE_RST = 0x0, 1892 MLXCX_RQ_STATE_RDY = 0x1, 1893 MLXCX_RQ_STATE_ERR = 0x3 1894 } mlxcx_rq_state_t; 1895 1896 typedef struct { 1897 mlxcx_cmd_in_t mlxi_modify_rq_head; 1898 bits8_t mlxi_modify_rq_state; 1899 uint24be_t mlxi_modify_rq_rqn; 1900 uint8_t mlxi_modify_rq_rsvd[4]; 1901 uint64be_t mlxi_modify_rq_bitmask; 1902 uint8_t mlxi_modify_rq_rsvd2[8]; 1903 mlxcx_rq_ctx_t mlxi_modify_rq_context; 1904 } mlxcx_cmd_modify_rq_in_t; 1905 1906 typedef struct { 1907 mlxcx_cmd_out_t mlxo_modify_rq_head; 1908 uint8_t mlxo_modify_rq_rsvd[8]; 1909 } mlxcx_cmd_modify_rq_out_t; 1910 1911 typedef struct { 1912 mlxcx_cmd_in_t mlxi_query_rq_head; 1913 uint8_t mlxi_query_rq_rsvd; 1914 uint24be_t mlxi_query_rq_rqn; 1915 uint8_t mlxi_query_rq_rsvd2[4]; 1916 } mlxcx_cmd_query_rq_in_t; 1917 1918 typedef struct { 1919 mlxcx_cmd_out_t mlxo_query_rq_head; 1920 uint8_t mlxo_query_rq_rsvd[24]; 1921 mlxcx_rq_ctx_t mlxo_query_rq_context; 1922 } mlxcx_cmd_query_rq_out_t; 1923 1924 typedef struct { 1925 mlxcx_cmd_in_t mlxi_destroy_rq_head; 1926 uint8_t mlxi_destroy_rq_rsvd; 1927 uint24be_t mlxi_destroy_rq_rqn; 1928 uint8_t mlxi_destroy_rq_rsvd2[4]; 1929 } mlxcx_cmd_destroy_rq_in_t; 1930 1931 typedef struct { 1932 mlxcx_cmd_out_t mlxo_destroy_rq_head; 1933 uint8_t mlxo_destroy_rq_rsvd[8]; 1934 } mlxcx_cmd_destroy_rq_out_t; 1935 1936 typedef struct { 1937 mlxcx_cmd_in_t mlxi_create_sq_head; 1938 uint8_t mlxi_create_sq_rsvd[24]; 1939 mlxcx_sq_ctx_t mlxi_create_sq_context; 1940 } mlxcx_cmd_create_sq_in_t; 1941 1942 typedef struct { 1943 mlxcx_cmd_out_t mlxo_create_sq_head; 1944 uint8_t mlxo_create_sq_rsvd; 1945 uint24be_t mlxo_create_sq_sqn; 1946 uint8_t mlxo_create_sq_rsvd2[4]; 1947 } mlxcx_cmd_create_sq_out_t; 1948 1949 /* CSTYLED */ 1950 #define MLXCX_CMD_MODIFY_SQ_STATE (bitdef_t){ \ 1951 .bit_shift = 4, .bit_mask = 0xF0 } 1952 1953 typedef enum { 1954 MLXCX_MODIFY_SQ_PACKET_PACING_INDEX = 1 << 0, 1955 } mlxcx_cmd_modify_sq_bitmask_t; 1956 1957 typedef enum { 1958 MLXCX_SQ_STATE_RST = 0x0, 1959 MLXCX_SQ_STATE_RDY = 0x1, 1960 MLXCX_SQ_STATE_ERR = 0x3 1961 } mlxcx_sq_state_t; 1962 1963 typedef struct { 1964 mlxcx_cmd_in_t mlxi_modify_sq_head; 1965 bits8_t mlxi_modify_sq_state; 1966 uint24be_t mlxi_modify_sq_sqn; 1967 uint8_t mlxi_modify_sq_rsvd[4]; 1968 uint64be_t mlxi_modify_sq_bitmask; 1969 uint8_t mlxi_modify_sq_rsvd2[8]; 1970 mlxcx_sq_ctx_t mlxi_modify_sq_context; 1971 } mlxcx_cmd_modify_sq_in_t; 1972 1973 typedef struct { 1974 mlxcx_cmd_out_t mlxo_modify_sq_head; 1975 uint8_t mlxo_modify_sq_rsvd[8]; 1976 } mlxcx_cmd_modify_sq_out_t; 1977 1978 typedef struct { 1979 mlxcx_cmd_in_t mlxi_query_sq_head; 1980 uint8_t mlxi_query_sq_rsvd; 1981 uint24be_t mlxi_query_sq_sqn; 1982 uint8_t mlxi_query_sq_rsvd2[4]; 1983 } mlxcx_cmd_query_sq_in_t; 1984 1985 typedef struct { 1986 mlxcx_cmd_out_t mlxo_query_sq_head; 1987 uint8_t mlxo_query_sq_rsvd[24]; 1988 mlxcx_sq_ctx_t mlxo_query_sq_context; 1989 } mlxcx_cmd_query_sq_out_t; 1990 1991 typedef struct { 1992 mlxcx_cmd_in_t mlxi_destroy_sq_head; 1993 uint8_t mlxi_destroy_sq_rsvd; 1994 uint24be_t mlxi_destroy_sq_sqn; 1995 uint8_t mlxi_destroy_sq_rsvd2[4]; 1996 } mlxcx_cmd_destroy_sq_in_t; 1997 1998 typedef struct { 1999 mlxcx_cmd_out_t mlxo_destroy_sq_head; 2000 uint8_t mlxo_destroy_sq_rsvd[8]; 2001 } mlxcx_cmd_destroy_sq_out_t; 2002 2003 typedef struct { 2004 mlxcx_cmd_in_t mlxi_create_rqt_head; 2005 uint8_t mlxi_create_rqt_rsvd[24]; 2006 mlxcx_rqtable_ctx_t mlxi_create_rqt_context; 2007 } mlxcx_cmd_create_rqt_in_t; 2008 2009 typedef struct { 2010 mlxcx_cmd_out_t mlxo_create_rqt_head; 2011 uint8_t mlxo_create_rqt_rsvd; 2012 uint24be_t mlxo_create_rqt_rqtn; 2013 uint8_t mlxo_create_rqt_rsvd2[4]; 2014 } mlxcx_cmd_create_rqt_out_t; 2015 2016 typedef struct { 2017 mlxcx_cmd_in_t mlxi_destroy_rqt_head; 2018 uint8_t mlxi_destroy_rqt_rsvd; 2019 uint24be_t mlxi_destroy_rqt_rqtn; 2020 uint8_t mlxi_destroy_rqt_rsvd2[4]; 2021 } mlxcx_cmd_destroy_rqt_in_t; 2022 2023 typedef struct { 2024 mlxcx_cmd_out_t mlxo_destroy_rqt_head; 2025 uint8_t mlxo_destroy_rqt_rsvd[8]; 2026 } mlxcx_cmd_destroy_rqt_out_t; 2027 2028 typedef enum { 2029 MLXCX_FLOW_TABLE_NIC_RX = 0x0, 2030 MLXCX_FLOW_TABLE_NIC_TX = 0x1, 2031 MLXCX_FLOW_TABLE_ESW_OUT = 0x2, 2032 MLXCX_FLOW_TABLE_ESW_IN = 0x3, 2033 MLXCX_FLOW_TABLE_ESW_FDB = 0x4, 2034 MLXCX_FLOW_TABLE_NIC_RX_SNIFF = 0x5, 2035 MLXCX_FLOW_TABLE_NIC_TX_SNIFF = 0x6, 2036 MLXCX_FLOW_TABLE_NIC_RX_RDMA = 0x7, 2037 MLXCX_FLOW_TABLE_NIC_TX_RDMA = 0x8 2038 } mlxcx_flow_table_type_t; 2039 2040 typedef struct { 2041 mlxcx_cmd_in_t mlxi_create_flow_table_head; 2042 uint8_t mlxi_create_flow_table_other_vport; 2043 uint8_t mlxi_create_flow_table_rsvd; 2044 uint16be_t mlxi_create_flow_table_vport_number; 2045 uint8_t mlxi_create_flow_table_rsvd2[4]; 2046 uint8_t mlxi_create_flow_table_table_type; 2047 uint8_t mlxi_create_flow_table_rsvd3[7]; 2048 mlxcx_flow_table_ctx_t mlxi_create_flow_table_context; 2049 } mlxcx_cmd_create_flow_table_in_t; 2050 2051 typedef struct { 2052 mlxcx_cmd_out_t mlxo_create_flow_table_head; 2053 uint8_t mlxo_create_flow_table_rsvd; 2054 uint24be_t mlxo_create_flow_table_table_id; 2055 uint8_t mlxo_create_flow_table_rsvd2[4]; 2056 } mlxcx_cmd_create_flow_table_out_t; 2057 2058 typedef struct { 2059 mlxcx_cmd_in_t mlxi_destroy_flow_table_head; 2060 uint8_t mlxi_destroy_flow_table_other_vport; 2061 uint8_t mlxi_destroy_flow_table_rsvd; 2062 uint16be_t mlxi_destroy_flow_table_vport_number; 2063 uint8_t mlxi_destroy_flow_table_rsvd2[4]; 2064 uint8_t mlxi_destroy_flow_table_table_type; 2065 uint8_t mlxi_destroy_flow_table_rsvd3[4]; 2066 uint24be_t mlxi_destroy_flow_table_table_id; 2067 uint8_t mlxi_destroy_flow_table_rsvd4[4]; 2068 } mlxcx_cmd_destroy_flow_table_in_t; 2069 2070 typedef struct { 2071 mlxcx_cmd_out_t mlxo_destroy_flow_table_head; 2072 uint8_t mlxo_destroy_flow_table_rsvd[8]; 2073 } mlxcx_cmd_destroy_flow_table_out_t; 2074 2075 typedef struct { 2076 mlxcx_cmd_in_t mlxi_set_flow_table_root_head; 2077 uint8_t mlxi_set_flow_table_root_other_vport; 2078 uint8_t mlxi_set_flow_table_root_rsvd; 2079 uint16be_t mlxi_set_flow_table_root_vport_number; 2080 uint8_t mlxi_set_flow_table_root_rsvd2[4]; 2081 uint8_t mlxi_set_flow_table_root_table_type; 2082 uint8_t mlxi_set_flow_table_root_rsvd3[4]; 2083 uint24be_t mlxi_set_flow_table_root_table_id; 2084 uint8_t mlxi_set_flow_table_root_rsvd4[4]; 2085 uint8_t mlxi_set_flow_table_root_esw_owner_vhca_id_valid; 2086 uint8_t mlxi_set_flow_table_root_rsvd5; 2087 uint16be_t mlxi_set_flow_table_root_esw_owner_vhca_id; 2088 uint8_t mlxi_set_flow_table_root_rsvd6[32]; 2089 } mlxcx_cmd_set_flow_table_root_in_t; 2090 2091 typedef struct { 2092 mlxcx_cmd_out_t mlxo_set_flow_table_root_head; 2093 uint8_t mlxo_set_flow_table_root_rsvd[8]; 2094 } mlxcx_cmd_set_flow_table_root_out_t; 2095 2096 typedef enum { 2097 MLXCX_FLOW_GROUP_MATCH_OUTER_HDRS = 1 << 0, 2098 MLXCX_FLOW_GROUP_MATCH_MISC_PARAMS = 1 << 1, 2099 MLXCX_FLOW_GROUP_MATCH_INNER_HDRS = 1 << 2, 2100 } mlxcx_flow_group_match_criteria_t; 2101 2102 typedef struct { 2103 mlxcx_cmd_in_t mlxi_create_flow_group_head; 2104 uint8_t mlxi_create_flow_group_other_vport; 2105 uint8_t mlxi_create_flow_group_rsvd; 2106 uint16be_t mlxi_create_flow_group_vport_number; 2107 uint8_t mlxi_create_flow_group_rsvd2[4]; 2108 uint8_t mlxi_create_flow_group_table_type; 2109 uint8_t mlxi_create_flow_group_rsvd3[4]; 2110 uint24be_t mlxi_create_flow_group_table_id; 2111 uint8_t mlxi_create_flow_group_rsvd4[4]; 2112 uint32be_t mlxi_create_flow_group_start_flow_index; 2113 uint8_t mlxi_create_flow_group_rsvd5[4]; 2114 uint32be_t mlxi_create_flow_group_end_flow_index; 2115 uint8_t mlxi_create_flow_group_rsvd6[23]; 2116 uint8_t mlxi_create_flow_group_match_criteria_en; 2117 mlxcx_flow_match_t mlxi_create_flow_group_match_criteria; 2118 uint8_t mlxi_create_flow_group_rsvd7[448]; 2119 } mlxcx_cmd_create_flow_group_in_t; 2120 2121 typedef struct { 2122 mlxcx_cmd_out_t mlxo_create_flow_group_head; 2123 uint8_t mlxo_create_flow_group_rsvd; 2124 uint24be_t mlxo_create_flow_group_group_id; 2125 uint8_t mlxo_create_flow_group_rsvd2[4]; 2126 } mlxcx_cmd_create_flow_group_out_t; 2127 2128 typedef struct { 2129 mlxcx_cmd_in_t mlxi_destroy_flow_group_head; 2130 uint8_t mlxi_destroy_flow_group_other_vport; 2131 uint8_t mlxi_destroy_flow_group_rsvd; 2132 uint16be_t mlxi_destroy_flow_group_vport_number; 2133 uint8_t mlxi_destroy_flow_group_rsvd2[4]; 2134 uint8_t mlxi_destroy_flow_group_table_type; 2135 uint8_t mlxi_destroy_flow_group_rsvd3[4]; 2136 uint24be_t mlxi_destroy_flow_group_table_id; 2137 uint32be_t mlxi_destroy_flow_group_group_id; 2138 uint8_t mlxi_destroy_flow_group_rsvd4[36]; 2139 } mlxcx_cmd_destroy_flow_group_in_t; 2140 2141 typedef struct { 2142 mlxcx_cmd_out_t mlxo_destroy_flow_group_head; 2143 uint8_t mlxo_destroy_flow_group_rsvd[8]; 2144 } mlxcx_cmd_destroy_flow_group_out_t; 2145 2146 typedef enum { 2147 MLXCX_CMD_FLOW_ENTRY_SET_NEW = 0, 2148 MLXCX_CMD_FLOW_ENTRY_MODIFY = 1, 2149 } mlxcx_cmd_set_flow_table_entry_opmod_t; 2150 2151 typedef enum { 2152 MLXCX_CMD_FLOW_ENTRY_SET_ACTION = 1 << 0, 2153 MLXCX_CMD_FLOW_ENTRY_SET_FLOW_TAG = 1 << 1, 2154 MLXCX_CMD_FLOW_ENTRY_SET_DESTINATION = 1 << 2, 2155 MLXCX_CMD_FLOW_ENTRY_SET_COUNTERS = 1 << 3, 2156 MLXCX_CMD_FLOW_ENTRY_SET_ENCAP = 1 << 4 2157 } mlxcx_cmd_set_flow_table_entry_bitmask_t; 2158 2159 typedef struct { 2160 mlxcx_cmd_in_t mlxi_set_flow_table_entry_head; 2161 uint8_t mlxi_set_flow_table_entry_other_vport; 2162 uint8_t mlxi_set_flow_table_entry_rsvd; 2163 uint16be_t mlxi_set_flow_table_entry_vport_number; 2164 uint8_t mlxi_set_flow_table_entry_rsvd2[4]; 2165 uint8_t mlxi_set_flow_table_entry_table_type; 2166 uint8_t mlxi_set_flow_table_entry_rsvd3[4]; 2167 uint24be_t mlxi_set_flow_table_entry_table_id; 2168 uint8_t mlxi_set_flow_table_entry_rsvd4[3]; 2169 bits8_t mlxi_set_flow_table_entry_modify_bitmask; 2170 uint8_t mlxi_set_flow_table_entry_rsvd5[4]; 2171 uint32be_t mlxi_set_flow_table_entry_flow_index; 2172 uint8_t mlxi_set_flow_table_entry_rsvd6[28]; 2173 mlxcx_flow_entry_ctx_t mlxi_set_flow_table_entry_context; 2174 } mlxcx_cmd_set_flow_table_entry_in_t; 2175 2176 typedef struct { 2177 mlxcx_cmd_out_t mlxo_set_flow_table_entry_head; 2178 uint8_t mlxo_set_flow_table_entry_rsvd[8]; 2179 } mlxcx_cmd_set_flow_table_entry_out_t; 2180 2181 typedef struct { 2182 mlxcx_cmd_in_t mlxi_delete_flow_table_entry_head; 2183 uint8_t mlxi_delete_flow_table_entry_other_vport; 2184 uint8_t mlxi_delete_flow_table_entry_rsvd; 2185 uint16be_t mlxi_delete_flow_table_entry_vport_number; 2186 uint8_t mlxi_delete_flow_table_entry_rsvd2[4]; 2187 uint8_t mlxi_delete_flow_table_entry_table_type; 2188 uint8_t mlxi_delete_flow_table_entry_rsvd3[4]; 2189 uint24be_t mlxi_delete_flow_table_entry_table_id; 2190 uint8_t mlxi_delete_flow_table_entry_rsvd4[8]; 2191 uint32be_t mlxi_delete_flow_table_entry_flow_index; 2192 uint8_t mlxi_delete_flow_table_entry_rsvd5[28]; 2193 } mlxcx_cmd_delete_flow_table_entry_in_t; 2194 2195 typedef struct { 2196 mlxcx_cmd_out_t mlxo_delete_flow_table_entry_head; 2197 uint8_t mlxo_delete_flow_table_entry_rsvd[8]; 2198 } mlxcx_cmd_delete_flow_table_entry_out_t; 2199 2200 typedef enum { 2201 MLXCX_CMD_CONFIG_INT_MOD_READ = 1, 2202 MLXCX_CMD_CONFIG_INT_MOD_WRITE = 0 2203 } mlxcx_cmd_config_int_mod_opmod_t; 2204 2205 typedef struct { 2206 mlxcx_cmd_in_t mlxi_config_int_mod_head; 2207 uint16be_t mlxi_config_int_mod_min_delay; 2208 uint16be_t mlxi_config_int_mod_int_vector; 2209 uint8_t mlxi_config_int_mod_rsvd[4]; 2210 } mlxcx_cmd_config_int_mod_in_t; 2211 2212 typedef struct { 2213 mlxcx_cmd_out_t mlxo_config_int_mod_head; 2214 uint16be_t mlxo_config_int_mod_min_delay; 2215 uint16be_t mlxo_config_int_mod_int_vector; 2216 uint8_t mlxo_config_int_mod_rsvd[4]; 2217 } mlxcx_cmd_config_int_mod_out_t; 2218 2219 typedef struct { 2220 uint8_t mlrd_pmtu_rsvd; 2221 uint8_t mlrd_pmtu_local_port; 2222 uint8_t mlrd_pmtu_rsvd2[2]; 2223 2224 uint16be_t mlrd_pmtu_max_mtu; 2225 uint8_t mlrd_pmtu_rsvd3[2]; 2226 2227 uint16be_t mlrd_pmtu_admin_mtu; 2228 uint8_t mlrd_pmtu_rsvd4[2]; 2229 2230 uint16be_t mlrd_pmtu_oper_mtu; 2231 uint8_t mlrd_pmtu_rsvd5[2]; 2232 } mlxcx_reg_pmtu_t; 2233 2234 typedef enum { 2235 MLXCX_PORT_STATUS_UP = 1, 2236 MLXCX_PORT_STATUS_DOWN = 2, 2237 MLXCX_PORT_STATUS_UP_ONCE = 3, 2238 MLXCX_PORT_STATUS_DISABLED = 4, 2239 } mlxcx_port_status_t; 2240 2241 typedef enum { 2242 MLXCX_PAOS_ADMIN_ST_EN = 1UL << 31, 2243 } mlxcx_paos_flags_t; 2244 2245 typedef struct { 2246 uint8_t mlrd_paos_swid; 2247 uint8_t mlrd_paos_local_port; 2248 uint8_t mlrd_paos_admin_status; 2249 uint8_t mlrd_paos_oper_status; 2250 bits32_t mlrd_paos_flags; 2251 uint8_t mlrd_paos_rsvd[8]; 2252 } mlxcx_reg_paos_t; 2253 2254 typedef enum { 2255 MLXCX_PROTO_SGMII = 1 << 0, 2256 MLXCX_PROTO_1000BASE_KX = 1 << 1, 2257 MLXCX_PROTO_10GBASE_CX4 = 1 << 2, 2258 MLXCX_PROTO_10GBASE_KX4 = 1 << 3, 2259 MLXCX_PROTO_10GBASE_KR = 1 << 4, 2260 MLXCX_PROTO_UNKNOWN_1 = 1 << 5, 2261 MLXCX_PROTO_40GBASE_CR4 = 1 << 6, 2262 MLXCX_PROTO_40GBASE_KR4 = 1 << 7, 2263 MLXCX_PROTO_UNKNOWN_2 = 1 << 8, 2264 MLXCX_PROTO_SGMII_100BASE = 1 << 9, 2265 MLXCX_PROTO_UNKNOWN_3 = 1 << 10, 2266 MLXCX_PROTO_UNKNOWN_4 = 1 << 11, 2267 MLXCX_PROTO_10GBASE_CR = 1 << 12, 2268 MLXCX_PROTO_10GBASE_SR = 1 << 13, 2269 MLXCX_PROTO_10GBASE_ER_LR = 1 << 14, 2270 MLXCX_PROTO_40GBASE_SR4 = 1 << 15, 2271 MLXCX_PROTO_40GBASE_LR4_ER4 = 1 << 16, 2272 MLXCX_PROTO_UNKNOWN_5 = 1 << 17, 2273 MLXCX_PROTO_50GBASE_SR2 = 1 << 18, 2274 MLXCX_PROTO_UNKNOWN_6 = 1 << 19, 2275 MLXCX_PROTO_100GBASE_CR4 = 1 << 20, 2276 MLXCX_PROTO_100GBASE_SR4 = 1 << 21, 2277 MLXCX_PROTO_100GBASE_KR4 = 1 << 22, 2278 MLXCX_PROTO_UNKNOWN_7 = 1 << 23, 2279 MLXCX_PROTO_UNKNOWN_8 = 1 << 24, 2280 MLXCX_PROTO_UNKNOWN_9 = 1 << 25, 2281 MLXCX_PROTO_UNKNOWN_10 = 1 << 26, 2282 MLXCX_PROTO_25GBASE_CR = 1 << 27, 2283 MLXCX_PROTO_25GBASE_KR = 1 << 28, 2284 MLXCX_PROTO_25GBASE_SR = 1 << 29, 2285 MLXCX_PROTO_50GBASE_CR2 = 1 << 30, 2286 MLXCX_PROTO_50GBASE_KR2 = 1UL << 31, 2287 } mlxcx_eth_proto_t; 2288 2289 #define MLXCX_PROTO_100M MLXCX_PROTO_SGMII_100BASE 2290 2291 #define MLXCX_PROTO_1G (MLXCX_PROTO_1000BASE_KX | MLXCX_PROTO_SGMII) 2292 2293 #define MLXCX_PROTO_10G (MLXCX_PROTO_10GBASE_CX4 | \ 2294 MLXCX_PROTO_10GBASE_KX4 | MLXCX_PROTO_10GBASE_KR | \ 2295 MLXCX_PROTO_10GBASE_CR | MLXCX_PROTO_10GBASE_SR | \ 2296 MLXCX_PROTO_10GBASE_ER_LR) 2297 2298 #define MLXCX_PROTO_25G (MLXCX_PROTO_25GBASE_CR | \ 2299 MLXCX_PROTO_25GBASE_KR | MLXCX_PROTO_25GBASE_SR) 2300 2301 #define MLXCX_PROTO_40G (MLXCX_PROTO_40GBASE_SR4 | \ 2302 MLXCX_PROTO_40GBASE_LR4_ER4 | MLXCX_PROTO_40GBASE_CR4 | \ 2303 MLXCX_PROTO_40GBASE_KR4) 2304 2305 #define MLXCX_PROTO_50G (MLXCX_PROTO_50GBASE_CR2 | \ 2306 MLXCX_PROTO_50GBASE_KR2 | MLXCX_PROTO_50GBASE_SR2) 2307 2308 #define MLXCX_PROTO_100G (MLXCX_PROTO_100GBASE_CR4 | \ 2309 MLXCX_PROTO_100GBASE_SR4 | MLXCX_PROTO_100GBASE_KR4) 2310 2311 typedef enum { 2312 MLXCX_AUTONEG_DISABLE_CAP = 1 << 5, 2313 MLXCX_AUTONEG_DISABLE = 1 << 6 2314 } mlxcx_autoneg_flags_t; 2315 2316 typedef enum { 2317 MLXCX_PTYS_PROTO_MASK_IB = 1 << 0, 2318 MLXCX_PTYS_PROTO_MASK_ETH = 1 << 2, 2319 } mlxcx_reg_ptys_proto_mask_t; 2320 2321 typedef struct { 2322 bits8_t mlrd_ptys_autoneg_flags; 2323 uint8_t mlrd_ptys_local_port; 2324 uint8_t mlrd_ptys_rsvd; 2325 bits8_t mlrd_ptys_proto_mask; 2326 2327 bits8_t mlrd_ptys_autoneg_status; 2328 uint8_t mlrd_ptys_rsvd2; 2329 uint16be_t mlrd_ptys_data_rate_oper; 2330 2331 uint8_t mlrd_ptys_rsvd3[4]; 2332 2333 bits32_t mlrd_ptys_proto_cap; 2334 uint8_t mlrd_ptys_rsvd4[8]; 2335 bits32_t mlrd_ptys_proto_admin; 2336 uint8_t mlrd_ptys_rsvd5[8]; 2337 bits32_t mlrd_ptys_proto_oper; 2338 uint8_t mlrd_ptys_rsvd6[8]; 2339 bits32_t mlrd_ptys_proto_partner_advert; 2340 uint8_t mlrd_ptys_rsvd7[12]; 2341 } mlxcx_reg_ptys_t; 2342 2343 typedef enum { 2344 MLXCX_LED_TYPE_BOTH = 0x0, 2345 MLXCX_LED_TYPE_UID = 0x1, 2346 MLXCX_LED_TYPE_PORT = 0x2, 2347 } mlxcx_led_type_t; 2348 2349 #define MLXCX_MLCR_INDIVIDUAL_ONLY (1 << 4) 2350 /* CSTYLED */ 2351 #define MLXCX_MLCR_LED_TYPE (bitdef_t){ 0, 0x0F } 2352 2353 typedef struct { 2354 uint8_t mlrd_mlcr_rsvd; 2355 uint8_t mlrd_mlcr_local_port; 2356 uint8_t mlrd_mlcr_rsvd2; 2357 bits8_t mlrd_mlcr_flags; 2358 uint8_t mlrd_mlcr_rsvd3[2]; 2359 uint16be_t mlrd_mlcr_beacon_duration; 2360 uint8_t mlrd_mlcr_rsvd4[2]; 2361 uint16be_t mlrd_mlcr_beacon_remain; 2362 } mlxcx_reg_mlcr_t; 2363 2364 typedef struct { 2365 uint8_t mlrd_pmaos_rsvd; 2366 uint8_t mlrd_pmaos_module; 2367 uint8_t mlrd_pmaos_admin_status; 2368 uint8_t mlrd_pmaos_oper_status; 2369 bits8_t mlrd_pmaos_flags; 2370 uint8_t mlrd_pmaos_rsvd2; 2371 uint8_t mlrd_pmaos_error_type; 2372 uint8_t mlrd_pmaos_event_en; 2373 uint8_t mlrd_pmaos_rsvd3[8]; 2374 } mlxcx_reg_pmaos_t; 2375 2376 typedef enum { 2377 MLXCX_MCIA_STATUS_OK = 0x0, 2378 MLXCX_MCIA_STATUS_NO_EEPROM = 0x1, 2379 MLXCX_MCIA_STATUS_NOT_SUPPORTED = 0x2, 2380 MLXCX_MCIA_STATUS_NOT_CONNECTED = 0x3, 2381 MLXCX_MCIA_STATUS_I2C_ERROR = 0x9, 2382 MLXCX_MCIA_STATUS_DISABLED = 0x10 2383 } mlxcx_mcia_status_t; 2384 2385 typedef struct { 2386 bits8_t mlrd_mcia_flags; 2387 uint8_t mlrd_mcia_module; 2388 uint8_t mlrd_mcia_rsvd; 2389 uint8_t mlrd_mcia_status; 2390 uint8_t mlrd_mcia_i2c_device_addr; 2391 uint8_t mlrd_mcia_page_number; 2392 uint16be_t mlrd_mcia_device_addr; 2393 uint8_t mlrd_mcia_rsvd2[2]; 2394 uint16be_t mlrd_mcia_size; 2395 uint8_t mlrd_mcia_rsvd3[4]; 2396 uint8_t mlrd_mcia_data[48]; 2397 } mlxcx_reg_mcia_t; 2398 2399 typedef struct { 2400 uint64be_t mlppc_ieee_802_3_frames_tx; 2401 uint64be_t mlppc_ieee_802_3_frames_rx; 2402 uint64be_t mlppc_ieee_802_3_fcs_err; 2403 uint64be_t mlppc_ieee_802_3_align_err; 2404 uint64be_t mlppc_ieee_802_3_bytes_tx; 2405 uint64be_t mlppc_ieee_802_3_bytes_rx; 2406 uint64be_t mlppc_ieee_802_3_mcast_tx; 2407 uint64be_t mlppc_ieee_802_3_bcast_tx; 2408 uint64be_t mlppc_ieee_802_3_mcast_rx; 2409 uint64be_t mlppc_ieee_802_3_bcast_rx; 2410 uint64be_t mlppc_ieee_802_3_in_range_len_err; 2411 uint64be_t mlppc_ieee_802_3_out_of_range_len_err; 2412 uint64be_t mlppc_ieee_802_3_frame_too_long_err; 2413 uint64be_t mlppc_ieee_802_3_symbol_err; 2414 uint64be_t mlppc_ieee_802_3_mac_ctrl_tx; 2415 uint64be_t mlppc_ieee_802_3_mac_ctrl_rx; 2416 uint64be_t mlppc_ieee_802_3_unsup_opcodes_rx; 2417 uint64be_t mlppc_ieee_802_3_pause_rx; 2418 uint64be_t mlppc_ieee_802_3_pause_tx; 2419 } mlxcx_ppcnt_ieee_802_3_t; 2420 2421 typedef struct { 2422 uint64be_t mlppc_rfc_2863_in_octets; 2423 uint64be_t mlppc_rfc_2863_in_ucast_pkts; 2424 uint64be_t mlppc_rfc_2863_in_discards; 2425 uint64be_t mlppc_rfc_2863_in_errors; 2426 uint64be_t mlppc_rfc_2863_in_unknown_protos; 2427 uint64be_t mlppc_rfc_2863_out_octets; 2428 uint64be_t mlppc_rfc_2863_out_ucast_pkts; 2429 uint64be_t mlppc_rfc_2863_out_discards; 2430 uint64be_t mlppc_rfc_2863_out_errors; 2431 uint64be_t mlppc_rfc_2863_in_mcast_pkts; 2432 uint64be_t mlppc_rfc_2863_in_bcast_pkts; 2433 uint64be_t mlppc_rfc_2863_out_mcast_pkts; 2434 uint64be_t mlppc_rfc_2863_out_bcast_pkts; 2435 } mlxcx_ppcnt_rfc_2863_t; 2436 2437 typedef struct { 2438 uint64be_t mlppc_phy_stats_time_since_last_clear; 2439 uint64be_t mlppc_phy_stats_rx_bits; 2440 uint64be_t mlppc_phy_stats_symbol_errs; 2441 uint64be_t mlppc_phy_stats_corrected_bits; 2442 uint8_t mlppc_phy_stats_rsvd[2]; 2443 uint8_t mlppc_phy_stats_raw_ber_mag; 2444 uint8_t mlppc_phy_stats_raw_ber_coef; 2445 uint8_t mlppc_phy_stats_rsvd2[2]; 2446 uint8_t mlppc_phy_stats_eff_ber_mag; 2447 uint8_t mlppc_phy_stats_eff_ber_coef; 2448 } mlxcx_ppcnt_phy_stats_t; 2449 2450 typedef enum { 2451 MLXCX_PPCNT_GRP_IEEE_802_3 = 0x0, 2452 MLXCX_PPCNT_GRP_RFC_2863 = 0x1, 2453 MLXCX_PPCNT_GRP_RFC_2819 = 0x2, 2454 MLXCX_PPCNT_GRP_RFC_3635 = 0x3, 2455 MLXCX_PPCNT_GRP_ETH_EXTD = 0x5, 2456 MLXCX_PPCNT_GRP_ETH_DISCARD = 0x6, 2457 MLXCX_PPCNT_GRP_PER_PRIO = 0x10, 2458 MLXCX_PPCNT_GRP_PER_TC = 0x11, 2459 MLXCX_PPCNT_GRP_PER_TC_CONGEST = 0x13, 2460 MLXCX_PPCNT_GRP_PHY_STATS = 0x16 2461 } mlxcx_ppcnt_grp_t; 2462 2463 typedef enum { 2464 MLXCX_PPCNT_CLEAR = (1 << 7), 2465 MLXCX_PPCNT_NO_CLEAR = 0 2466 } mlxcx_ppcnt_clear_t; 2467 2468 typedef struct { 2469 uint8_t mlrd_ppcnt_swid; 2470 uint8_t mlrd_ppcnt_local_port; 2471 uint8_t mlrd_ppcnt_pnat; 2472 uint8_t mlrd_ppcnt_grp; 2473 uint8_t mlrd_ppcnt_clear; 2474 uint8_t mlrd_ppcnt_rsvd[2]; 2475 uint8_t mlrd_ppcnt_prio_tc; 2476 union { 2477 uint8_t mlrd_ppcnt_data[248]; 2478 mlxcx_ppcnt_ieee_802_3_t mlrd_ppcnt_ieee_802_3; 2479 mlxcx_ppcnt_rfc_2863_t mlrd_ppcnt_rfc_2863; 2480 mlxcx_ppcnt_phy_stats_t mlrd_ppcnt_phy_stats; 2481 }; 2482 } mlxcx_reg_ppcnt_t; 2483 2484 typedef enum { 2485 MLXCX_PPLM_FEC_CAP_AUTO = 0, 2486 MLXCX_PPLM_FEC_CAP_NONE = (1 << 0), 2487 MLXCX_PPLM_FEC_CAP_FIRECODE = (1 << 1), 2488 MLXCX_PPLM_FEC_CAP_RS = (1 << 2), 2489 } mlxcx_pplm_fec_caps_t; 2490 2491 typedef enum { 2492 MLXCX_PPLM_FEC_ACTIVE_NONE = (1 << 0), 2493 MLXCX_PPLM_FEC_ACTIVE_FIRECODE = (1 << 1), 2494 MLXCX_PPLM_FEC_ACTIVE_RS528 = (1 << 2), 2495 MLXCX_PPLM_FEC_ACTIVE_RS271 = (1 << 3), 2496 MLXCX_PPLM_FEC_ACTIVE_RS544 = (1 << 7), 2497 MLXCX_PPLM_FEC_ACTIVE_RS272 = (1 << 9), 2498 } mlxcx_pplm_fec_active_t; 2499 2500 /* CSTYLED */ 2501 #define MLXCX_PPLM_CAP_56G (bitdef_t){ 16, 0x000f0000 } 2502 /* CSTYLED */ 2503 #define MLXCX_PPLM_CAP_100G (bitdef_t){ 12, 0x0000f000 } 2504 /* CSTYLED */ 2505 #define MLXCX_PPLM_CAP_50G (bitdef_t){ 8, 0x00000f00 } 2506 /* CSTYLED */ 2507 #define MLXCX_PPLM_CAP_25G (bitdef_t){ 4, 0x000000f0 } 2508 /* CSTYLED */ 2509 #define MLXCX_PPLM_CAP_10_40G (bitdef_t){ 0, 0x0000000f } 2510 2511 typedef struct { 2512 uint8_t mlrd_pplm_rsvd; 2513 uint8_t mlrd_pplm_local_port; 2514 uint8_t mlrd_pplm_rsvd1[11]; 2515 uint24be_t mlrd_pplm_fec_mode_active; 2516 bits32_t mlrd_pplm_fec_override_cap; 2517 bits32_t mlrd_pplm_fec_override_admin; 2518 uint16be_t mlrd_pplm_fec_override_cap_400g_8x; 2519 uint16be_t mlrd_pplm_fec_override_cap_200g_4x; 2520 uint16be_t mlrd_pplm_fec_override_cap_100g_2x; 2521 uint16be_t mlrd_pplm_fec_override_cap_50g_1x; 2522 uint16be_t mlrd_pplm_fec_override_admin_400g_8x; 2523 uint16be_t mlrd_pplm_fec_override_admin_200g_4x; 2524 uint16be_t mlrd_pplm_fec_override_admin_100g_2x; 2525 uint16be_t mlrd_pplm_fec_override_admin_50g_1x; 2526 uint8_t mlrd_pplm_rsvd2[8]; 2527 uint16be_t mlrd_pplm_fec_override_cap_hdr; 2528 uint16be_t mlrd_pplm_fec_override_cap_edr; 2529 uint16be_t mlrd_pplm_fec_override_cap_fdr; 2530 uint16be_t mlrd_pplm_fec_override_cap_fdr10; 2531 uint16be_t mlrd_pplm_fec_override_admin_hdr; 2532 uint16be_t mlrd_pplm_fec_override_admin_edr; 2533 uint16be_t mlrd_pplm_fec_override_admin_fdr; 2534 uint16be_t mlrd_pplm_fec_override_admin_fdr10; 2535 } mlxcx_reg_pplm_t; 2536 2537 typedef struct { 2538 uint8_t mlrd_mtcap_rsvd[3]; 2539 uint8_t mlrd_mtcap_sensor_count; 2540 uint8_t mlrd_mtcap_rsvd1[4]; 2541 uint64be_t mlrd_mtcap_sensor_map; 2542 } mlxcx_reg_mtcap_t; 2543 2544 #define MLXCX_MTMP_NAMELEN 8 2545 2546 typedef struct { 2547 uint8_t mlrd_mtmp_rsvd[2]; 2548 uint16be_t mlrd_mtmp_sensor_index; 2549 uint8_t mlrd_mtmp_rsvd1[2]; 2550 uint16be_t mlrd_mtmp_temperature; 2551 bits16_t mlrd_mtmp_max_flags; 2552 uint16be_t mlrd_mtmp_max_temperature; 2553 bits16_t mlrd_mtmp_tee; 2554 uint16be_t mlrd_mtmp_temp_thresh_hi; 2555 uint8_t mlrd_mtmp_rsvd2[2]; 2556 uint16be_t mlrd_mtmp_temp_thresh_lo; 2557 uint8_t mlrd_mtmp_rsvd3[4]; 2558 uint8_t mlrd_mtmp_name[MLXCX_MTMP_NAMELEN]; 2559 } mlxcx_reg_mtmp_t; 2560 2561 typedef enum { 2562 MLXCX_REG_PMTU = 0x5003, 2563 MLXCX_REG_PTYS = 0x5004, 2564 MLXCX_REG_PAOS = 0x5006, 2565 MLXCX_REG_PMAOS = 0x5012, 2566 MLXCX_REG_MSGI = 0x9021, 2567 MLXCX_REG_MLCR = 0x902B, 2568 MLXCX_REG_MCIA = 0x9014, 2569 MLXCX_REG_PPCNT = 0x5008, 2570 MLXCX_REG_PPLM = 0x5023, 2571 MLXCX_REG_MTCAP = 0x9009, 2572 MLXCX_REG_MTMP = 0x900A 2573 } mlxcx_register_id_t; 2574 2575 typedef union { 2576 mlxcx_reg_pmtu_t mlrd_pmtu; 2577 mlxcx_reg_paos_t mlrd_paos; 2578 mlxcx_reg_ptys_t mlrd_ptys; 2579 mlxcx_reg_mlcr_t mlrd_mlcr; 2580 mlxcx_reg_pmaos_t mlrd_pmaos; 2581 mlxcx_reg_mcia_t mlrd_mcia; 2582 mlxcx_reg_ppcnt_t mlrd_ppcnt; 2583 mlxcx_reg_pplm_t mlrd_pplm; 2584 mlxcx_reg_mtcap_t mlrd_mtcap; 2585 mlxcx_reg_mtmp_t mlrd_mtmp; 2586 } mlxcx_register_data_t; 2587 2588 typedef enum { 2589 MLXCX_CMD_ACCESS_REGISTER_READ = 1, 2590 MLXCX_CMD_ACCESS_REGISTER_WRITE = 0 2591 } mlxcx_cmd_reg_opmod_t; 2592 2593 typedef struct { 2594 mlxcx_cmd_in_t mlxi_access_register_head; 2595 uint8_t mlxi_access_register_rsvd[2]; 2596 uint16be_t mlxi_access_register_register_id; 2597 uint32be_t mlxi_access_register_argument; 2598 mlxcx_register_data_t mlxi_access_register_data; 2599 } mlxcx_cmd_access_register_in_t; 2600 2601 typedef struct { 2602 mlxcx_cmd_out_t mlxo_access_register_head; 2603 uint8_t mlxo_access_register_rsvd[8]; 2604 mlxcx_register_data_t mlxo_access_register_data; 2605 } mlxcx_cmd_access_register_out_t; 2606 2607 #pragma pack() 2608 2609 CTASSERT(MLXCX_SQE_MAX_PTRS > 0); 2610 2611 #ifdef __cplusplus 2612 } 2613 #endif 2614 2615 #endif /* _MLXCX_REG_H */ 2616