1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2020, The University of Queensland 14 * Copyright (c) 2018, Joyent, Inc. 15 */ 16 17 #ifndef _MLXCX_REG_H 18 #define _MLXCX_REG_H 19 20 #include <sys/types.h> 21 #include <sys/byteorder.h> 22 23 #include <mlxcx_endint.h> 24 25 #if !defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) 26 #error "Need _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH" 27 #endif 28 29 /* 30 * Register offsets. 31 */ 32 33 #define MLXCX_ISS_FIRMWARE 0x0000 34 #define MLXCX_ISS_FW_MAJOR(x) (((x) & 0xffff)) 35 #define MLXCX_ISS_FW_MINOR(x) (((x) >> 16) & 0xffff) 36 #define MLXCX_ISS_FW_CMD 0x0004 37 #define MLXCX_ISS_FW_REV(x) (((x) & 0xffff)) 38 #define MLXCX_ISS_CMD_REV(x) (((x) >> 16) & 0xffff) 39 #define MLXCX_ISS_CMD_HIGH 0x0010 40 #define MLXCX_ISS_CMD_LOW 0x0014 41 #define MLXCX_ISS_CMDQ_SIZE(x) (((x) >> 4) & 0xf) 42 #define MLXCX_ISS_CMDQ_STRIDE(x) ((x) & 0xf) 43 44 #define MLXCX_ISS_CMD_DOORBELL 0x0018 45 #define MLXCX_ISS_INIT 0x01fc 46 #define MLXCX_ISS_INITIALIZING(x) (((x) >> 31) & 0x1) 47 #define MLXCX_ISS_HEALTH_BUF 0x0200 48 #define MLXCX_ISS_NO_DRAM_NIC 0x0240 49 #define MLXCX_ISS_TIMER 0x1000 50 #define MLXCX_ISS_HEALTH_COUNT 0x1010 51 #define MLXCX_ISS_HEALTH_SYND 0x1013 52 53 #define MLXCX_CMD_INLINE_INPUT_LEN 16 54 #define MLXCX_CMD_INLINE_OUTPUT_LEN 16 55 56 #define MLXCX_CMD_MAILBOX_LEN 512 57 58 #define MLXCX_CMD_TRANSPORT_PCI 7 59 #define MLXCX_CMD_HW_OWNED 0x01 60 #define MLXCX_CMD_STATUS(x) ((x) >> 1) 61 62 #define MLXCX_UAR_CQ_ARM 0x0020 63 #define MLXCX_UAR_EQ_ARM 0x0040 64 #define MLXCX_UAR_EQ_NOARM 0x0048 65 66 /* Number of blue flame reg pairs per UAR */ 67 #define MLXCX_BF_PER_UAR 2 68 #define MLXCX_BF_PER_UAR_MASK 0x1 69 #define MLXCX_BF_SIZE 0x100 70 #define MLXCX_BF_BASE 0x0800 71 72 /* CSTYLED */ 73 #define MLXCX_EQ_ARM_EQN (bitdef_t){24, 0xff000000} 74 /* CSTYLED */ 75 #define MLXCX_EQ_ARM_CI (bitdef_t){0, 0x00ffffff} 76 77 /* 78 * Hardware structure that is used to represent a command. 79 */ 80 #pragma pack(1) 81 typedef struct { 82 uint8_t mce_type; 83 uint8_t mce_rsvd[3]; 84 uint32be_t mce_in_length; 85 uint64be_t mce_in_mbox; 86 uint8_t mce_input[MLXCX_CMD_INLINE_INPUT_LEN]; 87 uint8_t mce_output[MLXCX_CMD_INLINE_OUTPUT_LEN]; 88 uint64be_t mce_out_mbox; 89 uint32be_t mce_out_length; 90 uint8_t mce_token; 91 uint8_t mce_sig; 92 uint8_t mce_rsvd1; 93 uint8_t mce_status; 94 } mlxcx_cmd_ent_t; 95 96 typedef struct { 97 uint8_t mlxb_data[MLXCX_CMD_MAILBOX_LEN]; 98 uint8_t mlxb_rsvd[48]; 99 uint64be_t mlxb_nextp; 100 uint32be_t mlxb_blockno; 101 uint8_t mlxb_rsvd1; 102 uint8_t mlxb_token; 103 uint8_t mlxb_ctrl_sig; 104 uint8_t mlxb_sig; 105 } mlxcx_cmd_mailbox_t; 106 107 typedef struct { 108 uint8_t mled_page_request_rsvd[2]; 109 uint16be_t mled_page_request_function_id; 110 uint32be_t mled_page_request_num_pages; 111 } mlxcx_evdata_page_request_t; 112 113 /* CSTYLED */ 114 #define MLXCX_EVENT_PORT_NUM (bitdef_t){ .bit_shift = 4, .bit_mask = 0xF0 } 115 116 typedef struct { 117 uint8_t mled_port_state_rsvd[8]; 118 bits8_t mled_port_state_port_num; 119 } mlxcx_evdata_port_state_t; 120 121 typedef enum { 122 MLXCX_MODULE_INITIALIZING = 0x0, 123 MLXCX_MODULE_PLUGGED = 0x1, 124 MLXCX_MODULE_UNPLUGGED = 0x2, 125 MLXCX_MODULE_ERROR = 0x3 126 } mlxcx_module_status_t; 127 128 typedef enum { 129 MLXCX_MODULE_ERR_POWER_BUDGET = 0x0, 130 MLXCX_MODULE_ERR_LONG_RANGE = 0x1, 131 MLXCX_MODULE_ERR_BUS_STUCK = 0x2, 132 MLXCX_MODULE_ERR_NO_EEPROM = 0x3, 133 MLXCX_MODULE_ERR_ENFORCEMENT = 0x4, 134 MLXCX_MODULE_ERR_UNKNOWN_IDENT = 0x5, 135 MLXCX_MODULE_ERR_HIGH_TEMP = 0x6, 136 MLXCX_MODULE_ERR_CABLE_SHORTED = 0x7, 137 } mlxcx_module_error_type_t; 138 139 typedef struct { 140 uint8_t mled_port_mod_rsvd; 141 uint8_t mled_port_mod_module; 142 uint8_t mled_port_mod_rsvd2; 143 uint8_t mled_port_mod_module_status; 144 uint8_t mled_port_mod_rsvd3[2]; 145 uint8_t mled_port_mod_error_type; 146 uint8_t mled_port_mod_rsvd4; 147 } mlxcx_evdata_port_mod_t; 148 149 typedef struct { 150 uint8_t mled_completion_rsvd[25]; 151 uint24be_t mled_completion_cqn; 152 } mlxcx_evdata_completion_t; 153 154 typedef enum { 155 MLXCX_EV_QUEUE_TYPE_QP = 0x0, 156 MLXCX_EV_QUEUE_TYPE_RQ = 0x1, 157 MLXCX_EV_QUEUE_TYPE_SQ = 0x2, 158 } mlxcx_evdata_queue_type_t; 159 160 typedef struct { 161 uint8_t mled_queue_rsvd[20]; 162 uint8_t mled_queue_type; 163 uint8_t mled_queue_rsvd2[4]; 164 uint24be_t mled_queue_num; 165 } mlxcx_evdata_queue_t; 166 167 #define MLXCX_EQ_OWNER_INIT 1 168 169 typedef struct { 170 uint8_t mleqe_rsvd[1]; 171 uint8_t mleqe_event_type; 172 uint8_t mleqe_rsvd2[1]; 173 uint8_t mleqe_event_sub_type; 174 uint8_t mleqe_rsvd3[28]; 175 union { 176 uint8_t mleqe_unknown_data[28]; 177 mlxcx_evdata_completion_t mleqe_completion; 178 mlxcx_evdata_page_request_t mleqe_page_request; 179 mlxcx_evdata_port_state_t mleqe_port_state; 180 mlxcx_evdata_port_mod_t mleqe_port_mod; 181 mlxcx_evdata_queue_t mleqe_queue; 182 }; 183 uint8_t mleqe_rsvd4[2]; 184 uint8_t mleqe_signature; 185 uint8_t mleqe_owner; 186 } mlxcx_eventq_ent_t; 187 188 typedef enum { 189 MLXCX_CQE_L3_HDR_NONE = 0x0, 190 MLXCX_CQE_L3_HDR_RCV_BUF = 0x1, 191 MLXCX_CQE_L3_HDR_CQE = 0x2, 192 } mlxcx_cqe_l3_hdr_placement_t; 193 194 typedef enum { 195 MLXCX_CQE_CSFLAGS_L4_OK = 1 << 2, 196 MLXCX_CQE_CSFLAGS_L3_OK = 1 << 1, 197 MLXCX_CQE_CSFLAGS_L2_OK = 1 << 0, 198 } mlxcx_cqe_csflags_t; 199 200 typedef enum { 201 MLXCX_CQE_L4_TYPE_NONE = 0, 202 MLXCX_CQE_L4_TYPE_TCP = 1, 203 MLXCX_CQE_L4_TYPE_UDP = 2, 204 MLXCX_CQE_L4_TYPE_TCP_EMPTY_ACK = 3, 205 MLXCX_CQE_L4_TYPE_TCP_ACK = 4, 206 } mlxcx_cqe_l4_hdr_type_t; 207 208 typedef enum { 209 MLXCX_CQE_L3_TYPE_NONE = 0, 210 MLXCX_CQE_L3_TYPE_IPv6 = 1, 211 MLXCX_CQE_L3_TYPE_IPv4 = 2, 212 } mlxcx_cqe_l3_hdr_type_t; 213 214 typedef enum { 215 MLXCX_CQE_RX_HASH_NONE = 0, 216 MLXCX_CQE_RX_HASH_IPv4 = 1, 217 MLXCX_CQE_RX_HASH_IPv6 = 2, 218 MLXCX_CQE_RX_HASH_IPSEC_SPI = 3, 219 } mlxcx_cqe_rx_hash_type_t; 220 /* BEGIN CSTYLED */ 221 #define MLXCX_CQE_RX_HASH_IP_SRC (bitdef_t){0, 0x3} 222 #define MLXCX_CQE_RX_HASH_IP_DEST (bitdef_t){2, (0x3 << 2)} 223 #define MLXCX_CQE_RX_HASH_L4_SRC (bitdef_t){4, (0x3 << 4)} 224 #define MLXCX_CQE_RX_HASH_L4_DEST (bitdef_t){6, (0x3 << 6)} 225 /* END CSTYLED */ 226 227 typedef enum { 228 MLXCX_CQE_OP_REQ = 0x0, 229 MLXCX_CQE_OP_RESP_RDMA = 0x1, 230 MLXCX_CQE_OP_RESP = 0x2, 231 MLXCX_CQE_OP_RESP_IMMEDIATE = 0x3, 232 MLXCX_CQE_OP_RESP_INVALIDATE = 0x4, 233 MLXCX_CQE_OP_RESIZE_CQ = 0x5, 234 MLXCX_CQE_OP_SIG_ERR = 0x12, 235 MLXCX_CQE_OP_REQ_ERR = 0xd, 236 MLXCX_CQE_OP_RESP_ERR = 0xe, 237 MLXCX_CQE_OP_INVALID = 0xf 238 } mlxcx_cqe_opcode_t; 239 240 typedef enum { 241 MLXCX_CQE_FORMAT_BASIC = 0, 242 MLXCX_CQE_FORMAT_INLINE_32 = 1, 243 MLXCX_CQE_FORMAT_INLINE_64 = 2, 244 MLXCX_CQE_FORMAT_COMPRESSED = 3, 245 } mlxcx_cqe_format_t; 246 247 typedef enum { 248 MLXCX_CQE_OWNER_INIT = 1 249 } mlxcx_cqe_owner_t; 250 251 typedef enum { 252 MLXCX_VLAN_TYPE_NONE, 253 MLXCX_VLAN_TYPE_CVLAN, 254 MLXCX_VLAN_TYPE_SVLAN, 255 } mlxcx_vlan_type_t; 256 257 typedef enum { 258 MLXCX_CQ_ERR_LOCAL_LENGTH = 0x1, 259 MLXCX_CQ_ERR_LOCAL_QP_OP = 0x2, 260 MLXCX_CQ_ERR_LOCAL_PROTECTION = 0x4, 261 MLXCX_CQ_ERR_WR_FLUSHED = 0x5, 262 MLXCX_CQ_ERR_MEM_WINDOW_BIND = 0x6, 263 MLXCX_CQ_ERR_BAD_RESPONSE = 0x10, 264 MLXCX_CQ_ERR_LOCAL_ACCESS = 0x11, 265 MLXCX_CQ_ERR_XPORT_RETRY_CTR = 0x15, 266 MLXCX_CQ_ERR_RNR_RETRY_CTR = 0x16, 267 MLXCX_CQ_ERR_ABORTED = 0x22 268 } mlxcx_cq_error_syndrome_t; 269 270 typedef struct { 271 uint8_t mlcqee_rsvd[2]; 272 uint16be_t mlcqee_wqe_id; 273 uint8_t mlcqee_rsvd2[29]; 274 uint24be_t mlcqee_user_index; 275 uint8_t mlcqee_rsvd3[8]; 276 uint32be_t mlcqee_byte_cnt; 277 uint8_t mlcqee_rsvd4[6]; 278 uint8_t mlcqee_vendor_error_syndrome; 279 uint8_t mlcqee_syndrome; 280 uint8_t mlcqee_wqe_opcode; 281 uint24be_t mlcqee_flow_tag; 282 uint16be_t mlcqee_wqe_counter; 283 uint8_t mlcqee_signature; 284 struct { 285 #if defined(_BIT_FIELDS_HTOL) 286 uint8_t mlcqe_opcode:4; 287 uint8_t mlcqe_rsvd5:3; 288 uint8_t mlcqe_owner:1; 289 #elif defined(_BIT_FIELDS_LTOH) 290 uint8_t mlcqe_owner:1; 291 uint8_t mlcqe_rsvd5:3; 292 uint8_t mlcqe_opcode:4; 293 #endif 294 }; 295 } mlxcx_completionq_error_ent_t; 296 297 typedef struct { 298 uint8_t mlcqe_tunnel_flags; 299 uint8_t mlcqe_rsvd[3]; 300 uint8_t mlcqe_lro_flags; 301 uint8_t mlcqe_lro_min_ttl; 302 uint16be_t mlcqe_lro_tcp_win; 303 uint32be_t mlcqe_lro_ack_seq_num; 304 uint32be_t mlcqe_rx_hash_result; 305 bits8_t mlcqe_rx_hash_type; 306 uint8_t mlcqe_ml_path; 307 uint8_t mlcqe_rsvd2[2]; 308 uint16be_t mlcqe_checksum; 309 uint16be_t mlcqe_slid_smac_lo; 310 struct { 311 #if defined(_BIT_FIELDS_HTOL) 312 uint8_t mlcqe_rsvd3:1; 313 uint8_t mlcqe_force_loopback:1; 314 uint8_t mlcqe_l3_hdr:2; 315 uint8_t mlcqe_sl_roce_pktype:4; 316 #elif defined(_BIT_FIELDS_LTOH) 317 uint8_t mlcqe_sl_roce_pktype:4; 318 uint8_t mlcqe_l3_hdr:2; 319 uint8_t mlcqe_force_loopback:1; 320 uint8_t mlcqe_rsvd3:1; 321 #endif 322 }; 323 uint24be_t mlcqe_rqpn; 324 bits8_t mlcqe_csflags; 325 struct { 326 #if defined(_BIT_FIELDS_HTOL) 327 uint8_t mlcqe_ip_frag:1; 328 uint8_t mlcqe_l4_hdr_type:3; 329 uint8_t mlcqe_l3_hdr_type:2; 330 uint8_t mlcqe_ip_ext_opts:1; 331 uint8_t mlcqe_cv:1; 332 #elif defined(_BIT_FIELDS_LTOH) 333 uint8_t mlcqe_cv:1; 334 uint8_t mlcqe_ip_ext_opts:1; 335 uint8_t mlcqe_l3_hdr_type:2; 336 uint8_t mlcqe_l4_hdr_type:3; 337 uint8_t mlcqe_ip_frag:1; 338 #endif 339 }; 340 uint16be_t mlcqe_up_cfi_vid; 341 uint8_t mlcqe_lro_num_seg; 342 uint24be_t mlcqe_user_index; 343 uint32be_t mlcqe_immediate; 344 uint8_t mlcqe_rsvd4[4]; 345 uint32be_t mlcqe_byte_cnt; 346 union { 347 struct { 348 uint32be_t mlcqe_lro_timestamp_value; 349 uint32be_t mlcqe_lro_timestamp_echo; 350 }; 351 uint64be_t mlcqe_timestamp; 352 }; 353 union { 354 uint8_t mlcqe_rx_drop_counter; 355 uint8_t mlcqe_send_wqe_opcode; 356 }; 357 uint24be_t mlcqe_flow_tag; 358 uint16be_t mlcqe_wqe_counter; 359 uint8_t mlcqe_signature; 360 struct { 361 #if defined(_BIT_FIELDS_HTOL) 362 uint8_t mlcqe_opcode:4; 363 uint8_t mlcqe_format:2; 364 uint8_t mlcqe_se:1; 365 uint8_t mlcqe_owner:1; 366 #elif defined(_BIT_FIELDS_LTOH) 367 uint8_t mlcqe_owner:1; 368 uint8_t mlcqe_se:1; 369 uint8_t mlcqe_format:2; 370 uint8_t mlcqe_opcode:4; 371 #endif 372 }; 373 } mlxcx_completionq_ent_t; 374 375 typedef struct { 376 uint8_t mlcqe_data[64]; 377 mlxcx_completionq_ent_t mlcqe_ent; 378 } mlxcx_completionq_ent128_t; 379 380 typedef enum { 381 MLXCX_WQE_OP_NOP = 0x00, 382 MLXCX_WQE_OP_SEND_INVALIDATE = 0x01, 383 MLXCX_WQE_OP_RDMA_W = 0x08, 384 MLXCX_WQE_OP_RDMA_W_IMMEDIATE = 0x09, 385 MLXCX_WQE_OP_SEND = 0x0A, 386 MLXCX_WQE_OP_SEND_IMMEDIATE = 0x0B, 387 MLXCX_WQE_OP_LSO = 0x0E, 388 MLXCX_WQE_OP_WAIT = 0x0F, 389 MLXCX_WQE_OP_RDMA_R = 0x10, 390 } mlxcx_wqe_opcode_t; 391 392 #define MLXCX_SQE_MAX_DS ((1 << 6) - 1) 393 #define MLXCX_SQE_MAX_PTRS 61 394 395 typedef enum { 396 MLXCX_SQE_FENCE_NONE = 0x0, 397 MLXCX_SQE_FENCE_WAIT_OTHERS = 0x1, 398 MLXCX_SQE_FENCE_START = 0x2, 399 MLXCX_SQE_FENCE_STRONG_ORDER = 0x3, 400 MLXCX_SQE_FENCE_START_WAIT = 0x4 401 } mlxcx_sqe_fence_mode_t; 402 403 typedef enum { 404 MLXCX_SQE_CQE_ON_EACH_ERROR = 0x0, 405 MLXCX_SQE_CQE_ON_FIRST_ERROR = 0x1, 406 MLXCX_SQE_CQE_ALWAYS = 0x2, 407 MLXCX_SQE_CQE_ALWAYS_PLUS_EQE = 0x3 408 } mlxcx_sqe_completion_mode_t; 409 410 #define MLXCX_SQE_SOLICITED (1 << 1) 411 /* CSTYLED */ 412 #define MLXCX_SQE_FENCE_MODE (bitdef_t){5, 0xe0} 413 /* CSTYLED */ 414 #define MLXCX_SQE_COMPLETION_MODE (bitdef_t){2, 0x0c} 415 416 typedef struct { 417 uint8_t mlcs_opcode_mod; 418 uint16be_t mlcs_wqe_index; 419 uint8_t mlcs_opcode; 420 uint24be_t mlcs_qp_or_sq; 421 uint8_t mlcs_ds; 422 uint8_t mlcs_signature; 423 uint8_t mlcs_rsvd2[2]; 424 bits8_t mlcs_flags; 425 uint32be_t mlcs_immediate; 426 } mlxcx_wqe_control_seg_t; 427 428 typedef enum { 429 MLXCX_SQE_ETH_CSFLAG_L4_CHECKSUM = 1 << 7, 430 MLXCX_SQE_ETH_CSFLAG_L3_CHECKSUM = 1 << 6, 431 MLXCX_SQE_ETH_CSFLAG_L4_INNER_CHECKSUM = 1 << 5, 432 MLXCX_SQE_ETH_CSFLAG_L3_INNER_CHECKSUM = 1 << 4, 433 } mlxcx_wqe_eth_flags_t; 434 435 /* CSTYLED */ 436 #define MLXCX_SQE_ETH_INLINE_HDR_SZ (bitdef_t){0, 0x03ff} 437 #define MLXCX_SQE_ETH_SZFLAG_VLAN (1 << 15) 438 #define MLXCX_MAX_INLINE_HEADERLEN 64 439 440 typedef struct { 441 uint8_t mles_rsvd[4]; 442 bits8_t mles_csflags; 443 uint8_t mles_rsvd2[1]; 444 uint16_t mles_mss; 445 uint8_t mles_rsvd3[4]; 446 bits16_t mles_szflags; 447 uint8_t mles_inline_headers[18]; 448 } mlxcx_wqe_eth_seg_t; 449 450 typedef struct { 451 uint32be_t mlds_byte_count; 452 uint32be_t mlds_lkey; 453 uint64be_t mlds_address; 454 } mlxcx_wqe_data_seg_t; 455 456 #define MLXCX_SENDQ_STRIDE_SHIFT 6 457 458 typedef struct { 459 mlxcx_wqe_control_seg_t mlsqe_control; 460 mlxcx_wqe_eth_seg_t mlsqe_eth; 461 mlxcx_wqe_data_seg_t mlsqe_data[1]; 462 } mlxcx_sendq_ent_t; 463 464 typedef struct { 465 uint64be_t mlsqbf_qwords[8]; 466 } mlxcx_sendq_bf_t; 467 468 typedef struct { 469 mlxcx_wqe_data_seg_t mlsqe_data[4]; 470 } mlxcx_sendq_extra_ent_t; 471 472 #define MLXCX_RECVQ_STRIDE_SHIFT 7 473 /* 474 * Each mlxcx_wqe_data_seg_t is 1<<4 bytes long (there's a CTASSERT to verify 475 * this in mlxcx_cmd.c), so the number of pointers is 1 << (shift - 4). 476 */ 477 #define MLXCX_RECVQ_MAX_PTRS (1 << (MLXCX_RECVQ_STRIDE_SHIFT - 4)) 478 typedef struct { 479 mlxcx_wqe_data_seg_t mlrqe_data[MLXCX_RECVQ_MAX_PTRS]; 480 } mlxcx_recvq_ent_t; 481 482 /* CSTYLED */ 483 #define MLXCX_CQ_ARM_CI (bitdef_t){ .bit_shift = 0, \ 484 .bit_mask = 0x00ffffff } 485 /* CSTYLED */ 486 #define MLXCX_CQ_ARM_SEQ (bitdef_t){ .bit_shift = 28, \ 487 .bit_mask = 0x30000000 } 488 #define MLXCX_CQ_ARM_SOLICITED (1 << 24) 489 490 typedef struct { 491 uint8_t mlcqd_rsvd; 492 uint24be_t mlcqd_update_ci; 493 bits32_t mlcqd_arm_ci; 494 } mlxcx_completionq_doorbell_t; 495 496 typedef struct { 497 uint16be_t mlwqd_rsvd; 498 uint16be_t mlwqd_recv_counter; 499 uint16be_t mlwqd_rsvd2; 500 uint16be_t mlwqd_send_counter; 501 } mlxcx_workq_doorbell_t; 502 503 #define MLXCX_EQ_STATUS_OK (0x0 << 4) 504 #define MLXCX_EQ_STATUS_WRITE_FAILURE (0xA << 4) 505 506 #define MLXCX_EQ_OI (1 << 1) 507 #define MLXCX_EQ_EC (1 << 2) 508 509 #define MLXCX_EQ_ST_ARMED 0x9 510 #define MLXCX_EQ_ST_FIRED 0xA 511 512 /* CSTYLED */ 513 #define MLXCX_EQ_LOG_PAGE_SIZE (bitdef_t){ .bit_shift = 24, \ 514 .bit_mask = 0x1F000000 } 515 516 typedef struct { 517 uint8_t mleqc_status; 518 uint8_t mleqc_ecoi; 519 uint8_t mleqc_state; 520 uint8_t mleqc_rsvd[7]; 521 uint16be_t mleqc_page_offset; 522 uint8_t mleqc_log_eq_size; 523 uint24be_t mleqc_uar_page; 524 uint8_t mleqc_rsvd3[7]; 525 uint8_t mleqc_intr; 526 uint32be_t mleqc_log_page; 527 uint8_t mleqc_rsvd4[13]; 528 uint24be_t mleqc_consumer_counter; 529 uint8_t mleqc_rsvd5; 530 uint24be_t mleqc_producer_counter; 531 uint8_t mleqc_rsvd6[16]; 532 } mlxcx_eventq_ctx_t; 533 534 typedef enum { 535 MLXCX_CQC_CQE_SIZE_64 = 0x0, 536 MLXCX_CQC_CQE_SIZE_128 = 0x1, 537 } mlxcx_cqc_cqe_sz_t; 538 539 typedef enum { 540 MLXCX_CQC_STATUS_OK = 0x0, 541 MLXCX_CQC_STATUS_OVERFLOW = 0x9, 542 MLXCX_CQC_STATUS_WRITE_FAIL = 0xA, 543 MLXCX_CQC_STATUS_INVALID = 0xF 544 } mlxcx_cqc_status_t; 545 546 typedef enum { 547 MLXCX_CQC_STATE_ARMED_SOLICITED = 0x6, 548 MLXCX_CQC_STATE_ARMED = 0x9, 549 MLXCX_CQC_STATE_FIRED = 0xA 550 } mlxcx_cqc_state_t; 551 552 /* CSTYLED */ 553 #define MLXCX_CQ_CTX_STATUS (bitdef_t){28, 0xf0000000} 554 /* CSTYLED */ 555 #define MLXCX_CQ_CTX_CQE_SZ (bitdef_t){21, 0x00e00000} 556 /* CSTYLED */ 557 #define MLXCX_CQ_CTX_PERIOD_MODE (bitdef_t){15, 0x00018000} 558 /* CSTYLED */ 559 #define MLXCX_CQ_CTX_MINI_CQE_FORMAT (bitdef_t){12, 0x00003000} 560 /* CSTYLED */ 561 #define MLXCX_CQ_CTX_STATE (bitdef_t){8, 0x00000f00} 562 563 typedef struct mlxcx_completionq_ctx { 564 bits32_t mlcqc_flags; 565 566 uint8_t mlcqc_rsvd4[4]; 567 568 uint8_t mlcqc_rsvd5[2]; 569 uint16be_t mlcqc_page_offset; 570 571 uint8_t mlcqc_log_cq_size; 572 uint24be_t mlcqc_uar_page; 573 574 uint16be_t mlcqc_cq_period; 575 uint16be_t mlcqc_cq_max_count; 576 577 uint8_t mlcqc_rsvd7[3]; 578 uint8_t mlcqc_eqn; 579 580 uint8_t mlcqc_log_page_size; 581 uint8_t mlcqc_rsvd8[3]; 582 583 uint8_t mlcqc_rsvd9[4]; 584 585 uint8_t mlcqc_rsvd10; 586 uint24be_t mlcqc_last_notified_index; 587 uint8_t mlcqc_rsvd11; 588 uint24be_t mlcqc_last_solicit_index; 589 uint8_t mlcqc_rsvd12; 590 uint24be_t mlcqc_consumer_counter; 591 uint8_t mlcqc_rsvd13; 592 uint24be_t mlcqc_producer_counter; 593 594 uint8_t mlcqc_rsvd14[8]; 595 596 uint64be_t mlcqc_dbr_addr; 597 } mlxcx_completionq_ctx_t; 598 599 typedef enum { 600 MLXCX_WORKQ_TYPE_LINKED_LIST = 0x0, 601 MLXCX_WORKQ_TYPE_CYCLIC = 0x1, 602 MLXCX_WORKQ_TYPE_LINKED_LIST_STRIDING = 0x2, 603 MLXCX_WORKQ_TYPE_CYCLIC_STRIDING = 0x3 604 } mlxcx_workq_ctx_type_t; 605 606 typedef enum { 607 MLXCX_WORKQ_END_PAD_NONE = 0x0, 608 MLXCX_WORKQ_END_PAD_ALIGN = 0x1 609 } mlxcx_workq_end_padding_t; 610 611 /* CSTYLED */ 612 #define MLXCX_WORKQ_CTX_TYPE (bitdef_t){ \ 613 .bit_shift = 28, \ 614 .bit_mask = 0xf0000000 } 615 #define MLXCX_WORKQ_CTX_SIGNATURE (1 << 27) 616 #define MLXCX_WORKQ_CTX_CD_SLAVE (1 << 24) 617 /* CSTYLED */ 618 #define MLXCX_WORKQ_CTX_END_PADDING (bitdef_t){ \ 619 .bit_shift = 25, \ 620 .bit_mask = 0x06000000 } 621 622 #define MLXCX_WORKQ_CTX_MAX_ADDRESSES 128 623 624 typedef struct mlxcx_workq_ctx { 625 bits32_t mlwqc_flags; 626 uint8_t mlwqc_rsvd[2]; 627 uint16be_t mlwqc_lwm; 628 uint8_t mlwqc_rsvd2; 629 uint24be_t mlwqc_pd; 630 uint8_t mlwqc_rsvd3; 631 uint24be_t mlwqc_uar_page; 632 uint64be_t mlwqc_dbr_addr; 633 uint32be_t mlwqc_hw_counter; 634 uint32be_t mlwqc_sw_counter; 635 uint8_t mlwqc_rsvd4; 636 uint8_t mlwqc_log_wq_stride; 637 uint8_t mlwqc_log_wq_pg_sz; 638 uint8_t mlwqc_log_wq_sz; 639 uint8_t mlwqc_rsvd5[2]; 640 bits16_t mlwqc_strides; 641 uint8_t mlwqc_rsvd6[152]; 642 uint64be_t mlwqc_pas[MLXCX_WORKQ_CTX_MAX_ADDRESSES]; 643 } mlxcx_workq_ctx_t; 644 645 #define MLXCX_RQ_FLAGS_RLKEY (1UL << 31) 646 #define MLXCX_RQ_FLAGS_SCATTER_FCS (1 << 29) 647 #define MLXCX_RQ_FLAGS_VLAN_STRIP_DISABLE (1 << 28) 648 #define MLXCX_RQ_FLAGS_FLUSH_IN_ERROR (1 << 18) 649 /* CSTYLED */ 650 #define MLXCX_RQ_MEM_RQ_TYPE (bitdef_t){ \ 651 .bit_shift = 24, \ 652 .bit_mask = 0x0f000000 } 653 /* CSTYLED */ 654 #define MLXCX_RQ_STATE (bitdef_t){ \ 655 .bit_shift = 20, \ 656 .bit_mask = 0x00f00000 } 657 658 typedef struct mlxcx_rq_ctx { 659 bits32_t mlrqc_flags; 660 uint8_t mlrqc_rsvd; 661 uint24be_t mlrqc_user_index; 662 uint8_t mlrqc_rsvd2; 663 uint24be_t mlrqc_cqn; 664 uint8_t mlrqc_counter_set_id; 665 uint8_t mlrqc_rsvd3[4]; 666 uint24be_t mlrqc_rmpn; 667 uint8_t mlrqc_rsvd4[28]; 668 mlxcx_workq_ctx_t mlrqc_wq; 669 } mlxcx_rq_ctx_t; 670 671 #define MLXCX_SQ_FLAGS_RLKEY (1UL << 31) 672 #define MLXCX_SQ_FLAGS_CD_MASTER (1 << 30) 673 #define MLXCX_SQ_FLAGS_FRE (1 << 29) 674 #define MLXCX_SQ_FLAGS_FLUSH_IN_ERROR (1 << 28) 675 #define MLXCX_SQ_FLAGS_ALLOW_MULTI_PKT (1 << 27) 676 #define MLXCX_SQ_FLAGS_REG_UMR (1 << 19) 677 678 typedef enum { 679 MLXCX_ETH_CAP_INLINE_REQUIRE_L2 = 0, 680 MLXCX_ETH_CAP_INLINE_VPORT_CTX = 1, 681 MLXCX_ETH_CAP_INLINE_NOT_REQUIRED = 2 682 } mlxcx_eth_cap_inline_mode_t; 683 684 typedef enum { 685 MLXCX_ETH_INLINE_NONE = 0, 686 MLXCX_ETH_INLINE_L2 = 1, 687 MLXCX_ETH_INLINE_L3 = 2, 688 MLXCX_ETH_INLINE_L4 = 3, 689 MLXCX_ETH_INLINE_INNER_L2 = 5, 690 MLXCX_ETH_INLINE_INNER_L3 = 6, 691 MLXCX_ETH_INLINE_INNER_L4 = 7 692 } mlxcx_eth_inline_mode_t; 693 694 /* CSTYLED */ 695 #define MLXCX_SQ_MIN_WQE_INLINE (bitdef_t){ \ 696 .bit_shift = 24, \ 697 .bit_mask = 0x07000000 } 698 /* CSTYLED */ 699 #define MLXCX_SQ_STATE (bitdef_t){ \ 700 .bit_shift = 20, \ 701 .bit_mask = 0x00f00000 } 702 703 typedef struct mlxcx_sq_ctx { 704 bits32_t mlsqc_flags; 705 uint8_t mlsqc_rsvd; 706 uint24be_t mlsqc_user_index; 707 uint8_t mlsqc_rsvd2; 708 uint24be_t mlsqc_cqn; 709 uint8_t mlsqc_rsvd3[18]; 710 uint16be_t mlsqc_packet_pacing_rate_limit_index; 711 uint16be_t mlsqc_tis_lst_sz; 712 uint8_t mlsqc_rsvd4[11]; 713 uint24be_t mlsqc_tis_num; 714 mlxcx_workq_ctx_t mlsqc_wq; 715 } mlxcx_sq_ctx_t; 716 717 #define MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES 64 718 719 typedef enum { 720 MLXCX_VPORT_PROMISC_UCAST = 1 << 15, 721 MLXCX_VPORT_PROMISC_MCAST = 1 << 14, 722 MLXCX_VPORT_PROMISC_ALL = 1 << 13 723 } mlxcx_nic_vport_ctx_promisc_t; 724 725 #define MLXCX_VPORT_LIST_TYPE_MASK 0x07 726 #define MLXCX_VPORT_LIST_TYPE_SHIFT 0 727 728 /* CSTYLED */ 729 #define MLXCX_VPORT_CTX_MIN_WQE_INLINE (bitdef_t){56, 0x0700000000000000} 730 731 typedef struct { 732 bits64_t mlnvc_flags; 733 uint8_t mlnvc_rsvd[28]; 734 uint8_t mlnvc_rsvd2[2]; 735 uint16be_t mlnvc_mtu; 736 uint64be_t mlnvc_system_image_guid; 737 uint64be_t mlnvc_port_guid; 738 uint64be_t mlnvc_node_guid; 739 uint8_t mlnvc_rsvd3[40]; 740 uint16be_t mlnvc_qkey_violation_counter; 741 uint8_t mlnvc_rsvd4[2]; 742 uint8_t mlnvc_rsvd5[132]; 743 bits16_t mlnvc_promisc_list_type; 744 uint16be_t mlnvc_allowed_list_size; 745 uint8_t mlnvc_rsvd6[2]; 746 uint8_t mlnvc_permanent_address[6]; 747 uint8_t mlnvc_rsvd7[4]; 748 uint64be_t mlnvc_address[MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES]; 749 } mlxcx_nic_vport_ctx_t; 750 751 typedef struct { 752 uint8_t mlftc_flags; 753 uint8_t mlftc_level; 754 uint8_t mlftc_rsvd; 755 uint8_t mlftc_log_size; 756 uint8_t mlftc_rsvd2; 757 uint24be_t mlftc_table_miss_id; 758 uint8_t mlftc_rsvd3[4]; 759 uint8_t mlftc_rsvd4[28]; 760 } mlxcx_flow_table_ctx_t; 761 762 /* CSTYLED */ 763 #define MLXCX_FLOW_HDR_FIRST_VID (bitdef_t){0, 0x07ff} 764 /* CSTYLED */ 765 #define MLXCX_FLOW_HDR_FIRST_PRIO (bitdef_t){13,0x7000} 766 #define MLXCX_FLOW_HDR_FIRST_CFI (1 << 12) 767 768 #define MLXCX_FLOW_HDR_IP_DSCP_SHIFT 18 769 #define MLXCX_FLOW_HDR_IP_DSCP_MASK 0xfc0000 770 #define MLXCX_FLOW_HDR_IP_ECN_SHIFT 16 771 #define MLXCX_FLOW_HDR_IP_ECN_MASK 0x030000 772 #define MLXCX_FLOW_HDR_CVLAN_TAG (1 << 15) 773 #define MLXCX_FLOW_HDR_SVLAN_TAG (1 << 14) 774 #define MLXCX_FLOW_HDR_FRAG (1 << 13) 775 /* CSTYLED */ 776 #define MLXCX_FLOW_HDR_IP_VERSION (bitdef_t){ \ 777 .bit_shift = 9, \ 778 .bit_mask = 0x001e00 } 779 /* CSTYLED */ 780 #define MLXCX_FLOW_HDR_TCP_FLAGS (bitdef_t){ \ 781 .bit_shift = 0, \ 782 .bit_mask = 0x0001ff } 783 784 typedef struct { 785 uint8_t mlfh_smac[6]; 786 uint16be_t mlfh_ethertype; 787 uint8_t mlfh_dmac[6]; 788 bits16_t mlfh_first_vid_flags; 789 uint8_t mlfh_ip_protocol; 790 bits24_t mlfh_tcp_ip_flags; 791 uint16be_t mlfh_tcp_sport; 792 uint16be_t mlfh_tcp_dport; 793 uint8_t mlfh_rsvd[3]; 794 uint8_t mlfh_ip_ttl_hoplimit; 795 uint16be_t mlfh_udp_sport; 796 uint16be_t mlfh_udp_dport; 797 uint8_t mlfh_src_ip[16]; 798 uint8_t mlfh_dst_ip[16]; 799 } mlxcx_flow_header_match_t; 800 801 typedef struct { 802 uint8_t mlfp_rsvd; 803 uint24be_t mlfp_source_sqn; 804 uint8_t mlfp_rsvd2[2]; 805 uint16be_t mlfp_source_port; 806 bits16_t mlfp_outer_second_vid_flags; 807 bits16_t mlfp_inner_second_vid_flags; 808 bits16_t mlfp_vlan_flags; 809 uint16be_t mlfp_gre_protocol; 810 uint32be_t mlfp_gre_key; 811 uint24be_t mlfp_vxlan_vni; 812 uint8_t mlfp_rsvd3; 813 uint8_t mlfp_rsvd4[4]; 814 uint8_t mlfp_rsvd5; 815 uint24be_t mlfp_outer_ipv6_flow_label; 816 uint8_t mlfp_rsvd6; 817 uint24be_t mlfp_inner_ipv6_flow_label; 818 uint8_t mlfp_rsvd7[28]; 819 } mlxcx_flow_params_match_t; 820 821 typedef struct { 822 mlxcx_flow_header_match_t mlfm_outer_headers; 823 mlxcx_flow_params_match_t mlfm_misc_parameters; 824 mlxcx_flow_header_match_t mlfm_inner_headers; 825 uint8_t mlfm_rsvd[320]; 826 } mlxcx_flow_match_t; 827 828 #define MLXCX_FLOW_MAX_DESTINATIONS 64 829 typedef enum { 830 MLXCX_FLOW_DEST_VPORT = 0x0, 831 MLXCX_FLOW_DEST_FLOW_TABLE = 0x1, 832 MLXCX_FLOW_DEST_TIR = 0x2, 833 MLXCX_FLOW_DEST_QP = 0x3 834 } mlxcx_flow_destination_type_t; 835 836 typedef struct { 837 uint8_t mlfd_destination_type; 838 uint24be_t mlfd_destination_id; 839 uint8_t mlfd_rsvd[4]; 840 } mlxcx_flow_dest_t; 841 842 typedef enum { 843 MLXCX_FLOW_ACTION_ALLOW = 1 << 0, 844 MLXCX_FLOW_ACTION_DROP = 1 << 1, 845 MLXCX_FLOW_ACTION_FORWARD = 1 << 2, 846 MLXCX_FLOW_ACTION_COUNT = 1 << 3, 847 MLXCX_FLOW_ACTION_ENCAP = 1 << 4, 848 MLXCX_FLOW_ACTION_DECAP = 1 << 5 849 } mlxcx_flow_action_t; 850 851 typedef struct { 852 uint8_t mlfec_rsvd[4]; 853 uint32be_t mlfec_group_id; 854 uint8_t mlfec_rsvd2; 855 uint24be_t mlfec_flow_tag; 856 uint8_t mlfec_rsvd3[2]; 857 uint16be_t mlfec_action; 858 uint8_t mlfec_rsvd4; 859 uint24be_t mlfec_destination_list_size; 860 uint8_t mlfec_rsvd5; 861 uint24be_t mlfec_flow_counter_list_size; 862 uint32be_t mlfec_encap_id; 863 uint8_t mlfec_rsvd6[36]; 864 mlxcx_flow_match_t mlfec_match_value; 865 uint8_t mlfec_rsvd7[192]; 866 mlxcx_flow_dest_t mlfec_destination[MLXCX_FLOW_MAX_DESTINATIONS]; 867 } mlxcx_flow_entry_ctx_t; 868 869 /* CSTYLED */ 870 #define MLXCX_TIR_CTX_DISP_TYPE (bitdef_t){ 4, 0xf0 } 871 typedef enum { 872 MLXCX_TIR_DIRECT = 0x0, 873 MLXCX_TIR_INDIRECT = 0x1, 874 } mlxcx_tir_type_t; 875 876 /* CSTYLED */ 877 #define MLXCX_TIR_LRO_TIMEOUT (bitdef_t){ 12, 0x0ffff000 } 878 /* CSTYLED */ 879 #define MLXCX_TIR_LRO_ENABLE_MASK (bitdef_t){ 8, 0x00000f00 } 880 /* CSTYLED */ 881 #define MLXCX_TIR_LRO_MAX_MSG_SZ (bitdef_t){ 0, 0x000000ff } 882 883 /* CSTYLED */ 884 #define MLXCX_TIR_RX_HASH_FN (bitdef_t){ 4, 0xf0 } 885 typedef enum { 886 MLXCX_TIR_HASH_NONE = 0x0, 887 MLXCX_TIR_HASH_XOR8 = 0x1, 888 MLXCX_TIR_HASH_TOEPLITZ = 0x2 889 } mlxcx_tir_hash_fn_t; 890 #define MLXCX_TIR_LB_UNICAST (1 << 24) 891 #define MLXCX_TIR_LB_MULTICAST (1 << 25) 892 893 /* CSTYLED */ 894 #define MLXCX_RX_HASH_L3_TYPE (bitdef_t){ 31, 0x80000000 } 895 typedef enum { 896 MLXCX_RX_HASH_L3_IPv4 = 0, 897 MLXCX_RX_HASH_L3_IPv6 = 1 898 } mlxcx_tir_rx_hash_l3_type_t; 899 /* CSTYLED */ 900 #define MLXCX_RX_HASH_L4_TYPE (bitdef_t){ 30, 0x40000000 } 901 typedef enum { 902 MLXCX_RX_HASH_L4_TCP = 0, 903 MLXCX_RX_HASH_L4_UDP = 1 904 } mlxcx_tir_rx_hash_l4_type_t; 905 /* CSTYLED */ 906 #define MLXCX_RX_HASH_FIELDS (bitdef_t){ 0, 0x3fffffff } 907 typedef enum { 908 MLXCX_RX_HASH_SRC_IP = 1 << 0, 909 MLXCX_RX_HASH_DST_IP = 1 << 1, 910 MLXCX_RX_HASH_L4_SPORT = 1 << 2, 911 MLXCX_RX_HASH_L4_DPORT = 1 << 3, 912 MLXCX_RX_HASH_IPSEC_SPI = 1 << 4 913 } mlxcx_tir_rx_hash_fields_t; 914 915 typedef struct { 916 uint8_t mltirc_rsvd[4]; 917 bits8_t mltirc_disp_type; 918 uint8_t mltirc_rsvd2[11]; 919 bits32_t mltirc_lro; 920 uint8_t mltirc_rsvd3[9]; 921 uint24be_t mltirc_inline_rqn; 922 bits8_t mltirc_flags; 923 uint24be_t mltirc_indirect_table; 924 bits8_t mltirc_hash_lb; 925 uint24be_t mltirc_transport_domain; 926 uint8_t mltirc_rx_hash_toeplitz_key[40]; 927 bits32_t mltirc_rx_hash_fields_outer; 928 bits32_t mltirc_rx_hash_fields_inner; 929 uint8_t mltirc_rsvd4[152]; 930 } mlxcx_tir_ctx_t; 931 932 typedef struct { 933 uint8_t mltisc_rsvd; 934 uint8_t mltisc_prio_or_sl; 935 uint8_t mltisc_rsvd2[35]; 936 uint24be_t mltisc_transport_domain; 937 uint8_t mltisc_rsvd3[120]; 938 } mlxcx_tis_ctx_t; 939 940 #define MLXCX_RQT_MAX_RQ_REFS 64 941 942 typedef struct { 943 uint8_t mlrqtr_rsvd; 944 uint24be_t mlrqtr_rqn; 945 } mlxcx_rqtable_rq_ref_t; 946 947 typedef struct { 948 uint8_t mlrqtc_rsvd[22]; 949 uint16be_t mlrqtc_max_size; 950 uint8_t mlrqtc_rsvd2[2]; 951 uint16be_t mlrqtc_actual_size; 952 uint8_t mlrqtc_rsvd3[212]; 953 mlxcx_rqtable_rq_ref_t mlrqtc_rqref[MLXCX_RQT_MAX_RQ_REFS]; 954 } mlxcx_rqtable_ctx_t; 955 956 #pragma pack() 957 958 typedef enum { 959 MLXCX_EVENT_COMPLETION = 0x00, 960 MLXCX_EVENT_PATH_MIGRATED = 0x01, 961 MLXCX_EVENT_COMM_ESTABLISH = 0x02, 962 MLXCX_EVENT_SENDQ_DRAIN = 0x03, 963 MLXCX_EVENT_LAST_WQE = 0x13, 964 MLXCX_EVENT_SRQ_LIMIT = 0x14, 965 MLXCX_EVENT_DCT_ALL_CLOSED = 0x1C, 966 MLXCX_EVENT_DCT_ACCKEY_VIOL = 0x1D, 967 MLXCX_EVENT_CQ_ERROR = 0x04, 968 MLXCX_EVENT_WQ_CATASTROPHE = 0x05, 969 MLXCX_EVENT_PATH_MIGRATE_FAIL = 0x07, 970 MLXCX_EVENT_PAGE_FAULT = 0x0C, 971 MLXCX_EVENT_WQ_INVALID_REQ = 0x10, 972 MLXCX_EVENT_WQ_ACCESS_VIOL = 0x11, 973 MLXCX_EVENT_SRQ_CATASTROPHE = 0x12, 974 MLXCX_EVENT_INTERNAL_ERROR = 0x08, 975 MLXCX_EVENT_PORT_STATE = 0x09, 976 MLXCX_EVENT_GPIO = 0x15, 977 MLXCX_EVENT_PORT_MODULE = 0x16, 978 MLXCX_EVENT_TEMP_WARNING = 0x17, 979 MLXCX_EVENT_REMOTE_CONFIG = 0x19, 980 MLXCX_EVENT_DCBX_CHANGE = 0x1E, 981 MLXCX_EVENT_DOORBELL_CONGEST = 0x1A, 982 MLXCX_EVENT_STALL_VL = 0x1B, 983 MLXCX_EVENT_CMD_COMPLETION = 0x0A, 984 MLXCX_EVENT_PAGE_REQUEST = 0x0B, 985 MLXCX_EVENT_NIC_VPORT = 0x0D, 986 MLXCX_EVENT_EC_PARAMS_CHANGE = 0x0E, 987 MLXCX_EVENT_XRQ_ERROR = 0x18 988 } mlxcx_event_t; 989 990 typedef enum { 991 MLXCX_CMD_R_OK = 0x00, 992 MLXCX_CMD_R_INTERNAL_ERR = 0x01, 993 MLXCX_CMD_R_BAD_OP = 0x02, 994 MLXCX_CMD_R_BAD_PARAM = 0x03, 995 MLXCX_CMD_R_BAD_SYS_STATE = 0x04, 996 MLXCX_CMD_R_BAD_RESOURCE = 0x05, 997 MLXCX_CMD_R_RESOURCE_BUSY = 0x06, 998 MLXCX_CMD_R_EXCEED_LIM = 0x08, 999 MLXCX_CMD_R_BAD_RES_STATE = 0x09, 1000 MLXCX_CMD_R_BAD_INDEX = 0x0a, 1001 MLXCX_CMD_R_NO_RESOURCES = 0x0f, 1002 MLXCX_CMD_R_BAD_INPUT_LEN = 0x50, 1003 MLXCX_CMD_R_BAD_OUTPUT_LEN = 0x51, 1004 MLXCX_CMD_R_BAD_RESOURCE_STATE = 0x10, 1005 MLXCX_CMD_R_BAD_PKT = 0x30, 1006 MLXCX_CMD_R_BAD_SIZE = 0x40, 1007 MLXCX_CMD_R_TIMEOUT = 0xFF 1008 } mlxcx_cmd_ret_t; 1009 1010 typedef enum { 1011 MLXCX_OP_QUERY_HCA_CAP = 0x100, 1012 MLXCX_OP_QUERY_ADAPTER = 0x101, 1013 MLXCX_OP_INIT_HCA = 0x102, 1014 MLXCX_OP_TEARDOWN_HCA = 0x103, 1015 MLXCX_OP_ENABLE_HCA = 0x104, 1016 MLXCX_OP_DISABLE_HCA = 0x105, 1017 MLXCX_OP_QUERY_PAGES = 0x107, 1018 MLXCX_OP_MANAGE_PAGES = 0x108, 1019 MLXCX_OP_SET_HCA_CAP = 0x109, 1020 MLXCX_OP_QUERY_ISSI = 0x10A, 1021 MLXCX_OP_SET_ISSI = 0x10B, 1022 MLXCX_OP_SET_DRIVER_VERSION = 0x10D, 1023 MLXCX_OP_QUERY_OTHER_HCA_CAP = 0x10E, 1024 MLXCX_OP_MODIFY_OTHER_HCA_CAP = 0x10F, 1025 MLXCX_OP_SET_TUNNELED_OPERATIONS = 0x110, 1026 MLXCX_OP_CREATE_MKEY = 0x200, 1027 MLXCX_OP_QUERY_MKEY = 0x201, 1028 MLXCX_OP_DESTROY_MKEY = 0x202, 1029 MLXCX_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 1030 MLXCX_OP_PAGE_FAULT_RESUME = 0x204, 1031 MLXCX_OP_CREATE_EQ = 0x301, 1032 MLXCX_OP_DESTROY_EQ = 0x302, 1033 MLXCX_OP_QUERY_EQ = 0x303, 1034 MLXCX_OP_GEN_EQE = 0x304, 1035 MLXCX_OP_CREATE_CQ = 0x400, 1036 MLXCX_OP_DESTROY_CQ = 0x401, 1037 MLXCX_OP_QUERY_CQ = 0x402, 1038 MLXCX_OP_MODIFY_CQ = 0x403, 1039 MLXCX_OP_CREATE_QP = 0x500, 1040 MLXCX_OP_DESTROY_QP = 0x501, 1041 MLXCX_OP_RST2INIT_QP = 0x502, 1042 MLXCX_OP_INIT2RTR_QP = 0x503, 1043 MLXCX_OP_RTR2RTS_QP = 0x504, 1044 MLXCX_OP_RTS2RTS_QP = 0x505, 1045 MLXCX_OP_SQERR2RTS_QP = 0x506, 1046 MLXCX_OP__2ERR_QP = 0x507, 1047 MLXCX_OP__2RST_QP = 0x50A, 1048 MLXCX_OP_QUERY_QP = 0x50B, 1049 MLXCX_OP_SQD_RTS_QP = 0x50C, 1050 MLXCX_OP_INIT2INIT_QP = 0x50E, 1051 MLXCX_OP_CREATE_PSV = 0x600, 1052 MLXCX_OP_DESTROY_PSV = 0x601, 1053 MLXCX_OP_CREATE_SRQ = 0x700, 1054 MLXCX_OP_DESTROY_SRQ = 0x701, 1055 MLXCX_OP_QUERY_SRQ = 0x702, 1056 MLXCX_OP_ARM_RQ = 0x703, 1057 MLXCX_OP_CREATE_XRC_SRQ = 0x705, 1058 MLXCX_OP_DESTROY_XRC_SRQ = 0x706, 1059 MLXCX_OP_QUERY_XRC_SRQ = 0x707, 1060 MLXCX_OP_ARM_XRC_SRQ = 0x708, 1061 MLXCX_OP_CREATE_DCT = 0x710, 1062 MLXCX_OP_DESTROY_DCT = 0x711, 1063 MLXCX_OP_DRAIN_DCT = 0x712, 1064 MLXCX_OP_QUERY_DCT = 0x713, 1065 MLXCX_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 1066 MLXCX_OP_CREATE_XRQ = 0x717, 1067 MLXCX_OP_DESTROY_XRQ = 0x718, 1068 MLXCX_OP_QUERY_XRQ = 0x719, 1069 MLXCX_OP_CREATE_NVMF_BACKEND_CONTROLLER = 0x720, 1070 MLXCX_OP_DESTROY_NVMF_BACKEND_CONTROLLER = 0x721, 1071 MLXCX_OP_QUERY_NVMF_BACKEND_CONTROLLER = 0x722, 1072 MLXCX_OP_ATTACH_NVMF_NAMESPACE = 0x723, 1073 MLXCX_OP_DETACH_NVMF_NAMESPACE = 0x724, 1074 MLXCX_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 1075 MLXCX_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 1076 MLXCX_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 1077 MLXCX_OP_QUERY_VPORT_STATE = 0x750, 1078 MLXCX_OP_MODIFY_VPORT_STATE = 0x751, 1079 MLXCX_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 1080 MLXCX_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 1081 MLXCX_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1082 MLXCX_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 1083 MLXCX_OP_QUERY_ROCE_ADDRESS = 0x760, 1084 MLXCX_OP_SET_ROCE_ADDRESS = 0x761, 1085 MLXCX_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 1086 MLXCX_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 1087 MLXCX_OP_QUERY_HCA_VPORT_GID = 0x764, 1088 MLXCX_OP_QUERY_HCA_VPORT_PKEY = 0x765, 1089 MLXCX_OP_QUERY_VPORT_COUNTER = 0x770, 1090 MLXCX_OP_ALLOC_Q_COUNTER = 0x771, 1091 MLXCX_OP_DEALLOC_Q_COUNTER = 0x772, 1092 MLXCX_OP_QUERY_Q_COUNTER = 0x773, 1093 MLXCX_OP_SET_PP_RATE_LIMIT = 0x780, 1094 MLXCX_OP_QUERY_PP_RATE_LIMIT = 0x781, 1095 MLXCX_OP_ALLOC_PD = 0x800, 1096 MLXCX_OP_DEALLOC_PD = 0x801, 1097 MLXCX_OP_ALLOC_UAR = 0x802, 1098 MLXCX_OP_DEALLOC_UAR = 0x803, 1099 MLXCX_OP_CONFIG_INT_MODERATION = 0x804, 1100 MLXCX_OP_ACCESS_REG = 0x805, 1101 MLXCX_OP_ATTACH_TO_MCG = 0x806, 1102 MLXCX_OP_DETACH_FROM_MCG = 0x807, 1103 MLXCX_OP_MAD_IFC = 0x50D, 1104 MLXCX_OP_QUERY_MAD_DEMUX = 0x80B, 1105 MLXCX_OP_SET_MAD_DEMUX = 0x80C, 1106 MLXCX_OP_NOP = 0x80D, 1107 MLXCX_OP_ALLOC_XRCD = 0x80E, 1108 MLXCX_OP_DEALLOC_XRCD = 0x80F, 1109 MLXCX_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1110 MLXCX_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 1111 MLXCX_OP_QUERY_CONG_STATUS = 0x822, 1112 MLXCX_OP_MODIFY_CONG_STATUS = 0x823, 1113 MLXCX_OP_QUERY_CONG_PARAMS = 0x824, 1114 MLXCX_OP_MODIFY_CONG_PARAMS = 0x825, 1115 MLXCX_OP_QUERY_CONG_STATISTICS = 0x826, 1116 MLXCX_OP_ADD_VXLAN_UDP_DPORT = 0x827, 1117 MLXCX_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 1118 MLXCX_OP_SET_L2_TABLE_ENTRY = 0x829, 1119 MLXCX_OP_QUERY_L2_TABLE_ENTRY = 0x82A, 1120 MLXCX_OP_DELETE_L2_TABLE_ENTRY = 0x82B, 1121 MLXCX_OP_SET_WOL_ROL = 0x830, 1122 MLXCX_OP_QUERY_WOL_ROL = 0x831, 1123 MLXCX_OP_CREATE_TIR = 0x900, 1124 MLXCX_OP_MODIFY_TIR = 0x901, 1125 MLXCX_OP_DESTROY_TIR = 0x902, 1126 MLXCX_OP_QUERY_TIR = 0x903, 1127 MLXCX_OP_CREATE_SQ = 0x904, 1128 MLXCX_OP_MODIFY_SQ = 0x905, 1129 MLXCX_OP_DESTROY_SQ = 0x906, 1130 MLXCX_OP_QUERY_SQ = 0x907, 1131 MLXCX_OP_CREATE_RQ = 0x908, 1132 MLXCX_OP_MODIFY_RQ = 0x909, 1133 MLXCX_OP_DESTROY_RQ = 0x90A, 1134 MLXCX_OP_QUERY_RQ = 0x90B, 1135 MLXCX_OP_CREATE_RMP = 0x90C, 1136 MLXCX_OP_MODIFY_RMP = 0x90D, 1137 MLXCX_OP_DESTROY_RMP = 0x90E, 1138 MLXCX_OP_QUERY_RMP = 0x90F, 1139 MLXCX_OP_CREATE_TIS = 0x912, 1140 MLXCX_OP_MODIFY_TIS = 0x913, 1141 MLXCX_OP_DESTROY_TIS = 0x914, 1142 MLXCX_OP_QUERY_TIS = 0x915, 1143 MLXCX_OP_CREATE_RQT = 0x916, 1144 MLXCX_OP_MODIFY_RQT = 0x917, 1145 MLXCX_OP_DESTROY_RQT = 0x918, 1146 MLXCX_OP_QUERY_RQT = 0x919, 1147 MLXCX_OP_SET_FLOW_TABLE_ROOT = 0x92f, 1148 MLXCX_OP_CREATE_FLOW_TABLE = 0x930, 1149 MLXCX_OP_DESTROY_FLOW_TABLE = 0x931, 1150 MLXCX_OP_QUERY_FLOW_TABLE = 0x932, 1151 MLXCX_OP_CREATE_FLOW_GROUP = 0x933, 1152 MLXCX_OP_DESTROY_FLOW_GROUP = 0x934, 1153 MLXCX_OP_QUERY_FLOW_GROUP = 0x935, 1154 MLXCX_OP_SET_FLOW_TABLE_ENTRY = 0x936, 1155 MLXCX_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 1156 MLXCX_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 1157 MLXCX_OP_ALLOC_FLOW_COUNTER = 0x939, 1158 MLXCX_OP_DEALLOC_FLOW_COUNTER = 0x93a, 1159 MLXCX_OP_QUERY_FLOW_COUNTER = 0x93b, 1160 MLXCX_OP_MODIFY_FLOW_TABLE = 0x93c, 1161 MLXCX_OP_ALLOC_ENCAP_HEADER = 0x93d, 1162 MLXCX_OP_DEALLOC_ENCAP_HEADER = 0x93e, 1163 MLXCX_OP_QUERY_ENCAP_HEADER = 0x93f 1164 } mlxcx_cmd_op_t; 1165 1166 /* 1167 * Definitions for relevant commands 1168 */ 1169 #pragma pack(1) 1170 typedef struct { 1171 uint16be_t mci_opcode; 1172 uint8_t mci_rsvd[4]; 1173 uint16be_t mci_op_mod; 1174 } mlxcx_cmd_in_t; 1175 1176 typedef struct { 1177 uint8_t mco_status; 1178 uint8_t mco_rsvd[3]; 1179 uint32be_t mco_syndrome; 1180 } mlxcx_cmd_out_t; 1181 1182 typedef struct { 1183 mlxcx_cmd_in_t mlxi_enable_hca_head; 1184 uint8_t mlxi_enable_hca_rsvd[2]; 1185 uint16be_t mlxi_enable_hca_func; 1186 uint8_t mlxi_enable_hca_rsvd1[4]; 1187 } mlxcx_cmd_enable_hca_in_t; 1188 1189 typedef struct { 1190 mlxcx_cmd_out_t mlxo_enable_hca_head; 1191 uint8_t mlxo_enable_hca_rsvd[8]; 1192 } mlxcx_cmd_enable_hca_out_t; 1193 1194 typedef struct { 1195 mlxcx_cmd_in_t mlxi_disable_hca_head; 1196 uint8_t mlxi_disable_hca_rsvd[2]; 1197 uint16be_t mlxi_disable_hca_func; 1198 uint8_t mlxi_disable_hca_rsvd1[4]; 1199 } mlxcx_cmd_disable_hca_in_t; 1200 1201 typedef struct { 1202 mlxcx_cmd_out_t mlxo_disable_hca_head; 1203 uint8_t mlxo_disable_hca_rsvd[8]; 1204 } mlxcx_cmd_disable_hca_out_t; 1205 1206 typedef struct { 1207 mlxcx_cmd_in_t mlxi_query_issi_head; 1208 uint8_t mlxi_query_issi_rsvd[8]; 1209 } mlxcx_cmd_query_issi_in_t; 1210 1211 typedef struct { 1212 mlxcx_cmd_out_t mlxo_query_issi_head; 1213 uint8_t mlxo_query_issi_rsv[2]; 1214 uint16be_t mlxo_query_issi_current; 1215 uint8_t mlxo_query_issi_rsvd1[20]; 1216 /* 1217 * To date we only support version 1 of the ISSI. The last byte has the 1218 * ISSI data that we care about, therefore we phrase the struct this 1219 * way. 1220 */ 1221 uint8_t mlxo_query_issi_rsvd2[79]; 1222 uint8_t mlxo_supported_issi; 1223 } mlxcx_cmd_query_issi_out_t; 1224 1225 typedef struct { 1226 mlxcx_cmd_in_t mlxi_set_issi_head; 1227 uint8_t mlxi_set_issi_rsvd[2]; 1228 uint16be_t mlxi_set_issi_current; 1229 uint8_t mlxi_set_iss_rsvd1[4]; 1230 } mlxcx_cmd_set_issi_in_t; 1231 1232 typedef struct { 1233 mlxcx_cmd_out_t mlxo_set_issi_head; 1234 uint8_t mlxo_set_issi_rsvd[8]; 1235 } mlxcx_cmd_set_issi_out_t; 1236 1237 typedef struct { 1238 mlxcx_cmd_in_t mlxi_init_hca_head; 1239 uint8_t mlxi_init_hca_rsvd[8]; 1240 } mlxcx_cmd_init_hca_in_t; 1241 1242 typedef struct { 1243 mlxcx_cmd_out_t mlxo_init_hca_head; 1244 uint8_t mlxo_init_hca_rsvd[8]; 1245 } mlxcx_cmd_init_hca_out_t; 1246 1247 #define MLXCX_TEARDOWN_HCA_GRACEFUL 0x00 1248 #define MLXCX_TEARDOWN_HCA_FORCE 0x01 1249 1250 typedef struct { 1251 mlxcx_cmd_in_t mlxi_teardown_hca_head; 1252 uint8_t mlxi_teardown_hca_rsvd[2]; 1253 uint16be_t mlxi_teardown_hca_profile; 1254 uint8_t mlxi_teardown_hca_rsvd1[4]; 1255 } mlxcx_cmd_teardown_hca_in_t; 1256 1257 typedef struct { 1258 mlxcx_cmd_out_t mlxo_teardown_hca_head; 1259 uint8_t mlxo_teardown_hca_rsvd[7]; 1260 uint8_t mlxo_teardown_hca_state; 1261 } mlxcx_cmd_teardown_hca_out_t; 1262 1263 #define MLXCX_QUERY_PAGES_OPMOD_BOOT 0x01 1264 #define MLXCX_QUERY_PAGES_OPMOD_INIT 0x02 1265 #define MLXCX_QUERY_PAGES_OPMOD_REGULAR 0x03 1266 1267 typedef struct { 1268 mlxcx_cmd_in_t mlxi_query_pages_head; 1269 uint8_t mlxi_query_pages_rsvd[2]; 1270 uint16be_t mlxi_query_pages_func; 1271 uint8_t mlxi_query_pages_rsvd1[4]; 1272 } mlxcx_cmd_query_pages_in_t; 1273 1274 typedef struct { 1275 mlxcx_cmd_out_t mlxo_query_pages_head; 1276 uint8_t mlxo_query_pages_rsvd[2]; 1277 uint16be_t mlxo_query_pages_func; 1278 uint32be_t mlxo_query_pages_npages; 1279 } mlxcx_cmd_query_pages_out_t; 1280 1281 #define MLXCX_MANAGE_PAGES_OPMOD_ALLOC_FAIL 0x00 1282 #define MLXCX_MANAGE_PAGES_OPMOD_GIVE_PAGES 0x01 1283 #define MLXCX_MANAGE_PAGES_OPMOD_RETURN_PAGES 0x02 1284 1285 /* 1286 * This is an artificial limit that we're imposing on our actions. 1287 */ 1288 #define MLXCX_MANAGE_PAGES_MAX_PAGES 512 1289 1290 typedef struct { 1291 mlxcx_cmd_in_t mlxi_manage_pages_head; 1292 uint8_t mlxi_manage_pages_rsvd[2]; 1293 uint16be_t mlxi_manage_pages_func; 1294 uint32be_t mlxi_manage_pages_npages; 1295 uint64be_t mlxi_manage_pages_pas[MLXCX_MANAGE_PAGES_MAX_PAGES]; 1296 } mlxcx_cmd_manage_pages_in_t; 1297 1298 typedef struct { 1299 mlxcx_cmd_out_t mlxo_manage_pages_head; 1300 uint32be_t mlxo_manage_pages_npages; 1301 uint8_t mlxo_manage_pages_rsvd[4]; 1302 uint64be_t mlxo_manage_pages_pas[MLXCX_MANAGE_PAGES_MAX_PAGES]; 1303 } mlxcx_cmd_manage_pages_out_t; 1304 1305 typedef enum { 1306 MLXCX_HCA_CAP_MODE_MAX = 0x0, 1307 MLXCX_HCA_CAP_MODE_CURRENT = 0x1 1308 } mlxcx_hca_cap_mode_t; 1309 1310 typedef enum { 1311 MLXCX_HCA_CAP_GENERAL = 0x0, 1312 MLXCX_HCA_CAP_ETHERNET = 0x1, 1313 MLXCX_HCA_CAP_ODP = 0x2, 1314 MLXCX_HCA_CAP_ATOMIC = 0x3, 1315 MLXCX_HCA_CAP_ROCE = 0x4, 1316 MLXCX_HCA_CAP_IPoIB = 0x5, 1317 MLXCX_HCA_CAP_NIC_FLOW = 0x7, 1318 MLXCX_HCA_CAP_ESWITCH_FLOW = 0x8, 1319 MLXCX_HCA_CAP_ESWITCH = 0x9, 1320 MLXCX_HCA_CAP_VECTOR = 0xb, 1321 MLXCX_HCA_CAP_QoS = 0xc, 1322 MLXCX_HCA_CAP_NVMEoF = 0xe 1323 } mlxcx_hca_cap_type_t; 1324 1325 typedef enum { 1326 MLXCX_CAP_GENERAL_PORT_TYPE_IB = 0x0, 1327 MLXCX_CAP_GENERAL_PORT_TYPE_ETHERNET = 0x1, 1328 } mlxcx_hca_cap_general_port_type_t; 1329 1330 typedef enum { 1331 MLXCX_CAP_GENERAL_FLAGS_C_ESW_FLOW_TABLE = (1 << 8), 1332 MLXCX_CAP_GENERAL_FLAGS_C_NIC_FLOW_TABLE = (1 << 9), 1333 } mlxcx_hca_cap_general_flags_c_t; 1334 1335 typedef struct { 1336 uint8_t mlcap_general_access_other_hca_roce; 1337 uint8_t mlcap_general_rsvd[3]; 1338 1339 uint8_t mlcap_general_rsvd2[12]; 1340 1341 uint8_t mlcap_general_log_max_srq_sz; 1342 uint8_t mlcap_general_log_max_qp_sz; 1343 uint8_t mlcap_general_rsvd3[1]; 1344 uint8_t mlcap_general_log_max_qp; 1345 1346 uint8_t mlcap_general_rsvd4[1]; 1347 uint8_t mlcap_general_log_max_srq; 1348 uint8_t mlcap_general_rsvd5[2]; 1349 1350 uint8_t mlcap_general_rsvd6[1]; 1351 uint8_t mlcap_general_log_max_cq_sz; 1352 uint8_t mlcap_general_rsvd7[1]; 1353 uint8_t mlcap_general_log_max_cq; 1354 1355 uint8_t mlcap_general_log_max_eq_sz; 1356 uint8_t mlcap_general_log_max_mkey_flags; 1357 uint8_t mlcap_general_rsvd8[1]; 1358 uint8_t mlcap_general_log_max_eq; 1359 1360 uint8_t mlcap_general_max_indirection; 1361 uint8_t mlcap_general_log_max_mrw_sz_flags; 1362 uint8_t mlcap_general_log_max_bsf_list_size_flags; 1363 uint8_t mlcap_general_log_max_klm_list_size_flags; 1364 1365 uint8_t mlcap_general_rsvd9[1]; 1366 uint8_t mlcap_general_log_max_ra_req_dc; 1367 uint8_t mlcap_general_rsvd10[1]; 1368 uint8_t mlcap_general_log_max_ra_res_dc; 1369 1370 uint8_t mlcap_general_rsvd11[1]; 1371 uint8_t mlcap_general_log_max_ra_req_qp; 1372 uint8_t mlcap_general_rsvd12[1]; 1373 uint8_t mlcap_general_log_max_ra_res_qp; 1374 1375 uint16be_t mlcap_general_flags_a; 1376 uint16be_t mlcap_general_gid_table_size; 1377 1378 bits16_t mlcap_general_flags_b; 1379 uint16be_t mlcap_general_pkey_table_size; 1380 1381 bits16_t mlcap_general_flags_c; 1382 struct { 1383 #if defined(_BIT_FIELDS_HTOL) 1384 uint8_t mlcap_general_flags_d:6; 1385 uint8_t mlcap_general_port_type:2; 1386 #elif defined(_BIT_FIELDS_LTOH) 1387 uint8_t mlcap_general_port_type:2; 1388 uint8_t mlcap_general_flags_d:6; 1389 #endif 1390 }; 1391 uint8_t mlcap_general_num_ports; 1392 1393 struct { 1394 #if defined(_BIT_FIELDS_HTOL) 1395 uint8_t mlcap_general_rsvd13:3; 1396 uint8_t mlcap_general_log_max_msg:5; 1397 #elif defined(_BIT_FIELDS_LTOH) 1398 uint8_t mlcap_general_log_max_msg:5; 1399 uint8_t mlcap_general_rsvd13:3; 1400 #endif 1401 }; 1402 uint8_t mlcap_general_max_tc; 1403 bits16_t mlcap_general_flags_d_wol; 1404 1405 uint16be_t mlcap_general_state_rate_support; 1406 uint8_t mlcap_general_rsvd14[1]; 1407 struct { 1408 #if defined(_BIT_FIELDS_HTOL) 1409 uint8_t mlcap_general_rsvd15:4; 1410 uint8_t mlcap_general_cqe_version:4; 1411 #elif defined(_BIT_FIELDS_LTOH) 1412 uint8_t mlcap_general_cqe_version:4; 1413 uint8_t mlcap_general_rsvd15:4; 1414 #endif 1415 }; 1416 1417 uint32be_t mlcap_general_flags_e; 1418 1419 uint32be_t mlcap_general_flags_f; 1420 1421 uint8_t mlcap_general_rsvd16[1]; 1422 uint8_t mlcap_general_uar_sz; 1423 uint8_t mlcap_general_cnak; 1424 uint8_t mlcap_general_log_pg_sz; 1425 uint8_t mlcap_general_rsvd17[32]; 1426 bits8_t mlcap_general_log_max_rq_flags; 1427 uint8_t mlcap_general_log_max_sq; 1428 uint8_t mlcap_general_log_max_tir; 1429 uint8_t mlcap_general_log_max_tis; 1430 } mlxcx_hca_cap_general_caps_t; 1431 1432 typedef enum { 1433 MLXCX_ETH_CAP_TUNNEL_STATELESS_VXLAN = 1 << 0, 1434 MLXCX_ETH_CAP_TUNNEL_STATELESS_GRE = 1 << 1, 1435 MLXCX_ETH_CAP_TUNNEL_LSO_CONST_OUT_IP_ID = 1 << 4, 1436 MLXCX_ETH_CAP_SCATTER_FCS = 1 << 6, 1437 MLXCX_ETH_CAP_REG_UMR_SQ = 1 << 7, 1438 MLXCX_ETH_CAP_SELF_LB_UC = 1 << 21, 1439 MLXCX_ETH_CAP_SELF_LB_MC = 1 << 22, 1440 MLXCX_ETH_CAP_SELF_LB_EN_MODIFIABLE = 1 << 23, 1441 MLXCX_ETH_CAP_WQE_VLAN_INSERT = 1 << 24, 1442 MLXCX_ETH_CAP_LRO_TIME_STAMP = 1 << 27, 1443 MLXCX_ETH_CAP_LRO_PSH_FLAG = 1 << 28, 1444 MLXCX_ETH_CAP_LRO_CAP = 1 << 29, 1445 MLXCX_ETH_CAP_VLAN_STRIP = 1 << 30, 1446 MLXCX_ETH_CAP_CSUM_CAP = 1UL << 31 1447 } mlxcx_hca_eth_cap_flags_t; 1448 1449 /* CSTYLED */ 1450 #define MLXCX_ETH_CAP_RSS_IND_TBL_CAP (bitdef_t){8, 0x00000f00} 1451 /* CSTYLED */ 1452 #define MLXCX_ETH_CAP_WQE_INLINE_MODE (bitdef_t){12, 0x00003000} 1453 /* CSTYLED */ 1454 #define MLXCX_ETH_CAP_MULTI_PKT_SEND_WQE (bitdef_t){14, 0x0000c000} 1455 /* CSTYLED */ 1456 #define MLXCX_ETH_CAP_MAX_LSO_CAP (bitdef_t){16, 0x001f0000} 1457 /* CSTYLED */ 1458 #define MLXCX_ETH_CAP_LRO_MAX_MSG_SZ_MODE (bitdef_t){25, 0x06000000} 1459 1460 typedef struct { 1461 bits32_t mlcap_eth_flags; 1462 uint8_t mlcap_eth_rsvd[6]; 1463 uint16be_t mlcap_eth_lro_min_mss_size; 1464 uint8_t mlcap_eth_rsvd2[36]; 1465 uint32be_t mlcap_eth_lro_timer_supported_periods[4]; 1466 } mlxcx_hca_cap_eth_caps_t; 1467 1468 typedef enum { 1469 MLXCX_FLOW_CAP_PROPS_DECAP = 1 << 23, 1470 MLXCX_FLOW_CAP_PROPS_ENCAP = 1 << 24, 1471 MLXCX_FLOW_CAP_PROPS_MODIFY_TBL = 1 << 25, 1472 MLXCX_FLOW_CAP_PROPS_MISS_TABLE = 1 << 26, 1473 MLXCX_FLOW_CAP_PROPS_MODIFY_ROOT_TBL = 1 << 27, 1474 MLXCX_FLOW_CAP_PROPS_MODIFY = 1 << 28, 1475 MLXCX_FLOW_CAP_PROPS_COUNTER = 1 << 29, 1476 MLXCX_FLOW_CAP_PROPS_TAG = 1 << 30, 1477 MLXCX_FLOW_CAP_PROPS_SUPPORT = 1UL << 31 1478 } mlxcx_hca_cap_flow_cap_props_flags_t; 1479 1480 typedef struct { 1481 bits32_t mlcap_flow_prop_flags; 1482 uint8_t mlcap_flow_prop_log_max_ft_size; 1483 uint8_t mlcap_flow_prop_rsvd[2]; 1484 uint8_t mlcap_flow_prop_max_ft_level; 1485 uint8_t mlcap_flow_prop_rsvd2[7]; 1486 uint8_t mlcap_flow_prop_log_max_ft_num; 1487 uint8_t mlcap_flow_prop_rsvd3[2]; 1488 uint8_t mlcap_flow_prop_log_max_flow_counter; 1489 uint8_t mlcap_flow_prop_log_max_destination; 1490 uint8_t mlcap_flow_prop_rsvd4[3]; 1491 uint8_t mlcap_flow_prop_log_max_flow; 1492 uint8_t mlcap_flow_prop_rsvd5[8]; 1493 bits32_t mlcap_flow_prop_support[4]; 1494 bits32_t mlcap_flow_prop_bitmask[4]; 1495 } mlxcx_hca_cap_flow_cap_props_t; 1496 1497 typedef struct { 1498 bits32_t mlcap_flow_flags; 1499 uint8_t mlcap_flow_rsvd[60]; 1500 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx; 1501 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_rdma; 1502 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_sniffer; 1503 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx; 1504 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_rdma; 1505 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_sniffer; 1506 } mlxcx_hca_cap_flow_caps_t; 1507 1508 /* 1509 * Size of a buffer that is required to hold the output data. 1510 */ 1511 #define MLXCX_HCA_CAP_SIZE 0x1000 1512 1513 typedef struct { 1514 mlxcx_cmd_in_t mlxi_query_hca_cap_head; 1515 uint8_t mlxi_query_hca_cap_rsvd[8]; 1516 } mlxcx_cmd_query_hca_cap_in_t; 1517 1518 typedef struct { 1519 mlxcx_cmd_out_t mlxo_query_hca_cap_head; 1520 uint8_t mlxo_query_hca_cap_rsvd[8]; 1521 uint8_t mlxo_query_hca_cap_data[MLXCX_HCA_CAP_SIZE]; 1522 } mlxcx_cmd_query_hca_cap_out_t; 1523 1524 typedef struct { 1525 mlxcx_cmd_in_t mlxi_set_driver_version_head; 1526 uint8_t mlxi_set_driver_version_rsvd[8]; 1527 char mlxi_set_driver_version_version[64]; 1528 } mlxcx_cmd_set_driver_version_in_t; 1529 1530 typedef struct { 1531 mlxcx_cmd_out_t mlxo_set_driver_version_head; 1532 uint8_t mlxo_set_driver_version_rsvd[8]; 1533 } mlxcx_cmd_set_driver_version_out_t; 1534 1535 typedef struct { 1536 mlxcx_cmd_in_t mlxi_alloc_uar_head; 1537 uint8_t mlxi_alloc_uar_rsvd[8]; 1538 } mlxcx_cmd_alloc_uar_in_t; 1539 1540 typedef struct { 1541 mlxcx_cmd_out_t mlxo_alloc_uar_head; 1542 uint8_t mlxo_alloc_uar_rsvd; 1543 uint24be_t mlxo_alloc_uar_uar; 1544 uint8_t mlxo_alloc_uar_rsvd2[4]; 1545 } mlxcx_cmd_alloc_uar_out_t; 1546 1547 typedef struct { 1548 mlxcx_cmd_in_t mlxi_dealloc_uar_head; 1549 uint8_t mlxi_dealloc_uar_rsvd; 1550 uint24be_t mlxi_dealloc_uar_uar; 1551 uint8_t mlxi_dealloc_uar_rsvd2[4]; 1552 } mlxcx_cmd_dealloc_uar_in_t; 1553 1554 typedef struct { 1555 mlxcx_cmd_out_t mlxo_dealloc_uar_head; 1556 uint8_t mlxo_dealloc_uar_rsvd[8]; 1557 } mlxcx_cmd_dealloc_uar_out_t; 1558 1559 /* 1560 * This is an artificial limit that we're imposing on our actions. 1561 */ 1562 #define MLXCX_CREATE_QUEUE_MAX_PAGES 128 1563 1564 typedef struct { 1565 mlxcx_cmd_in_t mlxi_create_eq_head; 1566 uint8_t mlxi_create_eq_rsvd[8]; 1567 mlxcx_eventq_ctx_t mlxi_create_eq_context; 1568 uint8_t mlxi_create_eq_rsvd2[8]; 1569 uint64be_t mlxi_create_eq_event_bitmask; 1570 uint8_t mlxi_create_eq_rsvd3[176]; 1571 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1572 } mlxcx_cmd_create_eq_in_t; 1573 1574 typedef struct { 1575 mlxcx_cmd_out_t mlxo_create_eq_head; 1576 uint8_t mlxo_create_eq_rsvd[3]; 1577 uint8_t mlxo_create_eq_eqn; 1578 uint8_t mlxo_create_eq_rsvd2[4]; 1579 } mlxcx_cmd_create_eq_out_t; 1580 1581 typedef struct { 1582 mlxcx_cmd_in_t mlxi_query_eq_head; 1583 uint8_t mlxi_query_eq_rsvd[3]; 1584 uint8_t mlxi_query_eq_eqn; 1585 uint8_t mlxi_query_eq_rsvd2[4]; 1586 } mlxcx_cmd_query_eq_in_t; 1587 1588 typedef struct { 1589 mlxcx_cmd_out_t mlxo_query_eq_head; 1590 uint8_t mlxo_query_eq_rsvd[8]; 1591 mlxcx_eventq_ctx_t mlxo_query_eq_context; 1592 uint8_t mlxi_query_eq_rsvd2[8]; 1593 uint64be_t mlxi_query_eq_event_bitmask; 1594 uint8_t mlxi_query_eq_rsvd3[176]; 1595 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1596 } mlxcx_cmd_query_eq_out_t; 1597 1598 typedef struct { 1599 mlxcx_cmd_in_t mlxi_destroy_eq_head; 1600 uint8_t mlxi_destroy_eq_rsvd[3]; 1601 uint8_t mlxi_destroy_eq_eqn; 1602 uint8_t mlxi_destroy_eq_rsvd2[4]; 1603 } mlxcx_cmd_destroy_eq_in_t; 1604 1605 typedef struct { 1606 mlxcx_cmd_out_t mlxo_destroy_eq_head; 1607 uint8_t mlxo_destroy_eq_rsvd[8]; 1608 } mlxcx_cmd_destroy_eq_out_t; 1609 1610 typedef struct { 1611 mlxcx_cmd_in_t mlxi_alloc_pd_head; 1612 uint8_t mlxi_alloc_pd_rsvd[8]; 1613 } mlxcx_cmd_alloc_pd_in_t; 1614 1615 typedef struct { 1616 mlxcx_cmd_out_t mlxo_alloc_pd_head; 1617 uint8_t mlxo_alloc_pd_rsvd; 1618 uint24be_t mlxo_alloc_pd_pdn; 1619 uint8_t mlxo_alloc_pd_rsvd2[4]; 1620 } mlxcx_cmd_alloc_pd_out_t; 1621 1622 typedef struct { 1623 mlxcx_cmd_in_t mlxi_dealloc_pd_head; 1624 uint8_t mlxi_dealloc_pd_rsvd; 1625 uint24be_t mlxi_dealloc_pd_pdn; 1626 uint8_t mlxi_dealloc_pd_rsvd2[4]; 1627 } mlxcx_cmd_dealloc_pd_in_t; 1628 1629 typedef struct { 1630 mlxcx_cmd_out_t mlxo_dealloc_pd_head; 1631 uint8_t mlxo_dealloc_pd_rsvd[8]; 1632 } mlxcx_cmd_dealloc_pd_out_t; 1633 1634 typedef struct { 1635 mlxcx_cmd_in_t mlxi_alloc_tdom_head; 1636 uint8_t mlxi_alloc_tdom_rsvd[8]; 1637 } mlxcx_cmd_alloc_tdom_in_t; 1638 1639 typedef struct { 1640 mlxcx_cmd_out_t mlxo_alloc_tdom_head; 1641 uint8_t mlxo_alloc_tdom_rsvd; 1642 uint24be_t mlxo_alloc_tdom_tdomn; 1643 uint8_t mlxo_alloc_tdom_rsvd2[4]; 1644 } mlxcx_cmd_alloc_tdom_out_t; 1645 1646 typedef struct { 1647 mlxcx_cmd_in_t mlxi_dealloc_tdom_head; 1648 uint8_t mlxi_dealloc_tdom_rsvd; 1649 uint24be_t mlxi_dealloc_tdom_tdomn; 1650 uint8_t mlxi_dealloc_tdom_rsvd2[4]; 1651 } mlxcx_cmd_dealloc_tdom_in_t; 1652 1653 typedef struct { 1654 mlxcx_cmd_out_t mlxo_dealloc_tdom_head; 1655 uint8_t mlxo_dealloc_tdom_rsvd[8]; 1656 } mlxcx_cmd_dealloc_tdom_out_t; 1657 1658 typedef struct { 1659 mlxcx_cmd_in_t mlxi_create_tir_head; 1660 uint8_t mlxi_create_tir_rsvd[24]; 1661 mlxcx_tir_ctx_t mlxi_create_tir_context; 1662 } mlxcx_cmd_create_tir_in_t; 1663 1664 typedef struct { 1665 mlxcx_cmd_out_t mlxo_create_tir_head; 1666 uint8_t mlxo_create_tir_rsvd; 1667 uint24be_t mlxo_create_tir_tirn; 1668 uint8_t mlxo_create_tir_rsvd2[4]; 1669 } mlxcx_cmd_create_tir_out_t; 1670 1671 typedef struct { 1672 mlxcx_cmd_in_t mlxi_destroy_tir_head; 1673 uint8_t mlxi_destroy_tir_rsvd; 1674 uint24be_t mlxi_destroy_tir_tirn; 1675 uint8_t mlxi_destroy_tir_rsvd2[4]; 1676 } mlxcx_cmd_destroy_tir_in_t; 1677 1678 typedef struct { 1679 mlxcx_cmd_out_t mlxo_destroy_tir_head; 1680 uint8_t mlxo_destroy_tir_rsvd[8]; 1681 } mlxcx_cmd_destroy_tir_out_t; 1682 1683 typedef struct { 1684 mlxcx_cmd_in_t mlxi_create_tis_head; 1685 uint8_t mlxi_create_tis_rsvd[24]; 1686 mlxcx_tis_ctx_t mlxi_create_tis_context; 1687 } mlxcx_cmd_create_tis_in_t; 1688 1689 typedef struct { 1690 mlxcx_cmd_out_t mlxo_create_tis_head; 1691 uint8_t mlxo_create_tis_rsvd; 1692 uint24be_t mlxo_create_tis_tisn; 1693 uint8_t mlxo_create_tis_rsvd2[4]; 1694 } mlxcx_cmd_create_tis_out_t; 1695 1696 typedef struct { 1697 mlxcx_cmd_in_t mlxi_destroy_tis_head; 1698 uint8_t mlxi_destroy_tis_rsvd; 1699 uint24be_t mlxi_destroy_tis_tisn; 1700 uint8_t mlxi_destroy_tis_rsvd2[4]; 1701 } mlxcx_cmd_destroy_tis_in_t; 1702 1703 typedef struct { 1704 mlxcx_cmd_out_t mlxo_destroy_tis_head; 1705 uint8_t mlxo_destroy_tis_rsvd[8]; 1706 } mlxcx_cmd_destroy_tis_out_t; 1707 1708 typedef struct { 1709 mlxcx_cmd_in_t mlxi_query_special_ctxs_head; 1710 uint8_t mlxi_query_special_ctxs_rsvd[8]; 1711 } mlxcx_cmd_query_special_ctxs_in_t; 1712 1713 typedef struct { 1714 mlxcx_cmd_out_t mlxo_query_special_ctxs_head; 1715 uint8_t mlxo_query_special_ctxs_rsvd[4]; 1716 uint32be_t mlxo_query_special_ctxs_resd_lkey; 1717 uint32be_t mlxo_query_special_ctxs_null_mkey; 1718 uint8_t mlxo_query_special_ctxs_rsvd2[12]; 1719 } mlxcx_cmd_query_special_ctxs_out_t; 1720 1721 typedef enum { 1722 MLXCX_VPORT_TYPE_VNIC = 0x0, 1723 MLXCX_VPORT_TYPE_ESWITCH = 0x1, 1724 MLXCX_VPORT_TYPE_UPLINK = 0x2, 1725 } mlxcx_cmd_vport_op_mod_t; 1726 1727 typedef struct { 1728 mlxcx_cmd_in_t mlxi_query_nic_vport_ctx_head; 1729 uint8_t mlxi_query_nic_vport_ctx_other_vport; 1730 uint8_t mlxi_query_nic_vport_ctx_rsvd[1]; 1731 uint16be_t mlxi_query_nic_vport_ctx_vport_number; 1732 uint8_t mlxi_query_nic_vport_ctx_allowed_list_type; 1733 uint8_t mlxi_query_nic_vport_ctx_rsvd2[3]; 1734 } mlxcx_cmd_query_nic_vport_ctx_in_t; 1735 1736 typedef struct { 1737 mlxcx_cmd_out_t mlxo_query_nic_vport_ctx_head; 1738 uint8_t mlxo_query_nic_vport_ctx_rsvd[8]; 1739 mlxcx_nic_vport_ctx_t mlxo_query_nic_vport_ctx_context; 1740 } mlxcx_cmd_query_nic_vport_ctx_out_t; 1741 1742 typedef enum { 1743 MLXCX_MODIFY_NIC_VPORT_CTX_ROCE_EN = 1 << 1, 1744 MLXCX_MODIFY_NIC_VPORT_CTX_ADDR_LIST = 1 << 2, 1745 MLXCX_MODIFY_NIC_VPORT_CTX_PERM_ADDR = 1 << 3, 1746 MLXCX_MODIFY_NIC_VPORT_CTX_PROMISC = 1 << 4, 1747 MLXCX_MODIFY_NIC_VPORT_CTX_EVENT = 1 << 5, 1748 MLXCX_MODIFY_NIC_VPORT_CTX_MTU = 1 << 6, 1749 MLXCX_MODIFY_NIC_VPORT_CTX_WQE_INLINE = 1 << 7, 1750 MLXCX_MODIFY_NIC_VPORT_CTX_PORT_GUID = 1 << 8, 1751 MLXCX_MODIFY_NIC_VPORT_CTX_NODE_GUID = 1 << 9, 1752 } mlxcx_modify_nic_vport_ctx_fields_t; 1753 1754 typedef struct { 1755 mlxcx_cmd_in_t mlxi_modify_nic_vport_ctx_head; 1756 uint8_t mlxi_modify_nic_vport_ctx_other_vport; 1757 uint8_t mlxi_modify_nic_vport_ctx_rsvd[1]; 1758 uint16be_t mlxi_modify_nic_vport_ctx_vport_number; 1759 uint32be_t mlxi_modify_nic_vport_ctx_field_select; 1760 uint8_t mlxi_modify_nic_vport_ctx_rsvd2[240]; 1761 mlxcx_nic_vport_ctx_t mlxi_modify_nic_vport_ctx_context; 1762 } mlxcx_cmd_modify_nic_vport_ctx_in_t; 1763 1764 typedef struct { 1765 mlxcx_cmd_out_t mlxo_modify_nic_vport_ctx_head; 1766 uint8_t mlxo_modify_nic_vport_ctx_rsvd[8]; 1767 } mlxcx_cmd_modify_nic_vport_ctx_out_t; 1768 1769 typedef struct { 1770 mlxcx_cmd_in_t mlxi_query_vport_state_head; 1771 uint8_t mlxi_query_vport_state_other_vport; 1772 uint8_t mlxi_query_vport_state_rsvd[1]; 1773 uint16be_t mlxi_query_vport_state_vport_number; 1774 uint8_t mlxi_query_vport_state_rsvd2[4]; 1775 } mlxcx_cmd_query_vport_state_in_t; 1776 1777 /* CSTYLED */ 1778 #define MLXCX_VPORT_ADMIN_STATE (bitdef_t){4, 0xF0} 1779 /* CSTYLED */ 1780 #define MLXCX_VPORT_OPER_STATE (bitdef_t){0, 0x0F} 1781 1782 typedef enum { 1783 MLXCX_VPORT_OPER_STATE_DOWN = 0x0, 1784 MLXCX_VPORT_OPER_STATE_UP = 0x1, 1785 } mlxcx_vport_oper_state_t; 1786 1787 typedef enum { 1788 MLXCX_VPORT_ADMIN_STATE_DOWN = 0x0, 1789 MLXCX_VPORT_ADMIN_STATE_UP = 0x1, 1790 MLXCX_VPORT_ADMIN_STATE_FOLLOW = 0x2, 1791 } mlxcx_vport_admin_state_t; 1792 1793 typedef struct { 1794 mlxcx_cmd_out_t mlxo_query_vport_state_head; 1795 uint8_t mlxo_query_vport_state_rsvd[4]; 1796 uint16be_t mlxo_query_vport_state_max_tx_speed; 1797 uint8_t mlxo_query_vport_state_rsvd2[1]; 1798 uint8_t mlxo_query_vport_state_state; 1799 } mlxcx_cmd_query_vport_state_out_t; 1800 1801 typedef struct { 1802 mlxcx_cmd_in_t mlxi_create_cq_head; 1803 uint8_t mlxi_create_cq_rsvd[8]; 1804 mlxcx_completionq_ctx_t mlxi_create_cq_context; 1805 uint8_t mlxi_create_cq_rsvd2[192]; 1806 uint64be_t mlxi_create_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1807 } mlxcx_cmd_create_cq_in_t; 1808 1809 typedef struct { 1810 mlxcx_cmd_out_t mlxo_create_cq_head; 1811 uint8_t mlxo_create_cq_rsvd; 1812 uint24be_t mlxo_create_cq_cqn; 1813 uint8_t mlxo_create_cq_rsvd2[4]; 1814 } mlxcx_cmd_create_cq_out_t; 1815 1816 typedef struct { 1817 mlxcx_cmd_in_t mlxi_destroy_cq_head; 1818 uint8_t mlxi_destroy_cq_rsvd; 1819 uint24be_t mlxi_destroy_cq_cqn; 1820 uint8_t mlxi_destroy_cq_rsvd2[4]; 1821 } mlxcx_cmd_destroy_cq_in_t; 1822 1823 typedef struct { 1824 mlxcx_cmd_out_t mlxo_destroy_cq_head; 1825 uint8_t mlxo_destroy_cq_rsvd[8]; 1826 } mlxcx_cmd_destroy_cq_out_t; 1827 1828 typedef struct { 1829 mlxcx_cmd_in_t mlxi_query_cq_head; 1830 uint8_t mlxi_query_cq_rsvd; 1831 uint24be_t mlxi_query_cq_cqn; 1832 uint8_t mlxi_query_cq_rsvd2[4]; 1833 } mlxcx_cmd_query_cq_in_t; 1834 1835 typedef struct { 1836 mlxcx_cmd_out_t mlxo_query_cq_head; 1837 uint8_t mlxo_query_cq_rsvd[8]; 1838 mlxcx_completionq_ctx_t mlxo_query_cq_context; 1839 uint8_t mlxo_query_cq_rsvd2[192]; 1840 uint64be_t mlxo_query_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1841 } mlxcx_cmd_query_cq_out_t; 1842 1843 typedef struct { 1844 mlxcx_cmd_in_t mlxi_create_rq_head; 1845 uint8_t mlxi_create_rq_rsvd[24]; 1846 mlxcx_rq_ctx_t mlxi_create_rq_context; 1847 } mlxcx_cmd_create_rq_in_t; 1848 1849 typedef struct { 1850 mlxcx_cmd_out_t mlxo_create_rq_head; 1851 uint8_t mlxo_create_rq_rsvd; 1852 uint24be_t mlxo_create_rq_rqn; 1853 uint8_t mlxo_create_rq_rsvd2[4]; 1854 } mlxcx_cmd_create_rq_out_t; 1855 1856 /* CSTYLED */ 1857 #define MLXCX_CMD_MODIFY_RQ_STATE (bitdef_t){ \ 1858 .bit_shift = 4, .bit_mask = 0xF0 } 1859 1860 typedef enum { 1861 MLXCX_MODIFY_RQ_SCATTER_FCS = 1 << 2, 1862 MLXCX_MODIFY_RQ_VSD = 1 << 1, 1863 MLXCX_MODIFY_RQ_COUNTER_SET_ID = 1 << 3, 1864 MLXCX_MODIFY_RQ_LWM = 1 << 0 1865 } mlxcx_cmd_modify_rq_bitmask_t; 1866 1867 typedef enum { 1868 MLXCX_RQ_STATE_RST = 0x0, 1869 MLXCX_RQ_STATE_RDY = 0x1, 1870 MLXCX_RQ_STATE_ERR = 0x3 1871 } mlxcx_rq_state_t; 1872 1873 typedef struct { 1874 mlxcx_cmd_in_t mlxi_modify_rq_head; 1875 bits8_t mlxi_modify_rq_state; 1876 uint24be_t mlxi_modify_rq_rqn; 1877 uint8_t mlxi_modify_rq_rsvd[4]; 1878 uint64be_t mlxi_modify_rq_bitmask; 1879 uint8_t mlxi_modify_rq_rsvd2[8]; 1880 mlxcx_rq_ctx_t mlxi_modify_rq_context; 1881 } mlxcx_cmd_modify_rq_in_t; 1882 1883 typedef struct { 1884 mlxcx_cmd_out_t mlxo_modify_rq_head; 1885 uint8_t mlxo_modify_rq_rsvd[8]; 1886 } mlxcx_cmd_modify_rq_out_t; 1887 1888 typedef struct { 1889 mlxcx_cmd_in_t mlxi_query_rq_head; 1890 uint8_t mlxi_query_rq_rsvd; 1891 uint24be_t mlxi_query_rq_rqn; 1892 uint8_t mlxi_query_rq_rsvd2[4]; 1893 } mlxcx_cmd_query_rq_in_t; 1894 1895 typedef struct { 1896 mlxcx_cmd_out_t mlxo_query_rq_head; 1897 uint8_t mlxo_query_rq_rsvd[24]; 1898 mlxcx_rq_ctx_t mlxo_query_rq_context; 1899 } mlxcx_cmd_query_rq_out_t; 1900 1901 typedef struct { 1902 mlxcx_cmd_in_t mlxi_destroy_rq_head; 1903 uint8_t mlxi_destroy_rq_rsvd; 1904 uint24be_t mlxi_destroy_rq_rqn; 1905 uint8_t mlxi_destroy_rq_rsvd2[4]; 1906 } mlxcx_cmd_destroy_rq_in_t; 1907 1908 typedef struct { 1909 mlxcx_cmd_out_t mlxo_destroy_rq_head; 1910 uint8_t mlxo_destroy_rq_rsvd[8]; 1911 } mlxcx_cmd_destroy_rq_out_t; 1912 1913 typedef struct { 1914 mlxcx_cmd_in_t mlxi_create_sq_head; 1915 uint8_t mlxi_create_sq_rsvd[24]; 1916 mlxcx_sq_ctx_t mlxi_create_sq_context; 1917 } mlxcx_cmd_create_sq_in_t; 1918 1919 typedef struct { 1920 mlxcx_cmd_out_t mlxo_create_sq_head; 1921 uint8_t mlxo_create_sq_rsvd; 1922 uint24be_t mlxo_create_sq_sqn; 1923 uint8_t mlxo_create_sq_rsvd2[4]; 1924 } mlxcx_cmd_create_sq_out_t; 1925 1926 /* CSTYLED */ 1927 #define MLXCX_CMD_MODIFY_SQ_STATE (bitdef_t){ \ 1928 .bit_shift = 4, .bit_mask = 0xF0 } 1929 1930 typedef enum { 1931 MLXCX_MODIFY_SQ_PACKET_PACING_INDEX = 1 << 0, 1932 } mlxcx_cmd_modify_sq_bitmask_t; 1933 1934 typedef enum { 1935 MLXCX_SQ_STATE_RST = 0x0, 1936 MLXCX_SQ_STATE_RDY = 0x1, 1937 MLXCX_SQ_STATE_ERR = 0x3 1938 } mlxcx_sq_state_t; 1939 1940 typedef struct { 1941 mlxcx_cmd_in_t mlxi_modify_sq_head; 1942 bits8_t mlxi_modify_sq_state; 1943 uint24be_t mlxi_modify_sq_sqn; 1944 uint8_t mlxi_modify_sq_rsvd[4]; 1945 uint64be_t mlxi_modify_sq_bitmask; 1946 uint8_t mlxi_modify_sq_rsvd2[8]; 1947 mlxcx_sq_ctx_t mlxi_modify_sq_context; 1948 } mlxcx_cmd_modify_sq_in_t; 1949 1950 typedef struct { 1951 mlxcx_cmd_out_t mlxo_modify_sq_head; 1952 uint8_t mlxo_modify_sq_rsvd[8]; 1953 } mlxcx_cmd_modify_sq_out_t; 1954 1955 typedef struct { 1956 mlxcx_cmd_in_t mlxi_query_sq_head; 1957 uint8_t mlxi_query_sq_rsvd; 1958 uint24be_t mlxi_query_sq_sqn; 1959 uint8_t mlxi_query_sq_rsvd2[4]; 1960 } mlxcx_cmd_query_sq_in_t; 1961 1962 typedef struct { 1963 mlxcx_cmd_out_t mlxo_query_sq_head; 1964 uint8_t mlxo_query_sq_rsvd[24]; 1965 mlxcx_sq_ctx_t mlxo_query_sq_context; 1966 } mlxcx_cmd_query_sq_out_t; 1967 1968 typedef struct { 1969 mlxcx_cmd_in_t mlxi_destroy_sq_head; 1970 uint8_t mlxi_destroy_sq_rsvd; 1971 uint24be_t mlxi_destroy_sq_sqn; 1972 uint8_t mlxi_destroy_sq_rsvd2[4]; 1973 } mlxcx_cmd_destroy_sq_in_t; 1974 1975 typedef struct { 1976 mlxcx_cmd_out_t mlxo_destroy_sq_head; 1977 uint8_t mlxo_destroy_sq_rsvd[8]; 1978 } mlxcx_cmd_destroy_sq_out_t; 1979 1980 typedef struct { 1981 mlxcx_cmd_in_t mlxi_create_rqt_head; 1982 uint8_t mlxi_create_rqt_rsvd[24]; 1983 mlxcx_rqtable_ctx_t mlxi_create_rqt_context; 1984 } mlxcx_cmd_create_rqt_in_t; 1985 1986 typedef struct { 1987 mlxcx_cmd_out_t mlxo_create_rqt_head; 1988 uint8_t mlxo_create_rqt_rsvd; 1989 uint24be_t mlxo_create_rqt_rqtn; 1990 uint8_t mlxo_create_rqt_rsvd2[4]; 1991 } mlxcx_cmd_create_rqt_out_t; 1992 1993 typedef struct { 1994 mlxcx_cmd_in_t mlxi_destroy_rqt_head; 1995 uint8_t mlxi_destroy_rqt_rsvd; 1996 uint24be_t mlxi_destroy_rqt_rqtn; 1997 uint8_t mlxi_destroy_rqt_rsvd2[4]; 1998 } mlxcx_cmd_destroy_rqt_in_t; 1999 2000 typedef struct { 2001 mlxcx_cmd_out_t mlxo_destroy_rqt_head; 2002 uint8_t mlxo_destroy_rqt_rsvd[8]; 2003 } mlxcx_cmd_destroy_rqt_out_t; 2004 2005 typedef enum { 2006 MLXCX_FLOW_TABLE_NIC_RX = 0x0, 2007 MLXCX_FLOW_TABLE_NIC_TX = 0x1, 2008 MLXCX_FLOW_TABLE_ESW_OUT = 0x2, 2009 MLXCX_FLOW_TABLE_ESW_IN = 0x3, 2010 MLXCX_FLOW_TABLE_ESW_FDB = 0x4, 2011 MLXCX_FLOW_TABLE_NIC_RX_SNIFF = 0x5, 2012 MLXCX_FLOW_TABLE_NIC_TX_SNIFF = 0x6, 2013 MLXCX_FLOW_TABLE_NIC_RX_RDMA = 0x7, 2014 MLXCX_FLOW_TABLE_NIC_TX_RDMA = 0x8 2015 } mlxcx_flow_table_type_t; 2016 2017 typedef struct { 2018 mlxcx_cmd_in_t mlxi_create_flow_table_head; 2019 uint8_t mlxi_create_flow_table_other_vport; 2020 uint8_t mlxi_create_flow_table_rsvd; 2021 uint16be_t mlxi_create_flow_table_vport_number; 2022 uint8_t mlxi_create_flow_table_rsvd2[4]; 2023 uint8_t mlxi_create_flow_table_table_type; 2024 uint8_t mlxi_create_flow_table_rsvd3[7]; 2025 mlxcx_flow_table_ctx_t mlxi_create_flow_table_context; 2026 } mlxcx_cmd_create_flow_table_in_t; 2027 2028 typedef struct { 2029 mlxcx_cmd_out_t mlxo_create_flow_table_head; 2030 uint8_t mlxo_create_flow_table_rsvd; 2031 uint24be_t mlxo_create_flow_table_table_id; 2032 uint8_t mlxo_create_flow_table_rsvd2[4]; 2033 } mlxcx_cmd_create_flow_table_out_t; 2034 2035 typedef struct { 2036 mlxcx_cmd_in_t mlxi_destroy_flow_table_head; 2037 uint8_t mlxi_destroy_flow_table_other_vport; 2038 uint8_t mlxi_destroy_flow_table_rsvd; 2039 uint16be_t mlxi_destroy_flow_table_vport_number; 2040 uint8_t mlxi_destroy_flow_table_rsvd2[4]; 2041 uint8_t mlxi_destroy_flow_table_table_type; 2042 uint8_t mlxi_destroy_flow_table_rsvd3[4]; 2043 uint24be_t mlxi_destroy_flow_table_table_id; 2044 uint8_t mlxi_destroy_flow_table_rsvd4[4]; 2045 } mlxcx_cmd_destroy_flow_table_in_t; 2046 2047 typedef struct { 2048 mlxcx_cmd_out_t mlxo_destroy_flow_table_head; 2049 uint8_t mlxo_destroy_flow_table_rsvd[8]; 2050 } mlxcx_cmd_destroy_flow_table_out_t; 2051 2052 typedef struct { 2053 mlxcx_cmd_in_t mlxi_set_flow_table_root_head; 2054 uint8_t mlxi_set_flow_table_root_other_vport; 2055 uint8_t mlxi_set_flow_table_root_rsvd; 2056 uint16be_t mlxi_set_flow_table_root_vport_number; 2057 uint8_t mlxi_set_flow_table_root_rsvd2[4]; 2058 uint8_t mlxi_set_flow_table_root_table_type; 2059 uint8_t mlxi_set_flow_table_root_rsvd3[4]; 2060 uint24be_t mlxi_set_flow_table_root_table_id; 2061 uint8_t mlxi_set_flow_table_root_rsvd4[4]; 2062 } mlxcx_cmd_set_flow_table_root_in_t; 2063 2064 typedef struct { 2065 mlxcx_cmd_out_t mlxo_set_flow_table_root_head; 2066 uint8_t mlxo_set_flow_table_root_rsvd[8]; 2067 } mlxcx_cmd_set_flow_table_root_out_t; 2068 2069 typedef enum { 2070 MLXCX_FLOW_GROUP_MATCH_OUTER_HDRS = 1 << 0, 2071 MLXCX_FLOW_GROUP_MATCH_MISC_PARAMS = 1 << 1, 2072 MLXCX_FLOW_GROUP_MATCH_INNER_HDRS = 1 << 2, 2073 } mlxcx_flow_group_match_criteria_t; 2074 2075 typedef struct { 2076 mlxcx_cmd_in_t mlxi_create_flow_group_head; 2077 uint8_t mlxi_create_flow_group_other_vport; 2078 uint8_t mlxi_create_flow_group_rsvd; 2079 uint16be_t mlxi_create_flow_group_vport_number; 2080 uint8_t mlxi_create_flow_group_rsvd2[4]; 2081 uint8_t mlxi_create_flow_group_table_type; 2082 uint8_t mlxi_create_flow_group_rsvd3[4]; 2083 uint24be_t mlxi_create_flow_group_table_id; 2084 uint8_t mlxi_create_flow_group_rsvd4[4]; 2085 uint32be_t mlxi_create_flow_group_start_flow_index; 2086 uint8_t mlxi_create_flow_group_rsvd5[4]; 2087 uint32be_t mlxi_create_flow_group_end_flow_index; 2088 uint8_t mlxi_create_flow_group_rsvd6[23]; 2089 uint8_t mlxi_create_flow_group_match_criteria_en; 2090 mlxcx_flow_match_t mlxi_create_flow_group_match_criteria; 2091 uint8_t mlxi_create_flow_group_rsvd7[448]; 2092 } mlxcx_cmd_create_flow_group_in_t; 2093 2094 typedef struct { 2095 mlxcx_cmd_out_t mlxo_create_flow_group_head; 2096 uint8_t mlxo_create_flow_group_rsvd; 2097 uint24be_t mlxo_create_flow_group_group_id; 2098 uint8_t mlxo_create_flow_group_rsvd2[4]; 2099 } mlxcx_cmd_create_flow_group_out_t; 2100 2101 typedef struct { 2102 mlxcx_cmd_in_t mlxi_destroy_flow_group_head; 2103 uint8_t mlxi_destroy_flow_group_other_vport; 2104 uint8_t mlxi_destroy_flow_group_rsvd; 2105 uint16be_t mlxi_destroy_flow_group_vport_number; 2106 uint8_t mlxi_destroy_flow_group_rsvd2[4]; 2107 uint8_t mlxi_destroy_flow_group_table_type; 2108 uint8_t mlxi_destroy_flow_group_rsvd3[4]; 2109 uint24be_t mlxi_destroy_flow_group_table_id; 2110 uint32be_t mlxi_destroy_flow_group_group_id; 2111 uint8_t mlxi_destroy_flow_group_rsvd4[36]; 2112 } mlxcx_cmd_destroy_flow_group_in_t; 2113 2114 typedef struct { 2115 mlxcx_cmd_out_t mlxo_destroy_flow_group_head; 2116 uint8_t mlxo_destroy_flow_group_rsvd[8]; 2117 } mlxcx_cmd_destroy_flow_group_out_t; 2118 2119 typedef enum { 2120 MLXCX_CMD_FLOW_ENTRY_SET_NEW = 0, 2121 MLXCX_CMD_FLOW_ENTRY_MODIFY = 1, 2122 } mlxcx_cmd_set_flow_table_entry_opmod_t; 2123 2124 typedef enum { 2125 MLXCX_CMD_FLOW_ENTRY_SET_ACTION = 1 << 0, 2126 MLXCX_CMD_FLOW_ENTRY_SET_FLOW_TAG = 1 << 1, 2127 MLXCX_CMD_FLOW_ENTRY_SET_DESTINATION = 1 << 2, 2128 MLXCX_CMD_FLOW_ENTRY_SET_COUNTERS = 1 << 3, 2129 MLXCX_CMD_FLOW_ENTRY_SET_ENCAP = 1 << 4 2130 } mlxcx_cmd_set_flow_table_entry_bitmask_t; 2131 2132 typedef struct { 2133 mlxcx_cmd_in_t mlxi_set_flow_table_entry_head; 2134 uint8_t mlxi_set_flow_table_entry_other_vport; 2135 uint8_t mlxi_set_flow_table_entry_rsvd; 2136 uint16be_t mlxi_set_flow_table_entry_vport_number; 2137 uint8_t mlxi_set_flow_table_entry_rsvd2[4]; 2138 uint8_t mlxi_set_flow_table_entry_table_type; 2139 uint8_t mlxi_set_flow_table_entry_rsvd3[4]; 2140 uint24be_t mlxi_set_flow_table_entry_table_id; 2141 uint8_t mlxi_set_flow_table_entry_rsvd4[3]; 2142 bits8_t mlxi_set_flow_table_entry_modify_bitmask; 2143 uint8_t mlxi_set_flow_table_entry_rsvd5[4]; 2144 uint32be_t mlxi_set_flow_table_entry_flow_index; 2145 uint8_t mlxi_set_flow_table_entry_rsvd6[28]; 2146 mlxcx_flow_entry_ctx_t mlxi_set_flow_table_entry_context; 2147 } mlxcx_cmd_set_flow_table_entry_in_t; 2148 2149 typedef struct { 2150 mlxcx_cmd_out_t mlxo_set_flow_table_entry_head; 2151 uint8_t mlxo_set_flow_table_entry_rsvd[8]; 2152 } mlxcx_cmd_set_flow_table_entry_out_t; 2153 2154 typedef struct { 2155 mlxcx_cmd_in_t mlxi_delete_flow_table_entry_head; 2156 uint8_t mlxi_delete_flow_table_entry_other_vport; 2157 uint8_t mlxi_delete_flow_table_entry_rsvd; 2158 uint16be_t mlxi_delete_flow_table_entry_vport_number; 2159 uint8_t mlxi_delete_flow_table_entry_rsvd2[4]; 2160 uint8_t mlxi_delete_flow_table_entry_table_type; 2161 uint8_t mlxi_delete_flow_table_entry_rsvd3[4]; 2162 uint24be_t mlxi_delete_flow_table_entry_table_id; 2163 uint8_t mlxi_delete_flow_table_entry_rsvd4[8]; 2164 uint32be_t mlxi_delete_flow_table_entry_flow_index; 2165 uint8_t mlxi_delete_flow_table_entry_rsvd5[28]; 2166 } mlxcx_cmd_delete_flow_table_entry_in_t; 2167 2168 typedef struct { 2169 mlxcx_cmd_out_t mlxo_delete_flow_table_entry_head; 2170 uint8_t mlxo_delete_flow_table_entry_rsvd[8]; 2171 } mlxcx_cmd_delete_flow_table_entry_out_t; 2172 2173 typedef enum { 2174 MLXCX_CMD_CONFIG_INT_MOD_READ = 1, 2175 MLXCX_CMD_CONFIG_INT_MOD_WRITE = 0 2176 } mlxcx_cmd_config_int_mod_opmod_t; 2177 2178 typedef struct { 2179 mlxcx_cmd_in_t mlxi_config_int_mod_head; 2180 uint16be_t mlxi_config_int_mod_min_delay; 2181 uint16be_t mlxi_config_int_mod_int_vector; 2182 uint8_t mlxi_config_int_mod_rsvd[4]; 2183 } mlxcx_cmd_config_int_mod_in_t; 2184 2185 typedef struct { 2186 mlxcx_cmd_out_t mlxo_config_int_mod_head; 2187 uint16be_t mlxo_config_int_mod_min_delay; 2188 uint16be_t mlxo_config_int_mod_int_vector; 2189 uint8_t mlxo_config_int_mod_rsvd[4]; 2190 } mlxcx_cmd_config_int_mod_out_t; 2191 2192 typedef struct { 2193 uint8_t mlrd_pmtu_rsvd; 2194 uint8_t mlrd_pmtu_local_port; 2195 uint8_t mlrd_pmtu_rsvd2[2]; 2196 2197 uint16be_t mlrd_pmtu_max_mtu; 2198 uint8_t mlrd_pmtu_rsvd3[2]; 2199 2200 uint16be_t mlrd_pmtu_admin_mtu; 2201 uint8_t mlrd_pmtu_rsvd4[2]; 2202 2203 uint16be_t mlrd_pmtu_oper_mtu; 2204 uint8_t mlrd_pmtu_rsvd5[2]; 2205 } mlxcx_reg_pmtu_t; 2206 2207 typedef enum { 2208 MLXCX_PORT_STATUS_UP = 1, 2209 MLXCX_PORT_STATUS_DOWN = 2, 2210 MLXCX_PORT_STATUS_UP_ONCE = 3, 2211 MLXCX_PORT_STATUS_DISABLED = 4, 2212 } mlxcx_port_status_t; 2213 2214 typedef enum { 2215 MLXCX_PAOS_ADMIN_ST_EN = 1UL << 31, 2216 } mlxcx_paos_flags_t; 2217 2218 typedef struct { 2219 uint8_t mlrd_paos_swid; 2220 uint8_t mlrd_paos_local_port; 2221 uint8_t mlrd_paos_admin_status; 2222 uint8_t mlrd_paos_oper_status; 2223 bits32_t mlrd_paos_flags; 2224 uint8_t mlrd_paos_rsvd[8]; 2225 } mlxcx_reg_paos_t; 2226 2227 typedef enum { 2228 MLXCX_PROTO_SGMII = 1 << 0, 2229 MLXCX_PROTO_1000BASE_KX = 1 << 1, 2230 MLXCX_PROTO_10GBASE_CX4 = 1 << 2, 2231 MLXCX_PROTO_10GBASE_KX4 = 1 << 3, 2232 MLXCX_PROTO_10GBASE_KR = 1 << 4, 2233 MLXCX_PROTO_UNKNOWN_1 = 1 << 5, 2234 MLXCX_PROTO_40GBASE_CR4 = 1 << 6, 2235 MLXCX_PROTO_40GBASE_KR4 = 1 << 7, 2236 MLXCX_PROTO_UNKNOWN_2 = 1 << 8, 2237 MLXCX_PROTO_SGMII_100BASE = 1 << 9, 2238 MLXCX_PROTO_UNKNOWN_3 = 1 << 10, 2239 MLXCX_PROTO_UNKNOWN_4 = 1 << 11, 2240 MLXCX_PROTO_10GBASE_CR = 1 << 12, 2241 MLXCX_PROTO_10GBASE_SR = 1 << 13, 2242 MLXCX_PROTO_10GBASE_ER_LR = 1 << 14, 2243 MLXCX_PROTO_40GBASE_SR4 = 1 << 15, 2244 MLXCX_PROTO_40GBASE_LR4_ER4 = 1 << 16, 2245 MLXCX_PROTO_UNKNOWN_5 = 1 << 17, 2246 MLXCX_PROTO_50GBASE_SR2 = 1 << 18, 2247 MLXCX_PROTO_UNKNOWN_6 = 1 << 19, 2248 MLXCX_PROTO_100GBASE_CR4 = 1 << 20, 2249 MLXCX_PROTO_100GBASE_SR4 = 1 << 21, 2250 MLXCX_PROTO_100GBASE_KR4 = 1 << 22, 2251 MLXCX_PROTO_UNKNOWN_7 = 1 << 23, 2252 MLXCX_PROTO_UNKNOWN_8 = 1 << 24, 2253 MLXCX_PROTO_UNKNOWN_9 = 1 << 25, 2254 MLXCX_PROTO_UNKNOWN_10 = 1 << 26, 2255 MLXCX_PROTO_25GBASE_CR = 1 << 27, 2256 MLXCX_PROTO_25GBASE_KR = 1 << 28, 2257 MLXCX_PROTO_25GBASE_SR = 1 << 29, 2258 MLXCX_PROTO_50GBASE_CR2 = 1 << 30, 2259 MLXCX_PROTO_50GBASE_KR2 = 1UL << 31, 2260 } mlxcx_eth_proto_t; 2261 2262 typedef enum { 2263 MLXCX_AUTONEG_DISABLE_CAP = 1 << 5, 2264 MLXCX_AUTONEG_DISABLE = 1 << 6 2265 } mlxcx_autoneg_flags_t; 2266 2267 typedef enum { 2268 MLXCX_PTYS_PROTO_MASK_IB = 1 << 0, 2269 MLXCX_PTYS_PROTO_MASK_ETH = 1 << 2, 2270 } mlxcx_reg_ptys_proto_mask_t; 2271 2272 typedef struct { 2273 bits8_t mlrd_ptys_autoneg_flags; 2274 uint8_t mlrd_ptys_local_port; 2275 uint8_t mlrd_ptys_rsvd; 2276 bits8_t mlrd_ptys_proto_mask; 2277 2278 bits8_t mlrd_ptys_autoneg_status; 2279 uint8_t mlrd_ptys_rsvd2; 2280 uint16be_t mlrd_ptys_data_rate_oper; 2281 2282 uint8_t mlrd_ptys_rsvd3[4]; 2283 2284 bits32_t mlrd_ptys_proto_cap; 2285 uint8_t mlrd_ptys_rsvd4[8]; 2286 bits32_t mlrd_ptys_proto_admin; 2287 uint8_t mlrd_ptys_rsvd5[8]; 2288 bits32_t mlrd_ptys_proto_oper; 2289 uint8_t mlrd_ptys_rsvd6[8]; 2290 bits32_t mlrd_ptys_proto_partner_advert; 2291 uint8_t mlrd_ptys_rsvd7[12]; 2292 } mlxcx_reg_ptys_t; 2293 2294 typedef enum { 2295 MLXCX_LED_TYPE_BOTH = 0x0, 2296 MLXCX_LED_TYPE_UID = 0x1, 2297 MLXCX_LED_TYPE_PORT = 0x2, 2298 } mlxcx_led_type_t; 2299 2300 #define MLXCX_MLCR_INDIVIDUAL_ONLY (1 << 4) 2301 /* CSTYLED */ 2302 #define MLXCX_MLCR_LED_TYPE (bitdef_t){ 0, 0x0F } 2303 2304 typedef struct { 2305 uint8_t mlrd_mlcr_rsvd; 2306 uint8_t mlrd_mlcr_local_port; 2307 uint8_t mlrd_mlcr_rsvd2; 2308 bits8_t mlrd_mlcr_flags; 2309 uint8_t mlrd_mlcr_rsvd3[2]; 2310 uint16be_t mlrd_mlcr_beacon_duration; 2311 uint8_t mlrd_mlcr_rsvd4[2]; 2312 uint16be_t mlrd_mlcr_beacon_remain; 2313 } mlxcx_reg_mlcr_t; 2314 2315 typedef struct { 2316 uint8_t mlrd_pmaos_rsvd; 2317 uint8_t mlrd_pmaos_module; 2318 uint8_t mlrd_pmaos_admin_status; 2319 uint8_t mlrd_pmaos_oper_status; 2320 bits8_t mlrd_pmaos_flags; 2321 uint8_t mlrd_pmaos_rsvd2; 2322 uint8_t mlrd_pmaos_error_type; 2323 uint8_t mlrd_pmaos_event_en; 2324 uint8_t mlrd_pmaos_rsvd3[8]; 2325 } mlxcx_reg_pmaos_t; 2326 2327 typedef enum { 2328 MLXCX_MCIA_STATUS_OK = 0x0, 2329 MLXCX_MCIA_STATUS_NO_EEPROM = 0x1, 2330 MLXCX_MCIA_STATUS_NOT_SUPPORTED = 0x2, 2331 MLXCX_MCIA_STATUS_NOT_CONNECTED = 0x3, 2332 MLXCX_MCIA_STATUS_I2C_ERROR = 0x9, 2333 MLXCX_MCIA_STATUS_DISABLED = 0x10 2334 } mlxcx_mcia_status_t; 2335 2336 typedef struct { 2337 bits8_t mlrd_mcia_flags; 2338 uint8_t mlrd_mcia_module; 2339 uint8_t mlrd_mcia_rsvd; 2340 uint8_t mlrd_mcia_status; 2341 uint8_t mlrd_mcia_i2c_device_addr; 2342 uint8_t mlrd_mcia_page_number; 2343 uint16be_t mlrd_mcia_device_addr; 2344 uint8_t mlrd_mcia_rsvd2[2]; 2345 uint16be_t mlrd_mcia_size; 2346 uint8_t mlrd_mcia_rsvd3[4]; 2347 uint8_t mlrd_mcia_data[48]; 2348 } mlxcx_reg_mcia_t; 2349 2350 typedef struct { 2351 uint64be_t mlppc_ieee_802_3_frames_tx; 2352 uint64be_t mlppc_ieee_802_3_frames_rx; 2353 uint64be_t mlppc_ieee_802_3_fcs_err; 2354 uint64be_t mlppc_ieee_802_3_align_err; 2355 uint64be_t mlppc_ieee_802_3_bytes_tx; 2356 uint64be_t mlppc_ieee_802_3_bytes_rx; 2357 uint64be_t mlppc_ieee_802_3_mcast_tx; 2358 uint64be_t mlppc_ieee_802_3_bcast_tx; 2359 uint64be_t mlppc_ieee_802_3_mcast_rx; 2360 uint64be_t mlppc_ieee_802_3_bcast_rx; 2361 uint64be_t mlppc_ieee_802_3_in_range_len_err; 2362 uint64be_t mlppc_ieee_802_3_out_of_range_len_err; 2363 uint64be_t mlppc_ieee_802_3_frame_too_long_err; 2364 uint64be_t mlppc_ieee_802_3_symbol_err; 2365 uint64be_t mlppc_ieee_802_3_mac_ctrl_tx; 2366 uint64be_t mlppc_ieee_802_3_mac_ctrl_rx; 2367 uint64be_t mlppc_ieee_802_3_unsup_opcodes_rx; 2368 uint64be_t mlppc_ieee_802_3_pause_rx; 2369 uint64be_t mlppc_ieee_802_3_pause_tx; 2370 } mlxcx_ppcnt_ieee_802_3_t; 2371 2372 typedef struct { 2373 uint64be_t mlppc_rfc_2863_in_octets; 2374 uint64be_t mlppc_rfc_2863_in_ucast_pkts; 2375 uint64be_t mlppc_rfc_2863_in_discards; 2376 uint64be_t mlppc_rfc_2863_in_errors; 2377 uint64be_t mlppc_rfc_2863_in_unknown_protos; 2378 uint64be_t mlppc_rfc_2863_out_octets; 2379 uint64be_t mlppc_rfc_2863_out_ucast_pkts; 2380 uint64be_t mlppc_rfc_2863_out_discards; 2381 uint64be_t mlppc_rfc_2863_out_errors; 2382 uint64be_t mlppc_rfc_2863_in_mcast_pkts; 2383 uint64be_t mlppc_rfc_2863_in_bcast_pkts; 2384 uint64be_t mlppc_rfc_2863_out_mcast_pkts; 2385 uint64be_t mlppc_rfc_2863_out_bcast_pkts; 2386 } mlxcx_ppcnt_rfc_2863_t; 2387 2388 typedef struct { 2389 uint64be_t mlppc_phy_stats_time_since_last_clear; 2390 uint64be_t mlppc_phy_stats_rx_bits; 2391 uint64be_t mlppc_phy_stats_symbol_errs; 2392 uint64be_t mlppc_phy_stats_corrected_bits; 2393 uint8_t mlppc_phy_stats_rsvd[2]; 2394 uint8_t mlppc_phy_stats_raw_ber_mag; 2395 uint8_t mlppc_phy_stats_raw_ber_coef; 2396 uint8_t mlppc_phy_stats_rsvd2[2]; 2397 uint8_t mlppc_phy_stats_eff_ber_mag; 2398 uint8_t mlppc_phy_stats_eff_ber_coef; 2399 } mlxcx_ppcnt_phy_stats_t; 2400 2401 typedef enum { 2402 MLXCX_PPCNT_GRP_IEEE_802_3 = 0x0, 2403 MLXCX_PPCNT_GRP_RFC_2863 = 0x1, 2404 MLXCX_PPCNT_GRP_RFC_2819 = 0x2, 2405 MLXCX_PPCNT_GRP_RFC_3635 = 0x3, 2406 MLXCX_PPCNT_GRP_ETH_EXTD = 0x5, 2407 MLXCX_PPCNT_GRP_ETH_DISCARD = 0x6, 2408 MLXCX_PPCNT_GRP_PER_PRIO = 0x10, 2409 MLXCX_PPCNT_GRP_PER_TC = 0x11, 2410 MLXCX_PPCNT_GRP_PER_TC_CONGEST = 0x13, 2411 MLXCX_PPCNT_GRP_PHY_STATS = 0x16 2412 } mlxcx_ppcnt_grp_t; 2413 2414 typedef enum { 2415 MLXCX_PPCNT_CLEAR = (1 << 7), 2416 MLXCX_PPCNT_NO_CLEAR = 0 2417 } mlxcx_ppcnt_clear_t; 2418 2419 typedef struct { 2420 uint8_t mlrd_ppcnt_swid; 2421 uint8_t mlrd_ppcnt_local_port; 2422 uint8_t mlrd_ppcnt_pnat; 2423 uint8_t mlrd_ppcnt_grp; 2424 uint8_t mlrd_ppcnt_clear; 2425 uint8_t mlrd_ppcnt_rsvd[2]; 2426 uint8_t mlrd_ppcnt_prio_tc; 2427 union { 2428 uint8_t mlrd_ppcnt_data[248]; 2429 mlxcx_ppcnt_ieee_802_3_t mlrd_ppcnt_ieee_802_3; 2430 mlxcx_ppcnt_rfc_2863_t mlrd_ppcnt_rfc_2863; 2431 mlxcx_ppcnt_phy_stats_t mlrd_ppcnt_phy_stats; 2432 }; 2433 } mlxcx_reg_ppcnt_t; 2434 2435 typedef enum { 2436 MLXCX_REG_PMTU = 0x5003, 2437 MLXCX_REG_PTYS = 0x5004, 2438 MLXCX_REG_PAOS = 0x5006, 2439 MLXCX_REG_PMAOS = 0x5012, 2440 MLXCX_REG_MSGI = 0x9021, 2441 MLXCX_REG_MLCR = 0x902B, 2442 MLXCX_REG_MCIA = 0x9014, 2443 MLXCX_REG_PPCNT = 0x5008, 2444 } mlxcx_register_id_t; 2445 2446 typedef union { 2447 mlxcx_reg_pmtu_t mlrd_pmtu; 2448 mlxcx_reg_paos_t mlrd_paos; 2449 mlxcx_reg_ptys_t mlrd_ptys; 2450 mlxcx_reg_mlcr_t mlrd_mlcr; 2451 mlxcx_reg_pmaos_t mlrd_pmaos; 2452 mlxcx_reg_mcia_t mlrd_mcia; 2453 mlxcx_reg_ppcnt_t mlrd_ppcnt; 2454 } mlxcx_register_data_t; 2455 2456 typedef enum { 2457 MLXCX_CMD_ACCESS_REGISTER_READ = 1, 2458 MLXCX_CMD_ACCESS_REGISTER_WRITE = 0 2459 } mlxcx_cmd_reg_opmod_t; 2460 2461 typedef struct { 2462 mlxcx_cmd_in_t mlxi_access_register_head; 2463 uint8_t mlxi_access_register_rsvd[2]; 2464 uint16be_t mlxi_access_register_register_id; 2465 uint32be_t mlxi_access_register_argument; 2466 mlxcx_register_data_t mlxi_access_register_data; 2467 } mlxcx_cmd_access_register_in_t; 2468 2469 typedef struct { 2470 mlxcx_cmd_out_t mlxo_access_register_head; 2471 uint8_t mlxo_access_register_rsvd[8]; 2472 mlxcx_register_data_t mlxo_access_register_data; 2473 } mlxcx_cmd_access_register_out_t; 2474 2475 #pragma pack() 2476 2477 #ifdef __cplusplus 2478 } 2479 #endif 2480 2481 #endif /* _MLXCX_REG_H */ 2482