1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2020, The University of Queensland 14 * Copyright (c) 2018, Joyent, Inc. 15 * Copyright 2020 RackTop Systems, Inc. 16 */ 17 18 #ifndef _MLXCX_REG_H 19 #define _MLXCX_REG_H 20 21 #include <sys/types.h> 22 #include <sys/byteorder.h> 23 24 #include <mlxcx_endint.h> 25 26 #if !defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) 27 #error "Need _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH" 28 #endif 29 30 /* 31 * Register offsets. 32 */ 33 34 #define MLXCX_ISS_FIRMWARE 0x0000 35 #define MLXCX_ISS_FW_MAJOR(x) (((x) & 0xffff)) 36 #define MLXCX_ISS_FW_MINOR(x) (((x) >> 16) & 0xffff) 37 #define MLXCX_ISS_FW_CMD 0x0004 38 #define MLXCX_ISS_FW_REV(x) (((x) & 0xffff)) 39 #define MLXCX_ISS_CMD_REV(x) (((x) >> 16) & 0xffff) 40 #define MLXCX_ISS_CMD_HIGH 0x0010 41 #define MLXCX_ISS_CMD_LOW 0x0014 42 #define MLXCX_ISS_CMDQ_SIZE(x) (((x) >> 4) & 0xf) 43 #define MLXCX_ISS_CMDQ_STRIDE(x) ((x) & 0xf) 44 45 #define MLXCX_ISS_CMD_DOORBELL 0x0018 46 #define MLXCX_ISS_INIT 0x01fc 47 #define MLXCX_ISS_INITIALIZING(x) (((x) >> 31) & 0x1) 48 #define MLXCX_ISS_HEALTH_BUF 0x0200 49 #define MLXCX_ISS_NO_DRAM_NIC 0x0240 50 #define MLXCX_ISS_TIMER 0x1000 51 #define MLXCX_ISS_HEALTH_COUNT 0x1010 52 #define MLXCX_ISS_HEALTH_SYND 0x1013 53 54 #define MLXCX_CMD_INLINE_INPUT_LEN 16 55 #define MLXCX_CMD_INLINE_OUTPUT_LEN 16 56 57 #define MLXCX_CMD_MAILBOX_LEN 512 58 59 #define MLXCX_CMD_TRANSPORT_PCI 7 60 #define MLXCX_CMD_HW_OWNED 0x01 61 #define MLXCX_CMD_STATUS(x) ((x) >> 1) 62 63 #define MLXCX_UAR_CQ_ARM 0x0020 64 #define MLXCX_UAR_EQ_ARM 0x0040 65 #define MLXCX_UAR_EQ_NOARM 0x0048 66 67 /* Number of blue flame reg pairs per UAR */ 68 #define MLXCX_BF_PER_UAR 2 69 #define MLXCX_BF_PER_UAR_MASK 0x1 70 #define MLXCX_BF_SIZE 0x100 71 #define MLXCX_BF_BASE 0x0800 72 73 /* CSTYLED */ 74 #define MLXCX_EQ_ARM_EQN (bitdef_t){24, 0xff000000} 75 /* CSTYLED */ 76 #define MLXCX_EQ_ARM_CI (bitdef_t){0, 0x00ffffff} 77 78 /* 79 * Hardware structure that is used to represent a command. 80 */ 81 #pragma pack(1) 82 typedef struct { 83 uint8_t mce_type; 84 uint8_t mce_rsvd[3]; 85 uint32be_t mce_in_length; 86 uint64be_t mce_in_mbox; 87 uint8_t mce_input[MLXCX_CMD_INLINE_INPUT_LEN]; 88 uint8_t mce_output[MLXCX_CMD_INLINE_OUTPUT_LEN]; 89 uint64be_t mce_out_mbox; 90 uint32be_t mce_out_length; 91 uint8_t mce_token; 92 uint8_t mce_sig; 93 uint8_t mce_rsvd1; 94 uint8_t mce_status; 95 } mlxcx_cmd_ent_t; 96 97 typedef struct { 98 uint8_t mlxb_data[MLXCX_CMD_MAILBOX_LEN]; 99 uint8_t mlxb_rsvd[48]; 100 uint64be_t mlxb_nextp; 101 uint32be_t mlxb_blockno; 102 uint8_t mlxb_rsvd1; 103 uint8_t mlxb_token; 104 uint8_t mlxb_ctrl_sig; 105 uint8_t mlxb_sig; 106 } mlxcx_cmd_mailbox_t; 107 108 typedef struct { 109 uint8_t mled_page_request_rsvd[2]; 110 uint16be_t mled_page_request_function_id; 111 uint32be_t mled_page_request_num_pages; 112 } mlxcx_evdata_page_request_t; 113 114 /* CSTYLED */ 115 #define MLXCX_EVENT_PORT_NUM (bitdef_t){ .bit_shift = 4, .bit_mask = 0xF0 } 116 117 typedef struct { 118 uint8_t mled_port_state_rsvd[8]; 119 bits8_t mled_port_state_port_num; 120 } mlxcx_evdata_port_state_t; 121 122 typedef enum { 123 MLXCX_MODULE_INITIALIZING = 0x0, 124 MLXCX_MODULE_PLUGGED = 0x1, 125 MLXCX_MODULE_UNPLUGGED = 0x2, 126 MLXCX_MODULE_ERROR = 0x3 127 } mlxcx_module_status_t; 128 129 typedef enum { 130 MLXCX_MODULE_ERR_POWER_BUDGET = 0x0, 131 MLXCX_MODULE_ERR_LONG_RANGE = 0x1, 132 MLXCX_MODULE_ERR_BUS_STUCK = 0x2, 133 MLXCX_MODULE_ERR_NO_EEPROM = 0x3, 134 MLXCX_MODULE_ERR_ENFORCEMENT = 0x4, 135 MLXCX_MODULE_ERR_UNKNOWN_IDENT = 0x5, 136 MLXCX_MODULE_ERR_HIGH_TEMP = 0x6, 137 MLXCX_MODULE_ERR_CABLE_SHORTED = 0x7, 138 } mlxcx_module_error_type_t; 139 140 typedef struct { 141 uint8_t mled_port_mod_rsvd; 142 uint8_t mled_port_mod_module; 143 uint8_t mled_port_mod_rsvd2; 144 uint8_t mled_port_mod_module_status; 145 uint8_t mled_port_mod_rsvd3[2]; 146 uint8_t mled_port_mod_error_type; 147 uint8_t mled_port_mod_rsvd4; 148 } mlxcx_evdata_port_mod_t; 149 150 typedef struct { 151 uint8_t mled_completion_rsvd[25]; 152 uint24be_t mled_completion_cqn; 153 } mlxcx_evdata_completion_t; 154 155 typedef enum { 156 MLXCX_EV_QUEUE_TYPE_QP = 0x0, 157 MLXCX_EV_QUEUE_TYPE_RQ = 0x1, 158 MLXCX_EV_QUEUE_TYPE_SQ = 0x2, 159 } mlxcx_evdata_queue_type_t; 160 161 typedef struct { 162 uint8_t mled_queue_rsvd[20]; 163 uint8_t mled_queue_type; 164 uint8_t mled_queue_rsvd2[4]; 165 uint24be_t mled_queue_num; 166 } mlxcx_evdata_queue_t; 167 168 #define MLXCX_EQ_OWNER_INIT 1 169 170 typedef struct { 171 uint8_t mleqe_rsvd[1]; 172 uint8_t mleqe_event_type; 173 uint8_t mleqe_rsvd2[1]; 174 uint8_t mleqe_event_sub_type; 175 uint8_t mleqe_rsvd3[28]; 176 union { 177 uint8_t mleqe_unknown_data[28]; 178 mlxcx_evdata_completion_t mleqe_completion; 179 mlxcx_evdata_page_request_t mleqe_page_request; 180 mlxcx_evdata_port_state_t mleqe_port_state; 181 mlxcx_evdata_port_mod_t mleqe_port_mod; 182 mlxcx_evdata_queue_t mleqe_queue; 183 }; 184 uint8_t mleqe_rsvd4[2]; 185 uint8_t mleqe_signature; 186 uint8_t mleqe_owner; 187 } mlxcx_eventq_ent_t; 188 189 typedef enum { 190 MLXCX_CQE_L3_HDR_NONE = 0x0, 191 MLXCX_CQE_L3_HDR_RCV_BUF = 0x1, 192 MLXCX_CQE_L3_HDR_CQE = 0x2, 193 } mlxcx_cqe_l3_hdr_placement_t; 194 195 typedef enum { 196 MLXCX_CQE_CSFLAGS_L4_OK = 1 << 2, 197 MLXCX_CQE_CSFLAGS_L3_OK = 1 << 1, 198 MLXCX_CQE_CSFLAGS_L2_OK = 1 << 0, 199 } mlxcx_cqe_csflags_t; 200 201 typedef enum { 202 MLXCX_CQE_L4_TYPE_NONE = 0, 203 MLXCX_CQE_L4_TYPE_TCP = 1, 204 MLXCX_CQE_L4_TYPE_UDP = 2, 205 MLXCX_CQE_L4_TYPE_TCP_EMPTY_ACK = 3, 206 MLXCX_CQE_L4_TYPE_TCP_ACK = 4, 207 } mlxcx_cqe_l4_hdr_type_t; 208 209 typedef enum { 210 MLXCX_CQE_L3_TYPE_NONE = 0, 211 MLXCX_CQE_L3_TYPE_IPv6 = 1, 212 MLXCX_CQE_L3_TYPE_IPv4 = 2, 213 } mlxcx_cqe_l3_hdr_type_t; 214 215 typedef enum { 216 MLXCX_CQE_RX_HASH_NONE = 0, 217 MLXCX_CQE_RX_HASH_IPv4 = 1, 218 MLXCX_CQE_RX_HASH_IPv6 = 2, 219 MLXCX_CQE_RX_HASH_IPSEC_SPI = 3, 220 } mlxcx_cqe_rx_hash_type_t; 221 /* BEGIN CSTYLED */ 222 #define MLXCX_CQE_RX_HASH_IP_SRC (bitdef_t){0, 0x3} 223 #define MLXCX_CQE_RX_HASH_IP_DEST (bitdef_t){2, (0x3 << 2)} 224 #define MLXCX_CQE_RX_HASH_L4_SRC (bitdef_t){4, (0x3 << 4)} 225 #define MLXCX_CQE_RX_HASH_L4_DEST (bitdef_t){6, (0x3 << 6)} 226 /* END CSTYLED */ 227 228 typedef enum { 229 MLXCX_CQE_OP_REQ = 0x0, 230 MLXCX_CQE_OP_RESP_RDMA = 0x1, 231 MLXCX_CQE_OP_RESP = 0x2, 232 MLXCX_CQE_OP_RESP_IMMEDIATE = 0x3, 233 MLXCX_CQE_OP_RESP_INVALIDATE = 0x4, 234 MLXCX_CQE_OP_RESIZE_CQ = 0x5, 235 MLXCX_CQE_OP_SIG_ERR = 0x12, 236 MLXCX_CQE_OP_REQ_ERR = 0xd, 237 MLXCX_CQE_OP_RESP_ERR = 0xe, 238 MLXCX_CQE_OP_INVALID = 0xf 239 } mlxcx_cqe_opcode_t; 240 241 typedef enum { 242 MLXCX_CQE_FORMAT_BASIC = 0, 243 MLXCX_CQE_FORMAT_INLINE_32 = 1, 244 MLXCX_CQE_FORMAT_INLINE_64 = 2, 245 MLXCX_CQE_FORMAT_COMPRESSED = 3, 246 } mlxcx_cqe_format_t; 247 248 typedef enum { 249 MLXCX_CQE_OWNER_INIT = 1 250 } mlxcx_cqe_owner_t; 251 252 typedef enum { 253 MLXCX_VLAN_TYPE_NONE, 254 MLXCX_VLAN_TYPE_CVLAN, 255 MLXCX_VLAN_TYPE_SVLAN, 256 } mlxcx_vlan_type_t; 257 258 typedef enum { 259 MLXCX_CQ_ERR_LOCAL_LENGTH = 0x1, 260 MLXCX_CQ_ERR_LOCAL_QP_OP = 0x2, 261 MLXCX_CQ_ERR_LOCAL_PROTECTION = 0x4, 262 MLXCX_CQ_ERR_WR_FLUSHED = 0x5, 263 MLXCX_CQ_ERR_MEM_WINDOW_BIND = 0x6, 264 MLXCX_CQ_ERR_BAD_RESPONSE = 0x10, 265 MLXCX_CQ_ERR_LOCAL_ACCESS = 0x11, 266 MLXCX_CQ_ERR_XPORT_RETRY_CTR = 0x15, 267 MLXCX_CQ_ERR_RNR_RETRY_CTR = 0x16, 268 MLXCX_CQ_ERR_ABORTED = 0x22 269 } mlxcx_cq_error_syndrome_t; 270 271 typedef struct { 272 uint8_t mlcqee_rsvd[2]; 273 uint16be_t mlcqee_wqe_id; 274 uint8_t mlcqee_rsvd2[29]; 275 uint24be_t mlcqee_user_index; 276 uint8_t mlcqee_rsvd3[8]; 277 uint32be_t mlcqee_byte_cnt; 278 uint8_t mlcqee_rsvd4[6]; 279 uint8_t mlcqee_vendor_error_syndrome; 280 uint8_t mlcqee_syndrome; 281 uint8_t mlcqee_wqe_opcode; 282 uint24be_t mlcqee_flow_tag; 283 uint16be_t mlcqee_wqe_counter; 284 uint8_t mlcqee_signature; 285 struct { 286 #if defined(_BIT_FIELDS_HTOL) 287 uint8_t mlcqe_opcode:4; 288 uint8_t mlcqe_rsvd5:3; 289 uint8_t mlcqe_owner:1; 290 #elif defined(_BIT_FIELDS_LTOH) 291 uint8_t mlcqe_owner:1; 292 uint8_t mlcqe_rsvd5:3; 293 uint8_t mlcqe_opcode:4; 294 #endif 295 }; 296 } mlxcx_completionq_error_ent_t; 297 298 typedef struct { 299 uint8_t mlcqe_tunnel_flags; 300 uint8_t mlcqe_rsvd[3]; 301 uint8_t mlcqe_lro_flags; 302 uint8_t mlcqe_lro_min_ttl; 303 uint16be_t mlcqe_lro_tcp_win; 304 uint32be_t mlcqe_lro_ack_seq_num; 305 uint32be_t mlcqe_rx_hash_result; 306 bits8_t mlcqe_rx_hash_type; 307 uint8_t mlcqe_ml_path; 308 uint8_t mlcqe_rsvd2[2]; 309 uint16be_t mlcqe_checksum; 310 uint16be_t mlcqe_slid_smac_lo; 311 struct { 312 #if defined(_BIT_FIELDS_HTOL) 313 uint8_t mlcqe_rsvd3:1; 314 uint8_t mlcqe_force_loopback:1; 315 uint8_t mlcqe_l3_hdr:2; 316 uint8_t mlcqe_sl_roce_pktype:4; 317 #elif defined(_BIT_FIELDS_LTOH) 318 uint8_t mlcqe_sl_roce_pktype:4; 319 uint8_t mlcqe_l3_hdr:2; 320 uint8_t mlcqe_force_loopback:1; 321 uint8_t mlcqe_rsvd3:1; 322 #endif 323 }; 324 uint24be_t mlcqe_rqpn; 325 bits8_t mlcqe_csflags; 326 struct { 327 #if defined(_BIT_FIELDS_HTOL) 328 uint8_t mlcqe_ip_frag:1; 329 uint8_t mlcqe_l4_hdr_type:3; 330 uint8_t mlcqe_l3_hdr_type:2; 331 uint8_t mlcqe_ip_ext_opts:1; 332 uint8_t mlcqe_cv:1; 333 #elif defined(_BIT_FIELDS_LTOH) 334 uint8_t mlcqe_cv:1; 335 uint8_t mlcqe_ip_ext_opts:1; 336 uint8_t mlcqe_l3_hdr_type:2; 337 uint8_t mlcqe_l4_hdr_type:3; 338 uint8_t mlcqe_ip_frag:1; 339 #endif 340 }; 341 uint16be_t mlcqe_up_cfi_vid; 342 uint8_t mlcqe_lro_num_seg; 343 uint24be_t mlcqe_user_index; 344 uint32be_t mlcqe_immediate; 345 uint8_t mlcqe_rsvd4[4]; 346 uint32be_t mlcqe_byte_cnt; 347 union { 348 struct { 349 uint32be_t mlcqe_lro_timestamp_value; 350 uint32be_t mlcqe_lro_timestamp_echo; 351 }; 352 uint64be_t mlcqe_timestamp; 353 }; 354 union { 355 uint8_t mlcqe_rx_drop_counter; 356 uint8_t mlcqe_send_wqe_opcode; 357 }; 358 uint24be_t mlcqe_flow_tag; 359 uint16be_t mlcqe_wqe_counter; 360 uint8_t mlcqe_signature; 361 struct { 362 #if defined(_BIT_FIELDS_HTOL) 363 uint8_t mlcqe_opcode:4; 364 uint8_t mlcqe_format:2; 365 uint8_t mlcqe_se:1; 366 uint8_t mlcqe_owner:1; 367 #elif defined(_BIT_FIELDS_LTOH) 368 uint8_t mlcqe_owner:1; 369 uint8_t mlcqe_se:1; 370 uint8_t mlcqe_format:2; 371 uint8_t mlcqe_opcode:4; 372 #endif 373 }; 374 } mlxcx_completionq_ent_t; 375 376 typedef struct { 377 uint8_t mlcqe_data[64]; 378 mlxcx_completionq_ent_t mlcqe_ent; 379 } mlxcx_completionq_ent128_t; 380 381 typedef enum { 382 MLXCX_WQE_OP_NOP = 0x00, 383 MLXCX_WQE_OP_SEND_INVALIDATE = 0x01, 384 MLXCX_WQE_OP_RDMA_W = 0x08, 385 MLXCX_WQE_OP_RDMA_W_IMMEDIATE = 0x09, 386 MLXCX_WQE_OP_SEND = 0x0A, 387 MLXCX_WQE_OP_SEND_IMMEDIATE = 0x0B, 388 MLXCX_WQE_OP_LSO = 0x0E, 389 MLXCX_WQE_OP_WAIT = 0x0F, 390 MLXCX_WQE_OP_RDMA_R = 0x10, 391 } mlxcx_wqe_opcode_t; 392 393 #define MLXCX_WQE_OCTOWORD 16 394 #define MLXCX_SQE_MAX_DS ((1 << 6) - 1) 395 /* 396 * Calculate the max number of address pointers in a single ethernet 397 * send message. This is the remainder from MLXCX_SQE_MAX_DS 398 * after accounting for the Control and Ethernet segements. 399 */ 400 #define MLXCX_SQE_MAX_PTRS (MLXCX_SQE_MAX_DS - \ 401 (sizeof (mlxcx_wqe_eth_seg_t) + sizeof (mlxcx_wqe_control_seg_t)) / \ 402 MLXCX_WQE_OCTOWORD) 403 404 typedef enum { 405 MLXCX_SQE_FENCE_NONE = 0x0, 406 MLXCX_SQE_FENCE_WAIT_OTHERS = 0x1, 407 MLXCX_SQE_FENCE_START = 0x2, 408 MLXCX_SQE_FENCE_STRONG_ORDER = 0x3, 409 MLXCX_SQE_FENCE_START_WAIT = 0x4 410 } mlxcx_sqe_fence_mode_t; 411 412 typedef enum { 413 MLXCX_SQE_CQE_ON_EACH_ERROR = 0x0, 414 MLXCX_SQE_CQE_ON_FIRST_ERROR = 0x1, 415 MLXCX_SQE_CQE_ALWAYS = 0x2, 416 MLXCX_SQE_CQE_ALWAYS_PLUS_EQE = 0x3 417 } mlxcx_sqe_completion_mode_t; 418 419 #define MLXCX_SQE_SOLICITED (1 << 1) 420 /* CSTYLED */ 421 #define MLXCX_SQE_FENCE_MODE (bitdef_t){5, 0xe0} 422 /* CSTYLED */ 423 #define MLXCX_SQE_COMPLETION_MODE (bitdef_t){2, 0x0c} 424 425 typedef struct { 426 uint8_t mlcs_opcode_mod; 427 uint16be_t mlcs_wqe_index; 428 uint8_t mlcs_opcode; 429 uint24be_t mlcs_qp_or_sq; 430 uint8_t mlcs_ds; 431 uint8_t mlcs_signature; 432 uint8_t mlcs_rsvd2[2]; 433 bits8_t mlcs_flags; 434 uint32be_t mlcs_immediate; 435 } mlxcx_wqe_control_seg_t; 436 437 typedef enum { 438 MLXCX_SQE_ETH_CSFLAG_L4_CHECKSUM = 1 << 7, 439 MLXCX_SQE_ETH_CSFLAG_L3_CHECKSUM = 1 << 6, 440 MLXCX_SQE_ETH_CSFLAG_L4_INNER_CHECKSUM = 1 << 5, 441 MLXCX_SQE_ETH_CSFLAG_L3_INNER_CHECKSUM = 1 << 4, 442 } mlxcx_wqe_eth_flags_t; 443 444 /* CSTYLED */ 445 #define MLXCX_SQE_ETH_INLINE_HDR_SZ (bitdef_t){0, 0x03ff} 446 #define MLXCX_SQE_ETH_SZFLAG_VLAN (1 << 15) 447 #define MLXCX_MAX_INLINE_HEADERLEN 64 448 449 typedef struct { 450 uint8_t mles_rsvd[4]; 451 bits8_t mles_csflags; 452 uint8_t mles_rsvd2[1]; 453 uint16_t mles_mss; 454 uint8_t mles_rsvd3[4]; 455 bits16_t mles_szflags; 456 uint8_t mles_inline_headers[18]; 457 } mlxcx_wqe_eth_seg_t; 458 459 typedef struct { 460 uint32be_t mlds_byte_count; 461 uint32be_t mlds_lkey; 462 uint64be_t mlds_address; 463 } mlxcx_wqe_data_seg_t; 464 465 #define MLXCX_SENDQ_STRIDE_SHIFT 6 466 467 typedef struct { 468 mlxcx_wqe_control_seg_t mlsqe_control; 469 mlxcx_wqe_eth_seg_t mlsqe_eth; 470 mlxcx_wqe_data_seg_t mlsqe_data[1]; 471 } mlxcx_sendq_ent_t; 472 473 typedef struct { 474 uint64be_t mlsqbf_qwords[8]; 475 } mlxcx_sendq_bf_t; 476 477 typedef struct { 478 mlxcx_wqe_data_seg_t mlsqe_data[4]; 479 } mlxcx_sendq_extra_ent_t; 480 481 #define MLXCX_RECVQ_STRIDE_SHIFT 7 482 /* 483 * Each mlxcx_wqe_data_seg_t is 1<<4 bytes long (there's a CTASSERT to verify 484 * this in mlxcx_cmd.c), so the number of pointers is 1 << (shift - 4). 485 */ 486 #define MLXCX_RECVQ_MAX_PTRS (1 << (MLXCX_RECVQ_STRIDE_SHIFT - 4)) 487 typedef struct { 488 mlxcx_wqe_data_seg_t mlrqe_data[MLXCX_RECVQ_MAX_PTRS]; 489 } mlxcx_recvq_ent_t; 490 491 /* CSTYLED */ 492 #define MLXCX_CQ_ARM_CI (bitdef_t){ .bit_shift = 0, \ 493 .bit_mask = 0x00ffffff } 494 /* CSTYLED */ 495 #define MLXCX_CQ_ARM_SEQ (bitdef_t){ .bit_shift = 28, \ 496 .bit_mask = 0x30000000 } 497 #define MLXCX_CQ_ARM_SOLICITED (1 << 24) 498 499 typedef struct { 500 uint8_t mlcqd_rsvd; 501 uint24be_t mlcqd_update_ci; 502 bits32_t mlcqd_arm_ci; 503 } mlxcx_completionq_doorbell_t; 504 505 typedef struct { 506 uint16be_t mlwqd_rsvd; 507 uint16be_t mlwqd_recv_counter; 508 uint16be_t mlwqd_rsvd2; 509 uint16be_t mlwqd_send_counter; 510 } mlxcx_workq_doorbell_t; 511 512 #define MLXCX_EQ_STATUS_OK (0x0 << 4) 513 #define MLXCX_EQ_STATUS_WRITE_FAILURE (0xA << 4) 514 515 #define MLXCX_EQ_OI (1 << 1) 516 #define MLXCX_EQ_EC (1 << 2) 517 518 #define MLXCX_EQ_ST_ARMED 0x9 519 #define MLXCX_EQ_ST_FIRED 0xA 520 521 /* CSTYLED */ 522 #define MLXCX_EQ_LOG_PAGE_SIZE (bitdef_t){ .bit_shift = 24, \ 523 .bit_mask = 0x1F000000 } 524 525 typedef struct { 526 uint8_t mleqc_status; 527 uint8_t mleqc_ecoi; 528 uint8_t mleqc_state; 529 uint8_t mleqc_rsvd[7]; 530 uint16be_t mleqc_page_offset; 531 uint8_t mleqc_log_eq_size; 532 uint24be_t mleqc_uar_page; 533 uint8_t mleqc_rsvd3[7]; 534 uint8_t mleqc_intr; 535 uint32be_t mleqc_log_page; 536 uint8_t mleqc_rsvd4[13]; 537 uint24be_t mleqc_consumer_counter; 538 uint8_t mleqc_rsvd5; 539 uint24be_t mleqc_producer_counter; 540 uint8_t mleqc_rsvd6[16]; 541 } mlxcx_eventq_ctx_t; 542 543 typedef enum { 544 MLXCX_CQC_CQE_SIZE_64 = 0x0, 545 MLXCX_CQC_CQE_SIZE_128 = 0x1, 546 } mlxcx_cqc_cqe_sz_t; 547 548 typedef enum { 549 MLXCX_CQC_STATUS_OK = 0x0, 550 MLXCX_CQC_STATUS_OVERFLOW = 0x9, 551 MLXCX_CQC_STATUS_WRITE_FAIL = 0xA, 552 MLXCX_CQC_STATUS_INVALID = 0xF 553 } mlxcx_cqc_status_t; 554 555 typedef enum { 556 MLXCX_CQC_STATE_ARMED_SOLICITED = 0x6, 557 MLXCX_CQC_STATE_ARMED = 0x9, 558 MLXCX_CQC_STATE_FIRED = 0xA 559 } mlxcx_cqc_state_t; 560 561 /* CSTYLED */ 562 #define MLXCX_CQ_CTX_STATUS (bitdef_t){28, 0xf0000000} 563 /* CSTYLED */ 564 #define MLXCX_CQ_CTX_CQE_SZ (bitdef_t){21, 0x00e00000} 565 /* CSTYLED */ 566 #define MLXCX_CQ_CTX_PERIOD_MODE (bitdef_t){15, 0x00018000} 567 /* CSTYLED */ 568 #define MLXCX_CQ_CTX_MINI_CQE_FORMAT (bitdef_t){12, 0x00003000} 569 /* CSTYLED */ 570 #define MLXCX_CQ_CTX_STATE (bitdef_t){8, 0x00000f00} 571 572 typedef struct mlxcx_completionq_ctx { 573 bits32_t mlcqc_flags; 574 575 uint8_t mlcqc_rsvd4[4]; 576 577 uint8_t mlcqc_rsvd5[2]; 578 uint16be_t mlcqc_page_offset; 579 580 uint8_t mlcqc_log_cq_size; 581 uint24be_t mlcqc_uar_page; 582 583 uint16be_t mlcqc_cq_period; 584 uint16be_t mlcqc_cq_max_count; 585 586 uint8_t mlcqc_rsvd7[3]; 587 uint8_t mlcqc_eqn; 588 589 uint8_t mlcqc_log_page_size; 590 uint8_t mlcqc_rsvd8[3]; 591 592 uint8_t mlcqc_rsvd9[4]; 593 594 uint8_t mlcqc_rsvd10; 595 uint24be_t mlcqc_last_notified_index; 596 uint8_t mlcqc_rsvd11; 597 uint24be_t mlcqc_last_solicit_index; 598 uint8_t mlcqc_rsvd12; 599 uint24be_t mlcqc_consumer_counter; 600 uint8_t mlcqc_rsvd13; 601 uint24be_t mlcqc_producer_counter; 602 603 uint8_t mlcqc_rsvd14[8]; 604 605 uint64be_t mlcqc_dbr_addr; 606 } mlxcx_completionq_ctx_t; 607 608 typedef enum { 609 MLXCX_WORKQ_TYPE_LINKED_LIST = 0x0, 610 MLXCX_WORKQ_TYPE_CYCLIC = 0x1, 611 MLXCX_WORKQ_TYPE_LINKED_LIST_STRIDING = 0x2, 612 MLXCX_WORKQ_TYPE_CYCLIC_STRIDING = 0x3 613 } mlxcx_workq_ctx_type_t; 614 615 typedef enum { 616 MLXCX_WORKQ_END_PAD_NONE = 0x0, 617 MLXCX_WORKQ_END_PAD_ALIGN = 0x1 618 } mlxcx_workq_end_padding_t; 619 620 /* CSTYLED */ 621 #define MLXCX_WORKQ_CTX_TYPE (bitdef_t){ \ 622 .bit_shift = 28, \ 623 .bit_mask = 0xf0000000 } 624 #define MLXCX_WORKQ_CTX_SIGNATURE (1 << 27) 625 #define MLXCX_WORKQ_CTX_CD_SLAVE (1 << 24) 626 /* CSTYLED */ 627 #define MLXCX_WORKQ_CTX_END_PADDING (bitdef_t){ \ 628 .bit_shift = 25, \ 629 .bit_mask = 0x06000000 } 630 631 #define MLXCX_WORKQ_CTX_MAX_ADDRESSES 128 632 633 typedef struct mlxcx_workq_ctx { 634 bits32_t mlwqc_flags; 635 uint8_t mlwqc_rsvd[2]; 636 uint16be_t mlwqc_lwm; 637 uint8_t mlwqc_rsvd2; 638 uint24be_t mlwqc_pd; 639 uint8_t mlwqc_rsvd3; 640 uint24be_t mlwqc_uar_page; 641 uint64be_t mlwqc_dbr_addr; 642 uint32be_t mlwqc_hw_counter; 643 uint32be_t mlwqc_sw_counter; 644 uint8_t mlwqc_rsvd4; 645 uint8_t mlwqc_log_wq_stride; 646 uint8_t mlwqc_log_wq_pg_sz; 647 uint8_t mlwqc_log_wq_sz; 648 uint8_t mlwqc_rsvd5[2]; 649 bits16_t mlwqc_strides; 650 uint8_t mlwqc_rsvd6[152]; 651 uint64be_t mlwqc_pas[MLXCX_WORKQ_CTX_MAX_ADDRESSES]; 652 } mlxcx_workq_ctx_t; 653 654 #define MLXCX_RQ_FLAGS_RLKEY (1UL << 31) 655 #define MLXCX_RQ_FLAGS_SCATTER_FCS (1 << 29) 656 #define MLXCX_RQ_FLAGS_VLAN_STRIP_DISABLE (1 << 28) 657 #define MLXCX_RQ_FLAGS_FLUSH_IN_ERROR (1 << 18) 658 /* CSTYLED */ 659 #define MLXCX_RQ_MEM_RQ_TYPE (bitdef_t){ \ 660 .bit_shift = 24, \ 661 .bit_mask = 0x0f000000 } 662 /* CSTYLED */ 663 #define MLXCX_RQ_STATE (bitdef_t){ \ 664 .bit_shift = 20, \ 665 .bit_mask = 0x00f00000 } 666 667 typedef struct mlxcx_rq_ctx { 668 bits32_t mlrqc_flags; 669 uint8_t mlrqc_rsvd; 670 uint24be_t mlrqc_user_index; 671 uint8_t mlrqc_rsvd2; 672 uint24be_t mlrqc_cqn; 673 uint8_t mlrqc_counter_set_id; 674 uint8_t mlrqc_rsvd3[4]; 675 uint24be_t mlrqc_rmpn; 676 uint8_t mlrqc_rsvd4[28]; 677 mlxcx_workq_ctx_t mlrqc_wq; 678 } mlxcx_rq_ctx_t; 679 680 #define MLXCX_SQ_FLAGS_RLKEY (1UL << 31) 681 #define MLXCX_SQ_FLAGS_CD_MASTER (1 << 30) 682 #define MLXCX_SQ_FLAGS_FRE (1 << 29) 683 #define MLXCX_SQ_FLAGS_FLUSH_IN_ERROR (1 << 28) 684 #define MLXCX_SQ_FLAGS_ALLOW_MULTI_PKT (1 << 27) 685 #define MLXCX_SQ_FLAGS_REG_UMR (1 << 19) 686 687 typedef enum { 688 MLXCX_ETH_CAP_INLINE_REQUIRE_L2 = 0, 689 MLXCX_ETH_CAP_INLINE_VPORT_CTX = 1, 690 MLXCX_ETH_CAP_INLINE_NOT_REQUIRED = 2 691 } mlxcx_eth_cap_inline_mode_t; 692 693 typedef enum { 694 MLXCX_ETH_INLINE_NONE = 0, 695 MLXCX_ETH_INLINE_L2 = 1, 696 MLXCX_ETH_INLINE_L3 = 2, 697 MLXCX_ETH_INLINE_L4 = 3, 698 MLXCX_ETH_INLINE_INNER_L2 = 5, 699 MLXCX_ETH_INLINE_INNER_L3 = 6, 700 MLXCX_ETH_INLINE_INNER_L4 = 7 701 } mlxcx_eth_inline_mode_t; 702 703 /* CSTYLED */ 704 #define MLXCX_SQ_MIN_WQE_INLINE (bitdef_t){ \ 705 .bit_shift = 24, \ 706 .bit_mask = 0x07000000 } 707 /* CSTYLED */ 708 #define MLXCX_SQ_STATE (bitdef_t){ \ 709 .bit_shift = 20, \ 710 .bit_mask = 0x00f00000 } 711 712 typedef struct mlxcx_sq_ctx { 713 bits32_t mlsqc_flags; 714 uint8_t mlsqc_rsvd; 715 uint24be_t mlsqc_user_index; 716 uint8_t mlsqc_rsvd2; 717 uint24be_t mlsqc_cqn; 718 uint8_t mlsqc_rsvd3[18]; 719 uint16be_t mlsqc_packet_pacing_rate_limit_index; 720 uint16be_t mlsqc_tis_lst_sz; 721 uint8_t mlsqc_rsvd4[11]; 722 uint24be_t mlsqc_tis_num; 723 mlxcx_workq_ctx_t mlsqc_wq; 724 } mlxcx_sq_ctx_t; 725 726 #define MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES 64 727 728 typedef enum { 729 MLXCX_VPORT_PROMISC_UCAST = 1 << 15, 730 MLXCX_VPORT_PROMISC_MCAST = 1 << 14, 731 MLXCX_VPORT_PROMISC_ALL = 1 << 13 732 } mlxcx_nic_vport_ctx_promisc_t; 733 734 #define MLXCX_VPORT_LIST_TYPE_MASK 0x07 735 #define MLXCX_VPORT_LIST_TYPE_SHIFT 0 736 737 /* CSTYLED */ 738 #define MLXCX_VPORT_CTX_MIN_WQE_INLINE (bitdef_t){56, 0x0700000000000000} 739 740 typedef struct { 741 bits64_t mlnvc_flags; 742 uint8_t mlnvc_rsvd[28]; 743 uint8_t mlnvc_rsvd2[2]; 744 uint16be_t mlnvc_mtu; 745 uint64be_t mlnvc_system_image_guid; 746 uint64be_t mlnvc_port_guid; 747 uint64be_t mlnvc_node_guid; 748 uint8_t mlnvc_rsvd3[40]; 749 uint16be_t mlnvc_qkey_violation_counter; 750 uint8_t mlnvc_rsvd4[2]; 751 uint8_t mlnvc_rsvd5[132]; 752 bits16_t mlnvc_promisc_list_type; 753 uint16be_t mlnvc_allowed_list_size; 754 uint8_t mlnvc_rsvd6[2]; 755 uint8_t mlnvc_permanent_address[6]; 756 uint8_t mlnvc_rsvd7[4]; 757 uint64be_t mlnvc_address[MLXCX_NIC_VPORT_CTX_MAX_ADDRESSES]; 758 } mlxcx_nic_vport_ctx_t; 759 760 typedef struct { 761 uint8_t mlftc_flags; 762 uint8_t mlftc_level; 763 uint8_t mlftc_rsvd; 764 uint8_t mlftc_log_size; 765 uint8_t mlftc_rsvd2; 766 uint24be_t mlftc_table_miss_id; 767 uint8_t mlftc_rsvd3[4]; 768 uint8_t mlftc_rsvd4[28]; 769 } mlxcx_flow_table_ctx_t; 770 771 /* CSTYLED */ 772 #define MLXCX_FLOW_HDR_FIRST_VID (bitdef_t){0, 0x07ff} 773 /* CSTYLED */ 774 #define MLXCX_FLOW_HDR_FIRST_PRIO (bitdef_t){13,0x7000} 775 #define MLXCX_FLOW_HDR_FIRST_CFI (1 << 12) 776 777 #define MLXCX_FLOW_HDR_IP_DSCP_SHIFT 18 778 #define MLXCX_FLOW_HDR_IP_DSCP_MASK 0xfc0000 779 #define MLXCX_FLOW_HDR_IP_ECN_SHIFT 16 780 #define MLXCX_FLOW_HDR_IP_ECN_MASK 0x030000 781 #define MLXCX_FLOW_HDR_CVLAN_TAG (1 << 15) 782 #define MLXCX_FLOW_HDR_SVLAN_TAG (1 << 14) 783 #define MLXCX_FLOW_HDR_FRAG (1 << 13) 784 /* CSTYLED */ 785 #define MLXCX_FLOW_HDR_IP_VERSION (bitdef_t){ \ 786 .bit_shift = 9, \ 787 .bit_mask = 0x001e00 } 788 /* CSTYLED */ 789 #define MLXCX_FLOW_HDR_TCP_FLAGS (bitdef_t){ \ 790 .bit_shift = 0, \ 791 .bit_mask = 0x0001ff } 792 793 typedef struct { 794 uint8_t mlfh_smac[6]; 795 uint16be_t mlfh_ethertype; 796 uint8_t mlfh_dmac[6]; 797 bits16_t mlfh_first_vid_flags; 798 uint8_t mlfh_ip_protocol; 799 bits24_t mlfh_tcp_ip_flags; 800 uint16be_t mlfh_tcp_sport; 801 uint16be_t mlfh_tcp_dport; 802 uint8_t mlfh_rsvd[3]; 803 uint8_t mlfh_ip_ttl_hoplimit; 804 uint16be_t mlfh_udp_sport; 805 uint16be_t mlfh_udp_dport; 806 uint8_t mlfh_src_ip[16]; 807 uint8_t mlfh_dst_ip[16]; 808 } mlxcx_flow_header_match_t; 809 810 typedef struct { 811 uint8_t mlfp_rsvd; 812 uint24be_t mlfp_source_sqn; 813 uint8_t mlfp_rsvd2[2]; 814 uint16be_t mlfp_source_port; 815 bits16_t mlfp_outer_second_vid_flags; 816 bits16_t mlfp_inner_second_vid_flags; 817 bits16_t mlfp_vlan_flags; 818 uint16be_t mlfp_gre_protocol; 819 uint32be_t mlfp_gre_key; 820 uint24be_t mlfp_vxlan_vni; 821 uint8_t mlfp_rsvd3; 822 uint8_t mlfp_rsvd4[4]; 823 uint8_t mlfp_rsvd5; 824 uint24be_t mlfp_outer_ipv6_flow_label; 825 uint8_t mlfp_rsvd6; 826 uint24be_t mlfp_inner_ipv6_flow_label; 827 uint8_t mlfp_rsvd7[28]; 828 } mlxcx_flow_params_match_t; 829 830 typedef struct { 831 mlxcx_flow_header_match_t mlfm_outer_headers; 832 mlxcx_flow_params_match_t mlfm_misc_parameters; 833 mlxcx_flow_header_match_t mlfm_inner_headers; 834 uint8_t mlfm_rsvd[320]; 835 } mlxcx_flow_match_t; 836 837 #define MLXCX_FLOW_MAX_DESTINATIONS 64 838 typedef enum { 839 MLXCX_FLOW_DEST_VPORT = 0x0, 840 MLXCX_FLOW_DEST_FLOW_TABLE = 0x1, 841 MLXCX_FLOW_DEST_TIR = 0x2, 842 MLXCX_FLOW_DEST_QP = 0x3 843 } mlxcx_flow_destination_type_t; 844 845 typedef struct { 846 uint8_t mlfd_destination_type; 847 uint24be_t mlfd_destination_id; 848 uint8_t mlfd_rsvd[4]; 849 } mlxcx_flow_dest_t; 850 851 typedef enum { 852 MLXCX_FLOW_ACTION_ALLOW = 1 << 0, 853 MLXCX_FLOW_ACTION_DROP = 1 << 1, 854 MLXCX_FLOW_ACTION_FORWARD = 1 << 2, 855 MLXCX_FLOW_ACTION_COUNT = 1 << 3, 856 MLXCX_FLOW_ACTION_ENCAP = 1 << 4, 857 MLXCX_FLOW_ACTION_DECAP = 1 << 5 858 } mlxcx_flow_action_t; 859 860 typedef struct { 861 uint8_t mlfec_rsvd[4]; 862 uint32be_t mlfec_group_id; 863 uint8_t mlfec_rsvd2; 864 uint24be_t mlfec_flow_tag; 865 uint8_t mlfec_rsvd3[2]; 866 uint16be_t mlfec_action; 867 uint8_t mlfec_rsvd4; 868 uint24be_t mlfec_destination_list_size; 869 uint8_t mlfec_rsvd5; 870 uint24be_t mlfec_flow_counter_list_size; 871 uint32be_t mlfec_encap_id; 872 uint8_t mlfec_rsvd6[36]; 873 mlxcx_flow_match_t mlfec_match_value; 874 uint8_t mlfec_rsvd7[192]; 875 mlxcx_flow_dest_t mlfec_destination[MLXCX_FLOW_MAX_DESTINATIONS]; 876 } mlxcx_flow_entry_ctx_t; 877 878 /* CSTYLED */ 879 #define MLXCX_TIR_CTX_DISP_TYPE (bitdef_t){ 4, 0xf0 } 880 typedef enum { 881 MLXCX_TIR_DIRECT = 0x0, 882 MLXCX_TIR_INDIRECT = 0x1, 883 } mlxcx_tir_type_t; 884 885 /* CSTYLED */ 886 #define MLXCX_TIR_LRO_TIMEOUT (bitdef_t){ 12, 0x0ffff000 } 887 /* CSTYLED */ 888 #define MLXCX_TIR_LRO_ENABLE_MASK (bitdef_t){ 8, 0x00000f00 } 889 /* CSTYLED */ 890 #define MLXCX_TIR_LRO_MAX_MSG_SZ (bitdef_t){ 0, 0x000000ff } 891 892 /* CSTYLED */ 893 #define MLXCX_TIR_RX_HASH_FN (bitdef_t){ 4, 0xf0 } 894 typedef enum { 895 MLXCX_TIR_HASH_NONE = 0x0, 896 MLXCX_TIR_HASH_XOR8 = 0x1, 897 MLXCX_TIR_HASH_TOEPLITZ = 0x2 898 } mlxcx_tir_hash_fn_t; 899 #define MLXCX_TIR_LB_UNICAST (1 << 24) 900 #define MLXCX_TIR_LB_MULTICAST (1 << 25) 901 902 /* CSTYLED */ 903 #define MLXCX_RX_HASH_L3_TYPE (bitdef_t){ 31, 0x80000000 } 904 typedef enum { 905 MLXCX_RX_HASH_L3_IPv4 = 0, 906 MLXCX_RX_HASH_L3_IPv6 = 1 907 } mlxcx_tir_rx_hash_l3_type_t; 908 /* CSTYLED */ 909 #define MLXCX_RX_HASH_L4_TYPE (bitdef_t){ 30, 0x40000000 } 910 typedef enum { 911 MLXCX_RX_HASH_L4_TCP = 0, 912 MLXCX_RX_HASH_L4_UDP = 1 913 } mlxcx_tir_rx_hash_l4_type_t; 914 /* CSTYLED */ 915 #define MLXCX_RX_HASH_FIELDS (bitdef_t){ 0, 0x3fffffff } 916 typedef enum { 917 MLXCX_RX_HASH_SRC_IP = 1 << 0, 918 MLXCX_RX_HASH_DST_IP = 1 << 1, 919 MLXCX_RX_HASH_L4_SPORT = 1 << 2, 920 MLXCX_RX_HASH_L4_DPORT = 1 << 3, 921 MLXCX_RX_HASH_IPSEC_SPI = 1 << 4 922 } mlxcx_tir_rx_hash_fields_t; 923 924 typedef struct { 925 uint8_t mltirc_rsvd[4]; 926 bits8_t mltirc_disp_type; 927 uint8_t mltirc_rsvd2[11]; 928 bits32_t mltirc_lro; 929 uint8_t mltirc_rsvd3[9]; 930 uint24be_t mltirc_inline_rqn; 931 bits8_t mltirc_flags; 932 uint24be_t mltirc_indirect_table; 933 bits8_t mltirc_hash_lb; 934 uint24be_t mltirc_transport_domain; 935 uint8_t mltirc_rx_hash_toeplitz_key[40]; 936 bits32_t mltirc_rx_hash_fields_outer; 937 bits32_t mltirc_rx_hash_fields_inner; 938 uint8_t mltirc_rsvd4[152]; 939 } mlxcx_tir_ctx_t; 940 941 typedef struct { 942 uint8_t mltisc_rsvd; 943 uint8_t mltisc_prio_or_sl; 944 uint8_t mltisc_rsvd2[35]; 945 uint24be_t mltisc_transport_domain; 946 uint8_t mltisc_rsvd3[120]; 947 } mlxcx_tis_ctx_t; 948 949 #define MLXCX_RQT_MAX_RQ_REFS 64 950 951 typedef struct { 952 uint8_t mlrqtr_rsvd; 953 uint24be_t mlrqtr_rqn; 954 } mlxcx_rqtable_rq_ref_t; 955 956 typedef struct { 957 uint8_t mlrqtc_rsvd[22]; 958 uint16be_t mlrqtc_max_size; 959 uint8_t mlrqtc_rsvd2[2]; 960 uint16be_t mlrqtc_actual_size; 961 uint8_t mlrqtc_rsvd3[212]; 962 mlxcx_rqtable_rq_ref_t mlrqtc_rqref[MLXCX_RQT_MAX_RQ_REFS]; 963 } mlxcx_rqtable_ctx_t; 964 965 #pragma pack() 966 967 typedef enum { 968 MLXCX_EVENT_COMPLETION = 0x00, 969 MLXCX_EVENT_PATH_MIGRATED = 0x01, 970 MLXCX_EVENT_COMM_ESTABLISH = 0x02, 971 MLXCX_EVENT_SENDQ_DRAIN = 0x03, 972 MLXCX_EVENT_LAST_WQE = 0x13, 973 MLXCX_EVENT_SRQ_LIMIT = 0x14, 974 MLXCX_EVENT_DCT_ALL_CLOSED = 0x1C, 975 MLXCX_EVENT_DCT_ACCKEY_VIOL = 0x1D, 976 MLXCX_EVENT_CQ_ERROR = 0x04, 977 MLXCX_EVENT_WQ_CATASTROPHE = 0x05, 978 MLXCX_EVENT_PATH_MIGRATE_FAIL = 0x07, 979 MLXCX_EVENT_PAGE_FAULT = 0x0C, 980 MLXCX_EVENT_WQ_INVALID_REQ = 0x10, 981 MLXCX_EVENT_WQ_ACCESS_VIOL = 0x11, 982 MLXCX_EVENT_SRQ_CATASTROPHE = 0x12, 983 MLXCX_EVENT_INTERNAL_ERROR = 0x08, 984 MLXCX_EVENT_PORT_STATE = 0x09, 985 MLXCX_EVENT_GPIO = 0x15, 986 MLXCX_EVENT_PORT_MODULE = 0x16, 987 MLXCX_EVENT_TEMP_WARNING = 0x17, 988 MLXCX_EVENT_REMOTE_CONFIG = 0x19, 989 MLXCX_EVENT_DCBX_CHANGE = 0x1E, 990 MLXCX_EVENT_DOORBELL_CONGEST = 0x1A, 991 MLXCX_EVENT_STALL_VL = 0x1B, 992 MLXCX_EVENT_CMD_COMPLETION = 0x0A, 993 MLXCX_EVENT_PAGE_REQUEST = 0x0B, 994 MLXCX_EVENT_NIC_VPORT = 0x0D, 995 MLXCX_EVENT_EC_PARAMS_CHANGE = 0x0E, 996 MLXCX_EVENT_XRQ_ERROR = 0x18 997 } mlxcx_event_t; 998 999 typedef enum { 1000 MLXCX_CMD_R_OK = 0x00, 1001 MLXCX_CMD_R_INTERNAL_ERR = 0x01, 1002 MLXCX_CMD_R_BAD_OP = 0x02, 1003 MLXCX_CMD_R_BAD_PARAM = 0x03, 1004 MLXCX_CMD_R_BAD_SYS_STATE = 0x04, 1005 MLXCX_CMD_R_BAD_RESOURCE = 0x05, 1006 MLXCX_CMD_R_RESOURCE_BUSY = 0x06, 1007 MLXCX_CMD_R_EXCEED_LIM = 0x08, 1008 MLXCX_CMD_R_BAD_RES_STATE = 0x09, 1009 MLXCX_CMD_R_BAD_INDEX = 0x0a, 1010 MLXCX_CMD_R_NO_RESOURCES = 0x0f, 1011 MLXCX_CMD_R_BAD_INPUT_LEN = 0x50, 1012 MLXCX_CMD_R_BAD_OUTPUT_LEN = 0x51, 1013 MLXCX_CMD_R_BAD_RESOURCE_STATE = 0x10, 1014 MLXCX_CMD_R_BAD_PKT = 0x30, 1015 MLXCX_CMD_R_BAD_SIZE = 0x40, 1016 MLXCX_CMD_R_TIMEOUT = 0xFF 1017 } mlxcx_cmd_ret_t; 1018 1019 typedef enum { 1020 MLXCX_OP_QUERY_HCA_CAP = 0x100, 1021 MLXCX_OP_QUERY_ADAPTER = 0x101, 1022 MLXCX_OP_INIT_HCA = 0x102, 1023 MLXCX_OP_TEARDOWN_HCA = 0x103, 1024 MLXCX_OP_ENABLE_HCA = 0x104, 1025 MLXCX_OP_DISABLE_HCA = 0x105, 1026 MLXCX_OP_QUERY_PAGES = 0x107, 1027 MLXCX_OP_MANAGE_PAGES = 0x108, 1028 MLXCX_OP_SET_HCA_CAP = 0x109, 1029 MLXCX_OP_QUERY_ISSI = 0x10A, 1030 MLXCX_OP_SET_ISSI = 0x10B, 1031 MLXCX_OP_SET_DRIVER_VERSION = 0x10D, 1032 MLXCX_OP_QUERY_OTHER_HCA_CAP = 0x10E, 1033 MLXCX_OP_MODIFY_OTHER_HCA_CAP = 0x10F, 1034 MLXCX_OP_SET_TUNNELED_OPERATIONS = 0x110, 1035 MLXCX_OP_CREATE_MKEY = 0x200, 1036 MLXCX_OP_QUERY_MKEY = 0x201, 1037 MLXCX_OP_DESTROY_MKEY = 0x202, 1038 MLXCX_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 1039 MLXCX_OP_PAGE_FAULT_RESUME = 0x204, 1040 MLXCX_OP_CREATE_EQ = 0x301, 1041 MLXCX_OP_DESTROY_EQ = 0x302, 1042 MLXCX_OP_QUERY_EQ = 0x303, 1043 MLXCX_OP_GEN_EQE = 0x304, 1044 MLXCX_OP_CREATE_CQ = 0x400, 1045 MLXCX_OP_DESTROY_CQ = 0x401, 1046 MLXCX_OP_QUERY_CQ = 0x402, 1047 MLXCX_OP_MODIFY_CQ = 0x403, 1048 MLXCX_OP_CREATE_QP = 0x500, 1049 MLXCX_OP_DESTROY_QP = 0x501, 1050 MLXCX_OP_RST2INIT_QP = 0x502, 1051 MLXCX_OP_INIT2RTR_QP = 0x503, 1052 MLXCX_OP_RTR2RTS_QP = 0x504, 1053 MLXCX_OP_RTS2RTS_QP = 0x505, 1054 MLXCX_OP_SQERR2RTS_QP = 0x506, 1055 MLXCX_OP__2ERR_QP = 0x507, 1056 MLXCX_OP__2RST_QP = 0x50A, 1057 MLXCX_OP_QUERY_QP = 0x50B, 1058 MLXCX_OP_SQD_RTS_QP = 0x50C, 1059 MLXCX_OP_INIT2INIT_QP = 0x50E, 1060 MLXCX_OP_CREATE_PSV = 0x600, 1061 MLXCX_OP_DESTROY_PSV = 0x601, 1062 MLXCX_OP_CREATE_SRQ = 0x700, 1063 MLXCX_OP_DESTROY_SRQ = 0x701, 1064 MLXCX_OP_QUERY_SRQ = 0x702, 1065 MLXCX_OP_ARM_RQ = 0x703, 1066 MLXCX_OP_CREATE_XRC_SRQ = 0x705, 1067 MLXCX_OP_DESTROY_XRC_SRQ = 0x706, 1068 MLXCX_OP_QUERY_XRC_SRQ = 0x707, 1069 MLXCX_OP_ARM_XRC_SRQ = 0x708, 1070 MLXCX_OP_CREATE_DCT = 0x710, 1071 MLXCX_OP_DESTROY_DCT = 0x711, 1072 MLXCX_OP_DRAIN_DCT = 0x712, 1073 MLXCX_OP_QUERY_DCT = 0x713, 1074 MLXCX_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 1075 MLXCX_OP_CREATE_XRQ = 0x717, 1076 MLXCX_OP_DESTROY_XRQ = 0x718, 1077 MLXCX_OP_QUERY_XRQ = 0x719, 1078 MLXCX_OP_CREATE_NVMF_BACKEND_CONTROLLER = 0x720, 1079 MLXCX_OP_DESTROY_NVMF_BACKEND_CONTROLLER = 0x721, 1080 MLXCX_OP_QUERY_NVMF_BACKEND_CONTROLLER = 0x722, 1081 MLXCX_OP_ATTACH_NVMF_NAMESPACE = 0x723, 1082 MLXCX_OP_DETACH_NVMF_NAMESPACE = 0x724, 1083 MLXCX_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 1084 MLXCX_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 1085 MLXCX_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 1086 MLXCX_OP_QUERY_VPORT_STATE = 0x750, 1087 MLXCX_OP_MODIFY_VPORT_STATE = 0x751, 1088 MLXCX_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 1089 MLXCX_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 1090 MLXCX_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1091 MLXCX_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 1092 MLXCX_OP_QUERY_ROCE_ADDRESS = 0x760, 1093 MLXCX_OP_SET_ROCE_ADDRESS = 0x761, 1094 MLXCX_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 1095 MLXCX_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 1096 MLXCX_OP_QUERY_HCA_VPORT_GID = 0x764, 1097 MLXCX_OP_QUERY_HCA_VPORT_PKEY = 0x765, 1098 MLXCX_OP_QUERY_VPORT_COUNTER = 0x770, 1099 MLXCX_OP_ALLOC_Q_COUNTER = 0x771, 1100 MLXCX_OP_DEALLOC_Q_COUNTER = 0x772, 1101 MLXCX_OP_QUERY_Q_COUNTER = 0x773, 1102 MLXCX_OP_SET_PP_RATE_LIMIT = 0x780, 1103 MLXCX_OP_QUERY_PP_RATE_LIMIT = 0x781, 1104 MLXCX_OP_ALLOC_PD = 0x800, 1105 MLXCX_OP_DEALLOC_PD = 0x801, 1106 MLXCX_OP_ALLOC_UAR = 0x802, 1107 MLXCX_OP_DEALLOC_UAR = 0x803, 1108 MLXCX_OP_CONFIG_INT_MODERATION = 0x804, 1109 MLXCX_OP_ACCESS_REG = 0x805, 1110 MLXCX_OP_ATTACH_TO_MCG = 0x806, 1111 MLXCX_OP_DETACH_FROM_MCG = 0x807, 1112 MLXCX_OP_MAD_IFC = 0x50D, 1113 MLXCX_OP_QUERY_MAD_DEMUX = 0x80B, 1114 MLXCX_OP_SET_MAD_DEMUX = 0x80C, 1115 MLXCX_OP_NOP = 0x80D, 1116 MLXCX_OP_ALLOC_XRCD = 0x80E, 1117 MLXCX_OP_DEALLOC_XRCD = 0x80F, 1118 MLXCX_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1119 MLXCX_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 1120 MLXCX_OP_QUERY_CONG_STATUS = 0x822, 1121 MLXCX_OP_MODIFY_CONG_STATUS = 0x823, 1122 MLXCX_OP_QUERY_CONG_PARAMS = 0x824, 1123 MLXCX_OP_MODIFY_CONG_PARAMS = 0x825, 1124 MLXCX_OP_QUERY_CONG_STATISTICS = 0x826, 1125 MLXCX_OP_ADD_VXLAN_UDP_DPORT = 0x827, 1126 MLXCX_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 1127 MLXCX_OP_SET_L2_TABLE_ENTRY = 0x829, 1128 MLXCX_OP_QUERY_L2_TABLE_ENTRY = 0x82A, 1129 MLXCX_OP_DELETE_L2_TABLE_ENTRY = 0x82B, 1130 MLXCX_OP_SET_WOL_ROL = 0x830, 1131 MLXCX_OP_QUERY_WOL_ROL = 0x831, 1132 MLXCX_OP_CREATE_TIR = 0x900, 1133 MLXCX_OP_MODIFY_TIR = 0x901, 1134 MLXCX_OP_DESTROY_TIR = 0x902, 1135 MLXCX_OP_QUERY_TIR = 0x903, 1136 MLXCX_OP_CREATE_SQ = 0x904, 1137 MLXCX_OP_MODIFY_SQ = 0x905, 1138 MLXCX_OP_DESTROY_SQ = 0x906, 1139 MLXCX_OP_QUERY_SQ = 0x907, 1140 MLXCX_OP_CREATE_RQ = 0x908, 1141 MLXCX_OP_MODIFY_RQ = 0x909, 1142 MLXCX_OP_DESTROY_RQ = 0x90A, 1143 MLXCX_OP_QUERY_RQ = 0x90B, 1144 MLXCX_OP_CREATE_RMP = 0x90C, 1145 MLXCX_OP_MODIFY_RMP = 0x90D, 1146 MLXCX_OP_DESTROY_RMP = 0x90E, 1147 MLXCX_OP_QUERY_RMP = 0x90F, 1148 MLXCX_OP_CREATE_TIS = 0x912, 1149 MLXCX_OP_MODIFY_TIS = 0x913, 1150 MLXCX_OP_DESTROY_TIS = 0x914, 1151 MLXCX_OP_QUERY_TIS = 0x915, 1152 MLXCX_OP_CREATE_RQT = 0x916, 1153 MLXCX_OP_MODIFY_RQT = 0x917, 1154 MLXCX_OP_DESTROY_RQT = 0x918, 1155 MLXCX_OP_QUERY_RQT = 0x919, 1156 MLXCX_OP_SET_FLOW_TABLE_ROOT = 0x92f, 1157 MLXCX_OP_CREATE_FLOW_TABLE = 0x930, 1158 MLXCX_OP_DESTROY_FLOW_TABLE = 0x931, 1159 MLXCX_OP_QUERY_FLOW_TABLE = 0x932, 1160 MLXCX_OP_CREATE_FLOW_GROUP = 0x933, 1161 MLXCX_OP_DESTROY_FLOW_GROUP = 0x934, 1162 MLXCX_OP_QUERY_FLOW_GROUP = 0x935, 1163 MLXCX_OP_SET_FLOW_TABLE_ENTRY = 0x936, 1164 MLXCX_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 1165 MLXCX_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 1166 MLXCX_OP_ALLOC_FLOW_COUNTER = 0x939, 1167 MLXCX_OP_DEALLOC_FLOW_COUNTER = 0x93a, 1168 MLXCX_OP_QUERY_FLOW_COUNTER = 0x93b, 1169 MLXCX_OP_MODIFY_FLOW_TABLE = 0x93c, 1170 MLXCX_OP_ALLOC_ENCAP_HEADER = 0x93d, 1171 MLXCX_OP_DEALLOC_ENCAP_HEADER = 0x93e, 1172 MLXCX_OP_QUERY_ENCAP_HEADER = 0x93f 1173 } mlxcx_cmd_op_t; 1174 1175 /* 1176 * Definitions for relevant commands 1177 */ 1178 #pragma pack(1) 1179 typedef struct { 1180 uint16be_t mci_opcode; 1181 uint8_t mci_rsvd[4]; 1182 uint16be_t mci_op_mod; 1183 } mlxcx_cmd_in_t; 1184 1185 typedef struct { 1186 uint8_t mco_status; 1187 uint8_t mco_rsvd[3]; 1188 uint32be_t mco_syndrome; 1189 } mlxcx_cmd_out_t; 1190 1191 typedef struct { 1192 mlxcx_cmd_in_t mlxi_enable_hca_head; 1193 uint8_t mlxi_enable_hca_rsvd[2]; 1194 uint16be_t mlxi_enable_hca_func; 1195 uint8_t mlxi_enable_hca_rsvd1[4]; 1196 } mlxcx_cmd_enable_hca_in_t; 1197 1198 typedef struct { 1199 mlxcx_cmd_out_t mlxo_enable_hca_head; 1200 uint8_t mlxo_enable_hca_rsvd[8]; 1201 } mlxcx_cmd_enable_hca_out_t; 1202 1203 typedef struct { 1204 mlxcx_cmd_in_t mlxi_disable_hca_head; 1205 uint8_t mlxi_disable_hca_rsvd[2]; 1206 uint16be_t mlxi_disable_hca_func; 1207 uint8_t mlxi_disable_hca_rsvd1[4]; 1208 } mlxcx_cmd_disable_hca_in_t; 1209 1210 typedef struct { 1211 mlxcx_cmd_out_t mlxo_disable_hca_head; 1212 uint8_t mlxo_disable_hca_rsvd[8]; 1213 } mlxcx_cmd_disable_hca_out_t; 1214 1215 typedef struct { 1216 mlxcx_cmd_in_t mlxi_query_issi_head; 1217 uint8_t mlxi_query_issi_rsvd[8]; 1218 } mlxcx_cmd_query_issi_in_t; 1219 1220 typedef struct { 1221 mlxcx_cmd_out_t mlxo_query_issi_head; 1222 uint8_t mlxo_query_issi_rsv[2]; 1223 uint16be_t mlxo_query_issi_current; 1224 uint8_t mlxo_query_issi_rsvd1[20]; 1225 /* 1226 * To date we only support version 1 of the ISSI. The last byte has the 1227 * ISSI data that we care about, therefore we phrase the struct this 1228 * way. 1229 */ 1230 uint8_t mlxo_query_issi_rsvd2[79]; 1231 uint8_t mlxo_supported_issi; 1232 } mlxcx_cmd_query_issi_out_t; 1233 1234 typedef struct { 1235 mlxcx_cmd_in_t mlxi_set_issi_head; 1236 uint8_t mlxi_set_issi_rsvd[2]; 1237 uint16be_t mlxi_set_issi_current; 1238 uint8_t mlxi_set_iss_rsvd1[4]; 1239 } mlxcx_cmd_set_issi_in_t; 1240 1241 typedef struct { 1242 mlxcx_cmd_out_t mlxo_set_issi_head; 1243 uint8_t mlxo_set_issi_rsvd[8]; 1244 } mlxcx_cmd_set_issi_out_t; 1245 1246 typedef struct { 1247 mlxcx_cmd_in_t mlxi_init_hca_head; 1248 uint8_t mlxi_init_hca_rsvd[8]; 1249 } mlxcx_cmd_init_hca_in_t; 1250 1251 typedef struct { 1252 mlxcx_cmd_out_t mlxo_init_hca_head; 1253 uint8_t mlxo_init_hca_rsvd[8]; 1254 } mlxcx_cmd_init_hca_out_t; 1255 1256 #define MLXCX_TEARDOWN_HCA_GRACEFUL 0x00 1257 #define MLXCX_TEARDOWN_HCA_FORCE 0x01 1258 1259 typedef struct { 1260 mlxcx_cmd_in_t mlxi_teardown_hca_head; 1261 uint8_t mlxi_teardown_hca_rsvd[2]; 1262 uint16be_t mlxi_teardown_hca_profile; 1263 uint8_t mlxi_teardown_hca_rsvd1[4]; 1264 } mlxcx_cmd_teardown_hca_in_t; 1265 1266 typedef struct { 1267 mlxcx_cmd_out_t mlxo_teardown_hca_head; 1268 uint8_t mlxo_teardown_hca_rsvd[7]; 1269 uint8_t mlxo_teardown_hca_state; 1270 } mlxcx_cmd_teardown_hca_out_t; 1271 1272 #define MLXCX_QUERY_PAGES_OPMOD_BOOT 0x01 1273 #define MLXCX_QUERY_PAGES_OPMOD_INIT 0x02 1274 #define MLXCX_QUERY_PAGES_OPMOD_REGULAR 0x03 1275 1276 typedef struct { 1277 mlxcx_cmd_in_t mlxi_query_pages_head; 1278 uint8_t mlxi_query_pages_rsvd[2]; 1279 uint16be_t mlxi_query_pages_func; 1280 uint8_t mlxi_query_pages_rsvd1[4]; 1281 } mlxcx_cmd_query_pages_in_t; 1282 1283 typedef struct { 1284 mlxcx_cmd_out_t mlxo_query_pages_head; 1285 uint8_t mlxo_query_pages_rsvd[2]; 1286 uint16be_t mlxo_query_pages_func; 1287 uint32be_t mlxo_query_pages_npages; 1288 } mlxcx_cmd_query_pages_out_t; 1289 1290 #define MLXCX_MANAGE_PAGES_OPMOD_ALLOC_FAIL 0x00 1291 #define MLXCX_MANAGE_PAGES_OPMOD_GIVE_PAGES 0x01 1292 #define MLXCX_MANAGE_PAGES_OPMOD_RETURN_PAGES 0x02 1293 1294 /* 1295 * This is an artificial limit that we're imposing on our actions. 1296 */ 1297 #define MLXCX_MANAGE_PAGES_MAX_PAGES 512 1298 1299 typedef struct { 1300 mlxcx_cmd_in_t mlxi_manage_pages_head; 1301 uint8_t mlxi_manage_pages_rsvd[2]; 1302 uint16be_t mlxi_manage_pages_func; 1303 uint32be_t mlxi_manage_pages_npages; 1304 uint64be_t mlxi_manage_pages_pas[MLXCX_MANAGE_PAGES_MAX_PAGES]; 1305 } mlxcx_cmd_manage_pages_in_t; 1306 1307 typedef struct { 1308 mlxcx_cmd_out_t mlxo_manage_pages_head; 1309 uint32be_t mlxo_manage_pages_npages; 1310 uint8_t mlxo_manage_pages_rsvd[4]; 1311 uint64be_t mlxo_manage_pages_pas[MLXCX_MANAGE_PAGES_MAX_PAGES]; 1312 } mlxcx_cmd_manage_pages_out_t; 1313 1314 typedef enum { 1315 MLXCX_HCA_CAP_MODE_MAX = 0x0, 1316 MLXCX_HCA_CAP_MODE_CURRENT = 0x1 1317 } mlxcx_hca_cap_mode_t; 1318 1319 typedef enum { 1320 MLXCX_HCA_CAP_GENERAL = 0x0, 1321 MLXCX_HCA_CAP_ETHERNET = 0x1, 1322 MLXCX_HCA_CAP_ODP = 0x2, 1323 MLXCX_HCA_CAP_ATOMIC = 0x3, 1324 MLXCX_HCA_CAP_ROCE = 0x4, 1325 MLXCX_HCA_CAP_IPoIB = 0x5, 1326 MLXCX_HCA_CAP_NIC_FLOW = 0x7, 1327 MLXCX_HCA_CAP_ESWITCH_FLOW = 0x8, 1328 MLXCX_HCA_CAP_ESWITCH = 0x9, 1329 MLXCX_HCA_CAP_VECTOR = 0xb, 1330 MLXCX_HCA_CAP_QoS = 0xc, 1331 MLXCX_HCA_CAP_NVMEoF = 0xe 1332 } mlxcx_hca_cap_type_t; 1333 1334 typedef enum { 1335 MLXCX_CAP_GENERAL_PORT_TYPE_IB = 0x0, 1336 MLXCX_CAP_GENERAL_PORT_TYPE_ETHERNET = 0x1, 1337 } mlxcx_hca_cap_general_port_type_t; 1338 1339 typedef enum { 1340 MLXCX_CAP_GENERAL_FLAGS_C_ESW_FLOW_TABLE = (1 << 8), 1341 MLXCX_CAP_GENERAL_FLAGS_C_NIC_FLOW_TABLE = (1 << 9), 1342 } mlxcx_hca_cap_general_flags_c_t; 1343 1344 typedef struct { 1345 uint8_t mlcap_general_access_other_hca_roce; 1346 uint8_t mlcap_general_rsvd[3]; 1347 1348 uint8_t mlcap_general_rsvd2[12]; 1349 1350 uint8_t mlcap_general_log_max_srq_sz; 1351 uint8_t mlcap_general_log_max_qp_sz; 1352 uint8_t mlcap_general_rsvd3[1]; 1353 uint8_t mlcap_general_log_max_qp; 1354 1355 uint8_t mlcap_general_rsvd4[1]; 1356 uint8_t mlcap_general_log_max_srq; 1357 uint8_t mlcap_general_rsvd5[2]; 1358 1359 uint8_t mlcap_general_rsvd6[1]; 1360 uint8_t mlcap_general_log_max_cq_sz; 1361 uint8_t mlcap_general_rsvd7[1]; 1362 uint8_t mlcap_general_log_max_cq; 1363 1364 uint8_t mlcap_general_log_max_eq_sz; 1365 uint8_t mlcap_general_log_max_mkey_flags; 1366 uint8_t mlcap_general_rsvd8[1]; 1367 uint8_t mlcap_general_log_max_eq; 1368 1369 uint8_t mlcap_general_max_indirection; 1370 uint8_t mlcap_general_log_max_mrw_sz_flags; 1371 uint8_t mlcap_general_log_max_bsf_list_size_flags; 1372 uint8_t mlcap_general_log_max_klm_list_size_flags; 1373 1374 uint8_t mlcap_general_rsvd9[1]; 1375 uint8_t mlcap_general_log_max_ra_req_dc; 1376 uint8_t mlcap_general_rsvd10[1]; 1377 uint8_t mlcap_general_log_max_ra_res_dc; 1378 1379 uint8_t mlcap_general_rsvd11[1]; 1380 uint8_t mlcap_general_log_max_ra_req_qp; 1381 uint8_t mlcap_general_rsvd12[1]; 1382 uint8_t mlcap_general_log_max_ra_res_qp; 1383 1384 uint16be_t mlcap_general_flags_a; 1385 uint16be_t mlcap_general_gid_table_size; 1386 1387 bits16_t mlcap_general_flags_b; 1388 uint16be_t mlcap_general_pkey_table_size; 1389 1390 bits16_t mlcap_general_flags_c; 1391 struct { 1392 #if defined(_BIT_FIELDS_HTOL) 1393 uint8_t mlcap_general_flags_d:6; 1394 uint8_t mlcap_general_port_type:2; 1395 #elif defined(_BIT_FIELDS_LTOH) 1396 uint8_t mlcap_general_port_type:2; 1397 uint8_t mlcap_general_flags_d:6; 1398 #endif 1399 }; 1400 uint8_t mlcap_general_num_ports; 1401 1402 struct { 1403 #if defined(_BIT_FIELDS_HTOL) 1404 uint8_t mlcap_general_rsvd13:3; 1405 uint8_t mlcap_general_log_max_msg:5; 1406 #elif defined(_BIT_FIELDS_LTOH) 1407 uint8_t mlcap_general_log_max_msg:5; 1408 uint8_t mlcap_general_rsvd13:3; 1409 #endif 1410 }; 1411 uint8_t mlcap_general_max_tc; 1412 bits16_t mlcap_general_flags_d_wol; 1413 1414 uint16be_t mlcap_general_state_rate_support; 1415 uint8_t mlcap_general_rsvd14[1]; 1416 struct { 1417 #if defined(_BIT_FIELDS_HTOL) 1418 uint8_t mlcap_general_rsvd15:4; 1419 uint8_t mlcap_general_cqe_version:4; 1420 #elif defined(_BIT_FIELDS_LTOH) 1421 uint8_t mlcap_general_cqe_version:4; 1422 uint8_t mlcap_general_rsvd15:4; 1423 #endif 1424 }; 1425 1426 uint32be_t mlcap_general_flags_e; 1427 1428 uint32be_t mlcap_general_flags_f; 1429 1430 uint8_t mlcap_general_rsvd16[1]; 1431 uint8_t mlcap_general_uar_sz; 1432 uint8_t mlcap_general_cnak; 1433 uint8_t mlcap_general_log_pg_sz; 1434 uint8_t mlcap_general_rsvd17[32]; 1435 bits8_t mlcap_general_log_max_rq_flags; 1436 uint8_t mlcap_general_log_max_sq; 1437 uint8_t mlcap_general_log_max_tir; 1438 uint8_t mlcap_general_log_max_tis; 1439 } mlxcx_hca_cap_general_caps_t; 1440 1441 typedef enum { 1442 MLXCX_ETH_CAP_TUNNEL_STATELESS_VXLAN = 1 << 0, 1443 MLXCX_ETH_CAP_TUNNEL_STATELESS_GRE = 1 << 1, 1444 MLXCX_ETH_CAP_TUNNEL_LSO_CONST_OUT_IP_ID = 1 << 4, 1445 MLXCX_ETH_CAP_SCATTER_FCS = 1 << 6, 1446 MLXCX_ETH_CAP_REG_UMR_SQ = 1 << 7, 1447 MLXCX_ETH_CAP_SELF_LB_UC = 1 << 21, 1448 MLXCX_ETH_CAP_SELF_LB_MC = 1 << 22, 1449 MLXCX_ETH_CAP_SELF_LB_EN_MODIFIABLE = 1 << 23, 1450 MLXCX_ETH_CAP_WQE_VLAN_INSERT = 1 << 24, 1451 MLXCX_ETH_CAP_LRO_TIME_STAMP = 1 << 27, 1452 MLXCX_ETH_CAP_LRO_PSH_FLAG = 1 << 28, 1453 MLXCX_ETH_CAP_LRO_CAP = 1 << 29, 1454 MLXCX_ETH_CAP_VLAN_STRIP = 1 << 30, 1455 MLXCX_ETH_CAP_CSUM_CAP = 1UL << 31 1456 } mlxcx_hca_eth_cap_flags_t; 1457 1458 /* CSTYLED */ 1459 #define MLXCX_ETH_CAP_RSS_IND_TBL_CAP (bitdef_t){8, 0x00000f00} 1460 /* CSTYLED */ 1461 #define MLXCX_ETH_CAP_WQE_INLINE_MODE (bitdef_t){12, 0x00003000} 1462 /* CSTYLED */ 1463 #define MLXCX_ETH_CAP_MULTI_PKT_SEND_WQE (bitdef_t){14, 0x0000c000} 1464 /* CSTYLED */ 1465 #define MLXCX_ETH_CAP_MAX_LSO_CAP (bitdef_t){16, 0x001f0000} 1466 /* CSTYLED */ 1467 #define MLXCX_ETH_CAP_LRO_MAX_MSG_SZ_MODE (bitdef_t){25, 0x06000000} 1468 1469 typedef struct { 1470 bits32_t mlcap_eth_flags; 1471 uint8_t mlcap_eth_rsvd[6]; 1472 uint16be_t mlcap_eth_lro_min_mss_size; 1473 uint8_t mlcap_eth_rsvd2[36]; 1474 uint32be_t mlcap_eth_lro_timer_supported_periods[4]; 1475 } mlxcx_hca_cap_eth_caps_t; 1476 1477 typedef enum { 1478 MLXCX_FLOW_CAP_PROPS_DECAP = 1 << 23, 1479 MLXCX_FLOW_CAP_PROPS_ENCAP = 1 << 24, 1480 MLXCX_FLOW_CAP_PROPS_MODIFY_TBL = 1 << 25, 1481 MLXCX_FLOW_CAP_PROPS_MISS_TABLE = 1 << 26, 1482 MLXCX_FLOW_CAP_PROPS_MODIFY_ROOT_TBL = 1 << 27, 1483 MLXCX_FLOW_CAP_PROPS_MODIFY = 1 << 28, 1484 MLXCX_FLOW_CAP_PROPS_COUNTER = 1 << 29, 1485 MLXCX_FLOW_CAP_PROPS_TAG = 1 << 30, 1486 MLXCX_FLOW_CAP_PROPS_SUPPORT = 1UL << 31 1487 } mlxcx_hca_cap_flow_cap_props_flags_t; 1488 1489 typedef struct { 1490 bits32_t mlcap_flow_prop_flags; 1491 uint8_t mlcap_flow_prop_log_max_ft_size; 1492 uint8_t mlcap_flow_prop_rsvd[2]; 1493 uint8_t mlcap_flow_prop_max_ft_level; 1494 uint8_t mlcap_flow_prop_rsvd2[7]; 1495 uint8_t mlcap_flow_prop_log_max_ft_num; 1496 uint8_t mlcap_flow_prop_rsvd3[2]; 1497 uint8_t mlcap_flow_prop_log_max_flow_counter; 1498 uint8_t mlcap_flow_prop_log_max_destination; 1499 uint8_t mlcap_flow_prop_rsvd4[3]; 1500 uint8_t mlcap_flow_prop_log_max_flow; 1501 uint8_t mlcap_flow_prop_rsvd5[8]; 1502 bits32_t mlcap_flow_prop_support[4]; 1503 bits32_t mlcap_flow_prop_bitmask[4]; 1504 } mlxcx_hca_cap_flow_cap_props_t; 1505 1506 typedef struct { 1507 bits32_t mlcap_flow_flags; 1508 uint8_t mlcap_flow_rsvd[60]; 1509 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx; 1510 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_rdma; 1511 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_rx_sniffer; 1512 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx; 1513 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_rdma; 1514 mlxcx_hca_cap_flow_cap_props_t mlcap_flow_nic_tx_sniffer; 1515 } mlxcx_hca_cap_flow_caps_t; 1516 1517 /* 1518 * Size of a buffer that is required to hold the output data. 1519 */ 1520 #define MLXCX_HCA_CAP_SIZE 0x1000 1521 1522 typedef struct { 1523 mlxcx_cmd_in_t mlxi_query_hca_cap_head; 1524 uint8_t mlxi_query_hca_cap_rsvd[8]; 1525 } mlxcx_cmd_query_hca_cap_in_t; 1526 1527 typedef struct { 1528 mlxcx_cmd_out_t mlxo_query_hca_cap_head; 1529 uint8_t mlxo_query_hca_cap_rsvd[8]; 1530 uint8_t mlxo_query_hca_cap_data[MLXCX_HCA_CAP_SIZE]; 1531 } mlxcx_cmd_query_hca_cap_out_t; 1532 1533 typedef struct { 1534 mlxcx_cmd_in_t mlxi_set_driver_version_head; 1535 uint8_t mlxi_set_driver_version_rsvd[8]; 1536 char mlxi_set_driver_version_version[64]; 1537 } mlxcx_cmd_set_driver_version_in_t; 1538 1539 typedef struct { 1540 mlxcx_cmd_out_t mlxo_set_driver_version_head; 1541 uint8_t mlxo_set_driver_version_rsvd[8]; 1542 } mlxcx_cmd_set_driver_version_out_t; 1543 1544 typedef struct { 1545 mlxcx_cmd_in_t mlxi_alloc_uar_head; 1546 uint8_t mlxi_alloc_uar_rsvd[8]; 1547 } mlxcx_cmd_alloc_uar_in_t; 1548 1549 typedef struct { 1550 mlxcx_cmd_out_t mlxo_alloc_uar_head; 1551 uint8_t mlxo_alloc_uar_rsvd; 1552 uint24be_t mlxo_alloc_uar_uar; 1553 uint8_t mlxo_alloc_uar_rsvd2[4]; 1554 } mlxcx_cmd_alloc_uar_out_t; 1555 1556 typedef struct { 1557 mlxcx_cmd_in_t mlxi_dealloc_uar_head; 1558 uint8_t mlxi_dealloc_uar_rsvd; 1559 uint24be_t mlxi_dealloc_uar_uar; 1560 uint8_t mlxi_dealloc_uar_rsvd2[4]; 1561 } mlxcx_cmd_dealloc_uar_in_t; 1562 1563 typedef struct { 1564 mlxcx_cmd_out_t mlxo_dealloc_uar_head; 1565 uint8_t mlxo_dealloc_uar_rsvd[8]; 1566 } mlxcx_cmd_dealloc_uar_out_t; 1567 1568 /* 1569 * This is an artificial limit that we're imposing on our actions. 1570 */ 1571 #define MLXCX_CREATE_QUEUE_MAX_PAGES 128 1572 1573 typedef struct { 1574 mlxcx_cmd_in_t mlxi_create_eq_head; 1575 uint8_t mlxi_create_eq_rsvd[8]; 1576 mlxcx_eventq_ctx_t mlxi_create_eq_context; 1577 uint8_t mlxi_create_eq_rsvd2[8]; 1578 uint64be_t mlxi_create_eq_event_bitmask; 1579 uint8_t mlxi_create_eq_rsvd3[176]; 1580 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1581 } mlxcx_cmd_create_eq_in_t; 1582 1583 typedef struct { 1584 mlxcx_cmd_out_t mlxo_create_eq_head; 1585 uint8_t mlxo_create_eq_rsvd[3]; 1586 uint8_t mlxo_create_eq_eqn; 1587 uint8_t mlxo_create_eq_rsvd2[4]; 1588 } mlxcx_cmd_create_eq_out_t; 1589 1590 typedef struct { 1591 mlxcx_cmd_in_t mlxi_query_eq_head; 1592 uint8_t mlxi_query_eq_rsvd[3]; 1593 uint8_t mlxi_query_eq_eqn; 1594 uint8_t mlxi_query_eq_rsvd2[4]; 1595 } mlxcx_cmd_query_eq_in_t; 1596 1597 typedef struct { 1598 mlxcx_cmd_out_t mlxo_query_eq_head; 1599 uint8_t mlxo_query_eq_rsvd[8]; 1600 mlxcx_eventq_ctx_t mlxo_query_eq_context; 1601 uint8_t mlxi_query_eq_rsvd2[8]; 1602 uint64be_t mlxi_query_eq_event_bitmask; 1603 uint8_t mlxi_query_eq_rsvd3[176]; 1604 uint64be_t mlxi_create_eq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1605 } mlxcx_cmd_query_eq_out_t; 1606 1607 typedef struct { 1608 mlxcx_cmd_in_t mlxi_destroy_eq_head; 1609 uint8_t mlxi_destroy_eq_rsvd[3]; 1610 uint8_t mlxi_destroy_eq_eqn; 1611 uint8_t mlxi_destroy_eq_rsvd2[4]; 1612 } mlxcx_cmd_destroy_eq_in_t; 1613 1614 typedef struct { 1615 mlxcx_cmd_out_t mlxo_destroy_eq_head; 1616 uint8_t mlxo_destroy_eq_rsvd[8]; 1617 } mlxcx_cmd_destroy_eq_out_t; 1618 1619 typedef struct { 1620 mlxcx_cmd_in_t mlxi_alloc_pd_head; 1621 uint8_t mlxi_alloc_pd_rsvd[8]; 1622 } mlxcx_cmd_alloc_pd_in_t; 1623 1624 typedef struct { 1625 mlxcx_cmd_out_t mlxo_alloc_pd_head; 1626 uint8_t mlxo_alloc_pd_rsvd; 1627 uint24be_t mlxo_alloc_pd_pdn; 1628 uint8_t mlxo_alloc_pd_rsvd2[4]; 1629 } mlxcx_cmd_alloc_pd_out_t; 1630 1631 typedef struct { 1632 mlxcx_cmd_in_t mlxi_dealloc_pd_head; 1633 uint8_t mlxi_dealloc_pd_rsvd; 1634 uint24be_t mlxi_dealloc_pd_pdn; 1635 uint8_t mlxi_dealloc_pd_rsvd2[4]; 1636 } mlxcx_cmd_dealloc_pd_in_t; 1637 1638 typedef struct { 1639 mlxcx_cmd_out_t mlxo_dealloc_pd_head; 1640 uint8_t mlxo_dealloc_pd_rsvd[8]; 1641 } mlxcx_cmd_dealloc_pd_out_t; 1642 1643 typedef struct { 1644 mlxcx_cmd_in_t mlxi_alloc_tdom_head; 1645 uint8_t mlxi_alloc_tdom_rsvd[8]; 1646 } mlxcx_cmd_alloc_tdom_in_t; 1647 1648 typedef struct { 1649 mlxcx_cmd_out_t mlxo_alloc_tdom_head; 1650 uint8_t mlxo_alloc_tdom_rsvd; 1651 uint24be_t mlxo_alloc_tdom_tdomn; 1652 uint8_t mlxo_alloc_tdom_rsvd2[4]; 1653 } mlxcx_cmd_alloc_tdom_out_t; 1654 1655 typedef struct { 1656 mlxcx_cmd_in_t mlxi_dealloc_tdom_head; 1657 uint8_t mlxi_dealloc_tdom_rsvd; 1658 uint24be_t mlxi_dealloc_tdom_tdomn; 1659 uint8_t mlxi_dealloc_tdom_rsvd2[4]; 1660 } mlxcx_cmd_dealloc_tdom_in_t; 1661 1662 typedef struct { 1663 mlxcx_cmd_out_t mlxo_dealloc_tdom_head; 1664 uint8_t mlxo_dealloc_tdom_rsvd[8]; 1665 } mlxcx_cmd_dealloc_tdom_out_t; 1666 1667 typedef struct { 1668 mlxcx_cmd_in_t mlxi_create_tir_head; 1669 uint8_t mlxi_create_tir_rsvd[24]; 1670 mlxcx_tir_ctx_t mlxi_create_tir_context; 1671 } mlxcx_cmd_create_tir_in_t; 1672 1673 typedef struct { 1674 mlxcx_cmd_out_t mlxo_create_tir_head; 1675 uint8_t mlxo_create_tir_rsvd; 1676 uint24be_t mlxo_create_tir_tirn; 1677 uint8_t mlxo_create_tir_rsvd2[4]; 1678 } mlxcx_cmd_create_tir_out_t; 1679 1680 typedef struct { 1681 mlxcx_cmd_in_t mlxi_destroy_tir_head; 1682 uint8_t mlxi_destroy_tir_rsvd; 1683 uint24be_t mlxi_destroy_tir_tirn; 1684 uint8_t mlxi_destroy_tir_rsvd2[4]; 1685 } mlxcx_cmd_destroy_tir_in_t; 1686 1687 typedef struct { 1688 mlxcx_cmd_out_t mlxo_destroy_tir_head; 1689 uint8_t mlxo_destroy_tir_rsvd[8]; 1690 } mlxcx_cmd_destroy_tir_out_t; 1691 1692 typedef struct { 1693 mlxcx_cmd_in_t mlxi_create_tis_head; 1694 uint8_t mlxi_create_tis_rsvd[24]; 1695 mlxcx_tis_ctx_t mlxi_create_tis_context; 1696 } mlxcx_cmd_create_tis_in_t; 1697 1698 typedef struct { 1699 mlxcx_cmd_out_t mlxo_create_tis_head; 1700 uint8_t mlxo_create_tis_rsvd; 1701 uint24be_t mlxo_create_tis_tisn; 1702 uint8_t mlxo_create_tis_rsvd2[4]; 1703 } mlxcx_cmd_create_tis_out_t; 1704 1705 typedef struct { 1706 mlxcx_cmd_in_t mlxi_destroy_tis_head; 1707 uint8_t mlxi_destroy_tis_rsvd; 1708 uint24be_t mlxi_destroy_tis_tisn; 1709 uint8_t mlxi_destroy_tis_rsvd2[4]; 1710 } mlxcx_cmd_destroy_tis_in_t; 1711 1712 typedef struct { 1713 mlxcx_cmd_out_t mlxo_destroy_tis_head; 1714 uint8_t mlxo_destroy_tis_rsvd[8]; 1715 } mlxcx_cmd_destroy_tis_out_t; 1716 1717 typedef struct { 1718 mlxcx_cmd_in_t mlxi_query_special_ctxs_head; 1719 uint8_t mlxi_query_special_ctxs_rsvd[8]; 1720 } mlxcx_cmd_query_special_ctxs_in_t; 1721 1722 typedef struct { 1723 mlxcx_cmd_out_t mlxo_query_special_ctxs_head; 1724 uint8_t mlxo_query_special_ctxs_rsvd[4]; 1725 uint32be_t mlxo_query_special_ctxs_resd_lkey; 1726 uint32be_t mlxo_query_special_ctxs_null_mkey; 1727 uint8_t mlxo_query_special_ctxs_rsvd2[12]; 1728 } mlxcx_cmd_query_special_ctxs_out_t; 1729 1730 typedef enum { 1731 MLXCX_VPORT_TYPE_VNIC = 0x0, 1732 MLXCX_VPORT_TYPE_ESWITCH = 0x1, 1733 MLXCX_VPORT_TYPE_UPLINK = 0x2, 1734 } mlxcx_cmd_vport_op_mod_t; 1735 1736 typedef struct { 1737 mlxcx_cmd_in_t mlxi_query_nic_vport_ctx_head; 1738 uint8_t mlxi_query_nic_vport_ctx_other_vport; 1739 uint8_t mlxi_query_nic_vport_ctx_rsvd[1]; 1740 uint16be_t mlxi_query_nic_vport_ctx_vport_number; 1741 uint8_t mlxi_query_nic_vport_ctx_allowed_list_type; 1742 uint8_t mlxi_query_nic_vport_ctx_rsvd2[3]; 1743 } mlxcx_cmd_query_nic_vport_ctx_in_t; 1744 1745 typedef struct { 1746 mlxcx_cmd_out_t mlxo_query_nic_vport_ctx_head; 1747 uint8_t mlxo_query_nic_vport_ctx_rsvd[8]; 1748 mlxcx_nic_vport_ctx_t mlxo_query_nic_vport_ctx_context; 1749 } mlxcx_cmd_query_nic_vport_ctx_out_t; 1750 1751 typedef enum { 1752 MLXCX_MODIFY_NIC_VPORT_CTX_ROCE_EN = 1 << 1, 1753 MLXCX_MODIFY_NIC_VPORT_CTX_ADDR_LIST = 1 << 2, 1754 MLXCX_MODIFY_NIC_VPORT_CTX_PERM_ADDR = 1 << 3, 1755 MLXCX_MODIFY_NIC_VPORT_CTX_PROMISC = 1 << 4, 1756 MLXCX_MODIFY_NIC_VPORT_CTX_EVENT = 1 << 5, 1757 MLXCX_MODIFY_NIC_VPORT_CTX_MTU = 1 << 6, 1758 MLXCX_MODIFY_NIC_VPORT_CTX_WQE_INLINE = 1 << 7, 1759 MLXCX_MODIFY_NIC_VPORT_CTX_PORT_GUID = 1 << 8, 1760 MLXCX_MODIFY_NIC_VPORT_CTX_NODE_GUID = 1 << 9, 1761 } mlxcx_modify_nic_vport_ctx_fields_t; 1762 1763 typedef struct { 1764 mlxcx_cmd_in_t mlxi_modify_nic_vport_ctx_head; 1765 uint8_t mlxi_modify_nic_vport_ctx_other_vport; 1766 uint8_t mlxi_modify_nic_vport_ctx_rsvd[1]; 1767 uint16be_t mlxi_modify_nic_vport_ctx_vport_number; 1768 uint32be_t mlxi_modify_nic_vport_ctx_field_select; 1769 uint8_t mlxi_modify_nic_vport_ctx_rsvd2[240]; 1770 mlxcx_nic_vport_ctx_t mlxi_modify_nic_vport_ctx_context; 1771 } mlxcx_cmd_modify_nic_vport_ctx_in_t; 1772 1773 typedef struct { 1774 mlxcx_cmd_out_t mlxo_modify_nic_vport_ctx_head; 1775 uint8_t mlxo_modify_nic_vport_ctx_rsvd[8]; 1776 } mlxcx_cmd_modify_nic_vport_ctx_out_t; 1777 1778 typedef struct { 1779 mlxcx_cmd_in_t mlxi_query_vport_state_head; 1780 uint8_t mlxi_query_vport_state_other_vport; 1781 uint8_t mlxi_query_vport_state_rsvd[1]; 1782 uint16be_t mlxi_query_vport_state_vport_number; 1783 uint8_t mlxi_query_vport_state_rsvd2[4]; 1784 } mlxcx_cmd_query_vport_state_in_t; 1785 1786 /* CSTYLED */ 1787 #define MLXCX_VPORT_ADMIN_STATE (bitdef_t){4, 0xF0} 1788 /* CSTYLED */ 1789 #define MLXCX_VPORT_OPER_STATE (bitdef_t){0, 0x0F} 1790 1791 typedef enum { 1792 MLXCX_VPORT_OPER_STATE_DOWN = 0x0, 1793 MLXCX_VPORT_OPER_STATE_UP = 0x1, 1794 } mlxcx_vport_oper_state_t; 1795 1796 typedef enum { 1797 MLXCX_VPORT_ADMIN_STATE_DOWN = 0x0, 1798 MLXCX_VPORT_ADMIN_STATE_UP = 0x1, 1799 MLXCX_VPORT_ADMIN_STATE_FOLLOW = 0x2, 1800 } mlxcx_vport_admin_state_t; 1801 1802 typedef struct { 1803 mlxcx_cmd_out_t mlxo_query_vport_state_head; 1804 uint8_t mlxo_query_vport_state_rsvd[4]; 1805 uint16be_t mlxo_query_vport_state_max_tx_speed; 1806 uint8_t mlxo_query_vport_state_rsvd2[1]; 1807 uint8_t mlxo_query_vport_state_state; 1808 } mlxcx_cmd_query_vport_state_out_t; 1809 1810 typedef struct { 1811 mlxcx_cmd_in_t mlxi_create_cq_head; 1812 uint8_t mlxi_create_cq_rsvd[8]; 1813 mlxcx_completionq_ctx_t mlxi_create_cq_context; 1814 uint8_t mlxi_create_cq_rsvd2[192]; 1815 uint64be_t mlxi_create_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1816 } mlxcx_cmd_create_cq_in_t; 1817 1818 typedef struct { 1819 mlxcx_cmd_out_t mlxo_create_cq_head; 1820 uint8_t mlxo_create_cq_rsvd; 1821 uint24be_t mlxo_create_cq_cqn; 1822 uint8_t mlxo_create_cq_rsvd2[4]; 1823 } mlxcx_cmd_create_cq_out_t; 1824 1825 typedef struct { 1826 mlxcx_cmd_in_t mlxi_destroy_cq_head; 1827 uint8_t mlxi_destroy_cq_rsvd; 1828 uint24be_t mlxi_destroy_cq_cqn; 1829 uint8_t mlxi_destroy_cq_rsvd2[4]; 1830 } mlxcx_cmd_destroy_cq_in_t; 1831 1832 typedef struct { 1833 mlxcx_cmd_out_t mlxo_destroy_cq_head; 1834 uint8_t mlxo_destroy_cq_rsvd[8]; 1835 } mlxcx_cmd_destroy_cq_out_t; 1836 1837 typedef struct { 1838 mlxcx_cmd_in_t mlxi_query_cq_head; 1839 uint8_t mlxi_query_cq_rsvd; 1840 uint24be_t mlxi_query_cq_cqn; 1841 uint8_t mlxi_query_cq_rsvd2[4]; 1842 } mlxcx_cmd_query_cq_in_t; 1843 1844 typedef struct { 1845 mlxcx_cmd_out_t mlxo_query_cq_head; 1846 uint8_t mlxo_query_cq_rsvd[8]; 1847 mlxcx_completionq_ctx_t mlxo_query_cq_context; 1848 uint8_t mlxo_query_cq_rsvd2[192]; 1849 uint64be_t mlxo_query_cq_pas[MLXCX_CREATE_QUEUE_MAX_PAGES]; 1850 } mlxcx_cmd_query_cq_out_t; 1851 1852 typedef struct { 1853 mlxcx_cmd_in_t mlxi_create_rq_head; 1854 uint8_t mlxi_create_rq_rsvd[24]; 1855 mlxcx_rq_ctx_t mlxi_create_rq_context; 1856 } mlxcx_cmd_create_rq_in_t; 1857 1858 typedef struct { 1859 mlxcx_cmd_out_t mlxo_create_rq_head; 1860 uint8_t mlxo_create_rq_rsvd; 1861 uint24be_t mlxo_create_rq_rqn; 1862 uint8_t mlxo_create_rq_rsvd2[4]; 1863 } mlxcx_cmd_create_rq_out_t; 1864 1865 /* CSTYLED */ 1866 #define MLXCX_CMD_MODIFY_RQ_STATE (bitdef_t){ \ 1867 .bit_shift = 4, .bit_mask = 0xF0 } 1868 1869 typedef enum { 1870 MLXCX_MODIFY_RQ_SCATTER_FCS = 1 << 2, 1871 MLXCX_MODIFY_RQ_VSD = 1 << 1, 1872 MLXCX_MODIFY_RQ_COUNTER_SET_ID = 1 << 3, 1873 MLXCX_MODIFY_RQ_LWM = 1 << 0 1874 } mlxcx_cmd_modify_rq_bitmask_t; 1875 1876 typedef enum { 1877 MLXCX_RQ_STATE_RST = 0x0, 1878 MLXCX_RQ_STATE_RDY = 0x1, 1879 MLXCX_RQ_STATE_ERR = 0x3 1880 } mlxcx_rq_state_t; 1881 1882 typedef struct { 1883 mlxcx_cmd_in_t mlxi_modify_rq_head; 1884 bits8_t mlxi_modify_rq_state; 1885 uint24be_t mlxi_modify_rq_rqn; 1886 uint8_t mlxi_modify_rq_rsvd[4]; 1887 uint64be_t mlxi_modify_rq_bitmask; 1888 uint8_t mlxi_modify_rq_rsvd2[8]; 1889 mlxcx_rq_ctx_t mlxi_modify_rq_context; 1890 } mlxcx_cmd_modify_rq_in_t; 1891 1892 typedef struct { 1893 mlxcx_cmd_out_t mlxo_modify_rq_head; 1894 uint8_t mlxo_modify_rq_rsvd[8]; 1895 } mlxcx_cmd_modify_rq_out_t; 1896 1897 typedef struct { 1898 mlxcx_cmd_in_t mlxi_query_rq_head; 1899 uint8_t mlxi_query_rq_rsvd; 1900 uint24be_t mlxi_query_rq_rqn; 1901 uint8_t mlxi_query_rq_rsvd2[4]; 1902 } mlxcx_cmd_query_rq_in_t; 1903 1904 typedef struct { 1905 mlxcx_cmd_out_t mlxo_query_rq_head; 1906 uint8_t mlxo_query_rq_rsvd[24]; 1907 mlxcx_rq_ctx_t mlxo_query_rq_context; 1908 } mlxcx_cmd_query_rq_out_t; 1909 1910 typedef struct { 1911 mlxcx_cmd_in_t mlxi_destroy_rq_head; 1912 uint8_t mlxi_destroy_rq_rsvd; 1913 uint24be_t mlxi_destroy_rq_rqn; 1914 uint8_t mlxi_destroy_rq_rsvd2[4]; 1915 } mlxcx_cmd_destroy_rq_in_t; 1916 1917 typedef struct { 1918 mlxcx_cmd_out_t mlxo_destroy_rq_head; 1919 uint8_t mlxo_destroy_rq_rsvd[8]; 1920 } mlxcx_cmd_destroy_rq_out_t; 1921 1922 typedef struct { 1923 mlxcx_cmd_in_t mlxi_create_sq_head; 1924 uint8_t mlxi_create_sq_rsvd[24]; 1925 mlxcx_sq_ctx_t mlxi_create_sq_context; 1926 } mlxcx_cmd_create_sq_in_t; 1927 1928 typedef struct { 1929 mlxcx_cmd_out_t mlxo_create_sq_head; 1930 uint8_t mlxo_create_sq_rsvd; 1931 uint24be_t mlxo_create_sq_sqn; 1932 uint8_t mlxo_create_sq_rsvd2[4]; 1933 } mlxcx_cmd_create_sq_out_t; 1934 1935 /* CSTYLED */ 1936 #define MLXCX_CMD_MODIFY_SQ_STATE (bitdef_t){ \ 1937 .bit_shift = 4, .bit_mask = 0xF0 } 1938 1939 typedef enum { 1940 MLXCX_MODIFY_SQ_PACKET_PACING_INDEX = 1 << 0, 1941 } mlxcx_cmd_modify_sq_bitmask_t; 1942 1943 typedef enum { 1944 MLXCX_SQ_STATE_RST = 0x0, 1945 MLXCX_SQ_STATE_RDY = 0x1, 1946 MLXCX_SQ_STATE_ERR = 0x3 1947 } mlxcx_sq_state_t; 1948 1949 typedef struct { 1950 mlxcx_cmd_in_t mlxi_modify_sq_head; 1951 bits8_t mlxi_modify_sq_state; 1952 uint24be_t mlxi_modify_sq_sqn; 1953 uint8_t mlxi_modify_sq_rsvd[4]; 1954 uint64be_t mlxi_modify_sq_bitmask; 1955 uint8_t mlxi_modify_sq_rsvd2[8]; 1956 mlxcx_sq_ctx_t mlxi_modify_sq_context; 1957 } mlxcx_cmd_modify_sq_in_t; 1958 1959 typedef struct { 1960 mlxcx_cmd_out_t mlxo_modify_sq_head; 1961 uint8_t mlxo_modify_sq_rsvd[8]; 1962 } mlxcx_cmd_modify_sq_out_t; 1963 1964 typedef struct { 1965 mlxcx_cmd_in_t mlxi_query_sq_head; 1966 uint8_t mlxi_query_sq_rsvd; 1967 uint24be_t mlxi_query_sq_sqn; 1968 uint8_t mlxi_query_sq_rsvd2[4]; 1969 } mlxcx_cmd_query_sq_in_t; 1970 1971 typedef struct { 1972 mlxcx_cmd_out_t mlxo_query_sq_head; 1973 uint8_t mlxo_query_sq_rsvd[24]; 1974 mlxcx_sq_ctx_t mlxo_query_sq_context; 1975 } mlxcx_cmd_query_sq_out_t; 1976 1977 typedef struct { 1978 mlxcx_cmd_in_t mlxi_destroy_sq_head; 1979 uint8_t mlxi_destroy_sq_rsvd; 1980 uint24be_t mlxi_destroy_sq_sqn; 1981 uint8_t mlxi_destroy_sq_rsvd2[4]; 1982 } mlxcx_cmd_destroy_sq_in_t; 1983 1984 typedef struct { 1985 mlxcx_cmd_out_t mlxo_destroy_sq_head; 1986 uint8_t mlxo_destroy_sq_rsvd[8]; 1987 } mlxcx_cmd_destroy_sq_out_t; 1988 1989 typedef struct { 1990 mlxcx_cmd_in_t mlxi_create_rqt_head; 1991 uint8_t mlxi_create_rqt_rsvd[24]; 1992 mlxcx_rqtable_ctx_t mlxi_create_rqt_context; 1993 } mlxcx_cmd_create_rqt_in_t; 1994 1995 typedef struct { 1996 mlxcx_cmd_out_t mlxo_create_rqt_head; 1997 uint8_t mlxo_create_rqt_rsvd; 1998 uint24be_t mlxo_create_rqt_rqtn; 1999 uint8_t mlxo_create_rqt_rsvd2[4]; 2000 } mlxcx_cmd_create_rqt_out_t; 2001 2002 typedef struct { 2003 mlxcx_cmd_in_t mlxi_destroy_rqt_head; 2004 uint8_t mlxi_destroy_rqt_rsvd; 2005 uint24be_t mlxi_destroy_rqt_rqtn; 2006 uint8_t mlxi_destroy_rqt_rsvd2[4]; 2007 } mlxcx_cmd_destroy_rqt_in_t; 2008 2009 typedef struct { 2010 mlxcx_cmd_out_t mlxo_destroy_rqt_head; 2011 uint8_t mlxo_destroy_rqt_rsvd[8]; 2012 } mlxcx_cmd_destroy_rqt_out_t; 2013 2014 typedef enum { 2015 MLXCX_FLOW_TABLE_NIC_RX = 0x0, 2016 MLXCX_FLOW_TABLE_NIC_TX = 0x1, 2017 MLXCX_FLOW_TABLE_ESW_OUT = 0x2, 2018 MLXCX_FLOW_TABLE_ESW_IN = 0x3, 2019 MLXCX_FLOW_TABLE_ESW_FDB = 0x4, 2020 MLXCX_FLOW_TABLE_NIC_RX_SNIFF = 0x5, 2021 MLXCX_FLOW_TABLE_NIC_TX_SNIFF = 0x6, 2022 MLXCX_FLOW_TABLE_NIC_RX_RDMA = 0x7, 2023 MLXCX_FLOW_TABLE_NIC_TX_RDMA = 0x8 2024 } mlxcx_flow_table_type_t; 2025 2026 typedef struct { 2027 mlxcx_cmd_in_t mlxi_create_flow_table_head; 2028 uint8_t mlxi_create_flow_table_other_vport; 2029 uint8_t mlxi_create_flow_table_rsvd; 2030 uint16be_t mlxi_create_flow_table_vport_number; 2031 uint8_t mlxi_create_flow_table_rsvd2[4]; 2032 uint8_t mlxi_create_flow_table_table_type; 2033 uint8_t mlxi_create_flow_table_rsvd3[7]; 2034 mlxcx_flow_table_ctx_t mlxi_create_flow_table_context; 2035 } mlxcx_cmd_create_flow_table_in_t; 2036 2037 typedef struct { 2038 mlxcx_cmd_out_t mlxo_create_flow_table_head; 2039 uint8_t mlxo_create_flow_table_rsvd; 2040 uint24be_t mlxo_create_flow_table_table_id; 2041 uint8_t mlxo_create_flow_table_rsvd2[4]; 2042 } mlxcx_cmd_create_flow_table_out_t; 2043 2044 typedef struct { 2045 mlxcx_cmd_in_t mlxi_destroy_flow_table_head; 2046 uint8_t mlxi_destroy_flow_table_other_vport; 2047 uint8_t mlxi_destroy_flow_table_rsvd; 2048 uint16be_t mlxi_destroy_flow_table_vport_number; 2049 uint8_t mlxi_destroy_flow_table_rsvd2[4]; 2050 uint8_t mlxi_destroy_flow_table_table_type; 2051 uint8_t mlxi_destroy_flow_table_rsvd3[4]; 2052 uint24be_t mlxi_destroy_flow_table_table_id; 2053 uint8_t mlxi_destroy_flow_table_rsvd4[4]; 2054 } mlxcx_cmd_destroy_flow_table_in_t; 2055 2056 typedef struct { 2057 mlxcx_cmd_out_t mlxo_destroy_flow_table_head; 2058 uint8_t mlxo_destroy_flow_table_rsvd[8]; 2059 } mlxcx_cmd_destroy_flow_table_out_t; 2060 2061 typedef struct { 2062 mlxcx_cmd_in_t mlxi_set_flow_table_root_head; 2063 uint8_t mlxi_set_flow_table_root_other_vport; 2064 uint8_t mlxi_set_flow_table_root_rsvd; 2065 uint16be_t mlxi_set_flow_table_root_vport_number; 2066 uint8_t mlxi_set_flow_table_root_rsvd2[4]; 2067 uint8_t mlxi_set_flow_table_root_table_type; 2068 uint8_t mlxi_set_flow_table_root_rsvd3[4]; 2069 uint24be_t mlxi_set_flow_table_root_table_id; 2070 uint8_t mlxi_set_flow_table_root_rsvd4[4]; 2071 } mlxcx_cmd_set_flow_table_root_in_t; 2072 2073 typedef struct { 2074 mlxcx_cmd_out_t mlxo_set_flow_table_root_head; 2075 uint8_t mlxo_set_flow_table_root_rsvd[8]; 2076 } mlxcx_cmd_set_flow_table_root_out_t; 2077 2078 typedef enum { 2079 MLXCX_FLOW_GROUP_MATCH_OUTER_HDRS = 1 << 0, 2080 MLXCX_FLOW_GROUP_MATCH_MISC_PARAMS = 1 << 1, 2081 MLXCX_FLOW_GROUP_MATCH_INNER_HDRS = 1 << 2, 2082 } mlxcx_flow_group_match_criteria_t; 2083 2084 typedef struct { 2085 mlxcx_cmd_in_t mlxi_create_flow_group_head; 2086 uint8_t mlxi_create_flow_group_other_vport; 2087 uint8_t mlxi_create_flow_group_rsvd; 2088 uint16be_t mlxi_create_flow_group_vport_number; 2089 uint8_t mlxi_create_flow_group_rsvd2[4]; 2090 uint8_t mlxi_create_flow_group_table_type; 2091 uint8_t mlxi_create_flow_group_rsvd3[4]; 2092 uint24be_t mlxi_create_flow_group_table_id; 2093 uint8_t mlxi_create_flow_group_rsvd4[4]; 2094 uint32be_t mlxi_create_flow_group_start_flow_index; 2095 uint8_t mlxi_create_flow_group_rsvd5[4]; 2096 uint32be_t mlxi_create_flow_group_end_flow_index; 2097 uint8_t mlxi_create_flow_group_rsvd6[23]; 2098 uint8_t mlxi_create_flow_group_match_criteria_en; 2099 mlxcx_flow_match_t mlxi_create_flow_group_match_criteria; 2100 uint8_t mlxi_create_flow_group_rsvd7[448]; 2101 } mlxcx_cmd_create_flow_group_in_t; 2102 2103 typedef struct { 2104 mlxcx_cmd_out_t mlxo_create_flow_group_head; 2105 uint8_t mlxo_create_flow_group_rsvd; 2106 uint24be_t mlxo_create_flow_group_group_id; 2107 uint8_t mlxo_create_flow_group_rsvd2[4]; 2108 } mlxcx_cmd_create_flow_group_out_t; 2109 2110 typedef struct { 2111 mlxcx_cmd_in_t mlxi_destroy_flow_group_head; 2112 uint8_t mlxi_destroy_flow_group_other_vport; 2113 uint8_t mlxi_destroy_flow_group_rsvd; 2114 uint16be_t mlxi_destroy_flow_group_vport_number; 2115 uint8_t mlxi_destroy_flow_group_rsvd2[4]; 2116 uint8_t mlxi_destroy_flow_group_table_type; 2117 uint8_t mlxi_destroy_flow_group_rsvd3[4]; 2118 uint24be_t mlxi_destroy_flow_group_table_id; 2119 uint32be_t mlxi_destroy_flow_group_group_id; 2120 uint8_t mlxi_destroy_flow_group_rsvd4[36]; 2121 } mlxcx_cmd_destroy_flow_group_in_t; 2122 2123 typedef struct { 2124 mlxcx_cmd_out_t mlxo_destroy_flow_group_head; 2125 uint8_t mlxo_destroy_flow_group_rsvd[8]; 2126 } mlxcx_cmd_destroy_flow_group_out_t; 2127 2128 typedef enum { 2129 MLXCX_CMD_FLOW_ENTRY_SET_NEW = 0, 2130 MLXCX_CMD_FLOW_ENTRY_MODIFY = 1, 2131 } mlxcx_cmd_set_flow_table_entry_opmod_t; 2132 2133 typedef enum { 2134 MLXCX_CMD_FLOW_ENTRY_SET_ACTION = 1 << 0, 2135 MLXCX_CMD_FLOW_ENTRY_SET_FLOW_TAG = 1 << 1, 2136 MLXCX_CMD_FLOW_ENTRY_SET_DESTINATION = 1 << 2, 2137 MLXCX_CMD_FLOW_ENTRY_SET_COUNTERS = 1 << 3, 2138 MLXCX_CMD_FLOW_ENTRY_SET_ENCAP = 1 << 4 2139 } mlxcx_cmd_set_flow_table_entry_bitmask_t; 2140 2141 typedef struct { 2142 mlxcx_cmd_in_t mlxi_set_flow_table_entry_head; 2143 uint8_t mlxi_set_flow_table_entry_other_vport; 2144 uint8_t mlxi_set_flow_table_entry_rsvd; 2145 uint16be_t mlxi_set_flow_table_entry_vport_number; 2146 uint8_t mlxi_set_flow_table_entry_rsvd2[4]; 2147 uint8_t mlxi_set_flow_table_entry_table_type; 2148 uint8_t mlxi_set_flow_table_entry_rsvd3[4]; 2149 uint24be_t mlxi_set_flow_table_entry_table_id; 2150 uint8_t mlxi_set_flow_table_entry_rsvd4[3]; 2151 bits8_t mlxi_set_flow_table_entry_modify_bitmask; 2152 uint8_t mlxi_set_flow_table_entry_rsvd5[4]; 2153 uint32be_t mlxi_set_flow_table_entry_flow_index; 2154 uint8_t mlxi_set_flow_table_entry_rsvd6[28]; 2155 mlxcx_flow_entry_ctx_t mlxi_set_flow_table_entry_context; 2156 } mlxcx_cmd_set_flow_table_entry_in_t; 2157 2158 typedef struct { 2159 mlxcx_cmd_out_t mlxo_set_flow_table_entry_head; 2160 uint8_t mlxo_set_flow_table_entry_rsvd[8]; 2161 } mlxcx_cmd_set_flow_table_entry_out_t; 2162 2163 typedef struct { 2164 mlxcx_cmd_in_t mlxi_delete_flow_table_entry_head; 2165 uint8_t mlxi_delete_flow_table_entry_other_vport; 2166 uint8_t mlxi_delete_flow_table_entry_rsvd; 2167 uint16be_t mlxi_delete_flow_table_entry_vport_number; 2168 uint8_t mlxi_delete_flow_table_entry_rsvd2[4]; 2169 uint8_t mlxi_delete_flow_table_entry_table_type; 2170 uint8_t mlxi_delete_flow_table_entry_rsvd3[4]; 2171 uint24be_t mlxi_delete_flow_table_entry_table_id; 2172 uint8_t mlxi_delete_flow_table_entry_rsvd4[8]; 2173 uint32be_t mlxi_delete_flow_table_entry_flow_index; 2174 uint8_t mlxi_delete_flow_table_entry_rsvd5[28]; 2175 } mlxcx_cmd_delete_flow_table_entry_in_t; 2176 2177 typedef struct { 2178 mlxcx_cmd_out_t mlxo_delete_flow_table_entry_head; 2179 uint8_t mlxo_delete_flow_table_entry_rsvd[8]; 2180 } mlxcx_cmd_delete_flow_table_entry_out_t; 2181 2182 typedef enum { 2183 MLXCX_CMD_CONFIG_INT_MOD_READ = 1, 2184 MLXCX_CMD_CONFIG_INT_MOD_WRITE = 0 2185 } mlxcx_cmd_config_int_mod_opmod_t; 2186 2187 typedef struct { 2188 mlxcx_cmd_in_t mlxi_config_int_mod_head; 2189 uint16be_t mlxi_config_int_mod_min_delay; 2190 uint16be_t mlxi_config_int_mod_int_vector; 2191 uint8_t mlxi_config_int_mod_rsvd[4]; 2192 } mlxcx_cmd_config_int_mod_in_t; 2193 2194 typedef struct { 2195 mlxcx_cmd_out_t mlxo_config_int_mod_head; 2196 uint16be_t mlxo_config_int_mod_min_delay; 2197 uint16be_t mlxo_config_int_mod_int_vector; 2198 uint8_t mlxo_config_int_mod_rsvd[4]; 2199 } mlxcx_cmd_config_int_mod_out_t; 2200 2201 typedef struct { 2202 uint8_t mlrd_pmtu_rsvd; 2203 uint8_t mlrd_pmtu_local_port; 2204 uint8_t mlrd_pmtu_rsvd2[2]; 2205 2206 uint16be_t mlrd_pmtu_max_mtu; 2207 uint8_t mlrd_pmtu_rsvd3[2]; 2208 2209 uint16be_t mlrd_pmtu_admin_mtu; 2210 uint8_t mlrd_pmtu_rsvd4[2]; 2211 2212 uint16be_t mlrd_pmtu_oper_mtu; 2213 uint8_t mlrd_pmtu_rsvd5[2]; 2214 } mlxcx_reg_pmtu_t; 2215 2216 typedef enum { 2217 MLXCX_PORT_STATUS_UP = 1, 2218 MLXCX_PORT_STATUS_DOWN = 2, 2219 MLXCX_PORT_STATUS_UP_ONCE = 3, 2220 MLXCX_PORT_STATUS_DISABLED = 4, 2221 } mlxcx_port_status_t; 2222 2223 typedef enum { 2224 MLXCX_PAOS_ADMIN_ST_EN = 1UL << 31, 2225 } mlxcx_paos_flags_t; 2226 2227 typedef struct { 2228 uint8_t mlrd_paos_swid; 2229 uint8_t mlrd_paos_local_port; 2230 uint8_t mlrd_paos_admin_status; 2231 uint8_t mlrd_paos_oper_status; 2232 bits32_t mlrd_paos_flags; 2233 uint8_t mlrd_paos_rsvd[8]; 2234 } mlxcx_reg_paos_t; 2235 2236 typedef enum { 2237 MLXCX_PROTO_SGMII = 1 << 0, 2238 MLXCX_PROTO_1000BASE_KX = 1 << 1, 2239 MLXCX_PROTO_10GBASE_CX4 = 1 << 2, 2240 MLXCX_PROTO_10GBASE_KX4 = 1 << 3, 2241 MLXCX_PROTO_10GBASE_KR = 1 << 4, 2242 MLXCX_PROTO_UNKNOWN_1 = 1 << 5, 2243 MLXCX_PROTO_40GBASE_CR4 = 1 << 6, 2244 MLXCX_PROTO_40GBASE_KR4 = 1 << 7, 2245 MLXCX_PROTO_UNKNOWN_2 = 1 << 8, 2246 MLXCX_PROTO_SGMII_100BASE = 1 << 9, 2247 MLXCX_PROTO_UNKNOWN_3 = 1 << 10, 2248 MLXCX_PROTO_UNKNOWN_4 = 1 << 11, 2249 MLXCX_PROTO_10GBASE_CR = 1 << 12, 2250 MLXCX_PROTO_10GBASE_SR = 1 << 13, 2251 MLXCX_PROTO_10GBASE_ER_LR = 1 << 14, 2252 MLXCX_PROTO_40GBASE_SR4 = 1 << 15, 2253 MLXCX_PROTO_40GBASE_LR4_ER4 = 1 << 16, 2254 MLXCX_PROTO_UNKNOWN_5 = 1 << 17, 2255 MLXCX_PROTO_50GBASE_SR2 = 1 << 18, 2256 MLXCX_PROTO_UNKNOWN_6 = 1 << 19, 2257 MLXCX_PROTO_100GBASE_CR4 = 1 << 20, 2258 MLXCX_PROTO_100GBASE_SR4 = 1 << 21, 2259 MLXCX_PROTO_100GBASE_KR4 = 1 << 22, 2260 MLXCX_PROTO_UNKNOWN_7 = 1 << 23, 2261 MLXCX_PROTO_UNKNOWN_8 = 1 << 24, 2262 MLXCX_PROTO_UNKNOWN_9 = 1 << 25, 2263 MLXCX_PROTO_UNKNOWN_10 = 1 << 26, 2264 MLXCX_PROTO_25GBASE_CR = 1 << 27, 2265 MLXCX_PROTO_25GBASE_KR = 1 << 28, 2266 MLXCX_PROTO_25GBASE_SR = 1 << 29, 2267 MLXCX_PROTO_50GBASE_CR2 = 1 << 30, 2268 MLXCX_PROTO_50GBASE_KR2 = 1UL << 31, 2269 } mlxcx_eth_proto_t; 2270 2271 #define MLXCX_PROTO_100M MLXCX_PROTO_SGMII_100BASE 2272 2273 #define MLXCX_PROTO_1G (MLXCX_PROTO_1000BASE_KX | MLXCX_PROTO_SGMII) 2274 2275 #define MLXCX_PROTO_10G (MLXCX_PROTO_10GBASE_CX4 | \ 2276 MLXCX_PROTO_10GBASE_KX4 | MLXCX_PROTO_10GBASE_KR | \ 2277 MLXCX_PROTO_10GBASE_CR | MLXCX_PROTO_10GBASE_SR | \ 2278 MLXCX_PROTO_10GBASE_ER_LR) 2279 2280 #define MLXCX_PROTO_25G (MLXCX_PROTO_25GBASE_CR | \ 2281 MLXCX_PROTO_25GBASE_KR | MLXCX_PROTO_25GBASE_SR) 2282 2283 #define MLXCX_PROTO_40G (MLXCX_PROTO_40GBASE_SR4 | \ 2284 MLXCX_PROTO_40GBASE_LR4_ER4 | MLXCX_PROTO_40GBASE_CR4 | \ 2285 MLXCX_PROTO_40GBASE_KR4) 2286 2287 #define MLXCX_PROTO_50G (MLXCX_PROTO_50GBASE_CR2 | \ 2288 MLXCX_PROTO_50GBASE_KR2 | MLXCX_PROTO_50GBASE_SR2) 2289 2290 #define MLXCX_PROTO_100G (MLXCX_PROTO_100GBASE_CR4 | \ 2291 MLXCX_PROTO_100GBASE_SR4 | MLXCX_PROTO_100GBASE_KR4) 2292 2293 typedef enum { 2294 MLXCX_AUTONEG_DISABLE_CAP = 1 << 5, 2295 MLXCX_AUTONEG_DISABLE = 1 << 6 2296 } mlxcx_autoneg_flags_t; 2297 2298 typedef enum { 2299 MLXCX_PTYS_PROTO_MASK_IB = 1 << 0, 2300 MLXCX_PTYS_PROTO_MASK_ETH = 1 << 2, 2301 } mlxcx_reg_ptys_proto_mask_t; 2302 2303 typedef struct { 2304 bits8_t mlrd_ptys_autoneg_flags; 2305 uint8_t mlrd_ptys_local_port; 2306 uint8_t mlrd_ptys_rsvd; 2307 bits8_t mlrd_ptys_proto_mask; 2308 2309 bits8_t mlrd_ptys_autoneg_status; 2310 uint8_t mlrd_ptys_rsvd2; 2311 uint16be_t mlrd_ptys_data_rate_oper; 2312 2313 uint8_t mlrd_ptys_rsvd3[4]; 2314 2315 bits32_t mlrd_ptys_proto_cap; 2316 uint8_t mlrd_ptys_rsvd4[8]; 2317 bits32_t mlrd_ptys_proto_admin; 2318 uint8_t mlrd_ptys_rsvd5[8]; 2319 bits32_t mlrd_ptys_proto_oper; 2320 uint8_t mlrd_ptys_rsvd6[8]; 2321 bits32_t mlrd_ptys_proto_partner_advert; 2322 uint8_t mlrd_ptys_rsvd7[12]; 2323 } mlxcx_reg_ptys_t; 2324 2325 typedef enum { 2326 MLXCX_LED_TYPE_BOTH = 0x0, 2327 MLXCX_LED_TYPE_UID = 0x1, 2328 MLXCX_LED_TYPE_PORT = 0x2, 2329 } mlxcx_led_type_t; 2330 2331 #define MLXCX_MLCR_INDIVIDUAL_ONLY (1 << 4) 2332 /* CSTYLED */ 2333 #define MLXCX_MLCR_LED_TYPE (bitdef_t){ 0, 0x0F } 2334 2335 typedef struct { 2336 uint8_t mlrd_mlcr_rsvd; 2337 uint8_t mlrd_mlcr_local_port; 2338 uint8_t mlrd_mlcr_rsvd2; 2339 bits8_t mlrd_mlcr_flags; 2340 uint8_t mlrd_mlcr_rsvd3[2]; 2341 uint16be_t mlrd_mlcr_beacon_duration; 2342 uint8_t mlrd_mlcr_rsvd4[2]; 2343 uint16be_t mlrd_mlcr_beacon_remain; 2344 } mlxcx_reg_mlcr_t; 2345 2346 typedef struct { 2347 uint8_t mlrd_pmaos_rsvd; 2348 uint8_t mlrd_pmaos_module; 2349 uint8_t mlrd_pmaos_admin_status; 2350 uint8_t mlrd_pmaos_oper_status; 2351 bits8_t mlrd_pmaos_flags; 2352 uint8_t mlrd_pmaos_rsvd2; 2353 uint8_t mlrd_pmaos_error_type; 2354 uint8_t mlrd_pmaos_event_en; 2355 uint8_t mlrd_pmaos_rsvd3[8]; 2356 } mlxcx_reg_pmaos_t; 2357 2358 typedef enum { 2359 MLXCX_MCIA_STATUS_OK = 0x0, 2360 MLXCX_MCIA_STATUS_NO_EEPROM = 0x1, 2361 MLXCX_MCIA_STATUS_NOT_SUPPORTED = 0x2, 2362 MLXCX_MCIA_STATUS_NOT_CONNECTED = 0x3, 2363 MLXCX_MCIA_STATUS_I2C_ERROR = 0x9, 2364 MLXCX_MCIA_STATUS_DISABLED = 0x10 2365 } mlxcx_mcia_status_t; 2366 2367 typedef struct { 2368 bits8_t mlrd_mcia_flags; 2369 uint8_t mlrd_mcia_module; 2370 uint8_t mlrd_mcia_rsvd; 2371 uint8_t mlrd_mcia_status; 2372 uint8_t mlrd_mcia_i2c_device_addr; 2373 uint8_t mlrd_mcia_page_number; 2374 uint16be_t mlrd_mcia_device_addr; 2375 uint8_t mlrd_mcia_rsvd2[2]; 2376 uint16be_t mlrd_mcia_size; 2377 uint8_t mlrd_mcia_rsvd3[4]; 2378 uint8_t mlrd_mcia_data[48]; 2379 } mlxcx_reg_mcia_t; 2380 2381 typedef struct { 2382 uint64be_t mlppc_ieee_802_3_frames_tx; 2383 uint64be_t mlppc_ieee_802_3_frames_rx; 2384 uint64be_t mlppc_ieee_802_3_fcs_err; 2385 uint64be_t mlppc_ieee_802_3_align_err; 2386 uint64be_t mlppc_ieee_802_3_bytes_tx; 2387 uint64be_t mlppc_ieee_802_3_bytes_rx; 2388 uint64be_t mlppc_ieee_802_3_mcast_tx; 2389 uint64be_t mlppc_ieee_802_3_bcast_tx; 2390 uint64be_t mlppc_ieee_802_3_mcast_rx; 2391 uint64be_t mlppc_ieee_802_3_bcast_rx; 2392 uint64be_t mlppc_ieee_802_3_in_range_len_err; 2393 uint64be_t mlppc_ieee_802_3_out_of_range_len_err; 2394 uint64be_t mlppc_ieee_802_3_frame_too_long_err; 2395 uint64be_t mlppc_ieee_802_3_symbol_err; 2396 uint64be_t mlppc_ieee_802_3_mac_ctrl_tx; 2397 uint64be_t mlppc_ieee_802_3_mac_ctrl_rx; 2398 uint64be_t mlppc_ieee_802_3_unsup_opcodes_rx; 2399 uint64be_t mlppc_ieee_802_3_pause_rx; 2400 uint64be_t mlppc_ieee_802_3_pause_tx; 2401 } mlxcx_ppcnt_ieee_802_3_t; 2402 2403 typedef struct { 2404 uint64be_t mlppc_rfc_2863_in_octets; 2405 uint64be_t mlppc_rfc_2863_in_ucast_pkts; 2406 uint64be_t mlppc_rfc_2863_in_discards; 2407 uint64be_t mlppc_rfc_2863_in_errors; 2408 uint64be_t mlppc_rfc_2863_in_unknown_protos; 2409 uint64be_t mlppc_rfc_2863_out_octets; 2410 uint64be_t mlppc_rfc_2863_out_ucast_pkts; 2411 uint64be_t mlppc_rfc_2863_out_discards; 2412 uint64be_t mlppc_rfc_2863_out_errors; 2413 uint64be_t mlppc_rfc_2863_in_mcast_pkts; 2414 uint64be_t mlppc_rfc_2863_in_bcast_pkts; 2415 uint64be_t mlppc_rfc_2863_out_mcast_pkts; 2416 uint64be_t mlppc_rfc_2863_out_bcast_pkts; 2417 } mlxcx_ppcnt_rfc_2863_t; 2418 2419 typedef struct { 2420 uint64be_t mlppc_phy_stats_time_since_last_clear; 2421 uint64be_t mlppc_phy_stats_rx_bits; 2422 uint64be_t mlppc_phy_stats_symbol_errs; 2423 uint64be_t mlppc_phy_stats_corrected_bits; 2424 uint8_t mlppc_phy_stats_rsvd[2]; 2425 uint8_t mlppc_phy_stats_raw_ber_mag; 2426 uint8_t mlppc_phy_stats_raw_ber_coef; 2427 uint8_t mlppc_phy_stats_rsvd2[2]; 2428 uint8_t mlppc_phy_stats_eff_ber_mag; 2429 uint8_t mlppc_phy_stats_eff_ber_coef; 2430 } mlxcx_ppcnt_phy_stats_t; 2431 2432 typedef enum { 2433 MLXCX_PPCNT_GRP_IEEE_802_3 = 0x0, 2434 MLXCX_PPCNT_GRP_RFC_2863 = 0x1, 2435 MLXCX_PPCNT_GRP_RFC_2819 = 0x2, 2436 MLXCX_PPCNT_GRP_RFC_3635 = 0x3, 2437 MLXCX_PPCNT_GRP_ETH_EXTD = 0x5, 2438 MLXCX_PPCNT_GRP_ETH_DISCARD = 0x6, 2439 MLXCX_PPCNT_GRP_PER_PRIO = 0x10, 2440 MLXCX_PPCNT_GRP_PER_TC = 0x11, 2441 MLXCX_PPCNT_GRP_PER_TC_CONGEST = 0x13, 2442 MLXCX_PPCNT_GRP_PHY_STATS = 0x16 2443 } mlxcx_ppcnt_grp_t; 2444 2445 typedef enum { 2446 MLXCX_PPCNT_CLEAR = (1 << 7), 2447 MLXCX_PPCNT_NO_CLEAR = 0 2448 } mlxcx_ppcnt_clear_t; 2449 2450 typedef struct { 2451 uint8_t mlrd_ppcnt_swid; 2452 uint8_t mlrd_ppcnt_local_port; 2453 uint8_t mlrd_ppcnt_pnat; 2454 uint8_t mlrd_ppcnt_grp; 2455 uint8_t mlrd_ppcnt_clear; 2456 uint8_t mlrd_ppcnt_rsvd[2]; 2457 uint8_t mlrd_ppcnt_prio_tc; 2458 union { 2459 uint8_t mlrd_ppcnt_data[248]; 2460 mlxcx_ppcnt_ieee_802_3_t mlrd_ppcnt_ieee_802_3; 2461 mlxcx_ppcnt_rfc_2863_t mlrd_ppcnt_rfc_2863; 2462 mlxcx_ppcnt_phy_stats_t mlrd_ppcnt_phy_stats; 2463 }; 2464 } mlxcx_reg_ppcnt_t; 2465 2466 typedef enum { 2467 MLXCX_REG_PMTU = 0x5003, 2468 MLXCX_REG_PTYS = 0x5004, 2469 MLXCX_REG_PAOS = 0x5006, 2470 MLXCX_REG_PMAOS = 0x5012, 2471 MLXCX_REG_MSGI = 0x9021, 2472 MLXCX_REG_MLCR = 0x902B, 2473 MLXCX_REG_MCIA = 0x9014, 2474 MLXCX_REG_PPCNT = 0x5008, 2475 } mlxcx_register_id_t; 2476 2477 typedef union { 2478 mlxcx_reg_pmtu_t mlrd_pmtu; 2479 mlxcx_reg_paos_t mlrd_paos; 2480 mlxcx_reg_ptys_t mlrd_ptys; 2481 mlxcx_reg_mlcr_t mlrd_mlcr; 2482 mlxcx_reg_pmaos_t mlrd_pmaos; 2483 mlxcx_reg_mcia_t mlrd_mcia; 2484 mlxcx_reg_ppcnt_t mlrd_ppcnt; 2485 } mlxcx_register_data_t; 2486 2487 typedef enum { 2488 MLXCX_CMD_ACCESS_REGISTER_READ = 1, 2489 MLXCX_CMD_ACCESS_REGISTER_WRITE = 0 2490 } mlxcx_cmd_reg_opmod_t; 2491 2492 typedef struct { 2493 mlxcx_cmd_in_t mlxi_access_register_head; 2494 uint8_t mlxi_access_register_rsvd[2]; 2495 uint16be_t mlxi_access_register_register_id; 2496 uint32be_t mlxi_access_register_argument; 2497 mlxcx_register_data_t mlxi_access_register_data; 2498 } mlxcx_cmd_access_register_in_t; 2499 2500 typedef struct { 2501 mlxcx_cmd_out_t mlxo_access_register_head; 2502 uint8_t mlxo_access_register_rsvd[8]; 2503 mlxcx_register_data_t mlxo_access_register_data; 2504 } mlxcx_cmd_access_register_out_t; 2505 2506 #pragma pack() 2507 2508 CTASSERT(MLXCX_SQE_MAX_PTRS > 0); 2509 2510 #ifdef __cplusplus 2511 } 2512 #endif 2513 2514 #endif /* _MLXCX_REG_H */ 2515