1 /* 2 * megaraid_sas.h: header for mega_sas 3 * 4 * Solaris MegaRAID driver for SAS controllers 5 * Copyright (c) 2004-2008, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the author nor the names of its contributors may be 19 * used to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 * DAMAGE. 34 */ 35 36 /* 37 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 38 * Use is subject to license terms. 39 */ 40 41 #ifndef _MEGARAID_SAS_H_ 42 #define _MEGARAID_SAS_H_ 43 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 #include <sys/scsi/scsi.h> 50 #include "list.h" 51 52 #pragma pack(1) 53 54 /* 55 * MegaRAID SAS Driver meta data 56 */ 57 #define MEGASAS_VERSION "LSIv1.26" 58 #define MEGASAS_RELDATE "Mar 31, 2008" 59 60 #define MEGASAS_TRUE 1 61 #define MEGASAS_FALSE 0 62 63 /* 64 * MegaRAID device id conversion definitions. 65 */ 66 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT) 67 68 /* 69 * MegaRAID SAS supported controllers 70 */ 71 #define PCI_DEVICE_ID_LSI_1064 0x0411 72 #define PCI_DEVICE_ID_LSI_1078 0x0060 73 #define PCI_DEVICE_ID_LSI_1078DE 0x007C 74 75 #define PCI_DEVICE_ID_DELL_PERC5 0x0015 76 #define PCI_DEVICE_ID_DELL_SAS5 0x0054 77 78 #define PCI_SUBSYSTEM_DELL_PERC5E 0x1F01 79 #define PCI_SUBSYSTEM_DELL_PERC5I 0x1F02 80 #define PCI_SUBSYSTEM_DELL_PERC5I_INTEGRATED 0x1F03 81 #define PCI_SUBSYSTEM_DELL_SAS5I 0x1F05 82 #define PCI_SUBSYSTEM_DELL_SAS5I_INTEGRATED 0x1F06 83 84 #define PCI_SUB_DEVICEID_FSC 0x1081 85 #define PCI_SUB_VENDORID_FSC 0x1734 86 87 #define REGISTER_SET_IO (1) 88 89 #define MEGASAS_MAX_SGE_CNT 0x50 90 91 #define MEGASAS_IOCTL_DRIVER 0x12341234 92 #define MEGASAS_IOCTL_FIRMWARE 0x12345678 93 #define MEGASAS_IOCTL_AEN 0x87654321 94 95 #define MEGASAS_1_SECOND 1000000 96 /* 97 * ===================================== 98 * MegaRAID SAS MFI firmware definitions 99 * ===================================== 100 */ 101 /* 102 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 103 * protocol between the software and firmware. Commands are issued using 104 * "message frames" 105 */ 106 107 /* 108 * FW posts its state in upper 4 bits of outbound_msg_0 register 109 */ 110 #define MFI_STATE_MASK 0xF0000000 111 #define MFI_STATE_UNDEFINED 0x00000000 112 #define MFI_STATE_BB_INIT 0x10000000 113 #define MFI_STATE_FW_INIT 0x40000000 114 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 115 #define MFI_STATE_FW_INIT_2 0x70000000 116 #define MFI_STATE_DEVICE_SCAN 0x80000000 117 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 118 #define MFI_STATE_FLUSH_CACHE 0xA0000000 119 #define MFI_STATE_READY 0xB0000000 120 #define MFI_STATE_OPERATIONAL 0xC0000000 121 #define MFI_STATE_FAULT 0xF0000000 122 123 #define MEGAMFI_FRAME_SIZE 64 124 125 /* 126 * During FW init, clear pending cmds & reset state using inbound_msg_0 127 * 128 * ABORT : Abort all pending cmds 129 * READY : Move from OPERATIONAL to READY state; discard queue info 130 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 131 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 132 */ 133 #define MFI_INIT_ABORT 0x00000001 134 #define MFI_INIT_READY 0x00000002 135 #define MFI_INIT_MFIMODE 0x00000004 136 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 137 #define MFI_INIT_HOTPLUG 0x00000010 138 #define MFI_STOP_ADP 0x00000020 139 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT 140 141 /* 142 * MFI frame flags 143 */ 144 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 145 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 146 #define MFI_FRAME_SGL32 0x0000 147 #define MFI_FRAME_SGL64 0x0002 148 #define MFI_FRAME_SENSE32 0x0000 149 #define MFI_FRAME_SENSE64 0x0004 150 #define MFI_FRAME_DIR_NONE 0x0000 151 #define MFI_FRAME_DIR_WRITE 0x0008 152 #define MFI_FRAME_DIR_READ 0x0010 153 #define MFI_FRAME_DIR_BOTH 0x0018 154 155 /* 156 * Definition for cmd_status 157 */ 158 #define MFI_CMD_STATUS_POLL_MODE 0xFF 159 160 /* 161 * MFI command opcodes 162 */ 163 #define MFI_CMD_OP_INIT 0x00 164 #define MFI_CMD_OP_LD_READ 0x01 165 #define MFI_CMD_OP_LD_WRITE 0x02 166 #define MFI_CMD_OP_LD_SCSI 0x03 167 #define MFI_CMD_OP_PD_SCSI 0x04 168 #define MFI_CMD_OP_DCMD 0x05 169 #define MFI_CMD_OP_ABORT 0x06 170 #define MFI_CMD_OP_SMP 0x07 171 #define MFI_CMD_OP_STP 0x08 172 173 #define MR_DCMD_CTRL_GET_INFO 0x01010000 174 175 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 176 #define MR_FLUSH_CTRL_CACHE 0x01 177 #define MR_FLUSH_DISK_CACHE 0x02 178 179 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 180 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 181 182 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 183 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 184 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 185 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 186 187 /* 188 * Solaris Specific MAX values 189 */ 190 #define MAX_SGL 24 191 /* 192 * MFI command completion codes 193 */ 194 enum MFI_STAT { 195 MFI_STAT_OK = 0x00, 196 MFI_STAT_INVALID_CMD = 0x01, 197 MFI_STAT_INVALID_DCMD = 0x02, 198 MFI_STAT_INVALID_PARAMETER = 0x03, 199 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 200 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 201 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 202 MFI_STAT_APP_IN_USE = 0x07, 203 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 204 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 205 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 206 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 207 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 208 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 209 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 210 MFI_STAT_FLASH_BUSY = 0x0f, 211 MFI_STAT_FLASH_ERROR = 0x10, 212 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 213 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 214 MFI_STAT_FLASH_NOT_OPEN = 0x13, 215 MFI_STAT_FLASH_NOT_STARTED = 0x14, 216 MFI_STAT_FLUSH_FAILED = 0x15, 217 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 218 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 219 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 220 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 221 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 222 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 223 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 224 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 225 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 226 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 227 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 228 MFI_STAT_MFC_HW_ERROR = 0x21, 229 MFI_STAT_NO_HW_PRESENT = 0x22, 230 MFI_STAT_NOT_FOUND = 0x23, 231 MFI_STAT_NOT_IN_ENCL = 0x24, 232 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 233 MFI_STAT_PD_TYPE_WRONG = 0x26, 234 MFI_STAT_PR_DISABLED = 0x27, 235 MFI_STAT_ROW_INDEX_INVALID = 0x28, 236 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 237 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 238 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 239 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 240 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 241 MFI_STAT_SCSI_IO_FAILED = 0x2e, 242 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 243 MFI_STAT_SHUTDOWN_FAILED = 0x30, 244 MFI_STAT_TIME_NOT_SET = 0x31, 245 MFI_STAT_WRONG_STATE = 0x32, 246 MFI_STAT_LD_OFFLINE = 0x33, 247 MFI_STAT_INVALID_STATUS = 0xFF 248 }; 249 250 enum MR_EVT_CLASS { 251 MR_EVT_CLASS_DEBUG = -2, 252 MR_EVT_CLASS_PROGRESS = -1, 253 MR_EVT_CLASS_INFO = 0, 254 MR_EVT_CLASS_WARNING = 1, 255 MR_EVT_CLASS_CRITICAL = 2, 256 MR_EVT_CLASS_FATAL = 3, 257 MR_EVT_CLASS_DEAD = 4 258 }; 259 260 enum MR_EVT_LOCALE { 261 MR_EVT_LOCALE_LD = 0x0001, 262 MR_EVT_LOCALE_PD = 0x0002, 263 MR_EVT_LOCALE_ENCL = 0x0004, 264 MR_EVT_LOCALE_BBU = 0x0008, 265 MR_EVT_LOCALE_SAS = 0x0010, 266 MR_EVT_LOCALE_CTRL = 0x0020, 267 MR_EVT_LOCALE_CONFIG = 0x0040, 268 MR_EVT_LOCALE_CLUSTER = 0x0080, 269 MR_EVT_LOCALE_ALL = 0xffff 270 }; 271 272 enum MR_EVT_ARGS { 273 MR_EVT_ARGS_NONE, 274 MR_EVT_ARGS_CDB_SENSE, 275 MR_EVT_ARGS_LD, 276 MR_EVT_ARGS_LD_COUNT, 277 MR_EVT_ARGS_LD_LBA, 278 MR_EVT_ARGS_LD_OWNER, 279 MR_EVT_ARGS_LD_LBA_PD_LBA, 280 MR_EVT_ARGS_LD_PROG, 281 MR_EVT_ARGS_LD_STATE, 282 MR_EVT_ARGS_LD_STRIP, 283 MR_EVT_ARGS_PD, 284 MR_EVT_ARGS_PD_ERR, 285 MR_EVT_ARGS_PD_LBA, 286 MR_EVT_ARGS_PD_LBA_LD, 287 MR_EVT_ARGS_PD_PROG, 288 MR_EVT_ARGS_PD_STATE, 289 MR_EVT_ARGS_PCI, 290 MR_EVT_ARGS_RATE, 291 MR_EVT_ARGS_STR, 292 MR_EVT_ARGS_TIME, 293 MR_EVT_ARGS_ECC 294 }; 295 296 /* 297 * SAS controller properties 298 */ 299 struct megasas_ctrl_prop { 300 uint16_t seq_num; 301 uint16_t pred_fail_poll_interval; 302 uint16_t intr_throttle_count; 303 uint16_t intr_throttle_timeouts; 304 305 uint8_t rebuild_rate; 306 uint8_t patrol_read_rate; 307 uint8_t bgi_rate; 308 uint8_t cc_rate; 309 uint8_t recon_rate; 310 311 uint8_t cache_flush_interval; 312 313 uint8_t spinup_drv_count; 314 uint8_t spinup_delay; 315 316 uint8_t cluster_enable; 317 uint8_t coercion_mode; 318 uint8_t disk_write_cache_disable; 319 uint8_t alarm_enable; 320 321 uint8_t reserved[44]; 322 }; 323 324 /* 325 * SAS controller information 326 */ 327 struct megasas_ctrl_info { 328 /* PCI device information */ 329 struct { 330 uint16_t vendor_id; 331 uint16_t device_id; 332 uint16_t sub_vendor_id; 333 uint16_t sub_device_id; 334 uint8_t reserved[24]; 335 } pci; 336 337 /* Host interface information */ 338 struct { 339 uint8_t PCIX : 1; 340 uint8_t PCIE : 1; 341 uint8_t iSCSI : 1; 342 uint8_t SAS_3G : 1; 343 uint8_t reserved_0 : 4; 344 uint8_t reserved_1[6]; 345 uint8_t port_count; 346 uint64_t port_addr[8]; 347 } host_interface; 348 349 /* Device (backend) interface information */ 350 struct { 351 uint8_t SPI : 1; 352 uint8_t SAS_3G : 1; 353 uint8_t SATA_1_5G : 1; 354 uint8_t SATA_3G : 1; 355 uint8_t reserved_0 : 4; 356 uint8_t reserved_1[6]; 357 uint8_t port_count; 358 uint64_t port_addr[8]; 359 } device_interface; 360 361 /* List of components residing in flash. All str are null terminated */ 362 uint32_t image_check_word; 363 uint32_t image_component_count; 364 365 struct { 366 char name[8]; 367 char version[32]; 368 char build_date[16]; 369 char built_time[16]; 370 } image_component[8]; 371 372 /* 373 * List of flash components that have been flashed on the card, but 374 * are not in use, pending reset of the adapter. This list will be 375 * empty if a flash operation has not occurred. All stings are null 376 * terminated 377 */ 378 uint32_t pending_image_component_count; 379 380 struct { 381 char name[8]; 382 char version[32]; 383 char build_date[16]; 384 char build_time[16]; 385 } pending_image_component[8]; 386 387 uint8_t max_arms; 388 uint8_t max_spans; 389 uint8_t max_arrays; 390 uint8_t max_lds; 391 392 char product_name[80]; 393 char serial_no[32]; 394 395 /* 396 * Other physical/controller/operation information. Indicates the 397 * presence of the hardware 398 */ 399 struct { 400 uint32_t bbu : 1; 401 uint32_t alarm : 1; 402 uint32_t nvram : 1; 403 uint32_t uart : 1; 404 uint32_t reserved : 28; 405 } hw_present; 406 407 uint32_t current_fw_time; 408 409 /* Maximum data transfer sizes */ 410 uint16_t max_concurrent_cmds; 411 uint16_t max_sge_count; 412 uint32_t max_request_size; 413 414 /* Logical and physical device counts */ 415 uint16_t ld_present_count; 416 uint16_t ld_degraded_count; 417 uint16_t ld_offline_count; 418 419 uint16_t pd_present_count; 420 uint16_t pd_disk_present_count; 421 uint16_t pd_disk_pred_failure_count; 422 uint16_t pd_disk_failed_count; 423 424 /* Memory size information */ 425 uint16_t nvram_size; 426 uint16_t memory_size; 427 uint16_t flash_size; 428 429 /* Error counters */ 430 uint16_t mem_correctable_error_count; 431 uint16_t mem_uncorrectable_error_count; 432 433 /* Cluster information */ 434 uint8_t cluster_permitted; 435 uint8_t cluster_active; 436 uint8_t reserved_1[2]; 437 438 /* Controller capabilities structures */ 439 struct { 440 uint32_t raid_level_0 : 1; 441 uint32_t raid_level_1 : 1; 442 uint32_t raid_level_5 : 1; 443 uint32_t raid_level_1E : 1; 444 uint32_t reserved : 28; 445 } raid_levels; 446 447 struct { 448 uint32_t rbld_rate : 1; 449 uint32_t cc_rate : 1; 450 uint32_t bgi_rate : 1; 451 uint32_t recon_rate : 1; 452 uint32_t patrol_rate : 1; 453 uint32_t alarm_control : 1; 454 uint32_t cluster_supported : 1; 455 uint32_t bbu : 1; 456 uint32_t spanning_allowed : 1; 457 uint32_t dedicated_hotspares : 1; 458 uint32_t revertible_hotspares : 1; 459 uint32_t foreign_config_import : 1; 460 uint32_t self_diagnostic : 1; 461 uint32_t reserved : 19; 462 } adapter_operations; 463 464 struct { 465 uint32_t read_policy : 1; 466 uint32_t write_policy : 1; 467 uint32_t io_policy : 1; 468 uint32_t access_policy : 1; 469 uint32_t reserved : 28; 470 } ld_operations; 471 472 struct { 473 uint8_t min; 474 uint8_t max; 475 uint8_t reserved[2]; 476 } stripe_size_operations; 477 478 struct { 479 uint32_t force_online : 1; 480 uint32_t force_offline : 1; 481 uint32_t force_rebuild : 1; 482 uint32_t reserved : 29; 483 } pd_operations; 484 485 struct { 486 uint32_t ctrl_supports_sas : 1; 487 uint32_t ctrl_supports_sata : 1; 488 uint32_t allow_mix_in_encl : 1; 489 uint32_t allow_mix_in_ld : 1; 490 uint32_t allow_sata_in_cluster : 1; 491 uint32_t reserved : 27; 492 } pd_mix_support; 493 494 /* Include the controller properties (changeable items) */ 495 uint8_t reserved_2[12]; 496 struct megasas_ctrl_prop properties; 497 498 uint8_t pad[0x800 - 0x640]; 499 }; 500 501 /* 502 * =============================== 503 * MegaRAID SAS driver definitions 504 * =============================== 505 */ 506 #define MEGADRV_MAX_NUM_CMD 1024 507 508 #define MEGADRV_MAX_PD_CHANNELS 2 509 #define MEGADRV_MAX_LD_CHANNELS 2 510 #define MEGADRV_MAX_CHANNELS (MEGADRV_MAX_PD_CHANNELS + \ 511 MEGADRV_MAX_LD_CHANNELS) 512 #define MEGADRV_MAX_DEV_PER_CHANNEL 128 513 #define MEGADRV_DEFAULT_INIT_ID -1 514 #define MEGADRV_MAX_CMD_PER_LUN 1000 515 #define MEGADRV_MAX_LUN 8 516 #define MEGADRV_MAX_LD 64 517 518 #define MEGADRV_RESET_WAIT_TIME 300 519 #define MEGADRV_RESET_NOTICE_INTERVAL 5 520 521 #define MEGASAS_IOCTL_CMD 0 522 523 /* 524 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 525 * SGLs based on the size of dma_addr_t 526 */ 527 #define IS_DMA64 (sizeof (dma_addr_t) == 8) 528 529 /* 530 * All MFI register set macros accept megasas_register_set* 531 */ 532 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \ 533 (uint32_t *)((instance)->regmap + 0x10), (v)) 534 535 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \ 536 (uint32_t *)((instance)->regmap + 0x18)) 537 538 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \ 539 (uint32_t *)((instance)->regmap + 0x20), (v)) 540 541 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \ 542 (uint32_t *)((instance)->regmap + 0x20)) 543 544 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \ 545 (uint32_t *)((instance)->regmap + 0x30), (v)) 546 547 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \ 548 (uint32_t *)((instance)->regmap + 0x30)) 549 550 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \ 551 (uint32_t *)((instance)->regmap + 0x34), (v)) 552 553 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \ 554 (uint32_t *)((instance)->regmap + 0x34)) 555 556 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 557 (uint32_t *)((instance)->regmap + 0x40), (v)) 558 559 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \ 560 (uint32_t *)((instance)->regmap + 0xA0), (v)) 561 562 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \ 563 (uint32_t *)((instance)->regmap + 0xB0)) 564 565 /* 566 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data 567 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs 568 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled. 569 */ 570 #define MFI_OB_INTR_STATUS_MASK 0x00000002 571 572 /* 573 * This MFI_REPLY_1078_MESSAGE_INTR flag is used also 574 * in enable_intr_pcc also. Hence bit 2, i.e. 0x4 has 575 * been set in this flag along with bit 31. 576 */ 577 #define MFI_REPLY_1078_MESSAGE_INTR 0x80000004 578 579 #define MFI_POLL_TIMEOUT_SECS 60 580 581 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \ 582 (uint32_t *)((instance)->regmap + 0x34), 1) 583 #define MFI_DISABLE_INTR(instance) \ 584 { \ 585 uint32_t disable = 1; \ 586 uint32_t mask = ddi_get32((instance)->regmap_handle, \ 587 (uint32_t *)((instance)->regmap + 0x34)); \ 588 mask &= ~disable; \ 589 ddi_put32((instance)->regmap_handle, \ 590 (uint32_t *)((instance)->regmap + 0x34), mask); \ 591 } 592 593 594 struct megasas_register_set { 595 uint32_t reserved_0[4]; /* 0000h */ 596 597 uint32_t inbound_msg_0; /* 0010h */ 598 uint32_t inbound_msg_1; /* 0014h */ 599 uint32_t outbound_msg_0; /* 0018h */ 600 uint32_t outbound_msg_1; /* 001Ch */ 601 602 uint32_t inbound_doorbell; /* 0020h */ 603 uint32_t inbound_intr_status; /* 0024h */ 604 uint32_t inbound_intr_mask; /* 0028h */ 605 606 uint32_t outbound_doorbell; /* 002Ch */ 607 uint32_t outbound_intr_status; /* 0030h */ 608 uint32_t outbound_intr_mask; /* 0034h */ 609 610 uint32_t reserved_1[2]; /* 0038h */ 611 612 uint32_t inbound_queue_port; /* 0040h */ 613 uint32_t outbound_queue_port; /* 0044h */ 614 615 uint32_t reserved_2[22]; /* 0048h */ 616 617 uint32_t outbound_doorbell_clear; /* 00A0h */ 618 619 uint32_t reserved_3[3]; /* 00A4h */ 620 621 uint32_t outbound_scratch_pad; /* 00B0h */ 622 623 uint32_t reserved_4[3]; /* 00B4h */ 624 625 uint32_t inbound_low_queue_port; /* 00C0h */ 626 627 uint32_t inbound_high_queue_port; /* 00C4h */ 628 629 uint32_t reserved_5; /* 00C8h */ 630 uint32_t index_registers[820]; /* 00CCh */ 631 }; 632 633 struct megasas_sge32 { 634 uint32_t phys_addr; 635 uint32_t length; 636 }; 637 638 struct megasas_sge64 { 639 uint64_t phys_addr; 640 uint32_t length; 641 }; 642 643 union megasas_sgl { 644 struct megasas_sge32 sge32[1]; 645 struct megasas_sge64 sge64[1]; 646 }; 647 648 struct megasas_header { 649 uint8_t cmd; /* 00h */ 650 uint8_t sense_len; /* 01h */ 651 uint8_t cmd_status; /* 02h */ 652 uint8_t scsi_status; /* 03h */ 653 654 uint8_t target_id; /* 04h */ 655 uint8_t lun; /* 05h */ 656 uint8_t cdb_len; /* 06h */ 657 uint8_t sge_count; /* 07h */ 658 659 uint32_t context; /* 08h */ 660 uint32_t pad_0; /* 0Ch */ 661 662 uint16_t flags; /* 10h */ 663 uint16_t timeout; /* 12h */ 664 uint32_t data_xferlen; /* 14h */ 665 }; 666 667 union megasas_sgl_frame { 668 struct megasas_sge32 sge32[8]; 669 struct megasas_sge64 sge64[5]; 670 }; 671 672 struct megasas_init_frame { 673 uint8_t cmd; /* 00h */ 674 uint8_t reserved_0; /* 01h */ 675 uint8_t cmd_status; /* 02h */ 676 677 uint8_t reserved_1; /* 03h */ 678 uint32_t reserved_2; /* 04h */ 679 680 uint32_t context; /* 08h */ 681 uint32_t pad_0; /* 0Ch */ 682 683 uint16_t flags; /* 10h */ 684 uint16_t reserved_3; /* 12h */ 685 uint32_t data_xfer_len; /* 14h */ 686 687 uint32_t queue_info_new_phys_addr_lo; /* 18h */ 688 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */ 689 uint32_t queue_info_old_phys_addr_lo; /* 20h */ 690 uint32_t queue_info_old_phys_addr_hi; /* 24h */ 691 692 uint32_t reserved_4[6]; /* 28h */ 693 }; 694 695 struct megasas_init_queue_info { 696 uint32_t init_flags; /* 00h */ 697 uint32_t reply_queue_entries; /* 04h */ 698 699 uint32_t reply_queue_start_phys_addr_lo; /* 08h */ 700 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */ 701 uint32_t producer_index_phys_addr_lo; /* 10h */ 702 uint32_t producer_index_phys_addr_hi; /* 14h */ 703 uint32_t consumer_index_phys_addr_lo; /* 18h */ 704 uint32_t consumer_index_phys_addr_hi; /* 1Ch */ 705 }; 706 707 struct megasas_io_frame { 708 uint8_t cmd; /* 00h */ 709 uint8_t sense_len; /* 01h */ 710 uint8_t cmd_status; /* 02h */ 711 uint8_t scsi_status; /* 03h */ 712 713 uint8_t target_id; /* 04h */ 714 uint8_t access_byte; /* 05h */ 715 uint8_t reserved_0; /* 06h */ 716 uint8_t sge_count; /* 07h */ 717 718 uint32_t context; /* 08h */ 719 uint32_t pad_0; /* 0Ch */ 720 721 uint16_t flags; /* 10h */ 722 uint16_t timeout; /* 12h */ 723 uint32_t lba_count; /* 14h */ 724 725 uint32_t sense_buf_phys_addr_lo; /* 18h */ 726 uint32_t sense_buf_phys_addr_hi; /* 1Ch */ 727 728 uint32_t start_lba_lo; /* 20h */ 729 uint32_t start_lba_hi; /* 24h */ 730 731 union megasas_sgl sgl; /* 28h */ 732 }; 733 734 struct megasas_pthru_frame { 735 uint8_t cmd; /* 00h */ 736 uint8_t sense_len; /* 01h */ 737 uint8_t cmd_status; /* 02h */ 738 uint8_t scsi_status; /* 03h */ 739 740 uint8_t target_id; /* 04h */ 741 uint8_t lun; /* 05h */ 742 uint8_t cdb_len; /* 06h */ 743 uint8_t sge_count; /* 07h */ 744 745 uint32_t context; /* 08h */ 746 uint32_t pad_0; /* 0Ch */ 747 748 uint16_t flags; /* 10h */ 749 uint16_t timeout; /* 12h */ 750 uint32_t data_xfer_len; /* 14h */ 751 752 uint32_t sense_buf_phys_addr_lo; /* 18h */ 753 uint32_t sense_buf_phys_addr_hi; /* 1Ch */ 754 755 uint8_t cdb[16]; /* 20h */ 756 union megasas_sgl sgl; /* 30h */ 757 }; 758 759 struct megasas_dcmd_frame { 760 uint8_t cmd; /* 00h */ 761 uint8_t reserved_0; /* 01h */ 762 uint8_t cmd_status; /* 02h */ 763 uint8_t reserved_1[4]; /* 03h */ 764 uint8_t sge_count; /* 07h */ 765 766 uint32_t context; /* 08h */ 767 uint32_t pad_0; /* 0Ch */ 768 769 uint16_t flags; /* 10h */ 770 uint16_t timeout; /* 12h */ 771 772 uint32_t data_xfer_len; /* 14h */ 773 uint32_t opcode; /* 18h */ 774 775 /* uint8_t mbox[12]; */ /* 1Ch */ 776 union { /* 1Ch */ 777 uint8_t b[12]; 778 uint16_t s[6]; 779 uint32_t w[3]; 780 } mbox; 781 782 union megasas_sgl sgl; /* 28h */ 783 }; 784 785 struct megasas_abort_frame { 786 uint8_t cmd; /* 00h */ 787 uint8_t reserved_0; /* 01h */ 788 uint8_t cmd_status; /* 02h */ 789 790 uint8_t reserved_1; /* 03h */ 791 uint32_t reserved_2; /* 04h */ 792 793 uint32_t context; /* 08h */ 794 uint32_t pad_0; /* 0Ch */ 795 796 uint16_t flags; /* 10h */ 797 uint16_t reserved_3; /* 12h */ 798 uint32_t reserved_4; /* 14h */ 799 800 uint32_t abort_context; /* 18h */ 801 uint32_t pad_1; /* 1Ch */ 802 803 uint32_t abort_mfi_phys_addr_lo; /* 20h */ 804 uint32_t abort_mfi_phys_addr_hi; /* 24h */ 805 806 uint32_t reserved_5[6]; /* 28h */ 807 }; 808 809 struct megasas_smp_frame { 810 uint8_t cmd; /* 00h */ 811 uint8_t reserved_1; /* 01h */ 812 uint8_t cmd_status; /* 02h */ 813 uint8_t connection_status; /* 03h */ 814 815 uint8_t reserved_2[3]; /* 04h */ 816 uint8_t sge_count; /* 07h */ 817 818 uint32_t context; /* 08h */ 819 uint32_t pad_0; /* 0Ch */ 820 821 uint16_t flags; /* 10h */ 822 uint16_t timeout; /* 12h */ 823 824 uint32_t data_xfer_len; /* 14h */ 825 826 uint64_t sas_addr; /* 20h */ 827 828 union megasas_sgl sgl[2]; /* 28h */ 829 }; 830 831 struct megasas_stp_frame { 832 uint8_t cmd; /* 00h */ 833 uint8_t reserved_1; /* 01h */ 834 uint8_t cmd_status; /* 02h */ 835 uint8_t connection_status; /* 03h */ 836 837 uint8_t target_id; /* 04h */ 838 uint8_t reserved_2[2]; /* 04h */ 839 uint8_t sge_count; /* 07h */ 840 841 uint32_t context; /* 08h */ 842 uint32_t pad_0; /* 0Ch */ 843 844 uint16_t flags; /* 10h */ 845 uint16_t timeout; /* 12h */ 846 847 uint32_t data_xfer_len; /* 14h */ 848 849 uint16_t fis[10]; /* 28h */ 850 uint32_t stp_flags; /* 3C */ 851 union megasas_sgl sgl; /* 40 */ 852 }; 853 854 union megasas_frame { 855 struct megasas_header hdr; 856 struct megasas_init_frame init; 857 struct megasas_io_frame io; 858 struct megasas_pthru_frame pthru; 859 struct megasas_dcmd_frame dcmd; 860 struct megasas_abort_frame abort; 861 struct megasas_smp_frame smp; 862 struct megasas_stp_frame stp; 863 864 uint8_t raw_bytes[64]; 865 }; 866 867 union megasas_evt_class_locale { 868 struct { 869 uint16_t locale; 870 uint8_t reserved; 871 int8_t class; 872 } members; 873 874 uint32_t word; 875 }; 876 877 struct megasas_evt_log_info { 878 uint32_t newest_seq_num; 879 uint32_t oldest_seq_num; 880 uint32_t clear_seq_num; 881 uint32_t shutdown_seq_num; 882 uint32_t boot_seq_num; 883 }; 884 885 struct megasas_progress { 886 uint16_t progress; 887 uint16_t elapsed_seconds; 888 }; 889 890 struct megasas_evtarg_ld { 891 uint16_t target_id; 892 uint8_t ld_index; 893 uint8_t reserved; 894 }; 895 896 struct megasas_evtarg_pd { 897 uint16_t device_id; 898 uint8_t encl_index; 899 uint8_t slot_number; 900 }; 901 902 struct megasas_evt_detail { 903 uint32_t seq_num; 904 uint32_t time_stamp; 905 uint32_t code; 906 union megasas_evt_class_locale cl; 907 uint8_t arg_type; 908 uint8_t reserved1[15]; 909 910 union { 911 struct { 912 struct megasas_evtarg_pd pd; 913 uint8_t cdb_length; 914 uint8_t sense_length; 915 uint8_t reserved[2]; 916 uint8_t cdb[16]; 917 uint8_t sense[64]; 918 } cdbSense; 919 920 struct megasas_evtarg_ld ld; 921 922 struct { 923 struct megasas_evtarg_ld ld; 924 uint64_t count; 925 } ld_count; 926 927 struct { 928 uint64_t lba; 929 struct megasas_evtarg_ld ld; 930 } ld_lba; 931 932 struct { 933 struct megasas_evtarg_ld ld; 934 uint32_t prevOwner; 935 uint32_t newOwner; 936 } ld_owner; 937 938 struct { 939 uint64_t ld_lba; 940 uint64_t pd_lba; 941 struct megasas_evtarg_ld ld; 942 struct megasas_evtarg_pd pd; 943 } ld_lba_pd_lba; 944 945 struct { 946 struct megasas_evtarg_ld ld; 947 struct megasas_progress prog; 948 } ld_prog; 949 950 struct { 951 struct megasas_evtarg_ld ld; 952 uint32_t prev_state; 953 uint32_t new_state; 954 } ld_state; 955 956 struct { 957 uint64_t strip; 958 struct megasas_evtarg_ld ld; 959 } ld_strip; 960 961 struct megasas_evtarg_pd pd; 962 963 struct { 964 struct megasas_evtarg_pd pd; 965 uint32_t err; 966 } pd_err; 967 968 struct { 969 uint64_t lba; 970 struct megasas_evtarg_pd pd; 971 } pd_lba; 972 973 struct { 974 uint64_t lba; 975 struct megasas_evtarg_pd pd; 976 struct megasas_evtarg_ld ld; 977 } pd_lba_ld; 978 979 struct { 980 struct megasas_evtarg_pd pd; 981 struct megasas_progress prog; 982 } pd_prog; 983 984 struct { 985 struct megasas_evtarg_pd pd; 986 uint32_t prevState; 987 uint32_t newState; 988 } pd_state; 989 990 struct { 991 uint16_t vendorId; 992 uint16_t deviceId; 993 uint16_t subVendorId; 994 uint16_t subDeviceId; 995 } pci; 996 997 uint32_t rate; 998 char str[96]; 999 1000 struct { 1001 uint32_t rtc; 1002 uint32_t elapsedSeconds; 1003 } time; 1004 1005 struct { 1006 uint32_t ecar; 1007 uint32_t elog; 1008 char str[64]; 1009 } ecc; 1010 1011 uint8_t b[96]; 1012 uint16_t s[48]; 1013 uint32_t w[24]; 1014 uint64_t d[12]; 1015 } args; 1016 1017 char description[128]; 1018 1019 }; 1020 1021 /* only 63 are usable by the application */ 1022 #define MAX_LOGICAL_DRIVES 64 1023 /* only 255 physical devices may be used */ 1024 #define MAX_PHYSICAL_DEVICES 256 1025 #define MAX_PD_PER_ENCLOSURE 64 1026 /* maximum disks per array */ 1027 #define MAX_ROW_SIZE 32 1028 /* maximum spans per logical drive */ 1029 #define MAX_SPAN_DEPTH 8 1030 /* maximum number of arrays a hot spare may be dedicated to */ 1031 #define MAX_ARRAYS_DEDICATED 16 1032 /* maximum number of arrays which may exist */ 1033 #define MAX_ARRAYS 128 1034 /* maximum number of foreign configs that may ha managed at once */ 1035 #define MAX_FOREIGN_CONFIGS 8 1036 /* maximum spares (global and dedicated combined) */ 1037 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES 1038 /* maximum possible Target IDs (i.e. 0 to 63) */ 1039 #define MAX_TARGET_ID 63 1040 /* maximum number of supported enclosures */ 1041 #define MAX_ENCLOSURES 32 1042 /* maximum number of PHYs per controller */ 1043 #define MAX_PHYS_PER_CONTROLLER 16 1044 /* maximum number of LDs per array (due to DDF limitations) */ 1045 #define MAX_LDS_PER_ARRAY 16 1046 1047 /* 1048 * ----------------------------------------------------------------------------- 1049 * ----------------------------------------------------------------------------- 1050 * 1051 * Logical Drive commands 1052 * 1053 * ----------------------------------------------------------------------------- 1054 * ----------------------------------------------------------------------------- 1055 */ 1056 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */ 1057 1058 /* 1059 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST 1060 * dcmd.mbox - reserved 1061 * dcmd.sge IN - ptr to returned MR_LD_LIST structure 1062 * Desc: Return the logical drive list structure 1063 * Status: No error 1064 */ 1065 1066 /* 1067 * defines the logical drive reference structure 1068 */ 1069 typedef union _MR_LD_REF { /* LD reference structure */ 1070 struct { 1071 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */ 1072 uint8_t reserved; /* reserved to make in line with MR_PD_REF */ 1073 uint16_t seqNum; /* Sequence Number */ 1074 } ld_ref; 1075 uint32_t ref; /* shorthand reference to full 32-bits */ 1076 } MR_LD_REF; /* 4 bytes */ 1077 1078 /* 1079 * defines the logical drive list structure 1080 */ 1081 typedef struct _MR_LD_LIST { 1082 uint32_t ldCount; /* number of LDs */ 1083 uint32_t reserved; /* pad to 8-byte boundary */ 1084 struct { 1085 MR_LD_REF ref; /* LD reference */ 1086 uint8_t state; /* current LD state (MR_LD_STATE) */ 1087 uint8_t reserved[3]; /* pad to 8-byte boundary */ 1088 uint64_t size; /* LD size */ 1089 } ldList[MAX_LOGICAL_DRIVES]; 1090 } MR_LD_LIST; 1091 /* 4 + 4 + (MAX_LOGICAL_DRIVES * 16), for 40LD it is = 648 bytes */ 1092 1093 #define DMA_OBJ_ALLOCATED 1 1094 #define DMA_OBJ_REALLOCATED 2 1095 #define DMA_OBJ_FREED 3 1096 1097 #pragma pack() 1098 1099 /* 1100 * dma_obj_t - Our DMA object 1101 * @param buffer : kernel virtual address 1102 * @param size : size of the data to be allocated 1103 * @param acc_handle : access handle 1104 * @param dma_handle : dma handle 1105 * @param dma_cookie : scatter-gather list 1106 * @param dma_attr : dma attributes for this buffer 1107 * 1108 * Our DMA object. The caller must initialize the size and dma attributes 1109 * (dma_attr) fields before allocating the resources. 1110 */ 1111 typedef struct { 1112 caddr_t buffer; 1113 uint32_t size; 1114 ddi_acc_handle_t acc_handle; 1115 ddi_dma_handle_t dma_handle; 1116 ddi_dma_cookie_t dma_cookie[MEGASAS_MAX_SGE_CNT]; 1117 ddi_dma_attr_t dma_attr; 1118 uint8_t status; 1119 } dma_obj_t; 1120 1121 struct megasas_instance { 1122 uint32_t *producer; 1123 uint32_t *consumer; 1124 1125 uint32_t *reply_queue; 1126 dma_obj_t mfi_internal_dma_obj; 1127 1128 uint8_t init_id; 1129 uint8_t reserved[3]; 1130 1131 uint16_t max_num_sge; 1132 uint16_t max_fw_cmds; 1133 uint32_t max_sectors_per_req; 1134 1135 struct megasas_cmd **cmd_list; 1136 1137 mlist_t cmd_pool_list; 1138 kmutex_t cmd_pool_mtx; 1139 1140 mlist_t cmd_pend_list; 1141 kmutex_t cmd_pend_mtx; 1142 1143 dma_obj_t mfi_evt_detail_obj; 1144 struct megasas_cmd *aen_cmd; 1145 1146 uint32_t aen_seq_num; 1147 uint32_t aen_class_locale_word; 1148 1149 scsi_hba_tran_t *tran; 1150 1151 kcondvar_t int_cmd_cv; 1152 kmutex_t int_cmd_mtx; 1153 1154 kcondvar_t aen_cmd_cv; 1155 kmutex_t aen_cmd_mtx; 1156 1157 kcondvar_t abort_cmd_cv; 1158 kmutex_t abort_cmd_mtx; 1159 1160 dev_info_t *dip; 1161 ddi_acc_handle_t pci_handle; 1162 1163 timeout_id_t timeout_id; 1164 uint32_t unique_id; 1165 uint16_t fw_outstanding; 1166 caddr_t regmap; 1167 ddi_acc_handle_t regmap_handle; 1168 uint8_t isr_level; 1169 ddi_iblock_cookie_t iblock_cookie; 1170 ddi_iblock_cookie_t soft_iblock_cookie; 1171 ddi_softintr_t soft_intr_id; 1172 uint8_t softint_running; 1173 kmutex_t completed_pool_mtx; 1174 mlist_t completed_pool_list; 1175 1176 caddr_t internal_buf; 1177 uint32_t internal_buf_dmac_add; 1178 uint32_t internal_buf_size; 1179 1180 uint16_t vendor_id; 1181 uint16_t device_id; 1182 uint16_t subsysvid; 1183 uint16_t subsysid; 1184 int baseaddress; 1185 char iocnode[16]; 1186 1187 int fm_capabilities; 1188 1189 struct megasas_func_ptr *func_ptr; 1190 }; 1191 1192 struct megasas_func_ptr { 1193 int (*read_fw_status_reg)(struct megasas_instance *); 1194 void (*issue_cmd)(struct megasas_cmd *, struct megasas_instance *); 1195 int (*issue_cmd_in_sync_mode)(struct megasas_instance *, 1196 struct megasas_cmd *); 1197 int (*issue_cmd_in_poll_mode)(struct megasas_instance *, 1198 struct megasas_cmd *); 1199 void (*enable_intr)(struct megasas_instance *); 1200 void (*disable_intr)(struct megasas_instance *); 1201 int (*intr_ack)(struct megasas_instance *); 1202 }; 1203 1204 /* 1205 * ### Helper routines ### 1206 */ 1207 1208 /* 1209 * con_log() - console log routine 1210 * @param level : indicates the severity of the message. 1211 * @fparam mt : format string 1212 * 1213 * con_log displays the error messages on the console based on the current 1214 * debug level. Also it attaches the appropriate kernel severity level with 1215 * the message. 1216 * 1217 * 1218 * consolge messages debug levels 1219 */ 1220 #define CL_ANN 0 /* print unconditionally, announcements */ 1221 #define CL_ANN1 1 /* No o/p */ 1222 #define CL_DLEVEL1 2 /* debug level 1, informative */ 1223 #define CL_DLEVEL2 3 /* debug level 2, verbose */ 1224 #define CL_DLEVEL3 4 /* debug level 3, very verbose */ 1225 1226 #ifdef __SUNPRO_C 1227 #define __func__ "" 1228 #endif 1229 1230 #if DEBUG 1231 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; } 1232 #else 1233 #define con_log(level, fmt) 1234 #endif /* DEBUG */ 1235 1236 /* byte-ordering macros */ 1237 #ifdef __sparc 1238 #define host_to_le16(s) ((s) & 0xFF) << 8 | ((s) & 0xFF00) >> 8 1239 #else 1240 #define host_to_le16(s) (s) 1241 #endif 1242 1243 #ifdef __sparc 1244 #define host_to_le32(l) (((l) & 0xFF) << 24 | ((l) & 0xFF00) << 8 | \ 1245 ((l) & 0xFF0000) >> 8 | ((l) & 0xFF000000) >> 24) 1246 #else 1247 #define host_to_le32(l) (l) 1248 #endif 1249 1250 #ifdef __sparc 1251 #define host_to_le64(ull) ((host_to_le32(((ull) & 0xFFFFFFFF)) << 32) | \ 1252 (host_to_le32((((ull) & 0xFFFFFFFF00000000) >> 32)))) 1253 #else 1254 #define host_to_le64(ull) (ull) 1255 #endif 1256 1257 /* 1258 * ### SCSA definitions ### 1259 */ 1260 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target) 1261 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun) 1262 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran) 1263 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1264 1265 #define TRAN2MEGA(tran) (struct megasas_instance *)(tran)->tran_hba_private) 1266 #define ADDR2MEGA(ap) (TRAN2MEGA(ADDR2TRAN(ap)) 1267 1268 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private) 1269 #define CMD2PKT(sp) ((sp)->cmd_pkt) 1270 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request)) 1271 1272 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address) 1273 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran) 1274 #define CMD2MEGA(cmd) (TRAN2MEGA(CMD2TRAN(cmd))) 1275 1276 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */ 1277 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */ 1278 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */ 1279 1280 /* 1281 * ### Data structures for ioctl inteface and internal commands ### 1282 */ 1283 1284 /* 1285 * Data direction flags 1286 */ 1287 #define UIOC_RD 0x00001 1288 #define UIOC_WR 0x00002 1289 1290 #define SCP2HOST(scp) (scp)->device->host /* to host */ 1291 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */ 1292 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */ 1293 #define SCP2TARGET(scp) (scp)->device->id /* to target */ 1294 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */ 1295 1296 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0]) 1297 #define SCP2ADAPTER(scp) \ 1298 (struct megasas_instance *)SCSIHOST2ADAP(SCP2HOST(scp)) 1299 1300 #define MEGADRV_IS_LOGICAL_SCSA(instance, acmd) \ 1301 (acmd->device_id < MEGADRV_MAX_LD) ? 1 : 0 1302 #define MEGADRV_IS_LOGICAL(ap) \ 1303 (ap->a_target < MEGADRV_MAX_LD) ? 1 : 0 1304 #define MAP_DEVICE_ID(instance, ap) \ 1305 (ap->a_target % MEGADRV_MAX_LD) 1306 /* 1307 * #define MAP_DEVICE_ID(instance,ap) \ 1308 * (ap->a_target) 1309 */ 1310 1311 #define HIGH_LEVEL_INTR 1 1312 #define NORMAL_LEVEL_INTR 0 1313 1314 /* 1315 * scsa_cmd - Per-command mega private data 1316 * @param cmd_dmahandle : dma handle 1317 * @param cmd_dmacookies : current dma cookies 1318 * @param cmd_pkt : scsi_pkt reference 1319 * @param cmd_dmacount : dma count 1320 * @param cmd_cookie : next cookie 1321 * @param cmd_ncookies : cookies per window 1322 * @param cmd_cookiecnt : cookies per sub-win 1323 * @param cmd_nwin : number of dma windows 1324 * @param cmd_curwin : current dma window 1325 * @param cmd_dma_offset : current window offset 1326 * @param cmd_dma_len : current window length 1327 * @param cmd_flags : private flags 1328 * @param cmd_cdblen : length of cdb 1329 * @param cmd_scblen : length of scb 1330 * @param cmd_buf : command buffer 1331 * @param channel : channel for scsi sub-system 1332 * @param target : target for scsi sub-system 1333 * @param lun : LUN for scsi sub-system 1334 * 1335 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E) 1336 * - Pointed to by pkt_ha_private field in scsi_pkt 1337 */ 1338 struct scsa_cmd { 1339 ddi_dma_handle_t cmd_dmahandle; 1340 ddi_dma_cookie_t cmd_dmacookies[MEGASAS_MAX_SGE_CNT]; 1341 struct scsi_pkt *cmd_pkt; 1342 ulong_t cmd_dmacount; 1343 uint_t cmd_cookie; 1344 uint_t cmd_ncookies; 1345 uint_t cmd_cookiecnt; 1346 uint_t cmd_nwin; 1347 uint_t cmd_curwin; 1348 off_t cmd_dma_offset; 1349 ulong_t cmd_dma_len; 1350 ulong_t cmd_flags; 1351 uint_t cmd_cdblen; 1352 uint_t cmd_scblen; 1353 struct buf *cmd_buf; 1354 ushort_t device_id; 1355 uchar_t islogical; 1356 uchar_t lun; 1357 }; 1358 1359 1360 struct megasas_cmd { 1361 union megasas_frame *frame; 1362 uint32_t frame_phys_addr; 1363 uint8_t *sense; 1364 uint32_t sense_phys_addr; 1365 dma_obj_t frame_dma_obj; 1366 uint8_t frame_dma_obj_status; 1367 1368 uint32_t index; 1369 uint8_t sync_cmd; 1370 uint8_t cmd_status; 1371 uint16_t abort_aen; 1372 mlist_t list; 1373 uint32_t frame_count; 1374 struct scsa_cmd *cmd; 1375 struct scsi_pkt *pkt; 1376 }; 1377 1378 #define MAX_MGMT_ADAPTERS 1024 1379 #define IOC_SIGNATURE "MEGA-SAS" 1380 1381 #define IOC_CMD_FIRMWARE 0x0 1382 #define MR_DRIVER_IOCTL_COMMON 0xF0010000 1383 #define MR_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100 1384 #define MR_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200 1385 #define MR_DRIVER_IOCTL_MEGARAID_STATISTICS 0xF0010300 1386 1387 1388 #define MR_MAX_SENSE_LENGTH 32 1389 1390 struct megasas_mgmt_info { 1391 1392 uint16_t count; 1393 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1394 uint16_t map[MAX_MGMT_ADAPTERS]; 1395 int max_index; 1396 }; 1397 1398 #pragma pack(1) 1399 1400 struct megasas_drv_ver { 1401 uint8_t signature[12]; 1402 uint8_t os_name[16]; 1403 uint8_t os_ver[12]; 1404 uint8_t drv_name[20]; 1405 uint8_t drv_ver[32]; 1406 uint8_t drv_rel_date[20]; 1407 }; 1408 1409 #define PCI_TYPE0_ADDRESSES 6 1410 #define PCI_TYPE1_ADDRESSES 2 1411 #define PCI_TYPE2_ADDRESSES 5 1412 1413 struct megasas_pci_common_header { 1414 uint16_t vendorID; /* (ro) */ 1415 uint16_t deviceID; /* (ro) */ 1416 uint16_t command; /* Device control */ 1417 uint16_t status; 1418 uint8_t revisionID; /* (ro) */ 1419 uint8_t progIf; /* (ro) */ 1420 uint8_t subClass; /* (ro) */ 1421 uint8_t baseClass; /* (ro) */ 1422 uint8_t cacheLineSize; /* (ro+) */ 1423 uint8_t latencyTimer; /* (ro+) */ 1424 uint8_t headerType; /* (ro) */ 1425 uint8_t bist; /* Built in self test */ 1426 1427 union { 1428 struct { 1429 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 1430 uint32_t cis; 1431 uint16_t subVendorID; 1432 uint16_t subSystemID; 1433 uint32_t romBaseAddress; 1434 uint8_t capabilitiesPtr; 1435 uint8_t reserved1[3]; 1436 uint32_t reserved2; 1437 uint8_t interruptLine; 1438 uint8_t interruptPin; /* (ro) */ 1439 uint8_t minimumGrant; /* (ro) */ 1440 uint8_t maximumLatency; /* (ro) */ 1441 } type_0; 1442 1443 struct { 1444 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 1445 uint8_t primaryBus; 1446 uint8_t secondaryBus; 1447 uint8_t subordinateBus; 1448 uint8_t secondaryLatency; 1449 uint8_t ioBase; 1450 uint8_t ioLimit; 1451 uint16_t secondaryStatus; 1452 uint16_t memoryBase; 1453 uint16_t memoryLimit; 1454 uint16_t prefetchBase; 1455 uint16_t prefetchLimit; 1456 uint32_t prefetchBaseUpper32; 1457 uint32_t prefetchLimitUpper32; 1458 uint16_t ioBaseUpper16; 1459 uint16_t ioLimitUpper16; 1460 uint8_t capabilitiesPtr; 1461 uint8_t reserved1[3]; 1462 uint32_t romBaseAddress; 1463 uint8_t interruptLine; 1464 uint8_t interruptPin; 1465 uint16_t bridgeControl; 1466 } type_1; 1467 1468 struct { 1469 uint32_t socketRegistersBaseAddress; 1470 uint8_t capabilitiesPtr; 1471 uint8_t reserved; 1472 uint16_t secondaryStatus; 1473 uint8_t primaryBus; 1474 uint8_t secondaryBus; 1475 uint8_t subordinateBus; 1476 uint8_t secondaryLatency; 1477 struct { 1478 uint32_t base; 1479 uint32_t limit; 1480 } range[PCI_TYPE2_ADDRESSES-1]; 1481 uint8_t interruptLine; 1482 uint8_t interruptPin; 1483 uint16_t bridgeControl; 1484 } type_2; 1485 } header; 1486 }; 1487 1488 struct megasas_pci_link_capability { 1489 union { 1490 struct { 1491 uint32_t linkSpeed :4; 1492 uint32_t linkWidth :6; 1493 uint32_t aspmSupport :2; 1494 uint32_t losExitLatency :3; 1495 uint32_t l1ExitLatency :3; 1496 uint32_t rsvdp :6; 1497 uint32_t portNumber :8; 1498 } bits; 1499 1500 uint32_t asUlong; 1501 } cap; 1502 1503 }; 1504 1505 struct megasas_pci_link_status_capability { 1506 union { 1507 struct { 1508 uint16_t linkSpeed :4; 1509 uint16_t negotiatedLinkWidth :6; 1510 uint16_t linkTrainingError :1; 1511 uint16_t linkTraning :1; 1512 uint16_t slotClockConfig :1; 1513 uint16_t rsvdZ :3; 1514 } bits; 1515 1516 uint16_t asUshort; 1517 } stat_cap; 1518 1519 uint16_t reserved; 1520 1521 }; 1522 1523 struct megasas_pci_capabilities { 1524 struct megasas_pci_link_capability linkCapability; 1525 struct megasas_pci_link_status_capability linkStatusCapability; 1526 }; 1527 1528 struct megasas_pci_information 1529 { 1530 uint32_t busNumber; 1531 uint8_t deviceNumber; 1532 uint8_t functionNumber; 1533 uint8_t interruptVector; 1534 uint8_t reserved; 1535 struct megasas_pci_common_header pciHeaderInfo; 1536 struct megasas_pci_capabilities capability; 1537 uint8_t reserved2[32]; 1538 }; 1539 1540 struct megasas_ioctl { 1541 uint16_t version; 1542 uint16_t controller_id; 1543 uint8_t signature[8]; 1544 uint32_t reserved_1; 1545 uint32_t control_code; 1546 uint32_t reserved_2[2]; 1547 uint8_t frame[64]; 1548 union megasas_sgl_frame sgl_frame; 1549 uint8_t sense_buff[MR_MAX_SENSE_LENGTH]; 1550 uint8_t data[1]; 1551 }; 1552 1553 struct megasas_aen { 1554 uint16_t host_no; 1555 uint16_t cmd_status; 1556 uint32_t seq_num; 1557 uint32_t class_locale_word; 1558 }; 1559 1560 #pragma pack() 1561 1562 #ifndef DDI_VENDOR_LSI 1563 #define DDI_VENDOR_LSI "LSI" 1564 #endif /* DDI_VENDOR_LSI */ 1565 1566 static int megasas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 1567 static int megasas_attach(dev_info_t *, ddi_attach_cmd_t); 1568 static int megasas_reset(dev_info_t *, ddi_reset_cmd_t); 1569 static int megasas_detach(dev_info_t *, ddi_detach_cmd_t); 1570 static int megasas_open(dev_t *, int, int, cred_t *); 1571 static int megasas_close(dev_t, int, int, cred_t *); 1572 static int megasas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 1573 1574 static int megasas_tran_tgt_init(dev_info_t *, dev_info_t *, 1575 scsi_hba_tran_t *, struct scsi_device *); 1576 #if defined(USELESS) && !defined(lint) 1577 static int megasas_tran_tgt_probe(struct scsi_device *, int); 1578 #endif 1579 static struct scsi_pkt *megasas_tran_init_pkt(struct scsi_address *, register 1580 struct scsi_pkt *, struct buf *, int, int, int, int, 1581 int (*)(), caddr_t); 1582 static int megasas_tran_start(struct scsi_address *, 1583 register struct scsi_pkt *); 1584 static int megasas_tran_abort(struct scsi_address *, struct scsi_pkt *); 1585 static int megasas_tran_reset(struct scsi_address *, int); 1586 static int megasas_tran_bus_reset(dev_info_t *, int); 1587 static int megasas_tran_getcap(struct scsi_address *, char *, int); 1588 static int megasas_tran_setcap(struct scsi_address *, char *, int, int); 1589 static void megasas_tran_destroy_pkt(struct scsi_address *, 1590 struct scsi_pkt *); 1591 static void megasas_tran_dmafree(struct scsi_address *, struct scsi_pkt *); 1592 static void megasas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *); 1593 static int megasas_tran_quiesce(dev_info_t *dip); 1594 static int megasas_tran_unquiesce(dev_info_t *dip); 1595 static uint_t megasas_isr(caddr_t); 1596 static uint_t megasas_softintr(caddr_t); 1597 1598 static int init_mfi(struct megasas_instance *); 1599 static int mega_free_dma_obj(struct megasas_instance *, dma_obj_t); 1600 static int mega_alloc_dma_obj(struct megasas_instance *, dma_obj_t *); 1601 static struct megasas_cmd *get_mfi_pkt(struct megasas_instance *); 1602 static void return_mfi_pkt(struct megasas_instance *, 1603 struct megasas_cmd *); 1604 #ifndef lint 1605 static void push_pend_queue(struct megasas_instance *instance, 1606 struct megasas_cmd *cmd); 1607 static struct megasas_cmd *pull_pend_queue(struct megasas_instance *instance); 1608 #endif 1609 static void free_space_for_mfi(struct megasas_instance *); 1610 static void free_additional_dma_buffer(struct megasas_instance *); 1611 static int alloc_additional_dma_buffer(struct megasas_instance *); 1612 static int read_fw_status_reg_xscale(struct megasas_instance *); 1613 static int read_fw_status_reg_ppc(struct megasas_instance *); 1614 static void issue_cmd_xscale(struct megasas_cmd *, 1615 struct megasas_instance *); 1616 static void issue_cmd_ppc(struct megasas_cmd *, struct megasas_instance *); 1617 static int issue_cmd_in_poll_mode_xscale(struct megasas_instance *, 1618 struct megasas_cmd *); 1619 static int issue_cmd_in_poll_mode_ppc(struct megasas_instance *, 1620 struct megasas_cmd *); 1621 static int issue_cmd_in_sync_mode_xscale(struct megasas_instance *, 1622 struct megasas_cmd *); 1623 static int issue_cmd_in_sync_mode_ppc(struct megasas_instance *, 1624 struct megasas_cmd *); 1625 static void enable_intr_xscale(struct megasas_instance *); 1626 static void enable_intr_ppc(struct megasas_instance *); 1627 static void disable_intr_xscale(struct megasas_instance *); 1628 static void disable_intr_ppc(struct megasas_instance *); 1629 static int intr_ack_xscale(struct megasas_instance *); 1630 static int intr_ack_ppc(struct megasas_instance *); 1631 static int mfi_state_transition_to_ready(struct megasas_instance *); 1632 static void destroy_mfi_frame_pool(struct megasas_instance *); 1633 static int create_mfi_frame_pool(struct megasas_instance *); 1634 static int megasas_dma_alloc(struct megasas_instance *, struct scsi_pkt *, 1635 struct buf *, int, int (*)()); 1636 static int megasas_dma_move(struct megasas_instance *, 1637 struct scsi_pkt *, struct buf *); 1638 static void flush_cache(struct megasas_instance *instance); 1639 static void display_scsi_inquiry(caddr_t); 1640 static int start_mfi_aen(struct megasas_instance *instance); 1641 static int handle_drv_ioctl(struct megasas_instance *instance, 1642 struct megasas_ioctl *ioctl, int mode); 1643 static int handle_mfi_ioctl(struct megasas_instance *instance, 1644 struct megasas_ioctl *ioctl, int mode); 1645 static int handle_mfi_aen(struct megasas_instance *instance, 1646 struct megasas_aen *aen); 1647 static void fill_up_drv_ver(struct megasas_drv_ver *dv); 1648 #ifndef lint 1649 static void megasas_minphys(struct buf *bp); 1650 #endif 1651 static struct megasas_cmd *build_cmd(struct megasas_instance *instance, 1652 struct scsi_address *ap, struct scsi_pkt *pkt, 1653 uchar_t *cmd_done); 1654 static int wait_for_outstanding(struct megasas_instance *instance); 1655 static int register_mfi_aen(struct megasas_instance *instance, 1656 uint32_t seq_num, uint32_t class_locale_word); 1657 static int issue_mfi_pthru(struct megasas_instance *instance, struct 1658 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1659 static int issue_mfi_dcmd(struct megasas_instance *instance, struct 1660 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1661 static int issue_mfi_smp(struct megasas_instance *instance, struct 1662 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1663 static int issue_mfi_stp(struct megasas_instance *instance, struct 1664 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1665 static int abort_aen_cmd(struct megasas_instance *instance, 1666 struct megasas_cmd *cmd_to_abort); 1667 #if defined(NOT_YET) && !defined(lint) 1668 static void io_timeout_checker(void *instance); 1669 #endif 1670 1671 static int megasas_common_check(struct megasas_instance *instance, 1672 struct megasas_cmd *cmd); 1673 1674 static void megasas_fm_init(struct megasas_instance *instance); 1675 static void megasas_fm_fini(struct megasas_instance *instance); 1676 static int megasas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 1677 const void *); 1678 static void megasas_fm_ereport(struct megasas_instance *instance, 1679 char *detail); 1680 static int megasas_check_dma_handle(ddi_dma_handle_t handle); 1681 static int megasas_check_acc_handle(ddi_acc_handle_t handle); 1682 1683 #ifdef __cplusplus 1684 } 1685 #endif 1686 1687 #endif /* _MEGARAID_SAS_H_ */ 1688