1 /* 2 * megaraid_sas.h: header for mega_sas 3 * 4 * Solaris MegaRAID driver for SAS controllers 5 * Copyright (c) 2004-2008, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the author nor the names of its contributors may be 19 * used to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 * DAMAGE. 34 */ 35 36 /* 37 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 38 * Use is subject to license terms. 39 */ 40 41 #ifndef _MEGARAID_SAS_H_ 42 #define _MEGARAID_SAS_H_ 43 44 #pragma ident "%Z%%M% %I% %E% SMI" 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #include <sys/scsi/scsi.h> 51 #include "list.h" 52 53 #pragma pack(1) 54 55 /* 56 * MegaRAID SAS Driver meta data 57 */ 58 #define MEGASAS_VERSION "00.00.01.21" 59 #define MEGASAS_RELDATE "Feb 19, 2008" 60 61 #define MEGASAS_TRUE 1 62 #define MEGASAS_FALSE 0 63 64 /* 65 * MegaRAID device id conversion definitions. 66 */ 67 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT) 68 69 /* 70 * MegaRAID SAS supported controllers 71 */ 72 #define PCI_DEVICE_ID_LSI_1064 0x0411 73 #define PCI_DEVICE_ID_LSI_1078 0x0060 74 75 #define PCI_DEVICE_ID_DELL_PERC5 0x0015 76 #define PCI_DEVICE_ID_DELL_SAS5 0x0054 77 78 #define PCI_SUBSYSTEM_DELL_PERC5E 0x1F01 79 #define PCI_SUBSYSTEM_DELL_PERC5I 0x1F02 80 #define PCI_SUBSYSTEM_DELL_PERC5I_INTEGRATED 0x1F03 81 #define PCI_SUBSYSTEM_DELL_SAS5I 0x1F05 82 #define PCI_SUBSYSTEM_DELL_SAS5I_INTEGRATED 0x1F06 83 84 #define PCI_SUB_DEVICEID_FSC 0x1081 85 #define PCI_SUB_VENDORID_FSC 0x1734 86 87 #define REGISTER_SET_IO (1) 88 89 #define MEGASAS_MAX_SGE_CNT 0x50 90 91 #define MEGASAS_IOCTL_DRIVER 0x12341234 92 #define MEGASAS_IOCTL_FIRMWARE 0x12345678 93 #define MEGASAS_IOCTL_AEN 0x87654321 94 95 #define MEGASAS_1_SECOND 1000000 96 /* 97 * ===================================== 98 * MegaRAID SAS MFI firmware definitions 99 * ===================================== 100 */ 101 /* 102 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 103 * protocol between the software and firmware. Commands are issued using 104 * "message frames" 105 */ 106 107 /* 108 * FW posts its state in upper 4 bits of outbound_msg_0 register 109 */ 110 #define MFI_STATE_MASK 0xF0000000 111 #define MFI_STATE_UNDEFINED 0x00000000 112 #define MFI_STATE_BB_INIT 0x10000000 113 #define MFI_STATE_FW_INIT 0x40000000 114 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 115 #define MFI_STATE_FW_INIT_2 0x70000000 116 #define MFI_STATE_DEVICE_SCAN 0x80000000 117 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 118 #define MFI_STATE_FLUSH_CACHE 0xA0000000 119 #define MFI_STATE_READY 0xB0000000 120 #define MFI_STATE_OPERATIONAL 0xC0000000 121 #define MFI_STATE_FAULT 0xF0000000 122 123 #define MEGAMFI_FRAME_SIZE 64 124 125 /* 126 * During FW init, clear pending cmds & reset state using inbound_msg_0 127 * 128 * ABORT : Abort all pending cmds 129 * READY : Move from OPERATIONAL to READY state; discard queue info 130 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 131 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 132 */ 133 #define MFI_INIT_ABORT 0x00000001 134 #define MFI_INIT_READY 0x00000002 135 #define MFI_INIT_MFIMODE 0x00000004 136 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 137 #define MFI_INIT_HOTPLUG 0x00000010 138 #define MFI_STOP_ADP 0x00000020 139 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT 140 141 /* 142 * MFI frame flags 143 */ 144 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 145 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 146 #define MFI_FRAME_SGL32 0x0000 147 #define MFI_FRAME_SGL64 0x0002 148 #define MFI_FRAME_SENSE32 0x0000 149 #define MFI_FRAME_SENSE64 0x0004 150 #define MFI_FRAME_DIR_NONE 0x0000 151 #define MFI_FRAME_DIR_WRITE 0x0008 152 #define MFI_FRAME_DIR_READ 0x0010 153 #define MFI_FRAME_DIR_BOTH 0x0018 154 155 /* 156 * Definition for cmd_status 157 */ 158 #define MFI_CMD_STATUS_POLL_MODE 0xFF 159 160 /* 161 * MFI command opcodes 162 */ 163 #define MFI_CMD_OP_INIT 0x00 164 #define MFI_CMD_OP_LD_READ 0x01 165 #define MFI_CMD_OP_LD_WRITE 0x02 166 #define MFI_CMD_OP_LD_SCSI 0x03 167 #define MFI_CMD_OP_PD_SCSI 0x04 168 #define MFI_CMD_OP_DCMD 0x05 169 #define MFI_CMD_OP_ABORT 0x06 170 #define MFI_CMD_OP_SMP 0x07 171 #define MFI_CMD_OP_STP 0x08 172 173 #define MR_DCMD_CTRL_GET_INFO 0x01010000 174 175 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 176 #define MR_FLUSH_CTRL_CACHE 0x01 177 #define MR_FLUSH_DISK_CACHE 0x02 178 179 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 180 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 181 182 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 183 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 184 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 185 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 186 187 /* 188 * Solaris Specific MAX values 189 */ 190 #define MAX_SGL 24 191 /* 192 * MFI command completion codes 193 */ 194 enum MFI_STAT { 195 MFI_STAT_OK = 0x00, 196 MFI_STAT_INVALID_CMD = 0x01, 197 MFI_STAT_INVALID_DCMD = 0x02, 198 MFI_STAT_INVALID_PARAMETER = 0x03, 199 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 200 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 201 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 202 MFI_STAT_APP_IN_USE = 0x07, 203 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 204 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 205 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 206 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 207 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 208 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 209 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 210 MFI_STAT_FLASH_BUSY = 0x0f, 211 MFI_STAT_FLASH_ERROR = 0x10, 212 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 213 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 214 MFI_STAT_FLASH_NOT_OPEN = 0x13, 215 MFI_STAT_FLASH_NOT_STARTED = 0x14, 216 MFI_STAT_FLUSH_FAILED = 0x15, 217 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 218 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 219 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 220 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 221 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 222 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 223 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 224 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 225 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 226 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 227 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 228 MFI_STAT_MFC_HW_ERROR = 0x21, 229 MFI_STAT_NO_HW_PRESENT = 0x22, 230 MFI_STAT_NOT_FOUND = 0x23, 231 MFI_STAT_NOT_IN_ENCL = 0x24, 232 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 233 MFI_STAT_PD_TYPE_WRONG = 0x26, 234 MFI_STAT_PR_DISABLED = 0x27, 235 MFI_STAT_ROW_INDEX_INVALID = 0x28, 236 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 237 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 238 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 239 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 240 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 241 MFI_STAT_SCSI_IO_FAILED = 0x2e, 242 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 243 MFI_STAT_SHUTDOWN_FAILED = 0x30, 244 MFI_STAT_TIME_NOT_SET = 0x31, 245 MFI_STAT_WRONG_STATE = 0x32, 246 MFI_STAT_INVALID_STATUS = 0xFF 247 }; 248 249 enum MR_EVT_CLASS { 250 MR_EVT_CLASS_DEBUG = -2, 251 MR_EVT_CLASS_PROGRESS = -1, 252 MR_EVT_CLASS_INFO = 0, 253 MR_EVT_CLASS_WARNING = 1, 254 MR_EVT_CLASS_CRITICAL = 2, 255 MR_EVT_CLASS_FATAL = 3, 256 MR_EVT_CLASS_DEAD = 4 257 }; 258 259 enum MR_EVT_LOCALE { 260 MR_EVT_LOCALE_LD = 0x0001, 261 MR_EVT_LOCALE_PD = 0x0002, 262 MR_EVT_LOCALE_ENCL = 0x0004, 263 MR_EVT_LOCALE_BBU = 0x0008, 264 MR_EVT_LOCALE_SAS = 0x0010, 265 MR_EVT_LOCALE_CTRL = 0x0020, 266 MR_EVT_LOCALE_CONFIG = 0x0040, 267 MR_EVT_LOCALE_CLUSTER = 0x0080, 268 MR_EVT_LOCALE_ALL = 0xffff 269 }; 270 271 enum MR_EVT_ARGS { 272 MR_EVT_ARGS_NONE, 273 MR_EVT_ARGS_CDB_SENSE, 274 MR_EVT_ARGS_LD, 275 MR_EVT_ARGS_LD_COUNT, 276 MR_EVT_ARGS_LD_LBA, 277 MR_EVT_ARGS_LD_OWNER, 278 MR_EVT_ARGS_LD_LBA_PD_LBA, 279 MR_EVT_ARGS_LD_PROG, 280 MR_EVT_ARGS_LD_STATE, 281 MR_EVT_ARGS_LD_STRIP, 282 MR_EVT_ARGS_PD, 283 MR_EVT_ARGS_PD_ERR, 284 MR_EVT_ARGS_PD_LBA, 285 MR_EVT_ARGS_PD_LBA_LD, 286 MR_EVT_ARGS_PD_PROG, 287 MR_EVT_ARGS_PD_STATE, 288 MR_EVT_ARGS_PCI, 289 MR_EVT_ARGS_RATE, 290 MR_EVT_ARGS_STR, 291 MR_EVT_ARGS_TIME, 292 MR_EVT_ARGS_ECC 293 }; 294 295 /* 296 * SAS controller properties 297 */ 298 struct megasas_ctrl_prop { 299 uint16_t seq_num; 300 uint16_t pred_fail_poll_interval; 301 uint16_t intr_throttle_count; 302 uint16_t intr_throttle_timeouts; 303 304 uint8_t rebuild_rate; 305 uint8_t patrol_read_rate; 306 uint8_t bgi_rate; 307 uint8_t cc_rate; 308 uint8_t recon_rate; 309 310 uint8_t cache_flush_interval; 311 312 uint8_t spinup_drv_count; 313 uint8_t spinup_delay; 314 315 uint8_t cluster_enable; 316 uint8_t coercion_mode; 317 uint8_t disk_write_cache_disable; 318 uint8_t alarm_enable; 319 320 uint8_t reserved[44]; 321 }; 322 323 /* 324 * SAS controller information 325 */ 326 struct megasas_ctrl_info { 327 /* PCI device information */ 328 struct { 329 uint16_t vendor_id; 330 uint16_t device_id; 331 uint16_t sub_vendor_id; 332 uint16_t sub_device_id; 333 uint8_t reserved[24]; 334 } pci; 335 336 /* Host interface information */ 337 struct { 338 uint8_t PCIX : 1; 339 uint8_t PCIE : 1; 340 uint8_t iSCSI : 1; 341 uint8_t SAS_3G : 1; 342 uint8_t reserved_0 : 4; 343 uint8_t reserved_1[6]; 344 uint8_t port_count; 345 uint64_t port_addr[8]; 346 } host_interface; 347 348 /* Device (backend) interface information */ 349 struct { 350 uint8_t SPI : 1; 351 uint8_t SAS_3G : 1; 352 uint8_t SATA_1_5G : 1; 353 uint8_t SATA_3G : 1; 354 uint8_t reserved_0 : 4; 355 uint8_t reserved_1[6]; 356 uint8_t port_count; 357 uint64_t port_addr[8]; 358 } device_interface; 359 360 /* List of components residing in flash. All str are null terminated */ 361 uint32_t image_check_word; 362 uint32_t image_component_count; 363 364 struct { 365 char name[8]; 366 char version[32]; 367 char build_date[16]; 368 char built_time[16]; 369 } image_component[8]; 370 371 /* 372 * List of flash components that have been flashed on the card, but 373 * are not in use, pending reset of the adapter. This list will be 374 * empty if a flash operation has not occurred. All stings are null 375 * terminated 376 */ 377 uint32_t pending_image_component_count; 378 379 struct { 380 char name[8]; 381 char version[32]; 382 char build_date[16]; 383 char build_time[16]; 384 } pending_image_component[8]; 385 386 uint8_t max_arms; 387 uint8_t max_spans; 388 uint8_t max_arrays; 389 uint8_t max_lds; 390 391 char product_name[80]; 392 char serial_no[32]; 393 394 /* 395 * Other physical/controller/operation information. Indicates the 396 * presence of the hardware 397 */ 398 struct { 399 uint32_t bbu : 1; 400 uint32_t alarm : 1; 401 uint32_t nvram : 1; 402 uint32_t uart : 1; 403 uint32_t reserved : 28; 404 } hw_present; 405 406 uint32_t current_fw_time; 407 408 /* Maximum data transfer sizes */ 409 uint16_t max_concurrent_cmds; 410 uint16_t max_sge_count; 411 uint32_t max_request_size; 412 413 /* Logical and physical device counts */ 414 uint16_t ld_present_count; 415 uint16_t ld_degraded_count; 416 uint16_t ld_offline_count; 417 418 uint16_t pd_present_count; 419 uint16_t pd_disk_present_count; 420 uint16_t pd_disk_pred_failure_count; 421 uint16_t pd_disk_failed_count; 422 423 /* Memory size information */ 424 uint16_t nvram_size; 425 uint16_t memory_size; 426 uint16_t flash_size; 427 428 /* Error counters */ 429 uint16_t mem_correctable_error_count; 430 uint16_t mem_uncorrectable_error_count; 431 432 /* Cluster information */ 433 uint8_t cluster_permitted; 434 uint8_t cluster_active; 435 uint8_t reserved_1[2]; 436 437 /* Controller capabilities structures */ 438 struct { 439 uint32_t raid_level_0 : 1; 440 uint32_t raid_level_1 : 1; 441 uint32_t raid_level_5 : 1; 442 uint32_t raid_level_1E : 1; 443 uint32_t reserved : 28; 444 } raid_levels; 445 446 struct { 447 uint32_t rbld_rate : 1; 448 uint32_t cc_rate : 1; 449 uint32_t bgi_rate : 1; 450 uint32_t recon_rate : 1; 451 uint32_t patrol_rate : 1; 452 uint32_t alarm_control : 1; 453 uint32_t cluster_supported : 1; 454 uint32_t bbu : 1; 455 uint32_t spanning_allowed : 1; 456 uint32_t dedicated_hotspares : 1; 457 uint32_t revertible_hotspares : 1; 458 uint32_t foreign_config_import : 1; 459 uint32_t self_diagnostic : 1; 460 uint32_t reserved : 19; 461 } adapter_operations; 462 463 struct { 464 uint32_t read_policy : 1; 465 uint32_t write_policy : 1; 466 uint32_t io_policy : 1; 467 uint32_t access_policy : 1; 468 uint32_t reserved : 28; 469 } ld_operations; 470 471 struct { 472 uint8_t min; 473 uint8_t max; 474 uint8_t reserved[2]; 475 } stripe_size_operations; 476 477 struct { 478 uint32_t force_online : 1; 479 uint32_t force_offline : 1; 480 uint32_t force_rebuild : 1; 481 uint32_t reserved : 29; 482 } pd_operations; 483 484 struct { 485 uint32_t ctrl_supports_sas : 1; 486 uint32_t ctrl_supports_sata : 1; 487 uint32_t allow_mix_in_encl : 1; 488 uint32_t allow_mix_in_ld : 1; 489 uint32_t allow_sata_in_cluster : 1; 490 uint32_t reserved : 27; 491 } pd_mix_support; 492 493 /* Include the controller properties (changeable items) */ 494 uint8_t reserved_2[12]; 495 struct megasas_ctrl_prop properties; 496 497 uint8_t pad[0x800 - 0x640]; 498 }; 499 500 /* 501 * =============================== 502 * MegaRAID SAS driver definitions 503 * =============================== 504 */ 505 #define MEGADRV_MAX_NUM_CMD 1024 506 507 #define MEGADRV_MAX_PD_CHANNELS 2 508 #define MEGADRV_MAX_LD_CHANNELS 2 509 #define MEGADRV_MAX_CHANNELS (MEGADRV_MAX_PD_CHANNELS + \ 510 MEGADRV_MAX_LD_CHANNELS) 511 #define MEGADRV_MAX_DEV_PER_CHANNEL 128 512 #define MEGADRV_DEFAULT_INIT_ID -1 513 #define MEGADRV_MAX_CMD_PER_LUN 1000 514 #define MEGADRV_MAX_LUN 8 515 #define MEGADRV_MAX_LD 64 516 517 #define MEGADRV_RESET_WAIT_TIME 300 518 #define MEGADRV_RESET_NOTICE_INTERVAL 5 519 520 #define MEGASAS_IOCTL_CMD 0 521 522 /* 523 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 524 * SGLs based on the size of dma_addr_t 525 */ 526 #define IS_DMA64 (sizeof (dma_addr_t) == 8) 527 528 /* 529 * All MFI register set macros accept megasas_register_set* 530 */ 531 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \ 532 (uint32_t *)((instance)->regmap + 0x10), (v)) 533 534 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \ 535 (uint32_t *)((instance)->regmap + 0x18)) 536 537 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \ 538 (uint32_t *)((instance)->regmap + 0x20), (v)) 539 540 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \ 541 (uint32_t *)((instance)->regmap + 0x20)) 542 543 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \ 544 (uint32_t *)((instance)->regmap + 0x30), (v)) 545 546 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \ 547 (uint32_t *)((instance)->regmap + 0x30)) 548 549 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \ 550 (uint32_t *)((instance)->regmap + 0x34), (v)) 551 552 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \ 553 (uint32_t *)((instance)->regmap + 0x34)) 554 555 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 556 (uint32_t *)((instance)->regmap + 0x40), (v)) 557 558 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \ 559 (uint32_t *)((instance)->regmap + 0xA0), (v)) 560 561 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \ 562 (uint32_t *)((instance)->regmap + 0xB0)) 563 564 /* 565 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data 566 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs 567 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled. 568 */ 569 #define MFI_OB_INTR_STATUS_MASK 0x00000002 570 571 /* 572 * This MFI_REPLY_1078_MESSAGE_INTR flag is used also 573 * in enable_intr_pcc also. Hence bit 2, i.e. 0x4 has 574 * been set in this flag along with bit 31. 575 */ 576 #define MFI_REPLY_1078_MESSAGE_INTR 0x80000004 577 578 #define MFI_POLL_TIMEOUT_SECS 60 579 580 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \ 581 (uint32_t *)((instance)->regmap + 0x34), 1) 582 #define MFI_DISABLE_INTR(instance) \ 583 { \ 584 uint32_t disable = 1; \ 585 uint32_t mask = ddi_get32((instance)->regmap_handle, \ 586 (uint32_t *)((instance)->regmap + 0x34)); \ 587 mask &= ~disable; \ 588 ddi_put32((instance)->regmap_handle, \ 589 (uint32_t *)((instance)->regmap + 0x34), mask); \ 590 } 591 592 593 struct megasas_register_set { 594 uint32_t reserved_0[4]; /* 0000h */ 595 596 uint32_t inbound_msg_0; /* 0010h */ 597 uint32_t inbound_msg_1; /* 0014h */ 598 uint32_t outbound_msg_0; /* 0018h */ 599 uint32_t outbound_msg_1; /* 001Ch */ 600 601 uint32_t inbound_doorbell; /* 0020h */ 602 uint32_t inbound_intr_status; /* 0024h */ 603 uint32_t inbound_intr_mask; /* 0028h */ 604 605 uint32_t outbound_doorbell; /* 002Ch */ 606 uint32_t outbound_intr_status; /* 0030h */ 607 uint32_t outbound_intr_mask; /* 0034h */ 608 609 uint32_t reserved_1[2]; /* 0038h */ 610 611 uint32_t inbound_queue_port; /* 0040h */ 612 uint32_t outbound_queue_port; /* 0044h */ 613 614 uint32_t reserved_2[22]; /* 0048h */ 615 616 uint32_t outbound_doorbell_clear; /* 00A0h */ 617 618 uint32_t reserved_3[3]; /* 00A4h */ 619 620 uint32_t outbound_scratch_pad; /* 00B0h */ 621 622 uint32_t reserved_4[3]; /* 00B4h */ 623 624 uint32_t inbound_low_queue_port; /* 00C0h */ 625 626 uint32_t inbound_high_queue_port; /* 00C4h */ 627 628 uint32_t reserved_5; /* 00C8h */ 629 uint32_t index_registers[820]; /* 00CCh */ 630 }; 631 632 struct megasas_sge32 { 633 uint32_t phys_addr; 634 uint32_t length; 635 }; 636 637 struct megasas_sge64 { 638 uint64_t phys_addr; 639 uint32_t length; 640 }; 641 642 union megasas_sgl { 643 struct megasas_sge32 sge32[1]; 644 struct megasas_sge64 sge64[1]; 645 }; 646 647 struct megasas_header { 648 uint8_t cmd; /* 00h */ 649 uint8_t sense_len; /* 01h */ 650 uint8_t cmd_status; /* 02h */ 651 uint8_t scsi_status; /* 03h */ 652 653 uint8_t target_id; /* 04h */ 654 uint8_t lun; /* 05h */ 655 uint8_t cdb_len; /* 06h */ 656 uint8_t sge_count; /* 07h */ 657 658 uint32_t context; /* 08h */ 659 uint32_t pad_0; /* 0Ch */ 660 661 uint16_t flags; /* 10h */ 662 uint16_t timeout; /* 12h */ 663 uint32_t data_xferlen; /* 14h */ 664 }; 665 666 union megasas_sgl_frame { 667 struct megasas_sge32 sge32[8]; 668 struct megasas_sge64 sge64[5]; 669 }; 670 671 struct megasas_init_frame { 672 uint8_t cmd; /* 00h */ 673 uint8_t reserved_0; /* 01h */ 674 uint8_t cmd_status; /* 02h */ 675 676 uint8_t reserved_1; /* 03h */ 677 uint32_t reserved_2; /* 04h */ 678 679 uint32_t context; /* 08h */ 680 uint32_t pad_0; /* 0Ch */ 681 682 uint16_t flags; /* 10h */ 683 uint16_t reserved_3; /* 12h */ 684 uint32_t data_xfer_len; /* 14h */ 685 686 uint32_t queue_info_new_phys_addr_lo; /* 18h */ 687 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */ 688 uint32_t queue_info_old_phys_addr_lo; /* 20h */ 689 uint32_t queue_info_old_phys_addr_hi; /* 24h */ 690 691 uint32_t reserved_4[6]; /* 28h */ 692 }; 693 694 struct megasas_init_queue_info { 695 uint32_t init_flags; /* 00h */ 696 uint32_t reply_queue_entries; /* 04h */ 697 698 uint32_t reply_queue_start_phys_addr_lo; /* 08h */ 699 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */ 700 uint32_t producer_index_phys_addr_lo; /* 10h */ 701 uint32_t producer_index_phys_addr_hi; /* 14h */ 702 uint32_t consumer_index_phys_addr_lo; /* 18h */ 703 uint32_t consumer_index_phys_addr_hi; /* 1Ch */ 704 }; 705 706 struct megasas_io_frame { 707 uint8_t cmd; /* 00h */ 708 uint8_t sense_len; /* 01h */ 709 uint8_t cmd_status; /* 02h */ 710 uint8_t scsi_status; /* 03h */ 711 712 uint8_t target_id; /* 04h */ 713 uint8_t access_byte; /* 05h */ 714 uint8_t reserved_0; /* 06h */ 715 uint8_t sge_count; /* 07h */ 716 717 uint32_t context; /* 08h */ 718 uint32_t pad_0; /* 0Ch */ 719 720 uint16_t flags; /* 10h */ 721 uint16_t timeout; /* 12h */ 722 uint32_t lba_count; /* 14h */ 723 724 uint32_t sense_buf_phys_addr_lo; /* 18h */ 725 uint32_t sense_buf_phys_addr_hi; /* 1Ch */ 726 727 uint32_t start_lba_lo; /* 20h */ 728 uint32_t start_lba_hi; /* 24h */ 729 730 union megasas_sgl sgl; /* 28h */ 731 }; 732 733 struct megasas_pthru_frame { 734 uint8_t cmd; /* 00h */ 735 uint8_t sense_len; /* 01h */ 736 uint8_t cmd_status; /* 02h */ 737 uint8_t scsi_status; /* 03h */ 738 739 uint8_t target_id; /* 04h */ 740 uint8_t lun; /* 05h */ 741 uint8_t cdb_len; /* 06h */ 742 uint8_t sge_count; /* 07h */ 743 744 uint32_t context; /* 08h */ 745 uint32_t pad_0; /* 0Ch */ 746 747 uint16_t flags; /* 10h */ 748 uint16_t timeout; /* 12h */ 749 uint32_t data_xfer_len; /* 14h */ 750 751 uint32_t sense_buf_phys_addr_lo; /* 18h */ 752 uint32_t sense_buf_phys_addr_hi; /* 1Ch */ 753 754 uint8_t cdb[16]; /* 20h */ 755 union megasas_sgl sgl; /* 30h */ 756 }; 757 758 struct megasas_dcmd_frame { 759 uint8_t cmd; /* 00h */ 760 uint8_t reserved_0; /* 01h */ 761 uint8_t cmd_status; /* 02h */ 762 uint8_t reserved_1[4]; /* 03h */ 763 uint8_t sge_count; /* 07h */ 764 765 uint32_t context; /* 08h */ 766 uint32_t pad_0; /* 0Ch */ 767 768 uint16_t flags; /* 10h */ 769 uint16_t timeout; /* 12h */ 770 771 uint32_t data_xfer_len; /* 14h */ 772 uint32_t opcode; /* 18h */ 773 774 /* uint8_t mbox[12]; */ /* 1Ch */ 775 union { /* 1Ch */ 776 uint8_t b[12]; 777 uint16_t s[6]; 778 uint32_t w[3]; 779 } mbox; 780 781 union megasas_sgl sgl; /* 28h */ 782 }; 783 784 struct megasas_abort_frame { 785 uint8_t cmd; /* 00h */ 786 uint8_t reserved_0; /* 01h */ 787 uint8_t cmd_status; /* 02h */ 788 789 uint8_t reserved_1; /* 03h */ 790 uint32_t reserved_2; /* 04h */ 791 792 uint32_t context; /* 08h */ 793 uint32_t pad_0; /* 0Ch */ 794 795 uint16_t flags; /* 10h */ 796 uint16_t reserved_3; /* 12h */ 797 uint32_t reserved_4; /* 14h */ 798 799 uint32_t abort_context; /* 18h */ 800 uint32_t pad_1; /* 1Ch */ 801 802 uint32_t abort_mfi_phys_addr_lo; /* 20h */ 803 uint32_t abort_mfi_phys_addr_hi; /* 24h */ 804 805 uint32_t reserved_5[6]; /* 28h */ 806 }; 807 808 struct megasas_smp_frame { 809 uint8_t cmd; /* 00h */ 810 uint8_t reserved_1; /* 01h */ 811 uint8_t cmd_status; /* 02h */ 812 uint8_t connection_status; /* 03h */ 813 814 uint8_t reserved_2[3]; /* 04h */ 815 uint8_t sge_count; /* 07h */ 816 817 uint32_t context; /* 08h */ 818 uint32_t pad_0; /* 0Ch */ 819 820 uint16_t flags; /* 10h */ 821 uint16_t timeout; /* 12h */ 822 823 uint32_t data_xfer_len; /* 14h */ 824 825 uint64_t sas_addr; /* 20h */ 826 827 union megasas_sgl sgl[2]; /* 28h */ 828 }; 829 830 struct megasas_stp_frame { 831 uint8_t cmd; /* 00h */ 832 uint8_t reserved_1; /* 01h */ 833 uint8_t cmd_status; /* 02h */ 834 uint8_t connection_status; /* 03h */ 835 836 uint8_t target_id; /* 04h */ 837 uint8_t reserved_2[2]; /* 04h */ 838 uint8_t sge_count; /* 07h */ 839 840 uint32_t context; /* 08h */ 841 uint32_t pad_0; /* 0Ch */ 842 843 uint16_t flags; /* 10h */ 844 uint16_t timeout; /* 12h */ 845 846 uint32_t data_xfer_len; /* 14h */ 847 848 uint16_t fis[10]; /* 28h */ 849 uint32_t stp_flags; /* 3C */ 850 union megasas_sgl sgl; /* 40 */ 851 }; 852 853 union megasas_frame { 854 struct megasas_header hdr; 855 struct megasas_init_frame init; 856 struct megasas_io_frame io; 857 struct megasas_pthru_frame pthru; 858 struct megasas_dcmd_frame dcmd; 859 struct megasas_abort_frame abort; 860 struct megasas_smp_frame smp; 861 struct megasas_stp_frame stp; 862 863 uint8_t raw_bytes[64]; 864 }; 865 866 union megasas_evt_class_locale { 867 struct { 868 uint16_t locale; 869 uint8_t reserved; 870 int8_t class; 871 } members; 872 873 uint32_t word; 874 }; 875 876 struct megasas_evt_log_info { 877 uint32_t newest_seq_num; 878 uint32_t oldest_seq_num; 879 uint32_t clear_seq_num; 880 uint32_t shutdown_seq_num; 881 uint32_t boot_seq_num; 882 }; 883 884 struct megasas_progress { 885 uint16_t progress; 886 uint16_t elapsed_seconds; 887 }; 888 889 struct megasas_evtarg_ld { 890 uint16_t target_id; 891 uint8_t ld_index; 892 uint8_t reserved; 893 }; 894 895 struct megasas_evtarg_pd { 896 uint16_t device_id; 897 uint8_t encl_index; 898 uint8_t slot_number; 899 }; 900 901 struct megasas_evt_detail { 902 uint32_t seq_num; 903 uint32_t time_stamp; 904 uint32_t code; 905 union megasas_evt_class_locale cl; 906 uint8_t arg_type; 907 uint8_t reserved1[15]; 908 909 union { 910 struct { 911 struct megasas_evtarg_pd pd; 912 uint8_t cdb_length; 913 uint8_t sense_length; 914 uint8_t reserved[2]; 915 uint8_t cdb[16]; 916 uint8_t sense[64]; 917 } cdbSense; 918 919 struct megasas_evtarg_ld ld; 920 921 struct { 922 struct megasas_evtarg_ld ld; 923 uint64_t count; 924 } ld_count; 925 926 struct { 927 uint64_t lba; 928 struct megasas_evtarg_ld ld; 929 } ld_lba; 930 931 struct { 932 struct megasas_evtarg_ld ld; 933 uint32_t prevOwner; 934 uint32_t newOwner; 935 } ld_owner; 936 937 struct { 938 uint64_t ld_lba; 939 uint64_t pd_lba; 940 struct megasas_evtarg_ld ld; 941 struct megasas_evtarg_pd pd; 942 } ld_lba_pd_lba; 943 944 struct { 945 struct megasas_evtarg_ld ld; 946 struct megasas_progress prog; 947 } ld_prog; 948 949 struct { 950 struct megasas_evtarg_ld ld; 951 uint32_t prev_state; 952 uint32_t new_state; 953 } ld_state; 954 955 struct { 956 uint64_t strip; 957 struct megasas_evtarg_ld ld; 958 } ld_strip; 959 960 struct megasas_evtarg_pd pd; 961 962 struct { 963 struct megasas_evtarg_pd pd; 964 uint32_t err; 965 } pd_err; 966 967 struct { 968 uint64_t lba; 969 struct megasas_evtarg_pd pd; 970 } pd_lba; 971 972 struct { 973 uint64_t lba; 974 struct megasas_evtarg_pd pd; 975 struct megasas_evtarg_ld ld; 976 } pd_lba_ld; 977 978 struct { 979 struct megasas_evtarg_pd pd; 980 struct megasas_progress prog; 981 } pd_prog; 982 983 struct { 984 struct megasas_evtarg_pd pd; 985 uint32_t prevState; 986 uint32_t newState; 987 } pd_state; 988 989 struct { 990 uint16_t vendorId; 991 uint16_t deviceId; 992 uint16_t subVendorId; 993 uint16_t subDeviceId; 994 } pci; 995 996 uint32_t rate; 997 char str[96]; 998 999 struct { 1000 uint32_t rtc; 1001 uint32_t elapsedSeconds; 1002 } time; 1003 1004 struct { 1005 uint32_t ecar; 1006 uint32_t elog; 1007 char str[64]; 1008 } ecc; 1009 1010 uint8_t b[96]; 1011 uint16_t s[48]; 1012 uint32_t w[24]; 1013 uint64_t d[12]; 1014 } args; 1015 1016 char description[128]; 1017 1018 }; 1019 1020 /* only 63 are usable by the application */ 1021 #define MAX_LOGICAL_DRIVES 64 1022 /* only 255 physical devices may be used */ 1023 #define MAX_PHYSICAL_DEVICES 256 1024 #define MAX_PD_PER_ENCLOSURE 64 1025 /* maximum disks per array */ 1026 #define MAX_ROW_SIZE 32 1027 /* maximum spans per logical drive */ 1028 #define MAX_SPAN_DEPTH 8 1029 /* maximum number of arrays a hot spare may be dedicated to */ 1030 #define MAX_ARRAYS_DEDICATED 16 1031 /* maximum number of arrays which may exist */ 1032 #define MAX_ARRAYS 128 1033 /* maximum number of foreign configs that may ha managed at once */ 1034 #define MAX_FOREIGN_CONFIGS 8 1035 /* maximum spares (global and dedicated combined) */ 1036 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES 1037 /* maximum possible Target IDs (i.e. 0 to 63) */ 1038 #define MAX_TARGET_ID 63 1039 /* maximum number of supported enclosures */ 1040 #define MAX_ENCLOSURES 32 1041 /* maximum number of PHYs per controller */ 1042 #define MAX_PHYS_PER_CONTROLLER 16 1043 /* maximum number of LDs per array (due to DDF limitations) */ 1044 #define MAX_LDS_PER_ARRAY 16 1045 1046 /* 1047 * ----------------------------------------------------------------------------- 1048 * ----------------------------------------------------------------------------- 1049 * 1050 * Logical Drive commands 1051 * 1052 * ----------------------------------------------------------------------------- 1053 * ----------------------------------------------------------------------------- 1054 */ 1055 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */ 1056 1057 /* 1058 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST 1059 * dcmd.mbox - reserved 1060 * dcmd.sge IN - ptr to returned MR_LD_LIST structure 1061 * Desc: Return the logical drive list structure 1062 * Status: No error 1063 */ 1064 1065 /* 1066 * defines the logical drive reference structure 1067 */ 1068 typedef union _MR_LD_REF { /* LD reference structure */ 1069 struct { 1070 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */ 1071 uint8_t reserved; /* reserved to make in line with MR_PD_REF */ 1072 uint16_t seqNum; /* Sequence Number */ 1073 } ld_ref; 1074 uint32_t ref; /* shorthand reference to full 32-bits */ 1075 } MR_LD_REF; /* 4 bytes */ 1076 1077 /* 1078 * defines the logical drive list structure 1079 */ 1080 typedef struct _MR_LD_LIST { 1081 uint32_t ldCount; /* number of LDs */ 1082 uint32_t reserved; /* pad to 8-byte boundary */ 1083 struct { 1084 MR_LD_REF ref; /* LD reference */ 1085 uint8_t state; /* current LD state (MR_LD_STATE) */ 1086 uint8_t reserved[3]; /* pad to 8-byte boundary */ 1087 uint64_t size; /* LD size */ 1088 } ldList[MAX_LOGICAL_DRIVES]; 1089 } MR_LD_LIST; 1090 /* 4 + 4 + (MAX_LOGICAL_DRIVES * 16), for 40LD it is = 648 bytes */ 1091 1092 #define DMA_OBJ_ALLOCATED 1 1093 #define DMA_OBJ_REALLOCATED 2 1094 #define DMA_OBJ_FREED 3 1095 1096 #pragma pack() 1097 1098 /* 1099 * dma_obj_t - Our DMA object 1100 * @param buffer : kernel virtual address 1101 * @param size : size of the data to be allocated 1102 * @param acc_handle : access handle 1103 * @param dma_handle : dma handle 1104 * @param dma_cookie : scatter-gather list 1105 * @param dma_attr : dma attributes for this buffer 1106 * 1107 * Our DMA object. The caller must initialize the size and dma attributes 1108 * (dma_attr) fields before allocating the resources. 1109 */ 1110 typedef struct { 1111 caddr_t buffer; 1112 uint32_t size; 1113 ddi_acc_handle_t acc_handle; 1114 ddi_dma_handle_t dma_handle; 1115 ddi_dma_cookie_t dma_cookie[MEGASAS_MAX_SGE_CNT]; 1116 ddi_dma_attr_t dma_attr; 1117 uint8_t status; 1118 } dma_obj_t; 1119 1120 struct megasas_instance { 1121 uint32_t *producer; 1122 uint32_t *consumer; 1123 1124 uint32_t *reply_queue; 1125 dma_obj_t mfi_internal_dma_obj; 1126 1127 uint8_t init_id; 1128 uint8_t reserved[3]; 1129 1130 uint16_t max_num_sge; 1131 uint16_t max_fw_cmds; 1132 uint32_t max_sectors_per_req; 1133 1134 struct megasas_cmd **cmd_list; 1135 1136 mlist_t cmd_pool_list; 1137 kmutex_t cmd_pool_mtx; 1138 1139 mlist_t cmd_pend_list; 1140 kmutex_t cmd_pend_mtx; 1141 1142 dma_obj_t mfi_evt_detail_obj; 1143 struct megasas_cmd *aen_cmd; 1144 1145 uint32_t aen_seq_num; 1146 uint32_t aen_class_locale_word; 1147 1148 scsi_hba_tran_t *tran; 1149 1150 kcondvar_t int_cmd_cv; 1151 kmutex_t int_cmd_mtx; 1152 1153 kcondvar_t aen_cmd_cv; 1154 kmutex_t aen_cmd_mtx; 1155 1156 kcondvar_t abort_cmd_cv; 1157 kmutex_t abort_cmd_mtx; 1158 1159 dev_info_t *dip; 1160 ddi_acc_handle_t pci_handle; 1161 1162 timeout_id_t timeout_id; 1163 uint32_t unique_id; 1164 uint16_t fw_outstanding; 1165 caddr_t regmap; 1166 ddi_acc_handle_t regmap_handle; 1167 uint8_t isr_level; 1168 ddi_iblock_cookie_t iblock_cookie; 1169 ddi_iblock_cookie_t soft_iblock_cookie; 1170 ddi_softintr_t soft_intr_id; 1171 uint8_t softint_running; 1172 kmutex_t completed_pool_mtx; 1173 mlist_t completed_pool_list; 1174 1175 caddr_t internal_buf; 1176 uint32_t internal_buf_dmac_add; 1177 uint32_t internal_buf_size; 1178 1179 uint16_t vendor_id; 1180 uint16_t device_id; 1181 uint16_t subsysvid; 1182 uint16_t subsysid; 1183 int baseaddress; 1184 char iocnode[16]; 1185 1186 struct megasas_func_ptr *func_ptr; 1187 }; 1188 1189 struct megasas_func_ptr { 1190 int (*read_fw_status_reg)(struct megasas_instance *); 1191 void (*issue_cmd)(struct megasas_cmd *, struct megasas_instance *); 1192 int (*issue_cmd_in_sync_mode)(struct megasas_instance *, 1193 struct megasas_cmd *); 1194 int (*issue_cmd_in_poll_mode)(struct megasas_instance *, 1195 struct megasas_cmd *); 1196 void (*enable_intr)(struct megasas_instance *); 1197 void (*disable_intr)(struct megasas_instance *); 1198 int (*intr_ack)(struct megasas_instance *); 1199 }; 1200 1201 /* 1202 * ### Helper routines ### 1203 */ 1204 1205 /* 1206 * con_log() - console log routine 1207 * @param level : indicates the severity of the message. 1208 * @fparam mt : format string 1209 * 1210 * con_log displays the error messages on the console based on the current 1211 * debug level. Also it attaches the appropriate kernel severity level with 1212 * the message. 1213 * 1214 * 1215 * consolge messages debug levels 1216 */ 1217 #define CL_ANN 0 /* print unconditionally, announcements */ 1218 #define CL_ANN1 1 /* No o/p */ 1219 #define CL_DLEVEL1 2 /* debug level 1, informative */ 1220 #define CL_DLEVEL2 3 /* debug level 2, verbose */ 1221 #define CL_DLEVEL3 4 /* debug level 3, very verbose */ 1222 1223 #ifdef __SUNPRO_C 1224 #define __func__ "" 1225 #endif 1226 1227 #if DEBUG 1228 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; } 1229 #else 1230 #define con_log(level, fmt) 1231 #endif /* DEBUG */ 1232 1233 /* byte-ordering macros */ 1234 #ifdef __sparc 1235 #define host_to_le16(s) ((s) & 0xFF) << 8 | ((s) & 0xFF00) >> 8 1236 #else 1237 #define host_to_le16(s) (s) 1238 #endif 1239 1240 #ifdef __sparc 1241 #define host_to_le32(l) (((l) & 0xFF) << 24 | ((l) & 0xFF00) << 8 | \ 1242 ((l) & 0xFF0000) >> 8 | ((l) & 0xFF000000) >> 24) 1243 #else 1244 #define host_to_le32(l) (l) 1245 #endif 1246 1247 #ifdef __sparc 1248 #define host_to_le64(ull) ((host_to_le32(((ull) & 0xFFFFFFFF)) << 32) | \ 1249 (host_to_le32((((ull) & 0xFFFFFFFF00000000) >> 32)))) 1250 #else 1251 #define host_to_le64(ull) (ull) 1252 #endif 1253 1254 /* 1255 * ### SCSA definitions ### 1256 */ 1257 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target) 1258 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun) 1259 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran) 1260 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1261 1262 #define TRAN2MEGA(tran) (struct megasas_instance *)(tran)->tran_hba_private) 1263 #define ADDR2MEGA(ap) (TRAN2MEGA(ADDR2TRAN(ap)) 1264 1265 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private) 1266 #define CMD2PKT(sp) ((sp)->cmd_pkt) 1267 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request)) 1268 1269 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address) 1270 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran) 1271 #define CMD2MEGA(cmd) (TRAN2MEGA(CMD2TRAN(cmd))) 1272 1273 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */ 1274 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */ 1275 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */ 1276 1277 /* 1278 * ### Data structures for ioctl inteface and internal commands ### 1279 */ 1280 1281 /* 1282 * Data direction flags 1283 */ 1284 #define UIOC_RD 0x00001 1285 #define UIOC_WR 0x00002 1286 1287 #define SCP2HOST(scp) (scp)->device->host /* to host */ 1288 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */ 1289 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */ 1290 #define SCP2TARGET(scp) (scp)->device->id /* to target */ 1291 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */ 1292 1293 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0]) 1294 #define SCP2ADAPTER(scp) \ 1295 (struct megasas_instance *)SCSIHOST2ADAP(SCP2HOST(scp)) 1296 1297 #define MEGADRV_IS_LOGICAL_SCSA(instance, acmd) \ 1298 (acmd->device_id < MEGADRV_MAX_LD) ? 1 : 0 1299 #define MEGADRV_IS_LOGICAL(ap) \ 1300 (ap->a_target < MEGADRV_MAX_LD) ? 1 : 0 1301 #define MAP_DEVICE_ID(instance, ap) \ 1302 (ap->a_target % MEGADRV_MAX_LD) 1303 /* 1304 * #define MAP_DEVICE_ID(instance,ap) \ 1305 * (ap->a_target) 1306 */ 1307 1308 #define HIGH_LEVEL_INTR 1 1309 #define NORMAL_LEVEL_INTR 0 1310 1311 /* 1312 * scsa_cmd - Per-command mega private data 1313 * @param cmd_dmahandle : dma handle 1314 * @param cmd_dmacookies : current dma cookies 1315 * @param cmd_pkt : scsi_pkt reference 1316 * @param cmd_dmacount : dma count 1317 * @param cmd_cookie : next cookie 1318 * @param cmd_ncookies : cookies per window 1319 * @param cmd_cookiecnt : cookies per sub-win 1320 * @param cmd_nwin : number of dma windows 1321 * @param cmd_curwin : current dma window 1322 * @param cmd_dma_offset : current window offset 1323 * @param cmd_dma_len : current window length 1324 * @param cmd_flags : private flags 1325 * @param cmd_cdblen : length of cdb 1326 * @param cmd_scblen : length of scb 1327 * @param cmd_buf : command buffer 1328 * @param channel : channel for scsi sub-system 1329 * @param target : target for scsi sub-system 1330 * @param lun : LUN for scsi sub-system 1331 * 1332 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E) 1333 * - Pointed to by pkt_ha_private field in scsi_pkt 1334 */ 1335 struct scsa_cmd { 1336 ddi_dma_handle_t cmd_dmahandle; 1337 ddi_dma_cookie_t cmd_dmacookies[MEGASAS_MAX_SGE_CNT]; 1338 struct scsi_pkt *cmd_pkt; 1339 ulong_t cmd_dmacount; 1340 uint_t cmd_cookie; 1341 uint_t cmd_ncookies; 1342 uint_t cmd_cookiecnt; 1343 uint_t cmd_nwin; 1344 uint_t cmd_curwin; 1345 off_t cmd_dma_offset; 1346 ulong_t cmd_dma_len; 1347 ulong_t cmd_flags; 1348 uint_t cmd_cdblen; 1349 uint_t cmd_scblen; 1350 struct buf *cmd_buf; 1351 ushort_t device_id; 1352 uchar_t islogical; 1353 uchar_t lun; 1354 }; 1355 1356 1357 struct megasas_cmd { 1358 union megasas_frame *frame; 1359 uint32_t frame_phys_addr; 1360 uint8_t *sense; 1361 uint32_t sense_phys_addr; 1362 dma_obj_t frame_dma_obj; 1363 uint8_t frame_dma_obj_status; 1364 1365 uint32_t index; 1366 uint8_t sync_cmd; 1367 uint8_t cmd_status; 1368 uint16_t abort_aen; 1369 mlist_t list; 1370 uint32_t frame_count; 1371 struct scsa_cmd *cmd; 1372 struct scsi_pkt *pkt; 1373 }; 1374 1375 #define MAX_MGMT_ADAPTERS 1024 1376 #define IOC_SIGNATURE "MEGA-SAS" 1377 1378 #define IOC_CMD_FIRMWARE 0x0 1379 #define MR_DRIVER_IOCTL_COMMON 0xF0010000 1380 #define MR_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100 1381 #define MR_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200 1382 #define MR_DRIVER_IOCTL_MEGARAID_STATISTICS 0xF0010300 1383 1384 1385 #define MR_MAX_SENSE_LENGTH 32 1386 1387 struct megasas_mgmt_info { 1388 1389 uint16_t count; 1390 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1391 uint16_t map[MAX_MGMT_ADAPTERS]; 1392 int max_index; 1393 }; 1394 1395 #pragma pack(1) 1396 1397 struct megasas_drv_ver { 1398 uint8_t signature[12]; 1399 uint8_t os_name[16]; 1400 uint8_t os_ver[12]; 1401 uint8_t drv_name[20]; 1402 uint8_t drv_ver[32]; 1403 uint8_t drv_rel_date[20]; 1404 }; 1405 1406 #define PCI_TYPE0_ADDRESSES 6 1407 #define PCI_TYPE1_ADDRESSES 2 1408 #define PCI_TYPE2_ADDRESSES 5 1409 1410 struct megasas_pci_common_header { 1411 uint16_t vendorID; /* (ro) */ 1412 uint16_t deviceID; /* (ro) */ 1413 uint16_t command; /* Device control */ 1414 uint16_t status; 1415 uint8_t revisionID; /* (ro) */ 1416 uint8_t progIf; /* (ro) */ 1417 uint8_t subClass; /* (ro) */ 1418 uint8_t baseClass; /* (ro) */ 1419 uint8_t cacheLineSize; /* (ro+) */ 1420 uint8_t latencyTimer; /* (ro+) */ 1421 uint8_t headerType; /* (ro) */ 1422 uint8_t bist; /* Built in self test */ 1423 1424 union { 1425 struct { 1426 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 1427 uint32_t cis; 1428 uint16_t subVendorID; 1429 uint16_t subSystemID; 1430 uint32_t romBaseAddress; 1431 uint8_t capabilitiesPtr; 1432 uint8_t reserved1[3]; 1433 uint32_t reserved2; 1434 uint8_t interruptLine; 1435 uint8_t interruptPin; /* (ro) */ 1436 uint8_t minimumGrant; /* (ro) */ 1437 uint8_t maximumLatency; /* (ro) */ 1438 } type_0; 1439 1440 struct { 1441 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 1442 uint8_t primaryBus; 1443 uint8_t secondaryBus; 1444 uint8_t subordinateBus; 1445 uint8_t secondaryLatency; 1446 uint8_t ioBase; 1447 uint8_t ioLimit; 1448 uint16_t secondaryStatus; 1449 uint16_t memoryBase; 1450 uint16_t memoryLimit; 1451 uint16_t prefetchBase; 1452 uint16_t prefetchLimit; 1453 uint32_t prefetchBaseUpper32; 1454 uint32_t prefetchLimitUpper32; 1455 uint16_t ioBaseUpper16; 1456 uint16_t ioLimitUpper16; 1457 uint8_t capabilitiesPtr; 1458 uint8_t reserved1[3]; 1459 uint32_t romBaseAddress; 1460 uint8_t interruptLine; 1461 uint8_t interruptPin; 1462 uint16_t bridgeControl; 1463 } type_1; 1464 1465 struct { 1466 uint32_t socketRegistersBaseAddress; 1467 uint8_t capabilitiesPtr; 1468 uint8_t reserved; 1469 uint16_t secondaryStatus; 1470 uint8_t primaryBus; 1471 uint8_t secondaryBus; 1472 uint8_t subordinateBus; 1473 uint8_t secondaryLatency; 1474 struct { 1475 uint32_t base; 1476 uint32_t limit; 1477 } range[PCI_TYPE2_ADDRESSES-1]; 1478 uint8_t interruptLine; 1479 uint8_t interruptPin; 1480 uint16_t bridgeControl; 1481 } type_2; 1482 } header; 1483 }; 1484 1485 struct megasas_pci_link_capability { 1486 union { 1487 struct { 1488 uint32_t linkSpeed :4; 1489 uint32_t linkWidth :6; 1490 uint32_t aspmSupport :2; 1491 uint32_t losExitLatency :3; 1492 uint32_t l1ExitLatency :3; 1493 uint32_t rsvdp :6; 1494 uint32_t portNumber :8; 1495 } bits; 1496 1497 uint32_t asUlong; 1498 } cap; 1499 1500 }; 1501 1502 struct megasas_pci_link_status_capability { 1503 union { 1504 struct { 1505 uint16_t linkSpeed :4; 1506 uint16_t negotiatedLinkWidth :6; 1507 uint16_t linkTrainingError :1; 1508 uint16_t linkTraning :1; 1509 uint16_t slotClockConfig :1; 1510 uint16_t rsvdZ :3; 1511 } bits; 1512 1513 uint16_t asUshort; 1514 } stat_cap; 1515 1516 uint16_t reserved; 1517 1518 }; 1519 1520 struct megasas_pci_capabilities { 1521 struct megasas_pci_link_capability linkCapability; 1522 struct megasas_pci_link_status_capability linkStatusCapability; 1523 }; 1524 1525 struct megasas_pci_information 1526 { 1527 uint32_t busNumber; 1528 uint8_t deviceNumber; 1529 uint8_t functionNumber; 1530 uint8_t interruptVector; 1531 uint8_t reserved; 1532 struct megasas_pci_common_header pciHeaderInfo; 1533 struct megasas_pci_capabilities capability; 1534 uint8_t reserved2[32]; 1535 }; 1536 1537 struct megasas_ioctl { 1538 uint16_t version; 1539 uint16_t controller_id; 1540 uint8_t signature[8]; 1541 uint32_t reserved_1; 1542 uint32_t control_code; 1543 uint32_t reserved_2[2]; 1544 uint8_t frame[64]; 1545 union megasas_sgl_frame sgl_frame; 1546 uint8_t sense_buff[MR_MAX_SENSE_LENGTH]; 1547 uint8_t data[1]; 1548 }; 1549 1550 struct megasas_aen { 1551 uint16_t host_no; 1552 uint16_t cmd_status; 1553 uint32_t seq_num; 1554 uint32_t class_locale_word; 1555 }; 1556 1557 #pragma pack() 1558 1559 #ifndef DDI_VENDOR_LSI 1560 #define DDI_VENDOR_LSI "LSI" 1561 #endif /* DDI_VENDOR_LSI */ 1562 1563 static int megasas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 1564 static int megasas_attach(dev_info_t *, ddi_attach_cmd_t); 1565 static int megasas_reset(dev_info_t *, ddi_reset_cmd_t); 1566 static int megasas_detach(dev_info_t *, ddi_detach_cmd_t); 1567 static int megasas_open(dev_t *, int, int, cred_t *); 1568 static int megasas_close(dev_t, int, int, cred_t *); 1569 static int megasas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 1570 1571 static int megasas_tran_tgt_init(dev_info_t *, dev_info_t *, 1572 scsi_hba_tran_t *, struct scsi_device *); 1573 #if defined(USELESS) && !defined(lint) 1574 static int megasas_tran_tgt_probe(struct scsi_device *, int); 1575 #endif 1576 static struct scsi_pkt *megasas_tran_init_pkt(struct scsi_address *, register 1577 struct scsi_pkt *, struct buf *, int, int, int, int, 1578 int (*)(), caddr_t); 1579 static int megasas_tran_start(struct scsi_address *, 1580 register struct scsi_pkt *); 1581 static int megasas_tran_abort(struct scsi_address *, struct scsi_pkt *); 1582 static int megasas_tran_reset(struct scsi_address *, int); 1583 static int megasas_tran_bus_reset(dev_info_t *, int); 1584 static int megasas_tran_getcap(struct scsi_address *, char *, int); 1585 static int megasas_tran_setcap(struct scsi_address *, char *, int, int); 1586 static void megasas_tran_destroy_pkt(struct scsi_address *, 1587 struct scsi_pkt *); 1588 static void megasas_tran_dmafree(struct scsi_address *, struct scsi_pkt *); 1589 static void megasas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *); 1590 static int megasas_tran_quiesce(dev_info_t *dip); 1591 static int megasas_tran_unquiesce(dev_info_t *dip); 1592 static uint_t megasas_isr(caddr_t); 1593 static uint_t megasas_softintr(caddr_t); 1594 1595 static int init_mfi(struct megasas_instance *); 1596 static void mega_free_dma_obj(dma_obj_t); 1597 static int mega_alloc_dma_obj(struct megasas_instance *, dma_obj_t *); 1598 static struct megasas_cmd *get_mfi_pkt(struct megasas_instance *); 1599 static void return_mfi_pkt(struct megasas_instance *, 1600 struct megasas_cmd *); 1601 #ifndef lint 1602 static void push_pend_queue(struct megasas_instance *instance, 1603 struct megasas_cmd *cmd); 1604 static struct megasas_cmd *pull_pend_queue(struct megasas_instance *instance); 1605 #endif 1606 static void free_space_for_mfi(struct megasas_instance *); 1607 static void free_additional_dma_buffer(struct megasas_instance *); 1608 static int alloc_additional_dma_buffer(struct megasas_instance *); 1609 static int read_fw_status_reg_xscale(struct megasas_instance *); 1610 static int read_fw_status_reg_ppc(struct megasas_instance *); 1611 static void issue_cmd_xscale(struct megasas_cmd *, 1612 struct megasas_instance *); 1613 static void issue_cmd_ppc(struct megasas_cmd *, struct megasas_instance *); 1614 static int issue_cmd_in_poll_mode_xscale(struct megasas_instance *, 1615 struct megasas_cmd *); 1616 static int issue_cmd_in_poll_mode_ppc(struct megasas_instance *, 1617 struct megasas_cmd *); 1618 static int issue_cmd_in_sync_mode_xscale(struct megasas_instance *, 1619 struct megasas_cmd *); 1620 static int issue_cmd_in_sync_mode_ppc(struct megasas_instance *, 1621 struct megasas_cmd *); 1622 static void enable_intr_xscale(struct megasas_instance *); 1623 static void enable_intr_ppc(struct megasas_instance *); 1624 static void disable_intr_xscale(struct megasas_instance *); 1625 static void disable_intr_ppc(struct megasas_instance *); 1626 static int intr_ack_xscale(struct megasas_instance *); 1627 static int intr_ack_ppc(struct megasas_instance *); 1628 static int mfi_state_transition_to_ready(struct megasas_instance *); 1629 static void destroy_mfi_frame_pool(struct megasas_instance *); 1630 static int create_mfi_frame_pool(struct megasas_instance *); 1631 static int megasas_dma_alloc(struct megasas_instance *, struct scsi_pkt *, 1632 struct buf *, int, int (*)()); 1633 static int megasas_dma_move(struct megasas_instance *, 1634 struct scsi_pkt *, struct buf *); 1635 static void flush_cache(struct megasas_instance *instance); 1636 static void display_scsi_inquiry(caddr_t); 1637 static int start_mfi_aen(struct megasas_instance *instance); 1638 static int handle_drv_ioctl(struct megasas_instance *instance, 1639 struct megasas_ioctl *ioctl, int mode); 1640 static int handle_mfi_ioctl(struct megasas_instance *instance, 1641 struct megasas_ioctl *ioctl, int mode); 1642 static int handle_mfi_aen(struct megasas_instance *instance, 1643 struct megasas_aen *aen); 1644 static void fill_up_drv_ver(struct megasas_drv_ver *dv); 1645 #ifndef lint 1646 static void megasas_minphys(struct buf *bp); 1647 #endif 1648 static struct megasas_cmd *build_cmd(struct megasas_instance *instance, 1649 struct scsi_address *ap, struct scsi_pkt *pkt, 1650 uchar_t *cmd_done); 1651 static int wait_for_outstanding(struct megasas_instance *instance); 1652 static int register_mfi_aen(struct megasas_instance *instance, 1653 uint32_t seq_num, uint32_t class_locale_word); 1654 static int issue_mfi_pthru(struct megasas_instance *instance, struct 1655 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1656 static int issue_mfi_dcmd(struct megasas_instance *instance, struct 1657 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1658 static int issue_mfi_smp(struct megasas_instance *instance, struct 1659 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1660 static int issue_mfi_stp(struct megasas_instance *instance, struct 1661 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1662 static int abort_aen_cmd(struct megasas_instance *instance, 1663 struct megasas_cmd *cmd_to_abort); 1664 #if defined(NOT_YET) && !defined(lint) 1665 static void io_timeout_checker(void *instance); 1666 #endif 1667 1668 #ifdef __cplusplus 1669 } 1670 #endif 1671 1672 #endif /* _MEGARAID_SAS_H_ */ 1673