1 /* 2 * megaraid_sas.h: header for mega_sas 3 * 4 * Solaris MegaRAID driver for SAS controllers 5 * Copyright (c) 2004-2008, LSI Logic Corporation. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * 3. Neither the name of the author nor the names of its contributors may be 19 * used to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 29 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 33 * DAMAGE. 34 */ 35 36 /* 37 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 38 * Use is subject to license terms. 39 */ 40 41 #ifndef _MEGARAID_SAS_H_ 42 #define _MEGARAID_SAS_H_ 43 44 #pragma ident "%Z%%M% %I% %E% SMI" 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #include <sys/scsi/scsi.h> 51 #include "list.h" 52 53 #pragma pack(1) 54 55 /* 56 * MegaRAID SAS Driver meta data 57 */ 58 #define MEGASAS_VERSION "LSIv1.26" 59 #define MEGASAS_RELDATE "Mar 31, 2008" 60 61 #define MEGASAS_TRUE 1 62 #define MEGASAS_FALSE 0 63 64 /* 65 * MegaRAID device id conversion definitions. 66 */ 67 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT) 68 69 /* 70 * MegaRAID SAS supported controllers 71 */ 72 #define PCI_DEVICE_ID_LSI_1064 0x0411 73 #define PCI_DEVICE_ID_LSI_1078 0x0060 74 #define PCI_DEVICE_ID_LSI_1078DE 0x007C 75 76 #define PCI_DEVICE_ID_DELL_PERC5 0x0015 77 #define PCI_DEVICE_ID_DELL_SAS5 0x0054 78 79 #define PCI_SUBSYSTEM_DELL_PERC5E 0x1F01 80 #define PCI_SUBSYSTEM_DELL_PERC5I 0x1F02 81 #define PCI_SUBSYSTEM_DELL_PERC5I_INTEGRATED 0x1F03 82 #define PCI_SUBSYSTEM_DELL_SAS5I 0x1F05 83 #define PCI_SUBSYSTEM_DELL_SAS5I_INTEGRATED 0x1F06 84 85 #define PCI_SUB_DEVICEID_FSC 0x1081 86 #define PCI_SUB_VENDORID_FSC 0x1734 87 88 #define REGISTER_SET_IO (1) 89 90 #define MEGASAS_MAX_SGE_CNT 0x50 91 92 #define MEGASAS_IOCTL_DRIVER 0x12341234 93 #define MEGASAS_IOCTL_FIRMWARE 0x12345678 94 #define MEGASAS_IOCTL_AEN 0x87654321 95 96 #define MEGASAS_1_SECOND 1000000 97 /* 98 * ===================================== 99 * MegaRAID SAS MFI firmware definitions 100 * ===================================== 101 */ 102 /* 103 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for 104 * protocol between the software and firmware. Commands are issued using 105 * "message frames" 106 */ 107 108 /* 109 * FW posts its state in upper 4 bits of outbound_msg_0 register 110 */ 111 #define MFI_STATE_MASK 0xF0000000 112 #define MFI_STATE_UNDEFINED 0x00000000 113 #define MFI_STATE_BB_INIT 0x10000000 114 #define MFI_STATE_FW_INIT 0x40000000 115 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 116 #define MFI_STATE_FW_INIT_2 0x70000000 117 #define MFI_STATE_DEVICE_SCAN 0x80000000 118 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 119 #define MFI_STATE_FLUSH_CACHE 0xA0000000 120 #define MFI_STATE_READY 0xB0000000 121 #define MFI_STATE_OPERATIONAL 0xC0000000 122 #define MFI_STATE_FAULT 0xF0000000 123 124 #define MEGAMFI_FRAME_SIZE 64 125 126 /* 127 * During FW init, clear pending cmds & reset state using inbound_msg_0 128 * 129 * ABORT : Abort all pending cmds 130 * READY : Move from OPERATIONAL to READY state; discard queue info 131 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??) 132 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 133 */ 134 #define MFI_INIT_ABORT 0x00000001 135 #define MFI_INIT_READY 0x00000002 136 #define MFI_INIT_MFIMODE 0x00000004 137 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 138 #define MFI_INIT_HOTPLUG 0x00000010 139 #define MFI_STOP_ADP 0x00000020 140 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT 141 142 /* 143 * MFI frame flags 144 */ 145 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 146 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 147 #define MFI_FRAME_SGL32 0x0000 148 #define MFI_FRAME_SGL64 0x0002 149 #define MFI_FRAME_SENSE32 0x0000 150 #define MFI_FRAME_SENSE64 0x0004 151 #define MFI_FRAME_DIR_NONE 0x0000 152 #define MFI_FRAME_DIR_WRITE 0x0008 153 #define MFI_FRAME_DIR_READ 0x0010 154 #define MFI_FRAME_DIR_BOTH 0x0018 155 156 /* 157 * Definition for cmd_status 158 */ 159 #define MFI_CMD_STATUS_POLL_MODE 0xFF 160 161 /* 162 * MFI command opcodes 163 */ 164 #define MFI_CMD_OP_INIT 0x00 165 #define MFI_CMD_OP_LD_READ 0x01 166 #define MFI_CMD_OP_LD_WRITE 0x02 167 #define MFI_CMD_OP_LD_SCSI 0x03 168 #define MFI_CMD_OP_PD_SCSI 0x04 169 #define MFI_CMD_OP_DCMD 0x05 170 #define MFI_CMD_OP_ABORT 0x06 171 #define MFI_CMD_OP_SMP 0x07 172 #define MFI_CMD_OP_STP 0x08 173 174 #define MR_DCMD_CTRL_GET_INFO 0x01010000 175 176 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 177 #define MR_FLUSH_CTRL_CACHE 0x01 178 #define MR_FLUSH_DISK_CACHE 0x02 179 180 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 181 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 182 183 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 184 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 185 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 186 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 187 188 /* 189 * Solaris Specific MAX values 190 */ 191 #define MAX_SGL 24 192 /* 193 * MFI command completion codes 194 */ 195 enum MFI_STAT { 196 MFI_STAT_OK = 0x00, 197 MFI_STAT_INVALID_CMD = 0x01, 198 MFI_STAT_INVALID_DCMD = 0x02, 199 MFI_STAT_INVALID_PARAMETER = 0x03, 200 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 201 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 202 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 203 MFI_STAT_APP_IN_USE = 0x07, 204 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 205 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 206 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 207 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 208 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 209 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 210 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 211 MFI_STAT_FLASH_BUSY = 0x0f, 212 MFI_STAT_FLASH_ERROR = 0x10, 213 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 214 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 215 MFI_STAT_FLASH_NOT_OPEN = 0x13, 216 MFI_STAT_FLASH_NOT_STARTED = 0x14, 217 MFI_STAT_FLUSH_FAILED = 0x15, 218 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 219 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 220 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 221 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 222 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 223 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 224 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 225 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 226 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 227 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 228 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 229 MFI_STAT_MFC_HW_ERROR = 0x21, 230 MFI_STAT_NO_HW_PRESENT = 0x22, 231 MFI_STAT_NOT_FOUND = 0x23, 232 MFI_STAT_NOT_IN_ENCL = 0x24, 233 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 234 MFI_STAT_PD_TYPE_WRONG = 0x26, 235 MFI_STAT_PR_DISABLED = 0x27, 236 MFI_STAT_ROW_INDEX_INVALID = 0x28, 237 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 238 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 239 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 240 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 241 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 242 MFI_STAT_SCSI_IO_FAILED = 0x2e, 243 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 244 MFI_STAT_SHUTDOWN_FAILED = 0x30, 245 MFI_STAT_TIME_NOT_SET = 0x31, 246 MFI_STAT_WRONG_STATE = 0x32, 247 MFI_STAT_LD_OFFLINE = 0x33, 248 MFI_STAT_INVALID_STATUS = 0xFF 249 }; 250 251 enum MR_EVT_CLASS { 252 MR_EVT_CLASS_DEBUG = -2, 253 MR_EVT_CLASS_PROGRESS = -1, 254 MR_EVT_CLASS_INFO = 0, 255 MR_EVT_CLASS_WARNING = 1, 256 MR_EVT_CLASS_CRITICAL = 2, 257 MR_EVT_CLASS_FATAL = 3, 258 MR_EVT_CLASS_DEAD = 4 259 }; 260 261 enum MR_EVT_LOCALE { 262 MR_EVT_LOCALE_LD = 0x0001, 263 MR_EVT_LOCALE_PD = 0x0002, 264 MR_EVT_LOCALE_ENCL = 0x0004, 265 MR_EVT_LOCALE_BBU = 0x0008, 266 MR_EVT_LOCALE_SAS = 0x0010, 267 MR_EVT_LOCALE_CTRL = 0x0020, 268 MR_EVT_LOCALE_CONFIG = 0x0040, 269 MR_EVT_LOCALE_CLUSTER = 0x0080, 270 MR_EVT_LOCALE_ALL = 0xffff 271 }; 272 273 enum MR_EVT_ARGS { 274 MR_EVT_ARGS_NONE, 275 MR_EVT_ARGS_CDB_SENSE, 276 MR_EVT_ARGS_LD, 277 MR_EVT_ARGS_LD_COUNT, 278 MR_EVT_ARGS_LD_LBA, 279 MR_EVT_ARGS_LD_OWNER, 280 MR_EVT_ARGS_LD_LBA_PD_LBA, 281 MR_EVT_ARGS_LD_PROG, 282 MR_EVT_ARGS_LD_STATE, 283 MR_EVT_ARGS_LD_STRIP, 284 MR_EVT_ARGS_PD, 285 MR_EVT_ARGS_PD_ERR, 286 MR_EVT_ARGS_PD_LBA, 287 MR_EVT_ARGS_PD_LBA_LD, 288 MR_EVT_ARGS_PD_PROG, 289 MR_EVT_ARGS_PD_STATE, 290 MR_EVT_ARGS_PCI, 291 MR_EVT_ARGS_RATE, 292 MR_EVT_ARGS_STR, 293 MR_EVT_ARGS_TIME, 294 MR_EVT_ARGS_ECC 295 }; 296 297 /* 298 * SAS controller properties 299 */ 300 struct megasas_ctrl_prop { 301 uint16_t seq_num; 302 uint16_t pred_fail_poll_interval; 303 uint16_t intr_throttle_count; 304 uint16_t intr_throttle_timeouts; 305 306 uint8_t rebuild_rate; 307 uint8_t patrol_read_rate; 308 uint8_t bgi_rate; 309 uint8_t cc_rate; 310 uint8_t recon_rate; 311 312 uint8_t cache_flush_interval; 313 314 uint8_t spinup_drv_count; 315 uint8_t spinup_delay; 316 317 uint8_t cluster_enable; 318 uint8_t coercion_mode; 319 uint8_t disk_write_cache_disable; 320 uint8_t alarm_enable; 321 322 uint8_t reserved[44]; 323 }; 324 325 /* 326 * SAS controller information 327 */ 328 struct megasas_ctrl_info { 329 /* PCI device information */ 330 struct { 331 uint16_t vendor_id; 332 uint16_t device_id; 333 uint16_t sub_vendor_id; 334 uint16_t sub_device_id; 335 uint8_t reserved[24]; 336 } pci; 337 338 /* Host interface information */ 339 struct { 340 uint8_t PCIX : 1; 341 uint8_t PCIE : 1; 342 uint8_t iSCSI : 1; 343 uint8_t SAS_3G : 1; 344 uint8_t reserved_0 : 4; 345 uint8_t reserved_1[6]; 346 uint8_t port_count; 347 uint64_t port_addr[8]; 348 } host_interface; 349 350 /* Device (backend) interface information */ 351 struct { 352 uint8_t SPI : 1; 353 uint8_t SAS_3G : 1; 354 uint8_t SATA_1_5G : 1; 355 uint8_t SATA_3G : 1; 356 uint8_t reserved_0 : 4; 357 uint8_t reserved_1[6]; 358 uint8_t port_count; 359 uint64_t port_addr[8]; 360 } device_interface; 361 362 /* List of components residing in flash. All str are null terminated */ 363 uint32_t image_check_word; 364 uint32_t image_component_count; 365 366 struct { 367 char name[8]; 368 char version[32]; 369 char build_date[16]; 370 char built_time[16]; 371 } image_component[8]; 372 373 /* 374 * List of flash components that have been flashed on the card, but 375 * are not in use, pending reset of the adapter. This list will be 376 * empty if a flash operation has not occurred. All stings are null 377 * terminated 378 */ 379 uint32_t pending_image_component_count; 380 381 struct { 382 char name[8]; 383 char version[32]; 384 char build_date[16]; 385 char build_time[16]; 386 } pending_image_component[8]; 387 388 uint8_t max_arms; 389 uint8_t max_spans; 390 uint8_t max_arrays; 391 uint8_t max_lds; 392 393 char product_name[80]; 394 char serial_no[32]; 395 396 /* 397 * Other physical/controller/operation information. Indicates the 398 * presence of the hardware 399 */ 400 struct { 401 uint32_t bbu : 1; 402 uint32_t alarm : 1; 403 uint32_t nvram : 1; 404 uint32_t uart : 1; 405 uint32_t reserved : 28; 406 } hw_present; 407 408 uint32_t current_fw_time; 409 410 /* Maximum data transfer sizes */ 411 uint16_t max_concurrent_cmds; 412 uint16_t max_sge_count; 413 uint32_t max_request_size; 414 415 /* Logical and physical device counts */ 416 uint16_t ld_present_count; 417 uint16_t ld_degraded_count; 418 uint16_t ld_offline_count; 419 420 uint16_t pd_present_count; 421 uint16_t pd_disk_present_count; 422 uint16_t pd_disk_pred_failure_count; 423 uint16_t pd_disk_failed_count; 424 425 /* Memory size information */ 426 uint16_t nvram_size; 427 uint16_t memory_size; 428 uint16_t flash_size; 429 430 /* Error counters */ 431 uint16_t mem_correctable_error_count; 432 uint16_t mem_uncorrectable_error_count; 433 434 /* Cluster information */ 435 uint8_t cluster_permitted; 436 uint8_t cluster_active; 437 uint8_t reserved_1[2]; 438 439 /* Controller capabilities structures */ 440 struct { 441 uint32_t raid_level_0 : 1; 442 uint32_t raid_level_1 : 1; 443 uint32_t raid_level_5 : 1; 444 uint32_t raid_level_1E : 1; 445 uint32_t reserved : 28; 446 } raid_levels; 447 448 struct { 449 uint32_t rbld_rate : 1; 450 uint32_t cc_rate : 1; 451 uint32_t bgi_rate : 1; 452 uint32_t recon_rate : 1; 453 uint32_t patrol_rate : 1; 454 uint32_t alarm_control : 1; 455 uint32_t cluster_supported : 1; 456 uint32_t bbu : 1; 457 uint32_t spanning_allowed : 1; 458 uint32_t dedicated_hotspares : 1; 459 uint32_t revertible_hotspares : 1; 460 uint32_t foreign_config_import : 1; 461 uint32_t self_diagnostic : 1; 462 uint32_t reserved : 19; 463 } adapter_operations; 464 465 struct { 466 uint32_t read_policy : 1; 467 uint32_t write_policy : 1; 468 uint32_t io_policy : 1; 469 uint32_t access_policy : 1; 470 uint32_t reserved : 28; 471 } ld_operations; 472 473 struct { 474 uint8_t min; 475 uint8_t max; 476 uint8_t reserved[2]; 477 } stripe_size_operations; 478 479 struct { 480 uint32_t force_online : 1; 481 uint32_t force_offline : 1; 482 uint32_t force_rebuild : 1; 483 uint32_t reserved : 29; 484 } pd_operations; 485 486 struct { 487 uint32_t ctrl_supports_sas : 1; 488 uint32_t ctrl_supports_sata : 1; 489 uint32_t allow_mix_in_encl : 1; 490 uint32_t allow_mix_in_ld : 1; 491 uint32_t allow_sata_in_cluster : 1; 492 uint32_t reserved : 27; 493 } pd_mix_support; 494 495 /* Include the controller properties (changeable items) */ 496 uint8_t reserved_2[12]; 497 struct megasas_ctrl_prop properties; 498 499 uint8_t pad[0x800 - 0x640]; 500 }; 501 502 /* 503 * =============================== 504 * MegaRAID SAS driver definitions 505 * =============================== 506 */ 507 #define MEGADRV_MAX_NUM_CMD 1024 508 509 #define MEGADRV_MAX_PD_CHANNELS 2 510 #define MEGADRV_MAX_LD_CHANNELS 2 511 #define MEGADRV_MAX_CHANNELS (MEGADRV_MAX_PD_CHANNELS + \ 512 MEGADRV_MAX_LD_CHANNELS) 513 #define MEGADRV_MAX_DEV_PER_CHANNEL 128 514 #define MEGADRV_DEFAULT_INIT_ID -1 515 #define MEGADRV_MAX_CMD_PER_LUN 1000 516 #define MEGADRV_MAX_LUN 8 517 #define MEGADRV_MAX_LD 64 518 519 #define MEGADRV_RESET_WAIT_TIME 300 520 #define MEGADRV_RESET_NOTICE_INTERVAL 5 521 522 #define MEGASAS_IOCTL_CMD 0 523 524 /* 525 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit 526 * SGLs based on the size of dma_addr_t 527 */ 528 #define IS_DMA64 (sizeof (dma_addr_t) == 8) 529 530 /* 531 * All MFI register set macros accept megasas_register_set* 532 */ 533 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \ 534 (uint32_t *)((instance)->regmap + 0x10), (v)) 535 536 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \ 537 (uint32_t *)((instance)->regmap + 0x18)) 538 539 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \ 540 (uint32_t *)((instance)->regmap + 0x20), (v)) 541 542 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \ 543 (uint32_t *)((instance)->regmap + 0x20)) 544 545 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \ 546 (uint32_t *)((instance)->regmap + 0x30), (v)) 547 548 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \ 549 (uint32_t *)((instance)->regmap + 0x30)) 550 551 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \ 552 (uint32_t *)((instance)->regmap + 0x34), (v)) 553 554 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \ 555 (uint32_t *)((instance)->regmap + 0x34)) 556 557 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \ 558 (uint32_t *)((instance)->regmap + 0x40), (v)) 559 560 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \ 561 (uint32_t *)((instance)->regmap + 0xA0), (v)) 562 563 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \ 564 (uint32_t *)((instance)->regmap + 0xB0)) 565 566 /* 567 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data 568 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs 569 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled. 570 */ 571 #define MFI_OB_INTR_STATUS_MASK 0x00000002 572 573 /* 574 * This MFI_REPLY_1078_MESSAGE_INTR flag is used also 575 * in enable_intr_pcc also. Hence bit 2, i.e. 0x4 has 576 * been set in this flag along with bit 31. 577 */ 578 #define MFI_REPLY_1078_MESSAGE_INTR 0x80000004 579 580 #define MFI_POLL_TIMEOUT_SECS 60 581 582 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \ 583 (uint32_t *)((instance)->regmap + 0x34), 1) 584 #define MFI_DISABLE_INTR(instance) \ 585 { \ 586 uint32_t disable = 1; \ 587 uint32_t mask = ddi_get32((instance)->regmap_handle, \ 588 (uint32_t *)((instance)->regmap + 0x34)); \ 589 mask &= ~disable; \ 590 ddi_put32((instance)->regmap_handle, \ 591 (uint32_t *)((instance)->regmap + 0x34), mask); \ 592 } 593 594 595 struct megasas_register_set { 596 uint32_t reserved_0[4]; /* 0000h */ 597 598 uint32_t inbound_msg_0; /* 0010h */ 599 uint32_t inbound_msg_1; /* 0014h */ 600 uint32_t outbound_msg_0; /* 0018h */ 601 uint32_t outbound_msg_1; /* 001Ch */ 602 603 uint32_t inbound_doorbell; /* 0020h */ 604 uint32_t inbound_intr_status; /* 0024h */ 605 uint32_t inbound_intr_mask; /* 0028h */ 606 607 uint32_t outbound_doorbell; /* 002Ch */ 608 uint32_t outbound_intr_status; /* 0030h */ 609 uint32_t outbound_intr_mask; /* 0034h */ 610 611 uint32_t reserved_1[2]; /* 0038h */ 612 613 uint32_t inbound_queue_port; /* 0040h */ 614 uint32_t outbound_queue_port; /* 0044h */ 615 616 uint32_t reserved_2[22]; /* 0048h */ 617 618 uint32_t outbound_doorbell_clear; /* 00A0h */ 619 620 uint32_t reserved_3[3]; /* 00A4h */ 621 622 uint32_t outbound_scratch_pad; /* 00B0h */ 623 624 uint32_t reserved_4[3]; /* 00B4h */ 625 626 uint32_t inbound_low_queue_port; /* 00C0h */ 627 628 uint32_t inbound_high_queue_port; /* 00C4h */ 629 630 uint32_t reserved_5; /* 00C8h */ 631 uint32_t index_registers[820]; /* 00CCh */ 632 }; 633 634 struct megasas_sge32 { 635 uint32_t phys_addr; 636 uint32_t length; 637 }; 638 639 struct megasas_sge64 { 640 uint64_t phys_addr; 641 uint32_t length; 642 }; 643 644 union megasas_sgl { 645 struct megasas_sge32 sge32[1]; 646 struct megasas_sge64 sge64[1]; 647 }; 648 649 struct megasas_header { 650 uint8_t cmd; /* 00h */ 651 uint8_t sense_len; /* 01h */ 652 uint8_t cmd_status; /* 02h */ 653 uint8_t scsi_status; /* 03h */ 654 655 uint8_t target_id; /* 04h */ 656 uint8_t lun; /* 05h */ 657 uint8_t cdb_len; /* 06h */ 658 uint8_t sge_count; /* 07h */ 659 660 uint32_t context; /* 08h */ 661 uint32_t pad_0; /* 0Ch */ 662 663 uint16_t flags; /* 10h */ 664 uint16_t timeout; /* 12h */ 665 uint32_t data_xferlen; /* 14h */ 666 }; 667 668 union megasas_sgl_frame { 669 struct megasas_sge32 sge32[8]; 670 struct megasas_sge64 sge64[5]; 671 }; 672 673 struct megasas_init_frame { 674 uint8_t cmd; /* 00h */ 675 uint8_t reserved_0; /* 01h */ 676 uint8_t cmd_status; /* 02h */ 677 678 uint8_t reserved_1; /* 03h */ 679 uint32_t reserved_2; /* 04h */ 680 681 uint32_t context; /* 08h */ 682 uint32_t pad_0; /* 0Ch */ 683 684 uint16_t flags; /* 10h */ 685 uint16_t reserved_3; /* 12h */ 686 uint32_t data_xfer_len; /* 14h */ 687 688 uint32_t queue_info_new_phys_addr_lo; /* 18h */ 689 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */ 690 uint32_t queue_info_old_phys_addr_lo; /* 20h */ 691 uint32_t queue_info_old_phys_addr_hi; /* 24h */ 692 693 uint32_t reserved_4[6]; /* 28h */ 694 }; 695 696 struct megasas_init_queue_info { 697 uint32_t init_flags; /* 00h */ 698 uint32_t reply_queue_entries; /* 04h */ 699 700 uint32_t reply_queue_start_phys_addr_lo; /* 08h */ 701 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */ 702 uint32_t producer_index_phys_addr_lo; /* 10h */ 703 uint32_t producer_index_phys_addr_hi; /* 14h */ 704 uint32_t consumer_index_phys_addr_lo; /* 18h */ 705 uint32_t consumer_index_phys_addr_hi; /* 1Ch */ 706 }; 707 708 struct megasas_io_frame { 709 uint8_t cmd; /* 00h */ 710 uint8_t sense_len; /* 01h */ 711 uint8_t cmd_status; /* 02h */ 712 uint8_t scsi_status; /* 03h */ 713 714 uint8_t target_id; /* 04h */ 715 uint8_t access_byte; /* 05h */ 716 uint8_t reserved_0; /* 06h */ 717 uint8_t sge_count; /* 07h */ 718 719 uint32_t context; /* 08h */ 720 uint32_t pad_0; /* 0Ch */ 721 722 uint16_t flags; /* 10h */ 723 uint16_t timeout; /* 12h */ 724 uint32_t lba_count; /* 14h */ 725 726 uint32_t sense_buf_phys_addr_lo; /* 18h */ 727 uint32_t sense_buf_phys_addr_hi; /* 1Ch */ 728 729 uint32_t start_lba_lo; /* 20h */ 730 uint32_t start_lba_hi; /* 24h */ 731 732 union megasas_sgl sgl; /* 28h */ 733 }; 734 735 struct megasas_pthru_frame { 736 uint8_t cmd; /* 00h */ 737 uint8_t sense_len; /* 01h */ 738 uint8_t cmd_status; /* 02h */ 739 uint8_t scsi_status; /* 03h */ 740 741 uint8_t target_id; /* 04h */ 742 uint8_t lun; /* 05h */ 743 uint8_t cdb_len; /* 06h */ 744 uint8_t sge_count; /* 07h */ 745 746 uint32_t context; /* 08h */ 747 uint32_t pad_0; /* 0Ch */ 748 749 uint16_t flags; /* 10h */ 750 uint16_t timeout; /* 12h */ 751 uint32_t data_xfer_len; /* 14h */ 752 753 uint32_t sense_buf_phys_addr_lo; /* 18h */ 754 uint32_t sense_buf_phys_addr_hi; /* 1Ch */ 755 756 uint8_t cdb[16]; /* 20h */ 757 union megasas_sgl sgl; /* 30h */ 758 }; 759 760 struct megasas_dcmd_frame { 761 uint8_t cmd; /* 00h */ 762 uint8_t reserved_0; /* 01h */ 763 uint8_t cmd_status; /* 02h */ 764 uint8_t reserved_1[4]; /* 03h */ 765 uint8_t sge_count; /* 07h */ 766 767 uint32_t context; /* 08h */ 768 uint32_t pad_0; /* 0Ch */ 769 770 uint16_t flags; /* 10h */ 771 uint16_t timeout; /* 12h */ 772 773 uint32_t data_xfer_len; /* 14h */ 774 uint32_t opcode; /* 18h */ 775 776 /* uint8_t mbox[12]; */ /* 1Ch */ 777 union { /* 1Ch */ 778 uint8_t b[12]; 779 uint16_t s[6]; 780 uint32_t w[3]; 781 } mbox; 782 783 union megasas_sgl sgl; /* 28h */ 784 }; 785 786 struct megasas_abort_frame { 787 uint8_t cmd; /* 00h */ 788 uint8_t reserved_0; /* 01h */ 789 uint8_t cmd_status; /* 02h */ 790 791 uint8_t reserved_1; /* 03h */ 792 uint32_t reserved_2; /* 04h */ 793 794 uint32_t context; /* 08h */ 795 uint32_t pad_0; /* 0Ch */ 796 797 uint16_t flags; /* 10h */ 798 uint16_t reserved_3; /* 12h */ 799 uint32_t reserved_4; /* 14h */ 800 801 uint32_t abort_context; /* 18h */ 802 uint32_t pad_1; /* 1Ch */ 803 804 uint32_t abort_mfi_phys_addr_lo; /* 20h */ 805 uint32_t abort_mfi_phys_addr_hi; /* 24h */ 806 807 uint32_t reserved_5[6]; /* 28h */ 808 }; 809 810 struct megasas_smp_frame { 811 uint8_t cmd; /* 00h */ 812 uint8_t reserved_1; /* 01h */ 813 uint8_t cmd_status; /* 02h */ 814 uint8_t connection_status; /* 03h */ 815 816 uint8_t reserved_2[3]; /* 04h */ 817 uint8_t sge_count; /* 07h */ 818 819 uint32_t context; /* 08h */ 820 uint32_t pad_0; /* 0Ch */ 821 822 uint16_t flags; /* 10h */ 823 uint16_t timeout; /* 12h */ 824 825 uint32_t data_xfer_len; /* 14h */ 826 827 uint64_t sas_addr; /* 20h */ 828 829 union megasas_sgl sgl[2]; /* 28h */ 830 }; 831 832 struct megasas_stp_frame { 833 uint8_t cmd; /* 00h */ 834 uint8_t reserved_1; /* 01h */ 835 uint8_t cmd_status; /* 02h */ 836 uint8_t connection_status; /* 03h */ 837 838 uint8_t target_id; /* 04h */ 839 uint8_t reserved_2[2]; /* 04h */ 840 uint8_t sge_count; /* 07h */ 841 842 uint32_t context; /* 08h */ 843 uint32_t pad_0; /* 0Ch */ 844 845 uint16_t flags; /* 10h */ 846 uint16_t timeout; /* 12h */ 847 848 uint32_t data_xfer_len; /* 14h */ 849 850 uint16_t fis[10]; /* 28h */ 851 uint32_t stp_flags; /* 3C */ 852 union megasas_sgl sgl; /* 40 */ 853 }; 854 855 union megasas_frame { 856 struct megasas_header hdr; 857 struct megasas_init_frame init; 858 struct megasas_io_frame io; 859 struct megasas_pthru_frame pthru; 860 struct megasas_dcmd_frame dcmd; 861 struct megasas_abort_frame abort; 862 struct megasas_smp_frame smp; 863 struct megasas_stp_frame stp; 864 865 uint8_t raw_bytes[64]; 866 }; 867 868 union megasas_evt_class_locale { 869 struct { 870 uint16_t locale; 871 uint8_t reserved; 872 int8_t class; 873 } members; 874 875 uint32_t word; 876 }; 877 878 struct megasas_evt_log_info { 879 uint32_t newest_seq_num; 880 uint32_t oldest_seq_num; 881 uint32_t clear_seq_num; 882 uint32_t shutdown_seq_num; 883 uint32_t boot_seq_num; 884 }; 885 886 struct megasas_progress { 887 uint16_t progress; 888 uint16_t elapsed_seconds; 889 }; 890 891 struct megasas_evtarg_ld { 892 uint16_t target_id; 893 uint8_t ld_index; 894 uint8_t reserved; 895 }; 896 897 struct megasas_evtarg_pd { 898 uint16_t device_id; 899 uint8_t encl_index; 900 uint8_t slot_number; 901 }; 902 903 struct megasas_evt_detail { 904 uint32_t seq_num; 905 uint32_t time_stamp; 906 uint32_t code; 907 union megasas_evt_class_locale cl; 908 uint8_t arg_type; 909 uint8_t reserved1[15]; 910 911 union { 912 struct { 913 struct megasas_evtarg_pd pd; 914 uint8_t cdb_length; 915 uint8_t sense_length; 916 uint8_t reserved[2]; 917 uint8_t cdb[16]; 918 uint8_t sense[64]; 919 } cdbSense; 920 921 struct megasas_evtarg_ld ld; 922 923 struct { 924 struct megasas_evtarg_ld ld; 925 uint64_t count; 926 } ld_count; 927 928 struct { 929 uint64_t lba; 930 struct megasas_evtarg_ld ld; 931 } ld_lba; 932 933 struct { 934 struct megasas_evtarg_ld ld; 935 uint32_t prevOwner; 936 uint32_t newOwner; 937 } ld_owner; 938 939 struct { 940 uint64_t ld_lba; 941 uint64_t pd_lba; 942 struct megasas_evtarg_ld ld; 943 struct megasas_evtarg_pd pd; 944 } ld_lba_pd_lba; 945 946 struct { 947 struct megasas_evtarg_ld ld; 948 struct megasas_progress prog; 949 } ld_prog; 950 951 struct { 952 struct megasas_evtarg_ld ld; 953 uint32_t prev_state; 954 uint32_t new_state; 955 } ld_state; 956 957 struct { 958 uint64_t strip; 959 struct megasas_evtarg_ld ld; 960 } ld_strip; 961 962 struct megasas_evtarg_pd pd; 963 964 struct { 965 struct megasas_evtarg_pd pd; 966 uint32_t err; 967 } pd_err; 968 969 struct { 970 uint64_t lba; 971 struct megasas_evtarg_pd pd; 972 } pd_lba; 973 974 struct { 975 uint64_t lba; 976 struct megasas_evtarg_pd pd; 977 struct megasas_evtarg_ld ld; 978 } pd_lba_ld; 979 980 struct { 981 struct megasas_evtarg_pd pd; 982 struct megasas_progress prog; 983 } pd_prog; 984 985 struct { 986 struct megasas_evtarg_pd pd; 987 uint32_t prevState; 988 uint32_t newState; 989 } pd_state; 990 991 struct { 992 uint16_t vendorId; 993 uint16_t deviceId; 994 uint16_t subVendorId; 995 uint16_t subDeviceId; 996 } pci; 997 998 uint32_t rate; 999 char str[96]; 1000 1001 struct { 1002 uint32_t rtc; 1003 uint32_t elapsedSeconds; 1004 } time; 1005 1006 struct { 1007 uint32_t ecar; 1008 uint32_t elog; 1009 char str[64]; 1010 } ecc; 1011 1012 uint8_t b[96]; 1013 uint16_t s[48]; 1014 uint32_t w[24]; 1015 uint64_t d[12]; 1016 } args; 1017 1018 char description[128]; 1019 1020 }; 1021 1022 /* only 63 are usable by the application */ 1023 #define MAX_LOGICAL_DRIVES 64 1024 /* only 255 physical devices may be used */ 1025 #define MAX_PHYSICAL_DEVICES 256 1026 #define MAX_PD_PER_ENCLOSURE 64 1027 /* maximum disks per array */ 1028 #define MAX_ROW_SIZE 32 1029 /* maximum spans per logical drive */ 1030 #define MAX_SPAN_DEPTH 8 1031 /* maximum number of arrays a hot spare may be dedicated to */ 1032 #define MAX_ARRAYS_DEDICATED 16 1033 /* maximum number of arrays which may exist */ 1034 #define MAX_ARRAYS 128 1035 /* maximum number of foreign configs that may ha managed at once */ 1036 #define MAX_FOREIGN_CONFIGS 8 1037 /* maximum spares (global and dedicated combined) */ 1038 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES 1039 /* maximum possible Target IDs (i.e. 0 to 63) */ 1040 #define MAX_TARGET_ID 63 1041 /* maximum number of supported enclosures */ 1042 #define MAX_ENCLOSURES 32 1043 /* maximum number of PHYs per controller */ 1044 #define MAX_PHYS_PER_CONTROLLER 16 1045 /* maximum number of LDs per array (due to DDF limitations) */ 1046 #define MAX_LDS_PER_ARRAY 16 1047 1048 /* 1049 * ----------------------------------------------------------------------------- 1050 * ----------------------------------------------------------------------------- 1051 * 1052 * Logical Drive commands 1053 * 1054 * ----------------------------------------------------------------------------- 1055 * ----------------------------------------------------------------------------- 1056 */ 1057 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */ 1058 1059 /* 1060 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST 1061 * dcmd.mbox - reserved 1062 * dcmd.sge IN - ptr to returned MR_LD_LIST structure 1063 * Desc: Return the logical drive list structure 1064 * Status: No error 1065 */ 1066 1067 /* 1068 * defines the logical drive reference structure 1069 */ 1070 typedef union _MR_LD_REF { /* LD reference structure */ 1071 struct { 1072 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */ 1073 uint8_t reserved; /* reserved to make in line with MR_PD_REF */ 1074 uint16_t seqNum; /* Sequence Number */ 1075 } ld_ref; 1076 uint32_t ref; /* shorthand reference to full 32-bits */ 1077 } MR_LD_REF; /* 4 bytes */ 1078 1079 /* 1080 * defines the logical drive list structure 1081 */ 1082 typedef struct _MR_LD_LIST { 1083 uint32_t ldCount; /* number of LDs */ 1084 uint32_t reserved; /* pad to 8-byte boundary */ 1085 struct { 1086 MR_LD_REF ref; /* LD reference */ 1087 uint8_t state; /* current LD state (MR_LD_STATE) */ 1088 uint8_t reserved[3]; /* pad to 8-byte boundary */ 1089 uint64_t size; /* LD size */ 1090 } ldList[MAX_LOGICAL_DRIVES]; 1091 } MR_LD_LIST; 1092 /* 4 + 4 + (MAX_LOGICAL_DRIVES * 16), for 40LD it is = 648 bytes */ 1093 1094 #define DMA_OBJ_ALLOCATED 1 1095 #define DMA_OBJ_REALLOCATED 2 1096 #define DMA_OBJ_FREED 3 1097 1098 #pragma pack() 1099 1100 /* 1101 * dma_obj_t - Our DMA object 1102 * @param buffer : kernel virtual address 1103 * @param size : size of the data to be allocated 1104 * @param acc_handle : access handle 1105 * @param dma_handle : dma handle 1106 * @param dma_cookie : scatter-gather list 1107 * @param dma_attr : dma attributes for this buffer 1108 * 1109 * Our DMA object. The caller must initialize the size and dma attributes 1110 * (dma_attr) fields before allocating the resources. 1111 */ 1112 typedef struct { 1113 caddr_t buffer; 1114 uint32_t size; 1115 ddi_acc_handle_t acc_handle; 1116 ddi_dma_handle_t dma_handle; 1117 ddi_dma_cookie_t dma_cookie[MEGASAS_MAX_SGE_CNT]; 1118 ddi_dma_attr_t dma_attr; 1119 uint8_t status; 1120 } dma_obj_t; 1121 1122 struct megasas_instance { 1123 uint32_t *producer; 1124 uint32_t *consumer; 1125 1126 uint32_t *reply_queue; 1127 dma_obj_t mfi_internal_dma_obj; 1128 1129 uint8_t init_id; 1130 uint8_t reserved[3]; 1131 1132 uint16_t max_num_sge; 1133 uint16_t max_fw_cmds; 1134 uint32_t max_sectors_per_req; 1135 1136 struct megasas_cmd **cmd_list; 1137 1138 mlist_t cmd_pool_list; 1139 kmutex_t cmd_pool_mtx; 1140 1141 mlist_t cmd_pend_list; 1142 kmutex_t cmd_pend_mtx; 1143 1144 dma_obj_t mfi_evt_detail_obj; 1145 struct megasas_cmd *aen_cmd; 1146 1147 uint32_t aen_seq_num; 1148 uint32_t aen_class_locale_word; 1149 1150 scsi_hba_tran_t *tran; 1151 1152 kcondvar_t int_cmd_cv; 1153 kmutex_t int_cmd_mtx; 1154 1155 kcondvar_t aen_cmd_cv; 1156 kmutex_t aen_cmd_mtx; 1157 1158 kcondvar_t abort_cmd_cv; 1159 kmutex_t abort_cmd_mtx; 1160 1161 dev_info_t *dip; 1162 ddi_acc_handle_t pci_handle; 1163 1164 timeout_id_t timeout_id; 1165 uint32_t unique_id; 1166 uint16_t fw_outstanding; 1167 caddr_t regmap; 1168 ddi_acc_handle_t regmap_handle; 1169 uint8_t isr_level; 1170 ddi_iblock_cookie_t iblock_cookie; 1171 ddi_iblock_cookie_t soft_iblock_cookie; 1172 ddi_softintr_t soft_intr_id; 1173 uint8_t softint_running; 1174 kmutex_t completed_pool_mtx; 1175 mlist_t completed_pool_list; 1176 1177 caddr_t internal_buf; 1178 uint32_t internal_buf_dmac_add; 1179 uint32_t internal_buf_size; 1180 1181 uint16_t vendor_id; 1182 uint16_t device_id; 1183 uint16_t subsysvid; 1184 uint16_t subsysid; 1185 int baseaddress; 1186 char iocnode[16]; 1187 1188 struct megasas_func_ptr *func_ptr; 1189 }; 1190 1191 struct megasas_func_ptr { 1192 int (*read_fw_status_reg)(struct megasas_instance *); 1193 void (*issue_cmd)(struct megasas_cmd *, struct megasas_instance *); 1194 int (*issue_cmd_in_sync_mode)(struct megasas_instance *, 1195 struct megasas_cmd *); 1196 int (*issue_cmd_in_poll_mode)(struct megasas_instance *, 1197 struct megasas_cmd *); 1198 void (*enable_intr)(struct megasas_instance *); 1199 void (*disable_intr)(struct megasas_instance *); 1200 int (*intr_ack)(struct megasas_instance *); 1201 }; 1202 1203 /* 1204 * ### Helper routines ### 1205 */ 1206 1207 /* 1208 * con_log() - console log routine 1209 * @param level : indicates the severity of the message. 1210 * @fparam mt : format string 1211 * 1212 * con_log displays the error messages on the console based on the current 1213 * debug level. Also it attaches the appropriate kernel severity level with 1214 * the message. 1215 * 1216 * 1217 * consolge messages debug levels 1218 */ 1219 #define CL_ANN 0 /* print unconditionally, announcements */ 1220 #define CL_ANN1 1 /* No o/p */ 1221 #define CL_DLEVEL1 2 /* debug level 1, informative */ 1222 #define CL_DLEVEL2 3 /* debug level 2, verbose */ 1223 #define CL_DLEVEL3 4 /* debug level 3, very verbose */ 1224 1225 #ifdef __SUNPRO_C 1226 #define __func__ "" 1227 #endif 1228 1229 #if DEBUG 1230 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; } 1231 #else 1232 #define con_log(level, fmt) 1233 #endif /* DEBUG */ 1234 1235 /* byte-ordering macros */ 1236 #ifdef __sparc 1237 #define host_to_le16(s) ((s) & 0xFF) << 8 | ((s) & 0xFF00) >> 8 1238 #else 1239 #define host_to_le16(s) (s) 1240 #endif 1241 1242 #ifdef __sparc 1243 #define host_to_le32(l) (((l) & 0xFF) << 24 | ((l) & 0xFF00) << 8 | \ 1244 ((l) & 0xFF0000) >> 8 | ((l) & 0xFF000000) >> 24) 1245 #else 1246 #define host_to_le32(l) (l) 1247 #endif 1248 1249 #ifdef __sparc 1250 #define host_to_le64(ull) ((host_to_le32(((ull) & 0xFFFFFFFF)) << 32) | \ 1251 (host_to_le32((((ull) & 0xFFFFFFFF00000000) >> 32)))) 1252 #else 1253 #define host_to_le64(ull) (ull) 1254 #endif 1255 1256 /* 1257 * ### SCSA definitions ### 1258 */ 1259 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target) 1260 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun) 1261 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran) 1262 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1263 1264 #define TRAN2MEGA(tran) (struct megasas_instance *)(tran)->tran_hba_private) 1265 #define ADDR2MEGA(ap) (TRAN2MEGA(ADDR2TRAN(ap)) 1266 1267 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private) 1268 #define CMD2PKT(sp) ((sp)->cmd_pkt) 1269 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request)) 1270 1271 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address) 1272 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran) 1273 #define CMD2MEGA(cmd) (TRAN2MEGA(CMD2TRAN(cmd))) 1274 1275 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */ 1276 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */ 1277 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */ 1278 1279 /* 1280 * ### Data structures for ioctl inteface and internal commands ### 1281 */ 1282 1283 /* 1284 * Data direction flags 1285 */ 1286 #define UIOC_RD 0x00001 1287 #define UIOC_WR 0x00002 1288 1289 #define SCP2HOST(scp) (scp)->device->host /* to host */ 1290 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */ 1291 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */ 1292 #define SCP2TARGET(scp) (scp)->device->id /* to target */ 1293 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */ 1294 1295 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0]) 1296 #define SCP2ADAPTER(scp) \ 1297 (struct megasas_instance *)SCSIHOST2ADAP(SCP2HOST(scp)) 1298 1299 #define MEGADRV_IS_LOGICAL_SCSA(instance, acmd) \ 1300 (acmd->device_id < MEGADRV_MAX_LD) ? 1 : 0 1301 #define MEGADRV_IS_LOGICAL(ap) \ 1302 (ap->a_target < MEGADRV_MAX_LD) ? 1 : 0 1303 #define MAP_DEVICE_ID(instance, ap) \ 1304 (ap->a_target % MEGADRV_MAX_LD) 1305 /* 1306 * #define MAP_DEVICE_ID(instance,ap) \ 1307 * (ap->a_target) 1308 */ 1309 1310 #define HIGH_LEVEL_INTR 1 1311 #define NORMAL_LEVEL_INTR 0 1312 1313 /* 1314 * scsa_cmd - Per-command mega private data 1315 * @param cmd_dmahandle : dma handle 1316 * @param cmd_dmacookies : current dma cookies 1317 * @param cmd_pkt : scsi_pkt reference 1318 * @param cmd_dmacount : dma count 1319 * @param cmd_cookie : next cookie 1320 * @param cmd_ncookies : cookies per window 1321 * @param cmd_cookiecnt : cookies per sub-win 1322 * @param cmd_nwin : number of dma windows 1323 * @param cmd_curwin : current dma window 1324 * @param cmd_dma_offset : current window offset 1325 * @param cmd_dma_len : current window length 1326 * @param cmd_flags : private flags 1327 * @param cmd_cdblen : length of cdb 1328 * @param cmd_scblen : length of scb 1329 * @param cmd_buf : command buffer 1330 * @param channel : channel for scsi sub-system 1331 * @param target : target for scsi sub-system 1332 * @param lun : LUN for scsi sub-system 1333 * 1334 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E) 1335 * - Pointed to by pkt_ha_private field in scsi_pkt 1336 */ 1337 struct scsa_cmd { 1338 ddi_dma_handle_t cmd_dmahandle; 1339 ddi_dma_cookie_t cmd_dmacookies[MEGASAS_MAX_SGE_CNT]; 1340 struct scsi_pkt *cmd_pkt; 1341 ulong_t cmd_dmacount; 1342 uint_t cmd_cookie; 1343 uint_t cmd_ncookies; 1344 uint_t cmd_cookiecnt; 1345 uint_t cmd_nwin; 1346 uint_t cmd_curwin; 1347 off_t cmd_dma_offset; 1348 ulong_t cmd_dma_len; 1349 ulong_t cmd_flags; 1350 uint_t cmd_cdblen; 1351 uint_t cmd_scblen; 1352 struct buf *cmd_buf; 1353 ushort_t device_id; 1354 uchar_t islogical; 1355 uchar_t lun; 1356 }; 1357 1358 1359 struct megasas_cmd { 1360 union megasas_frame *frame; 1361 uint32_t frame_phys_addr; 1362 uint8_t *sense; 1363 uint32_t sense_phys_addr; 1364 dma_obj_t frame_dma_obj; 1365 uint8_t frame_dma_obj_status; 1366 1367 uint32_t index; 1368 uint8_t sync_cmd; 1369 uint8_t cmd_status; 1370 uint16_t abort_aen; 1371 mlist_t list; 1372 uint32_t frame_count; 1373 struct scsa_cmd *cmd; 1374 struct scsi_pkt *pkt; 1375 }; 1376 1377 #define MAX_MGMT_ADAPTERS 1024 1378 #define IOC_SIGNATURE "MEGA-SAS" 1379 1380 #define IOC_CMD_FIRMWARE 0x0 1381 #define MR_DRIVER_IOCTL_COMMON 0xF0010000 1382 #define MR_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100 1383 #define MR_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200 1384 #define MR_DRIVER_IOCTL_MEGARAID_STATISTICS 0xF0010300 1385 1386 1387 #define MR_MAX_SENSE_LENGTH 32 1388 1389 struct megasas_mgmt_info { 1390 1391 uint16_t count; 1392 struct megasas_instance *instance[MAX_MGMT_ADAPTERS]; 1393 uint16_t map[MAX_MGMT_ADAPTERS]; 1394 int max_index; 1395 }; 1396 1397 #pragma pack(1) 1398 1399 struct megasas_drv_ver { 1400 uint8_t signature[12]; 1401 uint8_t os_name[16]; 1402 uint8_t os_ver[12]; 1403 uint8_t drv_name[20]; 1404 uint8_t drv_ver[32]; 1405 uint8_t drv_rel_date[20]; 1406 }; 1407 1408 #define PCI_TYPE0_ADDRESSES 6 1409 #define PCI_TYPE1_ADDRESSES 2 1410 #define PCI_TYPE2_ADDRESSES 5 1411 1412 struct megasas_pci_common_header { 1413 uint16_t vendorID; /* (ro) */ 1414 uint16_t deviceID; /* (ro) */ 1415 uint16_t command; /* Device control */ 1416 uint16_t status; 1417 uint8_t revisionID; /* (ro) */ 1418 uint8_t progIf; /* (ro) */ 1419 uint8_t subClass; /* (ro) */ 1420 uint8_t baseClass; /* (ro) */ 1421 uint8_t cacheLineSize; /* (ro+) */ 1422 uint8_t latencyTimer; /* (ro+) */ 1423 uint8_t headerType; /* (ro) */ 1424 uint8_t bist; /* Built in self test */ 1425 1426 union { 1427 struct { 1428 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 1429 uint32_t cis; 1430 uint16_t subVendorID; 1431 uint16_t subSystemID; 1432 uint32_t romBaseAddress; 1433 uint8_t capabilitiesPtr; 1434 uint8_t reserved1[3]; 1435 uint32_t reserved2; 1436 uint8_t interruptLine; 1437 uint8_t interruptPin; /* (ro) */ 1438 uint8_t minimumGrant; /* (ro) */ 1439 uint8_t maximumLatency; /* (ro) */ 1440 } type_0; 1441 1442 struct { 1443 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 1444 uint8_t primaryBus; 1445 uint8_t secondaryBus; 1446 uint8_t subordinateBus; 1447 uint8_t secondaryLatency; 1448 uint8_t ioBase; 1449 uint8_t ioLimit; 1450 uint16_t secondaryStatus; 1451 uint16_t memoryBase; 1452 uint16_t memoryLimit; 1453 uint16_t prefetchBase; 1454 uint16_t prefetchLimit; 1455 uint32_t prefetchBaseUpper32; 1456 uint32_t prefetchLimitUpper32; 1457 uint16_t ioBaseUpper16; 1458 uint16_t ioLimitUpper16; 1459 uint8_t capabilitiesPtr; 1460 uint8_t reserved1[3]; 1461 uint32_t romBaseAddress; 1462 uint8_t interruptLine; 1463 uint8_t interruptPin; 1464 uint16_t bridgeControl; 1465 } type_1; 1466 1467 struct { 1468 uint32_t socketRegistersBaseAddress; 1469 uint8_t capabilitiesPtr; 1470 uint8_t reserved; 1471 uint16_t secondaryStatus; 1472 uint8_t primaryBus; 1473 uint8_t secondaryBus; 1474 uint8_t subordinateBus; 1475 uint8_t secondaryLatency; 1476 struct { 1477 uint32_t base; 1478 uint32_t limit; 1479 } range[PCI_TYPE2_ADDRESSES-1]; 1480 uint8_t interruptLine; 1481 uint8_t interruptPin; 1482 uint16_t bridgeControl; 1483 } type_2; 1484 } header; 1485 }; 1486 1487 struct megasas_pci_link_capability { 1488 union { 1489 struct { 1490 uint32_t linkSpeed :4; 1491 uint32_t linkWidth :6; 1492 uint32_t aspmSupport :2; 1493 uint32_t losExitLatency :3; 1494 uint32_t l1ExitLatency :3; 1495 uint32_t rsvdp :6; 1496 uint32_t portNumber :8; 1497 } bits; 1498 1499 uint32_t asUlong; 1500 } cap; 1501 1502 }; 1503 1504 struct megasas_pci_link_status_capability { 1505 union { 1506 struct { 1507 uint16_t linkSpeed :4; 1508 uint16_t negotiatedLinkWidth :6; 1509 uint16_t linkTrainingError :1; 1510 uint16_t linkTraning :1; 1511 uint16_t slotClockConfig :1; 1512 uint16_t rsvdZ :3; 1513 } bits; 1514 1515 uint16_t asUshort; 1516 } stat_cap; 1517 1518 uint16_t reserved; 1519 1520 }; 1521 1522 struct megasas_pci_capabilities { 1523 struct megasas_pci_link_capability linkCapability; 1524 struct megasas_pci_link_status_capability linkStatusCapability; 1525 }; 1526 1527 struct megasas_pci_information 1528 { 1529 uint32_t busNumber; 1530 uint8_t deviceNumber; 1531 uint8_t functionNumber; 1532 uint8_t interruptVector; 1533 uint8_t reserved; 1534 struct megasas_pci_common_header pciHeaderInfo; 1535 struct megasas_pci_capabilities capability; 1536 uint8_t reserved2[32]; 1537 }; 1538 1539 struct megasas_ioctl { 1540 uint16_t version; 1541 uint16_t controller_id; 1542 uint8_t signature[8]; 1543 uint32_t reserved_1; 1544 uint32_t control_code; 1545 uint32_t reserved_2[2]; 1546 uint8_t frame[64]; 1547 union megasas_sgl_frame sgl_frame; 1548 uint8_t sense_buff[MR_MAX_SENSE_LENGTH]; 1549 uint8_t data[1]; 1550 }; 1551 1552 struct megasas_aen { 1553 uint16_t host_no; 1554 uint16_t cmd_status; 1555 uint32_t seq_num; 1556 uint32_t class_locale_word; 1557 }; 1558 1559 #pragma pack() 1560 1561 #ifndef DDI_VENDOR_LSI 1562 #define DDI_VENDOR_LSI "LSI" 1563 #endif /* DDI_VENDOR_LSI */ 1564 1565 static int megasas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 1566 static int megasas_attach(dev_info_t *, ddi_attach_cmd_t); 1567 static int megasas_reset(dev_info_t *, ddi_reset_cmd_t); 1568 static int megasas_detach(dev_info_t *, ddi_detach_cmd_t); 1569 static int megasas_open(dev_t *, int, int, cred_t *); 1570 static int megasas_close(dev_t, int, int, cred_t *); 1571 static int megasas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 1572 1573 static int megasas_tran_tgt_init(dev_info_t *, dev_info_t *, 1574 scsi_hba_tran_t *, struct scsi_device *); 1575 #if defined(USELESS) && !defined(lint) 1576 static int megasas_tran_tgt_probe(struct scsi_device *, int); 1577 #endif 1578 static struct scsi_pkt *megasas_tran_init_pkt(struct scsi_address *, register 1579 struct scsi_pkt *, struct buf *, int, int, int, int, 1580 int (*)(), caddr_t); 1581 static int megasas_tran_start(struct scsi_address *, 1582 register struct scsi_pkt *); 1583 static int megasas_tran_abort(struct scsi_address *, struct scsi_pkt *); 1584 static int megasas_tran_reset(struct scsi_address *, int); 1585 static int megasas_tran_bus_reset(dev_info_t *, int); 1586 static int megasas_tran_getcap(struct scsi_address *, char *, int); 1587 static int megasas_tran_setcap(struct scsi_address *, char *, int, int); 1588 static void megasas_tran_destroy_pkt(struct scsi_address *, 1589 struct scsi_pkt *); 1590 static void megasas_tran_dmafree(struct scsi_address *, struct scsi_pkt *); 1591 static void megasas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *); 1592 static int megasas_tran_quiesce(dev_info_t *dip); 1593 static int megasas_tran_unquiesce(dev_info_t *dip); 1594 static uint_t megasas_isr(caddr_t); 1595 static uint_t megasas_softintr(caddr_t); 1596 1597 static int init_mfi(struct megasas_instance *); 1598 static void mega_free_dma_obj(dma_obj_t); 1599 static int mega_alloc_dma_obj(struct megasas_instance *, dma_obj_t *); 1600 static struct megasas_cmd *get_mfi_pkt(struct megasas_instance *); 1601 static void return_mfi_pkt(struct megasas_instance *, 1602 struct megasas_cmd *); 1603 #ifndef lint 1604 static void push_pend_queue(struct megasas_instance *instance, 1605 struct megasas_cmd *cmd); 1606 static struct megasas_cmd *pull_pend_queue(struct megasas_instance *instance); 1607 #endif 1608 static void free_space_for_mfi(struct megasas_instance *); 1609 static void free_additional_dma_buffer(struct megasas_instance *); 1610 static int alloc_additional_dma_buffer(struct megasas_instance *); 1611 static int read_fw_status_reg_xscale(struct megasas_instance *); 1612 static int read_fw_status_reg_ppc(struct megasas_instance *); 1613 static void issue_cmd_xscale(struct megasas_cmd *, 1614 struct megasas_instance *); 1615 static void issue_cmd_ppc(struct megasas_cmd *, struct megasas_instance *); 1616 static int issue_cmd_in_poll_mode_xscale(struct megasas_instance *, 1617 struct megasas_cmd *); 1618 static int issue_cmd_in_poll_mode_ppc(struct megasas_instance *, 1619 struct megasas_cmd *); 1620 static int issue_cmd_in_sync_mode_xscale(struct megasas_instance *, 1621 struct megasas_cmd *); 1622 static int issue_cmd_in_sync_mode_ppc(struct megasas_instance *, 1623 struct megasas_cmd *); 1624 static void enable_intr_xscale(struct megasas_instance *); 1625 static void enable_intr_ppc(struct megasas_instance *); 1626 static void disable_intr_xscale(struct megasas_instance *); 1627 static void disable_intr_ppc(struct megasas_instance *); 1628 static int intr_ack_xscale(struct megasas_instance *); 1629 static int intr_ack_ppc(struct megasas_instance *); 1630 static int mfi_state_transition_to_ready(struct megasas_instance *); 1631 static void destroy_mfi_frame_pool(struct megasas_instance *); 1632 static int create_mfi_frame_pool(struct megasas_instance *); 1633 static int megasas_dma_alloc(struct megasas_instance *, struct scsi_pkt *, 1634 struct buf *, int, int (*)()); 1635 static int megasas_dma_move(struct megasas_instance *, 1636 struct scsi_pkt *, struct buf *); 1637 static void flush_cache(struct megasas_instance *instance); 1638 static void display_scsi_inquiry(caddr_t); 1639 static int start_mfi_aen(struct megasas_instance *instance); 1640 static int handle_drv_ioctl(struct megasas_instance *instance, 1641 struct megasas_ioctl *ioctl, int mode); 1642 static int handle_mfi_ioctl(struct megasas_instance *instance, 1643 struct megasas_ioctl *ioctl, int mode); 1644 static int handle_mfi_aen(struct megasas_instance *instance, 1645 struct megasas_aen *aen); 1646 static void fill_up_drv_ver(struct megasas_drv_ver *dv); 1647 #ifndef lint 1648 static void megasas_minphys(struct buf *bp); 1649 #endif 1650 static struct megasas_cmd *build_cmd(struct megasas_instance *instance, 1651 struct scsi_address *ap, struct scsi_pkt *pkt, 1652 uchar_t *cmd_done); 1653 static int wait_for_outstanding(struct megasas_instance *instance); 1654 static int register_mfi_aen(struct megasas_instance *instance, 1655 uint32_t seq_num, uint32_t class_locale_word); 1656 static int issue_mfi_pthru(struct megasas_instance *instance, struct 1657 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1658 static int issue_mfi_dcmd(struct megasas_instance *instance, struct 1659 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1660 static int issue_mfi_smp(struct megasas_instance *instance, struct 1661 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1662 static int issue_mfi_stp(struct megasas_instance *instance, struct 1663 megasas_ioctl *ioctl, struct megasas_cmd *cmd, int mode); 1664 static int abort_aen_cmd(struct megasas_instance *instance, 1665 struct megasas_cmd *cmd_to_abort); 1666 #if defined(NOT_YET) && !defined(lint) 1667 static void io_timeout_checker(void *instance); 1668 #endif 1669 1670 #ifdef __cplusplus 1671 } 1672 #endif 1673 1674 #endif /* _MEGARAID_SAS_H_ */ 1675