19da57d7bSbt150084 /*
29da57d7bSbt150084 * CDDL HEADER START
39da57d7bSbt150084 *
49da57d7bSbt150084 * The contents of this file are subject to the terms of the
59da57d7bSbt150084 * Common Development and Distribution License (the "License").
69da57d7bSbt150084 * You may not use this file except in compliance with the License.
79da57d7bSbt150084 *
8da14cebeSEric Cheng * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9da14cebeSEric Cheng * or http://www.opensolaris.org/os/licensing.
109da57d7bSbt150084 * See the License for the specific language governing permissions
119da57d7bSbt150084 * and limitations under the License.
129da57d7bSbt150084 *
13da14cebeSEric Cheng * When distributing Covered Code, include this CDDL HEADER in each
14da14cebeSEric Cheng * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
159da57d7bSbt150084 * If applicable, add the following below this CDDL HEADER, with the
169da57d7bSbt150084 * fields enclosed by brackets "[]" replaced with your own identifying
179da57d7bSbt150084 * information: Portions Copyright [yyyy] [name of copyright owner]
189da57d7bSbt150084 *
199da57d7bSbt150084 * CDDL HEADER END
209da57d7bSbt150084 */
219da57d7bSbt150084
229da57d7bSbt150084 /*
235b6dd21fSchenlu chen - Sun Microsystems - Beijing China * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
245b6dd21fSchenlu chen - Sun Microsystems - Beijing China */
255b6dd21fSchenlu chen - Sun Microsystems - Beijing China
265b6dd21fSchenlu chen - Sun Microsystems - Beijing China /*
275b6dd21fSchenlu chen - Sun Microsystems - Beijing China * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
2869b5a878SDan McDonald * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
29dc0cb1cdSDale Ghent * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30168e1ed4SRyan Zezeski * Copyright 2019 Joyent, Inc.
31da14cebeSEric Cheng */
329da57d7bSbt150084
339da57d7bSbt150084 #include "ixgbe_sw.h"
349da57d7bSbt150084
359da57d7bSbt150084 /*
36168e1ed4SRyan Zezeski * The 82598 controller lacks a high/low register for the various
37168e1ed4SRyan Zezeski * octet counters, but the common code also lacks a definition for
38168e1ed4SRyan Zezeski * these older registers. In these cases, the high register address
39168e1ed4SRyan Zezeski * maps to the appropriate address in the 82598 controller.
40168e1ed4SRyan Zezeski */
41168e1ed4SRyan Zezeski #define IXGBE_TOR IXGBE_TORH
42168e1ed4SRyan Zezeski #define IXGBE_GOTC IXGBE_GOTCH
43168e1ed4SRyan Zezeski #define IXGBE_GORC IXGBE_GORCH
44168e1ed4SRyan Zezeski
45168e1ed4SRyan Zezeski /*
46168e1ed4SRyan Zezeski * Read total octets received.
47168e1ed4SRyan Zezeski */
48168e1ed4SRyan Zezeski static uint64_t
ixgbe_read_tor_value(const struct ixgbe_hw * hw)49168e1ed4SRyan Zezeski ixgbe_read_tor_value(const struct ixgbe_hw *hw)
50168e1ed4SRyan Zezeski {
51168e1ed4SRyan Zezeski uint64_t tor = 0;
52168e1ed4SRyan Zezeski uint64_t hi = 0, lo = 0;
53168e1ed4SRyan Zezeski
54168e1ed4SRyan Zezeski switch (hw->mac.type) {
55168e1ed4SRyan Zezeski case ixgbe_mac_82598EB:
56168e1ed4SRyan Zezeski tor = IXGBE_READ_REG(hw, IXGBE_TOR);
57168e1ed4SRyan Zezeski break;
58168e1ed4SRyan Zezeski
59168e1ed4SRyan Zezeski default:
60168e1ed4SRyan Zezeski lo = IXGBE_READ_REG(hw, IXGBE_TORL);
61168e1ed4SRyan Zezeski hi = IXGBE_READ_REG(hw, IXGBE_TORH) & 0xF;
62168e1ed4SRyan Zezeski tor = (hi << 32) + lo;
63168e1ed4SRyan Zezeski break;
64168e1ed4SRyan Zezeski }
65168e1ed4SRyan Zezeski
66168e1ed4SRyan Zezeski return (tor);
67168e1ed4SRyan Zezeski }
68168e1ed4SRyan Zezeski
69168e1ed4SRyan Zezeski /*
70168e1ed4SRyan Zezeski * Read queue octets received.
71168e1ed4SRyan Zezeski */
72168e1ed4SRyan Zezeski static uint64_t
ixgbe_read_qor_value(const struct ixgbe_hw * hw)73168e1ed4SRyan Zezeski ixgbe_read_qor_value(const struct ixgbe_hw *hw)
74168e1ed4SRyan Zezeski {
75168e1ed4SRyan Zezeski uint64_t qor = 0;
76168e1ed4SRyan Zezeski uint64_t hi = 0, lo = 0;
77168e1ed4SRyan Zezeski
78168e1ed4SRyan Zezeski switch (hw->mac.type) {
79168e1ed4SRyan Zezeski case ixgbe_mac_82598EB:
80168e1ed4SRyan Zezeski qor = IXGBE_READ_REG(hw, IXGBE_QBRC(0));
81168e1ed4SRyan Zezeski break;
82168e1ed4SRyan Zezeski
83168e1ed4SRyan Zezeski default:
84168e1ed4SRyan Zezeski lo = IXGBE_READ_REG(hw, IXGBE_QBRC_L(0));
85168e1ed4SRyan Zezeski hi = IXGBE_READ_REG(hw, IXGBE_QBRC_H(0)) & 0xF;
86168e1ed4SRyan Zezeski qor = (hi << 32) + lo;
87168e1ed4SRyan Zezeski break;
88168e1ed4SRyan Zezeski }
89168e1ed4SRyan Zezeski
90168e1ed4SRyan Zezeski return (qor);
91168e1ed4SRyan Zezeski }
92168e1ed4SRyan Zezeski
93168e1ed4SRyan Zezeski /*
94168e1ed4SRyan Zezeski * Read queue octets transmitted.
95168e1ed4SRyan Zezeski */
96168e1ed4SRyan Zezeski static uint64_t
ixgbe_read_qot_value(const struct ixgbe_hw * hw)97168e1ed4SRyan Zezeski ixgbe_read_qot_value(const struct ixgbe_hw *hw)
98168e1ed4SRyan Zezeski {
99168e1ed4SRyan Zezeski uint64_t qot = 0;
100168e1ed4SRyan Zezeski uint64_t hi = 0, lo = 0;
101168e1ed4SRyan Zezeski
102168e1ed4SRyan Zezeski switch (hw->mac.type) {
103168e1ed4SRyan Zezeski case ixgbe_mac_82598EB:
104168e1ed4SRyan Zezeski qot = IXGBE_READ_REG(hw, IXGBE_QBTC(0));
105168e1ed4SRyan Zezeski break;
106168e1ed4SRyan Zezeski
107168e1ed4SRyan Zezeski default:
108168e1ed4SRyan Zezeski lo = IXGBE_READ_REG(hw, IXGBE_QBTC_L(0));
109168e1ed4SRyan Zezeski hi = IXGBE_READ_REG(hw, IXGBE_QBTC_H(0)) & 0xF;
110168e1ed4SRyan Zezeski qot = (hi << 32) + lo;
111168e1ed4SRyan Zezeski break;
112168e1ed4SRyan Zezeski }
113168e1ed4SRyan Zezeski
114168e1ed4SRyan Zezeski return (qot);
115168e1ed4SRyan Zezeski }
116168e1ed4SRyan Zezeski
117168e1ed4SRyan Zezeski /*
118168e1ed4SRyan Zezeski * Read good octets transmitted.
119168e1ed4SRyan Zezeski */
120168e1ed4SRyan Zezeski static uint64_t
ixgbe_read_got_value(const struct ixgbe_hw * hw)121168e1ed4SRyan Zezeski ixgbe_read_got_value(const struct ixgbe_hw *hw)
122168e1ed4SRyan Zezeski {
123168e1ed4SRyan Zezeski uint64_t got = 0;
124168e1ed4SRyan Zezeski uint64_t hi = 0, lo = 0;
125168e1ed4SRyan Zezeski
126168e1ed4SRyan Zezeski switch (hw->mac.type) {
127168e1ed4SRyan Zezeski case ixgbe_mac_82598EB:
128168e1ed4SRyan Zezeski got = IXGBE_READ_REG(hw, IXGBE_GOTC);
129168e1ed4SRyan Zezeski break;
130168e1ed4SRyan Zezeski
131168e1ed4SRyan Zezeski default:
132168e1ed4SRyan Zezeski lo = IXGBE_READ_REG(hw, IXGBE_GOTCL);
133168e1ed4SRyan Zezeski hi = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
134168e1ed4SRyan Zezeski got = (hi << 32) + lo;
135168e1ed4SRyan Zezeski break;
136168e1ed4SRyan Zezeski }
137168e1ed4SRyan Zezeski
138168e1ed4SRyan Zezeski return (got);
139168e1ed4SRyan Zezeski }
140168e1ed4SRyan Zezeski
141168e1ed4SRyan Zezeski /*
142168e1ed4SRyan Zezeski * Read good octets received.
143168e1ed4SRyan Zezeski */
144168e1ed4SRyan Zezeski static uint64_t
ixgbe_read_gor_value(const struct ixgbe_hw * hw)145168e1ed4SRyan Zezeski ixgbe_read_gor_value(const struct ixgbe_hw *hw)
146168e1ed4SRyan Zezeski {
147168e1ed4SRyan Zezeski uint64_t gor = 0;
148168e1ed4SRyan Zezeski uint64_t hi = 0, lo = 0;
149168e1ed4SRyan Zezeski
150168e1ed4SRyan Zezeski switch (hw->mac.type) {
151168e1ed4SRyan Zezeski case ixgbe_mac_82598EB:
152168e1ed4SRyan Zezeski gor = IXGBE_READ_REG(hw, IXGBE_GORC);
153168e1ed4SRyan Zezeski break;
154168e1ed4SRyan Zezeski
155168e1ed4SRyan Zezeski default:
156168e1ed4SRyan Zezeski lo = IXGBE_READ_REG(hw, IXGBE_GORCL);
157168e1ed4SRyan Zezeski hi = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
158168e1ed4SRyan Zezeski gor = (hi << 32) + lo;
159168e1ed4SRyan Zezeski break;
160168e1ed4SRyan Zezeski }
161168e1ed4SRyan Zezeski
162168e1ed4SRyan Zezeski return (gor);
163168e1ed4SRyan Zezeski }
164168e1ed4SRyan Zezeski
165168e1ed4SRyan Zezeski /*
1669da57d7bSbt150084 * Update driver private statistics.
1679da57d7bSbt150084 */
1689da57d7bSbt150084 static int
ixgbe_update_stats(kstat_t * ks,int rw)1699da57d7bSbt150084 ixgbe_update_stats(kstat_t *ks, int rw)
1709da57d7bSbt150084 {
1719da57d7bSbt150084 ixgbe_t *ixgbe;
1729da57d7bSbt150084 struct ixgbe_hw *hw;
1739da57d7bSbt150084 ixgbe_stat_t *ixgbe_ks;
1749da57d7bSbt150084 int i;
1759da57d7bSbt150084
1769da57d7bSbt150084 if (rw == KSTAT_WRITE)
1779da57d7bSbt150084 return (EACCES);
1789da57d7bSbt150084
1799da57d7bSbt150084 ixgbe = (ixgbe_t *)ks->ks_private;
1809da57d7bSbt150084 ixgbe_ks = (ixgbe_stat_t *)ks->ks_data;
1819da57d7bSbt150084 hw = &ixgbe->hw;
1829da57d7bSbt150084
1839da57d7bSbt150084 mutex_enter(&ixgbe->gen_lock);
1849da57d7bSbt150084
1859da57d7bSbt150084 /*
1869da57d7bSbt150084 * Basic information
1879da57d7bSbt150084 */
1889da57d7bSbt150084 ixgbe_ks->link_speed.value.ui64 = ixgbe->link_speed;
1899da57d7bSbt150084 ixgbe_ks->reset_count.value.ui64 = ixgbe->reset_count;
190ffd8e883SWinson Wang - Sun Microsystems - Beijing China ixgbe_ks->lroc.value.ui64 = ixgbe->lro_pkt_count;
1919da57d7bSbt150084
1929da57d7bSbt150084 ixgbe_ks->rx_frame_error.value.ui64 = 0;
1939da57d7bSbt150084 ixgbe_ks->rx_cksum_error.value.ui64 = 0;
1949da57d7bSbt150084 ixgbe_ks->rx_exceed_pkt.value.ui64 = 0;
1959da57d7bSbt150084 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1969da57d7bSbt150084 ixgbe_ks->rx_frame_error.value.ui64 +=
1979da57d7bSbt150084 ixgbe->rx_rings[i].stat_frame_error;
1989da57d7bSbt150084 ixgbe_ks->rx_cksum_error.value.ui64 +=
1999da57d7bSbt150084 ixgbe->rx_rings[i].stat_cksum_error;
2009da57d7bSbt150084 ixgbe_ks->rx_exceed_pkt.value.ui64 +=
2019da57d7bSbt150084 ixgbe->rx_rings[i].stat_exceed_pkt;
2029da57d7bSbt150084 }
2039da57d7bSbt150084
2049da57d7bSbt150084 ixgbe_ks->tx_overload.value.ui64 = 0;
2059da57d7bSbt150084 ixgbe_ks->tx_fail_no_tbd.value.ui64 = 0;
2069da57d7bSbt150084 ixgbe_ks->tx_fail_no_tcb.value.ui64 = 0;
2079da57d7bSbt150084 ixgbe_ks->tx_fail_dma_bind.value.ui64 = 0;
2089da57d7bSbt150084 ixgbe_ks->tx_reschedule.value.ui64 = 0;
20963efadf0SRyan Zezeski ixgbe_ks->tx_break_tbd_limit.value.ui64 = 0;
21063efadf0SRyan Zezeski ixgbe_ks->tx_lso_header_fail.value.ui64 = 0;
2119da57d7bSbt150084 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2129da57d7bSbt150084 ixgbe_ks->tx_overload.value.ui64 +=
2139da57d7bSbt150084 ixgbe->tx_rings[i].stat_overload;
2149da57d7bSbt150084 ixgbe_ks->tx_fail_no_tbd.value.ui64 +=
2159da57d7bSbt150084 ixgbe->tx_rings[i].stat_fail_no_tbd;
2169da57d7bSbt150084 ixgbe_ks->tx_fail_no_tcb.value.ui64 +=
2179da57d7bSbt150084 ixgbe->tx_rings[i].stat_fail_no_tcb;
2189da57d7bSbt150084 ixgbe_ks->tx_fail_dma_bind.value.ui64 +=
2199da57d7bSbt150084 ixgbe->tx_rings[i].stat_fail_dma_bind;
2209da57d7bSbt150084 ixgbe_ks->tx_reschedule.value.ui64 +=
2219da57d7bSbt150084 ixgbe->tx_rings[i].stat_reschedule;
22263efadf0SRyan Zezeski ixgbe_ks->tx_break_tbd_limit.value.ui64 +=
22363efadf0SRyan Zezeski ixgbe->tx_rings[i].stat_break_tbd_limit;
22463efadf0SRyan Zezeski ixgbe_ks->tx_lso_header_fail.value.ui64 +=
22563efadf0SRyan Zezeski ixgbe->tx_rings[i].stat_lso_header_fail;
2269da57d7bSbt150084 }
2279da57d7bSbt150084
2289da57d7bSbt150084 /*
2299da57d7bSbt150084 * Hardware calculated statistics.
2309da57d7bSbt150084 */
231168e1ed4SRyan Zezeski ixgbe_ks->gprc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_GPRC);
232168e1ed4SRyan Zezeski ixgbe_ks->gptc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_GPTC);
233168e1ed4SRyan Zezeski ixgbe_ks->gor.value.ui64 += ixgbe_read_gor_value(hw);
234168e1ed4SRyan Zezeski ixgbe_ks->got.value.ui64 += ixgbe_read_got_value(hw);
235168e1ed4SRyan Zezeski ixgbe_ks->qpr.value.ui64 += IXGBE_READ_REG(hw, IXGBE_QPRC(0));
236168e1ed4SRyan Zezeski ixgbe_ks->qpt.value.ui64 += IXGBE_READ_REG(hw, IXGBE_QPTC(0));
237168e1ed4SRyan Zezeski ixgbe_ks->qor.value.ui64 += ixgbe_read_qor_value(hw);
238168e1ed4SRyan Zezeski ixgbe_ks->qot.value.ui64 += ixgbe_read_qot_value(hw);
239168e1ed4SRyan Zezeski ixgbe_ks->tor.value.ui64 += ixgbe_read_tor_value(hw);
240168e1ed4SRyan Zezeski ixgbe_ks->tot.value.ui64 = ixgbe_ks->got.value.ui64;
2419da57d7bSbt150084
2429da57d7bSbt150084 ixgbe_ks->prc64.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC64);
2439da57d7bSbt150084 ixgbe_ks->prc127.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC127);
2449da57d7bSbt150084 ixgbe_ks->prc255.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC255);
2459da57d7bSbt150084 ixgbe_ks->prc511.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC511);
2469da57d7bSbt150084 ixgbe_ks->prc1023.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2479da57d7bSbt150084 ixgbe_ks->prc1522.value.ul += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2489da57d7bSbt150084 ixgbe_ks->ptc64.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC64);
2499da57d7bSbt150084 ixgbe_ks->ptc127.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC127);
2509da57d7bSbt150084 ixgbe_ks->ptc255.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC255);
2519da57d7bSbt150084 ixgbe_ks->ptc511.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC511);
2529da57d7bSbt150084 ixgbe_ks->ptc1023.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2539da57d7bSbt150084 ixgbe_ks->ptc1522.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2549da57d7bSbt150084
2559da57d7bSbt150084 ixgbe_ks->mspdc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2569da57d7bSbt150084 for (i = 0; i < 8; i++)
2579da57d7bSbt150084 ixgbe_ks->mpc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MPC(i));
2589da57d7bSbt150084 ixgbe_ks->mlfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MLFC);
2599da57d7bSbt150084 ixgbe_ks->mrfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MRFC);
2609da57d7bSbt150084 ixgbe_ks->rlec.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RLEC);
2619da57d7bSbt150084 ixgbe_ks->lxontxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2625b6dd21fSchenlu chen - Sun Microsystems - Beijing China switch (hw->mac.type) {
2635b6dd21fSchenlu chen - Sun Microsystems - Beijing China case ixgbe_mac_82598EB:
26473cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
26573cd555cSBin Tu - Sun Microsystems - Beijing China IXGBE_LXONRXC);
2665b6dd21fSchenlu chen - Sun Microsystems - Beijing China break;
2675b6dd21fSchenlu chen - Sun Microsystems - Beijing China
2685b6dd21fSchenlu chen - Sun Microsystems - Beijing China case ixgbe_mac_82599EB:
26969b5a878SDan McDonald case ixgbe_mac_X540:
270dc0cb1cdSDale Ghent case ixgbe_mac_X550:
271dc0cb1cdSDale Ghent case ixgbe_mac_X550EM_x:
27248ed61a7SRobert Mustacchi case ixgbe_mac_X550EM_a:
27373cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
27473cd555cSBin Tu - Sun Microsystems - Beijing China IXGBE_LXONRXCNT);
2755b6dd21fSchenlu chen - Sun Microsystems - Beijing China break;
2765b6dd21fSchenlu chen - Sun Microsystems - Beijing China
2775b6dd21fSchenlu chen - Sun Microsystems - Beijing China default:
2785b6dd21fSchenlu chen - Sun Microsystems - Beijing China break;
27973cd555cSBin Tu - Sun Microsystems - Beijing China }
2809da57d7bSbt150084 ixgbe_ks->lxofftxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2815b6dd21fSchenlu chen - Sun Microsystems - Beijing China switch (hw->mac.type) {
2825b6dd21fSchenlu chen - Sun Microsystems - Beijing China case ixgbe_mac_82598EB:
28373cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
28473cd555cSBin Tu - Sun Microsystems - Beijing China IXGBE_LXOFFRXC);
2855b6dd21fSchenlu chen - Sun Microsystems - Beijing China break;
2865b6dd21fSchenlu chen - Sun Microsystems - Beijing China
2875b6dd21fSchenlu chen - Sun Microsystems - Beijing China case ixgbe_mac_82599EB:
28869b5a878SDan McDonald case ixgbe_mac_X540:
289dc0cb1cdSDale Ghent case ixgbe_mac_X550:
290dc0cb1cdSDale Ghent case ixgbe_mac_X550EM_x:
29148ed61a7SRobert Mustacchi case ixgbe_mac_X550EM_a:
29273cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
29373cd555cSBin Tu - Sun Microsystems - Beijing China IXGBE_LXOFFRXCNT);
2945b6dd21fSchenlu chen - Sun Microsystems - Beijing China break;
2955b6dd21fSchenlu chen - Sun Microsystems - Beijing China
2965b6dd21fSchenlu chen - Sun Microsystems - Beijing China default:
2975b6dd21fSchenlu chen - Sun Microsystems - Beijing China break;
29873cd555cSBin Tu - Sun Microsystems - Beijing China }
2999da57d7bSbt150084 ixgbe_ks->ruc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RUC);
3009da57d7bSbt150084 ixgbe_ks->rfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RFC);
3019da57d7bSbt150084 ixgbe_ks->roc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_ROC);
3029da57d7bSbt150084 ixgbe_ks->rjc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RJC);
3039da57d7bSbt150084
3049da57d7bSbt150084 mutex_exit(&ixgbe->gen_lock);
3059da57d7bSbt150084
3069da57d7bSbt150084 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK)
3079da57d7bSbt150084 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_UNAFFECTED);
3089da57d7bSbt150084
3099da57d7bSbt150084 return (0);
3109da57d7bSbt150084 }
3119da57d7bSbt150084
3129da57d7bSbt150084 /*
3139da57d7bSbt150084 * Create and initialize the driver private statistics.
3149da57d7bSbt150084 */
3159da57d7bSbt150084 int
ixgbe_init_stats(ixgbe_t * ixgbe)3169da57d7bSbt150084 ixgbe_init_stats(ixgbe_t *ixgbe)
3179da57d7bSbt150084 {
3189da57d7bSbt150084 kstat_t *ks;
3199da57d7bSbt150084 ixgbe_stat_t *ixgbe_ks;
3209da57d7bSbt150084
3219da57d7bSbt150084 /*
3229da57d7bSbt150084 * Create and init kstat
3239da57d7bSbt150084 */
3249da57d7bSbt150084 ks = kstat_create(MODULE_NAME, ddi_get_instance(ixgbe->dip),
3259da57d7bSbt150084 "statistics", "net", KSTAT_TYPE_NAMED,
3269da57d7bSbt150084 sizeof (ixgbe_stat_t) / sizeof (kstat_named_t), 0);
3279da57d7bSbt150084
3289da57d7bSbt150084 if (ks == NULL) {
3299da57d7bSbt150084 ixgbe_error(ixgbe,
3309da57d7bSbt150084 "Could not create kernel statistics");
3319da57d7bSbt150084 return (IXGBE_FAILURE);
3329da57d7bSbt150084 }
3339da57d7bSbt150084
3349da57d7bSbt150084 ixgbe->ixgbe_ks = ks;
3359da57d7bSbt150084
3369da57d7bSbt150084 ixgbe_ks = (ixgbe_stat_t *)ks->ks_data;
3379da57d7bSbt150084
3389da57d7bSbt150084 /*
3399da57d7bSbt150084 * Initialize all the statistics.
3409da57d7bSbt150084 */
3419da57d7bSbt150084 kstat_named_init(&ixgbe_ks->link_speed, "link_speed",
3429da57d7bSbt150084 KSTAT_DATA_UINT64);
3439da57d7bSbt150084 kstat_named_init(&ixgbe_ks->reset_count, "reset_count",
3449da57d7bSbt150084 KSTAT_DATA_UINT64);
3453cfa0eb9Schenlu chen - Sun Microsystems - Beijing China
3469da57d7bSbt150084 kstat_named_init(&ixgbe_ks->rx_frame_error, "rx_frame_error",
3479da57d7bSbt150084 KSTAT_DATA_UINT64);
3489da57d7bSbt150084 kstat_named_init(&ixgbe_ks->rx_cksum_error, "rx_cksum_error",
3499da57d7bSbt150084 KSTAT_DATA_UINT64);
3509da57d7bSbt150084 kstat_named_init(&ixgbe_ks->rx_exceed_pkt, "rx_exceed_pkt",
3519da57d7bSbt150084 KSTAT_DATA_UINT64);
3529da57d7bSbt150084 kstat_named_init(&ixgbe_ks->tx_overload, "tx_overload",
3539da57d7bSbt150084 KSTAT_DATA_UINT64);
3549da57d7bSbt150084 kstat_named_init(&ixgbe_ks->tx_fail_no_tbd, "tx_fail_no_tbd",
3559da57d7bSbt150084 KSTAT_DATA_UINT64);
3569da57d7bSbt150084 kstat_named_init(&ixgbe_ks->tx_fail_no_tcb, "tx_fail_no_tcb",
3579da57d7bSbt150084 KSTAT_DATA_UINT64);
3589da57d7bSbt150084 kstat_named_init(&ixgbe_ks->tx_fail_dma_bind, "tx_fail_dma_bind",
3599da57d7bSbt150084 KSTAT_DATA_UINT64);
3609da57d7bSbt150084 kstat_named_init(&ixgbe_ks->tx_reschedule, "tx_reschedule",
3619da57d7bSbt150084 KSTAT_DATA_UINT64);
36263efadf0SRyan Zezeski kstat_named_init(&ixgbe_ks->tx_break_tbd_limit, "tx_break_tbd_limit",
36363efadf0SRyan Zezeski KSTAT_DATA_UINT64);
36463efadf0SRyan Zezeski kstat_named_init(&ixgbe_ks->tx_lso_header_fail, "tx_lso_header_fail",
36563efadf0SRyan Zezeski KSTAT_DATA_UINT64);
3669da57d7bSbt150084
3679da57d7bSbt150084 kstat_named_init(&ixgbe_ks->gprc, "good_pkts_recvd",
3689da57d7bSbt150084 KSTAT_DATA_UINT64);
3699da57d7bSbt150084 kstat_named_init(&ixgbe_ks->gptc, "good_pkts_xmitd",
3709da57d7bSbt150084 KSTAT_DATA_UINT64);
3719da57d7bSbt150084 kstat_named_init(&ixgbe_ks->gor, "good_octets_recvd",
3729da57d7bSbt150084 KSTAT_DATA_UINT64);
3739da57d7bSbt150084 kstat_named_init(&ixgbe_ks->got, "good_octets_xmitd",
3749da57d7bSbt150084 KSTAT_DATA_UINT64);
375168e1ed4SRyan Zezeski kstat_named_init(&ixgbe_ks->qor, "queue_octets_recvd",
376168e1ed4SRyan Zezeski KSTAT_DATA_UINT64);
377168e1ed4SRyan Zezeski kstat_named_init(&ixgbe_ks->qot, "queue_octets_xmitd",
378168e1ed4SRyan Zezeski KSTAT_DATA_UINT64);
379168e1ed4SRyan Zezeski kstat_named_init(&ixgbe_ks->qpr, "queue_pkts_recvd",
380168e1ed4SRyan Zezeski KSTAT_DATA_UINT64);
381168e1ed4SRyan Zezeski kstat_named_init(&ixgbe_ks->qpt, "queue_pkts_xmitd",
382168e1ed4SRyan Zezeski KSTAT_DATA_UINT64);
3839da57d7bSbt150084 kstat_named_init(&ixgbe_ks->prc64, "pkts_recvd_( 64b)",
3849da57d7bSbt150084 KSTAT_DATA_UINT64);
3859da57d7bSbt150084 kstat_named_init(&ixgbe_ks->prc127, "pkts_recvd_( 65- 127b)",
3869da57d7bSbt150084 KSTAT_DATA_UINT64);
3879da57d7bSbt150084 kstat_named_init(&ixgbe_ks->prc255, "pkts_recvd_( 127- 255b)",
3889da57d7bSbt150084 KSTAT_DATA_UINT64);
3899da57d7bSbt150084 kstat_named_init(&ixgbe_ks->prc511, "pkts_recvd_( 256- 511b)",
3909da57d7bSbt150084 KSTAT_DATA_UINT64);
3919da57d7bSbt150084 kstat_named_init(&ixgbe_ks->prc1023, "pkts_recvd_( 511-1023b)",
3929da57d7bSbt150084 KSTAT_DATA_UINT64);
3939da57d7bSbt150084 kstat_named_init(&ixgbe_ks->prc1522, "pkts_recvd_(1024-1522b)",
3949da57d7bSbt150084 KSTAT_DATA_UINT64);
3959da57d7bSbt150084 kstat_named_init(&ixgbe_ks->ptc64, "pkts_xmitd_( 64b)",
3969da57d7bSbt150084 KSTAT_DATA_UINT64);
3979da57d7bSbt150084 kstat_named_init(&ixgbe_ks->ptc127, "pkts_xmitd_( 65- 127b)",
3989da57d7bSbt150084 KSTAT_DATA_UINT64);
3999da57d7bSbt150084 kstat_named_init(&ixgbe_ks->ptc255, "pkts_xmitd_( 128- 255b)",
4009da57d7bSbt150084 KSTAT_DATA_UINT64);
4019da57d7bSbt150084 kstat_named_init(&ixgbe_ks->ptc511, "pkts_xmitd_( 255- 511b)",
4029da57d7bSbt150084 KSTAT_DATA_UINT64);
4039da57d7bSbt150084 kstat_named_init(&ixgbe_ks->ptc1023, "pkts_xmitd_( 512-1023b)",
4049da57d7bSbt150084 KSTAT_DATA_UINT64);
4059da57d7bSbt150084 kstat_named_init(&ixgbe_ks->ptc1522, "pkts_xmitd_(1024-1522b)",
4069da57d7bSbt150084 KSTAT_DATA_UINT64);
407da14cebeSEric Cheng
4089da57d7bSbt150084 kstat_named_init(&ixgbe_ks->mspdc, "mac_short_packet_discard",
4099da57d7bSbt150084 KSTAT_DATA_UINT64);
4109da57d7bSbt150084 kstat_named_init(&ixgbe_ks->mpc, "missed_packets",
4119da57d7bSbt150084 KSTAT_DATA_UINT64);
4129da57d7bSbt150084 kstat_named_init(&ixgbe_ks->mlfc, "mac_local_fault",
4139da57d7bSbt150084 KSTAT_DATA_UINT64);
4149da57d7bSbt150084 kstat_named_init(&ixgbe_ks->mrfc, "mac_remote_fault",
4159da57d7bSbt150084 KSTAT_DATA_UINT64);
4169da57d7bSbt150084 kstat_named_init(&ixgbe_ks->rlec, "recv_length_err",
4179da57d7bSbt150084 KSTAT_DATA_UINT64);
4189da57d7bSbt150084 kstat_named_init(&ixgbe_ks->lxontxc, "link_xon_xmitd",
4199da57d7bSbt150084 KSTAT_DATA_UINT64);
4209da57d7bSbt150084 kstat_named_init(&ixgbe_ks->lxonrxc, "link_xon_recvd",
4219da57d7bSbt150084 KSTAT_DATA_UINT64);
4229da57d7bSbt150084 kstat_named_init(&ixgbe_ks->lxofftxc, "link_xoff_xmitd",
4239da57d7bSbt150084 KSTAT_DATA_UINT64);
4249da57d7bSbt150084 kstat_named_init(&ixgbe_ks->lxoffrxc, "link_xoff_recvd",
4259da57d7bSbt150084 KSTAT_DATA_UINT64);
4269da57d7bSbt150084 kstat_named_init(&ixgbe_ks->ruc, "recv_undersize",
4279da57d7bSbt150084 KSTAT_DATA_UINT64);
4289da57d7bSbt150084 kstat_named_init(&ixgbe_ks->rfc, "recv_fragment",
4299da57d7bSbt150084 KSTAT_DATA_UINT64);
4309da57d7bSbt150084 kstat_named_init(&ixgbe_ks->roc, "recv_oversize",
4319da57d7bSbt150084 KSTAT_DATA_UINT64);
4329da57d7bSbt150084 kstat_named_init(&ixgbe_ks->rjc, "recv_jabber",
4339da57d7bSbt150084 KSTAT_DATA_UINT64);
43413740cb2SPaul Guo kstat_named_init(&ixgbe_ks->rnbc, "recv_no_buffer",
43513740cb2SPaul Guo KSTAT_DATA_UINT64);
436ffd8e883SWinson Wang - Sun Microsystems - Beijing China kstat_named_init(&ixgbe_ks->lroc, "lro_pkt_count",
437ffd8e883SWinson Wang - Sun Microsystems - Beijing China KSTAT_DATA_UINT64);
43874b989c3SRobert Mustacchi
43974b989c3SRobert Mustacchi kstat_named_init(&ixgbe_ks->dev_gone, "device_gone",
44074b989c3SRobert Mustacchi KSTAT_DATA_UINT64);
4419da57d7bSbt150084 /*
4429da57d7bSbt150084 * Function to provide kernel stat update on demand
4439da57d7bSbt150084 */
4449da57d7bSbt150084 ks->ks_update = ixgbe_update_stats;
4459da57d7bSbt150084
4469da57d7bSbt150084 ks->ks_private = (void *)ixgbe;
4479da57d7bSbt150084
4489da57d7bSbt150084 /*
4499da57d7bSbt150084 * Add kstat to systems kstat chain
4509da57d7bSbt150084 */
4519da57d7bSbt150084 kstat_install(ks);
4529da57d7bSbt150084
4539da57d7bSbt150084 return (IXGBE_SUCCESS);
4549da57d7bSbt150084 }
4550dc2366fSVenugopal Iyer
4560dc2366fSVenugopal Iyer /*
4570dc2366fSVenugopal Iyer * Retrieve a value for one of the statistics.
4580dc2366fSVenugopal Iyer */
4590dc2366fSVenugopal Iyer int
ixgbe_m_stat(void * arg,uint_t stat,uint64_t * val)4600dc2366fSVenugopal Iyer ixgbe_m_stat(void *arg, uint_t stat, uint64_t *val)
4610dc2366fSVenugopal Iyer {
4620dc2366fSVenugopal Iyer ixgbe_t *ixgbe = (ixgbe_t *)arg;
4630dc2366fSVenugopal Iyer struct ixgbe_hw *hw = &ixgbe->hw;
4640dc2366fSVenugopal Iyer ixgbe_stat_t *ixgbe_ks;
4650dc2366fSVenugopal Iyer int i;
466dc0cb1cdSDale Ghent ixgbe_link_speed speeds = 0;
4670dc2366fSVenugopal Iyer
4680dc2366fSVenugopal Iyer ixgbe_ks = (ixgbe_stat_t *)ixgbe->ixgbe_ks->ks_data;
4690dc2366fSVenugopal Iyer
4700dc2366fSVenugopal Iyer mutex_enter(&ixgbe->gen_lock);
4710dc2366fSVenugopal Iyer
472dc0cb1cdSDale Ghent /*
473dc0cb1cdSDale Ghent * We cannot always rely on the common code maintaining
474dc0cb1cdSDale Ghent * hw->phy.speeds_supported, therefore we fall back to use the recorded
475dc0cb1cdSDale Ghent * supported speeds which were obtained during instance init in
476dc0cb1cdSDale Ghent * ixgbe_init_params().
477dc0cb1cdSDale Ghent */
478dc0cb1cdSDale Ghent speeds = hw->phy.speeds_supported;
479dc0cb1cdSDale Ghent if (speeds == 0)
480dc0cb1cdSDale Ghent speeds = ixgbe->speeds_supported;
481dc0cb1cdSDale Ghent
4820dc2366fSVenugopal Iyer if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
4830dc2366fSVenugopal Iyer mutex_exit(&ixgbe->gen_lock);
4840dc2366fSVenugopal Iyer return (ECANCELED);
4850dc2366fSVenugopal Iyer }
4860dc2366fSVenugopal Iyer
4870dc2366fSVenugopal Iyer switch (stat) {
4880dc2366fSVenugopal Iyer case MAC_STAT_IFSPEED:
4890dc2366fSVenugopal Iyer *val = ixgbe->link_speed * 1000000ull;
4900dc2366fSVenugopal Iyer break;
4910dc2366fSVenugopal Iyer
4920dc2366fSVenugopal Iyer case MAC_STAT_MULTIRCV:
4930dc2366fSVenugopal Iyer ixgbe_ks->mprc.value.ui64 +=
4940dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_MPRC);
4950dc2366fSVenugopal Iyer *val = ixgbe_ks->mprc.value.ui64;
4960dc2366fSVenugopal Iyer break;
4970dc2366fSVenugopal Iyer
4980dc2366fSVenugopal Iyer case MAC_STAT_BRDCSTRCV:
4990dc2366fSVenugopal Iyer ixgbe_ks->bprc.value.ui64 +=
5000dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_BPRC);
5010dc2366fSVenugopal Iyer *val = ixgbe_ks->bprc.value.ui64;
5020dc2366fSVenugopal Iyer break;
5030dc2366fSVenugopal Iyer
5040dc2366fSVenugopal Iyer case MAC_STAT_MULTIXMT:
5050dc2366fSVenugopal Iyer ixgbe_ks->mptc.value.ui64 +=
5060dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_MPTC);
5070dc2366fSVenugopal Iyer *val = ixgbe_ks->mptc.value.ui64;
5080dc2366fSVenugopal Iyer break;
5090dc2366fSVenugopal Iyer
5100dc2366fSVenugopal Iyer case MAC_STAT_BRDCSTXMT:
5110dc2366fSVenugopal Iyer ixgbe_ks->bptc.value.ui64 +=
5120dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_BPTC);
5130dc2366fSVenugopal Iyer *val = ixgbe_ks->bptc.value.ui64;
5140dc2366fSVenugopal Iyer break;
5150dc2366fSVenugopal Iyer
5160dc2366fSVenugopal Iyer case MAC_STAT_NORCVBUF:
517168e1ed4SRyan Zezeski /*
518168e1ed4SRyan Zezeski * The QPRDC[0] register maps to the same kstat as the
519168e1ed4SRyan Zezeski * old RNBC register because they have equivalent
520168e1ed4SRyan Zezeski * semantics.
521168e1ed4SRyan Zezeski */
522168e1ed4SRyan Zezeski if (hw->mac.type == ixgbe_mac_82598EB) {
5230dc2366fSVenugopal Iyer for (i = 0; i < 8; i++) {
5240dc2366fSVenugopal Iyer ixgbe_ks->rnbc.value.ui64 +=
5250dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5260dc2366fSVenugopal Iyer }
527168e1ed4SRyan Zezeski } else {
528168e1ed4SRyan Zezeski ixgbe_ks->rnbc.value.ui64 +=
529168e1ed4SRyan Zezeski IXGBE_READ_REG(hw, IXGBE_QPRDC(0));
530168e1ed4SRyan Zezeski }
531168e1ed4SRyan Zezeski
5320dc2366fSVenugopal Iyer *val = ixgbe_ks->rnbc.value.ui64;
5330dc2366fSVenugopal Iyer break;
5340dc2366fSVenugopal Iyer
5350dc2366fSVenugopal Iyer case MAC_STAT_IERRORS:
5360dc2366fSVenugopal Iyer ixgbe_ks->crcerrs.value.ui64 +=
5370dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5380dc2366fSVenugopal Iyer ixgbe_ks->illerrc.value.ui64 +=
5390dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_ILLERRC);
5400dc2366fSVenugopal Iyer ixgbe_ks->errbc.value.ui64 +=
5410dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_ERRBC);
5420dc2366fSVenugopal Iyer ixgbe_ks->rlec.value.ui64 +=
5430dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_RLEC);
5440dc2366fSVenugopal Iyer *val = ixgbe_ks->crcerrs.value.ui64 +
5450dc2366fSVenugopal Iyer ixgbe_ks->illerrc.value.ui64 +
5460dc2366fSVenugopal Iyer ixgbe_ks->errbc.value.ui64 +
5470dc2366fSVenugopal Iyer ixgbe_ks->rlec.value.ui64;
5480dc2366fSVenugopal Iyer break;
5490dc2366fSVenugopal Iyer
5500dc2366fSVenugopal Iyer case MAC_STAT_RBYTES:
551168e1ed4SRyan Zezeski ixgbe_ks->tor.value.ui64 += ixgbe_read_tor_value(hw);
5520dc2366fSVenugopal Iyer *val = ixgbe_ks->tor.value.ui64;
5530dc2366fSVenugopal Iyer break;
5540dc2366fSVenugopal Iyer
5550dc2366fSVenugopal Iyer case MAC_STAT_OBYTES:
556168e1ed4SRyan Zezeski /*
557168e1ed4SRyan Zezeski * The controller does not provide a Total Octets
558168e1ed4SRyan Zezeski * Transmitted statistic. The closest thing we have is
559168e1ed4SRyan Zezeski * Good Octets Transmitted. This makes sense, as what
560168e1ed4SRyan Zezeski * does it mean to transmit a packet if it didn't
561168e1ed4SRyan Zezeski * actually transmit.
562168e1ed4SRyan Zezeski */
563168e1ed4SRyan Zezeski ixgbe_ks->got.value.ui64 += ixgbe_read_got_value(hw);
564168e1ed4SRyan Zezeski ixgbe_ks->tot.value.ui64 = ixgbe_ks->got.value.ui64;
5650dc2366fSVenugopal Iyer *val = ixgbe_ks->tot.value.ui64;
5660dc2366fSVenugopal Iyer break;
5670dc2366fSVenugopal Iyer
5680dc2366fSVenugopal Iyer case MAC_STAT_IPACKETS:
5690dc2366fSVenugopal Iyer ixgbe_ks->tpr.value.ui64 +=
5700dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_TPR);
5710dc2366fSVenugopal Iyer *val = ixgbe_ks->tpr.value.ui64;
5720dc2366fSVenugopal Iyer break;
5730dc2366fSVenugopal Iyer
5740dc2366fSVenugopal Iyer case MAC_STAT_OPACKETS:
5750dc2366fSVenugopal Iyer ixgbe_ks->tpt.value.ui64 +=
5760dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_TPT);
5770dc2366fSVenugopal Iyer *val = ixgbe_ks->tpt.value.ui64;
5780dc2366fSVenugopal Iyer break;
5790dc2366fSVenugopal Iyer
5800dc2366fSVenugopal Iyer /* RFC 1643 stats */
5810dc2366fSVenugopal Iyer case ETHER_STAT_FCS_ERRORS:
5820dc2366fSVenugopal Iyer ixgbe_ks->crcerrs.value.ui64 +=
5830dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5840dc2366fSVenugopal Iyer *val = ixgbe_ks->crcerrs.value.ui64;
5850dc2366fSVenugopal Iyer break;
5860dc2366fSVenugopal Iyer
5870dc2366fSVenugopal Iyer case ETHER_STAT_TOOLONG_ERRORS:
5880dc2366fSVenugopal Iyer ixgbe_ks->roc.value.ui64 +=
5890dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_ROC);
5900dc2366fSVenugopal Iyer *val = ixgbe_ks->roc.value.ui64;
5910dc2366fSVenugopal Iyer break;
5920dc2366fSVenugopal Iyer
5930dc2366fSVenugopal Iyer case ETHER_STAT_MACRCV_ERRORS:
5940dc2366fSVenugopal Iyer ixgbe_ks->crcerrs.value.ui64 +=
5950dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5960dc2366fSVenugopal Iyer ixgbe_ks->illerrc.value.ui64 +=
5970dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_ILLERRC);
5980dc2366fSVenugopal Iyer ixgbe_ks->errbc.value.ui64 +=
5990dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_ERRBC);
6000dc2366fSVenugopal Iyer ixgbe_ks->rlec.value.ui64 +=
6010dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_RLEC);
6020dc2366fSVenugopal Iyer *val = ixgbe_ks->crcerrs.value.ui64 +
6030dc2366fSVenugopal Iyer ixgbe_ks->illerrc.value.ui64 +
6040dc2366fSVenugopal Iyer ixgbe_ks->errbc.value.ui64 +
6050dc2366fSVenugopal Iyer ixgbe_ks->rlec.value.ui64;
6060dc2366fSVenugopal Iyer break;
6070dc2366fSVenugopal Iyer
6080dc2366fSVenugopal Iyer /* MII/GMII stats */
6090dc2366fSVenugopal Iyer case ETHER_STAT_XCVR_ADDR:
6100dc2366fSVenugopal Iyer /* The Internal PHY's MDI address for each MAC is 1 */
6110dc2366fSVenugopal Iyer *val = 1;
6120dc2366fSVenugopal Iyer break;
6130dc2366fSVenugopal Iyer
6140dc2366fSVenugopal Iyer case ETHER_STAT_XCVR_ID:
6150dc2366fSVenugopal Iyer *val = hw->phy.id;
6160dc2366fSVenugopal Iyer break;
6170dc2366fSVenugopal Iyer
6180dc2366fSVenugopal Iyer case ETHER_STAT_XCVR_INUSE:
619*633c5e5cSRobert Mustacchi *val = (uint64_t)ixgbe_phy_to_media(ixgbe);
6200dc2366fSVenugopal Iyer break;
6210dc2366fSVenugopal Iyer
6220dc2366fSVenugopal Iyer case ETHER_STAT_CAP_10GFDX:
623dc0cb1cdSDale Ghent *val = (speeds & IXGBE_LINK_SPEED_10GB_FULL) ? 1 : 0;
624dc0cb1cdSDale Ghent break;
625dc0cb1cdSDale Ghent
626dc0cb1cdSDale Ghent case ETHER_STAT_CAP_5000FDX:
627dc0cb1cdSDale Ghent *val = (speeds & IXGBE_LINK_SPEED_5GB_FULL) ? 1 : 0;
628dc0cb1cdSDale Ghent break;
629dc0cb1cdSDale Ghent
630dc0cb1cdSDale Ghent case ETHER_STAT_CAP_2500FDX:
631dc0cb1cdSDale Ghent *val = (speeds & IXGBE_LINK_SPEED_2_5GB_FULL) ? 1 : 0;
6320dc2366fSVenugopal Iyer break;
6330dc2366fSVenugopal Iyer
6340dc2366fSVenugopal Iyer case ETHER_STAT_CAP_1000FDX:
635dc0cb1cdSDale Ghent *val = (speeds & IXGBE_LINK_SPEED_1GB_FULL) ? 1 : 0;
6360dc2366fSVenugopal Iyer break;
6370dc2366fSVenugopal Iyer
6380dc2366fSVenugopal Iyer case ETHER_STAT_CAP_100FDX:
639dc0cb1cdSDale Ghent *val = (speeds & IXGBE_LINK_SPEED_100_FULL) ? 1 : 0;
6400dc2366fSVenugopal Iyer break;
6410dc2366fSVenugopal Iyer
6420dc2366fSVenugopal Iyer case ETHER_STAT_CAP_ASMPAUSE:
6430dc2366fSVenugopal Iyer *val = ixgbe->param_asym_pause_cap;
6440dc2366fSVenugopal Iyer break;
6450dc2366fSVenugopal Iyer
6460dc2366fSVenugopal Iyer case ETHER_STAT_CAP_PAUSE:
6470dc2366fSVenugopal Iyer *val = ixgbe->param_pause_cap;
6480dc2366fSVenugopal Iyer break;
6490dc2366fSVenugopal Iyer
6500dc2366fSVenugopal Iyer case ETHER_STAT_CAP_AUTONEG:
6510dc2366fSVenugopal Iyer *val = 1;
6520dc2366fSVenugopal Iyer break;
6530dc2366fSVenugopal Iyer
6540dc2366fSVenugopal Iyer case ETHER_STAT_ADV_CAP_10GFDX:
6550dc2366fSVenugopal Iyer *val = ixgbe->param_adv_10000fdx_cap;
6560dc2366fSVenugopal Iyer break;
6570dc2366fSVenugopal Iyer
658dc0cb1cdSDale Ghent case ETHER_STAT_ADV_CAP_5000FDX:
659dc0cb1cdSDale Ghent *val = ixgbe->param_adv_5000fdx_cap;
660dc0cb1cdSDale Ghent break;
661dc0cb1cdSDale Ghent
662dc0cb1cdSDale Ghent case ETHER_STAT_ADV_CAP_2500FDX:
663dc0cb1cdSDale Ghent *val = ixgbe->param_adv_2500fdx_cap;
664dc0cb1cdSDale Ghent break;
665dc0cb1cdSDale Ghent
6660dc2366fSVenugopal Iyer case ETHER_STAT_ADV_CAP_1000FDX:
6670dc2366fSVenugopal Iyer *val = ixgbe->param_adv_1000fdx_cap;
6680dc2366fSVenugopal Iyer break;
6690dc2366fSVenugopal Iyer
6700dc2366fSVenugopal Iyer case ETHER_STAT_ADV_CAP_100FDX:
6710dc2366fSVenugopal Iyer *val = ixgbe->param_adv_100fdx_cap;
6720dc2366fSVenugopal Iyer break;
6730dc2366fSVenugopal Iyer
6740dc2366fSVenugopal Iyer case ETHER_STAT_ADV_CAP_ASMPAUSE:
6750dc2366fSVenugopal Iyer *val = ixgbe->param_adv_asym_pause_cap;
6760dc2366fSVenugopal Iyer break;
6770dc2366fSVenugopal Iyer
6780dc2366fSVenugopal Iyer case ETHER_STAT_ADV_CAP_PAUSE:
6790dc2366fSVenugopal Iyer *val = ixgbe->param_adv_pause_cap;
6800dc2366fSVenugopal Iyer break;
6810dc2366fSVenugopal Iyer
6820dc2366fSVenugopal Iyer case ETHER_STAT_ADV_CAP_AUTONEG:
6830dc2366fSVenugopal Iyer *val = ixgbe->param_adv_autoneg_cap;
6840dc2366fSVenugopal Iyer break;
6850dc2366fSVenugopal Iyer
6860dc2366fSVenugopal Iyer case ETHER_STAT_LP_CAP_10GFDX:
6870dc2366fSVenugopal Iyer *val = ixgbe->param_lp_10000fdx_cap;
6880dc2366fSVenugopal Iyer break;
6890dc2366fSVenugopal Iyer
690dc0cb1cdSDale Ghent case ETHER_STAT_LP_CAP_5000FDX:
691dc0cb1cdSDale Ghent *val = ixgbe->param_lp_5000fdx_cap;
692dc0cb1cdSDale Ghent break;
693dc0cb1cdSDale Ghent
694dc0cb1cdSDale Ghent case ETHER_STAT_LP_CAP_2500FDX:
695dc0cb1cdSDale Ghent *val = ixgbe->param_lp_2500fdx_cap;
696dc0cb1cdSDale Ghent break;
697dc0cb1cdSDale Ghent
6980dc2366fSVenugopal Iyer case ETHER_STAT_LP_CAP_1000FDX:
6990dc2366fSVenugopal Iyer *val = ixgbe->param_lp_1000fdx_cap;
7000dc2366fSVenugopal Iyer break;
7010dc2366fSVenugopal Iyer
7020dc2366fSVenugopal Iyer case ETHER_STAT_LP_CAP_100FDX:
7030dc2366fSVenugopal Iyer *val = ixgbe->param_lp_100fdx_cap;
7040dc2366fSVenugopal Iyer break;
7050dc2366fSVenugopal Iyer
7060dc2366fSVenugopal Iyer case ETHER_STAT_LP_CAP_ASMPAUSE:
7070dc2366fSVenugopal Iyer *val = ixgbe->param_lp_asym_pause_cap;
7080dc2366fSVenugopal Iyer break;
7090dc2366fSVenugopal Iyer
7100dc2366fSVenugopal Iyer case ETHER_STAT_LP_CAP_PAUSE:
7110dc2366fSVenugopal Iyer *val = ixgbe->param_lp_pause_cap;
7120dc2366fSVenugopal Iyer break;
7130dc2366fSVenugopal Iyer
7140dc2366fSVenugopal Iyer case ETHER_STAT_LP_CAP_AUTONEG:
7150dc2366fSVenugopal Iyer *val = ixgbe->param_lp_autoneg_cap;
7160dc2366fSVenugopal Iyer break;
7170dc2366fSVenugopal Iyer
7180dc2366fSVenugopal Iyer case ETHER_STAT_LINK_ASMPAUSE:
7190dc2366fSVenugopal Iyer *val = ixgbe->param_asym_pause_cap;
7200dc2366fSVenugopal Iyer break;
7210dc2366fSVenugopal Iyer
7220dc2366fSVenugopal Iyer case ETHER_STAT_LINK_PAUSE:
7230dc2366fSVenugopal Iyer *val = ixgbe->param_pause_cap;
7240dc2366fSVenugopal Iyer break;
7250dc2366fSVenugopal Iyer
7260dc2366fSVenugopal Iyer case ETHER_STAT_LINK_AUTONEG:
7270dc2366fSVenugopal Iyer *val = ixgbe->param_adv_autoneg_cap;
7280dc2366fSVenugopal Iyer break;
7290dc2366fSVenugopal Iyer
7300dc2366fSVenugopal Iyer case ETHER_STAT_LINK_DUPLEX:
7310dc2366fSVenugopal Iyer *val = ixgbe->link_duplex;
7320dc2366fSVenugopal Iyer break;
7330dc2366fSVenugopal Iyer
7340dc2366fSVenugopal Iyer case ETHER_STAT_TOOSHORT_ERRORS:
7350dc2366fSVenugopal Iyer ixgbe_ks->ruc.value.ui64 +=
7360dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_RUC);
7370dc2366fSVenugopal Iyer *val = ixgbe_ks->ruc.value.ui64;
7380dc2366fSVenugopal Iyer break;
7390dc2366fSVenugopal Iyer
7400dc2366fSVenugopal Iyer case ETHER_STAT_CAP_REMFAULT:
7410dc2366fSVenugopal Iyer *val = ixgbe->param_rem_fault;
7420dc2366fSVenugopal Iyer break;
7430dc2366fSVenugopal Iyer
7440dc2366fSVenugopal Iyer case ETHER_STAT_ADV_REMFAULT:
7450dc2366fSVenugopal Iyer *val = ixgbe->param_adv_rem_fault;
7460dc2366fSVenugopal Iyer break;
7470dc2366fSVenugopal Iyer
7480dc2366fSVenugopal Iyer case ETHER_STAT_LP_REMFAULT:
7490dc2366fSVenugopal Iyer *val = ixgbe->param_lp_rem_fault;
7500dc2366fSVenugopal Iyer break;
7510dc2366fSVenugopal Iyer
7520dc2366fSVenugopal Iyer case ETHER_STAT_JABBER_ERRORS:
7530dc2366fSVenugopal Iyer ixgbe_ks->rjc.value.ui64 +=
7540dc2366fSVenugopal Iyer IXGBE_READ_REG(hw, IXGBE_RJC);
7550dc2366fSVenugopal Iyer *val = ixgbe_ks->rjc.value.ui64;
7560dc2366fSVenugopal Iyer break;
7570dc2366fSVenugopal Iyer
7580dc2366fSVenugopal Iyer default:
7590dc2366fSVenugopal Iyer mutex_exit(&ixgbe->gen_lock);
7600dc2366fSVenugopal Iyer return (ENOTSUP);
7610dc2366fSVenugopal Iyer }
7620dc2366fSVenugopal Iyer
7630dc2366fSVenugopal Iyer mutex_exit(&ixgbe->gen_lock);
7640dc2366fSVenugopal Iyer
7650dc2366fSVenugopal Iyer if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
7660dc2366fSVenugopal Iyer ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
7670dc2366fSVenugopal Iyer return (EIO);
7680dc2366fSVenugopal Iyer }
7690dc2366fSVenugopal Iyer
7700dc2366fSVenugopal Iyer return (0);
7710dc2366fSVenugopal Iyer }
7720dc2366fSVenugopal Iyer
7730dc2366fSVenugopal Iyer /*
7740dc2366fSVenugopal Iyer * Retrieve a value for one of the statistics for a particular rx ring
7750dc2366fSVenugopal Iyer */
7760dc2366fSVenugopal Iyer int
ixgbe_rx_ring_stat(mac_ring_driver_t rh,uint_t stat,uint64_t * val)7770dc2366fSVenugopal Iyer ixgbe_rx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val)
7780dc2366fSVenugopal Iyer {
7790dc2366fSVenugopal Iyer ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)rh;
7800dc2366fSVenugopal Iyer ixgbe_t *ixgbe = rx_ring->ixgbe;
7810dc2366fSVenugopal Iyer
7820dc2366fSVenugopal Iyer if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
7830dc2366fSVenugopal Iyer return (ECANCELED);
7840dc2366fSVenugopal Iyer }
7850dc2366fSVenugopal Iyer
7860dc2366fSVenugopal Iyer switch (stat) {
7870dc2366fSVenugopal Iyer case MAC_STAT_RBYTES:
7880dc2366fSVenugopal Iyer *val = rx_ring->stat_rbytes;
7890dc2366fSVenugopal Iyer break;
7900dc2366fSVenugopal Iyer
7910dc2366fSVenugopal Iyer case MAC_STAT_IPACKETS:
7920dc2366fSVenugopal Iyer *val = rx_ring->stat_ipackets;
7930dc2366fSVenugopal Iyer break;
7940dc2366fSVenugopal Iyer
7950dc2366fSVenugopal Iyer default:
7960dc2366fSVenugopal Iyer *val = 0;
7970dc2366fSVenugopal Iyer return (ENOTSUP);
7980dc2366fSVenugopal Iyer }
7990dc2366fSVenugopal Iyer
8000dc2366fSVenugopal Iyer return (0);
8010dc2366fSVenugopal Iyer }
8020dc2366fSVenugopal Iyer
8030dc2366fSVenugopal Iyer /*
8040dc2366fSVenugopal Iyer * Retrieve a value for one of the statistics for a particular tx ring
8050dc2366fSVenugopal Iyer */
8060dc2366fSVenugopal Iyer int
ixgbe_tx_ring_stat(mac_ring_driver_t rh,uint_t stat,uint64_t * val)8070dc2366fSVenugopal Iyer ixgbe_tx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val)
8080dc2366fSVenugopal Iyer {
8090dc2366fSVenugopal Iyer ixgbe_tx_ring_t *tx_ring = (ixgbe_tx_ring_t *)rh;
8100dc2366fSVenugopal Iyer ixgbe_t *ixgbe = tx_ring->ixgbe;
8110dc2366fSVenugopal Iyer
8120dc2366fSVenugopal Iyer if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
8130dc2366fSVenugopal Iyer return (ECANCELED);
8140dc2366fSVenugopal Iyer }
8150dc2366fSVenugopal Iyer
8160dc2366fSVenugopal Iyer switch (stat) {
8170dc2366fSVenugopal Iyer case MAC_STAT_OBYTES:
8180dc2366fSVenugopal Iyer *val = tx_ring->stat_obytes;
8190dc2366fSVenugopal Iyer break;
8200dc2366fSVenugopal Iyer
8210dc2366fSVenugopal Iyer case MAC_STAT_OPACKETS:
8220dc2366fSVenugopal Iyer *val = tx_ring->stat_opackets;
8230dc2366fSVenugopal Iyer break;
8240dc2366fSVenugopal Iyer
8250dc2366fSVenugopal Iyer default:
8260dc2366fSVenugopal Iyer *val = 0;
8270dc2366fSVenugopal Iyer return (ENOTSUP);
8280dc2366fSVenugopal Iyer }
8290dc2366fSVenugopal Iyer
8300dc2366fSVenugopal Iyer return (0);
8310dc2366fSVenugopal Iyer }
832