1dc0cb1cdSDale Ghent /****************************************************************************** 2*48ed61a7SRobert Mustacchi SPDX-License-Identifier: BSD-3-Clause 3dc0cb1cdSDale Ghent 4*48ed61a7SRobert Mustacchi Copyright (c) 2001-2017, Intel Corporation 5dc0cb1cdSDale Ghent All rights reserved. 6dc0cb1cdSDale Ghent 7dc0cb1cdSDale Ghent Redistribution and use in source and binary forms, with or without 8dc0cb1cdSDale Ghent modification, are permitted provided that the following conditions are met: 9dc0cb1cdSDale Ghent 10dc0cb1cdSDale Ghent 1. Redistributions of source code must retain the above copyright notice, 11dc0cb1cdSDale Ghent this list of conditions and the following disclaimer. 12dc0cb1cdSDale Ghent 13dc0cb1cdSDale Ghent 2. Redistributions in binary form must reproduce the above copyright 14dc0cb1cdSDale Ghent notice, this list of conditions and the following disclaimer in the 15dc0cb1cdSDale Ghent documentation and/or other materials provided with the distribution. 16dc0cb1cdSDale Ghent 17dc0cb1cdSDale Ghent 3. Neither the name of the Intel Corporation nor the names of its 18dc0cb1cdSDale Ghent contributors may be used to endorse or promote products derived from 19dc0cb1cdSDale Ghent this software without specific prior written permission. 20dc0cb1cdSDale Ghent 21dc0cb1cdSDale Ghent THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22dc0cb1cdSDale Ghent AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23dc0cb1cdSDale Ghent IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24dc0cb1cdSDale Ghent ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25dc0cb1cdSDale Ghent LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26dc0cb1cdSDale Ghent CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27dc0cb1cdSDale Ghent SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28dc0cb1cdSDale Ghent INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29dc0cb1cdSDale Ghent CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30dc0cb1cdSDale Ghent ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31dc0cb1cdSDale Ghent POSSIBILITY OF SUCH DAMAGE. 32dc0cb1cdSDale Ghent 33dc0cb1cdSDale Ghent ******************************************************************************/ 34dc0cb1cdSDale Ghent /*$FreeBSD$*/ 35dc0cb1cdSDale Ghent 36dc0cb1cdSDale Ghent #ifndef _IXGBE_DCB_H_ 37dc0cb1cdSDale Ghent #define _IXGBE_DCB_H_ 38dc0cb1cdSDale Ghent 39dc0cb1cdSDale Ghent #include "ixgbe_type.h" 40dc0cb1cdSDale Ghent 41dc0cb1cdSDale Ghent /* DCB defines */ 42dc0cb1cdSDale Ghent /* DCB credit calculation defines */ 43dc0cb1cdSDale Ghent #define IXGBE_DCB_CREDIT_QUANTUM 64 44dc0cb1cdSDale Ghent #define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */ 45dc0cb1cdSDale Ghent #define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/ 46dc0cb1cdSDale Ghent #define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL) 47dc0cb1cdSDale Ghent 48dc0cb1cdSDale Ghent /* 513 for 32KB TSO packet */ 49dc0cb1cdSDale Ghent #define IXGBE_DCB_MIN_TSO_CREDIT \ 50dc0cb1cdSDale Ghent ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1) 51dc0cb1cdSDale Ghent 52dc0cb1cdSDale Ghent /* DCB configuration defines */ 53dc0cb1cdSDale Ghent #define IXGBE_DCB_MAX_USER_PRIORITY 8 54dc0cb1cdSDale Ghent #define IXGBE_DCB_MAX_BW_GROUP 8 55dc0cb1cdSDale Ghent #define IXGBE_DCB_BW_PERCENT 100 56dc0cb1cdSDale Ghent 57dc0cb1cdSDale Ghent #define IXGBE_DCB_TX_CONFIG 0 58dc0cb1cdSDale Ghent #define IXGBE_DCB_RX_CONFIG 1 59dc0cb1cdSDale Ghent 60dc0cb1cdSDale Ghent /* DCB capability defines */ 61dc0cb1cdSDale Ghent #define IXGBE_DCB_PG_SUPPORT 0x00000001 62dc0cb1cdSDale Ghent #define IXGBE_DCB_PFC_SUPPORT 0x00000002 63dc0cb1cdSDale Ghent #define IXGBE_DCB_BCN_SUPPORT 0x00000004 64dc0cb1cdSDale Ghent #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 65dc0cb1cdSDale Ghent #define IXGBE_DCB_GSP_SUPPORT 0x00000010 66dc0cb1cdSDale Ghent 67dc0cb1cdSDale Ghent struct ixgbe_dcb_support { 68dc0cb1cdSDale Ghent u32 capabilities; /* DCB capabilities */ 69dc0cb1cdSDale Ghent 70dc0cb1cdSDale Ghent /* Each bit represents a number of TCs configurable in the hw. 71dc0cb1cdSDale Ghent * If 8 traffic classes can be configured, the value is 0x80. */ 72dc0cb1cdSDale Ghent u8 traffic_classes; 73dc0cb1cdSDale Ghent u8 pfc_traffic_classes; 74dc0cb1cdSDale Ghent }; 75dc0cb1cdSDale Ghent 76dc0cb1cdSDale Ghent enum ixgbe_dcb_tsa { 77dc0cb1cdSDale Ghent ixgbe_dcb_tsa_ets = 0, 78dc0cb1cdSDale Ghent ixgbe_dcb_tsa_group_strict_cee, 79dc0cb1cdSDale Ghent ixgbe_dcb_tsa_strict 80dc0cb1cdSDale Ghent }; 81dc0cb1cdSDale Ghent 82dc0cb1cdSDale Ghent /* Traffic class bandwidth allocation per direction */ 83dc0cb1cdSDale Ghent struct ixgbe_dcb_tc_path { 84dc0cb1cdSDale Ghent u8 bwg_id; /* Bandwidth Group (BWG) ID */ 85dc0cb1cdSDale Ghent u8 bwg_percent; /* % of BWG's bandwidth */ 86dc0cb1cdSDale Ghent u8 link_percent; /* % of link bandwidth */ 87dc0cb1cdSDale Ghent u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ 88dc0cb1cdSDale Ghent u16 data_credits_refill; /* Credit refill amount in 64B granularity */ 89dc0cb1cdSDale Ghent u16 data_credits_max; /* Max credits for a configured packet buffer 90dc0cb1cdSDale Ghent * in 64B granularity.*/ 91dc0cb1cdSDale Ghent enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */ 92dc0cb1cdSDale Ghent }; 93dc0cb1cdSDale Ghent 94dc0cb1cdSDale Ghent enum ixgbe_dcb_pfc { 95dc0cb1cdSDale Ghent ixgbe_dcb_pfc_disabled = 0, 96dc0cb1cdSDale Ghent ixgbe_dcb_pfc_enabled, 97dc0cb1cdSDale Ghent ixgbe_dcb_pfc_enabled_txonly, 98dc0cb1cdSDale Ghent ixgbe_dcb_pfc_enabled_rxonly 99dc0cb1cdSDale Ghent }; 100dc0cb1cdSDale Ghent 101dc0cb1cdSDale Ghent /* Traffic class configuration */ 102dc0cb1cdSDale Ghent struct ixgbe_dcb_tc_config { 103dc0cb1cdSDale Ghent struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */ 104dc0cb1cdSDale Ghent enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */ 105dc0cb1cdSDale Ghent 106dc0cb1cdSDale Ghent u16 desc_credits_max; /* For Tx Descriptor arbitration */ 107dc0cb1cdSDale Ghent u8 tc; /* Traffic class (TC) */ 108dc0cb1cdSDale Ghent }; 109dc0cb1cdSDale Ghent 110dc0cb1cdSDale Ghent enum ixgbe_dcb_pba { 111dc0cb1cdSDale Ghent /* PBA[0-7] each use 64KB FIFO */ 112dc0cb1cdSDale Ghent ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL, 113dc0cb1cdSDale Ghent /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */ 114dc0cb1cdSDale Ghent ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED 115dc0cb1cdSDale Ghent }; 116dc0cb1cdSDale Ghent 117dc0cb1cdSDale Ghent struct ixgbe_dcb_num_tcs { 118dc0cb1cdSDale Ghent u8 pg_tcs; 119dc0cb1cdSDale Ghent u8 pfc_tcs; 120dc0cb1cdSDale Ghent }; 121dc0cb1cdSDale Ghent 122dc0cb1cdSDale Ghent struct ixgbe_dcb_config { 123dc0cb1cdSDale Ghent struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 124dc0cb1cdSDale Ghent struct ixgbe_dcb_support support; 125dc0cb1cdSDale Ghent struct ixgbe_dcb_num_tcs num_tcs; 126dc0cb1cdSDale Ghent u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */ 127dc0cb1cdSDale Ghent bool pfc_mode_enable; 128dc0cb1cdSDale Ghent bool round_robin_enable; 129dc0cb1cdSDale Ghent 130dc0cb1cdSDale Ghent enum ixgbe_dcb_pba rx_pba_cfg; 131dc0cb1cdSDale Ghent 132dc0cb1cdSDale Ghent u32 dcb_cfg_version; /* Not used...OS-specific? */ 133dc0cb1cdSDale Ghent u32 link_speed; /* For bandwidth allocation validation purpose */ 134dc0cb1cdSDale Ghent bool vt_mode; 135dc0cb1cdSDale Ghent }; 136dc0cb1cdSDale Ghent 137dc0cb1cdSDale Ghent /* DCB driver APIs */ 138dc0cb1cdSDale Ghent 139dc0cb1cdSDale Ghent /* DCB rule checking */ 140dc0cb1cdSDale Ghent s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *); 141dc0cb1cdSDale Ghent 142dc0cb1cdSDale Ghent /* DCB credits calculation */ 143dc0cb1cdSDale Ghent s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int); 144dc0cb1cdSDale Ghent s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *, 145dc0cb1cdSDale Ghent struct ixgbe_dcb_config *, u32, u8); 146dc0cb1cdSDale Ghent 147dc0cb1cdSDale Ghent /* DCB PFC */ 148dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *); 149dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 150dc0cb1cdSDale Ghent 151dc0cb1cdSDale Ghent /* DCB stats */ 152dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *); 153dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 154dc0cb1cdSDale Ghent s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 155dc0cb1cdSDale Ghent 156dc0cb1cdSDale Ghent /* DCB config arbiters */ 157dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *, 158dc0cb1cdSDale Ghent struct ixgbe_dcb_config *); 159dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *, 160dc0cb1cdSDale Ghent struct ixgbe_dcb_config *); 161dc0cb1cdSDale Ghent s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *, 162dc0cb1cdSDale Ghent struct ixgbe_dcb_config *); 163dc0cb1cdSDale Ghent 164dc0cb1cdSDale Ghent /* DCB unpack routines */ 165dc0cb1cdSDale Ghent void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *); 166dc0cb1cdSDale Ghent void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *); 167dc0cb1cdSDale Ghent void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *); 168dc0cb1cdSDale Ghent void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *); 169dc0cb1cdSDale Ghent void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *); 170dc0cb1cdSDale Ghent void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *); 171dc0cb1cdSDale Ghent u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8); 172dc0cb1cdSDale Ghent 173dc0cb1cdSDale Ghent /* DCB initialization */ 174dc0cb1cdSDale Ghent s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *); 175dc0cb1cdSDale Ghent s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 176dc0cb1cdSDale Ghent #endif /* _IXGBE_DCB_H_ */ 177