1*5fc77b81SRobert Mustacchi /****************************************************************************** 2*5fc77b81SRobert Mustacchi 3*5fc77b81SRobert Mustacchi Copyright (c) 2001-2012, Intel Corporation 4*5fc77b81SRobert Mustacchi All rights reserved. 5*5fc77b81SRobert Mustacchi 6*5fc77b81SRobert Mustacchi Redistribution and use in source and binary forms, with or without 7*5fc77b81SRobert Mustacchi modification, are permitted provided that the following conditions are met: 8*5fc77b81SRobert Mustacchi 9*5fc77b81SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 10*5fc77b81SRobert Mustacchi this list of conditions and the following disclaimer. 11*5fc77b81SRobert Mustacchi 12*5fc77b81SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 13*5fc77b81SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 14*5fc77b81SRobert Mustacchi documentation and/or other materials provided with the distribution. 15*5fc77b81SRobert Mustacchi 16*5fc77b81SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 17*5fc77b81SRobert Mustacchi contributors may be used to endorse or promote products derived from 18*5fc77b81SRobert Mustacchi this software without specific prior written permission. 19*5fc77b81SRobert Mustacchi 20*5fc77b81SRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21*5fc77b81SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22*5fc77b81SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23*5fc77b81SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24*5fc77b81SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25*5fc77b81SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26*5fc77b81SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27*5fc77b81SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28*5fc77b81SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29*5fc77b81SRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30*5fc77b81SRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 31*5fc77b81SRobert Mustacchi 32*5fc77b81SRobert Mustacchi ******************************************************************************/ 33*5fc77b81SRobert Mustacchi /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.14 2012/07/05 20:51:44 jfv Exp $*/ 34*5fc77b81SRobert Mustacchi 35*5fc77b81SRobert Mustacchi #include "ixgbe_common.h" 36*5fc77b81SRobert Mustacchi #include "ixgbe_phy.h" 37*5fc77b81SRobert Mustacchi #include "ixgbe_api.h" 38*5fc77b81SRobert Mustacchi 39*5fc77b81SRobert Mustacchi static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 40*5fc77b81SRobert Mustacchi static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 41*5fc77b81SRobert Mustacchi static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 42*5fc77b81SRobert Mustacchi static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 43*5fc77b81SRobert Mustacchi static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 44*5fc77b81SRobert Mustacchi static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 45*5fc77b81SRobert Mustacchi u16 count); 46*5fc77b81SRobert Mustacchi static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 47*5fc77b81SRobert Mustacchi static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48*5fc77b81SRobert Mustacchi static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 49*5fc77b81SRobert Mustacchi static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 50*5fc77b81SRobert Mustacchi 51*5fc77b81SRobert Mustacchi static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 52*5fc77b81SRobert Mustacchi static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 53*5fc77b81SRobert Mustacchi u16 *san_mac_offset); 54*5fc77b81SRobert Mustacchi static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 55*5fc77b81SRobert Mustacchi u16 words, u16 *data); 56*5fc77b81SRobert Mustacchi static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 57*5fc77b81SRobert Mustacchi u16 words, u16 *data); 58*5fc77b81SRobert Mustacchi static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 59*5fc77b81SRobert Mustacchi u16 offset); 60*5fc77b81SRobert Mustacchi 61*5fc77b81SRobert Mustacchi /** 62*5fc77b81SRobert Mustacchi * ixgbe_init_ops_generic - Inits function ptrs 63*5fc77b81SRobert Mustacchi * @hw: pointer to the hardware structure 64*5fc77b81SRobert Mustacchi * 65*5fc77b81SRobert Mustacchi * Initialize the function pointers. 66*5fc77b81SRobert Mustacchi **/ 67*5fc77b81SRobert Mustacchi s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 68*5fc77b81SRobert Mustacchi { 69*5fc77b81SRobert Mustacchi struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 70*5fc77b81SRobert Mustacchi struct ixgbe_mac_info *mac = &hw->mac; 71*5fc77b81SRobert Mustacchi u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 72*5fc77b81SRobert Mustacchi 73*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_init_ops_generic"); 74*5fc77b81SRobert Mustacchi 75*5fc77b81SRobert Mustacchi /* EEPROM */ 76*5fc77b81SRobert Mustacchi eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 77*5fc77b81SRobert Mustacchi /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 78*5fc77b81SRobert Mustacchi if (eec & IXGBE_EEC_PRES) { 79*5fc77b81SRobert Mustacchi eeprom->ops.read = &ixgbe_read_eerd_generic; 80*5fc77b81SRobert Mustacchi eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic; 81*5fc77b81SRobert Mustacchi } else { 82*5fc77b81SRobert Mustacchi eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 83*5fc77b81SRobert Mustacchi eeprom->ops.read_buffer = 84*5fc77b81SRobert Mustacchi &ixgbe_read_eeprom_buffer_bit_bang_generic; 85*5fc77b81SRobert Mustacchi } 86*5fc77b81SRobert Mustacchi eeprom->ops.write = &ixgbe_write_eeprom_generic; 87*5fc77b81SRobert Mustacchi eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic; 88*5fc77b81SRobert Mustacchi eeprom->ops.validate_checksum = 89*5fc77b81SRobert Mustacchi &ixgbe_validate_eeprom_checksum_generic; 90*5fc77b81SRobert Mustacchi eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 91*5fc77b81SRobert Mustacchi eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic; 92*5fc77b81SRobert Mustacchi 93*5fc77b81SRobert Mustacchi /* MAC */ 94*5fc77b81SRobert Mustacchi mac->ops.init_hw = &ixgbe_init_hw_generic; 95*5fc77b81SRobert Mustacchi mac->ops.reset_hw = NULL; 96*5fc77b81SRobert Mustacchi mac->ops.start_hw = &ixgbe_start_hw_generic; 97*5fc77b81SRobert Mustacchi mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 98*5fc77b81SRobert Mustacchi mac->ops.get_media_type = NULL; 99*5fc77b81SRobert Mustacchi mac->ops.get_supported_physical_layer = NULL; 100*5fc77b81SRobert Mustacchi mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 101*5fc77b81SRobert Mustacchi mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 102*5fc77b81SRobert Mustacchi mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 103*5fc77b81SRobert Mustacchi mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 104*5fc77b81SRobert Mustacchi mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 105*5fc77b81SRobert Mustacchi mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; 106*5fc77b81SRobert Mustacchi mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; 107*5fc77b81SRobert Mustacchi 108*5fc77b81SRobert Mustacchi /* LEDs */ 109*5fc77b81SRobert Mustacchi mac->ops.led_on = &ixgbe_led_on_generic; 110*5fc77b81SRobert Mustacchi mac->ops.led_off = &ixgbe_led_off_generic; 111*5fc77b81SRobert Mustacchi mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 112*5fc77b81SRobert Mustacchi mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 113*5fc77b81SRobert Mustacchi 114*5fc77b81SRobert Mustacchi /* RAR, Multicast, VLAN */ 115*5fc77b81SRobert Mustacchi mac->ops.set_rar = &ixgbe_set_rar_generic; 116*5fc77b81SRobert Mustacchi mac->ops.clear_rar = &ixgbe_clear_rar_generic; 117*5fc77b81SRobert Mustacchi mac->ops.insert_mac_addr = NULL; 118*5fc77b81SRobert Mustacchi mac->ops.set_vmdq = NULL; 119*5fc77b81SRobert Mustacchi mac->ops.clear_vmdq = NULL; 120*5fc77b81SRobert Mustacchi mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 121*5fc77b81SRobert Mustacchi mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 122*5fc77b81SRobert Mustacchi mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 123*5fc77b81SRobert Mustacchi mac->ops.enable_mc = &ixgbe_enable_mc_generic; 124*5fc77b81SRobert Mustacchi mac->ops.disable_mc = &ixgbe_disable_mc_generic; 125*5fc77b81SRobert Mustacchi mac->ops.clear_vfta = NULL; 126*5fc77b81SRobert Mustacchi mac->ops.set_vfta = NULL; 127*5fc77b81SRobert Mustacchi mac->ops.set_vlvf = NULL; 128*5fc77b81SRobert Mustacchi mac->ops.init_uta_tables = NULL; 129*5fc77b81SRobert Mustacchi 130*5fc77b81SRobert Mustacchi /* Flow Control */ 131*5fc77b81SRobert Mustacchi mac->ops.fc_enable = &ixgbe_fc_enable_generic; 132*5fc77b81SRobert Mustacchi 133*5fc77b81SRobert Mustacchi /* Link */ 134*5fc77b81SRobert Mustacchi mac->ops.get_link_capabilities = NULL; 135*5fc77b81SRobert Mustacchi mac->ops.setup_link = NULL; 136*5fc77b81SRobert Mustacchi mac->ops.check_link = NULL; 137*5fc77b81SRobert Mustacchi 138*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 139*5fc77b81SRobert Mustacchi } 140*5fc77b81SRobert Mustacchi 141*5fc77b81SRobert Mustacchi /** 142*5fc77b81SRobert Mustacchi * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow 143*5fc77b81SRobert Mustacchi * control 144*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 145*5fc77b81SRobert Mustacchi * 146*5fc77b81SRobert Mustacchi * There are several phys that do not support autoneg flow control. This 147*5fc77b81SRobert Mustacchi * function check the device id to see if the associated phy supports 148*5fc77b81SRobert Mustacchi * autoneg flow control. 149*5fc77b81SRobert Mustacchi **/ 150*5fc77b81SRobert Mustacchi static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 151*5fc77b81SRobert Mustacchi { 152*5fc77b81SRobert Mustacchi 153*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 154*5fc77b81SRobert Mustacchi 155*5fc77b81SRobert Mustacchi switch (hw->device_id) { 156*5fc77b81SRobert Mustacchi case IXGBE_DEV_ID_X540T: 157*5fc77b81SRobert Mustacchi case IXGBE_DEV_ID_X540T1: 158*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 159*5fc77b81SRobert Mustacchi case IXGBE_DEV_ID_82599_T3_LOM: 160*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 161*5fc77b81SRobert Mustacchi default: 162*5fc77b81SRobert Mustacchi return IXGBE_ERR_FC_NOT_SUPPORTED; 163*5fc77b81SRobert Mustacchi } 164*5fc77b81SRobert Mustacchi } 165*5fc77b81SRobert Mustacchi 166*5fc77b81SRobert Mustacchi /** 167*5fc77b81SRobert Mustacchi * ixgbe_setup_fc - Set up flow control 168*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 169*5fc77b81SRobert Mustacchi * 170*5fc77b81SRobert Mustacchi * Called at init time to set up flow control. 171*5fc77b81SRobert Mustacchi **/ 172*5fc77b81SRobert Mustacchi static s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 173*5fc77b81SRobert Mustacchi { 174*5fc77b81SRobert Mustacchi s32 ret_val = IXGBE_SUCCESS; 175*5fc77b81SRobert Mustacchi u32 reg = 0, reg_bp = 0; 176*5fc77b81SRobert Mustacchi u16 reg_cu = 0; 177*5fc77b81SRobert Mustacchi 178*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_setup_fc"); 179*5fc77b81SRobert Mustacchi 180*5fc77b81SRobert Mustacchi /* 181*5fc77b81SRobert Mustacchi * Validate the requested mode. Strict IEEE mode does not allow 182*5fc77b81SRobert Mustacchi * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 183*5fc77b81SRobert Mustacchi */ 184*5fc77b81SRobert Mustacchi if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 185*5fc77b81SRobert Mustacchi DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 186*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 187*5fc77b81SRobert Mustacchi goto out; 188*5fc77b81SRobert Mustacchi } 189*5fc77b81SRobert Mustacchi 190*5fc77b81SRobert Mustacchi /* 191*5fc77b81SRobert Mustacchi * 10gig parts do not have a word in the EEPROM to determine the 192*5fc77b81SRobert Mustacchi * default flow control setting, so we explicitly set it to full. 193*5fc77b81SRobert Mustacchi */ 194*5fc77b81SRobert Mustacchi if (hw->fc.requested_mode == ixgbe_fc_default) 195*5fc77b81SRobert Mustacchi hw->fc.requested_mode = ixgbe_fc_full; 196*5fc77b81SRobert Mustacchi 197*5fc77b81SRobert Mustacchi /* 198*5fc77b81SRobert Mustacchi * Set up the 1G and 10G flow control advertisement registers so the 199*5fc77b81SRobert Mustacchi * HW will be able to do fc autoneg once the cable is plugged in. If 200*5fc77b81SRobert Mustacchi * we link at 10G, the 1G advertisement is harmless and vice versa. 201*5fc77b81SRobert Mustacchi */ 202*5fc77b81SRobert Mustacchi switch (hw->phy.media_type) { 203*5fc77b81SRobert Mustacchi case ixgbe_media_type_fiber: 204*5fc77b81SRobert Mustacchi case ixgbe_media_type_backplane: 205*5fc77b81SRobert Mustacchi reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 206*5fc77b81SRobert Mustacchi reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC); 207*5fc77b81SRobert Mustacchi break; 208*5fc77b81SRobert Mustacchi case ixgbe_media_type_copper: 209*5fc77b81SRobert Mustacchi hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 210*5fc77b81SRobert Mustacchi IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 211*5fc77b81SRobert Mustacchi break; 212*5fc77b81SRobert Mustacchi default: 213*5fc77b81SRobert Mustacchi break; 214*5fc77b81SRobert Mustacchi } 215*5fc77b81SRobert Mustacchi 216*5fc77b81SRobert Mustacchi /* 217*5fc77b81SRobert Mustacchi * The possible values of fc.requested_mode are: 218*5fc77b81SRobert Mustacchi * 0: Flow control is completely disabled 219*5fc77b81SRobert Mustacchi * 1: Rx flow control is enabled (we can receive pause frames, 220*5fc77b81SRobert Mustacchi * but not send pause frames). 221*5fc77b81SRobert Mustacchi * 2: Tx flow control is enabled (we can send pause frames but 222*5fc77b81SRobert Mustacchi * we do not support receiving pause frames). 223*5fc77b81SRobert Mustacchi * 3: Both Rx and Tx flow control (symmetric) are enabled. 224*5fc77b81SRobert Mustacchi * other: Invalid. 225*5fc77b81SRobert Mustacchi */ 226*5fc77b81SRobert Mustacchi switch (hw->fc.requested_mode) { 227*5fc77b81SRobert Mustacchi case ixgbe_fc_none: 228*5fc77b81SRobert Mustacchi /* Flow control completely disabled by software override. */ 229*5fc77b81SRobert Mustacchi reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 230*5fc77b81SRobert Mustacchi if (hw->phy.media_type == ixgbe_media_type_backplane) 231*5fc77b81SRobert Mustacchi reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 232*5fc77b81SRobert Mustacchi IXGBE_AUTOC_ASM_PAUSE); 233*5fc77b81SRobert Mustacchi else if (hw->phy.media_type == ixgbe_media_type_copper) 234*5fc77b81SRobert Mustacchi reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 235*5fc77b81SRobert Mustacchi break; 236*5fc77b81SRobert Mustacchi case ixgbe_fc_tx_pause: 237*5fc77b81SRobert Mustacchi /* 238*5fc77b81SRobert Mustacchi * Tx Flow control is enabled, and Rx Flow control is 239*5fc77b81SRobert Mustacchi * disabled by software override. 240*5fc77b81SRobert Mustacchi */ 241*5fc77b81SRobert Mustacchi reg |= IXGBE_PCS1GANA_ASM_PAUSE; 242*5fc77b81SRobert Mustacchi reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 243*5fc77b81SRobert Mustacchi if (hw->phy.media_type == ixgbe_media_type_backplane) { 244*5fc77b81SRobert Mustacchi reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 245*5fc77b81SRobert Mustacchi reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 246*5fc77b81SRobert Mustacchi } else if (hw->phy.media_type == ixgbe_media_type_copper) { 247*5fc77b81SRobert Mustacchi reg_cu |= IXGBE_TAF_ASM_PAUSE; 248*5fc77b81SRobert Mustacchi reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 249*5fc77b81SRobert Mustacchi } 250*5fc77b81SRobert Mustacchi break; 251*5fc77b81SRobert Mustacchi case ixgbe_fc_rx_pause: 252*5fc77b81SRobert Mustacchi /* 253*5fc77b81SRobert Mustacchi * Rx Flow control is enabled and Tx Flow control is 254*5fc77b81SRobert Mustacchi * disabled by software override. Since there really 255*5fc77b81SRobert Mustacchi * isn't a way to advertise that we are capable of RX 256*5fc77b81SRobert Mustacchi * Pause ONLY, we will advertise that we support both 257*5fc77b81SRobert Mustacchi * symmetric and asymmetric Rx PAUSE, as such we fall 258*5fc77b81SRobert Mustacchi * through to the fc_full statement. Later, we will 259*5fc77b81SRobert Mustacchi * disable the adapter's ability to send PAUSE frames. 260*5fc77b81SRobert Mustacchi */ 261*5fc77b81SRobert Mustacchi case ixgbe_fc_full: 262*5fc77b81SRobert Mustacchi /* Flow control (both Rx and Tx) is enabled by SW override. */ 263*5fc77b81SRobert Mustacchi reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 264*5fc77b81SRobert Mustacchi if (hw->phy.media_type == ixgbe_media_type_backplane) 265*5fc77b81SRobert Mustacchi reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 266*5fc77b81SRobert Mustacchi IXGBE_AUTOC_ASM_PAUSE; 267*5fc77b81SRobert Mustacchi else if (hw->phy.media_type == ixgbe_media_type_copper) 268*5fc77b81SRobert Mustacchi reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 269*5fc77b81SRobert Mustacchi break; 270*5fc77b81SRobert Mustacchi default: 271*5fc77b81SRobert Mustacchi DEBUGOUT("Flow control param set incorrectly\n"); 272*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_CONFIG; 273*5fc77b81SRobert Mustacchi goto out; 274*5fc77b81SRobert Mustacchi } 275*5fc77b81SRobert Mustacchi 276*5fc77b81SRobert Mustacchi if (hw->mac.type != ixgbe_mac_X540) { 277*5fc77b81SRobert Mustacchi /* 278*5fc77b81SRobert Mustacchi * Enable auto-negotiation between the MAC & PHY; 279*5fc77b81SRobert Mustacchi * the MAC will advertise clause 37 flow control. 280*5fc77b81SRobert Mustacchi */ 281*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 282*5fc77b81SRobert Mustacchi reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 283*5fc77b81SRobert Mustacchi 284*5fc77b81SRobert Mustacchi /* Disable AN timeout */ 285*5fc77b81SRobert Mustacchi if (hw->fc.strict_ieee) 286*5fc77b81SRobert Mustacchi reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 287*5fc77b81SRobert Mustacchi 288*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 289*5fc77b81SRobert Mustacchi DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 290*5fc77b81SRobert Mustacchi } 291*5fc77b81SRobert Mustacchi 292*5fc77b81SRobert Mustacchi /* 293*5fc77b81SRobert Mustacchi * AUTOC restart handles negotiation of 1G and 10G on backplane 294*5fc77b81SRobert Mustacchi * and copper. There is no need to set the PCS1GCTL register. 295*5fc77b81SRobert Mustacchi * 296*5fc77b81SRobert Mustacchi */ 297*5fc77b81SRobert Mustacchi if (hw->phy.media_type == ixgbe_media_type_backplane) { 298*5fc77b81SRobert Mustacchi reg_bp |= IXGBE_AUTOC_AN_RESTART; 299*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp); 300*5fc77b81SRobert Mustacchi } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 301*5fc77b81SRobert Mustacchi (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) { 302*5fc77b81SRobert Mustacchi hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 303*5fc77b81SRobert Mustacchi IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 304*5fc77b81SRobert Mustacchi } 305*5fc77b81SRobert Mustacchi 306*5fc77b81SRobert Mustacchi DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 307*5fc77b81SRobert Mustacchi out: 308*5fc77b81SRobert Mustacchi return ret_val; 309*5fc77b81SRobert Mustacchi } 310*5fc77b81SRobert Mustacchi 311*5fc77b81SRobert Mustacchi /** 312*5fc77b81SRobert Mustacchi * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 313*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 314*5fc77b81SRobert Mustacchi * 315*5fc77b81SRobert Mustacchi * Starts the hardware by filling the bus info structure and media type, clears 316*5fc77b81SRobert Mustacchi * all on chip counters, initializes receive address registers, multicast 317*5fc77b81SRobert Mustacchi * table, VLAN filter table, calls routine to set up link and flow control 318*5fc77b81SRobert Mustacchi * settings, and leaves transmit and receive units disabled and uninitialized 319*5fc77b81SRobert Mustacchi **/ 320*5fc77b81SRobert Mustacchi s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 321*5fc77b81SRobert Mustacchi { 322*5fc77b81SRobert Mustacchi s32 ret_val; 323*5fc77b81SRobert Mustacchi u32 ctrl_ext; 324*5fc77b81SRobert Mustacchi 325*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_start_hw_generic"); 326*5fc77b81SRobert Mustacchi 327*5fc77b81SRobert Mustacchi /* Set the media type */ 328*5fc77b81SRobert Mustacchi hw->phy.media_type = hw->mac.ops.get_media_type(hw); 329*5fc77b81SRobert Mustacchi 330*5fc77b81SRobert Mustacchi /* PHY ops initialization must be done in reset_hw() */ 331*5fc77b81SRobert Mustacchi 332*5fc77b81SRobert Mustacchi /* Clear the VLAN filter table */ 333*5fc77b81SRobert Mustacchi hw->mac.ops.clear_vfta(hw); 334*5fc77b81SRobert Mustacchi 335*5fc77b81SRobert Mustacchi /* Clear statistics registers */ 336*5fc77b81SRobert Mustacchi hw->mac.ops.clear_hw_cntrs(hw); 337*5fc77b81SRobert Mustacchi 338*5fc77b81SRobert Mustacchi /* Set No Snoop Disable */ 339*5fc77b81SRobert Mustacchi ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 340*5fc77b81SRobert Mustacchi ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 341*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 342*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 343*5fc77b81SRobert Mustacchi 344*5fc77b81SRobert Mustacchi /* Setup flow control */ 345*5fc77b81SRobert Mustacchi ret_val = ixgbe_setup_fc(hw); 346*5fc77b81SRobert Mustacchi if (ret_val != IXGBE_SUCCESS) 347*5fc77b81SRobert Mustacchi goto out; 348*5fc77b81SRobert Mustacchi 349*5fc77b81SRobert Mustacchi /* Clear adapter stopped flag */ 350*5fc77b81SRobert Mustacchi hw->adapter_stopped = FALSE; 351*5fc77b81SRobert Mustacchi 352*5fc77b81SRobert Mustacchi out: 353*5fc77b81SRobert Mustacchi return ret_val; 354*5fc77b81SRobert Mustacchi } 355*5fc77b81SRobert Mustacchi 356*5fc77b81SRobert Mustacchi /** 357*5fc77b81SRobert Mustacchi * ixgbe_start_hw_gen2 - Init sequence for common device family 358*5fc77b81SRobert Mustacchi * @hw: pointer to hw structure 359*5fc77b81SRobert Mustacchi * 360*5fc77b81SRobert Mustacchi * Performs the init sequence common to the second generation 361*5fc77b81SRobert Mustacchi * of 10 GbE devices. 362*5fc77b81SRobert Mustacchi * Devices in the second generation: 363*5fc77b81SRobert Mustacchi * 82599 364*5fc77b81SRobert Mustacchi * X540 365*5fc77b81SRobert Mustacchi **/ 366*5fc77b81SRobert Mustacchi s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 367*5fc77b81SRobert Mustacchi { 368*5fc77b81SRobert Mustacchi u32 i; 369*5fc77b81SRobert Mustacchi u32 regval; 370*5fc77b81SRobert Mustacchi 371*5fc77b81SRobert Mustacchi /* Clear the rate limiters */ 372*5fc77b81SRobert Mustacchi for (i = 0; i < hw->mac.max_tx_queues; i++) { 373*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 374*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 375*5fc77b81SRobert Mustacchi } 376*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 377*5fc77b81SRobert Mustacchi 378*5fc77b81SRobert Mustacchi /* Disable relaxed ordering */ 379*5fc77b81SRobert Mustacchi for (i = 0; i < hw->mac.max_tx_queues; i++) { 380*5fc77b81SRobert Mustacchi regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 381*5fc77b81SRobert Mustacchi regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 382*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 383*5fc77b81SRobert Mustacchi } 384*5fc77b81SRobert Mustacchi 385*5fc77b81SRobert Mustacchi for (i = 0; i < hw->mac.max_rx_queues; i++) { 386*5fc77b81SRobert Mustacchi regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 387*5fc77b81SRobert Mustacchi regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 388*5fc77b81SRobert Mustacchi IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 389*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 390*5fc77b81SRobert Mustacchi } 391*5fc77b81SRobert Mustacchi 392*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 393*5fc77b81SRobert Mustacchi } 394*5fc77b81SRobert Mustacchi 395*5fc77b81SRobert Mustacchi /** 396*5fc77b81SRobert Mustacchi * ixgbe_init_hw_generic - Generic hardware initialization 397*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 398*5fc77b81SRobert Mustacchi * 399*5fc77b81SRobert Mustacchi * Initialize the hardware by resetting the hardware, filling the bus info 400*5fc77b81SRobert Mustacchi * structure and media type, clears all on chip counters, initializes receive 401*5fc77b81SRobert Mustacchi * address registers, multicast table, VLAN filter table, calls routine to set 402*5fc77b81SRobert Mustacchi * up link and flow control settings, and leaves transmit and receive units 403*5fc77b81SRobert Mustacchi * disabled and uninitialized 404*5fc77b81SRobert Mustacchi **/ 405*5fc77b81SRobert Mustacchi s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 406*5fc77b81SRobert Mustacchi { 407*5fc77b81SRobert Mustacchi s32 status; 408*5fc77b81SRobert Mustacchi 409*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_init_hw_generic"); 410*5fc77b81SRobert Mustacchi 411*5fc77b81SRobert Mustacchi /* Reset the hardware */ 412*5fc77b81SRobert Mustacchi status = hw->mac.ops.reset_hw(hw); 413*5fc77b81SRobert Mustacchi 414*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 415*5fc77b81SRobert Mustacchi /* Start the HW */ 416*5fc77b81SRobert Mustacchi status = hw->mac.ops.start_hw(hw); 417*5fc77b81SRobert Mustacchi } 418*5fc77b81SRobert Mustacchi 419*5fc77b81SRobert Mustacchi return status; 420*5fc77b81SRobert Mustacchi } 421*5fc77b81SRobert Mustacchi 422*5fc77b81SRobert Mustacchi /** 423*5fc77b81SRobert Mustacchi * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 424*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 425*5fc77b81SRobert Mustacchi * 426*5fc77b81SRobert Mustacchi * Clears all hardware statistics counters by reading them from the hardware 427*5fc77b81SRobert Mustacchi * Statistics counters are clear on read. 428*5fc77b81SRobert Mustacchi **/ 429*5fc77b81SRobert Mustacchi s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 430*5fc77b81SRobert Mustacchi { 431*5fc77b81SRobert Mustacchi u16 i = 0; 432*5fc77b81SRobert Mustacchi 433*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 434*5fc77b81SRobert Mustacchi 435*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS); 436*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC); 437*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_ERRBC); 438*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_MSPDC); 439*5fc77b81SRobert Mustacchi for (i = 0; i < 8; i++) 440*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_MPC(i)); 441*5fc77b81SRobert Mustacchi 442*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_MLFC); 443*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_MRFC); 444*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_RLEC); 445*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC); 446*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 447*5fc77b81SRobert Mustacchi if (hw->mac.type >= ixgbe_mac_82599EB) { 448*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 449*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 450*5fc77b81SRobert Mustacchi } else { 451*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC); 452*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 453*5fc77b81SRobert Mustacchi } 454*5fc77b81SRobert Mustacchi 455*5fc77b81SRobert Mustacchi for (i = 0; i < 8; i++) { 456*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 457*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 458*5fc77b81SRobert Mustacchi if (hw->mac.type >= ixgbe_mac_82599EB) { 459*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 460*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 461*5fc77b81SRobert Mustacchi } else { 462*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 463*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 464*5fc77b81SRobert Mustacchi } 465*5fc77b81SRobert Mustacchi } 466*5fc77b81SRobert Mustacchi if (hw->mac.type >= ixgbe_mac_82599EB) 467*5fc77b81SRobert Mustacchi for (i = 0; i < 8; i++) 468*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 469*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PRC64); 470*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PRC127); 471*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PRC255); 472*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PRC511); 473*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PRC1023); 474*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PRC1522); 475*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_GPRC); 476*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_BPRC); 477*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_MPRC); 478*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_GPTC); 479*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_GORCL); 480*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_GORCH); 481*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_GOTCL); 482*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_GOTCH); 483*5fc77b81SRobert Mustacchi if (hw->mac.type == ixgbe_mac_82598EB) 484*5fc77b81SRobert Mustacchi for (i = 0; i < 8; i++) 485*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 486*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_RUC); 487*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_RFC); 488*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_ROC); 489*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_RJC); 490*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC); 491*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC); 492*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC); 493*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_TORL); 494*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_TORH); 495*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_TPR); 496*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_TPT); 497*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PTC64); 498*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PTC127); 499*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PTC255); 500*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PTC511); 501*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PTC1023); 502*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_PTC1522); 503*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_MPTC); 504*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_BPTC); 505*5fc77b81SRobert Mustacchi for (i = 0; i < 16; i++) { 506*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 507*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 508*5fc77b81SRobert Mustacchi if (hw->mac.type >= ixgbe_mac_82599EB) { 509*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 510*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 511*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 512*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 513*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 514*5fc77b81SRobert Mustacchi } else { 515*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 516*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 517*5fc77b81SRobert Mustacchi } 518*5fc77b81SRobert Mustacchi } 519*5fc77b81SRobert Mustacchi 520*5fc77b81SRobert Mustacchi if (hw->mac.type == ixgbe_mac_X540) { 521*5fc77b81SRobert Mustacchi if (hw->phy.id == 0) 522*5fc77b81SRobert Mustacchi (void) ixgbe_identify_phy(hw); 523*5fc77b81SRobert Mustacchi hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 524*5fc77b81SRobert Mustacchi IXGBE_MDIO_PCS_DEV_TYPE, &i); 525*5fc77b81SRobert Mustacchi hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 526*5fc77b81SRobert Mustacchi IXGBE_MDIO_PCS_DEV_TYPE, &i); 527*5fc77b81SRobert Mustacchi hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 528*5fc77b81SRobert Mustacchi IXGBE_MDIO_PCS_DEV_TYPE, &i); 529*5fc77b81SRobert Mustacchi hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 530*5fc77b81SRobert Mustacchi IXGBE_MDIO_PCS_DEV_TYPE, &i); 531*5fc77b81SRobert Mustacchi } 532*5fc77b81SRobert Mustacchi 533*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 534*5fc77b81SRobert Mustacchi } 535*5fc77b81SRobert Mustacchi 536*5fc77b81SRobert Mustacchi /** 537*5fc77b81SRobert Mustacchi * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 538*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 539*5fc77b81SRobert Mustacchi * @pba_num: stores the part number string from the EEPROM 540*5fc77b81SRobert Mustacchi * @pba_num_size: part number string buffer length 541*5fc77b81SRobert Mustacchi * 542*5fc77b81SRobert Mustacchi * Reads the part number string from the EEPROM. 543*5fc77b81SRobert Mustacchi **/ 544*5fc77b81SRobert Mustacchi s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 545*5fc77b81SRobert Mustacchi u32 pba_num_size) 546*5fc77b81SRobert Mustacchi { 547*5fc77b81SRobert Mustacchi s32 ret_val; 548*5fc77b81SRobert Mustacchi u16 data; 549*5fc77b81SRobert Mustacchi u16 pba_ptr; 550*5fc77b81SRobert Mustacchi u16 offset; 551*5fc77b81SRobert Mustacchi u16 length; 552*5fc77b81SRobert Mustacchi 553*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_read_pba_string_generic"); 554*5fc77b81SRobert Mustacchi 555*5fc77b81SRobert Mustacchi if (pba_num == NULL) { 556*5fc77b81SRobert Mustacchi DEBUGOUT("PBA string buffer was null\n"); 557*5fc77b81SRobert Mustacchi return IXGBE_ERR_INVALID_ARGUMENT; 558*5fc77b81SRobert Mustacchi } 559*5fc77b81SRobert Mustacchi 560*5fc77b81SRobert Mustacchi ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 561*5fc77b81SRobert Mustacchi if (ret_val) { 562*5fc77b81SRobert Mustacchi DEBUGOUT("NVM Read Error\n"); 563*5fc77b81SRobert Mustacchi return ret_val; 564*5fc77b81SRobert Mustacchi } 565*5fc77b81SRobert Mustacchi 566*5fc77b81SRobert Mustacchi ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 567*5fc77b81SRobert Mustacchi if (ret_val) { 568*5fc77b81SRobert Mustacchi DEBUGOUT("NVM Read Error\n"); 569*5fc77b81SRobert Mustacchi return ret_val; 570*5fc77b81SRobert Mustacchi } 571*5fc77b81SRobert Mustacchi 572*5fc77b81SRobert Mustacchi /* 573*5fc77b81SRobert Mustacchi * if data is not ptr guard the PBA must be in legacy format which 574*5fc77b81SRobert Mustacchi * means pba_ptr is actually our second data word for the PBA number 575*5fc77b81SRobert Mustacchi * and we can decode it into an ascii string 576*5fc77b81SRobert Mustacchi */ 577*5fc77b81SRobert Mustacchi if (data != IXGBE_PBANUM_PTR_GUARD) { 578*5fc77b81SRobert Mustacchi DEBUGOUT("NVM PBA number is not stored as string\n"); 579*5fc77b81SRobert Mustacchi 580*5fc77b81SRobert Mustacchi /* we will need 11 characters to store the PBA */ 581*5fc77b81SRobert Mustacchi if (pba_num_size < 11) { 582*5fc77b81SRobert Mustacchi DEBUGOUT("PBA string buffer too small\n"); 583*5fc77b81SRobert Mustacchi return IXGBE_ERR_NO_SPACE; 584*5fc77b81SRobert Mustacchi } 585*5fc77b81SRobert Mustacchi 586*5fc77b81SRobert Mustacchi /* extract hex string from data and pba_ptr */ 587*5fc77b81SRobert Mustacchi pba_num[0] = (data >> 12) & 0xF; 588*5fc77b81SRobert Mustacchi pba_num[1] = (data >> 8) & 0xF; 589*5fc77b81SRobert Mustacchi pba_num[2] = (data >> 4) & 0xF; 590*5fc77b81SRobert Mustacchi pba_num[3] = data & 0xF; 591*5fc77b81SRobert Mustacchi pba_num[4] = (pba_ptr >> 12) & 0xF; 592*5fc77b81SRobert Mustacchi pba_num[5] = (pba_ptr >> 8) & 0xF; 593*5fc77b81SRobert Mustacchi pba_num[6] = '-'; 594*5fc77b81SRobert Mustacchi pba_num[7] = 0; 595*5fc77b81SRobert Mustacchi pba_num[8] = (pba_ptr >> 4) & 0xF; 596*5fc77b81SRobert Mustacchi pba_num[9] = pba_ptr & 0xF; 597*5fc77b81SRobert Mustacchi 598*5fc77b81SRobert Mustacchi /* put a null character on the end of our string */ 599*5fc77b81SRobert Mustacchi pba_num[10] = '\0'; 600*5fc77b81SRobert Mustacchi 601*5fc77b81SRobert Mustacchi /* switch all the data but the '-' to hex char */ 602*5fc77b81SRobert Mustacchi for (offset = 0; offset < 10; offset++) { 603*5fc77b81SRobert Mustacchi if (pba_num[offset] < 0xA) 604*5fc77b81SRobert Mustacchi pba_num[offset] += '0'; 605*5fc77b81SRobert Mustacchi else if (pba_num[offset] < 0x10) 606*5fc77b81SRobert Mustacchi pba_num[offset] += 'A' - 0xA; 607*5fc77b81SRobert Mustacchi } 608*5fc77b81SRobert Mustacchi 609*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 610*5fc77b81SRobert Mustacchi } 611*5fc77b81SRobert Mustacchi 612*5fc77b81SRobert Mustacchi ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 613*5fc77b81SRobert Mustacchi if (ret_val) { 614*5fc77b81SRobert Mustacchi DEBUGOUT("NVM Read Error\n"); 615*5fc77b81SRobert Mustacchi return ret_val; 616*5fc77b81SRobert Mustacchi } 617*5fc77b81SRobert Mustacchi 618*5fc77b81SRobert Mustacchi if (length == 0xFFFF || length == 0) { 619*5fc77b81SRobert Mustacchi DEBUGOUT("NVM PBA number section invalid length\n"); 620*5fc77b81SRobert Mustacchi return IXGBE_ERR_PBA_SECTION; 621*5fc77b81SRobert Mustacchi } 622*5fc77b81SRobert Mustacchi 623*5fc77b81SRobert Mustacchi /* check if pba_num buffer is big enough */ 624*5fc77b81SRobert Mustacchi if (pba_num_size < (((u32)length * 2) - 1)) { 625*5fc77b81SRobert Mustacchi DEBUGOUT("PBA string buffer too small\n"); 626*5fc77b81SRobert Mustacchi return IXGBE_ERR_NO_SPACE; 627*5fc77b81SRobert Mustacchi } 628*5fc77b81SRobert Mustacchi 629*5fc77b81SRobert Mustacchi /* trim pba length from start of string */ 630*5fc77b81SRobert Mustacchi pba_ptr++; 631*5fc77b81SRobert Mustacchi length--; 632*5fc77b81SRobert Mustacchi 633*5fc77b81SRobert Mustacchi for (offset = 0; offset < length; offset++) { 634*5fc77b81SRobert Mustacchi ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 635*5fc77b81SRobert Mustacchi if (ret_val) { 636*5fc77b81SRobert Mustacchi DEBUGOUT("NVM Read Error\n"); 637*5fc77b81SRobert Mustacchi return ret_val; 638*5fc77b81SRobert Mustacchi } 639*5fc77b81SRobert Mustacchi pba_num[offset * 2] = (u8)(data >> 8); 640*5fc77b81SRobert Mustacchi pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 641*5fc77b81SRobert Mustacchi } 642*5fc77b81SRobert Mustacchi pba_num[offset * 2] = '\0'; 643*5fc77b81SRobert Mustacchi 644*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 645*5fc77b81SRobert Mustacchi } 646*5fc77b81SRobert Mustacchi 647*5fc77b81SRobert Mustacchi /** 648*5fc77b81SRobert Mustacchi * ixgbe_read_pba_num_generic - Reads part number from EEPROM 649*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 650*5fc77b81SRobert Mustacchi * @pba_num: stores the part number from the EEPROM 651*5fc77b81SRobert Mustacchi * 652*5fc77b81SRobert Mustacchi * Reads the part number from the EEPROM. 653*5fc77b81SRobert Mustacchi **/ 654*5fc77b81SRobert Mustacchi s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 655*5fc77b81SRobert Mustacchi { 656*5fc77b81SRobert Mustacchi s32 ret_val; 657*5fc77b81SRobert Mustacchi u16 data; 658*5fc77b81SRobert Mustacchi 659*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_read_pba_num_generic"); 660*5fc77b81SRobert Mustacchi 661*5fc77b81SRobert Mustacchi ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 662*5fc77b81SRobert Mustacchi if (ret_val) { 663*5fc77b81SRobert Mustacchi DEBUGOUT("NVM Read Error\n"); 664*5fc77b81SRobert Mustacchi return ret_val; 665*5fc77b81SRobert Mustacchi } else if (data == IXGBE_PBANUM_PTR_GUARD) { 666*5fc77b81SRobert Mustacchi DEBUGOUT("NVM Not supported\n"); 667*5fc77b81SRobert Mustacchi return IXGBE_NOT_IMPLEMENTED; 668*5fc77b81SRobert Mustacchi } 669*5fc77b81SRobert Mustacchi *pba_num = (u32)(data << 16); 670*5fc77b81SRobert Mustacchi 671*5fc77b81SRobert Mustacchi ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 672*5fc77b81SRobert Mustacchi if (ret_val) { 673*5fc77b81SRobert Mustacchi DEBUGOUT("NVM Read Error\n"); 674*5fc77b81SRobert Mustacchi return ret_val; 675*5fc77b81SRobert Mustacchi } 676*5fc77b81SRobert Mustacchi *pba_num |= data; 677*5fc77b81SRobert Mustacchi 678*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 679*5fc77b81SRobert Mustacchi } 680*5fc77b81SRobert Mustacchi 681*5fc77b81SRobert Mustacchi /** 682*5fc77b81SRobert Mustacchi * ixgbe_get_mac_addr_generic - Generic get MAC address 683*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 684*5fc77b81SRobert Mustacchi * @mac_addr: Adapter MAC address 685*5fc77b81SRobert Mustacchi * 686*5fc77b81SRobert Mustacchi * Reads the adapter's MAC address from first Receive Address Register (RAR0) 687*5fc77b81SRobert Mustacchi * A reset of the adapter must be performed prior to calling this function 688*5fc77b81SRobert Mustacchi * in order for the MAC address to have been loaded from the EEPROM into RAR0 689*5fc77b81SRobert Mustacchi **/ 690*5fc77b81SRobert Mustacchi s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 691*5fc77b81SRobert Mustacchi { 692*5fc77b81SRobert Mustacchi u32 rar_high; 693*5fc77b81SRobert Mustacchi u32 rar_low; 694*5fc77b81SRobert Mustacchi u16 i; 695*5fc77b81SRobert Mustacchi 696*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_get_mac_addr_generic"); 697*5fc77b81SRobert Mustacchi 698*5fc77b81SRobert Mustacchi rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 699*5fc77b81SRobert Mustacchi rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 700*5fc77b81SRobert Mustacchi 701*5fc77b81SRobert Mustacchi for (i = 0; i < 4; i++) 702*5fc77b81SRobert Mustacchi mac_addr[i] = (u8)(rar_low >> (i*8)); 703*5fc77b81SRobert Mustacchi 704*5fc77b81SRobert Mustacchi for (i = 0; i < 2; i++) 705*5fc77b81SRobert Mustacchi mac_addr[i+4] = (u8)(rar_high >> (i*8)); 706*5fc77b81SRobert Mustacchi 707*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 708*5fc77b81SRobert Mustacchi } 709*5fc77b81SRobert Mustacchi 710*5fc77b81SRobert Mustacchi /** 711*5fc77b81SRobert Mustacchi * ixgbe_get_bus_info_generic - Generic set PCI bus info 712*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 713*5fc77b81SRobert Mustacchi * 714*5fc77b81SRobert Mustacchi * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 715*5fc77b81SRobert Mustacchi **/ 716*5fc77b81SRobert Mustacchi s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 717*5fc77b81SRobert Mustacchi { 718*5fc77b81SRobert Mustacchi struct ixgbe_mac_info *mac = &hw->mac; 719*5fc77b81SRobert Mustacchi u16 link_status; 720*5fc77b81SRobert Mustacchi 721*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_get_bus_info_generic"); 722*5fc77b81SRobert Mustacchi 723*5fc77b81SRobert Mustacchi hw->bus.type = ixgbe_bus_type_pci_express; 724*5fc77b81SRobert Mustacchi 725*5fc77b81SRobert Mustacchi /* Get the negotiated link width and speed from PCI config space */ 726*5fc77b81SRobert Mustacchi link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 727*5fc77b81SRobert Mustacchi 728*5fc77b81SRobert Mustacchi switch (link_status & IXGBE_PCI_LINK_WIDTH) { 729*5fc77b81SRobert Mustacchi case IXGBE_PCI_LINK_WIDTH_1: 730*5fc77b81SRobert Mustacchi hw->bus.width = ixgbe_bus_width_pcie_x1; 731*5fc77b81SRobert Mustacchi break; 732*5fc77b81SRobert Mustacchi case IXGBE_PCI_LINK_WIDTH_2: 733*5fc77b81SRobert Mustacchi hw->bus.width = ixgbe_bus_width_pcie_x2; 734*5fc77b81SRobert Mustacchi break; 735*5fc77b81SRobert Mustacchi case IXGBE_PCI_LINK_WIDTH_4: 736*5fc77b81SRobert Mustacchi hw->bus.width = ixgbe_bus_width_pcie_x4; 737*5fc77b81SRobert Mustacchi break; 738*5fc77b81SRobert Mustacchi case IXGBE_PCI_LINK_WIDTH_8: 739*5fc77b81SRobert Mustacchi hw->bus.width = ixgbe_bus_width_pcie_x8; 740*5fc77b81SRobert Mustacchi break; 741*5fc77b81SRobert Mustacchi default: 742*5fc77b81SRobert Mustacchi hw->bus.width = ixgbe_bus_width_unknown; 743*5fc77b81SRobert Mustacchi break; 744*5fc77b81SRobert Mustacchi } 745*5fc77b81SRobert Mustacchi 746*5fc77b81SRobert Mustacchi switch (link_status & IXGBE_PCI_LINK_SPEED) { 747*5fc77b81SRobert Mustacchi case IXGBE_PCI_LINK_SPEED_2500: 748*5fc77b81SRobert Mustacchi hw->bus.speed = ixgbe_bus_speed_2500; 749*5fc77b81SRobert Mustacchi break; 750*5fc77b81SRobert Mustacchi case IXGBE_PCI_LINK_SPEED_5000: 751*5fc77b81SRobert Mustacchi hw->bus.speed = ixgbe_bus_speed_5000; 752*5fc77b81SRobert Mustacchi break; 753*5fc77b81SRobert Mustacchi case IXGBE_PCI_LINK_SPEED_8000: 754*5fc77b81SRobert Mustacchi hw->bus.speed = ixgbe_bus_speed_8000; 755*5fc77b81SRobert Mustacchi break; 756*5fc77b81SRobert Mustacchi default: 757*5fc77b81SRobert Mustacchi hw->bus.speed = ixgbe_bus_speed_unknown; 758*5fc77b81SRobert Mustacchi break; 759*5fc77b81SRobert Mustacchi } 760*5fc77b81SRobert Mustacchi 761*5fc77b81SRobert Mustacchi mac->ops.set_lan_id(hw); 762*5fc77b81SRobert Mustacchi 763*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 764*5fc77b81SRobert Mustacchi } 765*5fc77b81SRobert Mustacchi 766*5fc77b81SRobert Mustacchi /** 767*5fc77b81SRobert Mustacchi * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 768*5fc77b81SRobert Mustacchi * @hw: pointer to the HW structure 769*5fc77b81SRobert Mustacchi * 770*5fc77b81SRobert Mustacchi * Determines the LAN function id by reading memory-mapped registers 771*5fc77b81SRobert Mustacchi * and swaps the port value if requested. 772*5fc77b81SRobert Mustacchi **/ 773*5fc77b81SRobert Mustacchi void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 774*5fc77b81SRobert Mustacchi { 775*5fc77b81SRobert Mustacchi struct ixgbe_bus_info *bus = &hw->bus; 776*5fc77b81SRobert Mustacchi u32 reg; 777*5fc77b81SRobert Mustacchi 778*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 779*5fc77b81SRobert Mustacchi 780*5fc77b81SRobert Mustacchi reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 781*5fc77b81SRobert Mustacchi bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 782*5fc77b81SRobert Mustacchi bus->lan_id = bus->func; 783*5fc77b81SRobert Mustacchi 784*5fc77b81SRobert Mustacchi /* check for a port swap */ 785*5fc77b81SRobert Mustacchi reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 786*5fc77b81SRobert Mustacchi if (reg & IXGBE_FACTPS_LFS) 787*5fc77b81SRobert Mustacchi bus->func ^= 0x1; 788*5fc77b81SRobert Mustacchi } 789*5fc77b81SRobert Mustacchi 790*5fc77b81SRobert Mustacchi /** 791*5fc77b81SRobert Mustacchi * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 792*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 793*5fc77b81SRobert Mustacchi * 794*5fc77b81SRobert Mustacchi * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 795*5fc77b81SRobert Mustacchi * disables transmit and receive units. The adapter_stopped flag is used by 796*5fc77b81SRobert Mustacchi * the shared code and drivers to determine if the adapter is in a stopped 797*5fc77b81SRobert Mustacchi * state and should not touch the hardware. 798*5fc77b81SRobert Mustacchi **/ 799*5fc77b81SRobert Mustacchi s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 800*5fc77b81SRobert Mustacchi { 801*5fc77b81SRobert Mustacchi u32 reg_val; 802*5fc77b81SRobert Mustacchi u16 i; 803*5fc77b81SRobert Mustacchi 804*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_stop_adapter_generic"); 805*5fc77b81SRobert Mustacchi 806*5fc77b81SRobert Mustacchi /* 807*5fc77b81SRobert Mustacchi * Set the adapter_stopped flag so other driver functions stop touching 808*5fc77b81SRobert Mustacchi * the hardware 809*5fc77b81SRobert Mustacchi */ 810*5fc77b81SRobert Mustacchi hw->adapter_stopped = TRUE; 811*5fc77b81SRobert Mustacchi 812*5fc77b81SRobert Mustacchi /* Disable the receive unit */ 813*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0); 814*5fc77b81SRobert Mustacchi 815*5fc77b81SRobert Mustacchi /* Clear interrupt mask to stop interrupts from being generated */ 816*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 817*5fc77b81SRobert Mustacchi 818*5fc77b81SRobert Mustacchi /* Clear any pending interrupts, flush previous writes */ 819*5fc77b81SRobert Mustacchi (void) IXGBE_READ_REG(hw, IXGBE_EICR); 820*5fc77b81SRobert Mustacchi 821*5fc77b81SRobert Mustacchi /* Disable the transmit unit. Each queue must be disabled. */ 822*5fc77b81SRobert Mustacchi for (i = 0; i < hw->mac.max_tx_queues; i++) 823*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 824*5fc77b81SRobert Mustacchi 825*5fc77b81SRobert Mustacchi /* Disable the receive unit by stopping each queue */ 826*5fc77b81SRobert Mustacchi for (i = 0; i < hw->mac.max_rx_queues; i++) { 827*5fc77b81SRobert Mustacchi reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 828*5fc77b81SRobert Mustacchi reg_val &= ~IXGBE_RXDCTL_ENABLE; 829*5fc77b81SRobert Mustacchi reg_val |= IXGBE_RXDCTL_SWFLSH; 830*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 831*5fc77b81SRobert Mustacchi } 832*5fc77b81SRobert Mustacchi 833*5fc77b81SRobert Mustacchi /* flush all queues disables */ 834*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 835*5fc77b81SRobert Mustacchi msec_delay(2); 836*5fc77b81SRobert Mustacchi 837*5fc77b81SRobert Mustacchi /* 838*5fc77b81SRobert Mustacchi * Prevent the PCI-E bus from from hanging by disabling PCI-E master 839*5fc77b81SRobert Mustacchi * access and verify no pending requests 840*5fc77b81SRobert Mustacchi */ 841*5fc77b81SRobert Mustacchi return ixgbe_disable_pcie_master(hw); 842*5fc77b81SRobert Mustacchi } 843*5fc77b81SRobert Mustacchi 844*5fc77b81SRobert Mustacchi /** 845*5fc77b81SRobert Mustacchi * ixgbe_led_on_generic - Turns on the software controllable LEDs. 846*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 847*5fc77b81SRobert Mustacchi * @index: led number to turn on 848*5fc77b81SRobert Mustacchi **/ 849*5fc77b81SRobert Mustacchi s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 850*5fc77b81SRobert Mustacchi { 851*5fc77b81SRobert Mustacchi u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 852*5fc77b81SRobert Mustacchi 853*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_led_on_generic"); 854*5fc77b81SRobert Mustacchi 855*5fc77b81SRobert Mustacchi /* To turn on the LED, set mode to ON. */ 856*5fc77b81SRobert Mustacchi led_reg &= ~IXGBE_LED_MODE_MASK(index); 857*5fc77b81SRobert Mustacchi led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 858*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 859*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 860*5fc77b81SRobert Mustacchi 861*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 862*5fc77b81SRobert Mustacchi } 863*5fc77b81SRobert Mustacchi 864*5fc77b81SRobert Mustacchi /** 865*5fc77b81SRobert Mustacchi * ixgbe_led_off_generic - Turns off the software controllable LEDs. 866*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 867*5fc77b81SRobert Mustacchi * @index: led number to turn off 868*5fc77b81SRobert Mustacchi **/ 869*5fc77b81SRobert Mustacchi s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 870*5fc77b81SRobert Mustacchi { 871*5fc77b81SRobert Mustacchi u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 872*5fc77b81SRobert Mustacchi 873*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_led_off_generic"); 874*5fc77b81SRobert Mustacchi 875*5fc77b81SRobert Mustacchi /* To turn off the LED, set mode to OFF. */ 876*5fc77b81SRobert Mustacchi led_reg &= ~IXGBE_LED_MODE_MASK(index); 877*5fc77b81SRobert Mustacchi led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 878*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 879*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 880*5fc77b81SRobert Mustacchi 881*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 882*5fc77b81SRobert Mustacchi } 883*5fc77b81SRobert Mustacchi 884*5fc77b81SRobert Mustacchi /** 885*5fc77b81SRobert Mustacchi * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 886*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 887*5fc77b81SRobert Mustacchi * 888*5fc77b81SRobert Mustacchi * Initializes the EEPROM parameters ixgbe_eeprom_info within the 889*5fc77b81SRobert Mustacchi * ixgbe_hw struct in order to set up EEPROM access. 890*5fc77b81SRobert Mustacchi **/ 891*5fc77b81SRobert Mustacchi s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 892*5fc77b81SRobert Mustacchi { 893*5fc77b81SRobert Mustacchi struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 894*5fc77b81SRobert Mustacchi u32 eec; 895*5fc77b81SRobert Mustacchi u16 eeprom_size; 896*5fc77b81SRobert Mustacchi 897*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 898*5fc77b81SRobert Mustacchi 899*5fc77b81SRobert Mustacchi if (eeprom->type == ixgbe_eeprom_uninitialized) { 900*5fc77b81SRobert Mustacchi eeprom->type = ixgbe_eeprom_none; 901*5fc77b81SRobert Mustacchi /* Set default semaphore delay to 10ms which is a well 902*5fc77b81SRobert Mustacchi * tested value */ 903*5fc77b81SRobert Mustacchi eeprom->semaphore_delay = 10; 904*5fc77b81SRobert Mustacchi /* Clear EEPROM page size, it will be initialized as needed */ 905*5fc77b81SRobert Mustacchi eeprom->word_page_size = 0; 906*5fc77b81SRobert Mustacchi 907*5fc77b81SRobert Mustacchi /* 908*5fc77b81SRobert Mustacchi * Check for EEPROM present first. 909*5fc77b81SRobert Mustacchi * If not present leave as none 910*5fc77b81SRobert Mustacchi */ 911*5fc77b81SRobert Mustacchi eec = IXGBE_READ_REG(hw, IXGBE_EEC); 912*5fc77b81SRobert Mustacchi if (eec & IXGBE_EEC_PRES) { 913*5fc77b81SRobert Mustacchi eeprom->type = ixgbe_eeprom_spi; 914*5fc77b81SRobert Mustacchi 915*5fc77b81SRobert Mustacchi /* 916*5fc77b81SRobert Mustacchi * SPI EEPROM is assumed here. This code would need to 917*5fc77b81SRobert Mustacchi * change if a future EEPROM is not SPI. 918*5fc77b81SRobert Mustacchi */ 919*5fc77b81SRobert Mustacchi eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 920*5fc77b81SRobert Mustacchi IXGBE_EEC_SIZE_SHIFT); 921*5fc77b81SRobert Mustacchi eeprom->word_size = 1 << (eeprom_size + 922*5fc77b81SRobert Mustacchi IXGBE_EEPROM_WORD_SIZE_SHIFT); 923*5fc77b81SRobert Mustacchi } 924*5fc77b81SRobert Mustacchi 925*5fc77b81SRobert Mustacchi if (eec & IXGBE_EEC_ADDR_SIZE) 926*5fc77b81SRobert Mustacchi eeprom->address_bits = 16; 927*5fc77b81SRobert Mustacchi else 928*5fc77b81SRobert Mustacchi eeprom->address_bits = 8; 929*5fc77b81SRobert Mustacchi DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 930*5fc77b81SRobert Mustacchi "%d\n", eeprom->type, eeprom->word_size, 931*5fc77b81SRobert Mustacchi eeprom->address_bits); 932*5fc77b81SRobert Mustacchi } 933*5fc77b81SRobert Mustacchi 934*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 935*5fc77b81SRobert Mustacchi } 936*5fc77b81SRobert Mustacchi 937*5fc77b81SRobert Mustacchi /** 938*5fc77b81SRobert Mustacchi * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 939*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 940*5fc77b81SRobert Mustacchi * @offset: offset within the EEPROM to write 941*5fc77b81SRobert Mustacchi * @words: number of word(s) 942*5fc77b81SRobert Mustacchi * @data: 16 bit word(s) to write to EEPROM 943*5fc77b81SRobert Mustacchi * 944*5fc77b81SRobert Mustacchi * Reads 16 bit word(s) from EEPROM through bit-bang method 945*5fc77b81SRobert Mustacchi **/ 946*5fc77b81SRobert Mustacchi s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 947*5fc77b81SRobert Mustacchi u16 words, u16 *data) 948*5fc77b81SRobert Mustacchi { 949*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 950*5fc77b81SRobert Mustacchi u16 i, count; 951*5fc77b81SRobert Mustacchi 952*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 953*5fc77b81SRobert Mustacchi 954*5fc77b81SRobert Mustacchi hw->eeprom.ops.init_params(hw); 955*5fc77b81SRobert Mustacchi 956*5fc77b81SRobert Mustacchi if (words == 0) { 957*5fc77b81SRobert Mustacchi status = IXGBE_ERR_INVALID_ARGUMENT; 958*5fc77b81SRobert Mustacchi goto out; 959*5fc77b81SRobert Mustacchi } 960*5fc77b81SRobert Mustacchi 961*5fc77b81SRobert Mustacchi if (offset + words > hw->eeprom.word_size) { 962*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 963*5fc77b81SRobert Mustacchi goto out; 964*5fc77b81SRobert Mustacchi } 965*5fc77b81SRobert Mustacchi 966*5fc77b81SRobert Mustacchi /* 967*5fc77b81SRobert Mustacchi * The EEPROM page size cannot be queried from the chip. We do lazy 968*5fc77b81SRobert Mustacchi * initialization. It is worth to do that when we write large buffer. 969*5fc77b81SRobert Mustacchi */ 970*5fc77b81SRobert Mustacchi if ((hw->eeprom.word_page_size == 0) && 971*5fc77b81SRobert Mustacchi (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 972*5fc77b81SRobert Mustacchi status = ixgbe_detect_eeprom_page_size_generic(hw, offset); 973*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) 974*5fc77b81SRobert Mustacchi goto out; 975*5fc77b81SRobert Mustacchi 976*5fc77b81SRobert Mustacchi /* 977*5fc77b81SRobert Mustacchi * We cannot hold synchronization semaphores for too long 978*5fc77b81SRobert Mustacchi * to avoid other entity starvation. However it is more efficient 979*5fc77b81SRobert Mustacchi * to read in bursts than synchronizing access for each word. 980*5fc77b81SRobert Mustacchi */ 981*5fc77b81SRobert Mustacchi for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 982*5fc77b81SRobert Mustacchi count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 983*5fc77b81SRobert Mustacchi IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 984*5fc77b81SRobert Mustacchi status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 985*5fc77b81SRobert Mustacchi count, &data[i]); 986*5fc77b81SRobert Mustacchi 987*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) 988*5fc77b81SRobert Mustacchi break; 989*5fc77b81SRobert Mustacchi } 990*5fc77b81SRobert Mustacchi 991*5fc77b81SRobert Mustacchi out: 992*5fc77b81SRobert Mustacchi return status; 993*5fc77b81SRobert Mustacchi } 994*5fc77b81SRobert Mustacchi 995*5fc77b81SRobert Mustacchi /** 996*5fc77b81SRobert Mustacchi * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 997*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 998*5fc77b81SRobert Mustacchi * @offset: offset within the EEPROM to be written to 999*5fc77b81SRobert Mustacchi * @words: number of word(s) 1000*5fc77b81SRobert Mustacchi * @data: 16 bit word(s) to be written to the EEPROM 1001*5fc77b81SRobert Mustacchi * 1002*5fc77b81SRobert Mustacchi * If ixgbe_eeprom_update_checksum is not called after this function, the 1003*5fc77b81SRobert Mustacchi * EEPROM will most likely contain an invalid checksum. 1004*5fc77b81SRobert Mustacchi **/ 1005*5fc77b81SRobert Mustacchi static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1006*5fc77b81SRobert Mustacchi u16 words, u16 *data) 1007*5fc77b81SRobert Mustacchi { 1008*5fc77b81SRobert Mustacchi s32 status; 1009*5fc77b81SRobert Mustacchi u16 word; 1010*5fc77b81SRobert Mustacchi u16 page_size; 1011*5fc77b81SRobert Mustacchi u16 i; 1012*5fc77b81SRobert Mustacchi u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1013*5fc77b81SRobert Mustacchi 1014*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1015*5fc77b81SRobert Mustacchi 1016*5fc77b81SRobert Mustacchi /* Prepare the EEPROM for writing */ 1017*5fc77b81SRobert Mustacchi status = ixgbe_acquire_eeprom(hw); 1018*5fc77b81SRobert Mustacchi 1019*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1020*5fc77b81SRobert Mustacchi if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1021*5fc77b81SRobert Mustacchi ixgbe_release_eeprom(hw); 1022*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1023*5fc77b81SRobert Mustacchi } 1024*5fc77b81SRobert Mustacchi } 1025*5fc77b81SRobert Mustacchi 1026*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1027*5fc77b81SRobert Mustacchi for (i = 0; i < words; i++) { 1028*5fc77b81SRobert Mustacchi ixgbe_standby_eeprom(hw); 1029*5fc77b81SRobert Mustacchi 1030*5fc77b81SRobert Mustacchi /* Send the WRITE ENABLE command (8 bit opcode ) */ 1031*5fc77b81SRobert Mustacchi ixgbe_shift_out_eeprom_bits(hw, 1032*5fc77b81SRobert Mustacchi IXGBE_EEPROM_WREN_OPCODE_SPI, 1033*5fc77b81SRobert Mustacchi IXGBE_EEPROM_OPCODE_BITS); 1034*5fc77b81SRobert Mustacchi 1035*5fc77b81SRobert Mustacchi ixgbe_standby_eeprom(hw); 1036*5fc77b81SRobert Mustacchi 1037*5fc77b81SRobert Mustacchi /* 1038*5fc77b81SRobert Mustacchi * Some SPI eeproms use the 8th address bit embedded 1039*5fc77b81SRobert Mustacchi * in the opcode 1040*5fc77b81SRobert Mustacchi */ 1041*5fc77b81SRobert Mustacchi if ((hw->eeprom.address_bits == 8) && 1042*5fc77b81SRobert Mustacchi ((offset + i) >= 128)) 1043*5fc77b81SRobert Mustacchi write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1044*5fc77b81SRobert Mustacchi 1045*5fc77b81SRobert Mustacchi /* Send the Write command (8-bit opcode + addr) */ 1046*5fc77b81SRobert Mustacchi ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1047*5fc77b81SRobert Mustacchi IXGBE_EEPROM_OPCODE_BITS); 1048*5fc77b81SRobert Mustacchi ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1049*5fc77b81SRobert Mustacchi hw->eeprom.address_bits); 1050*5fc77b81SRobert Mustacchi 1051*5fc77b81SRobert Mustacchi page_size = hw->eeprom.word_page_size; 1052*5fc77b81SRobert Mustacchi 1053*5fc77b81SRobert Mustacchi /* Send the data in burst via SPI*/ 1054*5fc77b81SRobert Mustacchi do { 1055*5fc77b81SRobert Mustacchi word = data[i]; 1056*5fc77b81SRobert Mustacchi word = (word >> 8) | (word << 8); 1057*5fc77b81SRobert Mustacchi ixgbe_shift_out_eeprom_bits(hw, word, 16); 1058*5fc77b81SRobert Mustacchi 1059*5fc77b81SRobert Mustacchi if (page_size == 0) 1060*5fc77b81SRobert Mustacchi break; 1061*5fc77b81SRobert Mustacchi 1062*5fc77b81SRobert Mustacchi /* do not wrap around page */ 1063*5fc77b81SRobert Mustacchi if (((offset + i) & (page_size - 1)) == 1064*5fc77b81SRobert Mustacchi (page_size - 1)) 1065*5fc77b81SRobert Mustacchi break; 1066*5fc77b81SRobert Mustacchi } while (++i < words); 1067*5fc77b81SRobert Mustacchi 1068*5fc77b81SRobert Mustacchi ixgbe_standby_eeprom(hw); 1069*5fc77b81SRobert Mustacchi msec_delay(10); 1070*5fc77b81SRobert Mustacchi } 1071*5fc77b81SRobert Mustacchi /* Done with writing - release the EEPROM */ 1072*5fc77b81SRobert Mustacchi ixgbe_release_eeprom(hw); 1073*5fc77b81SRobert Mustacchi } 1074*5fc77b81SRobert Mustacchi 1075*5fc77b81SRobert Mustacchi return status; 1076*5fc77b81SRobert Mustacchi } 1077*5fc77b81SRobert Mustacchi 1078*5fc77b81SRobert Mustacchi /** 1079*5fc77b81SRobert Mustacchi * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1080*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1081*5fc77b81SRobert Mustacchi * @offset: offset within the EEPROM to be written to 1082*5fc77b81SRobert Mustacchi * @data: 16 bit word to be written to the EEPROM 1083*5fc77b81SRobert Mustacchi * 1084*5fc77b81SRobert Mustacchi * If ixgbe_eeprom_update_checksum is not called after this function, the 1085*5fc77b81SRobert Mustacchi * EEPROM will most likely contain an invalid checksum. 1086*5fc77b81SRobert Mustacchi **/ 1087*5fc77b81SRobert Mustacchi s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1088*5fc77b81SRobert Mustacchi { 1089*5fc77b81SRobert Mustacchi s32 status; 1090*5fc77b81SRobert Mustacchi 1091*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_write_eeprom_generic"); 1092*5fc77b81SRobert Mustacchi 1093*5fc77b81SRobert Mustacchi hw->eeprom.ops.init_params(hw); 1094*5fc77b81SRobert Mustacchi 1095*5fc77b81SRobert Mustacchi if (offset >= hw->eeprom.word_size) { 1096*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1097*5fc77b81SRobert Mustacchi goto out; 1098*5fc77b81SRobert Mustacchi } 1099*5fc77b81SRobert Mustacchi 1100*5fc77b81SRobert Mustacchi status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1101*5fc77b81SRobert Mustacchi 1102*5fc77b81SRobert Mustacchi out: 1103*5fc77b81SRobert Mustacchi return status; 1104*5fc77b81SRobert Mustacchi } 1105*5fc77b81SRobert Mustacchi 1106*5fc77b81SRobert Mustacchi /** 1107*5fc77b81SRobert Mustacchi * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1108*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1109*5fc77b81SRobert Mustacchi * @offset: offset within the EEPROM to be read 1110*5fc77b81SRobert Mustacchi * @data: read 16 bit words(s) from EEPROM 1111*5fc77b81SRobert Mustacchi * @words: number of word(s) 1112*5fc77b81SRobert Mustacchi * 1113*5fc77b81SRobert Mustacchi * Reads 16 bit word(s) from EEPROM through bit-bang method 1114*5fc77b81SRobert Mustacchi **/ 1115*5fc77b81SRobert Mustacchi s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1116*5fc77b81SRobert Mustacchi u16 words, u16 *data) 1117*5fc77b81SRobert Mustacchi { 1118*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 1119*5fc77b81SRobert Mustacchi u16 i, count; 1120*5fc77b81SRobert Mustacchi 1121*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1122*5fc77b81SRobert Mustacchi 1123*5fc77b81SRobert Mustacchi hw->eeprom.ops.init_params(hw); 1124*5fc77b81SRobert Mustacchi 1125*5fc77b81SRobert Mustacchi if (words == 0) { 1126*5fc77b81SRobert Mustacchi status = IXGBE_ERR_INVALID_ARGUMENT; 1127*5fc77b81SRobert Mustacchi goto out; 1128*5fc77b81SRobert Mustacchi } 1129*5fc77b81SRobert Mustacchi 1130*5fc77b81SRobert Mustacchi if (offset + words > hw->eeprom.word_size) { 1131*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1132*5fc77b81SRobert Mustacchi goto out; 1133*5fc77b81SRobert Mustacchi } 1134*5fc77b81SRobert Mustacchi 1135*5fc77b81SRobert Mustacchi /* 1136*5fc77b81SRobert Mustacchi * We cannot hold synchronization semaphores for too long 1137*5fc77b81SRobert Mustacchi * to avoid other entity starvation. However it is more efficient 1138*5fc77b81SRobert Mustacchi * to read in bursts than synchronizing access for each word. 1139*5fc77b81SRobert Mustacchi */ 1140*5fc77b81SRobert Mustacchi for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1141*5fc77b81SRobert Mustacchi count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1142*5fc77b81SRobert Mustacchi IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1143*5fc77b81SRobert Mustacchi 1144*5fc77b81SRobert Mustacchi status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1145*5fc77b81SRobert Mustacchi count, &data[i]); 1146*5fc77b81SRobert Mustacchi 1147*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) 1148*5fc77b81SRobert Mustacchi break; 1149*5fc77b81SRobert Mustacchi } 1150*5fc77b81SRobert Mustacchi 1151*5fc77b81SRobert Mustacchi out: 1152*5fc77b81SRobert Mustacchi return status; 1153*5fc77b81SRobert Mustacchi } 1154*5fc77b81SRobert Mustacchi 1155*5fc77b81SRobert Mustacchi /** 1156*5fc77b81SRobert Mustacchi * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1157*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1158*5fc77b81SRobert Mustacchi * @offset: offset within the EEPROM to be read 1159*5fc77b81SRobert Mustacchi * @words: number of word(s) 1160*5fc77b81SRobert Mustacchi * @data: read 16 bit word(s) from EEPROM 1161*5fc77b81SRobert Mustacchi * 1162*5fc77b81SRobert Mustacchi * Reads 16 bit word(s) from EEPROM through bit-bang method 1163*5fc77b81SRobert Mustacchi **/ 1164*5fc77b81SRobert Mustacchi static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1165*5fc77b81SRobert Mustacchi u16 words, u16 *data) 1166*5fc77b81SRobert Mustacchi { 1167*5fc77b81SRobert Mustacchi s32 status; 1168*5fc77b81SRobert Mustacchi u16 word_in; 1169*5fc77b81SRobert Mustacchi u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1170*5fc77b81SRobert Mustacchi u16 i; 1171*5fc77b81SRobert Mustacchi 1172*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1173*5fc77b81SRobert Mustacchi 1174*5fc77b81SRobert Mustacchi /* Prepare the EEPROM for reading */ 1175*5fc77b81SRobert Mustacchi status = ixgbe_acquire_eeprom(hw); 1176*5fc77b81SRobert Mustacchi 1177*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1178*5fc77b81SRobert Mustacchi if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1179*5fc77b81SRobert Mustacchi ixgbe_release_eeprom(hw); 1180*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1181*5fc77b81SRobert Mustacchi } 1182*5fc77b81SRobert Mustacchi } 1183*5fc77b81SRobert Mustacchi 1184*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1185*5fc77b81SRobert Mustacchi for (i = 0; i < words; i++) { 1186*5fc77b81SRobert Mustacchi ixgbe_standby_eeprom(hw); 1187*5fc77b81SRobert Mustacchi /* 1188*5fc77b81SRobert Mustacchi * Some SPI eeproms use the 8th address bit embedded 1189*5fc77b81SRobert Mustacchi * in the opcode 1190*5fc77b81SRobert Mustacchi */ 1191*5fc77b81SRobert Mustacchi if ((hw->eeprom.address_bits == 8) && 1192*5fc77b81SRobert Mustacchi ((offset + i) >= 128)) 1193*5fc77b81SRobert Mustacchi read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1194*5fc77b81SRobert Mustacchi 1195*5fc77b81SRobert Mustacchi /* Send the READ command (opcode + addr) */ 1196*5fc77b81SRobert Mustacchi ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1197*5fc77b81SRobert Mustacchi IXGBE_EEPROM_OPCODE_BITS); 1198*5fc77b81SRobert Mustacchi ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1199*5fc77b81SRobert Mustacchi hw->eeprom.address_bits); 1200*5fc77b81SRobert Mustacchi 1201*5fc77b81SRobert Mustacchi /* Read the data. */ 1202*5fc77b81SRobert Mustacchi word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1203*5fc77b81SRobert Mustacchi data[i] = (word_in >> 8) | (word_in << 8); 1204*5fc77b81SRobert Mustacchi } 1205*5fc77b81SRobert Mustacchi 1206*5fc77b81SRobert Mustacchi /* End this read operation */ 1207*5fc77b81SRobert Mustacchi ixgbe_release_eeprom(hw); 1208*5fc77b81SRobert Mustacchi } 1209*5fc77b81SRobert Mustacchi 1210*5fc77b81SRobert Mustacchi return status; 1211*5fc77b81SRobert Mustacchi } 1212*5fc77b81SRobert Mustacchi 1213*5fc77b81SRobert Mustacchi /** 1214*5fc77b81SRobert Mustacchi * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1215*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1216*5fc77b81SRobert Mustacchi * @offset: offset within the EEPROM to be read 1217*5fc77b81SRobert Mustacchi * @data: read 16 bit value from EEPROM 1218*5fc77b81SRobert Mustacchi * 1219*5fc77b81SRobert Mustacchi * Reads 16 bit value from EEPROM through bit-bang method 1220*5fc77b81SRobert Mustacchi **/ 1221*5fc77b81SRobert Mustacchi s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1222*5fc77b81SRobert Mustacchi u16 *data) 1223*5fc77b81SRobert Mustacchi { 1224*5fc77b81SRobert Mustacchi s32 status; 1225*5fc77b81SRobert Mustacchi 1226*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1227*5fc77b81SRobert Mustacchi 1228*5fc77b81SRobert Mustacchi hw->eeprom.ops.init_params(hw); 1229*5fc77b81SRobert Mustacchi 1230*5fc77b81SRobert Mustacchi if (offset >= hw->eeprom.word_size) { 1231*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1232*5fc77b81SRobert Mustacchi goto out; 1233*5fc77b81SRobert Mustacchi } 1234*5fc77b81SRobert Mustacchi 1235*5fc77b81SRobert Mustacchi status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1236*5fc77b81SRobert Mustacchi 1237*5fc77b81SRobert Mustacchi out: 1238*5fc77b81SRobert Mustacchi return status; 1239*5fc77b81SRobert Mustacchi } 1240*5fc77b81SRobert Mustacchi 1241*5fc77b81SRobert Mustacchi /** 1242*5fc77b81SRobert Mustacchi * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1243*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1244*5fc77b81SRobert Mustacchi * @offset: offset of word in the EEPROM to read 1245*5fc77b81SRobert Mustacchi * @words: number of word(s) 1246*5fc77b81SRobert Mustacchi * @data: 16 bit word(s) from the EEPROM 1247*5fc77b81SRobert Mustacchi * 1248*5fc77b81SRobert Mustacchi * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1249*5fc77b81SRobert Mustacchi **/ 1250*5fc77b81SRobert Mustacchi s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1251*5fc77b81SRobert Mustacchi u16 words, u16 *data) 1252*5fc77b81SRobert Mustacchi { 1253*5fc77b81SRobert Mustacchi u32 eerd; 1254*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 1255*5fc77b81SRobert Mustacchi u32 i; 1256*5fc77b81SRobert Mustacchi 1257*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1258*5fc77b81SRobert Mustacchi 1259*5fc77b81SRobert Mustacchi hw->eeprom.ops.init_params(hw); 1260*5fc77b81SRobert Mustacchi 1261*5fc77b81SRobert Mustacchi if (words == 0) { 1262*5fc77b81SRobert Mustacchi status = IXGBE_ERR_INVALID_ARGUMENT; 1263*5fc77b81SRobert Mustacchi goto out; 1264*5fc77b81SRobert Mustacchi } 1265*5fc77b81SRobert Mustacchi 1266*5fc77b81SRobert Mustacchi if (offset >= hw->eeprom.word_size) { 1267*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1268*5fc77b81SRobert Mustacchi goto out; 1269*5fc77b81SRobert Mustacchi } 1270*5fc77b81SRobert Mustacchi 1271*5fc77b81SRobert Mustacchi for (i = 0; i < words; i++) { 1272*5fc77b81SRobert Mustacchi eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) + 1273*5fc77b81SRobert Mustacchi IXGBE_EEPROM_RW_REG_START; 1274*5fc77b81SRobert Mustacchi 1275*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1276*5fc77b81SRobert Mustacchi status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1277*5fc77b81SRobert Mustacchi 1278*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1279*5fc77b81SRobert Mustacchi data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1280*5fc77b81SRobert Mustacchi IXGBE_EEPROM_RW_REG_DATA); 1281*5fc77b81SRobert Mustacchi } else { 1282*5fc77b81SRobert Mustacchi DEBUGOUT("Eeprom read timed out\n"); 1283*5fc77b81SRobert Mustacchi goto out; 1284*5fc77b81SRobert Mustacchi } 1285*5fc77b81SRobert Mustacchi } 1286*5fc77b81SRobert Mustacchi out: 1287*5fc77b81SRobert Mustacchi return status; 1288*5fc77b81SRobert Mustacchi } 1289*5fc77b81SRobert Mustacchi 1290*5fc77b81SRobert Mustacchi /** 1291*5fc77b81SRobert Mustacchi * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1292*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1293*5fc77b81SRobert Mustacchi * @offset: offset within the EEPROM to be used as a scratch pad 1294*5fc77b81SRobert Mustacchi * 1295*5fc77b81SRobert Mustacchi * Discover EEPROM page size by writing marching data at given offset. 1296*5fc77b81SRobert Mustacchi * This function is called only when we are writing a new large buffer 1297*5fc77b81SRobert Mustacchi * at given offset so the data would be overwritten anyway. 1298*5fc77b81SRobert Mustacchi **/ 1299*5fc77b81SRobert Mustacchi static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1300*5fc77b81SRobert Mustacchi u16 offset) 1301*5fc77b81SRobert Mustacchi { 1302*5fc77b81SRobert Mustacchi u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1303*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 1304*5fc77b81SRobert Mustacchi u16 i; 1305*5fc77b81SRobert Mustacchi 1306*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1307*5fc77b81SRobert Mustacchi 1308*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1309*5fc77b81SRobert Mustacchi data[i] = i; 1310*5fc77b81SRobert Mustacchi 1311*5fc77b81SRobert Mustacchi hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1312*5fc77b81SRobert Mustacchi status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1313*5fc77b81SRobert Mustacchi IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1314*5fc77b81SRobert Mustacchi hw->eeprom.word_page_size = 0; 1315*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) 1316*5fc77b81SRobert Mustacchi goto out; 1317*5fc77b81SRobert Mustacchi 1318*5fc77b81SRobert Mustacchi status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1319*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) 1320*5fc77b81SRobert Mustacchi goto out; 1321*5fc77b81SRobert Mustacchi 1322*5fc77b81SRobert Mustacchi /* 1323*5fc77b81SRobert Mustacchi * When writing in burst more than the actual page size 1324*5fc77b81SRobert Mustacchi * EEPROM address wraps around current page. 1325*5fc77b81SRobert Mustacchi */ 1326*5fc77b81SRobert Mustacchi hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1327*5fc77b81SRobert Mustacchi 1328*5fc77b81SRobert Mustacchi DEBUGOUT1("Detected EEPROM page size = %d words.", 1329*5fc77b81SRobert Mustacchi hw->eeprom.word_page_size); 1330*5fc77b81SRobert Mustacchi out: 1331*5fc77b81SRobert Mustacchi return status; 1332*5fc77b81SRobert Mustacchi } 1333*5fc77b81SRobert Mustacchi 1334*5fc77b81SRobert Mustacchi /** 1335*5fc77b81SRobert Mustacchi * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1336*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1337*5fc77b81SRobert Mustacchi * @offset: offset of word in the EEPROM to read 1338*5fc77b81SRobert Mustacchi * @data: word read from the EEPROM 1339*5fc77b81SRobert Mustacchi * 1340*5fc77b81SRobert Mustacchi * Reads a 16 bit word from the EEPROM using the EERD register. 1341*5fc77b81SRobert Mustacchi **/ 1342*5fc77b81SRobert Mustacchi s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1343*5fc77b81SRobert Mustacchi { 1344*5fc77b81SRobert Mustacchi return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1345*5fc77b81SRobert Mustacchi } 1346*5fc77b81SRobert Mustacchi 1347*5fc77b81SRobert Mustacchi /** 1348*5fc77b81SRobert Mustacchi * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1349*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1350*5fc77b81SRobert Mustacchi * @offset: offset of word in the EEPROM to write 1351*5fc77b81SRobert Mustacchi * @words: number of word(s) 1352*5fc77b81SRobert Mustacchi * @data: word(s) write to the EEPROM 1353*5fc77b81SRobert Mustacchi * 1354*5fc77b81SRobert Mustacchi * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1355*5fc77b81SRobert Mustacchi **/ 1356*5fc77b81SRobert Mustacchi s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1357*5fc77b81SRobert Mustacchi u16 words, u16 *data) 1358*5fc77b81SRobert Mustacchi { 1359*5fc77b81SRobert Mustacchi u32 eewr; 1360*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 1361*5fc77b81SRobert Mustacchi u16 i; 1362*5fc77b81SRobert Mustacchi 1363*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_write_eewr_generic"); 1364*5fc77b81SRobert Mustacchi 1365*5fc77b81SRobert Mustacchi hw->eeprom.ops.init_params(hw); 1366*5fc77b81SRobert Mustacchi 1367*5fc77b81SRobert Mustacchi if (words == 0) { 1368*5fc77b81SRobert Mustacchi status = IXGBE_ERR_INVALID_ARGUMENT; 1369*5fc77b81SRobert Mustacchi goto out; 1370*5fc77b81SRobert Mustacchi } 1371*5fc77b81SRobert Mustacchi 1372*5fc77b81SRobert Mustacchi if (offset >= hw->eeprom.word_size) { 1373*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1374*5fc77b81SRobert Mustacchi goto out; 1375*5fc77b81SRobert Mustacchi } 1376*5fc77b81SRobert Mustacchi 1377*5fc77b81SRobert Mustacchi for (i = 0; i < words; i++) { 1378*5fc77b81SRobert Mustacchi eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1379*5fc77b81SRobert Mustacchi (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1380*5fc77b81SRobert Mustacchi IXGBE_EEPROM_RW_REG_START; 1381*5fc77b81SRobert Mustacchi 1382*5fc77b81SRobert Mustacchi status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1383*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) { 1384*5fc77b81SRobert Mustacchi DEBUGOUT("Eeprom write EEWR timed out\n"); 1385*5fc77b81SRobert Mustacchi goto out; 1386*5fc77b81SRobert Mustacchi } 1387*5fc77b81SRobert Mustacchi 1388*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1389*5fc77b81SRobert Mustacchi 1390*5fc77b81SRobert Mustacchi status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1391*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) { 1392*5fc77b81SRobert Mustacchi DEBUGOUT("Eeprom write EEWR timed out\n"); 1393*5fc77b81SRobert Mustacchi goto out; 1394*5fc77b81SRobert Mustacchi } 1395*5fc77b81SRobert Mustacchi } 1396*5fc77b81SRobert Mustacchi 1397*5fc77b81SRobert Mustacchi out: 1398*5fc77b81SRobert Mustacchi return status; 1399*5fc77b81SRobert Mustacchi } 1400*5fc77b81SRobert Mustacchi 1401*5fc77b81SRobert Mustacchi /** 1402*5fc77b81SRobert Mustacchi * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1403*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1404*5fc77b81SRobert Mustacchi * @offset: offset of word in the EEPROM to write 1405*5fc77b81SRobert Mustacchi * @data: word write to the EEPROM 1406*5fc77b81SRobert Mustacchi * 1407*5fc77b81SRobert Mustacchi * Write a 16 bit word to the EEPROM using the EEWR register. 1408*5fc77b81SRobert Mustacchi **/ 1409*5fc77b81SRobert Mustacchi s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1410*5fc77b81SRobert Mustacchi { 1411*5fc77b81SRobert Mustacchi return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1412*5fc77b81SRobert Mustacchi } 1413*5fc77b81SRobert Mustacchi 1414*5fc77b81SRobert Mustacchi /** 1415*5fc77b81SRobert Mustacchi * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1416*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1417*5fc77b81SRobert Mustacchi * @ee_reg: EEPROM flag for polling 1418*5fc77b81SRobert Mustacchi * 1419*5fc77b81SRobert Mustacchi * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1420*5fc77b81SRobert Mustacchi * read or write is done respectively. 1421*5fc77b81SRobert Mustacchi **/ 1422*5fc77b81SRobert Mustacchi s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1423*5fc77b81SRobert Mustacchi { 1424*5fc77b81SRobert Mustacchi u32 i; 1425*5fc77b81SRobert Mustacchi u32 reg; 1426*5fc77b81SRobert Mustacchi s32 status = IXGBE_ERR_EEPROM; 1427*5fc77b81SRobert Mustacchi 1428*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1429*5fc77b81SRobert Mustacchi 1430*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1431*5fc77b81SRobert Mustacchi if (ee_reg == IXGBE_NVM_POLL_READ) 1432*5fc77b81SRobert Mustacchi reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1433*5fc77b81SRobert Mustacchi else 1434*5fc77b81SRobert Mustacchi reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1435*5fc77b81SRobert Mustacchi 1436*5fc77b81SRobert Mustacchi if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1437*5fc77b81SRobert Mustacchi status = IXGBE_SUCCESS; 1438*5fc77b81SRobert Mustacchi break; 1439*5fc77b81SRobert Mustacchi } 1440*5fc77b81SRobert Mustacchi usec_delay(5); 1441*5fc77b81SRobert Mustacchi } 1442*5fc77b81SRobert Mustacchi return status; 1443*5fc77b81SRobert Mustacchi } 1444*5fc77b81SRobert Mustacchi 1445*5fc77b81SRobert Mustacchi /** 1446*5fc77b81SRobert Mustacchi * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1447*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1448*5fc77b81SRobert Mustacchi * 1449*5fc77b81SRobert Mustacchi * Prepares EEPROM for access using bit-bang method. This function should 1450*5fc77b81SRobert Mustacchi * be called before issuing a command to the EEPROM. 1451*5fc77b81SRobert Mustacchi **/ 1452*5fc77b81SRobert Mustacchi static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1453*5fc77b81SRobert Mustacchi { 1454*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 1455*5fc77b81SRobert Mustacchi u32 eec; 1456*5fc77b81SRobert Mustacchi u32 i; 1457*5fc77b81SRobert Mustacchi 1458*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_acquire_eeprom"); 1459*5fc77b81SRobert Mustacchi 1460*5fc77b81SRobert Mustacchi if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1461*5fc77b81SRobert Mustacchi != IXGBE_SUCCESS) 1462*5fc77b81SRobert Mustacchi status = IXGBE_ERR_SWFW_SYNC; 1463*5fc77b81SRobert Mustacchi 1464*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1465*5fc77b81SRobert Mustacchi eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1466*5fc77b81SRobert Mustacchi 1467*5fc77b81SRobert Mustacchi /* Request EEPROM Access */ 1468*5fc77b81SRobert Mustacchi eec |= IXGBE_EEC_REQ; 1469*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1470*5fc77b81SRobert Mustacchi 1471*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1472*5fc77b81SRobert Mustacchi eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1473*5fc77b81SRobert Mustacchi if (eec & IXGBE_EEC_GNT) 1474*5fc77b81SRobert Mustacchi break; 1475*5fc77b81SRobert Mustacchi usec_delay(5); 1476*5fc77b81SRobert Mustacchi } 1477*5fc77b81SRobert Mustacchi 1478*5fc77b81SRobert Mustacchi /* Release if grant not acquired */ 1479*5fc77b81SRobert Mustacchi if (!(eec & IXGBE_EEC_GNT)) { 1480*5fc77b81SRobert Mustacchi eec &= ~IXGBE_EEC_REQ; 1481*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1482*5fc77b81SRobert Mustacchi DEBUGOUT("Could not acquire EEPROM grant\n"); 1483*5fc77b81SRobert Mustacchi 1484*5fc77b81SRobert Mustacchi hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1485*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1486*5fc77b81SRobert Mustacchi } 1487*5fc77b81SRobert Mustacchi 1488*5fc77b81SRobert Mustacchi /* Setup EEPROM for Read/Write */ 1489*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1490*5fc77b81SRobert Mustacchi /* Clear CS and SK */ 1491*5fc77b81SRobert Mustacchi eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1492*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1493*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 1494*5fc77b81SRobert Mustacchi usec_delay(1); 1495*5fc77b81SRobert Mustacchi } 1496*5fc77b81SRobert Mustacchi } 1497*5fc77b81SRobert Mustacchi return status; 1498*5fc77b81SRobert Mustacchi } 1499*5fc77b81SRobert Mustacchi 1500*5fc77b81SRobert Mustacchi /** 1501*5fc77b81SRobert Mustacchi * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1502*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1503*5fc77b81SRobert Mustacchi * 1504*5fc77b81SRobert Mustacchi * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1505*5fc77b81SRobert Mustacchi **/ 1506*5fc77b81SRobert Mustacchi static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1507*5fc77b81SRobert Mustacchi { 1508*5fc77b81SRobert Mustacchi s32 status = IXGBE_ERR_EEPROM; 1509*5fc77b81SRobert Mustacchi u32 timeout = 2000; 1510*5fc77b81SRobert Mustacchi u32 i; 1511*5fc77b81SRobert Mustacchi u32 swsm; 1512*5fc77b81SRobert Mustacchi 1513*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1514*5fc77b81SRobert Mustacchi 1515*5fc77b81SRobert Mustacchi 1516*5fc77b81SRobert Mustacchi /* Get SMBI software semaphore between device drivers first */ 1517*5fc77b81SRobert Mustacchi for (i = 0; i < timeout; i++) { 1518*5fc77b81SRobert Mustacchi /* 1519*5fc77b81SRobert Mustacchi * If the SMBI bit is 0 when we read it, then the bit will be 1520*5fc77b81SRobert Mustacchi * set and we have the semaphore 1521*5fc77b81SRobert Mustacchi */ 1522*5fc77b81SRobert Mustacchi swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1523*5fc77b81SRobert Mustacchi if (!(swsm & IXGBE_SWSM_SMBI)) { 1524*5fc77b81SRobert Mustacchi status = IXGBE_SUCCESS; 1525*5fc77b81SRobert Mustacchi break; 1526*5fc77b81SRobert Mustacchi } 1527*5fc77b81SRobert Mustacchi usec_delay(50); 1528*5fc77b81SRobert Mustacchi } 1529*5fc77b81SRobert Mustacchi 1530*5fc77b81SRobert Mustacchi if (i == timeout) { 1531*5fc77b81SRobert Mustacchi DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1532*5fc77b81SRobert Mustacchi "not granted.\n"); 1533*5fc77b81SRobert Mustacchi /* 1534*5fc77b81SRobert Mustacchi * this release is particularly important because our attempts 1535*5fc77b81SRobert Mustacchi * above to get the semaphore may have succeeded, and if there 1536*5fc77b81SRobert Mustacchi * was a timeout, we should unconditionally clear the semaphore 1537*5fc77b81SRobert Mustacchi * bits to free the driver to make progress 1538*5fc77b81SRobert Mustacchi */ 1539*5fc77b81SRobert Mustacchi ixgbe_release_eeprom_semaphore(hw); 1540*5fc77b81SRobert Mustacchi 1541*5fc77b81SRobert Mustacchi usec_delay(50); 1542*5fc77b81SRobert Mustacchi /* 1543*5fc77b81SRobert Mustacchi * one last try 1544*5fc77b81SRobert Mustacchi * If the SMBI bit is 0 when we read it, then the bit will be 1545*5fc77b81SRobert Mustacchi * set and we have the semaphore 1546*5fc77b81SRobert Mustacchi */ 1547*5fc77b81SRobert Mustacchi swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1548*5fc77b81SRobert Mustacchi if (!(swsm & IXGBE_SWSM_SMBI)) 1549*5fc77b81SRobert Mustacchi status = IXGBE_SUCCESS; 1550*5fc77b81SRobert Mustacchi } 1551*5fc77b81SRobert Mustacchi 1552*5fc77b81SRobert Mustacchi /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1553*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1554*5fc77b81SRobert Mustacchi for (i = 0; i < timeout; i++) { 1555*5fc77b81SRobert Mustacchi swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1556*5fc77b81SRobert Mustacchi 1557*5fc77b81SRobert Mustacchi /* Set the SW EEPROM semaphore bit to request access */ 1558*5fc77b81SRobert Mustacchi swsm |= IXGBE_SWSM_SWESMBI; 1559*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1560*5fc77b81SRobert Mustacchi 1561*5fc77b81SRobert Mustacchi /* 1562*5fc77b81SRobert Mustacchi * If we set the bit successfully then we got the 1563*5fc77b81SRobert Mustacchi * semaphore. 1564*5fc77b81SRobert Mustacchi */ 1565*5fc77b81SRobert Mustacchi swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1566*5fc77b81SRobert Mustacchi if (swsm & IXGBE_SWSM_SWESMBI) 1567*5fc77b81SRobert Mustacchi break; 1568*5fc77b81SRobert Mustacchi 1569*5fc77b81SRobert Mustacchi usec_delay(50); 1570*5fc77b81SRobert Mustacchi } 1571*5fc77b81SRobert Mustacchi 1572*5fc77b81SRobert Mustacchi /* 1573*5fc77b81SRobert Mustacchi * Release semaphores and return error if SW EEPROM semaphore 1574*5fc77b81SRobert Mustacchi * was not granted because we don't have access to the EEPROM 1575*5fc77b81SRobert Mustacchi */ 1576*5fc77b81SRobert Mustacchi if (i >= timeout) { 1577*5fc77b81SRobert Mustacchi DEBUGOUT("SWESMBI Software EEPROM semaphore " 1578*5fc77b81SRobert Mustacchi "not granted.\n"); 1579*5fc77b81SRobert Mustacchi ixgbe_release_eeprom_semaphore(hw); 1580*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1581*5fc77b81SRobert Mustacchi } 1582*5fc77b81SRobert Mustacchi } else { 1583*5fc77b81SRobert Mustacchi DEBUGOUT("Software semaphore SMBI between device drivers " 1584*5fc77b81SRobert Mustacchi "not granted.\n"); 1585*5fc77b81SRobert Mustacchi } 1586*5fc77b81SRobert Mustacchi 1587*5fc77b81SRobert Mustacchi return status; 1588*5fc77b81SRobert Mustacchi } 1589*5fc77b81SRobert Mustacchi 1590*5fc77b81SRobert Mustacchi /** 1591*5fc77b81SRobert Mustacchi * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1592*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1593*5fc77b81SRobert Mustacchi * 1594*5fc77b81SRobert Mustacchi * This function clears hardware semaphore bits. 1595*5fc77b81SRobert Mustacchi **/ 1596*5fc77b81SRobert Mustacchi static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1597*5fc77b81SRobert Mustacchi { 1598*5fc77b81SRobert Mustacchi u32 swsm; 1599*5fc77b81SRobert Mustacchi 1600*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1601*5fc77b81SRobert Mustacchi 1602*5fc77b81SRobert Mustacchi swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1603*5fc77b81SRobert Mustacchi 1604*5fc77b81SRobert Mustacchi /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1605*5fc77b81SRobert Mustacchi swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1606*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1607*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 1608*5fc77b81SRobert Mustacchi } 1609*5fc77b81SRobert Mustacchi 1610*5fc77b81SRobert Mustacchi /** 1611*5fc77b81SRobert Mustacchi * ixgbe_ready_eeprom - Polls for EEPROM ready 1612*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1613*5fc77b81SRobert Mustacchi **/ 1614*5fc77b81SRobert Mustacchi static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1615*5fc77b81SRobert Mustacchi { 1616*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 1617*5fc77b81SRobert Mustacchi u16 i; 1618*5fc77b81SRobert Mustacchi u8 spi_stat_reg; 1619*5fc77b81SRobert Mustacchi 1620*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_ready_eeprom"); 1621*5fc77b81SRobert Mustacchi 1622*5fc77b81SRobert Mustacchi /* 1623*5fc77b81SRobert Mustacchi * Read "Status Register" repeatedly until the LSB is cleared. The 1624*5fc77b81SRobert Mustacchi * EEPROM will signal that the command has been completed by clearing 1625*5fc77b81SRobert Mustacchi * bit 0 of the internal status register. If it's not cleared within 1626*5fc77b81SRobert Mustacchi * 5 milliseconds, then error out. 1627*5fc77b81SRobert Mustacchi */ 1628*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1629*5fc77b81SRobert Mustacchi ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1630*5fc77b81SRobert Mustacchi IXGBE_EEPROM_OPCODE_BITS); 1631*5fc77b81SRobert Mustacchi spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1632*5fc77b81SRobert Mustacchi if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1633*5fc77b81SRobert Mustacchi break; 1634*5fc77b81SRobert Mustacchi 1635*5fc77b81SRobert Mustacchi usec_delay(5); 1636*5fc77b81SRobert Mustacchi ixgbe_standby_eeprom(hw); 1637*5fc77b81SRobert Mustacchi }; 1638*5fc77b81SRobert Mustacchi 1639*5fc77b81SRobert Mustacchi /* 1640*5fc77b81SRobert Mustacchi * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1641*5fc77b81SRobert Mustacchi * devices (and only 0-5mSec on 5V devices) 1642*5fc77b81SRobert Mustacchi */ 1643*5fc77b81SRobert Mustacchi if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1644*5fc77b81SRobert Mustacchi DEBUGOUT("SPI EEPROM Status error\n"); 1645*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM; 1646*5fc77b81SRobert Mustacchi } 1647*5fc77b81SRobert Mustacchi 1648*5fc77b81SRobert Mustacchi return status; 1649*5fc77b81SRobert Mustacchi } 1650*5fc77b81SRobert Mustacchi 1651*5fc77b81SRobert Mustacchi /** 1652*5fc77b81SRobert Mustacchi * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1653*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1654*5fc77b81SRobert Mustacchi **/ 1655*5fc77b81SRobert Mustacchi static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1656*5fc77b81SRobert Mustacchi { 1657*5fc77b81SRobert Mustacchi u32 eec; 1658*5fc77b81SRobert Mustacchi 1659*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_standby_eeprom"); 1660*5fc77b81SRobert Mustacchi 1661*5fc77b81SRobert Mustacchi eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1662*5fc77b81SRobert Mustacchi 1663*5fc77b81SRobert Mustacchi /* Toggle CS to flush commands */ 1664*5fc77b81SRobert Mustacchi eec |= IXGBE_EEC_CS; 1665*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1666*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 1667*5fc77b81SRobert Mustacchi usec_delay(1); 1668*5fc77b81SRobert Mustacchi eec &= ~IXGBE_EEC_CS; 1669*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1670*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 1671*5fc77b81SRobert Mustacchi usec_delay(1); 1672*5fc77b81SRobert Mustacchi } 1673*5fc77b81SRobert Mustacchi 1674*5fc77b81SRobert Mustacchi /** 1675*5fc77b81SRobert Mustacchi * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1676*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1677*5fc77b81SRobert Mustacchi * @data: data to send to the EEPROM 1678*5fc77b81SRobert Mustacchi * @count: number of bits to shift out 1679*5fc77b81SRobert Mustacchi **/ 1680*5fc77b81SRobert Mustacchi static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1681*5fc77b81SRobert Mustacchi u16 count) 1682*5fc77b81SRobert Mustacchi { 1683*5fc77b81SRobert Mustacchi u32 eec; 1684*5fc77b81SRobert Mustacchi u32 mask; 1685*5fc77b81SRobert Mustacchi u32 i; 1686*5fc77b81SRobert Mustacchi 1687*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 1688*5fc77b81SRobert Mustacchi 1689*5fc77b81SRobert Mustacchi eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1690*5fc77b81SRobert Mustacchi 1691*5fc77b81SRobert Mustacchi /* 1692*5fc77b81SRobert Mustacchi * Mask is used to shift "count" bits of "data" out to the EEPROM 1693*5fc77b81SRobert Mustacchi * one bit at a time. Determine the starting bit based on count 1694*5fc77b81SRobert Mustacchi */ 1695*5fc77b81SRobert Mustacchi mask = 0x01 << (count - 1); 1696*5fc77b81SRobert Mustacchi 1697*5fc77b81SRobert Mustacchi for (i = 0; i < count; i++) { 1698*5fc77b81SRobert Mustacchi /* 1699*5fc77b81SRobert Mustacchi * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1700*5fc77b81SRobert Mustacchi * "1", and then raising and then lowering the clock (the SK 1701*5fc77b81SRobert Mustacchi * bit controls the clock input to the EEPROM). A "0" is 1702*5fc77b81SRobert Mustacchi * shifted out to the EEPROM by setting "DI" to "0" and then 1703*5fc77b81SRobert Mustacchi * raising and then lowering the clock. 1704*5fc77b81SRobert Mustacchi */ 1705*5fc77b81SRobert Mustacchi if (data & mask) 1706*5fc77b81SRobert Mustacchi eec |= IXGBE_EEC_DI; 1707*5fc77b81SRobert Mustacchi else 1708*5fc77b81SRobert Mustacchi eec &= ~IXGBE_EEC_DI; 1709*5fc77b81SRobert Mustacchi 1710*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1711*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 1712*5fc77b81SRobert Mustacchi 1713*5fc77b81SRobert Mustacchi usec_delay(1); 1714*5fc77b81SRobert Mustacchi 1715*5fc77b81SRobert Mustacchi ixgbe_raise_eeprom_clk(hw, &eec); 1716*5fc77b81SRobert Mustacchi ixgbe_lower_eeprom_clk(hw, &eec); 1717*5fc77b81SRobert Mustacchi 1718*5fc77b81SRobert Mustacchi /* 1719*5fc77b81SRobert Mustacchi * Shift mask to signify next bit of data to shift in to the 1720*5fc77b81SRobert Mustacchi * EEPROM 1721*5fc77b81SRobert Mustacchi */ 1722*5fc77b81SRobert Mustacchi mask = mask >> 1; 1723*5fc77b81SRobert Mustacchi }; 1724*5fc77b81SRobert Mustacchi 1725*5fc77b81SRobert Mustacchi /* We leave the "DI" bit set to "0" when we leave this routine. */ 1726*5fc77b81SRobert Mustacchi eec &= ~IXGBE_EEC_DI; 1727*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1728*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 1729*5fc77b81SRobert Mustacchi } 1730*5fc77b81SRobert Mustacchi 1731*5fc77b81SRobert Mustacchi /** 1732*5fc77b81SRobert Mustacchi * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1733*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1734*5fc77b81SRobert Mustacchi **/ 1735*5fc77b81SRobert Mustacchi static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1736*5fc77b81SRobert Mustacchi { 1737*5fc77b81SRobert Mustacchi u32 eec; 1738*5fc77b81SRobert Mustacchi u32 i; 1739*5fc77b81SRobert Mustacchi u16 data = 0; 1740*5fc77b81SRobert Mustacchi 1741*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 1742*5fc77b81SRobert Mustacchi 1743*5fc77b81SRobert Mustacchi /* 1744*5fc77b81SRobert Mustacchi * In order to read a register from the EEPROM, we need to shift 1745*5fc77b81SRobert Mustacchi * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1746*5fc77b81SRobert Mustacchi * the clock input to the EEPROM (setting the SK bit), and then reading 1747*5fc77b81SRobert Mustacchi * the value of the "DO" bit. During this "shifting in" process the 1748*5fc77b81SRobert Mustacchi * "DI" bit should always be clear. 1749*5fc77b81SRobert Mustacchi */ 1750*5fc77b81SRobert Mustacchi eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1751*5fc77b81SRobert Mustacchi 1752*5fc77b81SRobert Mustacchi eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1753*5fc77b81SRobert Mustacchi 1754*5fc77b81SRobert Mustacchi for (i = 0; i < count; i++) { 1755*5fc77b81SRobert Mustacchi data = data << 1; 1756*5fc77b81SRobert Mustacchi ixgbe_raise_eeprom_clk(hw, &eec); 1757*5fc77b81SRobert Mustacchi 1758*5fc77b81SRobert Mustacchi eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1759*5fc77b81SRobert Mustacchi 1760*5fc77b81SRobert Mustacchi eec &= ~(IXGBE_EEC_DI); 1761*5fc77b81SRobert Mustacchi if (eec & IXGBE_EEC_DO) 1762*5fc77b81SRobert Mustacchi data |= 1; 1763*5fc77b81SRobert Mustacchi 1764*5fc77b81SRobert Mustacchi ixgbe_lower_eeprom_clk(hw, &eec); 1765*5fc77b81SRobert Mustacchi } 1766*5fc77b81SRobert Mustacchi 1767*5fc77b81SRobert Mustacchi return data; 1768*5fc77b81SRobert Mustacchi } 1769*5fc77b81SRobert Mustacchi 1770*5fc77b81SRobert Mustacchi /** 1771*5fc77b81SRobert Mustacchi * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1772*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1773*5fc77b81SRobert Mustacchi * @eec: EEC register's current value 1774*5fc77b81SRobert Mustacchi **/ 1775*5fc77b81SRobert Mustacchi static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1776*5fc77b81SRobert Mustacchi { 1777*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_raise_eeprom_clk"); 1778*5fc77b81SRobert Mustacchi 1779*5fc77b81SRobert Mustacchi /* 1780*5fc77b81SRobert Mustacchi * Raise the clock input to the EEPROM 1781*5fc77b81SRobert Mustacchi * (setting the SK bit), then delay 1782*5fc77b81SRobert Mustacchi */ 1783*5fc77b81SRobert Mustacchi *eec = *eec | IXGBE_EEC_SK; 1784*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1785*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 1786*5fc77b81SRobert Mustacchi usec_delay(1); 1787*5fc77b81SRobert Mustacchi } 1788*5fc77b81SRobert Mustacchi 1789*5fc77b81SRobert Mustacchi /** 1790*5fc77b81SRobert Mustacchi * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1791*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1792*5fc77b81SRobert Mustacchi * @eecd: EECD's current value 1793*5fc77b81SRobert Mustacchi **/ 1794*5fc77b81SRobert Mustacchi static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1795*5fc77b81SRobert Mustacchi { 1796*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_lower_eeprom_clk"); 1797*5fc77b81SRobert Mustacchi 1798*5fc77b81SRobert Mustacchi /* 1799*5fc77b81SRobert Mustacchi * Lower the clock input to the EEPROM (clearing the SK bit), then 1800*5fc77b81SRobert Mustacchi * delay 1801*5fc77b81SRobert Mustacchi */ 1802*5fc77b81SRobert Mustacchi *eec = *eec & ~IXGBE_EEC_SK; 1803*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1804*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 1805*5fc77b81SRobert Mustacchi usec_delay(1); 1806*5fc77b81SRobert Mustacchi } 1807*5fc77b81SRobert Mustacchi 1808*5fc77b81SRobert Mustacchi /** 1809*5fc77b81SRobert Mustacchi * ixgbe_release_eeprom - Release EEPROM, release semaphores 1810*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1811*5fc77b81SRobert Mustacchi **/ 1812*5fc77b81SRobert Mustacchi static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1813*5fc77b81SRobert Mustacchi { 1814*5fc77b81SRobert Mustacchi u32 eec; 1815*5fc77b81SRobert Mustacchi 1816*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_release_eeprom"); 1817*5fc77b81SRobert Mustacchi 1818*5fc77b81SRobert Mustacchi eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1819*5fc77b81SRobert Mustacchi 1820*5fc77b81SRobert Mustacchi eec |= IXGBE_EEC_CS; /* Pull CS high */ 1821*5fc77b81SRobert Mustacchi eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1822*5fc77b81SRobert Mustacchi 1823*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1824*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 1825*5fc77b81SRobert Mustacchi 1826*5fc77b81SRobert Mustacchi usec_delay(1); 1827*5fc77b81SRobert Mustacchi 1828*5fc77b81SRobert Mustacchi /* Stop requesting EEPROM access */ 1829*5fc77b81SRobert Mustacchi eec &= ~IXGBE_EEC_REQ; 1830*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1831*5fc77b81SRobert Mustacchi 1832*5fc77b81SRobert Mustacchi hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1833*5fc77b81SRobert Mustacchi 1834*5fc77b81SRobert Mustacchi /* Delay before attempt to obtain semaphore again to allow FW access */ 1835*5fc77b81SRobert Mustacchi msec_delay(hw->eeprom.semaphore_delay); 1836*5fc77b81SRobert Mustacchi } 1837*5fc77b81SRobert Mustacchi 1838*5fc77b81SRobert Mustacchi /** 1839*5fc77b81SRobert Mustacchi * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1840*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1841*5fc77b81SRobert Mustacchi **/ 1842*5fc77b81SRobert Mustacchi u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1843*5fc77b81SRobert Mustacchi { 1844*5fc77b81SRobert Mustacchi u16 i; 1845*5fc77b81SRobert Mustacchi u16 j; 1846*5fc77b81SRobert Mustacchi u16 checksum = 0; 1847*5fc77b81SRobert Mustacchi u16 length = 0; 1848*5fc77b81SRobert Mustacchi u16 pointer = 0; 1849*5fc77b81SRobert Mustacchi u16 word = 0; 1850*5fc77b81SRobert Mustacchi 1851*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 1852*5fc77b81SRobert Mustacchi 1853*5fc77b81SRobert Mustacchi /* Include 0x0-0x3F in the checksum */ 1854*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1855*5fc77b81SRobert Mustacchi if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1856*5fc77b81SRobert Mustacchi DEBUGOUT("EEPROM read failed\n"); 1857*5fc77b81SRobert Mustacchi break; 1858*5fc77b81SRobert Mustacchi } 1859*5fc77b81SRobert Mustacchi checksum += word; 1860*5fc77b81SRobert Mustacchi } 1861*5fc77b81SRobert Mustacchi 1862*5fc77b81SRobert Mustacchi /* Include all data from pointers except for the fw pointer */ 1863*5fc77b81SRobert Mustacchi for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1864*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, i, &pointer); 1865*5fc77b81SRobert Mustacchi 1866*5fc77b81SRobert Mustacchi /* Make sure the pointer seems valid */ 1867*5fc77b81SRobert Mustacchi if (pointer != 0xFFFF && pointer != 0) { 1868*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, pointer, &length); 1869*5fc77b81SRobert Mustacchi 1870*5fc77b81SRobert Mustacchi if (length != 0xFFFF && length != 0) { 1871*5fc77b81SRobert Mustacchi for (j = pointer+1; j <= pointer+length; j++) { 1872*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, j, &word); 1873*5fc77b81SRobert Mustacchi checksum += word; 1874*5fc77b81SRobert Mustacchi } 1875*5fc77b81SRobert Mustacchi } 1876*5fc77b81SRobert Mustacchi } 1877*5fc77b81SRobert Mustacchi } 1878*5fc77b81SRobert Mustacchi 1879*5fc77b81SRobert Mustacchi checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1880*5fc77b81SRobert Mustacchi 1881*5fc77b81SRobert Mustacchi return checksum; 1882*5fc77b81SRobert Mustacchi } 1883*5fc77b81SRobert Mustacchi 1884*5fc77b81SRobert Mustacchi /** 1885*5fc77b81SRobert Mustacchi * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1886*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1887*5fc77b81SRobert Mustacchi * @checksum_val: calculated checksum 1888*5fc77b81SRobert Mustacchi * 1889*5fc77b81SRobert Mustacchi * Performs checksum calculation and validates the EEPROM checksum. If the 1890*5fc77b81SRobert Mustacchi * caller does not need checksum_val, the value can be NULL. 1891*5fc77b81SRobert Mustacchi **/ 1892*5fc77b81SRobert Mustacchi s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1893*5fc77b81SRobert Mustacchi u16 *checksum_val) 1894*5fc77b81SRobert Mustacchi { 1895*5fc77b81SRobert Mustacchi s32 status; 1896*5fc77b81SRobert Mustacchi u16 checksum; 1897*5fc77b81SRobert Mustacchi u16 read_checksum = 0; 1898*5fc77b81SRobert Mustacchi 1899*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 1900*5fc77b81SRobert Mustacchi 1901*5fc77b81SRobert Mustacchi /* 1902*5fc77b81SRobert Mustacchi * Read the first word from the EEPROM. If this times out or fails, do 1903*5fc77b81SRobert Mustacchi * not continue or we could be in for a very long wait while every 1904*5fc77b81SRobert Mustacchi * EEPROM read fails 1905*5fc77b81SRobert Mustacchi */ 1906*5fc77b81SRobert Mustacchi status = hw->eeprom.ops.read(hw, 0, &checksum); 1907*5fc77b81SRobert Mustacchi 1908*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1909*5fc77b81SRobert Mustacchi checksum = hw->eeprom.ops.calc_checksum(hw); 1910*5fc77b81SRobert Mustacchi 1911*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1912*5fc77b81SRobert Mustacchi 1913*5fc77b81SRobert Mustacchi /* 1914*5fc77b81SRobert Mustacchi * Verify read checksum from EEPROM is the same as 1915*5fc77b81SRobert Mustacchi * calculated checksum 1916*5fc77b81SRobert Mustacchi */ 1917*5fc77b81SRobert Mustacchi if (read_checksum != checksum) 1918*5fc77b81SRobert Mustacchi status = IXGBE_ERR_EEPROM_CHECKSUM; 1919*5fc77b81SRobert Mustacchi 1920*5fc77b81SRobert Mustacchi /* If the user cares, return the calculated checksum */ 1921*5fc77b81SRobert Mustacchi if (checksum_val) 1922*5fc77b81SRobert Mustacchi *checksum_val = checksum; 1923*5fc77b81SRobert Mustacchi } else { 1924*5fc77b81SRobert Mustacchi DEBUGOUT("EEPROM read failed\n"); 1925*5fc77b81SRobert Mustacchi } 1926*5fc77b81SRobert Mustacchi 1927*5fc77b81SRobert Mustacchi return status; 1928*5fc77b81SRobert Mustacchi } 1929*5fc77b81SRobert Mustacchi 1930*5fc77b81SRobert Mustacchi /** 1931*5fc77b81SRobert Mustacchi * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1932*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1933*5fc77b81SRobert Mustacchi **/ 1934*5fc77b81SRobert Mustacchi s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1935*5fc77b81SRobert Mustacchi { 1936*5fc77b81SRobert Mustacchi s32 status; 1937*5fc77b81SRobert Mustacchi u16 checksum; 1938*5fc77b81SRobert Mustacchi 1939*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 1940*5fc77b81SRobert Mustacchi 1941*5fc77b81SRobert Mustacchi /* 1942*5fc77b81SRobert Mustacchi * Read the first word from the EEPROM. If this times out or fails, do 1943*5fc77b81SRobert Mustacchi * not continue or we could be in for a very long wait while every 1944*5fc77b81SRobert Mustacchi * EEPROM read fails 1945*5fc77b81SRobert Mustacchi */ 1946*5fc77b81SRobert Mustacchi status = hw->eeprom.ops.read(hw, 0, &checksum); 1947*5fc77b81SRobert Mustacchi 1948*5fc77b81SRobert Mustacchi if (status == IXGBE_SUCCESS) { 1949*5fc77b81SRobert Mustacchi checksum = hw->eeprom.ops.calc_checksum(hw); 1950*5fc77b81SRobert Mustacchi status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1951*5fc77b81SRobert Mustacchi checksum); 1952*5fc77b81SRobert Mustacchi } else { 1953*5fc77b81SRobert Mustacchi DEBUGOUT("EEPROM read failed\n"); 1954*5fc77b81SRobert Mustacchi } 1955*5fc77b81SRobert Mustacchi 1956*5fc77b81SRobert Mustacchi return status; 1957*5fc77b81SRobert Mustacchi } 1958*5fc77b81SRobert Mustacchi 1959*5fc77b81SRobert Mustacchi /** 1960*5fc77b81SRobert Mustacchi * ixgbe_validate_mac_addr - Validate MAC address 1961*5fc77b81SRobert Mustacchi * @mac_addr: pointer to MAC address. 1962*5fc77b81SRobert Mustacchi * 1963*5fc77b81SRobert Mustacchi * Tests a MAC address to ensure it is a valid Individual Address 1964*5fc77b81SRobert Mustacchi **/ 1965*5fc77b81SRobert Mustacchi s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1966*5fc77b81SRobert Mustacchi { 1967*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 1968*5fc77b81SRobert Mustacchi 1969*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_validate_mac_addr"); 1970*5fc77b81SRobert Mustacchi 1971*5fc77b81SRobert Mustacchi /* Make sure it is not a multicast address */ 1972*5fc77b81SRobert Mustacchi if (IXGBE_IS_MULTICAST(mac_addr)) { 1973*5fc77b81SRobert Mustacchi DEBUGOUT("MAC address is multicast\n"); 1974*5fc77b81SRobert Mustacchi status = IXGBE_ERR_INVALID_MAC_ADDR; 1975*5fc77b81SRobert Mustacchi /* Not a broadcast address */ 1976*5fc77b81SRobert Mustacchi } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1977*5fc77b81SRobert Mustacchi DEBUGOUT("MAC address is broadcast\n"); 1978*5fc77b81SRobert Mustacchi status = IXGBE_ERR_INVALID_MAC_ADDR; 1979*5fc77b81SRobert Mustacchi /* Reject the zero address */ 1980*5fc77b81SRobert Mustacchi } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1981*5fc77b81SRobert Mustacchi mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1982*5fc77b81SRobert Mustacchi DEBUGOUT("MAC address is all zeros\n"); 1983*5fc77b81SRobert Mustacchi status = IXGBE_ERR_INVALID_MAC_ADDR; 1984*5fc77b81SRobert Mustacchi } 1985*5fc77b81SRobert Mustacchi return status; 1986*5fc77b81SRobert Mustacchi } 1987*5fc77b81SRobert Mustacchi 1988*5fc77b81SRobert Mustacchi /** 1989*5fc77b81SRobert Mustacchi * ixgbe_set_rar_generic - Set Rx address register 1990*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 1991*5fc77b81SRobert Mustacchi * @index: Receive address register to write 1992*5fc77b81SRobert Mustacchi * @addr: Address to put into receive address register 1993*5fc77b81SRobert Mustacchi * @vmdq: VMDq "set" or "pool" index 1994*5fc77b81SRobert Mustacchi * @enable_addr: set flag that address is active 1995*5fc77b81SRobert Mustacchi * 1996*5fc77b81SRobert Mustacchi * Puts an ethernet address into a receive address register. 1997*5fc77b81SRobert Mustacchi **/ 1998*5fc77b81SRobert Mustacchi s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1999*5fc77b81SRobert Mustacchi u32 enable_addr) 2000*5fc77b81SRobert Mustacchi { 2001*5fc77b81SRobert Mustacchi u32 rar_low, rar_high; 2002*5fc77b81SRobert Mustacchi u32 rar_entries = hw->mac.num_rar_entries; 2003*5fc77b81SRobert Mustacchi 2004*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_set_rar_generic"); 2005*5fc77b81SRobert Mustacchi 2006*5fc77b81SRobert Mustacchi /* Make sure we are using a valid rar index range */ 2007*5fc77b81SRobert Mustacchi if (index >= rar_entries) { 2008*5fc77b81SRobert Mustacchi DEBUGOUT1("RAR index %d is out of range.\n", index); 2009*5fc77b81SRobert Mustacchi return IXGBE_ERR_INVALID_ARGUMENT; 2010*5fc77b81SRobert Mustacchi } 2011*5fc77b81SRobert Mustacchi 2012*5fc77b81SRobert Mustacchi /* setup VMDq pool selection before this RAR gets enabled */ 2013*5fc77b81SRobert Mustacchi hw->mac.ops.set_vmdq(hw, index, vmdq); 2014*5fc77b81SRobert Mustacchi 2015*5fc77b81SRobert Mustacchi /* 2016*5fc77b81SRobert Mustacchi * HW expects these in little endian so we reverse the byte 2017*5fc77b81SRobert Mustacchi * order from network order (big endian) to little endian 2018*5fc77b81SRobert Mustacchi */ 2019*5fc77b81SRobert Mustacchi rar_low = ((u32)addr[0] | 2020*5fc77b81SRobert Mustacchi ((u32)addr[1] << 8) | 2021*5fc77b81SRobert Mustacchi ((u32)addr[2] << 16) | 2022*5fc77b81SRobert Mustacchi ((u32)addr[3] << 24)); 2023*5fc77b81SRobert Mustacchi /* 2024*5fc77b81SRobert Mustacchi * Some parts put the VMDq setting in the extra RAH bits, 2025*5fc77b81SRobert Mustacchi * so save everything except the lower 16 bits that hold part 2026*5fc77b81SRobert Mustacchi * of the address and the address valid bit. 2027*5fc77b81SRobert Mustacchi */ 2028*5fc77b81SRobert Mustacchi rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2029*5fc77b81SRobert Mustacchi rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2030*5fc77b81SRobert Mustacchi rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2031*5fc77b81SRobert Mustacchi 2032*5fc77b81SRobert Mustacchi if (enable_addr != 0) 2033*5fc77b81SRobert Mustacchi rar_high |= IXGBE_RAH_AV; 2034*5fc77b81SRobert Mustacchi 2035*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2036*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2037*5fc77b81SRobert Mustacchi 2038*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2039*5fc77b81SRobert Mustacchi } 2040*5fc77b81SRobert Mustacchi 2041*5fc77b81SRobert Mustacchi /** 2042*5fc77b81SRobert Mustacchi * ixgbe_clear_rar_generic - Remove Rx address register 2043*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2044*5fc77b81SRobert Mustacchi * @index: Receive address register to write 2045*5fc77b81SRobert Mustacchi * 2046*5fc77b81SRobert Mustacchi * Clears an ethernet address from a receive address register. 2047*5fc77b81SRobert Mustacchi **/ 2048*5fc77b81SRobert Mustacchi s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2049*5fc77b81SRobert Mustacchi { 2050*5fc77b81SRobert Mustacchi u32 rar_high; 2051*5fc77b81SRobert Mustacchi u32 rar_entries = hw->mac.num_rar_entries; 2052*5fc77b81SRobert Mustacchi 2053*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_clear_rar_generic"); 2054*5fc77b81SRobert Mustacchi 2055*5fc77b81SRobert Mustacchi /* Make sure we are using a valid rar index range */ 2056*5fc77b81SRobert Mustacchi if (index >= rar_entries) { 2057*5fc77b81SRobert Mustacchi DEBUGOUT1("RAR index %d is out of range.\n", index); 2058*5fc77b81SRobert Mustacchi return IXGBE_ERR_INVALID_ARGUMENT; 2059*5fc77b81SRobert Mustacchi } 2060*5fc77b81SRobert Mustacchi 2061*5fc77b81SRobert Mustacchi /* 2062*5fc77b81SRobert Mustacchi * Some parts put the VMDq setting in the extra RAH bits, 2063*5fc77b81SRobert Mustacchi * so save everything except the lower 16 bits that hold part 2064*5fc77b81SRobert Mustacchi * of the address and the address valid bit. 2065*5fc77b81SRobert Mustacchi */ 2066*5fc77b81SRobert Mustacchi rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2067*5fc77b81SRobert Mustacchi rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2068*5fc77b81SRobert Mustacchi 2069*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2070*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2071*5fc77b81SRobert Mustacchi 2072*5fc77b81SRobert Mustacchi /* clear VMDq pool/queue selection for this RAR */ 2073*5fc77b81SRobert Mustacchi hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2074*5fc77b81SRobert Mustacchi 2075*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2076*5fc77b81SRobert Mustacchi } 2077*5fc77b81SRobert Mustacchi 2078*5fc77b81SRobert Mustacchi /** 2079*5fc77b81SRobert Mustacchi * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2080*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2081*5fc77b81SRobert Mustacchi * 2082*5fc77b81SRobert Mustacchi * Places the MAC address in receive address register 0 and clears the rest 2083*5fc77b81SRobert Mustacchi * of the receive address registers. Clears the multicast table. Assumes 2084*5fc77b81SRobert Mustacchi * the receiver is in reset when the routine is called. 2085*5fc77b81SRobert Mustacchi **/ 2086*5fc77b81SRobert Mustacchi s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2087*5fc77b81SRobert Mustacchi { 2088*5fc77b81SRobert Mustacchi u32 i; 2089*5fc77b81SRobert Mustacchi u32 rar_entries = hw->mac.num_rar_entries; 2090*5fc77b81SRobert Mustacchi 2091*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2092*5fc77b81SRobert Mustacchi 2093*5fc77b81SRobert Mustacchi /* 2094*5fc77b81SRobert Mustacchi * If the current mac address is valid, assume it is a software override 2095*5fc77b81SRobert Mustacchi * to the permanent address. 2096*5fc77b81SRobert Mustacchi * Otherwise, use the permanent address from the eeprom. 2097*5fc77b81SRobert Mustacchi */ 2098*5fc77b81SRobert Mustacchi if (ixgbe_validate_mac_addr(hw->mac.addr) == 2099*5fc77b81SRobert Mustacchi IXGBE_ERR_INVALID_MAC_ADDR) { 2100*5fc77b81SRobert Mustacchi /* Get the MAC address from the RAR0 for later reference */ 2101*5fc77b81SRobert Mustacchi hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2102*5fc77b81SRobert Mustacchi 2103*5fc77b81SRobert Mustacchi DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2104*5fc77b81SRobert Mustacchi hw->mac.addr[0], hw->mac.addr[1], 2105*5fc77b81SRobert Mustacchi hw->mac.addr[2]); 2106*5fc77b81SRobert Mustacchi DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2107*5fc77b81SRobert Mustacchi hw->mac.addr[4], hw->mac.addr[5]); 2108*5fc77b81SRobert Mustacchi } else { 2109*5fc77b81SRobert Mustacchi /* Setup the receive address. */ 2110*5fc77b81SRobert Mustacchi DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2111*5fc77b81SRobert Mustacchi DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2112*5fc77b81SRobert Mustacchi hw->mac.addr[0], hw->mac.addr[1], 2113*5fc77b81SRobert Mustacchi hw->mac.addr[2]); 2114*5fc77b81SRobert Mustacchi DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2115*5fc77b81SRobert Mustacchi hw->mac.addr[4], hw->mac.addr[5]); 2116*5fc77b81SRobert Mustacchi 2117*5fc77b81SRobert Mustacchi hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2118*5fc77b81SRobert Mustacchi 2119*5fc77b81SRobert Mustacchi /* clear VMDq pool/queue selection for RAR 0 */ 2120*5fc77b81SRobert Mustacchi hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2121*5fc77b81SRobert Mustacchi } 2122*5fc77b81SRobert Mustacchi hw->addr_ctrl.overflow_promisc = 0; 2123*5fc77b81SRobert Mustacchi 2124*5fc77b81SRobert Mustacchi hw->addr_ctrl.rar_used_count = 1; 2125*5fc77b81SRobert Mustacchi 2126*5fc77b81SRobert Mustacchi /* Zero out the other receive addresses. */ 2127*5fc77b81SRobert Mustacchi DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2128*5fc77b81SRobert Mustacchi for (i = 1; i < rar_entries; i++) { 2129*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2130*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2131*5fc77b81SRobert Mustacchi } 2132*5fc77b81SRobert Mustacchi 2133*5fc77b81SRobert Mustacchi /* Clear the MTA */ 2134*5fc77b81SRobert Mustacchi hw->addr_ctrl.mta_in_use = 0; 2135*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2136*5fc77b81SRobert Mustacchi 2137*5fc77b81SRobert Mustacchi DEBUGOUT(" Clearing MTA\n"); 2138*5fc77b81SRobert Mustacchi for (i = 0; i < hw->mac.mcft_size; i++) 2139*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2140*5fc77b81SRobert Mustacchi 2141*5fc77b81SRobert Mustacchi /* Should always be IXGBE_SUCCESS. */ 2142*5fc77b81SRobert Mustacchi return ixgbe_init_uta_tables(hw); 2143*5fc77b81SRobert Mustacchi } 2144*5fc77b81SRobert Mustacchi 2145*5fc77b81SRobert Mustacchi /** 2146*5fc77b81SRobert Mustacchi * ixgbe_add_uc_addr - Adds a secondary unicast address. 2147*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2148*5fc77b81SRobert Mustacchi * @addr: new address 2149*5fc77b81SRobert Mustacchi * 2150*5fc77b81SRobert Mustacchi * Adds it to unused receive address register or goes into promiscuous mode. 2151*5fc77b81SRobert Mustacchi **/ 2152*5fc77b81SRobert Mustacchi void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2153*5fc77b81SRobert Mustacchi { 2154*5fc77b81SRobert Mustacchi u32 rar_entries = hw->mac.num_rar_entries; 2155*5fc77b81SRobert Mustacchi u32 rar; 2156*5fc77b81SRobert Mustacchi 2157*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_add_uc_addr"); 2158*5fc77b81SRobert Mustacchi 2159*5fc77b81SRobert Mustacchi DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2160*5fc77b81SRobert Mustacchi addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2161*5fc77b81SRobert Mustacchi 2162*5fc77b81SRobert Mustacchi /* 2163*5fc77b81SRobert Mustacchi * Place this address in the RAR if there is room, 2164*5fc77b81SRobert Mustacchi * else put the controller into promiscuous mode 2165*5fc77b81SRobert Mustacchi */ 2166*5fc77b81SRobert Mustacchi if (hw->addr_ctrl.rar_used_count < rar_entries) { 2167*5fc77b81SRobert Mustacchi rar = hw->addr_ctrl.rar_used_count; 2168*5fc77b81SRobert Mustacchi hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2169*5fc77b81SRobert Mustacchi DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2170*5fc77b81SRobert Mustacchi hw->addr_ctrl.rar_used_count++; 2171*5fc77b81SRobert Mustacchi } else { 2172*5fc77b81SRobert Mustacchi hw->addr_ctrl.overflow_promisc++; 2173*5fc77b81SRobert Mustacchi } 2174*5fc77b81SRobert Mustacchi 2175*5fc77b81SRobert Mustacchi DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2176*5fc77b81SRobert Mustacchi } 2177*5fc77b81SRobert Mustacchi 2178*5fc77b81SRobert Mustacchi /** 2179*5fc77b81SRobert Mustacchi * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2180*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2181*5fc77b81SRobert Mustacchi * @addr_list: the list of new addresses 2182*5fc77b81SRobert Mustacchi * @addr_count: number of addresses 2183*5fc77b81SRobert Mustacchi * @next: iterator function to walk the address list 2184*5fc77b81SRobert Mustacchi * 2185*5fc77b81SRobert Mustacchi * The given list replaces any existing list. Clears the secondary addrs from 2186*5fc77b81SRobert Mustacchi * receive address registers. Uses unused receive address registers for the 2187*5fc77b81SRobert Mustacchi * first secondary addresses, and falls back to promiscuous mode as needed. 2188*5fc77b81SRobert Mustacchi * 2189*5fc77b81SRobert Mustacchi * Drivers using secondary unicast addresses must set user_set_promisc when 2190*5fc77b81SRobert Mustacchi * manually putting the device into promiscuous mode. 2191*5fc77b81SRobert Mustacchi **/ 2192*5fc77b81SRobert Mustacchi s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2193*5fc77b81SRobert Mustacchi u32 addr_count, ixgbe_mc_addr_itr next) 2194*5fc77b81SRobert Mustacchi { 2195*5fc77b81SRobert Mustacchi u8 *addr; 2196*5fc77b81SRobert Mustacchi u32 i; 2197*5fc77b81SRobert Mustacchi u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2198*5fc77b81SRobert Mustacchi u32 uc_addr_in_use; 2199*5fc77b81SRobert Mustacchi u32 fctrl; 2200*5fc77b81SRobert Mustacchi u32 vmdq; 2201*5fc77b81SRobert Mustacchi 2202*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2203*5fc77b81SRobert Mustacchi 2204*5fc77b81SRobert Mustacchi /* 2205*5fc77b81SRobert Mustacchi * Clear accounting of old secondary address list, 2206*5fc77b81SRobert Mustacchi * don't count RAR[0] 2207*5fc77b81SRobert Mustacchi */ 2208*5fc77b81SRobert Mustacchi uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2209*5fc77b81SRobert Mustacchi hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2210*5fc77b81SRobert Mustacchi hw->addr_ctrl.overflow_promisc = 0; 2211*5fc77b81SRobert Mustacchi 2212*5fc77b81SRobert Mustacchi /* Zero out the other receive addresses */ 2213*5fc77b81SRobert Mustacchi DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2214*5fc77b81SRobert Mustacchi for (i = 0; i < uc_addr_in_use; i++) { 2215*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2216*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2217*5fc77b81SRobert Mustacchi } 2218*5fc77b81SRobert Mustacchi 2219*5fc77b81SRobert Mustacchi /* Add the new addresses */ 2220*5fc77b81SRobert Mustacchi for (i = 0; i < addr_count; i++) { 2221*5fc77b81SRobert Mustacchi DEBUGOUT(" Adding the secondary addresses:\n"); 2222*5fc77b81SRobert Mustacchi addr = next(hw, &addr_list, &vmdq); 2223*5fc77b81SRobert Mustacchi ixgbe_add_uc_addr(hw, addr, vmdq); 2224*5fc77b81SRobert Mustacchi } 2225*5fc77b81SRobert Mustacchi 2226*5fc77b81SRobert Mustacchi if (hw->addr_ctrl.overflow_promisc) { 2227*5fc77b81SRobert Mustacchi /* enable promisc if not already in overflow or set by user */ 2228*5fc77b81SRobert Mustacchi if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2229*5fc77b81SRobert Mustacchi DEBUGOUT(" Entering address overflow promisc mode\n"); 2230*5fc77b81SRobert Mustacchi fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2231*5fc77b81SRobert Mustacchi fctrl |= IXGBE_FCTRL_UPE; 2232*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2233*5fc77b81SRobert Mustacchi } 2234*5fc77b81SRobert Mustacchi } else { 2235*5fc77b81SRobert Mustacchi /* only disable if set by overflow, not by user */ 2236*5fc77b81SRobert Mustacchi if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2237*5fc77b81SRobert Mustacchi DEBUGOUT(" Leaving address overflow promisc mode\n"); 2238*5fc77b81SRobert Mustacchi fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2239*5fc77b81SRobert Mustacchi fctrl &= ~IXGBE_FCTRL_UPE; 2240*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2241*5fc77b81SRobert Mustacchi } 2242*5fc77b81SRobert Mustacchi } 2243*5fc77b81SRobert Mustacchi 2244*5fc77b81SRobert Mustacchi DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2245*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2246*5fc77b81SRobert Mustacchi } 2247*5fc77b81SRobert Mustacchi 2248*5fc77b81SRobert Mustacchi /** 2249*5fc77b81SRobert Mustacchi * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2250*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2251*5fc77b81SRobert Mustacchi * @mc_addr: the multicast address 2252*5fc77b81SRobert Mustacchi * 2253*5fc77b81SRobert Mustacchi * Extracts the 12 bits, from a multicast address, to determine which 2254*5fc77b81SRobert Mustacchi * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2255*5fc77b81SRobert Mustacchi * incoming rx multicast addresses, to determine the bit-vector to check in 2256*5fc77b81SRobert Mustacchi * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2257*5fc77b81SRobert Mustacchi * by the MO field of the MCSTCTRL. The MO field is set during initialization 2258*5fc77b81SRobert Mustacchi * to mc_filter_type. 2259*5fc77b81SRobert Mustacchi **/ 2260*5fc77b81SRobert Mustacchi static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2261*5fc77b81SRobert Mustacchi { 2262*5fc77b81SRobert Mustacchi u32 vector = 0; 2263*5fc77b81SRobert Mustacchi 2264*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_mta_vector"); 2265*5fc77b81SRobert Mustacchi 2266*5fc77b81SRobert Mustacchi switch (hw->mac.mc_filter_type) { 2267*5fc77b81SRobert Mustacchi case 0: /* use bits [47:36] of the address */ 2268*5fc77b81SRobert Mustacchi vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2269*5fc77b81SRobert Mustacchi break; 2270*5fc77b81SRobert Mustacchi case 1: /* use bits [46:35] of the address */ 2271*5fc77b81SRobert Mustacchi vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2272*5fc77b81SRobert Mustacchi break; 2273*5fc77b81SRobert Mustacchi case 2: /* use bits [45:34] of the address */ 2274*5fc77b81SRobert Mustacchi vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2275*5fc77b81SRobert Mustacchi break; 2276*5fc77b81SRobert Mustacchi case 3: /* use bits [43:32] of the address */ 2277*5fc77b81SRobert Mustacchi vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2278*5fc77b81SRobert Mustacchi break; 2279*5fc77b81SRobert Mustacchi default: /* Invalid mc_filter_type */ 2280*5fc77b81SRobert Mustacchi DEBUGOUT("MC filter type param set incorrectly\n"); 2281*5fc77b81SRobert Mustacchi ASSERT(0); 2282*5fc77b81SRobert Mustacchi break; 2283*5fc77b81SRobert Mustacchi } 2284*5fc77b81SRobert Mustacchi 2285*5fc77b81SRobert Mustacchi /* vector can only be 12-bits or boundary will be exceeded */ 2286*5fc77b81SRobert Mustacchi vector &= 0xFFF; 2287*5fc77b81SRobert Mustacchi return vector; 2288*5fc77b81SRobert Mustacchi } 2289*5fc77b81SRobert Mustacchi 2290*5fc77b81SRobert Mustacchi /** 2291*5fc77b81SRobert Mustacchi * ixgbe_set_mta - Set bit-vector in multicast table 2292*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2293*5fc77b81SRobert Mustacchi * @hash_value: Multicast address hash value 2294*5fc77b81SRobert Mustacchi * 2295*5fc77b81SRobert Mustacchi * Sets the bit-vector in the multicast table. 2296*5fc77b81SRobert Mustacchi **/ 2297*5fc77b81SRobert Mustacchi void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2298*5fc77b81SRobert Mustacchi { 2299*5fc77b81SRobert Mustacchi u32 vector; 2300*5fc77b81SRobert Mustacchi u32 vector_bit; 2301*5fc77b81SRobert Mustacchi u32 vector_reg; 2302*5fc77b81SRobert Mustacchi 2303*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_set_mta"); 2304*5fc77b81SRobert Mustacchi 2305*5fc77b81SRobert Mustacchi hw->addr_ctrl.mta_in_use++; 2306*5fc77b81SRobert Mustacchi 2307*5fc77b81SRobert Mustacchi vector = ixgbe_mta_vector(hw, mc_addr); 2308*5fc77b81SRobert Mustacchi DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2309*5fc77b81SRobert Mustacchi 2310*5fc77b81SRobert Mustacchi /* 2311*5fc77b81SRobert Mustacchi * The MTA is a register array of 128 32-bit registers. It is treated 2312*5fc77b81SRobert Mustacchi * like an array of 4096 bits. We want to set bit 2313*5fc77b81SRobert Mustacchi * BitArray[vector_value]. So we figure out what register the bit is 2314*5fc77b81SRobert Mustacchi * in, read it, OR in the new bit, then write back the new value. The 2315*5fc77b81SRobert Mustacchi * register is determined by the upper 7 bits of the vector value and 2316*5fc77b81SRobert Mustacchi * the bit within that register are determined by the lower 5 bits of 2317*5fc77b81SRobert Mustacchi * the value. 2318*5fc77b81SRobert Mustacchi */ 2319*5fc77b81SRobert Mustacchi vector_reg = (vector >> 5) & 0x7F; 2320*5fc77b81SRobert Mustacchi vector_bit = vector & 0x1F; 2321*5fc77b81SRobert Mustacchi hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2322*5fc77b81SRobert Mustacchi } 2323*5fc77b81SRobert Mustacchi 2324*5fc77b81SRobert Mustacchi /** 2325*5fc77b81SRobert Mustacchi * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2326*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2327*5fc77b81SRobert Mustacchi * @mc_addr_list: the list of new multicast addresses 2328*5fc77b81SRobert Mustacchi * @mc_addr_count: number of addresses 2329*5fc77b81SRobert Mustacchi * @next: iterator function to walk the multicast address list 2330*5fc77b81SRobert Mustacchi * @clear: flag, when set clears the table beforehand 2331*5fc77b81SRobert Mustacchi * 2332*5fc77b81SRobert Mustacchi * When the clear flag is set, the given list replaces any existing list. 2333*5fc77b81SRobert Mustacchi * Hashes the given addresses into the multicast table. 2334*5fc77b81SRobert Mustacchi **/ 2335*5fc77b81SRobert Mustacchi s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2336*5fc77b81SRobert Mustacchi u32 mc_addr_count, ixgbe_mc_addr_itr next, 2337*5fc77b81SRobert Mustacchi bool clear) 2338*5fc77b81SRobert Mustacchi { 2339*5fc77b81SRobert Mustacchi u32 i; 2340*5fc77b81SRobert Mustacchi u32 vmdq; 2341*5fc77b81SRobert Mustacchi 2342*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2343*5fc77b81SRobert Mustacchi 2344*5fc77b81SRobert Mustacchi /* 2345*5fc77b81SRobert Mustacchi * Set the new number of MC addresses that we are being requested to 2346*5fc77b81SRobert Mustacchi * use. 2347*5fc77b81SRobert Mustacchi */ 2348*5fc77b81SRobert Mustacchi hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2349*5fc77b81SRobert Mustacchi hw->addr_ctrl.mta_in_use = 0; 2350*5fc77b81SRobert Mustacchi 2351*5fc77b81SRobert Mustacchi /* Clear mta_shadow */ 2352*5fc77b81SRobert Mustacchi if (clear) { 2353*5fc77b81SRobert Mustacchi DEBUGOUT(" Clearing MTA\n"); 2354*5fc77b81SRobert Mustacchi (void) memset(&hw->mac.mta_shadow, 0, 2355*5fc77b81SRobert Mustacchi sizeof(hw->mac.mta_shadow)); 2356*5fc77b81SRobert Mustacchi } 2357*5fc77b81SRobert Mustacchi 2358*5fc77b81SRobert Mustacchi /* Update mta_shadow */ 2359*5fc77b81SRobert Mustacchi for (i = 0; i < mc_addr_count; i++) { 2360*5fc77b81SRobert Mustacchi DEBUGOUT(" Adding the multicast addresses:\n"); 2361*5fc77b81SRobert Mustacchi ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2362*5fc77b81SRobert Mustacchi } 2363*5fc77b81SRobert Mustacchi 2364*5fc77b81SRobert Mustacchi /* Enable mta */ 2365*5fc77b81SRobert Mustacchi for (i = 0; i < hw->mac.mcft_size; i++) 2366*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2367*5fc77b81SRobert Mustacchi hw->mac.mta_shadow[i]); 2368*5fc77b81SRobert Mustacchi 2369*5fc77b81SRobert Mustacchi if (hw->addr_ctrl.mta_in_use > 0) 2370*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2371*5fc77b81SRobert Mustacchi IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2372*5fc77b81SRobert Mustacchi 2373*5fc77b81SRobert Mustacchi DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2374*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2375*5fc77b81SRobert Mustacchi } 2376*5fc77b81SRobert Mustacchi 2377*5fc77b81SRobert Mustacchi /** 2378*5fc77b81SRobert Mustacchi * ixgbe_enable_mc_generic - Enable multicast address in RAR 2379*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2380*5fc77b81SRobert Mustacchi * 2381*5fc77b81SRobert Mustacchi * Enables multicast address in RAR and the use of the multicast hash table. 2382*5fc77b81SRobert Mustacchi **/ 2383*5fc77b81SRobert Mustacchi s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2384*5fc77b81SRobert Mustacchi { 2385*5fc77b81SRobert Mustacchi struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2386*5fc77b81SRobert Mustacchi 2387*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_enable_mc_generic"); 2388*5fc77b81SRobert Mustacchi 2389*5fc77b81SRobert Mustacchi if (a->mta_in_use > 0) 2390*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2391*5fc77b81SRobert Mustacchi hw->mac.mc_filter_type); 2392*5fc77b81SRobert Mustacchi 2393*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2394*5fc77b81SRobert Mustacchi } 2395*5fc77b81SRobert Mustacchi 2396*5fc77b81SRobert Mustacchi /** 2397*5fc77b81SRobert Mustacchi * ixgbe_disable_mc_generic - Disable multicast address in RAR 2398*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2399*5fc77b81SRobert Mustacchi * 2400*5fc77b81SRobert Mustacchi * Disables multicast address in RAR and the use of the multicast hash table. 2401*5fc77b81SRobert Mustacchi **/ 2402*5fc77b81SRobert Mustacchi s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2403*5fc77b81SRobert Mustacchi { 2404*5fc77b81SRobert Mustacchi struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2405*5fc77b81SRobert Mustacchi 2406*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_disable_mc_generic"); 2407*5fc77b81SRobert Mustacchi 2408*5fc77b81SRobert Mustacchi if (a->mta_in_use > 0) 2409*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2410*5fc77b81SRobert Mustacchi 2411*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2412*5fc77b81SRobert Mustacchi } 2413*5fc77b81SRobert Mustacchi 2414*5fc77b81SRobert Mustacchi /** 2415*5fc77b81SRobert Mustacchi * ixgbe_fc_enable_generic - Enable flow control 2416*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2417*5fc77b81SRobert Mustacchi * 2418*5fc77b81SRobert Mustacchi * Enable flow control according to the current settings. 2419*5fc77b81SRobert Mustacchi **/ 2420*5fc77b81SRobert Mustacchi s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2421*5fc77b81SRobert Mustacchi { 2422*5fc77b81SRobert Mustacchi s32 ret_val = IXGBE_SUCCESS; 2423*5fc77b81SRobert Mustacchi u32 mflcn_reg, fccfg_reg; 2424*5fc77b81SRobert Mustacchi u32 reg; 2425*5fc77b81SRobert Mustacchi u32 fcrtl, fcrth; 2426*5fc77b81SRobert Mustacchi int i; 2427*5fc77b81SRobert Mustacchi 2428*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_fc_enable_generic"); 2429*5fc77b81SRobert Mustacchi 2430*5fc77b81SRobert Mustacchi /* Validate the water mark configuration */ 2431*5fc77b81SRobert Mustacchi if (!hw->fc.pause_time) { 2432*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2433*5fc77b81SRobert Mustacchi goto out; 2434*5fc77b81SRobert Mustacchi } 2435*5fc77b81SRobert Mustacchi 2436*5fc77b81SRobert Mustacchi /* Low water mark of zero causes XOFF floods */ 2437*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2438*5fc77b81SRobert Mustacchi if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2439*5fc77b81SRobert Mustacchi hw->fc.high_water[i]) { 2440*5fc77b81SRobert Mustacchi if (!hw->fc.low_water[i] || 2441*5fc77b81SRobert Mustacchi hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2442*5fc77b81SRobert Mustacchi DEBUGOUT("Invalid water mark configuration\n"); 2443*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2444*5fc77b81SRobert Mustacchi goto out; 2445*5fc77b81SRobert Mustacchi } 2446*5fc77b81SRobert Mustacchi } 2447*5fc77b81SRobert Mustacchi } 2448*5fc77b81SRobert Mustacchi 2449*5fc77b81SRobert Mustacchi /* Negotiate the fc mode to use */ 2450*5fc77b81SRobert Mustacchi ixgbe_fc_autoneg(hw); 2451*5fc77b81SRobert Mustacchi 2452*5fc77b81SRobert Mustacchi /* Disable any previous flow control settings */ 2453*5fc77b81SRobert Mustacchi mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2454*5fc77b81SRobert Mustacchi mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2455*5fc77b81SRobert Mustacchi 2456*5fc77b81SRobert Mustacchi fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2457*5fc77b81SRobert Mustacchi fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2458*5fc77b81SRobert Mustacchi 2459*5fc77b81SRobert Mustacchi /* 2460*5fc77b81SRobert Mustacchi * The possible values of fc.current_mode are: 2461*5fc77b81SRobert Mustacchi * 0: Flow control is completely disabled 2462*5fc77b81SRobert Mustacchi * 1: Rx flow control is enabled (we can receive pause frames, 2463*5fc77b81SRobert Mustacchi * but not send pause frames). 2464*5fc77b81SRobert Mustacchi * 2: Tx flow control is enabled (we can send pause frames but 2465*5fc77b81SRobert Mustacchi * we do not support receiving pause frames). 2466*5fc77b81SRobert Mustacchi * 3: Both Rx and Tx flow control (symmetric) are enabled. 2467*5fc77b81SRobert Mustacchi * other: Invalid. 2468*5fc77b81SRobert Mustacchi */ 2469*5fc77b81SRobert Mustacchi switch (hw->fc.current_mode) { 2470*5fc77b81SRobert Mustacchi case ixgbe_fc_none: 2471*5fc77b81SRobert Mustacchi /* 2472*5fc77b81SRobert Mustacchi * Flow control is disabled by software override or autoneg. 2473*5fc77b81SRobert Mustacchi * The code below will actually disable it in the HW. 2474*5fc77b81SRobert Mustacchi */ 2475*5fc77b81SRobert Mustacchi break; 2476*5fc77b81SRobert Mustacchi case ixgbe_fc_rx_pause: 2477*5fc77b81SRobert Mustacchi /* 2478*5fc77b81SRobert Mustacchi * Rx Flow control is enabled and Tx Flow control is 2479*5fc77b81SRobert Mustacchi * disabled by software override. Since there really 2480*5fc77b81SRobert Mustacchi * isn't a way to advertise that we are capable of RX 2481*5fc77b81SRobert Mustacchi * Pause ONLY, we will advertise that we support both 2482*5fc77b81SRobert Mustacchi * symmetric and asymmetric Rx PAUSE. Later, we will 2483*5fc77b81SRobert Mustacchi * disable the adapter's ability to send PAUSE frames. 2484*5fc77b81SRobert Mustacchi */ 2485*5fc77b81SRobert Mustacchi mflcn_reg |= IXGBE_MFLCN_RFCE; 2486*5fc77b81SRobert Mustacchi break; 2487*5fc77b81SRobert Mustacchi case ixgbe_fc_tx_pause: 2488*5fc77b81SRobert Mustacchi /* 2489*5fc77b81SRobert Mustacchi * Tx Flow control is enabled, and Rx Flow control is 2490*5fc77b81SRobert Mustacchi * disabled by software override. 2491*5fc77b81SRobert Mustacchi */ 2492*5fc77b81SRobert Mustacchi fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2493*5fc77b81SRobert Mustacchi break; 2494*5fc77b81SRobert Mustacchi case ixgbe_fc_full: 2495*5fc77b81SRobert Mustacchi /* Flow control (both Rx and Tx) is enabled by SW override. */ 2496*5fc77b81SRobert Mustacchi mflcn_reg |= IXGBE_MFLCN_RFCE; 2497*5fc77b81SRobert Mustacchi fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2498*5fc77b81SRobert Mustacchi break; 2499*5fc77b81SRobert Mustacchi default: 2500*5fc77b81SRobert Mustacchi DEBUGOUT("Flow control param set incorrectly\n"); 2501*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_CONFIG; 2502*5fc77b81SRobert Mustacchi goto out; 2503*5fc77b81SRobert Mustacchi } 2504*5fc77b81SRobert Mustacchi 2505*5fc77b81SRobert Mustacchi /* Set 802.3x based flow control settings. */ 2506*5fc77b81SRobert Mustacchi mflcn_reg |= IXGBE_MFLCN_DPF; 2507*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2508*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2509*5fc77b81SRobert Mustacchi 2510*5fc77b81SRobert Mustacchi 2511*5fc77b81SRobert Mustacchi /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2512*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2513*5fc77b81SRobert Mustacchi if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2514*5fc77b81SRobert Mustacchi hw->fc.high_water[i]) { 2515*5fc77b81SRobert Mustacchi fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2516*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2517*5fc77b81SRobert Mustacchi fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2518*5fc77b81SRobert Mustacchi } else { 2519*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2520*5fc77b81SRobert Mustacchi /* 2521*5fc77b81SRobert Mustacchi * In order to prevent Tx hangs when the internal Tx 2522*5fc77b81SRobert Mustacchi * switch is enabled we must set the high water mark 2523*5fc77b81SRobert Mustacchi * to the maximum FCRTH value. This allows the Tx 2524*5fc77b81SRobert Mustacchi * switch to function even under heavy Rx workloads. 2525*5fc77b81SRobert Mustacchi */ 2526*5fc77b81SRobert Mustacchi fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; 2527*5fc77b81SRobert Mustacchi } 2528*5fc77b81SRobert Mustacchi 2529*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2530*5fc77b81SRobert Mustacchi } 2531*5fc77b81SRobert Mustacchi 2532*5fc77b81SRobert Mustacchi /* Configure pause time (2 TCs per register) */ 2533*5fc77b81SRobert Mustacchi reg = hw->fc.pause_time * 0x00010001; 2534*5fc77b81SRobert Mustacchi for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2535*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2536*5fc77b81SRobert Mustacchi 2537*5fc77b81SRobert Mustacchi /* Configure flow control refresh threshold value */ 2538*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2539*5fc77b81SRobert Mustacchi 2540*5fc77b81SRobert Mustacchi out: 2541*5fc77b81SRobert Mustacchi return ret_val; 2542*5fc77b81SRobert Mustacchi } 2543*5fc77b81SRobert Mustacchi 2544*5fc77b81SRobert Mustacchi /** 2545*5fc77b81SRobert Mustacchi * ixgbe_negotiate_fc - Negotiate flow control 2546*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2547*5fc77b81SRobert Mustacchi * @adv_reg: flow control advertised settings 2548*5fc77b81SRobert Mustacchi * @lp_reg: link partner's flow control settings 2549*5fc77b81SRobert Mustacchi * @adv_sym: symmetric pause bit in advertisement 2550*5fc77b81SRobert Mustacchi * @adv_asm: asymmetric pause bit in advertisement 2551*5fc77b81SRobert Mustacchi * @lp_sym: symmetric pause bit in link partner advertisement 2552*5fc77b81SRobert Mustacchi * @lp_asm: asymmetric pause bit in link partner advertisement 2553*5fc77b81SRobert Mustacchi * 2554*5fc77b81SRobert Mustacchi * Find the intersection between advertised settings and link partner's 2555*5fc77b81SRobert Mustacchi * advertised settings 2556*5fc77b81SRobert Mustacchi **/ 2557*5fc77b81SRobert Mustacchi static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2558*5fc77b81SRobert Mustacchi u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2559*5fc77b81SRobert Mustacchi { 2560*5fc77b81SRobert Mustacchi if ((!(adv_reg)) || (!(lp_reg))) 2561*5fc77b81SRobert Mustacchi return IXGBE_ERR_FC_NOT_NEGOTIATED; 2562*5fc77b81SRobert Mustacchi 2563*5fc77b81SRobert Mustacchi if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2564*5fc77b81SRobert Mustacchi /* 2565*5fc77b81SRobert Mustacchi * Now we need to check if the user selected Rx ONLY 2566*5fc77b81SRobert Mustacchi * of pause frames. In this case, we had to advertise 2567*5fc77b81SRobert Mustacchi * FULL flow control because we could not advertise RX 2568*5fc77b81SRobert Mustacchi * ONLY. Hence, we must now check to see if we need to 2569*5fc77b81SRobert Mustacchi * turn OFF the TRANSMISSION of PAUSE frames. 2570*5fc77b81SRobert Mustacchi */ 2571*5fc77b81SRobert Mustacchi if (hw->fc.requested_mode == ixgbe_fc_full) { 2572*5fc77b81SRobert Mustacchi hw->fc.current_mode = ixgbe_fc_full; 2573*5fc77b81SRobert Mustacchi DEBUGOUT("Flow Control = FULL.\n"); 2574*5fc77b81SRobert Mustacchi } else { 2575*5fc77b81SRobert Mustacchi hw->fc.current_mode = ixgbe_fc_rx_pause; 2576*5fc77b81SRobert Mustacchi DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2577*5fc77b81SRobert Mustacchi } 2578*5fc77b81SRobert Mustacchi } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2579*5fc77b81SRobert Mustacchi (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2580*5fc77b81SRobert Mustacchi hw->fc.current_mode = ixgbe_fc_tx_pause; 2581*5fc77b81SRobert Mustacchi DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2582*5fc77b81SRobert Mustacchi } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2583*5fc77b81SRobert Mustacchi !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2584*5fc77b81SRobert Mustacchi hw->fc.current_mode = ixgbe_fc_rx_pause; 2585*5fc77b81SRobert Mustacchi DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2586*5fc77b81SRobert Mustacchi } else { 2587*5fc77b81SRobert Mustacchi hw->fc.current_mode = ixgbe_fc_none; 2588*5fc77b81SRobert Mustacchi DEBUGOUT("Flow Control = NONE.\n"); 2589*5fc77b81SRobert Mustacchi } 2590*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2591*5fc77b81SRobert Mustacchi } 2592*5fc77b81SRobert Mustacchi 2593*5fc77b81SRobert Mustacchi /** 2594*5fc77b81SRobert Mustacchi * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2595*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2596*5fc77b81SRobert Mustacchi * 2597*5fc77b81SRobert Mustacchi * Enable flow control according on 1 gig fiber. 2598*5fc77b81SRobert Mustacchi **/ 2599*5fc77b81SRobert Mustacchi static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2600*5fc77b81SRobert Mustacchi { 2601*5fc77b81SRobert Mustacchi u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2602*5fc77b81SRobert Mustacchi s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2603*5fc77b81SRobert Mustacchi 2604*5fc77b81SRobert Mustacchi /* 2605*5fc77b81SRobert Mustacchi * On multispeed fiber at 1g, bail out if 2606*5fc77b81SRobert Mustacchi * - link is up but AN did not complete, or if 2607*5fc77b81SRobert Mustacchi * - link is up and AN completed but timed out 2608*5fc77b81SRobert Mustacchi */ 2609*5fc77b81SRobert Mustacchi 2610*5fc77b81SRobert Mustacchi linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2611*5fc77b81SRobert Mustacchi if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2612*5fc77b81SRobert Mustacchi (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) 2613*5fc77b81SRobert Mustacchi goto out; 2614*5fc77b81SRobert Mustacchi 2615*5fc77b81SRobert Mustacchi pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2616*5fc77b81SRobert Mustacchi pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2617*5fc77b81SRobert Mustacchi 2618*5fc77b81SRobert Mustacchi ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2619*5fc77b81SRobert Mustacchi pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2620*5fc77b81SRobert Mustacchi IXGBE_PCS1GANA_ASM_PAUSE, 2621*5fc77b81SRobert Mustacchi IXGBE_PCS1GANA_SYM_PAUSE, 2622*5fc77b81SRobert Mustacchi IXGBE_PCS1GANA_ASM_PAUSE); 2623*5fc77b81SRobert Mustacchi 2624*5fc77b81SRobert Mustacchi out: 2625*5fc77b81SRobert Mustacchi return ret_val; 2626*5fc77b81SRobert Mustacchi } 2627*5fc77b81SRobert Mustacchi 2628*5fc77b81SRobert Mustacchi /** 2629*5fc77b81SRobert Mustacchi * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2630*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2631*5fc77b81SRobert Mustacchi * 2632*5fc77b81SRobert Mustacchi * Enable flow control according to IEEE clause 37. 2633*5fc77b81SRobert Mustacchi **/ 2634*5fc77b81SRobert Mustacchi static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2635*5fc77b81SRobert Mustacchi { 2636*5fc77b81SRobert Mustacchi u32 links2, anlp1_reg, autoc_reg, links; 2637*5fc77b81SRobert Mustacchi s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2638*5fc77b81SRobert Mustacchi 2639*5fc77b81SRobert Mustacchi /* 2640*5fc77b81SRobert Mustacchi * On backplane, bail out if 2641*5fc77b81SRobert Mustacchi * - backplane autoneg was not completed, or if 2642*5fc77b81SRobert Mustacchi * - we are 82599 and link partner is not AN enabled 2643*5fc77b81SRobert Mustacchi */ 2644*5fc77b81SRobert Mustacchi links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2645*5fc77b81SRobert Mustacchi if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) 2646*5fc77b81SRobert Mustacchi goto out; 2647*5fc77b81SRobert Mustacchi 2648*5fc77b81SRobert Mustacchi if (hw->mac.type == ixgbe_mac_82599EB) { 2649*5fc77b81SRobert Mustacchi links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2650*5fc77b81SRobert Mustacchi if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) 2651*5fc77b81SRobert Mustacchi goto out; 2652*5fc77b81SRobert Mustacchi } 2653*5fc77b81SRobert Mustacchi /* 2654*5fc77b81SRobert Mustacchi * Read the 10g AN autoc and LP ability registers and resolve 2655*5fc77b81SRobert Mustacchi * local flow control settings accordingly 2656*5fc77b81SRobert Mustacchi */ 2657*5fc77b81SRobert Mustacchi autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2658*5fc77b81SRobert Mustacchi anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2659*5fc77b81SRobert Mustacchi 2660*5fc77b81SRobert Mustacchi ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2661*5fc77b81SRobert Mustacchi anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2662*5fc77b81SRobert Mustacchi IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2663*5fc77b81SRobert Mustacchi 2664*5fc77b81SRobert Mustacchi out: 2665*5fc77b81SRobert Mustacchi return ret_val; 2666*5fc77b81SRobert Mustacchi } 2667*5fc77b81SRobert Mustacchi 2668*5fc77b81SRobert Mustacchi /** 2669*5fc77b81SRobert Mustacchi * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2670*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2671*5fc77b81SRobert Mustacchi * 2672*5fc77b81SRobert Mustacchi * Enable flow control according to IEEE clause 37. 2673*5fc77b81SRobert Mustacchi **/ 2674*5fc77b81SRobert Mustacchi static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2675*5fc77b81SRobert Mustacchi { 2676*5fc77b81SRobert Mustacchi u16 technology_ability_reg = 0; 2677*5fc77b81SRobert Mustacchi u16 lp_technology_ability_reg = 0; 2678*5fc77b81SRobert Mustacchi 2679*5fc77b81SRobert Mustacchi hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 2680*5fc77b81SRobert Mustacchi IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2681*5fc77b81SRobert Mustacchi &technology_ability_reg); 2682*5fc77b81SRobert Mustacchi hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 2683*5fc77b81SRobert Mustacchi IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2684*5fc77b81SRobert Mustacchi &lp_technology_ability_reg); 2685*5fc77b81SRobert Mustacchi 2686*5fc77b81SRobert Mustacchi return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2687*5fc77b81SRobert Mustacchi (u32)lp_technology_ability_reg, 2688*5fc77b81SRobert Mustacchi IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2689*5fc77b81SRobert Mustacchi IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2690*5fc77b81SRobert Mustacchi } 2691*5fc77b81SRobert Mustacchi 2692*5fc77b81SRobert Mustacchi /** 2693*5fc77b81SRobert Mustacchi * ixgbe_fc_autoneg - Configure flow control 2694*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2695*5fc77b81SRobert Mustacchi * 2696*5fc77b81SRobert Mustacchi * Compares our advertised flow control capabilities to those advertised by 2697*5fc77b81SRobert Mustacchi * our link partner, and determines the proper flow control mode to use. 2698*5fc77b81SRobert Mustacchi **/ 2699*5fc77b81SRobert Mustacchi void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2700*5fc77b81SRobert Mustacchi { 2701*5fc77b81SRobert Mustacchi s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2702*5fc77b81SRobert Mustacchi ixgbe_link_speed speed; 2703*5fc77b81SRobert Mustacchi bool link_up; 2704*5fc77b81SRobert Mustacchi 2705*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_fc_autoneg"); 2706*5fc77b81SRobert Mustacchi 2707*5fc77b81SRobert Mustacchi /* 2708*5fc77b81SRobert Mustacchi * AN should have completed when the cable was plugged in. 2709*5fc77b81SRobert Mustacchi * Look for reasons to bail out. Bail out if: 2710*5fc77b81SRobert Mustacchi * - FC autoneg is disabled, or if 2711*5fc77b81SRobert Mustacchi * - link is not up. 2712*5fc77b81SRobert Mustacchi */ 2713*5fc77b81SRobert Mustacchi if (hw->fc.disable_fc_autoneg) 2714*5fc77b81SRobert Mustacchi goto out; 2715*5fc77b81SRobert Mustacchi 2716*5fc77b81SRobert Mustacchi hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 2717*5fc77b81SRobert Mustacchi if (!link_up) 2718*5fc77b81SRobert Mustacchi goto out; 2719*5fc77b81SRobert Mustacchi 2720*5fc77b81SRobert Mustacchi switch (hw->phy.media_type) { 2721*5fc77b81SRobert Mustacchi /* Autoneg flow control on fiber adapters */ 2722*5fc77b81SRobert Mustacchi case ixgbe_media_type_fiber: 2723*5fc77b81SRobert Mustacchi if (speed == IXGBE_LINK_SPEED_1GB_FULL) 2724*5fc77b81SRobert Mustacchi ret_val = ixgbe_fc_autoneg_fiber(hw); 2725*5fc77b81SRobert Mustacchi break; 2726*5fc77b81SRobert Mustacchi 2727*5fc77b81SRobert Mustacchi /* Autoneg flow control on backplane adapters */ 2728*5fc77b81SRobert Mustacchi case ixgbe_media_type_backplane: 2729*5fc77b81SRobert Mustacchi ret_val = ixgbe_fc_autoneg_backplane(hw); 2730*5fc77b81SRobert Mustacchi break; 2731*5fc77b81SRobert Mustacchi 2732*5fc77b81SRobert Mustacchi /* Autoneg flow control on copper adapters */ 2733*5fc77b81SRobert Mustacchi case ixgbe_media_type_copper: 2734*5fc77b81SRobert Mustacchi if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS) 2735*5fc77b81SRobert Mustacchi ret_val = ixgbe_fc_autoneg_copper(hw); 2736*5fc77b81SRobert Mustacchi break; 2737*5fc77b81SRobert Mustacchi 2738*5fc77b81SRobert Mustacchi default: 2739*5fc77b81SRobert Mustacchi break; 2740*5fc77b81SRobert Mustacchi } 2741*5fc77b81SRobert Mustacchi 2742*5fc77b81SRobert Mustacchi out: 2743*5fc77b81SRobert Mustacchi if (ret_val == IXGBE_SUCCESS) { 2744*5fc77b81SRobert Mustacchi hw->fc.fc_was_autonegged = TRUE; 2745*5fc77b81SRobert Mustacchi } else { 2746*5fc77b81SRobert Mustacchi hw->fc.fc_was_autonegged = FALSE; 2747*5fc77b81SRobert Mustacchi hw->fc.current_mode = hw->fc.requested_mode; 2748*5fc77b81SRobert Mustacchi } 2749*5fc77b81SRobert Mustacchi } 2750*5fc77b81SRobert Mustacchi 2751*5fc77b81SRobert Mustacchi /** 2752*5fc77b81SRobert Mustacchi * ixgbe_disable_pcie_master - Disable PCI-express master access 2753*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2754*5fc77b81SRobert Mustacchi * 2755*5fc77b81SRobert Mustacchi * Disables PCI-Express master access and verifies there are no pending 2756*5fc77b81SRobert Mustacchi * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2757*5fc77b81SRobert Mustacchi * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 2758*5fc77b81SRobert Mustacchi * is returned signifying master requests disabled. 2759*5fc77b81SRobert Mustacchi **/ 2760*5fc77b81SRobert Mustacchi s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2761*5fc77b81SRobert Mustacchi { 2762*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 2763*5fc77b81SRobert Mustacchi u32 i; 2764*5fc77b81SRobert Mustacchi 2765*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_disable_pcie_master"); 2766*5fc77b81SRobert Mustacchi 2767*5fc77b81SRobert Mustacchi /* Always set this bit to ensure any future transactions are blocked */ 2768*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 2769*5fc77b81SRobert Mustacchi 2770*5fc77b81SRobert Mustacchi /* Exit if master requets are blocked */ 2771*5fc77b81SRobert Mustacchi if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2772*5fc77b81SRobert Mustacchi goto out; 2773*5fc77b81SRobert Mustacchi 2774*5fc77b81SRobert Mustacchi /* Poll for master request bit to clear */ 2775*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2776*5fc77b81SRobert Mustacchi usec_delay(100); 2777*5fc77b81SRobert Mustacchi if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2778*5fc77b81SRobert Mustacchi goto out; 2779*5fc77b81SRobert Mustacchi } 2780*5fc77b81SRobert Mustacchi 2781*5fc77b81SRobert Mustacchi /* 2782*5fc77b81SRobert Mustacchi * Two consecutive resets are required via CTRL.RST per datasheet 2783*5fc77b81SRobert Mustacchi * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2784*5fc77b81SRobert Mustacchi * of this need. The first reset prevents new master requests from 2785*5fc77b81SRobert Mustacchi * being issued by our device. We then must wait 1usec or more for any 2786*5fc77b81SRobert Mustacchi * remaining completions from the PCIe bus to trickle in, and then reset 2787*5fc77b81SRobert Mustacchi * again to clear out any effects they may have had on our device. 2788*5fc77b81SRobert Mustacchi */ 2789*5fc77b81SRobert Mustacchi DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 2790*5fc77b81SRobert Mustacchi hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2791*5fc77b81SRobert Mustacchi 2792*5fc77b81SRobert Mustacchi /* 2793*5fc77b81SRobert Mustacchi * Before proceeding, make sure that the PCIe block does not have 2794*5fc77b81SRobert Mustacchi * transactions pending. 2795*5fc77b81SRobert Mustacchi */ 2796*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2797*5fc77b81SRobert Mustacchi usec_delay(100); 2798*5fc77b81SRobert Mustacchi if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) & 2799*5fc77b81SRobert Mustacchi IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2800*5fc77b81SRobert Mustacchi goto out; 2801*5fc77b81SRobert Mustacchi } 2802*5fc77b81SRobert Mustacchi 2803*5fc77b81SRobert Mustacchi DEBUGOUT("PCIe transaction pending bit also did not clear.\n"); 2804*5fc77b81SRobert Mustacchi status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2805*5fc77b81SRobert Mustacchi 2806*5fc77b81SRobert Mustacchi out: 2807*5fc77b81SRobert Mustacchi return status; 2808*5fc77b81SRobert Mustacchi } 2809*5fc77b81SRobert Mustacchi 2810*5fc77b81SRobert Mustacchi /** 2811*5fc77b81SRobert Mustacchi * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2812*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2813*5fc77b81SRobert Mustacchi * @mask: Mask to specify which semaphore to acquire 2814*5fc77b81SRobert Mustacchi * 2815*5fc77b81SRobert Mustacchi * Acquires the SWFW semaphore through the GSSR register for the specified 2816*5fc77b81SRobert Mustacchi * function (CSR, PHY0, PHY1, EEPROM, Flash) 2817*5fc77b81SRobert Mustacchi **/ 2818*5fc77b81SRobert Mustacchi s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2819*5fc77b81SRobert Mustacchi { 2820*5fc77b81SRobert Mustacchi u32 gssr; 2821*5fc77b81SRobert Mustacchi u32 swmask = mask; 2822*5fc77b81SRobert Mustacchi u32 fwmask = mask << 5; 2823*5fc77b81SRobert Mustacchi s32 timeout = 200; 2824*5fc77b81SRobert Mustacchi 2825*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_acquire_swfw_sync"); 2826*5fc77b81SRobert Mustacchi 2827*5fc77b81SRobert Mustacchi while (timeout) { 2828*5fc77b81SRobert Mustacchi /* 2829*5fc77b81SRobert Mustacchi * SW EEPROM semaphore bit is used for access to all 2830*5fc77b81SRobert Mustacchi * SW_FW_SYNC/GSSR bits (not just EEPROM) 2831*5fc77b81SRobert Mustacchi */ 2832*5fc77b81SRobert Mustacchi if (ixgbe_get_eeprom_semaphore(hw)) 2833*5fc77b81SRobert Mustacchi return IXGBE_ERR_SWFW_SYNC; 2834*5fc77b81SRobert Mustacchi 2835*5fc77b81SRobert Mustacchi gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2836*5fc77b81SRobert Mustacchi if (!(gssr & (fwmask | swmask))) 2837*5fc77b81SRobert Mustacchi break; 2838*5fc77b81SRobert Mustacchi 2839*5fc77b81SRobert Mustacchi /* 2840*5fc77b81SRobert Mustacchi * Firmware currently using resource (fwmask) or other software 2841*5fc77b81SRobert Mustacchi * thread currently using resource (swmask) 2842*5fc77b81SRobert Mustacchi */ 2843*5fc77b81SRobert Mustacchi ixgbe_release_eeprom_semaphore(hw); 2844*5fc77b81SRobert Mustacchi msec_delay(5); 2845*5fc77b81SRobert Mustacchi timeout--; 2846*5fc77b81SRobert Mustacchi } 2847*5fc77b81SRobert Mustacchi 2848*5fc77b81SRobert Mustacchi if (!timeout) { 2849*5fc77b81SRobert Mustacchi DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2850*5fc77b81SRobert Mustacchi return IXGBE_ERR_SWFW_SYNC; 2851*5fc77b81SRobert Mustacchi } 2852*5fc77b81SRobert Mustacchi 2853*5fc77b81SRobert Mustacchi gssr |= swmask; 2854*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2855*5fc77b81SRobert Mustacchi 2856*5fc77b81SRobert Mustacchi ixgbe_release_eeprom_semaphore(hw); 2857*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2858*5fc77b81SRobert Mustacchi } 2859*5fc77b81SRobert Mustacchi 2860*5fc77b81SRobert Mustacchi /** 2861*5fc77b81SRobert Mustacchi * ixgbe_release_swfw_sync - Release SWFW semaphore 2862*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2863*5fc77b81SRobert Mustacchi * @mask: Mask to specify which semaphore to release 2864*5fc77b81SRobert Mustacchi * 2865*5fc77b81SRobert Mustacchi * Releases the SWFW semaphore through the GSSR register for the specified 2866*5fc77b81SRobert Mustacchi * function (CSR, PHY0, PHY1, EEPROM, Flash) 2867*5fc77b81SRobert Mustacchi **/ 2868*5fc77b81SRobert Mustacchi void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2869*5fc77b81SRobert Mustacchi { 2870*5fc77b81SRobert Mustacchi u32 gssr; 2871*5fc77b81SRobert Mustacchi u32 swmask = mask; 2872*5fc77b81SRobert Mustacchi 2873*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_release_swfw_sync"); 2874*5fc77b81SRobert Mustacchi 2875*5fc77b81SRobert Mustacchi (void) ixgbe_get_eeprom_semaphore(hw); 2876*5fc77b81SRobert Mustacchi 2877*5fc77b81SRobert Mustacchi gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2878*5fc77b81SRobert Mustacchi gssr &= ~swmask; 2879*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2880*5fc77b81SRobert Mustacchi 2881*5fc77b81SRobert Mustacchi ixgbe_release_eeprom_semaphore(hw); 2882*5fc77b81SRobert Mustacchi } 2883*5fc77b81SRobert Mustacchi 2884*5fc77b81SRobert Mustacchi /** 2885*5fc77b81SRobert Mustacchi * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 2886*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2887*5fc77b81SRobert Mustacchi * 2888*5fc77b81SRobert Mustacchi * Stops the receive data path and waits for the HW to internally empty 2889*5fc77b81SRobert Mustacchi * the Rx security block 2890*5fc77b81SRobert Mustacchi **/ 2891*5fc77b81SRobert Mustacchi s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 2892*5fc77b81SRobert Mustacchi { 2893*5fc77b81SRobert Mustacchi #define IXGBE_MAX_SECRX_POLL 40 2894*5fc77b81SRobert Mustacchi 2895*5fc77b81SRobert Mustacchi int i; 2896*5fc77b81SRobert Mustacchi int secrxreg; 2897*5fc77b81SRobert Mustacchi 2898*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 2899*5fc77b81SRobert Mustacchi 2900*5fc77b81SRobert Mustacchi 2901*5fc77b81SRobert Mustacchi secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2902*5fc77b81SRobert Mustacchi secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 2903*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2904*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 2905*5fc77b81SRobert Mustacchi secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 2906*5fc77b81SRobert Mustacchi if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 2907*5fc77b81SRobert Mustacchi break; 2908*5fc77b81SRobert Mustacchi else 2909*5fc77b81SRobert Mustacchi /* Use interrupt-safe sleep just in case */ 2910*5fc77b81SRobert Mustacchi usec_delay(1000); 2911*5fc77b81SRobert Mustacchi } 2912*5fc77b81SRobert Mustacchi 2913*5fc77b81SRobert Mustacchi /* For informational purposes only */ 2914*5fc77b81SRobert Mustacchi if (i >= IXGBE_MAX_SECRX_POLL) 2915*5fc77b81SRobert Mustacchi DEBUGOUT("Rx unit being enabled before security " 2916*5fc77b81SRobert Mustacchi "path fully disabled. Continuing with init.\n"); 2917*5fc77b81SRobert Mustacchi 2918*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2919*5fc77b81SRobert Mustacchi } 2920*5fc77b81SRobert Mustacchi 2921*5fc77b81SRobert Mustacchi /** 2922*5fc77b81SRobert Mustacchi * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 2923*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2924*5fc77b81SRobert Mustacchi * 2925*5fc77b81SRobert Mustacchi * Enables the receive data path. 2926*5fc77b81SRobert Mustacchi **/ 2927*5fc77b81SRobert Mustacchi s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 2928*5fc77b81SRobert Mustacchi { 2929*5fc77b81SRobert Mustacchi int secrxreg; 2930*5fc77b81SRobert Mustacchi 2931*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 2932*5fc77b81SRobert Mustacchi 2933*5fc77b81SRobert Mustacchi secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 2934*5fc77b81SRobert Mustacchi secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 2935*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 2936*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 2937*5fc77b81SRobert Mustacchi 2938*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2939*5fc77b81SRobert Mustacchi } 2940*5fc77b81SRobert Mustacchi 2941*5fc77b81SRobert Mustacchi /** 2942*5fc77b81SRobert Mustacchi * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2943*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2944*5fc77b81SRobert Mustacchi * @regval: register value to write to RXCTRL 2945*5fc77b81SRobert Mustacchi * 2946*5fc77b81SRobert Mustacchi * Enables the Rx DMA unit 2947*5fc77b81SRobert Mustacchi **/ 2948*5fc77b81SRobert Mustacchi s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2949*5fc77b81SRobert Mustacchi { 2950*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 2951*5fc77b81SRobert Mustacchi 2952*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2953*5fc77b81SRobert Mustacchi 2954*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2955*5fc77b81SRobert Mustacchi } 2956*5fc77b81SRobert Mustacchi 2957*5fc77b81SRobert Mustacchi /** 2958*5fc77b81SRobert Mustacchi * ixgbe_blink_led_start_generic - Blink LED based on index. 2959*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2960*5fc77b81SRobert Mustacchi * @index: led number to blink 2961*5fc77b81SRobert Mustacchi **/ 2962*5fc77b81SRobert Mustacchi s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2963*5fc77b81SRobert Mustacchi { 2964*5fc77b81SRobert Mustacchi ixgbe_link_speed speed = 0; 2965*5fc77b81SRobert Mustacchi bool link_up = 0; 2966*5fc77b81SRobert Mustacchi u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2967*5fc77b81SRobert Mustacchi u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2968*5fc77b81SRobert Mustacchi 2969*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_blink_led_start_generic"); 2970*5fc77b81SRobert Mustacchi 2971*5fc77b81SRobert Mustacchi /* 2972*5fc77b81SRobert Mustacchi * Link must be up to auto-blink the LEDs; 2973*5fc77b81SRobert Mustacchi * Force it if link is down. 2974*5fc77b81SRobert Mustacchi */ 2975*5fc77b81SRobert Mustacchi hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 2976*5fc77b81SRobert Mustacchi 2977*5fc77b81SRobert Mustacchi if (!link_up) { 2978*5fc77b81SRobert Mustacchi autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2979*5fc77b81SRobert Mustacchi autoc_reg |= IXGBE_AUTOC_FLU; 2980*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2981*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 2982*5fc77b81SRobert Mustacchi msec_delay(10); 2983*5fc77b81SRobert Mustacchi } 2984*5fc77b81SRobert Mustacchi 2985*5fc77b81SRobert Mustacchi led_reg &= ~IXGBE_LED_MODE_MASK(index); 2986*5fc77b81SRobert Mustacchi led_reg |= IXGBE_LED_BLINK(index); 2987*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2988*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 2989*5fc77b81SRobert Mustacchi 2990*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 2991*5fc77b81SRobert Mustacchi } 2992*5fc77b81SRobert Mustacchi 2993*5fc77b81SRobert Mustacchi /** 2994*5fc77b81SRobert Mustacchi * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2995*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 2996*5fc77b81SRobert Mustacchi * @index: led number to stop blinking 2997*5fc77b81SRobert Mustacchi **/ 2998*5fc77b81SRobert Mustacchi s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2999*5fc77b81SRobert Mustacchi { 3000*5fc77b81SRobert Mustacchi u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3001*5fc77b81SRobert Mustacchi u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3002*5fc77b81SRobert Mustacchi 3003*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3004*5fc77b81SRobert Mustacchi 3005*5fc77b81SRobert Mustacchi 3006*5fc77b81SRobert Mustacchi autoc_reg &= ~IXGBE_AUTOC_FLU; 3007*5fc77b81SRobert Mustacchi autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3008*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 3009*5fc77b81SRobert Mustacchi 3010*5fc77b81SRobert Mustacchi led_reg &= ~IXGBE_LED_MODE_MASK(index); 3011*5fc77b81SRobert Mustacchi led_reg &= ~IXGBE_LED_BLINK(index); 3012*5fc77b81SRobert Mustacchi led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3013*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3014*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 3015*5fc77b81SRobert Mustacchi 3016*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3017*5fc77b81SRobert Mustacchi } 3018*5fc77b81SRobert Mustacchi 3019*5fc77b81SRobert Mustacchi /** 3020*5fc77b81SRobert Mustacchi * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3021*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3022*5fc77b81SRobert Mustacchi * @san_mac_offset: SAN MAC address offset 3023*5fc77b81SRobert Mustacchi * 3024*5fc77b81SRobert Mustacchi * This function will read the EEPROM location for the SAN MAC address 3025*5fc77b81SRobert Mustacchi * pointer, and returns the value at that location. This is used in both 3026*5fc77b81SRobert Mustacchi * get and set mac_addr routines. 3027*5fc77b81SRobert Mustacchi **/ 3028*5fc77b81SRobert Mustacchi static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3029*5fc77b81SRobert Mustacchi u16 *san_mac_offset) 3030*5fc77b81SRobert Mustacchi { 3031*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3032*5fc77b81SRobert Mustacchi 3033*5fc77b81SRobert Mustacchi /* 3034*5fc77b81SRobert Mustacchi * First read the EEPROM pointer to see if the MAC addresses are 3035*5fc77b81SRobert Mustacchi * available. 3036*5fc77b81SRobert Mustacchi */ 3037*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); 3038*5fc77b81SRobert Mustacchi 3039*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3040*5fc77b81SRobert Mustacchi } 3041*5fc77b81SRobert Mustacchi 3042*5fc77b81SRobert Mustacchi /** 3043*5fc77b81SRobert Mustacchi * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3044*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3045*5fc77b81SRobert Mustacchi * @san_mac_addr: SAN MAC address 3046*5fc77b81SRobert Mustacchi * 3047*5fc77b81SRobert Mustacchi * Reads the SAN MAC address from the EEPROM, if it's available. This is 3048*5fc77b81SRobert Mustacchi * per-port, so set_lan_id() must be called before reading the addresses. 3049*5fc77b81SRobert Mustacchi * set_lan_id() is called by identify_sfp(), but this cannot be relied 3050*5fc77b81SRobert Mustacchi * upon for non-SFP connections, so we must call it here. 3051*5fc77b81SRobert Mustacchi **/ 3052*5fc77b81SRobert Mustacchi s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3053*5fc77b81SRobert Mustacchi { 3054*5fc77b81SRobert Mustacchi u16 san_mac_data, san_mac_offset; 3055*5fc77b81SRobert Mustacchi u8 i; 3056*5fc77b81SRobert Mustacchi 3057*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3058*5fc77b81SRobert Mustacchi 3059*5fc77b81SRobert Mustacchi /* 3060*5fc77b81SRobert Mustacchi * First read the EEPROM pointer to see if the MAC addresses are 3061*5fc77b81SRobert Mustacchi * available. If they're not, no point in calling set_lan_id() here. 3062*5fc77b81SRobert Mustacchi */ 3063*5fc77b81SRobert Mustacchi (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3064*5fc77b81SRobert Mustacchi 3065*5fc77b81SRobert Mustacchi if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 3066*5fc77b81SRobert Mustacchi /* 3067*5fc77b81SRobert Mustacchi * No addresses available in this EEPROM. It's not an 3068*5fc77b81SRobert Mustacchi * error though, so just wipe the local address and return. 3069*5fc77b81SRobert Mustacchi */ 3070*5fc77b81SRobert Mustacchi for (i = 0; i < 6; i++) 3071*5fc77b81SRobert Mustacchi san_mac_addr[i] = 0xFF; 3072*5fc77b81SRobert Mustacchi 3073*5fc77b81SRobert Mustacchi goto san_mac_addr_out; 3074*5fc77b81SRobert Mustacchi } 3075*5fc77b81SRobert Mustacchi 3076*5fc77b81SRobert Mustacchi /* make sure we know which port we need to program */ 3077*5fc77b81SRobert Mustacchi hw->mac.ops.set_lan_id(hw); 3078*5fc77b81SRobert Mustacchi /* apply the port offset to the address offset */ 3079*5fc77b81SRobert Mustacchi (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3080*5fc77b81SRobert Mustacchi (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3081*5fc77b81SRobert Mustacchi for (i = 0; i < 3; i++) { 3082*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); 3083*5fc77b81SRobert Mustacchi san_mac_addr[i * 2] = (u8)(san_mac_data); 3084*5fc77b81SRobert Mustacchi san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3085*5fc77b81SRobert Mustacchi san_mac_offset++; 3086*5fc77b81SRobert Mustacchi } 3087*5fc77b81SRobert Mustacchi 3088*5fc77b81SRobert Mustacchi san_mac_addr_out: 3089*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3090*5fc77b81SRobert Mustacchi } 3091*5fc77b81SRobert Mustacchi 3092*5fc77b81SRobert Mustacchi /** 3093*5fc77b81SRobert Mustacchi * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3094*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3095*5fc77b81SRobert Mustacchi * @san_mac_addr: SAN MAC address 3096*5fc77b81SRobert Mustacchi * 3097*5fc77b81SRobert Mustacchi * Write a SAN MAC address to the EEPROM. 3098*5fc77b81SRobert Mustacchi **/ 3099*5fc77b81SRobert Mustacchi s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3100*5fc77b81SRobert Mustacchi { 3101*5fc77b81SRobert Mustacchi s32 status = IXGBE_SUCCESS; 3102*5fc77b81SRobert Mustacchi u16 san_mac_data, san_mac_offset; 3103*5fc77b81SRobert Mustacchi u8 i; 3104*5fc77b81SRobert Mustacchi 3105*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3106*5fc77b81SRobert Mustacchi 3107*5fc77b81SRobert Mustacchi /* Look for SAN mac address pointer. If not defined, return */ 3108*5fc77b81SRobert Mustacchi (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3109*5fc77b81SRobert Mustacchi 3110*5fc77b81SRobert Mustacchi if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 3111*5fc77b81SRobert Mustacchi status = IXGBE_ERR_NO_SAN_ADDR_PTR; 3112*5fc77b81SRobert Mustacchi goto san_mac_addr_out; 3113*5fc77b81SRobert Mustacchi } 3114*5fc77b81SRobert Mustacchi 3115*5fc77b81SRobert Mustacchi /* Make sure we know which port we need to write */ 3116*5fc77b81SRobert Mustacchi hw->mac.ops.set_lan_id(hw); 3117*5fc77b81SRobert Mustacchi /* Apply the port offset to the address offset */ 3118*5fc77b81SRobert Mustacchi (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3119*5fc77b81SRobert Mustacchi (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3120*5fc77b81SRobert Mustacchi 3121*5fc77b81SRobert Mustacchi for (i = 0; i < 3; i++) { 3122*5fc77b81SRobert Mustacchi san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3123*5fc77b81SRobert Mustacchi san_mac_data |= (u16)(san_mac_addr[i * 2]); 3124*5fc77b81SRobert Mustacchi hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3125*5fc77b81SRobert Mustacchi san_mac_offset++; 3126*5fc77b81SRobert Mustacchi } 3127*5fc77b81SRobert Mustacchi 3128*5fc77b81SRobert Mustacchi san_mac_addr_out: 3129*5fc77b81SRobert Mustacchi return status; 3130*5fc77b81SRobert Mustacchi } 3131*5fc77b81SRobert Mustacchi 3132*5fc77b81SRobert Mustacchi /** 3133*5fc77b81SRobert Mustacchi * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3134*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3135*5fc77b81SRobert Mustacchi * 3136*5fc77b81SRobert Mustacchi * Read PCIe configuration space, and get the MSI-X vector count from 3137*5fc77b81SRobert Mustacchi * the capabilities table. 3138*5fc77b81SRobert Mustacchi **/ 3139*5fc77b81SRobert Mustacchi u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3140*5fc77b81SRobert Mustacchi { 3141*5fc77b81SRobert Mustacchi u16 msix_count = 1; 3142*5fc77b81SRobert Mustacchi u16 max_msix_count; 3143*5fc77b81SRobert Mustacchi u16 pcie_offset; 3144*5fc77b81SRobert Mustacchi 3145*5fc77b81SRobert Mustacchi switch (hw->mac.type) { 3146*5fc77b81SRobert Mustacchi case ixgbe_mac_82598EB: 3147*5fc77b81SRobert Mustacchi pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3148*5fc77b81SRobert Mustacchi max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3149*5fc77b81SRobert Mustacchi break; 3150*5fc77b81SRobert Mustacchi case ixgbe_mac_82599EB: 3151*5fc77b81SRobert Mustacchi case ixgbe_mac_X540: 3152*5fc77b81SRobert Mustacchi pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3153*5fc77b81SRobert Mustacchi max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3154*5fc77b81SRobert Mustacchi break; 3155*5fc77b81SRobert Mustacchi default: 3156*5fc77b81SRobert Mustacchi return msix_count; 3157*5fc77b81SRobert Mustacchi } 3158*5fc77b81SRobert Mustacchi 3159*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3160*5fc77b81SRobert Mustacchi msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3161*5fc77b81SRobert Mustacchi msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3162*5fc77b81SRobert Mustacchi 3163*5fc77b81SRobert Mustacchi /* MSI-X count is zero-based in HW */ 3164*5fc77b81SRobert Mustacchi msix_count++; 3165*5fc77b81SRobert Mustacchi 3166*5fc77b81SRobert Mustacchi if (msix_count > max_msix_count) 3167*5fc77b81SRobert Mustacchi msix_count = max_msix_count; 3168*5fc77b81SRobert Mustacchi 3169*5fc77b81SRobert Mustacchi return msix_count; 3170*5fc77b81SRobert Mustacchi } 3171*5fc77b81SRobert Mustacchi 3172*5fc77b81SRobert Mustacchi /** 3173*5fc77b81SRobert Mustacchi * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3174*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3175*5fc77b81SRobert Mustacchi * @addr: Address to put into receive address register 3176*5fc77b81SRobert Mustacchi * @vmdq: VMDq pool to assign 3177*5fc77b81SRobert Mustacchi * 3178*5fc77b81SRobert Mustacchi * Puts an ethernet address into a receive address register, or 3179*5fc77b81SRobert Mustacchi * finds the rar that it is aleady in; adds to the pool list 3180*5fc77b81SRobert Mustacchi **/ 3181*5fc77b81SRobert Mustacchi s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3182*5fc77b81SRobert Mustacchi { 3183*5fc77b81SRobert Mustacchi static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3184*5fc77b81SRobert Mustacchi u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3185*5fc77b81SRobert Mustacchi u32 rar; 3186*5fc77b81SRobert Mustacchi u32 rar_low, rar_high; 3187*5fc77b81SRobert Mustacchi u32 addr_low, addr_high; 3188*5fc77b81SRobert Mustacchi 3189*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3190*5fc77b81SRobert Mustacchi 3191*5fc77b81SRobert Mustacchi /* swap bytes for HW little endian */ 3192*5fc77b81SRobert Mustacchi addr_low = addr[0] | (addr[1] << 8) 3193*5fc77b81SRobert Mustacchi | (addr[2] << 16) 3194*5fc77b81SRobert Mustacchi | (addr[3] << 24); 3195*5fc77b81SRobert Mustacchi addr_high = addr[4] | (addr[5] << 8); 3196*5fc77b81SRobert Mustacchi 3197*5fc77b81SRobert Mustacchi /* 3198*5fc77b81SRobert Mustacchi * Either find the mac_id in rar or find the first empty space. 3199*5fc77b81SRobert Mustacchi * rar_highwater points to just after the highest currently used 3200*5fc77b81SRobert Mustacchi * rar in order to shorten the search. It grows when we add a new 3201*5fc77b81SRobert Mustacchi * rar to the top. 3202*5fc77b81SRobert Mustacchi */ 3203*5fc77b81SRobert Mustacchi for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3204*5fc77b81SRobert Mustacchi rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3205*5fc77b81SRobert Mustacchi 3206*5fc77b81SRobert Mustacchi if (((IXGBE_RAH_AV & rar_high) == 0) 3207*5fc77b81SRobert Mustacchi && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3208*5fc77b81SRobert Mustacchi first_empty_rar = rar; 3209*5fc77b81SRobert Mustacchi } else if ((rar_high & 0xFFFF) == addr_high) { 3210*5fc77b81SRobert Mustacchi rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3211*5fc77b81SRobert Mustacchi if (rar_low == addr_low) 3212*5fc77b81SRobert Mustacchi break; /* found it already in the rars */ 3213*5fc77b81SRobert Mustacchi } 3214*5fc77b81SRobert Mustacchi } 3215*5fc77b81SRobert Mustacchi 3216*5fc77b81SRobert Mustacchi if (rar < hw->mac.rar_highwater) { 3217*5fc77b81SRobert Mustacchi /* already there so just add to the pool bits */ 3218*5fc77b81SRobert Mustacchi (void) ixgbe_set_vmdq(hw, rar, vmdq); 3219*5fc77b81SRobert Mustacchi } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3220*5fc77b81SRobert Mustacchi /* stick it into first empty RAR slot we found */ 3221*5fc77b81SRobert Mustacchi rar = first_empty_rar; 3222*5fc77b81SRobert Mustacchi (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3223*5fc77b81SRobert Mustacchi } else if (rar == hw->mac.rar_highwater) { 3224*5fc77b81SRobert Mustacchi /* add it to the top of the list and inc the highwater mark */ 3225*5fc77b81SRobert Mustacchi (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3226*5fc77b81SRobert Mustacchi hw->mac.rar_highwater++; 3227*5fc77b81SRobert Mustacchi } else if (rar >= hw->mac.num_rar_entries) { 3228*5fc77b81SRobert Mustacchi return IXGBE_ERR_INVALID_MAC_ADDR; 3229*5fc77b81SRobert Mustacchi } 3230*5fc77b81SRobert Mustacchi 3231*5fc77b81SRobert Mustacchi /* 3232*5fc77b81SRobert Mustacchi * If we found rar[0], make sure the default pool bit (we use pool 0) 3233*5fc77b81SRobert Mustacchi * remains cleared to be sure default pool packets will get delivered 3234*5fc77b81SRobert Mustacchi */ 3235*5fc77b81SRobert Mustacchi if (rar == 0) 3236*5fc77b81SRobert Mustacchi (void) ixgbe_clear_vmdq(hw, rar, 0); 3237*5fc77b81SRobert Mustacchi 3238*5fc77b81SRobert Mustacchi return rar; 3239*5fc77b81SRobert Mustacchi } 3240*5fc77b81SRobert Mustacchi 3241*5fc77b81SRobert Mustacchi /** 3242*5fc77b81SRobert Mustacchi * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3243*5fc77b81SRobert Mustacchi * @hw: pointer to hardware struct 3244*5fc77b81SRobert Mustacchi * @rar: receive address register index to disassociate 3245*5fc77b81SRobert Mustacchi * @vmdq: VMDq pool index to remove from the rar 3246*5fc77b81SRobert Mustacchi **/ 3247*5fc77b81SRobert Mustacchi s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3248*5fc77b81SRobert Mustacchi { 3249*5fc77b81SRobert Mustacchi u32 mpsar_lo, mpsar_hi; 3250*5fc77b81SRobert Mustacchi u32 rar_entries = hw->mac.num_rar_entries; 3251*5fc77b81SRobert Mustacchi 3252*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3253*5fc77b81SRobert Mustacchi 3254*5fc77b81SRobert Mustacchi /* Make sure we are using a valid rar index range */ 3255*5fc77b81SRobert Mustacchi if (rar >= rar_entries) { 3256*5fc77b81SRobert Mustacchi DEBUGOUT1("RAR index %d is out of range.\n", rar); 3257*5fc77b81SRobert Mustacchi return IXGBE_ERR_INVALID_ARGUMENT; 3258*5fc77b81SRobert Mustacchi } 3259*5fc77b81SRobert Mustacchi 3260*5fc77b81SRobert Mustacchi mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3261*5fc77b81SRobert Mustacchi mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3262*5fc77b81SRobert Mustacchi 3263*5fc77b81SRobert Mustacchi if (!mpsar_lo && !mpsar_hi) 3264*5fc77b81SRobert Mustacchi goto done; 3265*5fc77b81SRobert Mustacchi 3266*5fc77b81SRobert Mustacchi if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3267*5fc77b81SRobert Mustacchi if (mpsar_lo) { 3268*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3269*5fc77b81SRobert Mustacchi mpsar_lo = 0; 3270*5fc77b81SRobert Mustacchi } 3271*5fc77b81SRobert Mustacchi if (mpsar_hi) { 3272*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3273*5fc77b81SRobert Mustacchi mpsar_hi = 0; 3274*5fc77b81SRobert Mustacchi } 3275*5fc77b81SRobert Mustacchi } else if (vmdq < 32) { 3276*5fc77b81SRobert Mustacchi mpsar_lo &= ~(1 << vmdq); 3277*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3278*5fc77b81SRobert Mustacchi } else { 3279*5fc77b81SRobert Mustacchi mpsar_hi &= ~(1 << (vmdq - 32)); 3280*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3281*5fc77b81SRobert Mustacchi } 3282*5fc77b81SRobert Mustacchi 3283*5fc77b81SRobert Mustacchi /* was that the last pool using this rar? */ 3284*5fc77b81SRobert Mustacchi if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 3285*5fc77b81SRobert Mustacchi hw->mac.ops.clear_rar(hw, rar); 3286*5fc77b81SRobert Mustacchi done: 3287*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3288*5fc77b81SRobert Mustacchi } 3289*5fc77b81SRobert Mustacchi 3290*5fc77b81SRobert Mustacchi /** 3291*5fc77b81SRobert Mustacchi * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3292*5fc77b81SRobert Mustacchi * @hw: pointer to hardware struct 3293*5fc77b81SRobert Mustacchi * @rar: receive address register index to associate with a VMDq index 3294*5fc77b81SRobert Mustacchi * @vmdq: VMDq pool index 3295*5fc77b81SRobert Mustacchi **/ 3296*5fc77b81SRobert Mustacchi s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3297*5fc77b81SRobert Mustacchi { 3298*5fc77b81SRobert Mustacchi u32 mpsar; 3299*5fc77b81SRobert Mustacchi u32 rar_entries = hw->mac.num_rar_entries; 3300*5fc77b81SRobert Mustacchi 3301*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_set_vmdq_generic"); 3302*5fc77b81SRobert Mustacchi 3303*5fc77b81SRobert Mustacchi /* Make sure we are using a valid rar index range */ 3304*5fc77b81SRobert Mustacchi if (rar >= rar_entries) { 3305*5fc77b81SRobert Mustacchi DEBUGOUT1("RAR index %d is out of range.\n", rar); 3306*5fc77b81SRobert Mustacchi return IXGBE_ERR_INVALID_ARGUMENT; 3307*5fc77b81SRobert Mustacchi } 3308*5fc77b81SRobert Mustacchi 3309*5fc77b81SRobert Mustacchi if (vmdq < 32) { 3310*5fc77b81SRobert Mustacchi mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3311*5fc77b81SRobert Mustacchi mpsar |= 1 << vmdq; 3312*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3313*5fc77b81SRobert Mustacchi } else { 3314*5fc77b81SRobert Mustacchi mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3315*5fc77b81SRobert Mustacchi mpsar |= 1 << (vmdq - 32); 3316*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3317*5fc77b81SRobert Mustacchi } 3318*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3319*5fc77b81SRobert Mustacchi } 3320*5fc77b81SRobert Mustacchi 3321*5fc77b81SRobert Mustacchi /** 3322*5fc77b81SRobert Mustacchi * This function should only be involved in the IOV mode. 3323*5fc77b81SRobert Mustacchi * In IOV mode, Default pool is next pool after the number of 3324*5fc77b81SRobert Mustacchi * VFs advertized and not 0. 3325*5fc77b81SRobert Mustacchi * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3326*5fc77b81SRobert Mustacchi * 3327*5fc77b81SRobert Mustacchi * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3328*5fc77b81SRobert Mustacchi * @hw: pointer to hardware struct 3329*5fc77b81SRobert Mustacchi * @vmdq: VMDq pool index 3330*5fc77b81SRobert Mustacchi **/ 3331*5fc77b81SRobert Mustacchi s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3332*5fc77b81SRobert Mustacchi { 3333*5fc77b81SRobert Mustacchi u32 rar = hw->mac.san_mac_rar_index; 3334*5fc77b81SRobert Mustacchi 3335*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3336*5fc77b81SRobert Mustacchi 3337*5fc77b81SRobert Mustacchi if (vmdq < 32) { 3338*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3339*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3340*5fc77b81SRobert Mustacchi } else { 3341*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3342*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3343*5fc77b81SRobert Mustacchi } 3344*5fc77b81SRobert Mustacchi 3345*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3346*5fc77b81SRobert Mustacchi } 3347*5fc77b81SRobert Mustacchi 3348*5fc77b81SRobert Mustacchi /** 3349*5fc77b81SRobert Mustacchi * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3350*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3351*5fc77b81SRobert Mustacchi **/ 3352*5fc77b81SRobert Mustacchi s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3353*5fc77b81SRobert Mustacchi { 3354*5fc77b81SRobert Mustacchi int i; 3355*5fc77b81SRobert Mustacchi 3356*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3357*5fc77b81SRobert Mustacchi DEBUGOUT(" Clearing UTA\n"); 3358*5fc77b81SRobert Mustacchi 3359*5fc77b81SRobert Mustacchi for (i = 0; i < 128; i++) 3360*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3361*5fc77b81SRobert Mustacchi 3362*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3363*5fc77b81SRobert Mustacchi } 3364*5fc77b81SRobert Mustacchi 3365*5fc77b81SRobert Mustacchi /** 3366*5fc77b81SRobert Mustacchi * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3367*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3368*5fc77b81SRobert Mustacchi * @vlan: VLAN id to write to VLAN filter 3369*5fc77b81SRobert Mustacchi * 3370*5fc77b81SRobert Mustacchi * return the VLVF index where this VLAN id should be placed 3371*5fc77b81SRobert Mustacchi * 3372*5fc77b81SRobert Mustacchi **/ 3373*5fc77b81SRobert Mustacchi s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 3374*5fc77b81SRobert Mustacchi { 3375*5fc77b81SRobert Mustacchi u32 bits = 0; 3376*5fc77b81SRobert Mustacchi u32 first_empty_slot = 0; 3377*5fc77b81SRobert Mustacchi s32 regindex; 3378*5fc77b81SRobert Mustacchi 3379*5fc77b81SRobert Mustacchi /* short cut the special case */ 3380*5fc77b81SRobert Mustacchi if (vlan == 0) 3381*5fc77b81SRobert Mustacchi return 0; 3382*5fc77b81SRobert Mustacchi 3383*5fc77b81SRobert Mustacchi /* 3384*5fc77b81SRobert Mustacchi * Search for the vlan id in the VLVF entries. Save off the first empty 3385*5fc77b81SRobert Mustacchi * slot found along the way 3386*5fc77b81SRobert Mustacchi */ 3387*5fc77b81SRobert Mustacchi for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 3388*5fc77b81SRobert Mustacchi bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3389*5fc77b81SRobert Mustacchi if (!bits && !(first_empty_slot)) 3390*5fc77b81SRobert Mustacchi first_empty_slot = regindex; 3391*5fc77b81SRobert Mustacchi else if ((bits & 0x0FFF) == vlan) 3392*5fc77b81SRobert Mustacchi break; 3393*5fc77b81SRobert Mustacchi } 3394*5fc77b81SRobert Mustacchi 3395*5fc77b81SRobert Mustacchi /* 3396*5fc77b81SRobert Mustacchi * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 3397*5fc77b81SRobert Mustacchi * in the VLVF. Else use the first empty VLVF register for this 3398*5fc77b81SRobert Mustacchi * vlan id. 3399*5fc77b81SRobert Mustacchi */ 3400*5fc77b81SRobert Mustacchi if (regindex >= IXGBE_VLVF_ENTRIES) { 3401*5fc77b81SRobert Mustacchi if (first_empty_slot) 3402*5fc77b81SRobert Mustacchi regindex = first_empty_slot; 3403*5fc77b81SRobert Mustacchi else { 3404*5fc77b81SRobert Mustacchi DEBUGOUT("No space in VLVF.\n"); 3405*5fc77b81SRobert Mustacchi regindex = IXGBE_ERR_NO_SPACE; 3406*5fc77b81SRobert Mustacchi } 3407*5fc77b81SRobert Mustacchi } 3408*5fc77b81SRobert Mustacchi 3409*5fc77b81SRobert Mustacchi return regindex; 3410*5fc77b81SRobert Mustacchi } 3411*5fc77b81SRobert Mustacchi 3412*5fc77b81SRobert Mustacchi /** 3413*5fc77b81SRobert Mustacchi * ixgbe_set_vfta_generic - Set VLAN filter table 3414*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3415*5fc77b81SRobert Mustacchi * @vlan: VLAN id to write to VLAN filter 3416*5fc77b81SRobert Mustacchi * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3417*5fc77b81SRobert Mustacchi * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3418*5fc77b81SRobert Mustacchi * 3419*5fc77b81SRobert Mustacchi * Turn on/off specified VLAN in the VLAN filter table. 3420*5fc77b81SRobert Mustacchi **/ 3421*5fc77b81SRobert Mustacchi s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3422*5fc77b81SRobert Mustacchi bool vlan_on) 3423*5fc77b81SRobert Mustacchi { 3424*5fc77b81SRobert Mustacchi s32 regindex; 3425*5fc77b81SRobert Mustacchi u32 bitindex; 3426*5fc77b81SRobert Mustacchi u32 vfta; 3427*5fc77b81SRobert Mustacchi u32 targetbit; 3428*5fc77b81SRobert Mustacchi s32 ret_val = IXGBE_SUCCESS; 3429*5fc77b81SRobert Mustacchi bool vfta_changed = FALSE; 3430*5fc77b81SRobert Mustacchi 3431*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_set_vfta_generic"); 3432*5fc77b81SRobert Mustacchi 3433*5fc77b81SRobert Mustacchi if (vlan > 4095) 3434*5fc77b81SRobert Mustacchi return IXGBE_ERR_PARAM; 3435*5fc77b81SRobert Mustacchi 3436*5fc77b81SRobert Mustacchi /* 3437*5fc77b81SRobert Mustacchi * this is a 2 part operation - first the VFTA, then the 3438*5fc77b81SRobert Mustacchi * VLVF and VLVFB if VT Mode is set 3439*5fc77b81SRobert Mustacchi * We don't write the VFTA until we know the VLVF part succeeded. 3440*5fc77b81SRobert Mustacchi */ 3441*5fc77b81SRobert Mustacchi 3442*5fc77b81SRobert Mustacchi /* Part 1 3443*5fc77b81SRobert Mustacchi * The VFTA is a bitstring made up of 128 32-bit registers 3444*5fc77b81SRobert Mustacchi * that enable the particular VLAN id, much like the MTA: 3445*5fc77b81SRobert Mustacchi * bits[11-5]: which register 3446*5fc77b81SRobert Mustacchi * bits[4-0]: which bit in the register 3447*5fc77b81SRobert Mustacchi */ 3448*5fc77b81SRobert Mustacchi regindex = (vlan >> 5) & 0x7F; 3449*5fc77b81SRobert Mustacchi bitindex = vlan & 0x1F; 3450*5fc77b81SRobert Mustacchi targetbit = (1 << bitindex); 3451*5fc77b81SRobert Mustacchi vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 3452*5fc77b81SRobert Mustacchi 3453*5fc77b81SRobert Mustacchi if (vlan_on) { 3454*5fc77b81SRobert Mustacchi if (!(vfta & targetbit)) { 3455*5fc77b81SRobert Mustacchi vfta |= targetbit; 3456*5fc77b81SRobert Mustacchi vfta_changed = TRUE; 3457*5fc77b81SRobert Mustacchi } 3458*5fc77b81SRobert Mustacchi } else { 3459*5fc77b81SRobert Mustacchi if ((vfta & targetbit)) { 3460*5fc77b81SRobert Mustacchi vfta &= ~targetbit; 3461*5fc77b81SRobert Mustacchi vfta_changed = TRUE; 3462*5fc77b81SRobert Mustacchi } 3463*5fc77b81SRobert Mustacchi } 3464*5fc77b81SRobert Mustacchi 3465*5fc77b81SRobert Mustacchi /* Part 2 3466*5fc77b81SRobert Mustacchi * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 3467*5fc77b81SRobert Mustacchi */ 3468*5fc77b81SRobert Mustacchi ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, 3469*5fc77b81SRobert Mustacchi &vfta_changed); 3470*5fc77b81SRobert Mustacchi if (ret_val != IXGBE_SUCCESS) 3471*5fc77b81SRobert Mustacchi return ret_val; 3472*5fc77b81SRobert Mustacchi 3473*5fc77b81SRobert Mustacchi if (vfta_changed) 3474*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); 3475*5fc77b81SRobert Mustacchi 3476*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3477*5fc77b81SRobert Mustacchi } 3478*5fc77b81SRobert Mustacchi 3479*5fc77b81SRobert Mustacchi /** 3480*5fc77b81SRobert Mustacchi * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 3481*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3482*5fc77b81SRobert Mustacchi * @vlan: VLAN id to write to VLAN filter 3483*5fc77b81SRobert Mustacchi * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3484*5fc77b81SRobert Mustacchi * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3485*5fc77b81SRobert Mustacchi * @vfta_changed: pointer to boolean flag which indicates whether VFTA 3486*5fc77b81SRobert Mustacchi * should be changed 3487*5fc77b81SRobert Mustacchi * 3488*5fc77b81SRobert Mustacchi * Turn on/off specified bit in VLVF table. 3489*5fc77b81SRobert Mustacchi **/ 3490*5fc77b81SRobert Mustacchi s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3491*5fc77b81SRobert Mustacchi bool vlan_on, bool *vfta_changed) 3492*5fc77b81SRobert Mustacchi { 3493*5fc77b81SRobert Mustacchi u32 vt; 3494*5fc77b81SRobert Mustacchi 3495*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_set_vlvf_generic"); 3496*5fc77b81SRobert Mustacchi 3497*5fc77b81SRobert Mustacchi if (vlan > 4095) 3498*5fc77b81SRobert Mustacchi return IXGBE_ERR_PARAM; 3499*5fc77b81SRobert Mustacchi 3500*5fc77b81SRobert Mustacchi /* If VT Mode is set 3501*5fc77b81SRobert Mustacchi * Either vlan_on 3502*5fc77b81SRobert Mustacchi * make sure the vlan is in VLVF 3503*5fc77b81SRobert Mustacchi * set the vind bit in the matching VLVFB 3504*5fc77b81SRobert Mustacchi * Or !vlan_on 3505*5fc77b81SRobert Mustacchi * clear the pool bit and possibly the vind 3506*5fc77b81SRobert Mustacchi */ 3507*5fc77b81SRobert Mustacchi vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3508*5fc77b81SRobert Mustacchi if (vt & IXGBE_VT_CTL_VT_ENABLE) { 3509*5fc77b81SRobert Mustacchi s32 vlvf_index; 3510*5fc77b81SRobert Mustacchi u32 bits; 3511*5fc77b81SRobert Mustacchi 3512*5fc77b81SRobert Mustacchi vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); 3513*5fc77b81SRobert Mustacchi if (vlvf_index < 0) 3514*5fc77b81SRobert Mustacchi return vlvf_index; 3515*5fc77b81SRobert Mustacchi 3516*5fc77b81SRobert Mustacchi if (vlan_on) { 3517*5fc77b81SRobert Mustacchi /* set the pool bit */ 3518*5fc77b81SRobert Mustacchi if (vind < 32) { 3519*5fc77b81SRobert Mustacchi bits = IXGBE_READ_REG(hw, 3520*5fc77b81SRobert Mustacchi IXGBE_VLVFB(vlvf_index * 2)); 3521*5fc77b81SRobert Mustacchi bits |= (1 << vind); 3522*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, 3523*5fc77b81SRobert Mustacchi IXGBE_VLVFB(vlvf_index * 2), 3524*5fc77b81SRobert Mustacchi bits); 3525*5fc77b81SRobert Mustacchi } else { 3526*5fc77b81SRobert Mustacchi bits = IXGBE_READ_REG(hw, 3527*5fc77b81SRobert Mustacchi IXGBE_VLVFB((vlvf_index * 2) + 1)); 3528*5fc77b81SRobert Mustacchi bits |= (1 << (vind - 32)); 3529*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, 3530*5fc77b81SRobert Mustacchi IXGBE_VLVFB((vlvf_index * 2) + 1), 3531*5fc77b81SRobert Mustacchi bits); 3532*5fc77b81SRobert Mustacchi } 3533*5fc77b81SRobert Mustacchi } else { 3534*5fc77b81SRobert Mustacchi /* clear the pool bit */ 3535*5fc77b81SRobert Mustacchi if (vind < 32) { 3536*5fc77b81SRobert Mustacchi bits = IXGBE_READ_REG(hw, 3537*5fc77b81SRobert Mustacchi IXGBE_VLVFB(vlvf_index * 2)); 3538*5fc77b81SRobert Mustacchi bits &= ~(1 << vind); 3539*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, 3540*5fc77b81SRobert Mustacchi IXGBE_VLVFB(vlvf_index * 2), 3541*5fc77b81SRobert Mustacchi bits); 3542*5fc77b81SRobert Mustacchi bits |= IXGBE_READ_REG(hw, 3543*5fc77b81SRobert Mustacchi IXGBE_VLVFB((vlvf_index * 2) + 1)); 3544*5fc77b81SRobert Mustacchi } else { 3545*5fc77b81SRobert Mustacchi bits = IXGBE_READ_REG(hw, 3546*5fc77b81SRobert Mustacchi IXGBE_VLVFB((vlvf_index * 2) + 1)); 3547*5fc77b81SRobert Mustacchi bits &= ~(1 << (vind - 32)); 3548*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, 3549*5fc77b81SRobert Mustacchi IXGBE_VLVFB((vlvf_index * 2) + 1), 3550*5fc77b81SRobert Mustacchi bits); 3551*5fc77b81SRobert Mustacchi bits |= IXGBE_READ_REG(hw, 3552*5fc77b81SRobert Mustacchi IXGBE_VLVFB(vlvf_index * 2)); 3553*5fc77b81SRobert Mustacchi } 3554*5fc77b81SRobert Mustacchi } 3555*5fc77b81SRobert Mustacchi 3556*5fc77b81SRobert Mustacchi /* 3557*5fc77b81SRobert Mustacchi * If there are still bits set in the VLVFB registers 3558*5fc77b81SRobert Mustacchi * for the VLAN ID indicated we need to see if the 3559*5fc77b81SRobert Mustacchi * caller is requesting that we clear the VFTA entry bit. 3560*5fc77b81SRobert Mustacchi * If the caller has requested that we clear the VFTA 3561*5fc77b81SRobert Mustacchi * entry bit but there are still pools/VFs using this VLAN 3562*5fc77b81SRobert Mustacchi * ID entry then ignore the request. We're not worried 3563*5fc77b81SRobert Mustacchi * about the case where we're turning the VFTA VLAN ID 3564*5fc77b81SRobert Mustacchi * entry bit on, only when requested to turn it off as 3565*5fc77b81SRobert Mustacchi * there may be multiple pools and/or VFs using the 3566*5fc77b81SRobert Mustacchi * VLAN ID entry. In that case we cannot clear the 3567*5fc77b81SRobert Mustacchi * VFTA bit until all pools/VFs using that VLAN ID have also 3568*5fc77b81SRobert Mustacchi * been cleared. This will be indicated by "bits" being 3569*5fc77b81SRobert Mustacchi * zero. 3570*5fc77b81SRobert Mustacchi */ 3571*5fc77b81SRobert Mustacchi if (bits) { 3572*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 3573*5fc77b81SRobert Mustacchi (IXGBE_VLVF_VIEN | vlan)); 3574*5fc77b81SRobert Mustacchi if ((!vlan_on) && (vfta_changed != NULL)) { 3575*5fc77b81SRobert Mustacchi /* someone wants to clear the vfta entry 3576*5fc77b81SRobert Mustacchi * but some pools/VFs are still using it. 3577*5fc77b81SRobert Mustacchi * Ignore it. */ 3578*5fc77b81SRobert Mustacchi *vfta_changed = FALSE; 3579*5fc77b81SRobert Mustacchi } 3580*5fc77b81SRobert Mustacchi } else 3581*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3582*5fc77b81SRobert Mustacchi } 3583*5fc77b81SRobert Mustacchi 3584*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3585*5fc77b81SRobert Mustacchi } 3586*5fc77b81SRobert Mustacchi 3587*5fc77b81SRobert Mustacchi /** 3588*5fc77b81SRobert Mustacchi * ixgbe_clear_vfta_generic - Clear VLAN filter table 3589*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3590*5fc77b81SRobert Mustacchi * 3591*5fc77b81SRobert Mustacchi * Clears the VLAN filer table, and the VMDq index associated with the filter 3592*5fc77b81SRobert Mustacchi **/ 3593*5fc77b81SRobert Mustacchi s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3594*5fc77b81SRobert Mustacchi { 3595*5fc77b81SRobert Mustacchi u32 offset; 3596*5fc77b81SRobert Mustacchi 3597*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_clear_vfta_generic"); 3598*5fc77b81SRobert Mustacchi 3599*5fc77b81SRobert Mustacchi for (offset = 0; offset < hw->mac.vft_size; offset++) 3600*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3601*5fc77b81SRobert Mustacchi 3602*5fc77b81SRobert Mustacchi for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3603*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3604*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 3605*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); 3606*5fc77b81SRobert Mustacchi } 3607*5fc77b81SRobert Mustacchi 3608*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3609*5fc77b81SRobert Mustacchi } 3610*5fc77b81SRobert Mustacchi 3611*5fc77b81SRobert Mustacchi /** 3612*5fc77b81SRobert Mustacchi * ixgbe_check_mac_link_generic - Determine link and speed status 3613*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3614*5fc77b81SRobert Mustacchi * @speed: pointer to link speed 3615*5fc77b81SRobert Mustacchi * @link_up: TRUE when link is up 3616*5fc77b81SRobert Mustacchi * @link_up_wait_to_complete: bool used to wait for link up or not 3617*5fc77b81SRobert Mustacchi * 3618*5fc77b81SRobert Mustacchi * Reads the links register to determine if link is up and the current speed 3619*5fc77b81SRobert Mustacchi **/ 3620*5fc77b81SRobert Mustacchi s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3621*5fc77b81SRobert Mustacchi bool *link_up, bool link_up_wait_to_complete) 3622*5fc77b81SRobert Mustacchi { 3623*5fc77b81SRobert Mustacchi u32 links_reg, links_orig; 3624*5fc77b81SRobert Mustacchi u32 i; 3625*5fc77b81SRobert Mustacchi 3626*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_check_mac_link_generic"); 3627*5fc77b81SRobert Mustacchi 3628*5fc77b81SRobert Mustacchi /* clear the old state */ 3629*5fc77b81SRobert Mustacchi links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 3630*5fc77b81SRobert Mustacchi 3631*5fc77b81SRobert Mustacchi links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3632*5fc77b81SRobert Mustacchi 3633*5fc77b81SRobert Mustacchi if (links_orig != links_reg) { 3634*5fc77b81SRobert Mustacchi DEBUGOUT2("LINKS changed from %08X to %08X\n", 3635*5fc77b81SRobert Mustacchi links_orig, links_reg); 3636*5fc77b81SRobert Mustacchi } 3637*5fc77b81SRobert Mustacchi 3638*5fc77b81SRobert Mustacchi if (link_up_wait_to_complete) { 3639*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 3640*5fc77b81SRobert Mustacchi if (links_reg & IXGBE_LINKS_UP) { 3641*5fc77b81SRobert Mustacchi *link_up = TRUE; 3642*5fc77b81SRobert Mustacchi break; 3643*5fc77b81SRobert Mustacchi } else { 3644*5fc77b81SRobert Mustacchi *link_up = FALSE; 3645*5fc77b81SRobert Mustacchi } 3646*5fc77b81SRobert Mustacchi msec_delay(100); 3647*5fc77b81SRobert Mustacchi links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 3648*5fc77b81SRobert Mustacchi } 3649*5fc77b81SRobert Mustacchi } else { 3650*5fc77b81SRobert Mustacchi if (links_reg & IXGBE_LINKS_UP) 3651*5fc77b81SRobert Mustacchi *link_up = TRUE; 3652*5fc77b81SRobert Mustacchi else 3653*5fc77b81SRobert Mustacchi *link_up = FALSE; 3654*5fc77b81SRobert Mustacchi } 3655*5fc77b81SRobert Mustacchi 3656*5fc77b81SRobert Mustacchi if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3657*5fc77b81SRobert Mustacchi IXGBE_LINKS_SPEED_10G_82599) 3658*5fc77b81SRobert Mustacchi *speed = IXGBE_LINK_SPEED_10GB_FULL; 3659*5fc77b81SRobert Mustacchi else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3660*5fc77b81SRobert Mustacchi IXGBE_LINKS_SPEED_1G_82599) 3661*5fc77b81SRobert Mustacchi *speed = IXGBE_LINK_SPEED_1GB_FULL; 3662*5fc77b81SRobert Mustacchi else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 3663*5fc77b81SRobert Mustacchi IXGBE_LINKS_SPEED_100_82599) 3664*5fc77b81SRobert Mustacchi *speed = IXGBE_LINK_SPEED_100_FULL; 3665*5fc77b81SRobert Mustacchi else 3666*5fc77b81SRobert Mustacchi *speed = IXGBE_LINK_SPEED_UNKNOWN; 3667*5fc77b81SRobert Mustacchi 3668*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3669*5fc77b81SRobert Mustacchi } 3670*5fc77b81SRobert Mustacchi 3671*5fc77b81SRobert Mustacchi /** 3672*5fc77b81SRobert Mustacchi * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 3673*5fc77b81SRobert Mustacchi * the EEPROM 3674*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3675*5fc77b81SRobert Mustacchi * @wwnn_prefix: the alternative WWNN prefix 3676*5fc77b81SRobert Mustacchi * @wwpn_prefix: the alternative WWPN prefix 3677*5fc77b81SRobert Mustacchi * 3678*5fc77b81SRobert Mustacchi * This function will read the EEPROM from the alternative SAN MAC address 3679*5fc77b81SRobert Mustacchi * block to check the support for the alternative WWNN/WWPN prefix support. 3680*5fc77b81SRobert Mustacchi **/ 3681*5fc77b81SRobert Mustacchi s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3682*5fc77b81SRobert Mustacchi u16 *wwpn_prefix) 3683*5fc77b81SRobert Mustacchi { 3684*5fc77b81SRobert Mustacchi u16 offset, caps; 3685*5fc77b81SRobert Mustacchi u16 alt_san_mac_blk_offset; 3686*5fc77b81SRobert Mustacchi 3687*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 3688*5fc77b81SRobert Mustacchi 3689*5fc77b81SRobert Mustacchi /* clear output first */ 3690*5fc77b81SRobert Mustacchi *wwnn_prefix = 0xFFFF; 3691*5fc77b81SRobert Mustacchi *wwpn_prefix = 0xFFFF; 3692*5fc77b81SRobert Mustacchi 3693*5fc77b81SRobert Mustacchi /* check if alternative SAN MAC is supported */ 3694*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR, 3695*5fc77b81SRobert Mustacchi &alt_san_mac_blk_offset); 3696*5fc77b81SRobert Mustacchi 3697*5fc77b81SRobert Mustacchi if ((alt_san_mac_blk_offset == 0) || 3698*5fc77b81SRobert Mustacchi (alt_san_mac_blk_offset == 0xFFFF)) 3699*5fc77b81SRobert Mustacchi goto wwn_prefix_out; 3700*5fc77b81SRobert Mustacchi 3701*5fc77b81SRobert Mustacchi /* check capability in alternative san mac address block */ 3702*5fc77b81SRobert Mustacchi offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3703*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, offset, &caps); 3704*5fc77b81SRobert Mustacchi if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3705*5fc77b81SRobert Mustacchi goto wwn_prefix_out; 3706*5fc77b81SRobert Mustacchi 3707*5fc77b81SRobert Mustacchi /* get the corresponding prefix for WWNN/WWPN */ 3708*5fc77b81SRobert Mustacchi offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3709*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, offset, wwnn_prefix); 3710*5fc77b81SRobert Mustacchi 3711*5fc77b81SRobert Mustacchi offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3712*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, offset, wwpn_prefix); 3713*5fc77b81SRobert Mustacchi 3714*5fc77b81SRobert Mustacchi wwn_prefix_out: 3715*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3716*5fc77b81SRobert Mustacchi } 3717*5fc77b81SRobert Mustacchi 3718*5fc77b81SRobert Mustacchi /** 3719*5fc77b81SRobert Mustacchi * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 3720*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3721*5fc77b81SRobert Mustacchi * @bs: the fcoe boot status 3722*5fc77b81SRobert Mustacchi * 3723*5fc77b81SRobert Mustacchi * This function will read the FCOE boot status from the iSCSI FCOE block 3724*5fc77b81SRobert Mustacchi **/ 3725*5fc77b81SRobert Mustacchi s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 3726*5fc77b81SRobert Mustacchi { 3727*5fc77b81SRobert Mustacchi u16 offset, caps, flags; 3728*5fc77b81SRobert Mustacchi s32 status; 3729*5fc77b81SRobert Mustacchi 3730*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 3731*5fc77b81SRobert Mustacchi 3732*5fc77b81SRobert Mustacchi /* clear output first */ 3733*5fc77b81SRobert Mustacchi *bs = ixgbe_fcoe_bootstatus_unavailable; 3734*5fc77b81SRobert Mustacchi 3735*5fc77b81SRobert Mustacchi /* check if FCOE IBA block is present */ 3736*5fc77b81SRobert Mustacchi offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 3737*5fc77b81SRobert Mustacchi status = hw->eeprom.ops.read(hw, offset, &caps); 3738*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) 3739*5fc77b81SRobert Mustacchi goto out; 3740*5fc77b81SRobert Mustacchi 3741*5fc77b81SRobert Mustacchi if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 3742*5fc77b81SRobert Mustacchi goto out; 3743*5fc77b81SRobert Mustacchi 3744*5fc77b81SRobert Mustacchi /* check if iSCSI FCOE block is populated */ 3745*5fc77b81SRobert Mustacchi status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 3746*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) 3747*5fc77b81SRobert Mustacchi goto out; 3748*5fc77b81SRobert Mustacchi 3749*5fc77b81SRobert Mustacchi if ((offset == 0) || (offset == 0xFFFF)) 3750*5fc77b81SRobert Mustacchi goto out; 3751*5fc77b81SRobert Mustacchi 3752*5fc77b81SRobert Mustacchi /* read fcoe flags in iSCSI FCOE block */ 3753*5fc77b81SRobert Mustacchi offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 3754*5fc77b81SRobert Mustacchi status = hw->eeprom.ops.read(hw, offset, &flags); 3755*5fc77b81SRobert Mustacchi if (status != IXGBE_SUCCESS) 3756*5fc77b81SRobert Mustacchi goto out; 3757*5fc77b81SRobert Mustacchi 3758*5fc77b81SRobert Mustacchi if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 3759*5fc77b81SRobert Mustacchi *bs = ixgbe_fcoe_bootstatus_enabled; 3760*5fc77b81SRobert Mustacchi else 3761*5fc77b81SRobert Mustacchi *bs = ixgbe_fcoe_bootstatus_disabled; 3762*5fc77b81SRobert Mustacchi 3763*5fc77b81SRobert Mustacchi out: 3764*5fc77b81SRobert Mustacchi return status; 3765*5fc77b81SRobert Mustacchi } 3766*5fc77b81SRobert Mustacchi 3767*5fc77b81SRobert Mustacchi /** 3768*5fc77b81SRobert Mustacchi * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 3769*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3770*5fc77b81SRobert Mustacchi * @enable: enable or disable switch for anti-spoofing 3771*5fc77b81SRobert Mustacchi * @pf: Physical Function pool - do not enable anti-spoofing for the PF 3772*5fc77b81SRobert Mustacchi * 3773*5fc77b81SRobert Mustacchi **/ 3774*5fc77b81SRobert Mustacchi void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) 3775*5fc77b81SRobert Mustacchi { 3776*5fc77b81SRobert Mustacchi int j; 3777*5fc77b81SRobert Mustacchi int pf_target_reg = pf >> 3; 3778*5fc77b81SRobert Mustacchi int pf_target_shift = pf % 8; 3779*5fc77b81SRobert Mustacchi u32 pfvfspoof = 0; 3780*5fc77b81SRobert Mustacchi 3781*5fc77b81SRobert Mustacchi if (hw->mac.type == ixgbe_mac_82598EB) 3782*5fc77b81SRobert Mustacchi return; 3783*5fc77b81SRobert Mustacchi 3784*5fc77b81SRobert Mustacchi if (enable) 3785*5fc77b81SRobert Mustacchi pfvfspoof = IXGBE_SPOOF_MACAS_MASK; 3786*5fc77b81SRobert Mustacchi 3787*5fc77b81SRobert Mustacchi /* 3788*5fc77b81SRobert Mustacchi * PFVFSPOOF register array is size 8 with 8 bits assigned to 3789*5fc77b81SRobert Mustacchi * MAC anti-spoof enables in each register array element. 3790*5fc77b81SRobert Mustacchi */ 3791*5fc77b81SRobert Mustacchi for (j = 0; j < pf_target_reg; j++) 3792*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 3793*5fc77b81SRobert Mustacchi 3794*5fc77b81SRobert Mustacchi /* 3795*5fc77b81SRobert Mustacchi * The PF should be allowed to spoof so that it can support 3796*5fc77b81SRobert Mustacchi * emulation mode NICs. Do not set the bits assigned to the PF 3797*5fc77b81SRobert Mustacchi */ 3798*5fc77b81SRobert Mustacchi pfvfspoof &= (1 << pf_target_shift) - 1; 3799*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 3800*5fc77b81SRobert Mustacchi 3801*5fc77b81SRobert Mustacchi /* 3802*5fc77b81SRobert Mustacchi * Remaining pools belong to the PF so they do not need to have 3803*5fc77b81SRobert Mustacchi * anti-spoofing enabled. 3804*5fc77b81SRobert Mustacchi */ 3805*5fc77b81SRobert Mustacchi for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++) 3806*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0); 3807*5fc77b81SRobert Mustacchi } 3808*5fc77b81SRobert Mustacchi 3809*5fc77b81SRobert Mustacchi /** 3810*5fc77b81SRobert Mustacchi * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 3811*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3812*5fc77b81SRobert Mustacchi * @enable: enable or disable switch for VLAN anti-spoofing 3813*5fc77b81SRobert Mustacchi * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 3814*5fc77b81SRobert Mustacchi * 3815*5fc77b81SRobert Mustacchi **/ 3816*5fc77b81SRobert Mustacchi void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 3817*5fc77b81SRobert Mustacchi { 3818*5fc77b81SRobert Mustacchi int vf_target_reg = vf >> 3; 3819*5fc77b81SRobert Mustacchi int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 3820*5fc77b81SRobert Mustacchi u32 pfvfspoof; 3821*5fc77b81SRobert Mustacchi 3822*5fc77b81SRobert Mustacchi if (hw->mac.type == ixgbe_mac_82598EB) 3823*5fc77b81SRobert Mustacchi return; 3824*5fc77b81SRobert Mustacchi 3825*5fc77b81SRobert Mustacchi pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3826*5fc77b81SRobert Mustacchi if (enable) 3827*5fc77b81SRobert Mustacchi pfvfspoof |= (1 << vf_target_shift); 3828*5fc77b81SRobert Mustacchi else 3829*5fc77b81SRobert Mustacchi pfvfspoof &= ~(1 << vf_target_shift); 3830*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3831*5fc77b81SRobert Mustacchi } 3832*5fc77b81SRobert Mustacchi 3833*5fc77b81SRobert Mustacchi /** 3834*5fc77b81SRobert Mustacchi * ixgbe_get_device_caps_generic - Get additional device capabilities 3835*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3836*5fc77b81SRobert Mustacchi * @device_caps: the EEPROM word with the extra device capabilities 3837*5fc77b81SRobert Mustacchi * 3838*5fc77b81SRobert Mustacchi * This function will read the EEPROM location for the device capabilities, 3839*5fc77b81SRobert Mustacchi * and return the word through device_caps. 3840*5fc77b81SRobert Mustacchi **/ 3841*5fc77b81SRobert Mustacchi s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 3842*5fc77b81SRobert Mustacchi { 3843*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_get_device_caps_generic"); 3844*5fc77b81SRobert Mustacchi 3845*5fc77b81SRobert Mustacchi hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 3846*5fc77b81SRobert Mustacchi 3847*5fc77b81SRobert Mustacchi return IXGBE_SUCCESS; 3848*5fc77b81SRobert Mustacchi } 3849*5fc77b81SRobert Mustacchi 3850*5fc77b81SRobert Mustacchi /** 3851*5fc77b81SRobert Mustacchi * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 3852*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 3853*5fc77b81SRobert Mustacchi * 3854*5fc77b81SRobert Mustacchi **/ 3855*5fc77b81SRobert Mustacchi void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 3856*5fc77b81SRobert Mustacchi { 3857*5fc77b81SRobert Mustacchi u32 regval; 3858*5fc77b81SRobert Mustacchi u32 i; 3859*5fc77b81SRobert Mustacchi 3860*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 3861*5fc77b81SRobert Mustacchi 3862*5fc77b81SRobert Mustacchi /* Enable relaxed ordering */ 3863*5fc77b81SRobert Mustacchi for (i = 0; i < hw->mac.max_tx_queues; i++) { 3864*5fc77b81SRobert Mustacchi regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 3865*5fc77b81SRobert Mustacchi regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 3866*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 3867*5fc77b81SRobert Mustacchi } 3868*5fc77b81SRobert Mustacchi 3869*5fc77b81SRobert Mustacchi for (i = 0; i < hw->mac.max_rx_queues; i++) { 3870*5fc77b81SRobert Mustacchi regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 3871*5fc77b81SRobert Mustacchi regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 3872*5fc77b81SRobert Mustacchi IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 3873*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 3874*5fc77b81SRobert Mustacchi } 3875*5fc77b81SRobert Mustacchi 3876*5fc77b81SRobert Mustacchi } 3877*5fc77b81SRobert Mustacchi 3878*5fc77b81SRobert Mustacchi /** 3879*5fc77b81SRobert Mustacchi * ixgbe_calculate_checksum - Calculate checksum for buffer 3880*5fc77b81SRobert Mustacchi * @buffer: pointer to EEPROM 3881*5fc77b81SRobert Mustacchi * @length: size of EEPROM to calculate a checksum for 3882*5fc77b81SRobert Mustacchi * Calculates the checksum for some buffer on a specified length. The 3883*5fc77b81SRobert Mustacchi * checksum calculated is returned. 3884*5fc77b81SRobert Mustacchi **/ 3885*5fc77b81SRobert Mustacchi static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 3886*5fc77b81SRobert Mustacchi { 3887*5fc77b81SRobert Mustacchi u32 i; 3888*5fc77b81SRobert Mustacchi u8 sum = 0; 3889*5fc77b81SRobert Mustacchi 3890*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_calculate_checksum"); 3891*5fc77b81SRobert Mustacchi 3892*5fc77b81SRobert Mustacchi if (!buffer) 3893*5fc77b81SRobert Mustacchi return 0; 3894*5fc77b81SRobert Mustacchi 3895*5fc77b81SRobert Mustacchi for (i = 0; i < length; i++) 3896*5fc77b81SRobert Mustacchi sum += buffer[i]; 3897*5fc77b81SRobert Mustacchi 3898*5fc77b81SRobert Mustacchi return (u8) (0 - sum); 3899*5fc77b81SRobert Mustacchi } 3900*5fc77b81SRobert Mustacchi 3901*5fc77b81SRobert Mustacchi /** 3902*5fc77b81SRobert Mustacchi * ixgbe_host_interface_command - Issue command to manageability block 3903*5fc77b81SRobert Mustacchi * @hw: pointer to the HW structure 3904*5fc77b81SRobert Mustacchi * @buffer: contains the command to write and where the return status will 3905*5fc77b81SRobert Mustacchi * be placed 3906*5fc77b81SRobert Mustacchi * @length: length of buffer, must be multiple of 4 bytes 3907*5fc77b81SRobert Mustacchi * 3908*5fc77b81SRobert Mustacchi * Communicates with the manageability block. On success return IXGBE_SUCCESS 3909*5fc77b81SRobert Mustacchi * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 3910*5fc77b81SRobert Mustacchi **/ 3911*5fc77b81SRobert Mustacchi static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 3912*5fc77b81SRobert Mustacchi u32 length) 3913*5fc77b81SRobert Mustacchi { 3914*5fc77b81SRobert Mustacchi u32 hicr, i, bi; 3915*5fc77b81SRobert Mustacchi u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 3916*5fc77b81SRobert Mustacchi u8 buf_len, dword_len; 3917*5fc77b81SRobert Mustacchi 3918*5fc77b81SRobert Mustacchi s32 ret_val = IXGBE_SUCCESS; 3919*5fc77b81SRobert Mustacchi 3920*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_host_interface_command"); 3921*5fc77b81SRobert Mustacchi 3922*5fc77b81SRobert Mustacchi if (length == 0 || length & 0x3 || 3923*5fc77b81SRobert Mustacchi length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 3924*5fc77b81SRobert Mustacchi DEBUGOUT("Buffer length failure.\n"); 3925*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3926*5fc77b81SRobert Mustacchi goto out; 3927*5fc77b81SRobert Mustacchi } 3928*5fc77b81SRobert Mustacchi 3929*5fc77b81SRobert Mustacchi /* Check that the host interface is enabled. */ 3930*5fc77b81SRobert Mustacchi hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3931*5fc77b81SRobert Mustacchi if ((hicr & IXGBE_HICR_EN) == 0) { 3932*5fc77b81SRobert Mustacchi DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 3933*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3934*5fc77b81SRobert Mustacchi goto out; 3935*5fc77b81SRobert Mustacchi } 3936*5fc77b81SRobert Mustacchi 3937*5fc77b81SRobert Mustacchi /* Calculate length in DWORDs */ 3938*5fc77b81SRobert Mustacchi dword_len = length >> 2; 3939*5fc77b81SRobert Mustacchi 3940*5fc77b81SRobert Mustacchi /* 3941*5fc77b81SRobert Mustacchi * The device driver writes the relevant command block 3942*5fc77b81SRobert Mustacchi * into the ram area. 3943*5fc77b81SRobert Mustacchi */ 3944*5fc77b81SRobert Mustacchi for (i = 0; i < dword_len; i++) 3945*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 3946*5fc77b81SRobert Mustacchi i, IXGBE_CPU_TO_LE32(buffer[i])); 3947*5fc77b81SRobert Mustacchi 3948*5fc77b81SRobert Mustacchi /* Setting this bit tells the ARC that a new command is pending. */ 3949*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 3950*5fc77b81SRobert Mustacchi 3951*5fc77b81SRobert Mustacchi for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) { 3952*5fc77b81SRobert Mustacchi hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 3953*5fc77b81SRobert Mustacchi if (!(hicr & IXGBE_HICR_C)) 3954*5fc77b81SRobert Mustacchi break; 3955*5fc77b81SRobert Mustacchi msec_delay(1); 3956*5fc77b81SRobert Mustacchi } 3957*5fc77b81SRobert Mustacchi 3958*5fc77b81SRobert Mustacchi /* Check command successful completion. */ 3959*5fc77b81SRobert Mustacchi if (i == IXGBE_HI_COMMAND_TIMEOUT || 3960*5fc77b81SRobert Mustacchi (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) { 3961*5fc77b81SRobert Mustacchi DEBUGOUT("Command has failed with no status valid.\n"); 3962*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3963*5fc77b81SRobert Mustacchi goto out; 3964*5fc77b81SRobert Mustacchi } 3965*5fc77b81SRobert Mustacchi 3966*5fc77b81SRobert Mustacchi /* Calculate length in DWORDs */ 3967*5fc77b81SRobert Mustacchi dword_len = hdr_size >> 2; 3968*5fc77b81SRobert Mustacchi 3969*5fc77b81SRobert Mustacchi /* first pull in the header so we know the buffer length */ 3970*5fc77b81SRobert Mustacchi for (bi = 0; bi < dword_len; bi++) { 3971*5fc77b81SRobert Mustacchi buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3972*5fc77b81SRobert Mustacchi buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]); 3973*5fc77b81SRobert Mustacchi } 3974*5fc77b81SRobert Mustacchi 3975*5fc77b81SRobert Mustacchi /* If there is any thing in data position pull it in */ 3976*5fc77b81SRobert Mustacchi buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; 3977*5fc77b81SRobert Mustacchi if (buf_len == 0) 3978*5fc77b81SRobert Mustacchi goto out; 3979*5fc77b81SRobert Mustacchi 3980*5fc77b81SRobert Mustacchi if (length < (buf_len + hdr_size)) { 3981*5fc77b81SRobert Mustacchi DEBUGOUT("Buffer not large enough for reply message.\n"); 3982*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 3983*5fc77b81SRobert Mustacchi goto out; 3984*5fc77b81SRobert Mustacchi } 3985*5fc77b81SRobert Mustacchi 3986*5fc77b81SRobert Mustacchi /* Calculate length in DWORDs, add 3 for odd lengths */ 3987*5fc77b81SRobert Mustacchi dword_len = (buf_len + 3) >> 2; 3988*5fc77b81SRobert Mustacchi 3989*5fc77b81SRobert Mustacchi /* Pull in the rest of the buffer (bi is where we left off)*/ 3990*5fc77b81SRobert Mustacchi for (; bi <= dword_len; bi++) { 3991*5fc77b81SRobert Mustacchi buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 3992*5fc77b81SRobert Mustacchi buffer[bi] = IXGBE_LE32_TO_CPUS(buffer[bi]); 3993*5fc77b81SRobert Mustacchi } 3994*5fc77b81SRobert Mustacchi 3995*5fc77b81SRobert Mustacchi out: 3996*5fc77b81SRobert Mustacchi return ret_val; 3997*5fc77b81SRobert Mustacchi } 3998*5fc77b81SRobert Mustacchi 3999*5fc77b81SRobert Mustacchi /** 4000*5fc77b81SRobert Mustacchi * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4001*5fc77b81SRobert Mustacchi * @hw: pointer to the HW structure 4002*5fc77b81SRobert Mustacchi * @maj: driver version major number 4003*5fc77b81SRobert Mustacchi * @min: driver version minor number 4004*5fc77b81SRobert Mustacchi * @build: driver version build number 4005*5fc77b81SRobert Mustacchi * @sub: driver version sub build number 4006*5fc77b81SRobert Mustacchi * 4007*5fc77b81SRobert Mustacchi * Sends driver version number to firmware through the manageability 4008*5fc77b81SRobert Mustacchi * block. On success return IXGBE_SUCCESS 4009*5fc77b81SRobert Mustacchi * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4010*5fc77b81SRobert Mustacchi * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4011*5fc77b81SRobert Mustacchi **/ 4012*5fc77b81SRobert Mustacchi s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 4013*5fc77b81SRobert Mustacchi u8 build, u8 sub) 4014*5fc77b81SRobert Mustacchi { 4015*5fc77b81SRobert Mustacchi struct ixgbe_hic_drv_info fw_cmd; 4016*5fc77b81SRobert Mustacchi int i; 4017*5fc77b81SRobert Mustacchi s32 ret_val = IXGBE_SUCCESS; 4018*5fc77b81SRobert Mustacchi 4019*5fc77b81SRobert Mustacchi DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4020*5fc77b81SRobert Mustacchi 4021*5fc77b81SRobert Mustacchi if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) 4022*5fc77b81SRobert Mustacchi != IXGBE_SUCCESS) { 4023*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_SWFW_SYNC; 4024*5fc77b81SRobert Mustacchi goto out; 4025*5fc77b81SRobert Mustacchi } 4026*5fc77b81SRobert Mustacchi 4027*5fc77b81SRobert Mustacchi fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4028*5fc77b81SRobert Mustacchi fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4029*5fc77b81SRobert Mustacchi fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4030*5fc77b81SRobert Mustacchi fw_cmd.port_num = (u8)hw->bus.func; 4031*5fc77b81SRobert Mustacchi fw_cmd.ver_maj = maj; 4032*5fc77b81SRobert Mustacchi fw_cmd.ver_min = min; 4033*5fc77b81SRobert Mustacchi fw_cmd.ver_build = build; 4034*5fc77b81SRobert Mustacchi fw_cmd.ver_sub = sub; 4035*5fc77b81SRobert Mustacchi fw_cmd.hdr.checksum = 0; 4036*5fc77b81SRobert Mustacchi fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4037*5fc77b81SRobert Mustacchi (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4038*5fc77b81SRobert Mustacchi fw_cmd.pad = 0; 4039*5fc77b81SRobert Mustacchi fw_cmd.pad2 = 0; 4040*5fc77b81SRobert Mustacchi 4041*5fc77b81SRobert Mustacchi for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4042*5fc77b81SRobert Mustacchi /* LINTED */ 4043*5fc77b81SRobert Mustacchi ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4044*5fc77b81SRobert Mustacchi sizeof(fw_cmd)); 4045*5fc77b81SRobert Mustacchi if (ret_val != IXGBE_SUCCESS) 4046*5fc77b81SRobert Mustacchi continue; 4047*5fc77b81SRobert Mustacchi 4048*5fc77b81SRobert Mustacchi if (fw_cmd.hdr.cmd_or_resp.ret_status == 4049*5fc77b81SRobert Mustacchi FW_CEM_RESP_STATUS_SUCCESS) 4050*5fc77b81SRobert Mustacchi ret_val = IXGBE_SUCCESS; 4051*5fc77b81SRobert Mustacchi else 4052*5fc77b81SRobert Mustacchi ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4053*5fc77b81SRobert Mustacchi 4054*5fc77b81SRobert Mustacchi break; 4055*5fc77b81SRobert Mustacchi } 4056*5fc77b81SRobert Mustacchi 4057*5fc77b81SRobert Mustacchi hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4058*5fc77b81SRobert Mustacchi out: 4059*5fc77b81SRobert Mustacchi return ret_val; 4060*5fc77b81SRobert Mustacchi } 4061*5fc77b81SRobert Mustacchi 4062*5fc77b81SRobert Mustacchi /** 4063*5fc77b81SRobert Mustacchi * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4064*5fc77b81SRobert Mustacchi * @hw: pointer to hardware structure 4065*5fc77b81SRobert Mustacchi * @num_pb: number of packet buffers to allocate 4066*5fc77b81SRobert Mustacchi * @headroom: reserve n KB of headroom 4067*5fc77b81SRobert Mustacchi * @strategy: packet buffer allocation strategy 4068*5fc77b81SRobert Mustacchi **/ 4069*5fc77b81SRobert Mustacchi void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4070*5fc77b81SRobert Mustacchi int strategy) 4071*5fc77b81SRobert Mustacchi { 4072*5fc77b81SRobert Mustacchi u32 pbsize = hw->mac.rx_pb_size; 4073*5fc77b81SRobert Mustacchi int i = 0; 4074*5fc77b81SRobert Mustacchi u32 rxpktsize, txpktsize, txpbthresh; 4075*5fc77b81SRobert Mustacchi 4076*5fc77b81SRobert Mustacchi /* Reserve headroom */ 4077*5fc77b81SRobert Mustacchi pbsize -= headroom; 4078*5fc77b81SRobert Mustacchi 4079*5fc77b81SRobert Mustacchi if (!num_pb) 4080*5fc77b81SRobert Mustacchi num_pb = 1; 4081*5fc77b81SRobert Mustacchi 4082*5fc77b81SRobert Mustacchi /* Divide remaining packet buffer space amongst the number of packet 4083*5fc77b81SRobert Mustacchi * buffers requested using supplied strategy. 4084*5fc77b81SRobert Mustacchi */ 4085*5fc77b81SRobert Mustacchi switch (strategy) { 4086*5fc77b81SRobert Mustacchi case PBA_STRATEGY_WEIGHTED: 4087*5fc77b81SRobert Mustacchi /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4088*5fc77b81SRobert Mustacchi * buffer with 5/8 of the packet buffer space. 4089*5fc77b81SRobert Mustacchi */ 4090*5fc77b81SRobert Mustacchi rxpktsize = (pbsize * 5) / (num_pb * 4); 4091*5fc77b81SRobert Mustacchi pbsize -= rxpktsize * (num_pb / 2); 4092*5fc77b81SRobert Mustacchi rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4093*5fc77b81SRobert Mustacchi for (; i < (num_pb / 2); i++) 4094*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4095*5fc77b81SRobert Mustacchi /* Fall through to configure remaining packet buffers */ 4096*5fc77b81SRobert Mustacchi /* FALLTHRU */ 4097*5fc77b81SRobert Mustacchi case PBA_STRATEGY_EQUAL: 4098*5fc77b81SRobert Mustacchi rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4099*5fc77b81SRobert Mustacchi for (; i < num_pb; i++) 4100*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4101*5fc77b81SRobert Mustacchi break; 4102*5fc77b81SRobert Mustacchi default: 4103*5fc77b81SRobert Mustacchi break; 4104*5fc77b81SRobert Mustacchi } 4105*5fc77b81SRobert Mustacchi 4106*5fc77b81SRobert Mustacchi /* Only support an equally distributed Tx packet buffer strategy. */ 4107*5fc77b81SRobert Mustacchi txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4108*5fc77b81SRobert Mustacchi txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4109*5fc77b81SRobert Mustacchi for (i = 0; i < num_pb; i++) { 4110*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4111*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4112*5fc77b81SRobert Mustacchi } 4113*5fc77b81SRobert Mustacchi 4114*5fc77b81SRobert Mustacchi /* Clear unused TCs, if any, to zero buffer size*/ 4115*5fc77b81SRobert Mustacchi for (; i < IXGBE_MAX_PB; i++) { 4116*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4117*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4118*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4119*5fc77b81SRobert Mustacchi } 4120*5fc77b81SRobert Mustacchi } 4121*5fc77b81SRobert Mustacchi 4122*5fc77b81SRobert Mustacchi /** 4123*5fc77b81SRobert Mustacchi * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4124*5fc77b81SRobert Mustacchi * @hw: pointer to the hardware structure 4125*5fc77b81SRobert Mustacchi * 4126*5fc77b81SRobert Mustacchi * The 82599 and x540 MACs can experience issues if TX work is still pending 4127*5fc77b81SRobert Mustacchi * when a reset occurs. This function prevents this by flushing the PCIe 4128*5fc77b81SRobert Mustacchi * buffers on the system. 4129*5fc77b81SRobert Mustacchi **/ 4130*5fc77b81SRobert Mustacchi void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4131*5fc77b81SRobert Mustacchi { 4132*5fc77b81SRobert Mustacchi u32 gcr_ext, hlreg0; 4133*5fc77b81SRobert Mustacchi 4134*5fc77b81SRobert Mustacchi /* 4135*5fc77b81SRobert Mustacchi * If double reset is not requested then all transactions should 4136*5fc77b81SRobert Mustacchi * already be clear and as such there is no work to do 4137*5fc77b81SRobert Mustacchi */ 4138*5fc77b81SRobert Mustacchi if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4139*5fc77b81SRobert Mustacchi return; 4140*5fc77b81SRobert Mustacchi 4141*5fc77b81SRobert Mustacchi /* 4142*5fc77b81SRobert Mustacchi * Set loopback enable to prevent any transmits from being sent 4143*5fc77b81SRobert Mustacchi * should the link come up. This assumes that the RXCTRL.RXEN bit 4144*5fc77b81SRobert Mustacchi * has already been cleared. 4145*5fc77b81SRobert Mustacchi */ 4146*5fc77b81SRobert Mustacchi hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4147*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4148*5fc77b81SRobert Mustacchi 4149*5fc77b81SRobert Mustacchi /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4150*5fc77b81SRobert Mustacchi gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4151*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4152*5fc77b81SRobert Mustacchi gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4153*5fc77b81SRobert Mustacchi 4154*5fc77b81SRobert Mustacchi /* Flush all writes and allow 20usec for all transactions to clear */ 4155*5fc77b81SRobert Mustacchi IXGBE_WRITE_FLUSH(hw); 4156*5fc77b81SRobert Mustacchi usec_delay(20); 4157*5fc77b81SRobert Mustacchi 4158*5fc77b81SRobert Mustacchi /* restore previous register values */ 4159*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4160*5fc77b81SRobert Mustacchi IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4161*5fc77b81SRobert Mustacchi } 4162*5fc77b81SRobert Mustacchi 4163