1 /* $NetBSD: if_iwnreg.h,v 1.15 2014/11/09 14:40:54 nonaka Exp $ */ 2 /* $OpenBSD: if_iwnreg.h,v 1.49 2014/09/09 18:56:24 sthen Exp $ */ 3 4 /*- 5 * Copyright (c) 2007, 2008 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Copyright 2016 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> 23 */ 24 25 #ifndef _IF_IWNREG_H 26 #define _IF_IWNREG_H 27 28 /* XXX Added for NetBSD */ 29 #define IEEE80211_TKIP_MICLEN 8 30 31 #define IWN_TX_RING_COUNT 256 32 #define IWN_TX_RING_LOMARK 192 33 #define IWN_TX_RING_HIMARK 224 34 #define IWN_RX_RING_COUNT_LOG 6 35 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG) 36 37 #define IWN4965_NTXQUEUES 16 38 #define IWN5000_NTXQUEUES 20 39 40 #define IWN_CMD_QUEUE_NUM 4 41 42 #define IWN4965_NDMACHNLS 7 43 #define IWN5000_NDMACHNLS 8 44 45 #define IWN_SRVC_DMACHNL 9 46 47 #define IWN_KW_SIZE 4096 48 49 #define IWN_ICT_SIZE 4096 50 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t)) 51 52 /* Maximum number of DMA segments for TX. */ 53 #define IWN_MAX_SCATTER 20 54 55 /* RX buffers must be large enough to hold a full 4K A-MPDU. */ 56 #define IWN_RBUF_SIZE (4 * 1024) 57 58 #define IWN_TBUF_SIZE (4 * 1024) 59 60 61 #if defined(_LP64) 62 /* HW supports 36-bit DMA addresses. */ 63 #define IWN_LOADDR(paddr) ((uint32_t)(paddr)) 64 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf) 65 #else 66 #define IWN_LOADDR(paddr) (paddr) 67 #define IWN_HIADDR(paddr) (0) 68 #endif 69 70 /* Base Address Register. */ 71 #define IWN_PCI_BAR0 PCI_MAPREG_START 72 73 /* 74 * Control and status registers. 75 */ 76 #define IWN_HW_IF_CONFIG 0x000 77 #define IWN_INT_COALESCING 0x004 78 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */ 79 #define IWN_INT 0x008 80 #define IWN_INT_MASK 0x00c 81 #define IWN_FH_INT 0x010 82 #define IWN_RESET 0x020 83 #define IWN_GP_CNTRL 0x024 84 #define IWN_HW_REV 0x028 85 #define IWN_EEPROM 0x02c 86 #define IWN_EEPROM_GP 0x030 87 #define IWN_OTP_GP 0x034 88 #define IWN_GIO 0x03c 89 #define IWN_GP_DRIVER 0x050 90 #define IWN_UCODE_GP1_CLR 0x05c 91 #define IWN_LED 0x094 92 #define IWN_DRAM_INT_TBL 0x0a0 93 #define IWN_SHADOW_REG_CTRL 0x0a8 94 #define IWN_GIO_CHICKEN 0x100 95 #define IWN_ANA_PLL 0x20c 96 #define IWN_HW_REV_WA 0x22c 97 #define IWN_DBG_HPET_MEM 0x240 98 #define IWN_DBG_LINK_PWR_MGMT 0x250 99 #define IWN_MEM_RADDR 0x40c 100 #define IWN_MEM_WADDR 0x410 101 #define IWN_MEM_WDATA 0x418 102 #define IWN_MEM_RDATA 0x41c 103 #define IWN_PRPH_WADDR 0x444 104 #define IWN_PRPH_RADDR 0x448 105 #define IWN_PRPH_WDATA 0x44c 106 #define IWN_PRPH_RDATA 0x450 107 #define IWN_HBUS_TARG_WRPTR 0x460 108 109 /* 110 * Flow-Handler registers. 111 */ 112 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8) 113 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8) 114 #define IWN_FH_KW_ADDR 0x197c 115 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4) 116 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4) 117 #define IWN_FH_STATUS_WPTR 0x1bc0 118 #define IWN_FH_RX_BASE 0x1bc4 119 #define IWN_FH_RX_WPTR 0x1bc8 120 #define IWN_FH_RX_CONFIG 0x1c00 121 #define IWN_FH_RX_STATUS 0x1c44 122 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32) 123 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32) 124 #define IWN_FH_TX_CHICKEN 0x1e98 125 #define IWN_FH_TX_STATUS 0x1eb0 126 127 /* 128 * TX scheduler registers. 129 */ 130 #define IWN_SCHED_BASE 0xa02c00 131 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000) 132 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008) 133 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010) 134 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010) 135 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c) 136 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4) 137 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4) 138 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0) 139 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4) 140 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8) 141 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4) 142 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108) 143 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4) 144 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248) 145 146 /* 147 * Offsets in TX scheduler's SRAM. 148 */ 149 #define IWN4965_SCHED_CTX_OFF 0x380 150 #define IWN4965_SCHED_CTX_LEN 416 151 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8) 152 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2) 153 #define IWN5000_SCHED_CTX_OFF 0x600 154 #define IWN5000_SCHED_CTX_LEN 520 155 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8) 156 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2) 157 158 /* 159 * NIC internal memory offsets. 160 */ 161 #define IWN_APMG_CLK_CTRL 0x3000 162 #define IWN_APMG_CLK_EN 0x3004 163 #define IWN_APMG_CLK_DIS 0x3008 164 #define IWN_APMG_PS 0x300c 165 #define IWN_APMG_DIGITAL_SVR 0x3058 166 #define IWN_APMG_ANALOG_SVR 0x306c 167 #define IWN_APMG_PCI_STT 0x3010 168 #define IWN_BSM_WR_CTRL 0x3400 169 #define IWN_BSM_WR_MEM_SRC 0x3404 170 #define IWN_BSM_WR_MEM_DST 0x3408 171 #define IWN_BSM_WR_DWCOUNT 0x340c 172 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490 173 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494 174 #define IWN_BSM_DRAM_DATA_ADDR 0x3498 175 #define IWN_BSM_DRAM_DATA_SIZE 0x349c 176 #define IWN_BSM_SRAM_BASE 0x3800 177 178 /* Possible flags for register IWN_HW_IF_CONFIG. */ 179 #define IWN_HW_IF_CONFIG_4965_R (1 << 4) 180 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8) 181 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9) 182 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21) 183 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22) 184 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23) 185 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25) 186 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27) 187 188 /* Possible values for register IWN_INT_PERIODIC. */ 189 #define IWN_INT_PERIODIC_DIS 0x00 190 #define IWN_INT_PERIODIC_ENA 0xff 191 192 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */ 193 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 194 195 /* Possible values for IWN_BSM_WR_MEM_DST. */ 196 #define IWN_FW_TEXT_BASE 0x00000000 197 #define IWN_FW_DATA_BASE 0x00800000 198 199 /* Possible flags for register IWN_RESET. */ 200 #define IWN_RESET_NEVO (1U << 0) 201 #define IWN_RESET_SW (1U << 7) 202 #define IWN_RESET_MASTER_DISABLED (1U << 8) 203 #define IWN_RESET_STOP_MASTER (1U << 9) 204 #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31) 205 206 /* Possible flags for register IWN_GP_CNTRL. */ 207 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 208 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 209 #define IWN_GP_CNTRL_INIT_DONE (1 << 2) 210 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 211 #define IWN_GP_CNTRL_SLEEP (1 << 4) 212 #define IWN_GP_CNTRL_RFKILL (1 << 27) 213 214 /* Possible flags for register IWN_HW_REV. */ 215 #define IWN_HW_REV_TYPE_SHIFT 4 216 #define IWN_HW_REV_TYPE_MASK 0x000001f0 217 #define IWN_HW_REV_TYPE_4965 0 218 #define IWN_HW_REV_TYPE_5300 2 219 #define IWN_HW_REV_TYPE_5350 3 220 #define IWN_HW_REV_TYPE_5150 4 221 #define IWN_HW_REV_TYPE_5100 5 222 #define IWN_HW_REV_TYPE_1000 6 223 #define IWN_HW_REV_TYPE_6000 7 224 #define IWN_HW_REV_TYPE_6050 8 225 #define IWN_HW_REV_TYPE_6005 11 226 /* Types 6030 and 6035 also return 11 */ 227 #define IWN_HW_REV_TYPE_2030 12 228 #define IWN_HW_REV_TYPE_2000 16 229 #define IWN_HW_REV_TYPE_105 17 230 #define IWN_HW_REV_TYPE_135 18 231 232 /* Possible flags for register IWN_GIO_CHICKEN. */ 233 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 234 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 235 236 /* Possible flags for register IWN_GIO. */ 237 #define IWN_GIO_L0S_ENA (1 << 1) 238 239 /* Possible flags for register IWN_GP_DRIVER. */ 240 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0) 241 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0) 242 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0) 243 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2) 244 #define IWN_GP_DRIVER_6050_1X2 (1 << 3) 245 #define IWN_GP_DRIVER_RADIO_IQ_INVERT (1 << 7) 246 247 /* Possible flags for register IWN_UCODE_GP1_CLR. */ 248 #define IWN_UCODE_GP1_RFKILL (1 << 1) 249 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2) 250 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3) 251 252 /* Possible flags/values for register IWN_LED. */ 253 #define IWN_LED_BSM_CTRL (1 << 5) 254 #define IWN_LED_OFF 0x00000038 255 #define IWN_LED_ON 0x00000078 256 257 /* Possible flags for register IWN_DRAM_INT_TBL. */ 258 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27) 259 #define IWN_DRAM_INT_TBL_ENABLE (1 << 31) 260 261 /* Possible values for register IWN_ANA_PLL. */ 262 #define IWN_ANA_PLL_INIT 0x00880300 263 264 /* Possible flags for register IWN_FH_RX_STATUS. */ 265 #define IWN_FH_RX_STATUS_IDLE (1 << 24) 266 267 /* Possible flags for register IWN_BSM_WR_CTRL. */ 268 #define IWN_BSM_WR_CTRL_START_EN (1 << 30) 269 #define IWN_BSM_WR_CTRL_START (1 << 31) 270 271 /* Possible flags for register IWN_INT. */ 272 #define IWN_INT_ALIVE (1 << 0) 273 #define IWN_INT_WAKEUP (1 << 1) 274 #define IWN_INT_SW_RX (1 << 3) 275 #define IWN_INT_CT_REACHED (1 << 6) 276 #define IWN_INT_RF_TOGGLED (1 << 7) 277 #define IWN_INT_SW_ERR (1 << 25) 278 #define IWN_INT_SCHED (1 << 26) 279 #define IWN_INT_FH_TX (1 << 27) 280 #define IWN_INT_RX_PERIODIC (1 << 28) 281 #define IWN_INT_HW_ERR (1 << 29) 282 #define IWN_INT_FH_RX (1U << 31) 283 284 /* Shortcut. */ 285 #define IWN_INT_MASK_DEF \ 286 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \ 287 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \ 288 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED) 289 290 /* Possible flags for register IWN_FH_INT. */ 291 #define IWN_FH_INT_TX_CHNL(x) (1 << (x)) 292 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 293 #define IWN_FH_INT_HI_PRIOR (1 << 30) 294 /* Shortcuts for the above. */ 295 #define IWN_FH_INT_TX \ 296 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1)) 297 #define IWN_FH_INT_RX \ 298 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR) 299 300 /* Possible flags/values for register IWN_FH_TX_CONFIG. */ 301 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0 302 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 303 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1U << 20) 304 305 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */ 306 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20) 307 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12) 308 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3 309 310 /* Possible flags for register IWN_FH_TX_CHICKEN. */ 311 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1) 312 313 /* Possible flags for register IWN_FH_TX_STATUS. */ 314 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16)) 315 316 /* Possible flags for register IWN_FH_RX_CONFIG. */ 317 #define IWN_FH_RX_CONFIG_ENA (1U << 31) 318 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20) 319 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1U << 16) 320 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1U << 15) 321 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1U << 12) 322 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4) 323 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1U << 2) 324 325 /* Possible flags for register IWN_FH_TX_CONFIG. */ 326 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31) 327 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1U << 3) 328 329 /* Possible flags for register IWN_EEPROM. */ 330 #define IWN_EEPROM_READ_VALID (1 << 0) 331 #define IWN_EEPROM_CMD (1 << 1) 332 333 /* Possible flags for register IWN_EEPROM_GP. */ 334 #define IWN_EEPROM_GP_IF_OWNER 0x00000180 335 336 /* Possible flags for register IWN_OTP_GP. */ 337 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16) 338 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17) 339 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20) 340 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21) 341 342 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */ 343 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01 344 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00 345 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8) 346 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10) 347 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018 348 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010 349 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19) 350 351 /* Possible flags for registers IWN_APMG_CLK_*. */ 352 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 353 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 354 355 /* Possible flags for register IWN_APMG_PS. */ 356 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22) 357 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24) 358 #define IWN_APMG_PS_PWR_SRC_VMAIN 0 359 #define IWN_APMG_PS_PWR_SRC_VAUX 2 360 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3) 361 #define IWN_APMG_PS_RESET_REQ (1 << 26) 362 363 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */ 364 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5) 365 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \ 366 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf) 367 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \ 368 IWN_APMG_DIGITAL_SVR_VOLTAGE(3) 369 370 /* Possible flags for IWN_APMG_PCI_STT. */ 371 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11) 372 373 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */ 374 #define IWN_FW_UPDATED (1U << 31) 375 376 #define IWN_SCHED_WINSZ 64 377 #define IWN_SCHED_LIMIT 64 378 #define IWN4965_SCHED_COUNT 512 379 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ) 380 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2) 381 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2) 382 383 struct iwn_tx_desc { 384 uint8_t reserved1[3]; 385 uint8_t nsegs; 386 struct { 387 uint32_t addr; 388 uint16_t len; 389 } __packed segs[IWN_MAX_SCATTER]; 390 /* Pad to 128 bytes. */ 391 uint32_t reserved2; 392 } __packed; 393 394 struct iwn_rx_status { 395 uint16_t closed_count; 396 uint16_t closed_rx_count; 397 uint16_t finished_count; 398 uint16_t finished_rx_count; 399 uint32_t reserved[2]; 400 } __packed; 401 402 struct iwn_rx_desc { 403 uint32_t len; 404 uint8_t type; 405 #define IWN_UC_READY 1 406 #define IWN_ADD_NODE_DONE 24 407 #define IWN_TX_DONE 28 408 #define IWN5000_CALIBRATION_RESULT 102 409 #define IWN5000_CALIBRATION_DONE 103 410 #define IWN_START_SCAN 130 411 #define IWN_STOP_SCAN 132 412 #define IWN_RX_STATISTICS 156 413 #define IWN_BEACON_STATISTICS 157 414 #define IWN_STATE_CHANGED 161 415 #define IWN_BEACON_MISSED 162 416 #define IWN_RX_PHY 192 417 #define IWN_MPDU_RX_DONE 193 418 #define IWN_RX_DONE 195 419 #define IWN_RX_COMPRESSED_BA 197 420 421 uint8_t flags; 422 uint8_t idx; 423 uint8_t qid; 424 } __packed; 425 426 /* Possible RX status flags. */ 427 #define IWN_RX_NO_CRC_ERR (1 << 0) 428 #define IWN_RX_NO_OVFL_ERR (1 << 1) 429 /* Shortcut for the above. */ 430 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR) 431 #define IWN_RX_MPDU_MIC_OK (1 << 6) 432 #define IWN_RX_CIPHER_MASK (7 << 8) 433 #define IWN_RX_CIPHER_CCMP (2 << 8) 434 #define IWN_RX_MPDU_DEC (1 << 11) 435 #define IWN_RX_DECRYPT_MASK (3 << 11) 436 #define IWN_RX_DECRYPT_OK (3 << 11) 437 438 struct iwn_tx_cmd { 439 uint8_t code; 440 #define IWN_CMD_RXON 16 441 #define IWN_CMD_RXON_ASSOC 17 442 #define IWN_CMD_EDCA_PARAMS 19 443 #define IWN_CMD_TIMING 20 444 #define IWN_CMD_ADD_NODE 24 445 #define IWN_CMD_TX_DATA 28 446 #define IWN_CMD_SET_LED 72 447 #define IWN_CMD_LINK_QUALITY 78 448 #define IWN5000_CMD_WIMAX_COEX 90 449 #define IWN5000_CMD_CALIB_CONFIG 101 450 #define IWN_CMD_SET_POWER_MODE 119 451 #define IWN_CMD_SCAN 128 452 #define IWN_CMD_TXPOWER_DBM 149 453 #define IWN_CMD_TXPOWER 151 454 #define IWN5000_CMD_TX_ANT_CONFIG 152 455 #define IWN_CMD_BT_COEX 155 456 #define IWN_CMD_GET_STATISTICS 156 457 #define IWN_CMD_SET_CRITICAL_TEMP 164 458 #define IWN_CMD_SET_SENSITIVITY 168 459 #define IWN_CMD_PHY_CALIB 176 460 #define IWN_CMD_BT_COEX_PRIO_TABLE 204 461 #define IWN_CMD_BT_COEX_PROT 205 462 463 uint8_t flags; 464 uint8_t idx; 465 uint8_t qid; 466 uint8_t data[136]; 467 } __packed; 468 469 /* Antenna flags, used in various commands. */ 470 #define IWN_ANT_A (1 << 0) 471 #define IWN_ANT_B (1 << 1) 472 #define IWN_ANT_C (1 << 2) 473 /* Shortcuts. */ 474 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B) 475 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C) 476 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C) 477 478 /* Structure for command IWN_CMD_RXON. */ 479 struct iwn_rxon { 480 uint8_t myaddr[IEEE80211_ADDR_LEN]; 481 uint16_t reserved1; 482 uint8_t bssid[IEEE80211_ADDR_LEN]; 483 uint16_t reserved2; 484 uint8_t wlap[IEEE80211_ADDR_LEN]; 485 uint16_t reserved3; 486 uint8_t mode; 487 #define IWN_MODE_HOSTAP 1 488 #define IWN_MODE_STA 3 489 #define IWN_MODE_IBSS 4 490 #define IWN_MODE_MONITOR 6 491 492 uint8_t air; 493 uint16_t rxchain; 494 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0) 495 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1) 496 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4) 497 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7) 498 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10) 499 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12) 500 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14) 501 502 uint8_t ofdm_mask; 503 uint8_t cck_mask; 504 uint16_t associd; 505 uint32_t flags; 506 #define IWN_RXON_24GHZ (1 << 0) 507 #define IWN_RXON_CCK (1 << 1) 508 #define IWN_RXON_AUTO (1 << 2) 509 #define IWN_RXON_SHSLOT (1 << 4) 510 #define IWN_RXON_SHPREAMBLE (1 << 5) 511 #define IWN_RXON_NODIVERSITY (1 << 7) 512 #define IWN_RXON_ANTENNA_A (1 << 8) 513 #define IWN_RXON_ANTENNA_B (1 << 9) 514 #define IWN_RXON_TSF (1 << 15) 515 #define IWN_RXON_CTS_TO_SELF (1 << 30) 516 517 uint32_t filter; 518 #define IWN_FILTER_PROMISC (1 << 0) 519 #define IWN_FILTER_CTL (1 << 1) 520 #define IWN_FILTER_MULTICAST (1 << 2) 521 #define IWN_FILTER_NODECRYPT (1 << 3) 522 #define IWN_FILTER_MC_NODECRYPT (1 << 4) 523 #define IWN_FILTER_BSS (1 << 5) 524 #define IWN_FILTER_BEACON (1 << 6) 525 526 uint8_t chan; 527 uint8_t reserved4; 528 uint8_t ht_single_mask; 529 uint8_t ht_dual_mask; 530 /* The following fields are for >=5000 Series only. */ 531 uint8_t ht_triple_mask; 532 uint8_t reserved5; 533 uint16_t acquisition; 534 uint16_t reserved6; 535 } __packed; 536 537 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6) 538 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon)) 539 540 /* Structure for command IWN_CMD_ASSOCIATE. */ 541 struct iwn_assoc { 542 uint32_t flags; 543 uint32_t filter; 544 uint8_t ofdm_mask; 545 uint8_t cck_mask; 546 uint16_t reserved; 547 } __packed; 548 549 /* Structure for command IWN_CMD_EDCA_PARAMS. */ 550 struct iwn_edca_params { 551 uint32_t flags; 552 #define IWN_EDCA_UPDATE (1 << 0) 553 #define IWN_EDCA_TXOP (1 << 4) 554 555 struct { 556 uint16_t cwmin; 557 uint16_t cwmax; 558 uint8_t aifsn; 559 uint8_t reserved; 560 uint16_t txoplimit; 561 } __packed ac[WME_NUM_AC]; 562 } __packed; 563 564 /* Structure for command IWN_CMD_TIMING. */ 565 struct iwn_cmd_timing { 566 uint64_t tstamp; 567 uint16_t bintval; 568 uint16_t atim; 569 uint32_t binitval; 570 uint16_t lintval; 571 uint16_t reserved; 572 } __packed; 573 574 /* Structure for command IWN_CMD_ADD_NODE. */ 575 struct iwn_node_info { 576 uint8_t control; 577 #define IWN_NODE_UPDATE (1 << 0) 578 579 uint8_t reserved1[3]; 580 581 uint8_t macaddr[IEEE80211_ADDR_LEN]; 582 uint16_t reserved2; 583 uint8_t id; 584 #define IWN_ID_BSS 0 585 #define IWN5000_ID_BROADCAST 15 586 #define IWN4965_ID_BROADCAST 31 587 588 uint8_t flags; 589 #define IWN_FLAG_SET_KEY (1 << 0) 590 #define IWN_FLAG_SET_DISABLE_TID (1 << 1) 591 #define IWN_FLAG_SET_TXRATE (1 << 2) 592 #define IWN_FLAG_SET_ADDBA (1 << 3) 593 #define IWN_FLAG_SET_DELBA (1 << 4) 594 595 uint16_t reserved3; 596 uint16_t kflags; 597 #define IWN_KFLAG_CCMP (1 << 1) 598 #define IWN_KFLAG_MAP (1 << 3) 599 #define IWN_KFLAG_KID(kid) ((kid) << 8) 600 #define IWN_KFLAG_INVALID (1 << 11) 601 #define IWN_KFLAG_GROUP (1 << 14) 602 603 uint8_t tsc2; /* TKIP TSC2 */ 604 uint8_t reserved4; 605 uint16_t ttak[5]; 606 uint8_t kid; 607 uint8_t reserved5; 608 uint8_t key[16]; 609 /* The following 3 fields are for 5000 Series only. */ 610 uint64_t tsc; 611 uint8_t rxmic[IEEE80211_TKIP_MICLEN]; 612 uint8_t txmic[IEEE80211_TKIP_MICLEN]; 613 614 uint32_t htflags; 615 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19) 616 #define IWN_AMDPU_DENSITY(x) ((x) << 23) 617 618 uint32_t mask; 619 uint16_t disable_tid; 620 uint16_t reserved6; 621 uint8_t addba_tid; 622 uint8_t delba_tid; 623 uint16_t addba_ssn; 624 uint32_t reserved7; 625 } __packed; 626 627 struct iwn4965_node_info { 628 uint8_t control; 629 uint8_t reserved1[3]; 630 uint8_t macaddr[IEEE80211_ADDR_LEN]; 631 uint16_t reserved2; 632 uint8_t id; 633 uint8_t flags; 634 uint16_t reserved3; 635 uint16_t kflags; 636 uint8_t tsc2; /* TKIP TSC2 */ 637 uint8_t reserved4; 638 uint16_t ttak[5]; 639 uint8_t kid; 640 uint8_t reserved5; 641 uint8_t key[16]; 642 uint32_t htflags; 643 uint32_t mask; 644 uint16_t disable_tid; 645 uint16_t reserved6; 646 uint8_t addba_tid; 647 uint8_t delba_tid; 648 uint16_t addba_ssn; 649 uint32_t reserved7; 650 } __packed; 651 652 #define IWN_RFLAG_CCK (1 << 1) 653 #define IWN_RFLAG_ANT(x) ((x) << 6) 654 655 /* Structure for command IWN_CMD_TX_DATA. */ 656 struct iwn_cmd_data { 657 uint16_t len; 658 uint16_t lnext; 659 uint32_t flags; 660 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */ 661 #define IWN_TX_NEED_RTS (1 << 1) 662 #define IWN_TX_NEED_CTS (1 << 2) 663 #define IWN_TX_NEED_ACK (1 << 3) 664 #define IWN_TX_LINKQ (1 << 4) 665 #define IWN_TX_IMM_BA (1 << 6) 666 #define IWN_TX_FULL_TXOP (1 << 7) 667 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 668 #define IWN_TX_AUTO_SEQ (1 << 13) 669 #define IWN_TX_MORE_FRAG (1 << 14) 670 #define IWN_TX_INSERT_TSTAMP (1 << 16) 671 #define IWN_TX_NEED_PADDING (1 << 20) 672 673 uint32_t scratch; 674 uint8_t plcp; 675 uint8_t rflags; 676 uint16_t xrflags; 677 678 uint8_t id; 679 uint8_t security; 680 #define IWN_CIPHER_WEP40 1 681 #define IWN_CIPHER_CCMP 2 682 #define IWN_CIPHER_TKIP 3 683 #define IWN_CIPHER_WEP104 9 684 685 uint8_t linkq; 686 uint8_t reserved2; 687 uint8_t key[16]; 688 uint16_t fnext; 689 uint16_t reserved3; 690 uint32_t lifetime; 691 #define IWN_LIFETIME_INFINITE 0xffffffff 692 693 uint32_t loaddr; 694 uint8_t hiaddr; 695 uint8_t rts_ntries; 696 uint8_t data_ntries; 697 uint8_t tid; 698 uint16_t timeout; 699 uint16_t txop; 700 } __packed; 701 702 /* Structure for command IWN_CMD_LINK_QUALITY. */ 703 #define IWN_MAX_TX_RETRIES 16 704 struct iwn_cmd_link_quality { 705 uint8_t id; 706 uint8_t reserved1; 707 uint16_t ctl; 708 uint8_t flags; 709 uint8_t mimo; 710 uint8_t antmsk_1stream; 711 uint8_t antmsk_2stream; 712 uint8_t ridx[WME_NUM_AC]; 713 uint16_t ampdu_limit; 714 uint8_t ampdu_threshold; 715 uint8_t ampdu_max; 716 uint32_t reserved2; 717 struct { 718 uint8_t plcp; 719 uint8_t rflags; 720 uint16_t xrflags; 721 } __packed retry[IWN_MAX_TX_RETRIES]; 722 uint32_t reserved3; 723 } __packed; 724 725 /* Structure for command IWN_CMD_SET_LED. */ 726 struct iwn_cmd_led { 727 uint32_t unit; /* multiplier (in usecs) */ 728 uint8_t which; 729 #define IWN_LED_ACTIVITY 1 730 #define IWN_LED_LINK 2 731 732 uint8_t off; 733 uint8_t on; 734 uint8_t reserved; 735 } __packed; 736 737 /* Structure for command IWN5000_CMD_WIMAX_COEX. */ 738 struct iwn5000_wimax_coex { 739 uint32_t flags; 740 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0) 741 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2) 742 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3) 743 #define IWN_WIMAX_COEX_ENABLE (1 << 7) 744 745 struct iwn5000_wimax_event { 746 uint8_t request; 747 uint8_t window; 748 uint8_t reserved; 749 uint8_t flags; 750 } __packed events[16]; 751 } __packed; 752 753 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */ 754 struct iwn5000_calib_elem { 755 uint32_t enable; 756 uint32_t start; 757 #define IWN5000_CALIB_DC (1 << 1) 758 uint32_t send; 759 uint32_t apply; 760 uint32_t reserved; 761 } __packed; 762 763 struct iwn5000_calib_status { 764 struct iwn5000_calib_elem once; 765 struct iwn5000_calib_elem perd; 766 uint32_t flags; 767 } __packed; 768 769 struct iwn5000_calib_config { 770 struct iwn5000_calib_status ucode; 771 struct iwn5000_calib_status driver; 772 uint32_t reserved; 773 } __packed; 774 775 /* Structure for command IWN_CMD_SET_POWER_MODE. */ 776 struct iwn_pmgt_cmd { 777 uint16_t flags; 778 #define IWN_PS_ALLOW_SLEEP (1 << 0) 779 #define IWN_PS_NOTIFY (1 << 1) 780 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2) 781 #define IWN_PS_PCI_PMGT (1 << 3) 782 #define IWN_PS_FAST_PD (1 << 4) 783 784 uint8_t keepalive; 785 uint8_t debug; 786 uint32_t rxtimeout; 787 uint32_t txtimeout; 788 uint32_t intval[5]; 789 uint32_t beacons; 790 } __packed; 791 792 /* Structures for command IWN_CMD_SCAN. */ 793 struct iwn_scan_essid { 794 uint8_t id; 795 uint8_t len; 796 uint8_t data[IEEE80211_NWID_LEN]; 797 } __packed; 798 799 struct iwn_scan_hdr { 800 uint16_t len; 801 uint8_t scan_flags; 802 #define IWN_SCAN_PASSIVE2ACTIVE (1<<5) 803 804 uint8_t nchan; 805 uint16_t quiet_time; 806 uint16_t quiet_threshold; 807 uint16_t crc_threshold; 808 uint16_t rxchain; 809 uint32_t max_svc; /* background scans */ 810 uint32_t pause_svc; /* background scans */ 811 uint32_t flags; 812 uint32_t filter; 813 814 /* Followed by a struct iwn_cmd_data. */ 815 /* Followed by an array of 20 structs iwn_scan_essid. */ 816 /* Followed by probe request body. */ 817 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */ 818 } __packed; 819 820 struct iwn_scan_chan { 821 uint32_t flags; 822 #define IWN_CHAN_ACTIVE (1 << 0) 823 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 824 825 uint16_t chan; 826 uint8_t rf_gain; 827 uint8_t dsp_gain; 828 uint16_t active; /* msecs */ 829 uint16_t passive; /* msecs */ 830 } __packed; 831 832 /* Maximum size of a scan command. */ 833 #define IWN_SCAN_MAXSZ 4092 834 835 /* 836 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 837 * sending probe req. This should be set long enough to hear probe responses 838 * from more than one AP. 839 */ 840 #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 841 #define IWN_ACTIVE_DWELL_TIME_5GHZ (20) 842 #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3) 843 #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2) 844 845 /* 846 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. 847 * Must be set longer than active dwell time. 848 * For the most reliable scan, set > AP beacon interval (typically 100msec). 849 */ 850 #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */ 851 #define IWN_PASSIVE_DWELL_TIME_5GHZ (10) 852 #define IWN_PASSIVE_DWELL_BASE (100) 853 #define IWN_CHANNEL_TUNE_TIME (5) 854 855 /* 856 * If active scanning is requested but a certain channel is 857 * marked passive, we can do active scanning if we detect 858 * transmissions. 859 * 860 * There is an issue with some firmware versions that triggers 861 * a sysassert on a "good CRC threshold" of zero (== disabled), 862 * on a radar channel even though this means that we should NOT 863 * send probes. 864 * 865 * The "good CRC threshold" is the number of frames that we 866 * need to receive during our dwell time on a channel before 867 * sending out probes -- setting this to a huge value will 868 * mean we never reach it, but at the same time work around 869 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 870 * here instead of IWN_GOOD_CRC_TH_DISABLED. 871 * 872 * This was fixed in later versions along with some other 873 * scan changes, and the threshold behaves as a flag in those 874 * versions. 875 */ 876 #define IWN_GOOD_CRC_TH_DISABLED 0 877 #define IWN_GOOD_CRC_TH_DEFAULT htole16(1) 878 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff) 879 880 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */ 881 #define IWN_RIDX_MAX 32 882 struct iwn4965_cmd_txpower { 883 uint8_t band; 884 uint8_t reserved1; 885 uint8_t chan; 886 uint8_t reserved2; 887 struct { 888 uint8_t rf_gain[2]; 889 uint8_t dsp_gain[2]; 890 } __packed power[IWN_RIDX_MAX + 1]; 891 } __packed; 892 893 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */ 894 struct iwn5000_cmd_txpower { 895 int8_t global_limit; /* in half-dBm */ 896 #define IWN5000_TXPOWER_AUTO 0x7f 897 #define IWN5000_TXPOWER_MAX_DBM 16 898 899 uint8_t flags; 900 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6) 901 902 int8_t srv_limit; /* in half-dBm */ 903 uint8_t reserved; 904 } __packed; 905 906 /* Structure for command IWN_CMD_BT_COEX. */ 907 struct iwn_bluetooth { 908 uint8_t flags; 909 #define IWN_BT_COEX_CHAN_ANN (1 << 0) 910 #define IWN_BT_COEX_BT_PRIO (1 << 1) 911 #define IWN_BT_COEX_2_WIRE (1 << 2) 912 #define IWN_BT_COEX_ENABLE (IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO) 913 uint8_t lead_time; 914 #define IWN_BT_LEAD_TIME_DEF 30 915 uint8_t max_kill; 916 #define IWN_BT_MAX_KILL_DEF 5 917 uint8_t bt3_timer_t7_value; 918 #define IWN_BT_BT3_T7_DEF 1 919 uint32_t kill_ack_mask; 920 #define IWN_BT_KILL_ACK_MASK_DEF htole32(0xffff0000) 921 uint32_t kill_cts_mask; 922 #define IWN_BT_KILL_CTS_MASK_DEF htole32(0xffff0000) 923 } __packed; 924 925 struct iwn_bt_basic { 926 struct iwn_bluetooth bt; 927 #define IWN_BT_BASIC_CHAN_INHIBITION 1 928 #define IWN_BT_BASIC_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5)) 929 #define IWN_BT_BASIC_MODE_SHIFT 3 930 #define IWN_BT_BASIC_MODE_DISABLED 0 931 #define IWN_BT_BASIC_MODE_LEGACY_2W 1 932 #define IWN_BT_BASIC_MODE_3W 2 933 #define IWN_BT_BASIC_MODE_4W 3 934 #define IWN_BT_UCODE_DEFAULT (1 << 6) 935 #define IWN_BT_SYNC_2_BT_DISABLE (1 << 7) 936 uint8_t bt3_prio_sample_time; 937 #define IWN_BT_BT3_PRIO_SAMPLE_DEF 2 938 uint8_t bt3_timer_t2_value; 939 #define IWN_BT_BT3_T2_DEF 12 940 uint16_t bt4_reaction_time; /* unused */ 941 uint32_t bt3_lookup_table[12]; 942 943 uint16_t reduce_txpower; /* bit 0 */ 944 #if 0 945 /* 946 * The original code causes problems with lint. These declarations 947 * could be fixed with lint tags, but the assignment to 948 * reduce_txpower in iwn_config_bt_coex_adv_config() cannot. 949 * For reference it remains here but is ifdef'ed out. 950 */ 951 union { 952 struct { 953 uint8_t reduce_txpower; /* bit 0 */ 954 uint8_t reserved; 955 }; 956 uint16_t bt4_decision; 957 }; 958 #endif 959 uint16_t valid; 960 #define IWN_BT_VALID_ENABLE_FLAGS htole16(1 << 0) 961 #define IWN_BT_VALID_BOOST htole16(1 << 1) 962 #define IWN_BT_VALID_MAX_KILL htole16(1 << 2) 963 #define IWN_BT_VALID_3W_TIMERS htole16(1 << 3) 964 #define IWN_BT_VALID_KILL_ACK_MASK htole16(1 << 4) 965 #define IWN_BT_VALID_KILL_CTS_MASK htole16(1 << 5) 966 #define IWN_BT_VALID_REDUCED_TX_PWR htole16(1 << 6) 967 #define IWN_BT_VALID_3W_LUT htole16(1 << 7) 968 #define IWN_BT_ALL_VALID_MASK (IWN_BT_VALID_ENABLE_FLAGS | \ 969 IWN_BT_VALID_BOOST | \ 970 IWN_BT_VALID_MAX_KILL | \ 971 IWN_BT_VALID_3W_TIMERS | \ 972 IWN_BT_VALID_KILL_ACK_MASK | \ 973 IWN_BT_VALID_KILL_CTS_MASK | \ 974 IWN_BT_VALID_REDUCED_TX_PWR | \ 975 IWN_BT_VALID_3W_LUT) 976 } __packed; 977 978 struct iwn_bt_adv1 { 979 struct iwn_bt_basic basic; 980 uint8_t prio_boost; 981 #define IWN_BT_PRIO_BOOST_DEF 0xf0 982 /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ 983 uint8_t tx_prio_boost; 984 uint16_t rx_prio_boost; 985 } __packed; 986 987 struct iwn_bt_adv2 { 988 struct iwn_bt_basic basic; 989 uint32_t prio_boost; 990 #define IWN_BT_PRIO_BOOST_DEF32 0xf0f0f0 991 uint8_t reserved; 992 /* set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask for */ 993 uint8_t tx_prio_boost; 994 uint16_t rx_prio_boost; 995 } __packed; 996 997 /* Structure for command IWN_CMD_BT_COEX_PRIOTABLE */ 998 struct iwn_btcoex_priotable { 999 uint8_t calib_init1; 1000 uint8_t calib_init2; 1001 uint8_t calib_periodic_low1; 1002 uint8_t calib_periodic_low2; 1003 uint8_t calib_periodic_high1; 1004 uint8_t calib_periodic_high2; 1005 uint8_t dtim; 1006 uint8_t scan52; 1007 uint8_t scan24; 1008 uint8_t reserved[7]; 1009 } __packed; 1010 1011 /* Structure for command IWN_CMD_BT_COEX_PROT */ 1012 struct iwn_btcoex_prot { 1013 uint8_t open; 1014 uint8_t type; 1015 uint8_t reserved[2]; 1016 } __packed; 1017 1018 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */ 1019 struct iwn_critical_temp { 1020 uint32_t reserved; 1021 uint32_t tempM; 1022 uint32_t tempR; 1023 /* degK <-> degC conversion macros. */ 1024 #define IWN_CTOK(c) ((c) + 273) 1025 #define IWN_KTOC(k) ((k) - 273) 1026 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000) 1027 } __packed; 1028 1029 /* Structures for command IWN_CMD_SET_SENSITIVITY. */ 1030 struct iwn_sensitivity_cmd { 1031 uint16_t which; 1032 #define IWN_SENSITIVITY_DEFAULTTBL 0 1033 #define IWN_SENSITIVITY_WORKTBL 1 1034 1035 uint16_t energy_cck; 1036 uint16_t energy_ofdm; 1037 uint16_t corr_ofdm_x1; 1038 uint16_t corr_ofdm_mrc_x1; 1039 uint16_t corr_cck_mrc_x4; 1040 uint16_t corr_ofdm_x4; 1041 uint16_t corr_ofdm_mrc_x4; 1042 uint16_t corr_barker; 1043 uint16_t corr_barker_mrc; 1044 uint16_t corr_cck_x4; 1045 uint16_t energy_ofdm_th; 1046 } __packed; 1047 1048 struct iwn_enhanced_sensitivity_cmd { 1049 uint16_t which; 1050 uint16_t energy_cck; 1051 uint16_t energy_ofdm; 1052 uint16_t corr_ofdm_x1; 1053 uint16_t corr_ofdm_mrc_x1; 1054 uint16_t corr_cck_mrc_x4; 1055 uint16_t corr_ofdm_x4; 1056 uint16_t corr_ofdm_mrc_x4; 1057 uint16_t corr_barker; 1058 uint16_t corr_barker_mrc; 1059 uint16_t corr_cck_x4; 1060 uint16_t energy_ofdm_th; 1061 /* "Enhanced" part. */ 1062 uint16_t ina_det_ofdm; 1063 uint16_t ina_det_cck; 1064 uint16_t corr_11_9_en; 1065 uint16_t ofdm_det_slope_mrc; 1066 uint16_t ofdm_det_icept_mrc; 1067 uint16_t ofdm_det_slope; 1068 uint16_t ofdm_det_icept; 1069 uint16_t cck_det_slope_mrc; 1070 uint16_t cck_det_icept_mrc; 1071 uint16_t cck_det_slope; 1072 uint16_t cck_det_icept; 1073 uint16_t reserved; 1074 } __packed; 1075 1076 /* Structures for command IWN_CMD_PHY_CALIB. */ 1077 struct iwn_phy_calib { 1078 uint8_t code; 1079 #define IWN4965_PHY_CALIB_DIFF_GAIN 7 1080 #define IWN5000_PHY_CALIB_DC 8 1081 #define IWN5000_PHY_CALIB_LO 9 1082 #define IWN5000_PHY_CALIB_TX_IQ 11 1083 #define IWN5000_PHY_CALIB_CRYSTAL 15 1084 #define IWN5000_PHY_CALIB_BASE_BAND 16 1085 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17 1086 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18 1087 #define IWN5000_PHY_CALIB_NOISE_GAIN 19 1088 1089 #define IWN6000_PHY_CALIB_TEMP_OFFSET 18 1090 #define IWN2000_PHY_CALIB_TEMP_OFFSET 18 1091 1092 #define IWN5000_PHY_CALIB_MAX 253 1093 1094 uint8_t group; 1095 uint8_t ngroups; 1096 uint8_t isvalid; 1097 } __packed; 1098 1099 struct iwn5000_phy_calib_crystal { 1100 uint8_t code; 1101 uint8_t group; 1102 uint8_t ngroups; 1103 uint8_t isvalid; 1104 1105 uint8_t cap_pin[2]; 1106 uint8_t reserved[2]; 1107 } __packed; 1108 1109 struct iwn6000_phy_calib_temp_offset { 1110 uint8_t code; 1111 uint8_t group; 1112 uint8_t ngroups; 1113 uint8_t isvalid; 1114 int16_t offset; 1115 #define IWN_DEFAULT_TEMP_OFFSET 2700 1116 1117 uint16_t reserved; 1118 } __packed; 1119 1120 struct iwn2000_phy_calib_temp_offset { 1121 uint8_t code; 1122 uint8_t group; 1123 uint8_t ngroups; 1124 uint8_t isvalid; 1125 int16_t offset_high; 1126 int16_t offset_low; 1127 int16_t burnt_voltage_ref; 1128 int16_t reserved; 1129 } __packed; 1130 1131 struct iwn_phy_calib_gain { 1132 uint8_t code; 1133 uint8_t group; 1134 uint8_t ngroups; 1135 uint8_t isvalid; 1136 1137 int8_t gain[3]; 1138 uint8_t reserved; 1139 } __packed; 1140 1141 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */ 1142 struct iwn_spectrum_cmd { 1143 uint16_t len; 1144 uint8_t token; 1145 uint8_t id; 1146 uint8_t origin; 1147 uint8_t periodic; 1148 uint16_t timeout; 1149 uint32_t start; 1150 uint32_t reserved1; 1151 uint32_t flags; 1152 uint32_t filter; 1153 uint16_t nchan; 1154 uint16_t reserved2; 1155 struct { 1156 uint32_t duration; 1157 uint8_t chan; 1158 uint8_t type; 1159 #define IWN_MEASUREMENT_BASIC (1 << 0) 1160 #define IWN_MEASUREMENT_CCA (1 << 1) 1161 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2) 1162 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3) 1163 #define IWN_MEASUREMENT_FRAME (1 << 4) 1164 #define IWN_MEASUREMENT_IDLE (1 << 7) 1165 1166 uint16_t reserved; 1167 } __packed chan[10]; 1168 } __packed; 1169 1170 /* Structure for IWN_UC_READY notification. */ 1171 #define IWN_NATTEN_GROUPS 5 1172 struct iwn_ucode_info { 1173 uint8_t minor; 1174 uint8_t major; 1175 uint16_t reserved1; 1176 uint8_t revision[8]; 1177 uint8_t type; 1178 uint8_t subtype; 1179 #define IWN_UCODE_RUNTIME 0 1180 #define IWN_UCODE_INIT 9 1181 1182 uint16_t reserved2; 1183 uint32_t logptr; 1184 uint32_t errptr; 1185 uint32_t tstamp; 1186 uint32_t valid; 1187 1188 /* The following fields are for UCODE_INIT only. */ 1189 int32_t volt; 1190 struct { 1191 int32_t chan20MHz; 1192 int32_t chan40MHz; 1193 } __packed temp[4]; 1194 int32_t atten[IWN_NATTEN_GROUPS][2]; 1195 } __packed; 1196 1197 /* Structures for IWN_TX_DONE notification. */ 1198 struct iwn4965_tx_stat { 1199 uint8_t nframes; 1200 uint8_t btkillcnt; 1201 uint8_t rtsfailcnt; 1202 uint8_t ackfailcnt; 1203 uint8_t rate; 1204 uint8_t rflags; 1205 uint16_t xrflags; 1206 uint16_t duration; 1207 uint16_t reserved; 1208 uint32_t power[2]; 1209 uint32_t status; 1210 } __packed; 1211 1212 struct iwn5000_tx_stat { 1213 uint8_t nframes; 1214 uint8_t btkillcnt; 1215 uint8_t rtsfailcnt; 1216 uint8_t ackfailcnt; 1217 uint8_t rate; 1218 uint8_t rflags; 1219 uint16_t xrflags; 1220 uint16_t duration; 1221 uint16_t reserved; 1222 uint32_t power[2]; 1223 uint32_t info; 1224 uint16_t seq; 1225 uint16_t len; 1226 uint8_t tlc; 1227 uint8_t ratid; 1228 uint8_t fc[2]; 1229 uint16_t status; 1230 uint16_t sequence; 1231 } __packed; 1232 1233 /* Structure for IWN_BEACON_MISSED notification. */ 1234 struct iwn_beacon_missed { 1235 uint32_t consecutive; 1236 uint32_t total; 1237 uint32_t expected; 1238 uint32_t received; 1239 } __packed; 1240 1241 /* Structure for IWN_MPDU_RX_DONE notification. */ 1242 struct iwn_rx_mpdu { 1243 uint16_t len; 1244 uint16_t reserved; 1245 } __packed; 1246 1247 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */ 1248 struct iwn4965_rx_phystat { 1249 uint16_t antenna; 1250 uint16_t agc; 1251 uint8_t rssi[6]; 1252 } __packed; 1253 1254 struct iwn5000_rx_phystat { 1255 uint32_t reserved1; 1256 uint32_t agc; 1257 uint16_t rssi[3]; 1258 } __packed; 1259 1260 struct iwn_rx_stat { 1261 uint8_t phy_len; 1262 uint8_t cfg_phy_len; 1263 #define IWN_STAT_MAXLEN 20 1264 1265 uint8_t id; 1266 uint8_t reserved1; 1267 uint64_t tstamp; 1268 uint32_t beacon; 1269 uint16_t flags; 1270 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2) 1271 1272 uint16_t chan; 1273 uint8_t phybuf[32]; 1274 uint8_t rate; 1275 uint8_t rflags; 1276 uint16_t xrflags; 1277 uint16_t len; 1278 uint16_t reserve3; 1279 } __packed; 1280 1281 #define IWN_RSSI_TO_DBM 44 1282 1283 /* Structure for IWN_RX_COMPRESSED_BA notification. */ 1284 struct iwn_compressed_ba { 1285 uint8_t macaddr[IEEE80211_ADDR_LEN]; 1286 uint16_t reserved; 1287 uint8_t id; 1288 uint8_t tid; 1289 uint16_t seq; 1290 uint64_t bitmap; 1291 uint16_t qid; 1292 uint16_t ssn; 1293 } __packed; 1294 1295 /* Structure for IWN_START_SCAN notification. */ 1296 struct iwn_start_scan { 1297 uint64_t tstamp; 1298 uint32_t tbeacon; 1299 uint8_t chan; 1300 uint8_t band; 1301 uint16_t reserved; 1302 uint32_t status; 1303 } __packed; 1304 1305 /* Structure for IWN_STOP_SCAN notification. */ 1306 struct iwn_stop_scan { 1307 uint8_t nchan; 1308 uint8_t status; 1309 uint8_t reserved; 1310 uint8_t chan; 1311 uint64_t tsf; 1312 } __packed; 1313 1314 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */ 1315 struct iwn_spectrum_notif { 1316 uint8_t id; 1317 uint8_t token; 1318 uint8_t idx; 1319 uint8_t state; 1320 #define IWN_MEASUREMENT_START 0 1321 #define IWN_MEASUREMENT_STOP 1 1322 1323 uint32_t start; 1324 uint8_t band; 1325 uint8_t chan; 1326 uint8_t type; 1327 uint8_t reserved1; 1328 uint32_t cca_ofdm; 1329 uint32_t cca_cck; 1330 uint32_t cca_time; 1331 uint8_t basic; 1332 uint8_t reserved2[3]; 1333 uint32_t ofdm[8]; 1334 uint32_t cck[8]; 1335 uint32_t stop; 1336 uint32_t status; 1337 #define IWN_MEASUREMENT_OK 0 1338 #define IWN_MEASUREMENT_CONCURRENT 1 1339 #define IWN_MEASUREMENT_CSA_CONFLICT 2 1340 #define IWN_MEASUREMENT_TGH_CONFLICT 3 1341 #define IWN_MEASUREMENT_STOPPED 6 1342 #define IWN_MEASUREMENT_TIMEOUT 7 1343 #define IWN_MEASUREMENT_FAILED 8 1344 } __packed; 1345 1346 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */ 1347 struct iwn_rx_phy_stats { 1348 uint32_t ina; 1349 uint32_t fina; 1350 uint32_t bad_plcp; 1351 uint32_t bad_crc32; 1352 uint32_t overrun; 1353 uint32_t eoverrun; 1354 uint32_t good_crc32; 1355 uint32_t fa; 1356 uint32_t bad_fina_sync; 1357 uint32_t sfd_timeout; 1358 uint32_t fina_timeout; 1359 uint32_t no_rts_ack; 1360 uint32_t rxe_limit; 1361 uint32_t ack; 1362 uint32_t cts; 1363 uint32_t ba_resp; 1364 uint32_t dsp_kill; 1365 uint32_t bad_mh; 1366 uint32_t rssi_sum; 1367 uint32_t reserved; 1368 } __packed; 1369 1370 struct iwn_rx_general_stats { 1371 uint32_t bad_cts; 1372 uint32_t bad_ack; 1373 uint32_t not_bss; 1374 uint32_t filtered; 1375 uint32_t bad_chan; 1376 uint32_t beacons; 1377 uint32_t missed_beacons; 1378 uint32_t adc_saturated; /* time in 0.8us */ 1379 uint32_t ina_searched; /* time in 0.8us */ 1380 int32_t noise[3]; 1381 uint32_t flags; 1382 uint32_t load; 1383 uint32_t fa; 1384 uint32_t rssi[3]; 1385 uint32_t energy[3]; 1386 } __packed; 1387 1388 struct iwn_rx_ht_phy_stats { 1389 uint32_t bad_plcp; 1390 uint32_t overrun; 1391 uint32_t eoverrun; 1392 uint32_t good_crc32; 1393 uint32_t bad_crc32; 1394 uint32_t bad_mh; 1395 uint32_t good_ampdu_crc32; 1396 uint32_t ampdu; 1397 uint32_t fragment; 1398 uint32_t reserved; 1399 } __packed; 1400 1401 struct iwn_rx_stats { 1402 struct iwn_rx_phy_stats ofdm; 1403 struct iwn_rx_phy_stats cck; 1404 struct iwn_rx_general_stats general; 1405 struct iwn_rx_ht_phy_stats ht; 1406 } __packed; 1407 1408 struct iwn_tx_stats { 1409 uint32_t preamble; 1410 uint32_t rx_detected; 1411 uint32_t bt_defer; 1412 uint32_t bt_kill; 1413 uint32_t short_len; 1414 uint32_t cts_timeout; 1415 uint32_t ack_timeout; 1416 uint32_t exp_ack; 1417 uint32_t ack; 1418 uint32_t msdu; 1419 uint32_t busrt_err1; 1420 uint32_t burst_err2; 1421 uint32_t cts_collision; 1422 uint32_t ack_collision; 1423 uint32_t ba_timeout; 1424 uint32_t ba_resched; 1425 uint32_t query_ampdu; 1426 uint32_t query; 1427 uint32_t query_ampdu_frag; 1428 uint32_t query_mismatch; 1429 uint32_t not_ready; 1430 uint32_t underrun; 1431 uint32_t bt_ht_kill; 1432 uint32_t rx_ba_resp; 1433 uint32_t reserved[2]; 1434 } __packed; 1435 1436 struct iwn_general_stats { 1437 uint32_t temp; 1438 uint32_t temp_m; 1439 uint32_t burst_check; 1440 uint32_t burst; 1441 uint32_t reserved1[4]; 1442 uint32_t sleep; 1443 uint32_t slot_out; 1444 uint32_t slot_idle; 1445 uint32_t ttl_tstamp; 1446 uint32_t tx_ant_a; 1447 uint32_t tx_ant_b; 1448 uint32_t exec; 1449 uint32_t probe; 1450 uint32_t reserved2[2]; 1451 uint32_t rx_enabled; 1452 uint32_t reserved3[3]; 1453 } __packed; 1454 1455 struct iwn_stats { 1456 uint32_t flags; 1457 struct iwn_rx_stats rx; 1458 struct iwn_tx_stats tx; 1459 struct iwn_general_stats general; 1460 } __packed; 1461 1462 1463 /* Firmware error dump. */ 1464 struct iwn_fw_dump { 1465 uint32_t valid; 1466 uint32_t id; 1467 uint32_t pc; 1468 uint32_t branch_link[2]; 1469 uint32_t interrupt_link[2]; 1470 uint32_t error_data[2]; 1471 uint32_t src_line; 1472 uint32_t tsf; 1473 uint32_t time[2]; 1474 } __packed; 1475 1476 /* TLV firmware header. */ 1477 struct iwn_fw_tlv_hdr { 1478 uint32_t zero; /* Always 0, to differentiate from legacy. */ 1479 uint32_t signature; 1480 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */ 1481 1482 uint8_t descr[64]; 1483 uint32_t rev; 1484 #define IWN_FW_API(x) (((x) >> 8) & 0xff) 1485 1486 uint32_t build; 1487 uint64_t altmask; 1488 } __packed; 1489 1490 /* TLV header. */ 1491 struct iwn_fw_tlv { 1492 uint16_t type; 1493 #define IWN_FW_TLV_MAIN_TEXT 1 1494 #define IWN_FW_TLV_MAIN_DATA 2 1495 #define IWN_FW_TLV_INIT_TEXT 3 1496 #define IWN_FW_TLV_INIT_DATA 4 1497 #define IWN_FW_TLV_BOOT_TEXT 5 1498 #define IWN_FW_TLV_PBREQ_MAXLEN 6 1499 #define IWN_FW_TLV_ENH_SENS 14 1500 #define IWN_FW_TLV_PHY_CALIB 15 1501 #define IWN_FW_TLV_FLAGS 18 1502 1503 uint16_t alt; 1504 uint32_t len; 1505 } __packed; 1506 1507 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024) 1508 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024) 1509 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024) 1510 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024) 1511 #define IWN_FW_BOOT_TEXT_MAXSZ 1024 1512 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ) 1513 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ 1514 1515 /** 1516 * enum iwn_ucode_tlv_flag - ucode API flags 1517 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1518 * was a separate TLV but moved here to save space. 1519 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1520 * treats good CRC threshold as a boolean 1521 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1522 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1523 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1524 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1525 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1526 * offload profile config command. 1527 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 1528 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 1529 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1530 * (rather than two) IPv6 addresses 1531 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 1532 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1533 * from the probe request template. 1534 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 1535 * connection when going back to D0 1536 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1537 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1538 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 1539 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 1540 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 1541 * containing CAM (Continuous Active Mode) indication. 1542 */ 1543 enum iwn_ucode_tlv_flag { 1544 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0), 1545 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 1546 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2), 1547 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3), 1548 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 1549 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 1550 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6), 1551 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 1552 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 1553 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 1554 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 1555 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 1556 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 1557 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 1558 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 1559 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 1560 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 1561 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 1562 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 1563 }; 1564 1565 /* 1566 * Offsets into EEPROM. 1567 */ 1568 #define IWN_EEPROM_MAC 0x015 1569 #define IWN_EEPROM_SKU_CAP 0x045 1570 #define IWN_EEPROM_RFCFG 0x048 1571 #define IWN4965_EEPROM_DOMAIN 0x060 1572 #define IWN4965_EEPROM_BAND1 0x063 1573 #define IWN5000_EEPROM_REG 0x066 1574 #define IWN5000_EEPROM_CAL 0x067 1575 #define IWN4965_EEPROM_BAND2 0x072 1576 #define IWN4965_EEPROM_BAND3 0x080 1577 #define IWN4965_EEPROM_BAND4 0x08d 1578 #define IWN4965_EEPROM_BAND5 0x099 1579 #define IWN4965_EEPROM_BAND6 0x0a0 1580 #define IWN4965_EEPROM_BAND7 0x0a8 1581 #define IWN4965_EEPROM_MAXPOW 0x0e8 1582 #define IWN4965_EEPROM_VOLTAGE 0x0e9 1583 #define IWN4965_EEPROM_BANDS 0x0ea 1584 /* Indirect offsets. */ 1585 #define IWN5000_EEPROM_DOMAIN 0x001 1586 #define IWN5000_EEPROM_BAND1 0x004 1587 #define IWN5000_EEPROM_BAND2 0x013 1588 #define IWN5000_EEPROM_BAND3 0x021 1589 #define IWN5000_EEPROM_BAND4 0x02e 1590 #define IWN5000_EEPROM_BAND5 0x03a 1591 #define IWN5000_EEPROM_BAND6 0x041 1592 #define IWN5000_EEPROM_BAND7 0x049 1593 #define IWN6000_EEPROM_ENHINFO 0x054 1594 #define IWN5000_EEPROM_CRYSTAL 0x128 1595 #define IWN5000_EEPROM_TEMP 0x12a 1596 #define IWN5000_EEPROM_VOLT 0x12b 1597 #define IWN2000_EEPROM_RAWTEMP 0x12b 1598 1599 /* Possible flags for IWN_EEPROM_SKU_CAP. */ 1600 #define IWN_EEPROM_SKU_CAP_11N (1 << 6) 1601 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7) 1602 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8) 1603 1604 /* Possible flags for IWN_EEPROM_RFCFG. */ 1605 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3) 1606 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3) 1607 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3) 1608 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf) 1609 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf) 1610 1611 struct iwn_eeprom_chan { 1612 uint8_t flags; 1613 #define IWN_EEPROM_CHAN_VALID (1 << 0) 1614 #define IWN_EEPROM_CHAN_IBSS (1 << 1) 1615 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3) 1616 #define IWN_EEPROM_CHAN_RADAR (1 << 4) 1617 #define IWN_EEPROM_CHAN_WIDE (1 << 5) 1618 #define IWN_EEPROM_CHAN_DFS (1 << 7) 1619 1620 int8_t maxpwr; 1621 } __packed; 1622 1623 struct iwn_eeprom_enhinfo { 1624 uint16_t chan; 1625 int8_t chain[3]; /* max power in half-dBm */ 1626 uint8_t reserved; 1627 int8_t mimo2; /* max power in half-dBm */ 1628 int8_t mimo3; /* max power in half-dBm */ 1629 } __packed; 1630 1631 struct iwn5000_eeprom_calib_hdr { 1632 uint8_t version; 1633 uint8_t pa_type; 1634 uint16_t volt; 1635 } __packed; 1636 1637 #define IWN_NSAMPLES 3 1638 struct iwn4965_eeprom_chan_samples { 1639 uint8_t num; 1640 struct { 1641 uint8_t temp; 1642 uint8_t gain; 1643 uint8_t power; 1644 int8_t pa_det; 1645 } samples[2][IWN_NSAMPLES]; 1646 } __packed; 1647 1648 #define IWN_NBANDS 8 1649 struct iwn4965_eeprom_band { 1650 uint8_t lo; /* low channel number */ 1651 uint8_t hi; /* high channel number */ 1652 struct iwn4965_eeprom_chan_samples chans[2]; 1653 } __packed; 1654 1655 /* 1656 * Offsets of channels descriptions in EEPROM. 1657 */ 1658 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = { 1659 IWN4965_EEPROM_BAND1, 1660 IWN4965_EEPROM_BAND2, 1661 IWN4965_EEPROM_BAND3, 1662 IWN4965_EEPROM_BAND4, 1663 IWN4965_EEPROM_BAND5, 1664 IWN4965_EEPROM_BAND6, 1665 IWN4965_EEPROM_BAND7 1666 }; 1667 1668 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = { 1669 IWN5000_EEPROM_BAND1, 1670 IWN5000_EEPROM_BAND2, 1671 IWN5000_EEPROM_BAND3, 1672 IWN5000_EEPROM_BAND4, 1673 IWN5000_EEPROM_BAND5, 1674 IWN5000_EEPROM_BAND6, 1675 IWN5000_EEPROM_BAND7 1676 }; 1677 1678 #define IWN_CHAN_BANDS_COUNT 7 1679 #define IWN_MAX_CHAN_PER_BAND 14 1680 static const struct iwn_chan_band { 1681 uint8_t nchan; 1682 uint8_t chan[IWN_MAX_CHAN_PER_BAND]; 1683 } iwn_bands[] = { 1684 /* 20MHz channels, 2GHz band. */ 1685 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 1686 /* 20MHz channels, 5GHz band. */ 1687 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 1688 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 1689 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 1690 { 6, { 145, 149, 153, 157, 161, 165 } }, 1691 /* 40MHz channels (primary channels), 2GHz band. */ 1692 { 7, { 1, 2, 3, 4, 5, 6, 7 } }, 1693 /* 40MHz channels (primary channels), 5GHz band. */ 1694 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } 1695 }; 1696 1697 #define IWN1000_OTP_NBLOCKS 3 1698 #define IWN6000_OTP_NBLOCKS 4 1699 #define IWN6050_OTP_NBLOCKS 7 1700 1701 /* HW rate indices. */ 1702 #define IWN_RIDX_CCK1 0 1703 #define IWN_RIDX_OFDM6 4 1704 1705 static const struct iwn_rate { 1706 uint8_t rate; 1707 uint8_t plcp; 1708 uint8_t flags; 1709 } iwn_rates[IWN_RIDX_MAX + 1] = { 1710 { 2, 10, IWN_RFLAG_CCK }, 1711 { 4, 20, IWN_RFLAG_CCK }, 1712 { 11, 55, IWN_RFLAG_CCK }, 1713 { 22, 110, IWN_RFLAG_CCK }, 1714 { 12, 0xd, 0 }, 1715 { 18, 0xf, 0 }, 1716 { 24, 0x5, 0 }, 1717 { 36, 0x7, 0 }, 1718 { 48, 0x9, 0 }, 1719 { 72, 0xb, 0 }, 1720 { 96, 0x1, 0 }, 1721 { 108, 0x3, 0 }, 1722 { 120, 0x3, 0 } 1723 }; 1724 1725 #define IWN4965_MAX_PWR_INDEX 107 1726 1727 /* 1728 * RF Tx gain values from highest to lowest power (values obtained from 1729 * the reference driver.) 1730 */ 1731 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1732 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 1733 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38, 1734 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35, 1735 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31, 1736 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04, 1737 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01, 1738 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1739 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1740 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1741 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1742 }; 1743 1744 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1745 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 1746 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 1747 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 1748 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 1749 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24, 1750 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 1751 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13, 1752 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05, 1753 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 1754 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 1755 }; 1756 1757 /* 1758 * DSP pre-DAC gain values from highest to lowest power (values obtained 1759 * from the reference driver.) 1760 */ 1761 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1762 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1763 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1764 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1765 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1766 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1767 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1768 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a, 1769 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f, 1770 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 1771 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b 1772 }; 1773 1774 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = { 1775 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1776 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1777 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1778 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1779 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1780 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1781 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 1782 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 1783 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 1784 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e 1785 }; 1786 1787 /* 1788 * Power saving settings (values obtained from the reference driver.) 1789 */ 1790 #define IWN_NDTIMRANGES 3 1791 #define IWN_NPOWERLEVELS 6 1792 static const struct iwn_pmgt { 1793 uint32_t rxtimeout; 1794 uint32_t txtimeout; 1795 int32_t intval[5]; 1796 int skip_dtim; 1797 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = { 1798 /* DTIM <= 2 */ 1799 { 1800 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1801 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */ 1802 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */ 1803 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */ 1804 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */ 1805 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */ 1806 }, 1807 /* 3 <= DTIM <= 10 */ 1808 { 1809 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1810 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 1811 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */ 1812 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */ 1813 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */ 1814 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */ 1815 }, 1816 /* DTIM >= 11 */ 1817 { 1818 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 1819 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 1820 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 1821 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */ 1822 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 1823 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1824 } 1825 }; 1826 1827 struct iwn_sensitivity_limits { 1828 uint32_t min_ofdm_x1; 1829 uint32_t max_ofdm_x1; 1830 uint32_t min_ofdm_mrc_x1; 1831 uint32_t max_ofdm_mrc_x1; 1832 uint32_t min_ofdm_x4; 1833 uint32_t max_ofdm_x4; 1834 uint32_t min_ofdm_mrc_x4; 1835 uint32_t max_ofdm_mrc_x4; 1836 uint32_t min_cck_x4; 1837 uint32_t max_cck_x4; 1838 uint32_t min_cck_mrc_x4; 1839 uint32_t max_cck_mrc_x4; 1840 uint32_t min_energy_cck; 1841 uint32_t energy_cck; 1842 uint32_t energy_ofdm; 1843 }; 1844 1845 /* 1846 * RX sensitivity limits (values obtained from the reference driver.) 1847 */ 1848 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = { 1849 105, 140, 1850 220, 270, 1851 85, 120, 1852 170, 210, 1853 125, 200, 1854 200, 400, 1855 97, 1856 100, 1857 100 1858 }; 1859 1860 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = { 1861 120, 120, /* min = max for performance bug in DSP. */ 1862 240, 240, /* min = max for performance bug in DSP. */ 1863 90, 120, 1864 170, 210, 1865 125, 200, 1866 170, 400, 1867 95, 1868 95, 1869 95 1870 }; 1871 1872 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = { 1873 105, 105, /* min = max for performance bug in DSP. */ 1874 220, 220, /* min = max for performance bug in DSP. */ 1875 90, 120, 1876 170, 210, 1877 125, 200, 1878 170, 400, 1879 95, 1880 95, 1881 95 1882 }; 1883 1884 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = { 1885 120, 155, 1886 240, 290, 1887 90, 120, 1888 170, 210, 1889 125, 200, 1890 170, 400, 1891 95, 1892 95, 1893 95 1894 }; 1895 1896 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = { 1897 105, 110, 1898 192, 232, 1899 80, 145, 1900 128, 232, 1901 125, 175, 1902 160, 310, 1903 97, 1904 97, 1905 100 1906 }; 1907 1908 static const struct iwn_sensitivity_limits iwn2000_sensitivity_limits = { 1909 105, 110, 1910 192, 232, 1911 80, 145, 1912 128, 232, 1913 125, 175, 1914 160, 310, 1915 97, 1916 97, 1917 100 1918 }; 1919 1920 #ifndef IEEE80211_NO_HT 1921 /* Map TID to TX scheduler's FIFO. */ 1922 static const uint8_t iwn_tid2fifo[] = { 1923 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3 1924 }; 1925 #endif 1926 1927 #ifdef notyet 1928 /* WiFi/WiMAX coexist event priority table for 6050. */ 1929 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = { 1930 { 0x04, 0x03, 0x00, 0x00 }, 1931 { 0x04, 0x03, 0x00, 0x03 }, 1932 { 0x04, 0x03, 0x00, 0x03 }, 1933 { 0x04, 0x03, 0x00, 0x03 }, 1934 { 0x04, 0x03, 0x00, 0x00 }, 1935 { 0x04, 0x03, 0x00, 0x07 }, 1936 { 0x04, 0x03, 0x00, 0x00 }, 1937 { 0x04, 0x03, 0x00, 0x03 }, 1938 { 0x04, 0x03, 0x00, 0x03 }, 1939 { 0x04, 0x03, 0x00, 0x00 }, 1940 { 0x06, 0x03, 0x00, 0x07 }, 1941 { 0x04, 0x03, 0x00, 0x00 }, 1942 { 0x06, 0x06, 0x00, 0x03 }, 1943 { 0x04, 0x03, 0x00, 0x07 }, 1944 { 0x04, 0x03, 0x00, 0x00 }, 1945 { 0x04, 0x03, 0x00, 0x00 } 1946 }; 1947 #endif 1948 1949 /* Firmware errors. */ 1950 static const char * const iwn_fw_errmsg[] = { 1951 "OK", 1952 "FAIL", 1953 "BAD_PARAM", 1954 "BAD_CHECKSUM", 1955 "NMI_INTERRUPT_WDG", 1956 "SYSASSERT", 1957 "FATAL_ERROR", 1958 "BAD_COMMAND", 1959 "HW_ERROR_TUNE_LOCK", 1960 "HW_ERROR_TEMPERATURE", 1961 "ILLEGAL_CHAN_FREQ", 1962 "VCC_NOT_STABLE", 1963 "FH_ERROR", 1964 "NMI_INTERRUPT_HOST", 1965 "NMI_INTERRUPT_ACTION_PT", 1966 "NMI_INTERRUPT_UNKNOWN", 1967 "UCODE_VERSION_MISMATCH", 1968 "HW_ERROR_ABS_LOCK", 1969 "HW_ERROR_CAL_LOCK_FAIL", 1970 "NMI_INTERRUPT_INST_ACTION_PT", 1971 "NMI_INTERRUPT_DATA_ACTION_PT", 1972 "NMI_TRM_HW_ER", 1973 "NMI_INTERRUPT_TRM", 1974 "NMI_INTERRUPT_BREAKPOINT" 1975 "DEBUG_0", 1976 "DEBUG_1", 1977 "DEBUG_2", 1978 "DEBUG_3", 1979 "ADVANCED_SYSASSERT" 1980 }; 1981 1982 /* Find least significant bit that is set. */ 1983 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x)) 1984 1985 #define IWN_READ(sc, reg) \ 1986 iwn_read(sc, reg) 1987 1988 #define IWN_WRITE(sc, reg, val) \ 1989 iwn_write(sc, reg, val) 1990 1991 #define IWN_WRITE_1(sc, reg, val) \ 1992 iwn_write_1(sc, reg, val) 1993 1994 #define IWN_SETBITS(sc, reg, mask) \ 1995 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask)) 1996 1997 #define IWN_CLRBITS(sc, reg, mask) \ 1998 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask)) 1999 2000 #define IWN_BARRIER_WRITE(sc) \ 2001 membar_producer() 2002 2003 #define IWN_BARRIER_READ_WRITE(sc) \ 2004 (membar_producer(), membar_consumer()) 2005 2006 #endif /* _IF_IWNREG_H */ 2007