1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2007, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Sun elects to use this software under the BSD license. 13 */ 14 15 /* 16 * This file is provided under a dual BSD/GPLv2 license. When using or 17 * redistributing this file, you may do so under either license. 18 * 19 * GPL LICENSE SUMMARY 20 * 21 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. 22 * 23 * This program is free software; you can redistribute it and/or modify 24 * it under the terms of version 2 of the GNU Geeral Public License as 25 * published by the Free Software Foundation. 26 * 27 * This program is distributed in the hope that it will be useful, but 28 * WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 35 * USA 36 * 37 * The full GNU General Public License is included in this distribution 38 * in the file called LICENSE.GPL. 39 * 40 * Contact Information: 41 * James P. Ketrenos <ipw2100-admin@linux.intel.com> 42 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 43 * 44 * BSD LICENSE 45 * 46 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 53 * * Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * * Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in 57 * the documentation and/or other materials provided with the 58 * distribution. 59 * * Neither the name Intel Corporation nor the names of its 60 * contributors may be used to endorse or promote products derived 61 * from this software without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 64 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 65 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 66 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 67 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 68 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 69 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 70 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 71 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 72 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 74 */ 75 76 #ifndef _IWK_HW_H_ 77 #define _IWK_HW_H_ 78 79 #pragma ident "%Z%%M% %I% %E% SMI" 80 81 #ifdef __cplusplus 82 extern "C" { 83 #endif 84 85 /* 86 * maximum scatter/gather 87 */ 88 #define IWK_MAX_SCATTER (10) 89 90 /* 91 * Flow Handler Definitions 92 */ 93 #define FH_MEM_LOWER_BOUND (0x1000) 94 #define FH_MEM_UPPER_BOUND (0x1EF0) 95 96 #define IWK_FH_REGS_LOWER_BOUND (0x1000) 97 #define IWK_FH_REGS_UPPER_BOUND (0x2000) 98 99 /* 100 * TFDB Area - TFDs buffer table 101 */ 102 #define FH_MEM_TFDB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x000) 103 #define FH_MEM_TFDB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 104 105 /* 106 * channels 0 - 8 107 */ 108 #define FH_MEM_TFDB_CHNL_BUF0(x) (FH_MEM_TFDB_LOWER_BOUND + (x) * 0x100) 109 #define FH_MEM_TFDB_CHNL_BUF1(x) (FH_MEM_TFDB_LOWER_BOUND + 0x80 + (x) * 0x100) 110 111 /* 112 * TFDIB Area - TFD Immediate Buffer 113 */ 114 #define FH_MEM_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 115 #define FH_MEM_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) 116 117 /* 118 * channels 0 - 10 119 */ 120 #define FH_MEM_TFDIB_CHNL(x) (FH_MEM_TFDIB_LOWER_BOUND + (x) * 0x8) 121 122 /* 123 * TFDIB registers used in Service Mode 124 */ 125 #define FH_MEM_TFDIB_CHNL9_REG0 (FH_MEM_TFDIB_CHNL(9)) 126 #define FH_MEM_TFDIB_CHNL9_REG1 (FH_MEM_TFDIB_CHNL(9) + 4) 127 #define FH_MEM_TFDIB_CHNL10_REG0 (FH_MEM_TFDIB_CHNL(10)) 128 #define FH_MEM_TFDIB_CHNL10_REG1 (FH_MEM_TFDIB_CHNL(10) + 4) 129 130 /* 131 * Tx service channels 132 */ 133 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MASK (0xFFFFFFFF) 134 #define FH_MEM_TFDIB_DRAM_ADDR_MSB_MASK (0xF00000000) 135 #define FH_MEM_TFDIB_TB_LENGTH_MASK (0x0001FFFF) /* bits 16:0 */ 136 137 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_BITSHIFT (0) 138 #define FH_MEM_TFDIB_DRAM_ADDR_MSB_BITSHIFT (32) 139 #define FH_MEM_TFDIB_TB_LENGTH_BITSHIFT (0) 140 141 #define FH_MEM_TFDIB_REG0_ADDR_MASK (0xFFFFFFFF) 142 #define FH_MEM_TFDIB_REG1_ADDR_MASK (0xF0000000) 143 #define FH_MEM_TFDIB_REG1_LENGTH_MASK (0x0001FFFF) 144 145 #define FH_MEM_TFDIB_REG0_ADDR_BITSHIFT (0) 146 #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT (28) 147 #define FH_MEM_TFDIB_REG1_LENGTH_BITSHIFT (0) 148 149 /* 150 * TRB Area - Transmit Request Buffers 151 */ 152 #define FH_MEM_TRB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x0958) 153 #define FH_MEM_TRB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x0980) 154 155 /* 156 * channels 0 - 8 157 */ 158 #define FH_MEM_TRB_CHNL(x) (FH_MEM_TRB_LOWER_BOUND + (x) * 0x4) 159 160 /* 161 * Keep-Warm (KW) buffer base address. 162 * 163 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the 164 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 165 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host 166 * from going into a power-savings mode that would cause higher DRAM latency, 167 * and possible data over/under-runs, before all Tx/Rx is complete. 168 * 169 * Driver loads IWK_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 170 * of the buffer, which must be 4K aligned. Once this is set up, the 4965 171 * automatically invokes keep-warm accesses when normal accesses might not 172 * be sufficient to maintain fast DRAM response. 173 * 174 * Bit fields: 175 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 176 */ 177 #define IWK_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) 178 179 /* 180 * STAGB Area - Scheduler TAG Buffer 181 */ 182 #define FH_MEM_STAGB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x980) 183 #define FH_MEM_STAGB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 184 185 /* 186 * channels 0 - 8 187 */ 188 #define FH_MEM_STAGB_0(x) (FH_MEM_STAGB_LOWER_BOUND + (x) * 0x8) 189 #define FH_MEM_STAGB_1(x) (FH_MEM_STAGB_LOWER_BOUND + 0x4 + (x) * 0x8) 190 191 /* 192 * Tx service channels 193 */ 194 #define FH_MEM_SRAM_ADDR_9 (FH_MEM_STAGB_LOWER_BOUND + 0x048) 195 #define FH_MEM_SRAM_ADDR_10 (FH_MEM_STAGB_LOWER_BOUND + 0x04C) 196 197 #define FH_MEM_STAGB_SRAM_ADDR_MASK (0x00FFFFFF) 198 199 /* 200 * TFD Circular Buffers Base (CBBC) addresses 201 * 202 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident 203 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 204 * (see struct iwk_tfd_frame). These 16 pointer registers are offset by 0x04 205 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 206 * aligned (address bits 0-7 must be 0). 207 * 208 * Bit fields in each pointer register: 209 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 210 */ 211 #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 212 #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 213 214 /* 215 * queues 0 - 15 216 */ 217 #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4) 218 219 /* 220 * TAGR Area - TAG reconstruct table 221 */ 222 #define FH_MEM_TAGR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 223 #define FH_MEM_TAGR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA70) 224 225 /* 226 * TDBGR Area - Tx Debug Registers 227 */ 228 #define FH_MEM_TDBGR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x0A70) 229 #define FH_MEM_TDBGR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x0B20) 230 231 /* 232 * channels 0 - 10 233 */ 234 #define FH_MEM_TDBGR_CHNL(x) (FH_MEM_TDBGR_LOWER_BOUND + (x) * 0x10) 235 236 #define FH_MEM_TDBGR_CHNL_REG_0(x) (FH_MEM_TDBGR_CHNL(x)) 237 #define FH_MEM_TDBGR_CHNL_REG_1(x) (FH_MEM_TDBGR_CHNL_REG_0(x) + 0x4) 238 239 #define FH_MEM_TDBGR_CHNL_BYTES_TO_FIFO_MASK (0x000FFFFF) 240 #define FH_MEM_TDBGR_CHNL_BYTES_TO_FIFO_BITSHIFT (0) 241 242 /* 243 * RDBUF Area 244 */ 245 #define FH_MEM_RDBUF_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) 246 #define FH_MEM_RDBUF_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 247 #define FH_MEM_RDBUF_CHNL0 (FH_MEM_RDBUF_LOWER_BOUND) 248 249 /* 250 * Rx SRAM Control and Status Registers (RSCSR) 251 * 252 * These registers provide handshake between driver and 4965 for the Rx queue 253 * (this queue handles *all* command responses, notifications, Rx data, etc. 254 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx 255 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 256 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 257 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 258 * mapping between RBDs and RBs. 259 * 260 * Driver must allocate host DRAM memory for the following, and set the 261 * physical address of each into 4965 registers: 262 * 263 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 264 * entries (although any power of 2, up to 4096, is selectable by driver). 265 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 266 * (typically 4K, although 8K or 16K are also selectable by driver). 267 * Driver sets up RB size and number of RBDs in the CB via Rx config 268 * register FH_MEM_RCSR_CHNL0_CONFIG_REG. 269 * 270 * Bit fields within one RBD: 271 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned. 272 * 273 * Driver sets physical address [35:8] of base of RBD circular buffer 274 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 275 * 276 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers 277 * (RBs) have been filled, via a "write pointer", actually the index of 278 * the RB's corresponding RBD within the circular buffer. Driver sets 279 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 280 * 281 * Bit fields in lower dword of Rx status buffer (upper dword not used 282 * by driver; see struct iwk_shared, val0): 283 * 31-12: Not used by driver 284 * 11- 0: Index of last filled Rx buffer descriptor 285 * (4965 writes, driver reads this value) 286 * 287 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must 288 * enter pointers to these RBs into contiguous RBD circular buffer entries, 289 * and update the 4965's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 290 * 291 * This "write" index corresponds to the *next* RBD that the driver will make 292 * available, i.e. one RBD past the the tail of the ready-to-fill RBDs within 293 * the circular buffer. This value should initially be 0 (before preparing any 294 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 295 * wrap back to 0 at the end of the circular buffer (but don't wrap before 296 * "read" index has advanced past 1! See below). 297 * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 298 * 299 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular 300 * buffer), it updates the Rx status buffer in DRAM, 2) described above, 301 * to tell the driver the index of the latest filled RBD. The driver must 302 * read this "read" index from DRAM after receiving an Rx interrupt from 4965. 303 * 304 * The driver must also internally keep track of a third index, which is the 305 * next RBD to process. When receiving an Rx interrupt, driver should process 306 * all filled but unprocessed RBs up to, but not including, the RB 307 * corresponding to the "read" index. For example, if "read" index becomes "1", 308 * driver may process the RB pointed to by RBD 0. Depending on volume of 309 * traffic, there may be many RBs to process. 310 * 311 * If read index == write index, 4965 thinks there is no room to put new data. 312 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 313 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 314 * and "read" indexes; that is, make sure that there are no more than 254 315 * buffers waiting to be filled. 316 */ 317 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 318 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 319 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) 320 #define FH_MEM_RSCSR_CHNL1 (FH_MEM_RSCSR_LOWER_BOUND + 0x020) 321 322 /* 323 * Physical base address of 8-byte Rx Status buffer. 324 * Bit fields: 325 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 326 */ 327 328 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) 329 330 /* 331 * Physical base address of Rx Buffer Descriptor Circular Buffer. 332 * Bit fields: 333 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 334 */ 335 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) 336 337 /* 338 * Rx write pointer (index, really!). 339 * Bit fields: 340 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 341 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 342 */ 343 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) 344 #define FH_RSCSR_CHNL0_RBDCB_RPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) 345 346 #define FH_RSCSR_FRAME_SIZE_MASK (0x00000FFF) /* bits 0-11 */ 347 348 /* 349 * RSCSR registers used in Service mode 350 */ 351 #define FH_RSCSR_CHNL1_RB_WPTR_REG (FH_MEM_RSCSR_CHNL1) 352 #define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_REG (FH_MEM_RSCSR_CHNL1 + 0x004) 353 #define FH_RSCSR_CHNL1_RB_CHUNK_NUM_REG (FH_MEM_RSCSR_CHNL1 + 0x008) 354 #define FH_RSCSR_CHNL1_SRAM_ADDR_REG (FH_MEM_RSCSR_CHNL1 + 0x00C) 355 356 /* 357 * Rx Config/Status Registers (RCSR) 358 * Rx Config Reg for channel 0 (only channel used) 359 * 360 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 361 * normal operation (see bit fields). 362 * 363 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 364 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for 365 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 366 * 367 * Bit fields: 368 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 369 * '10' operate normally 370 * 29-24: reserved 371 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 372 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 373 * 19-18: reserved 374 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 375 * '10' 12K, '11' 16K. 376 * 15-14: reserved 377 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 378 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 379 * typical value 0x10 (about 1/2 msec) 380 * 3- 0: reserved 381 */ 382 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 383 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) 384 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) 385 #define FH_MEM_RCSR_CHNL1 (FH_MEM_RCSR_LOWER_BOUND + 0x020) 386 387 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) 388 #define FH_MEM_RCSR_CHNL0_CREDIT_REG (FH_MEM_RCSR_CHNL0 + 0x004) 389 #define FH_MEM_RCSR_CHNL0_RBD_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x008) 390 #define FH_MEM_RCSR_CHNL0_RB_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x00C) 391 #define FH_MEM_RCSR_CHNL0_RXPD_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x010) 392 393 #define FH_MEM_RCSR_CHNL0_RBD_STTS_FRAME_RB_CNT_MASK (0x7FFFFFF0) 394 395 /* 396 * RCSR registers used in Service mode 397 */ 398 #define FH_MEM_RCSR_CHNL1_CONFIG_REG (FH_MEM_RCSR_CHNL1) 399 #define FH_MEM_RCSR_CHNL1_RB_STTS_REG (FH_MEM_RCSR_CHNL1 + 0x00C) 400 #define FH_MEM_RCSR_CHNL1_RX_PD_STTS_REG (FH_MEM_RCSR_CHNL1 + 0x010) 401 402 /* 403 * Rx Shared Status Registers (RSSR) 404 * 405 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG), 406 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 407 * 408 * Bit fields: 409 * 24: 1 = Channel 0 is idle 410 * 411 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain 412 * default values that should not be altered by the driver. 413 */ 414 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) 415 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 416 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) 417 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) 418 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008) 419 420 /* 421 * Transmit DMA Channel Control/Status Registers (TCSR) 422 * 423 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels 424 * supported in hardware; config regs are separated by 0x20 bytes. 425 * 426 * To use a Tx DMA channel, driver must initialize its 427 * IWK_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 428 * 429 * IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 430 * IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 431 * 432 * All other bits should be 0. 433 * 434 * Bit fields: 435 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 436 * '10' operate normally 437 * 29- 4: Reserved, set to "0" 438 * 3: Enable internal DMA requests (1, normal operation), disable (0) 439 * 2- 0: Reserved, set to "0" 440 */ 441 #define IWK_FH_TCSR_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xD00) 442 #define IWK_FH_TCSR_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xE60) 443 444 #define IWK_FH_TCSR_CHNL_NUM (7) 445 #define IWK_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 446 (IWK_FH_TCSR_LOWER_BOUND + 0x20 * _chnl) 447 #define IWK_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 448 (IWK_FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x4) 449 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 450 (IWK_FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x8) 451 452 /* 453 * Tx Shared Status Registers (TSSR) 454 * 455 * After stopping Tx DMA channel (writing 0 to 456 * IWK_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 457 * IWK_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 458 * (channel's buffers empty | no pending requests). 459 * 460 * Bit fields: 461 * 31-24: 1 = Channel buffers empty (channel 7:0) 462 * 23-16: 1 = No pending requests (channel 7:0) 463 */ 464 #define IWK_FH_TSSR_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xEA0) 465 #define IWK_FH_TSSR_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xEC0) 466 467 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG (IWK_FH_TSSR_LOWER_BOUND + 0x008) 468 #define IWK_FH_TSSR_TX_STATUS_REG (IWK_FH_TSSR_LOWER_BOUND + 0x010) 469 470 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) 471 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) 472 473 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_64B (0x00000000) 474 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) 475 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_256B (0x00000800) 476 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_512B (0x00000C00) 477 478 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) 479 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) 480 481 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) 482 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) 483 484 #define IWK_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \ 485 ((1 << (_chnl)) << 24) 486 #define IWK_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \ 487 ((1 << (_chnl)) << 16) 488 489 #define IWK_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \ 490 (IWK_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \ 491 IWK_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl)) 492 493 /* 494 * SRVC 495 */ 496 #define IWK_FH_SRVC_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x9C8) 497 #define IWK_FH_SRVC_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x9D0) 498 499 #define IWK_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 500 (IWK_FH_SRVC_LOWER_BOUND + (_chnl - 9) * 0x4) 501 502 /* 503 * TFDIB 504 */ 505 #define IWK_FH_TFDIB_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x900) 506 #define IWK_FH_TFDIB_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x958) 507 508 #define IWK_FH_TFDIB_CTRL0_REG(_chnl) \ 509 (IWK_FH_TFDIB_LOWER_BOUND + 0x8 * _chnl) 510 #define IWK_FH_TFDIB_CTRL1_REG(_chnl) \ 511 (IWK_FH_TFDIB_LOWER_BOUND + 0x8 * _chnl + 0x4) 512 513 #define IWK_FH_SRVC_CHNL (9) 514 #define IWK_FH_TFDIB_CTRL1_REG_POS_MSB (28) 515 516 /* 517 * Debug Monitor Area 518 */ 519 #define FH_MEM_DM_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEE0) 520 #define FH_MEM_DM_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEF0) 521 #define FH_MEM_DM_CONTROL_MASK_REG (FH_MEM_DM_LOWER_BOUND) 522 #define FH_MEM_DM_CONTROL_START_REG (FH_MEM_DM_LOWER_BOUND + 0x004) 523 #define FH_MEM_DM_CONTROL_STATUS_REG (FH_MEM_DM_LOWER_BOUND + 0x008) 524 #define FH_MEM_DM_MONITOR_REG (FH_MEM_DM_LOWER_BOUND + 0x00C) 525 526 #define FH_TB1_ADDR_LOW_MASK (0xFFFFFFFF) /* bits 31:0 */ 527 #define FH_TB1_ADDR_HIGH_MASK (0xF00000000) /* bits 35:32 */ 528 #define FH_TB2_ADDR_LOW_MASK (0x0000FFFF) /* bits 15:0 */ 529 #define FH_TB2_ADDR_HIGH_MASK (0xFFFFF0000) /* bits 35:16 */ 530 531 #define FH_TB1_ADDR_LOW_BITSHIFT (0) 532 #define FH_TB1_ADDR_HIGH_BITSHIFT (32) 533 #define FH_TB2_ADDR_LOW_BITSHIFT (0) 534 #define FH_TB2_ADDR_HIGH_BITSHIFT (16) 535 536 #define FH_TB1_LENGTH_MASK (0x00000FFF) /* bits 11:0 */ 537 #define FH_TB2_LENGTH_MASK (0x00000FFF) /* bits 11:0 */ 538 539 /* 540 * number of FH channels including 2 service mode 541 */ 542 #define NUM_OF_FH_CHANNELS (10) 543 544 /* 545 * ctrl field bitology 546 */ 547 #define FH_TFD_CTRL_PADDING_MASK (0xC0000000) /* bits 31:30 */ 548 #define FH_TFD_CTRL_NUMTB_MASK (0x1F000000) /* bits 28:24 */ 549 550 #define FH_TFD_CTRL_PADDING_BITSHIFT (30) 551 #define FH_TFD_CTRL_NUMTB_BITSHIFT (24) 552 553 #define FH_TFD_GET_NUM_TBS(ctrl) \ 554 ((ctrl & FH_TFD_CTRL_NUMTB_MASK) >> FH_TFD_CTRL_NUMTB_BITSHIFT) 555 #define FH_TFD_GET_PADDING(ctrl) \ 556 ((ctrl & FH_TFD_CTRL_PADDING_MASK) >> FH_TFD_CTRL_PADDING_BITSHIFT) 557 558 /* TCSR: tx_config register values */ 559 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 560 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) 561 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_ARC (0x00000002) 562 563 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) 564 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) 565 566 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 567 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 568 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 569 570 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 571 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 572 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 573 574 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 575 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 576 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 577 578 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 579 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 580 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 581 582 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) 583 584 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 585 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 586 587 /* 588 * CBB table 589 */ 590 #define FH_CBB_ADDR_MASK 0x0FFFFFFF /* bits 27:0 */ 591 #define FH_CBB_ADDR_BIT_SHIFT (8) 592 593 /* 594 * RCSR: channel 0 rx_config register defines 595 */ 596 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ 597 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */ 598 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */ 599 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */ 600 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */ 601 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */ 602 603 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20) 604 #define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16) 605 606 #define FH_RCSR_GET_RDBC_SIZE(reg) \ 607 ((reg & FH_RCSR_RX_CONFIG_RDBC_SIZE_MASK) >> \ 608 FH_RCSR_RX_CONFIG_RDBC_SIZE_BITSHIFT) 609 610 /* 611 * RCSR: channel 1 rx_config register defines 612 */ 613 #define FH_RCSR_CHNL1_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ 614 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_MASK (0x00003000) /* bits 12-13 */ 615 616 /* 617 * RCSR: rx_config register values 618 */ 619 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 620 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 621 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 622 #define FH_RCSR_RX_CONFIG_SINGLE_FRAME_MODE (0x00008000) 623 624 #define FH_RCSR_RX_CONFIG_RDRBD_DISABLE_VAL (0x00000000) 625 #define FH_RCSR_RX_CONFIG_RDRBD_ENABLE_VAL (0x20000000) 626 627 #define IWK_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 628 629 /* 630 * RCSR channel 0 config register values 631 */ 632 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 633 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 634 635 /* 636 * RCSR channel 1 config register values 637 */ 638 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 639 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 640 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_RTC_VAL (0x00002000) 641 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_HOST_RTC_VAL (0x00003000) 642 643 /* 644 * RCSR: rb status register defines 645 */ 646 #define FH_RCSR_RB_BYTE_TO_SEND_MASK (0x0001FFFF) /* bits 0-16 */ 647 648 /* 649 * RSCSR: defs used in normal mode 650 */ 651 #define FH_RSCSR_CHNL0_RBDCB_WPTR_MASK (0x00000FFF) /* bits 0-11 */ 652 653 /* 654 * RSCSR: defs used in service mode 655 */ 656 #define FH_RSCSR_CHNL1_SRAM_ADDR_MASK (0x00FFFFFF) /* bits 0-23 */ 657 #define FH_RSCSR_CHNL1_RB_WPTR_MASK (0x0FFFFFFF) /* bits 0-27 */ 658 #define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_MASK (0x000000FF) /* bits 0-7 */ 659 660 /* 661 * RSSR: RX Enable Error IRQ to Driver register defines 662 */ 663 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV_NO_RBD (0x00400000) /* bit 22 */ 664 665 #define FH_DRAM2SRAM_DRAM_ADDR_HIGH_MASK (0xFFFFFFF00) /* bits 8-35 */ 666 #define FH_DRAM2SRAM_DRAM_ADDR_LOW_MASK (0x000000FF) /* bits 0-7 */ 667 668 #define FH_DRAM2SRAM_DRAM_ADDR_HIGH_BITSHIFT (8) /* bits 8-35 */ 669 670 /* 671 * RX DRAM status regs definitions 672 */ 673 #define FH_RX_RB_NUM_MASK (0x00000FFF) /* bits 0-11 */ 674 #define FH_RX_FRAME_NUM_MASK (0x0FFF0000) /* bits 16-27 */ 675 676 #define FH_RX_RB_NUM_BITSHIFT (0) 677 #define FH_RX_FRAME_NUM_BITSHIFT (16) 678 679 /* 680 * Tx Scheduler 681 * 682 * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs 683 * (Transmit Frame Descriptors) from up to 16 circular queues resident in 684 * host DRAM. It steers each frame's Tx command (which contains the frame 685 * data) through one of up to 7 prioritized Tx DMA FIFO channels within the 686 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 687 * but one DMA channel may take input from several queues. 688 * 689 * Tx DMA channels have dedicated purposes. For 4965, and are used as follows: 690 * BMC TODO: CONFIRM channel assignments, esp for 0/1 691 * 692 * 0 -- EDCA BK (background) frames, lowest priority 693 * 1 -- EDCA BE (best effort) frames, normal priority 694 * 2 -- EDCA VI (video) frames, higher priority 695 * 3 -- EDCA VO (voice) and management frames, highest priority 696 * 4 -- Commands (e.g. RXON, etc.) 697 * 5 -- HCCA short frames 698 * 6 -- HCCA long frames 699 * 7 -- not used by driver (device-internal only) 700 * 701 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 702 * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to 703 * support 11n aggregation via EDCA DMA channels. BMC confirm. 704 * 705 * The driver sets up each queue to work in one of two modes: 706 * 707 * 1) Scheduler-Ack, in which the scheduler automatically supports a 708 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 709 * contains TFDs for a unique combination of Recipient Address (RA) 710 * and Traffic Identifier (TID), that is, traffic of a given 711 * Quality-Of-Service (QOS) priority, destined for a single station. 712 * 713 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 714 * each frame within the BA window, including whether it's been transmitted, 715 * and whether it's been acknowledged by the receiving station. The device 716 * automatically processes block-acks received from the receiving STA, 717 * and reschedules un-acked frames to be retransmitted (successful 718 * Tx completion may end up being out-of-order). 719 * 720 * The driver must maintain the queue's Byte Count table in host DRAM 721 * (struct iwk_sched_queue_byte_cnt_tbl) for this mode. 722 * This mode does not support fragmentation. 723 * 724 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 725 * The device may automatically retry Tx, but will retry only one frame 726 * at a time, until receiving ACK from receiving station, or reaching 727 * retry limit and giving up. 728 * 729 * The command queue (#4) must use this mode! 730 * This mode does not require use of the Byte Count table in host DRAM. 731 * 732 * Driver controls scheduler operation via 3 means: 733 * 1) Scheduler registers 734 * 2) Shared scheduler data base in internal 4956 SRAM 735 * 3) Shared data in host DRAM 736 * 737 * Initialization: 738 * 739 * When loading, driver should allocate memory for: 740 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 741 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 742 * (1024 bytes for each queue). 743 * 744 * After receiving "Alive" response from uCode, driver must initialize 745 * the following (especially for queue #4, the command queue, otherwise 746 * the driver can't issue commands!): 747 * 748 * 1) 4965's scheduler data base area in SRAM: 749 * a) Read SRAM address of data base area from SCD_SRAM_BASE_ADDR 750 * b) Clear and Init SCD_CONTEXT_DATA_OFFSET area (size 128 bytes) 751 * c) Clear SCD_TX_STTS_BITMAP_OFFSET area (size 256 bytes) 752 * d) Clear (BMC and init?) SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) 753 * 754 * 2) Init SCD_DRAM_BASE_ADDR with physical base of Tx byte count circular 755 * buffer array, allocated by driver in host DRAM. 756 * 757 * 3) 758 */ 759 760 /* 761 * Max Tx window size is the max number of contiguous TFDs that the scheduler 762 * can keep track of at one time when creating block-ack chains of frames. 763 * Note that "64" matches the number of ack bits in a block-ack. 764 * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize 765 * SCD_CONTEXT_QUEUE_OFFSET(x) values. 766 */ 767 #define SCD_WIN_SIZE 64 768 #define SCD_FRAME_LIMIT 10 769 770 /* 771 * Memory mapped registers ... access via HBUS_TARG_PRPH regs 772 */ 773 #define SCD_START_OFFSET 0xa02c00 774 775 /* 776 * 4965 tells driver SRAM address for internal scheduler structs via this reg. 777 * Value is valid only after "Alive" response from uCode. 778 */ 779 #define SCD_SRAM_BASE_ADDR (SCD_START_OFFSET + 0x0) 780 781 /* 782 * Driver may need to update queue-empty bits after changing queue's 783 * write and read pointers (indexes) during (re-)initialization (i.e. when 784 * scheduler is not tracking what's happening). 785 * Bit fields: 786 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit 787 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty 788 * NOTE BMC: THIS REGISTER NOT USED BY LINUX DRIVER. 789 */ 790 #define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4) 791 792 /* 793 * Physical base address of array of byte count (BC) circular buffers (CBs). 794 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode. 795 * This register points to BC CB for queue 0, must be on 1024-byte boundary. 796 * Others are spaced by 1024 bytes. 797 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. 798 * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff). 799 * Bit fields: 800 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned. 801 */ 802 #define SCD_DRAM_BASE_ADDR (SCD_START_OFFSET + 0x10) 803 #define SCD_AIT (SCD_START_OFFSET + 0x18) 804 805 /* 806 * Enables any/all Tx DMA/FIFO channels. 807 * Scheduler generates requests for only the active channels. 808 * Set this to 0xff to enable all 8 channels (normal usage). 809 * Bit fields: 810 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7 811 */ 812 #define SCD_TXFACT (SCD_START_OFFSET + 0x1c) 813 814 /* 815 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue. 816 * Initialized and updated by driver as new TFDs are added to queue. 817 * NOTE: If using Block Ack, index must correspond to frame's 818 * Start Sequence Number; index = (SSN & 0xff) 819 * NOTE BMC: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses? 820 */ 821 #define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4) 822 823 /* 824 * Queue (x) Read Pointers (indexes, really!), one for each Tx queue. 825 * For FIFO mode, index indicates next frame to transmit. 826 * For Scheduler-ACK mode, index indicates first frame in Tx window. 827 * Initialized by driver, updated by scheduler. 828 */ 829 #define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4) 830 #define SCD_SETQUEUENUM (SCD_START_OFFSET + 0xa4) 831 #define SCD_SET_TXSTAT_TXED (SCD_START_OFFSET + 0xa8) 832 #define SCD_SET_TXSTAT_DONE (SCD_START_OFFSET + 0xac) 833 #define SCD_SET_TXSTAT_NOT_SCHD (SCD_START_OFFSET + 0xb0) 834 #define SCD_DECREASE_CREDIT (SCD_START_OFFSET + 0xb4) 835 #define SCD_DECREASE_SCREDIT (SCD_START_OFFSET + 0xb8) 836 #define SCD_LOAD_CREDIT (SCD_START_OFFSET + 0xbc) 837 #define SCD_LOAD_SCREDIT (SCD_START_OFFSET + 0xc0) 838 #define SCD_BAR (SCD_START_OFFSET + 0xc4) 839 #define SCD_BAR_DW0 (SCD_START_OFFSET + 0xc8) 840 #define SCD_BAR_DW1 (SCD_START_OFFSET + 0xcc) 841 842 /* 843 * Select which queues work in chain mode (1) vs. not (0). 844 * Use chain mode to build chains of aggregated frames. 845 * Bit fields: 846 * 31-16: Reserved 847 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time 848 * NOTE: If driver sets up queue for chain mode, it should be also set up 849 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x). 850 */ 851 #define SCD_QUEUECHAIN_SEL (SCD_START_OFFSET + 0xd0) 852 #define SCD_QUERY_REQ (SCD_START_OFFSET + 0xd8) 853 #define SCD_QUERY_RES (SCD_START_OFFSET + 0xdc) 854 #define SCD_PENDING_FRAMES (SCD_START_OFFSET + 0xe0) 855 856 /* 857 * Select which queues interrupt driver when read pointer (index) increments. 858 * Bit fields: 859 * 31-16: Reserved 860 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled 861 * NOTE BMC: THIS FUNCTIONALITY IS APPARENTLY A NO-OP. 862 */ 863 #define SCD_INTERRUPT_MASK (SCD_START_OFFSET + 0xe4) 864 #define SCD_INTERRUPT_THRESHOLD (SCD_START_OFFSET + 0xe8) 865 #define SCD_QUERY_MIN_FRAME_SIZE (SCD_START_OFFSET + 0x100) 866 867 /* 868 * Queue search status registers. One for each queue. 869 * Sets up queue mode and assigns queue to Tx DMA channel. 870 * Bit fields: 871 * 19-10: Write mask/enable bits for bits 0-9 872 * 9: Driver should init to "0" 873 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0). 874 * Driver should init to "1" for aggregation mode, or "0" otherwise. 875 * 7-6: Driver should init to "0" 876 * 5: Window Size Left; indicates whether scheduler can request 877 * another TFD, based on window size, etc. Driver should init 878 * this bit to "1" for aggregation mode, or "0" for non-agg. 879 * 4-1: Tx FIFO to use (range 0-7). 880 * 0: Queue is active (1), not active (0). 881 * Other bits should be written as "0" 882 * 883 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled 884 * via SCD_QUEUECHAIN_SEL. 885 */ 886 #define SCD_QUEUE_STATUS_BITS(x) (SCD_START_OFFSET + 0x104 + (x) * 4) 887 888 /* 889 * 4965 internal SRAM structures for scheduler, shared with driver ... 890 * Driver should clear and initialize the following areas after receiving 891 * "Alive" response from 4965 uCode, i.e. after initial 892 * uCode load, or after a uCode load done for error recovery: 893 * 894 * SCD_CONTEXT_DATA_OFFSET (size 128 bytes) 895 * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes) 896 * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) 897 * 898 * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR. 899 * All OFFSET values must be added to this base address. 900 * Use HBUS_TARG_MEM_* registers to access SRAM. 901 */ 902 903 /* 904 * Queue context. One 8-byte entry for each of 16 queues. 905 * 906 * Driver should clear this entire area (size 0x80) to 0 after receiving 907 * "Alive" notification from uCode. Additionally, driver should init 908 * each queue's entry as follows: 909 * 910 * LS Dword bit fields: 911 * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64. 912 * 913 * MS Dword bit fields: 914 * 16-22: Frame limit. Driver should init to 10 (0xa). 915 * 916 * Driver should init all other bits to 0. 917 * 918 * Init must be done after driver receives "Alive" response from 4965 uCode, 919 * and when setting up queue for aggregation. 920 */ 921 #define SCD_CONTEXT_DATA_OFFSET 0x380 922 923 /* 924 * Tx Status Bitmap 925 * 926 * Driver should clear this entire area (size 0x100) to 0 after receiving 927 * "Alive" notification from uCode. Area is used only by device itself; 928 * no other support (besides clearing) is required from driver. 929 */ 930 #define SCD_TX_STTS_BITMAP_OFFSET 0x400 931 932 /* 933 * RAxTID to queue translation mapping. 934 * 935 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be 936 * for only one combination of receiver address (RA) and traffic ID (TID), i.e. 937 * one QOS priority level destined for one station (for this link, not final 938 * destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit mappings, 939 * one for each of the 16 queues. If queue is not in Scheduler-ACK mode, the 940 * device ignores the mapping value. 941 * 942 * Bit fields, for each 16-bit map: 943 * 15-9: Reserved, set to 0 944 * 8-4: Index into device's station table for recipient station 945 * 3-0: Traffic ID (tid), range 0-15 946 * 947 * Driver should clear this entire area (size 32 bytes) to 0 after receiving 948 * "Alive" notification from uCode. To update a 16-bit map value, driver 949 * must read a dword-aligned value from device SRAM, replace the 16-bit map 950 * value of interest, and write the dword value back into device SRAM. 951 */ 952 #define SCD_TRANSLATE_TBL_OFFSET 0x500 953 #define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) 954 #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ 955 ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) 956 957 /* 958 * Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". 959 */ 960 #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ 961 ((1<<(hi))|((1<<(hi))-(1<<(lo)))) 962 963 #define SCD_MODE_REG_BIT_SEARCH_MODE (1<<0) 964 #define SCD_MODE_REG_BIT_SBYP_MODE (1<<1) 965 966 #define SCD_TXFIFO_POS_TID (0) 967 #define SCD_TXFIFO_POS_RA (4) 968 #define SCD_QUEUE_STTS_REG_POS_ACTIVE (0) 969 #define SCD_QUEUE_STTS_REG_POS_TXF (1) 970 #define SCD_QUEUE_STTS_REG_POS_WSL (5) 971 #define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) 972 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) 973 #define SCD_QUEUE_STTS_REG_MSK (0x0007FC00) 974 975 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 976 977 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) 978 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) 979 #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 980 #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 981 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 982 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 983 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 984 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 985 986 #define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010) 987 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) 988 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 989 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 990 #define CSR_HW_IF_CONFIG_REG_EEP_SEM (0x00200000) 991 992 /* IWK-END */ 993 994 #define RX_RES_PHY_CNT 14 995 996 #define STATISTICS_FLG_CLEAR (0x1) 997 #define STATISTICS_FLG_DISABLE_NOTIFICATION (0x2) 998 999 #define STATISTICS_REPLY_FLG_CLEAR (0x1) 1000 #define STATISTICS_REPLY_FLG_BAND_24G_MSK (0x2) 1001 #define STATISTICS_REPLY_FLG_TGJ_NARROW_BAND_MSK (0x4) 1002 #define STATISTICS_REPLY_FLG_FAT_MODE_MSK (0x8) 1003 #define RX_PHY_FLAGS_ANTENNAE_OFFSET (4) 1004 #define RX_PHY_FLAGS_ANTENNAE_MASK (0x70) 1005 1006 /* 1007 * Register and values 1008 */ 1009 #define CSR_BASE (0x0) 1010 #define HBUS_BASE (0x400) 1011 1012 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 1013 1014 /* 1015 * CSR (control and status registers) 1016 */ 1017 #define CSR_SW_VER (CSR_BASE+0x000) 1018 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 1019 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 1020 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 1021 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 1022 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */ 1023 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 1024 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */ 1025 #define CSR_GP_CNTRL (CSR_BASE+0x024) 1026 /* 0x028 - reserved */ 1027 #define CSR_EEPROM_REG (CSR_BASE+0x02c) 1028 #define CSR_EEPROM_GP (CSR_BASE+0x030) 1029 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 1030 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 1031 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 1032 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 1033 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 1034 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 1035 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 1036 1037 /* 1038 * BSM (Bootstrap State Machine) 1039 */ 1040 #define BSM_BASE (CSR_BASE + 0x3400) 1041 1042 #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */ 1043 #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */ 1044 #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */ 1045 #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */ 1046 #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */ 1047 1048 /* 1049 * pointers and size regs for bootstrap load and data SRAM save 1050 */ 1051 #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090) 1052 #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094) 1053 #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098) 1054 #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C) 1055 1056 /* 1057 * BSM special memory, stays powered during power-save sleeps 1058 */ 1059 #define BSM_SRAM_LOWER_BOUND (CSR_BASE + 0x3800) 1060 #define BSM_SRAM_SIZE (1024) 1061 1062 1063 /* 1064 * card static random access memory (SRAM) for processor data and instructs 1065 */ 1066 #define RTC_INST_LOWER_BOUND (0x00000) 1067 #define ALM_RTC_INST_UPPER_BOUND (0x14000) 1068 1069 #define RTC_DATA_LOWER_BOUND (0x800000) 1070 #define ALM_RTC_DATA_UPPER_BOUND (0x808000) 1071 1072 /* 1073 * HBUS (Host-side bus) 1074 */ 1075 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 1076 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 1077 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 1078 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 1079 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 1080 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 1081 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 1082 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 1083 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 1084 1085 /* 1086 * HW I/F configuration 1087 */ 1088 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100) 1089 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200) 1090 #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) 1091 #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) 1092 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) 1093 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) 1094 1095 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 1096 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 1097 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 1098 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 1099 1100 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 1101 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 1102 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 1103 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 1104 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER 1105 1106 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) 1107 1108 /* 1109 * interrupt flags in INTA, set by uCode or hardware (e.g. dma), 1110 * acknowledged (reset) by host writing "1" to flagged bits. 1111 */ 1112 #define BIT_INT_FH_RX \ 1113 (((uint32_t)1) << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 1114 #define BIT_INT_ERR (1<<29) /* DMA hardware error FH_INT[31] */ 1115 #define BIT_INT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ 1116 #define BIT_INT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ 1117 #define BIT_INT_SWERROR (1<<25) /* uCode error */ 1118 #define BIT_INT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 1119 #define BIT_INT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ 1120 #define BIT_INT_SW_RX (1<<3) /* Rx, command responses, 3945 */ 1121 #define BIT_INT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ 1122 #define BIT_INT_ALIVE (1<<0) /* uCode interrupts once it initializes */ 1123 1124 #define CSR_INI_SET_MASK (BIT_INT_FH_RX | \ 1125 BIT_INT_ERR | \ 1126 BIT_INT_FH_TX | \ 1127 BIT_INT_SWERROR | \ 1128 BIT_INT_RF_KILL | \ 1129 BIT_INT_SW_RX | \ 1130 BIT_INT_WAKEUP | \ 1131 BIT_INT_ALIVE) 1132 1133 /* 1134 * interrupt flags in FH (flow handler) (PCI busmaster DMA) 1135 */ 1136 #define BIT_FH_INT_ERR (((uint32_t)1) << 31) /* Error */ 1137 #define BIT_FH_INT_HI_PRIOR (1<<30) /* High priority Rx,bypass coalescing */ 1138 #define BIT_FH_INT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */ 1139 #define BIT_FH_INT_RX_CHNL1 (1<<17) /* Rx channel 1 */ 1140 #define BIT_FH_INT_RX_CHNL0 (1<<16) /* Rx channel 0 */ 1141 #define BIT_FH_INT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */ 1142 #define BIT_FH_INT_TX_CHNL1 (1<<1) /* Tx channel 1 */ 1143 #define BIT_FH_INT_TX_CHNL0 (1<<0) /* Tx channel 0 */ 1144 1145 #define FH_INT_RX_MASK (BIT_FH_INT_HI_PRIOR | \ 1146 BIT_FH_INT_RX_CHNL2 | \ 1147 BIT_FH_INT_RX_CHNL1 | \ 1148 BIT_FH_INT_RX_CHNL0) 1149 1150 #define FH_INT_TX_MASK (BIT_FH_INT_TX_CHNL6 | \ 1151 BIT_FH_INT_TX_CHNL1 | \ 1152 BIT_FH_INT_TX_CHNL0) 1153 1154 /* 1155 * RESET 1156 */ 1157 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 1158 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 1159 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 1160 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 1161 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 1162 1163 /* 1164 * GP (general purpose) CONTROL 1165 */ 1166 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 1167 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 1168 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 1169 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 1170 1171 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 1172 1173 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 1174 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 1175 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 1176 1177 /* 1178 * APMG (power management) constants 1179 */ 1180 #define APMG_CLK_CTRL_REG (0x003000) 1181 #define ALM_APMG_CLK_EN (0x003004) 1182 #define ALM_APMG_CLK_DIS (0x003008) 1183 #define ALM_APMG_PS_CTL (0x00300c) 1184 #define ALM_APMG_PCIDEV_STT (0x003010) 1185 #define ALM_APMG_RFKILL (0x003014) 1186 #define ALM_APMG_LARC_INT (0x00301c) 1187 #define ALM_APMG_LARC_INT_MSK (0x003020) 1188 1189 #define APMG_CLK_REG_VAL_DMA_CLK_RQT (0x00000200) 1190 #define APMG_CLK_REG_VAL_BSM_CLK_RQT (0x00000800) 1191 1192 #define APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ (0x04000000) 1193 1194 #define APMG_DEV_STATE_REG_VAL_L1_ACTIVE_DISABLE (0x00000800) 1195 1196 #define APMG_PS_CTRL_REG_MSK_POWER_SRC (0x03000000) 1197 #define APMG_PS_CTRL_REG_VAL_POWER_SRC_VMAIN (0x00000000) 1198 #define APMG_PS_CTRL_REG_VAL_POWER_SRC_VAUX (0x01000000) 1199 1200 /* 1201 * BSM (bootstrap state machine) 1202 */ 1203 /* 1204 * start boot load now 1205 */ 1206 #define BSM_WR_CTRL_REG_BIT_START (0x80000000) 1207 /* 1208 * enable boot after power up 1209 */ 1210 #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) 1211 1212 /* 1213 * DBM 1214 */ 1215 #define ALM_FH_SRVC_CHNL (6) 1216 1217 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20) 1218 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4) 1219 1220 #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000) 1221 1222 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000) 1223 1224 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000) 1225 1226 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000) 1227 1228 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000) 1229 1230 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000) 1231 1232 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1233 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) 1234 1235 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) 1236 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) 1237 1238 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1239 1240 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1241 1242 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1243 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1244 1245 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000) 1246 1247 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) 1248 1249 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) 1250 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) 1251 1252 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) 1253 1254 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) 1255 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) 1256 1257 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) 1258 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) 1259 1260 #define ALM_TB_MAX_BYTES_COUNT (0xFFF0) 1261 1262 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \ 1263 ((1LU << _channel) << 24) 1264 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \ 1265 ((1LU << _channel) << 16) 1266 1267 #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \ 1268 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \ 1269 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel)) 1270 #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ 1271 #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ 1272 1273 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 1274 1275 #define TFD_QUEUE_MIN 0 1276 #define TFD_QUEUE_MAX 6 1277 #define TFD_QUEUE_SIZE_MAX (256) 1278 1279 /* 1280 * spectrum and channel data structures 1281 */ 1282 #define IWK_NUM_SCAN_RATES (2) 1283 1284 #define IWK_SCAN_FLAG_24GHZ (1<<0) 1285 #define IWK_SCAN_FLAG_52GHZ (1<<1) 1286 #define IWK_SCAN_FLAG_ACTIVE (1<<2) 1287 #define IWK_SCAN_FLAG_DIRECT (1<<3) 1288 1289 #define IWK_MAX_CMD_SIZE 1024 1290 1291 #define IWK_DEFAULT_TX_RETRY 15 1292 #define IWK_MAX_TX_RETRY 16 1293 1294 #define RFD_SIZE 4 1295 #define NUM_TFD_CHUNKS 4 1296 1297 #define RX_QUEUE_SIZE 256 1298 #define RX_QUEUE_SIZE_LOG 8 1299 1300 /* 1301 * TX Queue Flag Definitions 1302 */ 1303 /* 1304 * use short preamble 1305 */ 1306 #define DCT_FLAG_LONG_PREAMBLE 0x00 1307 #define DCT_FLAG_SHORT_PREAMBLE 0x04 1308 1309 /* 1310 * ACK rx is expected to follow 1311 */ 1312 #define DCT_FLAG_ACK_REQD 0x80 1313 1314 #define IWK_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24 1315 #define IWK_MB_ROAMING_THRESHOLD_DEFAULT 8 1316 #define IWK_REAL_RATE_RX_PACKET_THRESHOLD 300 1317 1318 /* 1319 * QoS definitions 1320 */ 1321 #define CW_MIN_OFDM 15 1322 #define CW_MAX_OFDM 1023 1323 #define CW_MIN_CCK 31 1324 #define CW_MAX_CCK 1023 1325 1326 #define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM 1327 #define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM 1328 #define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1) 1329 #define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1) 1330 1331 #define QOS_TX0_CW_MIN_CCK CW_MIN_CCK 1332 #define QOS_TX1_CW_MIN_CCK CW_MIN_CCK 1333 #define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1) 1334 #define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1) 1335 1336 #define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM 1337 #define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM 1338 #define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM 1339 #define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1) 1340 1341 #define QOS_TX0_CW_MAX_CCK CW_MAX_CCK 1342 #define QOS_TX1_CW_MAX_CCK CW_MAX_CCK 1343 #define QOS_TX2_CW_MAX_CCK CW_MIN_CCK 1344 #define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1) 1345 1346 #define QOS_TX0_AIFS (3) 1347 #define QOS_TX1_AIFS (7) 1348 #define QOS_TX2_AIFS (2) 1349 #define QOS_TX3_AIFS (2) 1350 1351 #define QOS_TX0_ACM 0 1352 #define QOS_TX1_ACM 0 1353 #define QOS_TX2_ACM 0 1354 #define QOS_TX3_ACM 0 1355 1356 #define QOS_TX0_TXOP_LIMIT_CCK 0 1357 #define QOS_TX1_TXOP_LIMIT_CCK 0 1358 #define QOS_TX2_TXOP_LIMIT_CCK 6016 1359 #define QOS_TX3_TXOP_LIMIT_CCK 3264 1360 1361 #define QOS_TX0_TXOP_LIMIT_OFDM 0 1362 #define QOS_TX1_TXOP_LIMIT_OFDM 0 1363 #define QOS_TX2_TXOP_LIMIT_OFDM 3008 1364 #define QOS_TX3_TXOP_LIMIT_OFDM 1504 1365 1366 #define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM 1367 #define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM 1368 #define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM 1369 #define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM 1370 1371 #define DEF_TX0_CW_MIN_CCK CW_MIN_CCK 1372 #define DEF_TX1_CW_MIN_CCK CW_MIN_CCK 1373 #define DEF_TX2_CW_MIN_CCK CW_MIN_CCK 1374 #define DEF_TX3_CW_MIN_CCK CW_MIN_CCK 1375 1376 #define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM 1377 #define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM 1378 #define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM 1379 #define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM 1380 1381 #define DEF_TX0_CW_MAX_CCK CW_MAX_CCK 1382 #define DEF_TX1_CW_MAX_CCK CW_MAX_CCK 1383 #define DEF_TX2_CW_MAX_CCK CW_MAX_CCK 1384 #define DEF_TX3_CW_MAX_CCK CW_MAX_CCK 1385 1386 #define DEF_TX0_AIFS (2) 1387 #define DEF_TX1_AIFS (2) 1388 #define DEF_TX2_AIFS (2) 1389 #define DEF_TX3_AIFS (2) 1390 1391 #define DEF_TX0_ACM (0) 1392 #define DEF_TX1_ACM (0) 1393 #define DEF_TX2_ACM (0) 1394 #define DEF_TX3_ACM (0) 1395 1396 #define DEF_TX0_TXOP_LIMIT_CCK (0) 1397 #define DEF_TX1_TXOP_LIMIT_CCK (0) 1398 #define DEF_TX2_TXOP_LIMIT_CCK (0) 1399 #define DEF_TX3_TXOP_LIMIT_CCK (0) 1400 1401 #define DEF_TX0_TXOP_LIMIT_OFDM (0) 1402 #define DEF_TX1_TXOP_LIMIT_OFDM (0) 1403 #define DEF_TX2_TXOP_LIMIT_OFDM (0) 1404 #define DEF_TX3_TXOP_LIMIT_OFDM (0) 1405 1406 #define QOS_QOS_SETS (3) 1407 #define QOS_PARAM_SET_ACTIVE (0) 1408 #define QOS_PARAM_SET_DEF_CCK (1) 1409 #define QOS_PARAM_SET_DEF_OFDM (2) 1410 1411 #define CTRL_QOS_NO_ACK (0x0020) 1412 #define DCT_FLAG_EXT_QOS_ENABLED (0x10) 1413 1414 #define IWK_TX_QUEUE_AC0 (0) 1415 #define IWK_TX_QUEUE_AC1 (1) 1416 #define IWK_TX_QUEUE_AC2 (2) 1417 #define IWK_TX_QUEUE_AC3 (3) 1418 #define IWK_TX_QUEUE_HCCA_1 (5) 1419 #define IWK_TX_QUEUE_HCCA_2 (6) 1420 1421 #define U32_PAD(n) ((4-(n%4))%4) 1422 1423 #define AC_BE_TID_MASK 0x9 /* TID 0 and 3 */ 1424 #define AC_BK_TID_MASK 0x6 /* TID 1 and 2 */ 1425 1426 /* 1427 * Generic queue structure 1428 * 1429 * Contains common data for Rx and Tx queues 1430 */ 1431 #define TFD_CTL_COUNT_SET(n) (n<<24) 1432 #define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7) 1433 #define TFD_CTL_PAD_SET(n) (n<<28) 1434 #define TFD_CTL_PAD_GET(ctl) (ctl>>28) 1435 1436 #define TFD_TX_CMD_SLOTS 64 1437 #define TFD_CMD_SLOTS 32 1438 1439 /* 1440 * Tx/Rx Queues 1441 * 1442 * Most communication between driver and 4965 is via queues of data buffers. 1443 * For example, all commands that the driver issues to device's embedded 1444 * controller (uCode) are via the command queue (one of the Tx queues). All 1445 * uCode command responses/replies/notifications, including Rx frames, are 1446 * conveyed from uCode to driver via the Rx queue. 1447 * 1448 * Most support for these queues, including handshake support, resides in 1449 * structures in host DRAM, shared between the driver and the device. When 1450 * allocating this memory, the driver must make sure that data written by 1451 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's 1452 * cache memory), so DRAM and cache are consistent, and the device can 1453 * immediately see changes made by the driver. 1454 * 1455 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via 1456 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array 1457 * in DRAM containing 256 Transmit Frame Descriptors (TFDs). 1458 */ 1459 #define IWK_MAX_WIN_SIZE 64 1460 #define IWK_QUEUE_SIZE 256 1461 #define IWK_NUM_FIFOS 7 1462 #define IWK_NUM_QUEUES 16 1463 #define IWK_CMD_QUEUE_NUM 4 1464 #define IWK_KW_SIZE 0x1000 /* 4k */ 1465 1466 struct iwk_rate { 1467 union { 1468 struct { 1469 uint8_t rate; 1470 uint8_t flags; 1471 uint16_t ext_flags; 1472 } s; 1473 uint32_t rate_n_flags; 1474 } r; 1475 }; 1476 1477 struct iwk_dram_scratch { 1478 uint8_t try_cnt; 1479 uint8_t bt_kill_cnt; 1480 uint16_t reserved; 1481 }; 1482 1483 /* 1484 * START TEMPERATURE 1485 */ 1486 /* 1487 * 4965 temperature calculation. 1488 * 1489 * The driver must calculate the device temperature before calculating 1490 * a txpower setting (amplifier gain is temperature dependent). The 1491 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration 1492 * values used for the life of the driver, and one of which (R4) is the 1493 * real-time temperature indicator. 1494 * 1495 * uCode provides all 4 values to the driver via the "initialize alive" 1496 * notification (see struct iwk_init_alive_resp). After the runtime uCode 1497 * image loads, uCode updates the R4 value via statistics notifications 1498 * (see STATISTICS_NOTIFICATION), which occur after each received beacon 1499 * when associated, or can be requested via REPLY_STATISTICS_CMD. 1500 * 1501 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver 1502 * must sign-extend to 32 bits before applying formula below. 1503 * 1504 * Formula: 1505 * 1506 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8 1507 * 1508 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is 1509 * an additional correction, which should be centered around 0 degrees 1510 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for 1511 * centering the 97/100 correction around 0 degrees K. 1512 * 1513 * Add 273 to Kelvin value to find degrees Celsius, for comparing current 1514 * temperature with factory-measured temperatures when calculating txpower 1515 * settings. 1516 */ 1517 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 1518 #define TEMPERATURE_CALIB_A_VAL 259 1519 1520 /* 1521 * Limit range of calculated temperature to be between these Kelvin values 1522 */ 1523 #define IWK_TX_POWER_TEMPERATURE_MIN (263) 1524 #define IWK_TX_POWER_TEMPERATURE_MAX (410) 1525 1526 #define IWK_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ 1527 (((t) < IWK_TX_POWER_TEMPERATURE_MIN) || \ 1528 ((t) > IWK_TX_POWER_TEMPERATURE_MAX)) 1529 1530 /* 1531 * END TEMPERATURE 1532 */ 1533 1534 /* 1535 * START TXPOWER 1536 */ 1537 /* 1538 * 4965 txpower calculations rely on information from three sources: 1539 * 1540 * 1) EEPROM 1541 * 2) "initialize" alive notification 1542 * 3) statistics notifications 1543 * 1544 * EEPROM data consists of: 1545 * 1546 * 1) Regulatory information (max txpower and channel usage flags) is provided 1547 * separately for each channel that can possibly supported by 4965. 1548 * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz 1549 * (legacy) channels. 1550 * 1551 * See struct iwk_eeprom_channel for format, and struct iwk_eeprom for 1552 * locations in EEPROM. 1553 * 1554 * 2) Factory txpower calibration information is provided separately for 1555 * sub-bands of contiguous channels. 2.4GHz has just one sub-band, 1556 * but 5 GHz has several sub-bands. 1557 * 1558 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided. 1559 * 1560 * See struct iwk_eeprom_calib_info (and the tree of structures contained 1561 * within it) for format, and struct iwk_eeprom for locations in EEPROM. 1562 * 1563 * "Initialization alive" notification (see struct iwk_init_alive_resp) 1564 * consists of: 1565 * 1566 * 1) Temperature calculation parameters. 1567 * 1568 * 2) Power supply voltage measurement. 1569 * 1570 * 3) Tx gain compensation to balance 2 transmitters for MIMO use. 1571 * 1572 * Statistics notifications deliver: 1573 * 1574 * 1) Current values for temperature param R4. 1575 */ 1576 1577 /* 1578 * To calculate a txpower setting for a given desired target txpower, channel, 1579 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to 1580 * support MIMO and transmit diversity), driver must do the following: 1581 * 1582 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel. 1583 * Do not exceed regulatory limit; reduce target txpower if necessary. 1584 * 1585 * If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), 1586 * 2 transmitters will be used simultaneously; driver must reduce the 1587 * regulatory limit by 3 dB (half-power) for each transmitter, so the 1588 * combined total output of the 2 transmitters is within regulatory limits. 1589 * 1590 * 1591 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by 1592 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]); 1593 * reduce target txpower if necessary. 1594 * 1595 * Backoff values below are in 1/2 dB units (equivalent to steps in 1596 * txpower gain tables): 1597 * 1598 * OFDM 6 - 36 MBit: 10 steps (5 dB) 1599 * OFDM 48 MBit: 15 steps (7.5 dB) 1600 * OFDM 54 MBit: 17 steps (8.5 dB) 1601 * OFDM 60 MBit: 20 steps (10 dB) 1602 * CCK all rates: 10 steps (5 dB) 1603 * 1604 * Backoff values apply to saturation txpower on a per-transmitter basis; 1605 * when using MIMO (2 transmitters), each transmitter uses the same 1606 * saturation level provided in EEPROM, and the same backoff values; 1607 * no reduction (such as with regulatory txpower limits) is required. 1608 * 1609 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel 1610 * widths and 40 Mhz (.11n fat) channel widths; there is no separate 1611 * factory measurement for fat channels. 1612 * 1613 * The result of this step is the final target txpower. The rest of 1614 * the steps figure out the proper settings for the device. 1615 * 1616 * 1617 * 3) Determine (EEPROM) calibration subband for the target channel, by 1618 * comparing against first and last channels in each subband 1619 * (see struct iwk_eeprom_calib_subband_info). 1620 * 1621 * 1622 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets, 1623 * referencing the 2 factory-measured (sample) channels within the subband. 1624 * 1625 * Interpolation is based on difference between target channel's frequency 1626 * and the sample channels' frequencies. Since channel numbers are based 1627 * on frequency (5 MHz between each channel number), this is equivalent 1628 * to interpolating based on channel number differences. 1629 * 1630 * Note that the sample channels may or may not be the channels at the 1631 * edges of the subband. The target channel may be "outside" of the 1632 * span of the sampled channels. 1633 * 1634 * Driver may choose the pair (for 2 Tx chains) of measurements (see 1635 * struct iwk_eeprom_calib_ch_info) for which the actual measured 1636 * txpower comes closest to the desired txpower. Usually, though, 1637 * the middle set of measurements is closest to the regulatory limits, 1638 * and is therefore a good choice for all txpower calculations. 1639 * 1640 * Driver should interpolate both members of the chosen measurement pair, 1641 * i.e. for both Tx chains (radio transmitters), unless the driver knows 1642 * that only one of the chains will be used (e.g. only one tx antenna 1643 * connected, but this should be unusual). 1644 * 1645 * Driver should interpolate factory values for temperature, gain table 1646 * index, and actual power. The power amplifier detector values are 1647 * not used by the driver. 1648 * 1649 * If the target channel happens to be one of the sample channels, the 1650 * results should agree with the sample channel's measurements! 1651 * 1652 * 1653 * 5) Find difference between desired txpower and (interpolated) 1654 * factory-measured txpower. Using (interpolated) factory gain table index 1655 * as a starting point, adjust this index lower to increase txpower, 1656 * or higher to decrease txpower, until the target txpower is reached. 1657 * Each step in the gain table is 1/2 dB. 1658 * 1659 * For example, if factory measured txpower is 16 dBm, and target txpower 1660 * is 13 dBm, add 6 steps to the factory gain index to reduce txpower 1661 * by 3 dB. 1662 * 1663 * 1664 * 6) Find difference between current device temperature and (interpolated) 1665 * factory-measured temperature for sub-band. Factory values are in 1666 * degrees Celsius. To calculate current temperature, see comments for 1667 * "4965 temperature calculation". 1668 * 1669 * If current temperature is higher than factory temperature, driver must 1670 * increase gain (lower gain table index), and vice versa. 1671 * 1672 * Temperature affects gain differently for different channels: 1673 * 1674 * 2.4 GHz all channels: 3.5 degrees per half-dB step 1675 * 5 GHz channels 34-43: 4.5 degrees per half-dB step 1676 * 5 GHz channels >= 44: 4.0 degrees per half-dB step 1677 * 1678 * NOTE: Temperature can increase rapidly when transmitting, especially 1679 * with heavy traffic at high txpowers. Driver should update 1680 * temperature calculations often under these conditions to 1681 * maintain strong txpower in the face of rising temperature. 1682 * 1683 * 1684 * 7) Find difference between current power supply voltage indicator 1685 * (from "initialize alive") and factory-measured power supply voltage 1686 * indicator (EEPROM). 1687 * 1688 * If the current voltage is higher (indicator is lower) than factory 1689 * voltage, gain should be reduced (gain table index increased) by: 1690 * 1691 * (eeprom - current) / 7 1692 * 1693 * If the current voltage is lower (indicator is higher) than factory 1694 * voltage, gain should be increased (gain table index decreased) by: 1695 * 1696 * 2 * (current - eeprom) / 7 1697 * 1698 * If number of index steps in either direction turns out to be > 2, 1699 * something is wrong ... just use 0. 1700 * 1701 * NOTE: Voltage compensation is independent of band/channel. 1702 * 1703 * NOTE: "Initialize" uCode measures current voltage, which is assumed 1704 * to be constant after this initial measurement. Voltage 1705 * compensation for txpower (number of steps in gain table) 1706 * may be calculated once and used until the next uCode bootload. 1707 * 1708 * 1709 * 8) If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), 1710 * adjust txpower for each transmitter chain, so txpower is balanced 1711 * between the two chains. There are 5 pairs of tx_atten[group][chain] 1712 * values in "initialize alive", one pair for each of 5 channel ranges: 1713 * 1714 * Group 0: 5 GHz channel 34-43 1715 * Group 1: 5 GHz channel 44-70 1716 * Group 2: 5 GHz channel 71-124 1717 * Group 3: 5 GHz channel 125-200 1718 * Group 4: 2.4 GHz all channels 1719 * 1720 * Add the tx_atten[group][chain] value to the index for the target chain. 1721 * The values are signed, but are in pairs of 0 and a non-negative number, 1722 * so as to reduce gain (if necessary) of the "hotter" channel. This 1723 * avoids any need to double-check for regulatory compliance after 1724 * this step. 1725 * 1726 * 1727 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation 1728 * value to the index: 1729 * 1730 * Hardware rev B: 9 steps (4.5 dB) 1731 * Hardware rev C: 5 steps (2.5 dB) 1732 * 1733 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, 1734 * bits [3:2], 1 = B, 2 = C. 1735 * 1736 * NOTE: This compensation is in addition to any saturation backoff that 1737 * might have been applied in an earlier step. 1738 * 1739 * 1740 * 10) Select the gain table, based on band (2.4 vs 5 GHz). 1741 * 1742 * Limit the adjusted index to stay within the table! 1743 * 1744 * 1745 * 11) Read gain table entries for DSP and radio gain, place into appropriate 1746 * location(s) in command. 1747 */ 1748 1749 enum { 1750 HT_IE_EXT_CHANNEL_NONE = 0, 1751 HT_IE_EXT_CHANNEL_ABOVE, 1752 HT_IE_EXT_CHANNEL_INVALID, 1753 HT_IE_EXT_CHANNEL_BELOW, 1754 HT_IE_EXT_CHANNEL_MAX 1755 }; 1756 1757 enum { 1758 CALIB_CH_GROUP_1 = 0, 1759 CALIB_CH_GROUP_2 = 1, 1760 CALIB_CH_GROUP_3 = 2, 1761 CALIB_CH_GROUP_4 = 3, 1762 CALIB_CH_GROUP_5 = 4, 1763 CALIB_CH_GROUP_MAX 1764 }; 1765 1766 #define POWER_TABLE_NUM_HT_OFDM_ENTRIES (32) 1767 1768 /* 1769 * Temperature calibration offset is 3% 0C in Kelvin 1770 */ 1771 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 1772 #define TEMPERATURE_CALIB_A_VAL 259 1773 1774 #define IWK_TX_POWER_TEMPERATURE_MIN (263) 1775 #define IWK_TX_POWER_TEMPERATURE_MAX (410) 1776 1777 #define IWK_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ 1778 (((t) < IWK_TX_POWER_TEMPERATURE_MIN) || \ 1779 ((t) > IWK_TX_POWER_TEMPERATURE_MAX)) 1780 1781 #define IWK_TX_POWER_ILLEGAL_TEMPERATURE (300) 1782 1783 #define IWK_TX_POWER_TEMPERATURE_DIFFERENCE (2) 1784 1785 /* 1786 * When MIMO is used (2 transmitters operating simultaneously), driver should 1787 * limit each transmitter to deliver a max of 3 dB below the regulatory limit 1788 * for the device. That is, half power for each transmitter, so total power 1789 * is within regulatory limits. 1790 * 1791 * The value "6" represents number of steps in gain table to reduce power. 1792 * Each step is 1/2 dB. 1793 */ 1794 #define IWK_TX_POWER_MIMO_REGULATORY_COMPENSATION (6) 1795 1796 /* 1797 * Limit range of txpower output target to be between these values 1798 */ 1799 #define IWK_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */ 1800 #define IWK_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */ 1801 1802 /* 1803 * timeout equivalent to 3 minutes 1804 */ 1805 #define IWK_TX_POWER_TIMELIMIT_NOCALIB 1800000000 1806 1807 /* 1808 * CCK gain compensation. 1809 * 1810 * When calculating txpowers for CCK, after making sure that the target power 1811 * is within regulatory and saturation limits, driver must additionally 1812 * back off gain by adding these values to the gain table index. 1813 */ 1814 #define IWK_TX_POWER_CCK_COMPENSATION (9) 1815 #define IWK_TX_POWER_CCK_COMPENSATION_B_STEP (9) 1816 #define IWK_TX_POWER_CCK_COMPENSATION_C_STEP (5) 1817 1818 /* 1819 * 4965 power supply voltage compensation 1820 */ 1821 #define TX_POWER_IWK_VOLTAGE_CODES_PER_03V (7) 1822 1823 /* 1824 * Gain tables. 1825 * 1826 * The following tables contain pair of values for setting txpower, i.e. 1827 * gain settings for the output of the device's digital signal processor (DSP), 1828 * and for the analog gain structure of the transmitter. 1829 * 1830 * Each entry in the gain tables represents a step of 1/2 dB. Note that these 1831 * are *relative* steps, not indications of absolute output power. Output 1832 * power varies with temperature, voltage, and channel frequency, and also 1833 * requires consideration of average power (to satisfy regulatory constraints), 1834 * and peak power (to avoid distortion of the output signal). 1835 * 1836 * Each entry contains two values: 1837 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained 1838 * linear value that multiplies the output of the digital signal processor, 1839 * before being sent to the analog radio. 1840 * 2) Radio gain. This sets the analog gain of the radio Tx path. 1841 * It is a coarser setting, and behaves in a logarithmic (dB) fashion. 1842 * 1843 * EEPROM contains factory calibration data for txpower. This maps actual 1844 * measured txpower levels to gain settings in the "well known" tables 1845 * below ("well-known" means here that both factory calibration *and* the 1846 * driver work with the same table). 1847 * 1848 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table 1849 * has an extension (into negative indexes), in case the driver needs to 1850 * boost power setting for high device temperatures (higher than would be 1851 * present during factory calibration). A 5 Ghz EEPROM index of "40" 1852 * corresponds to the 49th entry in the table used by the driver. 1853 */ 1854 #define MIN_TX_GAIN_INDEX (0) 1855 #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) 1856 #define MAX_TX_GAIN_INDEX_52GHZ (98) 1857 #define MIN_TX_GAIN_52GHZ (98) 1858 #define MAX_TX_GAIN_INDEX_24GHZ (98) 1859 #define MIN_TX_GAIN_24GHZ (98) 1860 #define MAX_TX_GAIN (0) 1861 #define MAX_TX_GAIN_52GHZ_EXT (-9) 1862 1863 /* 1864 * 2.4 GHz gain table 1865 * 1866 * Index Dsp gain Radio gain 1867 * 0 110 0x3f 1868 * 1 104 0x3f 1869 * 2 98 0x3f 1870 * 3 110 0x3e 1871 * 4 104 0x3e 1872 * 5 98 0x3e 1873 * 6 110 0x3d 1874 * 7 104 0x3d 1875 * 8 98 0x3d 1876 * 9 110 0x3c 1877 * 10 104 0x3c 1878 * 11 98 0x3c 1879 * 12 110 0x3b 1880 * 13 104 0x3b 1881 * 14 98 0x3b 1882 * 15 110 0x3a 1883 * 16 104 0x3a 1884 * 17 98 0x3a 1885 * 18 110 0x39 1886 * 19 104 0x39 1887 * 20 98 0x39 1888 * 21 110 0x38 1889 * 22 104 0x38 1890 * 23 98 0x38 1891 * 24 110 0x37 1892 * 25 104 0x37 1893 * 26 98 0x37 1894 * 27 110 0x36 1895 * 28 104 0x36 1896 * 29 98 0x36 1897 * 30 110 0x35 1898 * 31 104 0x35 1899 * 32 98 0x35 1900 * 33 110 0x34 1901 * 34 104 0x34 1902 * 35 98 0x34 1903 * 36 110 0x33 1904 * 37 104 0x33 1905 * 38 98 0x33 1906 * 39 110 0x32 1907 * 40 104 0x32 1908 * 41 98 0x32 1909 * 42 110 0x31 1910 * 43 104 0x31 1911 * 44 98 0x31 1912 * 45 110 0x30 1913 * 46 104 0x30 1914 * 47 98 0x30 1915 * 48 110 0x6 1916 * 49 104 0x6 1917 * 50 98 0x6 1918 * 51 110 0x5 1919 * 52 104 0x5 1920 * 53 98 0x5 1921 * 54 110 0x4 1922 * 55 104 0x4 1923 * 56 98 0x4 1924 * 57 110 0x3 1925 * 58 104 0x3 1926 * 59 98 0x3 1927 * 60 110 0x2 1928 * 61 104 0x2 1929 * 62 98 0x2 1930 * 63 110 0x1 1931 * 64 104 0x1 1932 * 65 98 0x1 1933 * 66 110 0x0 1934 * 67 104 0x0 1935 * 68 98 0x0 1936 * 69 97 0 1937 * 70 96 0 1938 * 71 95 0 1939 * 72 94 0 1940 * 73 93 0 1941 * 74 92 0 1942 * 75 91 0 1943 * 76 90 0 1944 * 77 89 0 1945 * 78 88 0 1946 * 79 87 0 1947 * 80 86 0 1948 * 81 85 0 1949 * 82 84 0 1950 * 83 83 0 1951 * 84 82 0 1952 * 85 81 0 1953 * 86 80 0 1954 * 87 79 0 1955 * 88 78 0 1956 * 89 77 0 1957 * 90 76 0 1958 * 91 75 0 1959 * 92 74 0 1960 * 93 73 0 1961 * 94 72 0 1962 * 95 71 0 1963 * 96 70 0 1964 * 97 69 0 1965 * 98 68 0 1966 */ 1967 1968 /* 1969 * 5 GHz gain table 1970 * 1971 * Index Dsp gain Radio gain 1972 * -9 123 0x3F 1973 * -8 117 0x3F 1974 * -7 110 0x3F 1975 * -6 104 0x3F 1976 * -5 98 0x3F 1977 * -4 110 0x3E 1978 * -3 104 0x3E 1979 * -2 98 0x3E 1980 * -1 110 0x3D 1981 * 0 104 0x3D 1982 * 1 98 0x3D 1983 * 2 110 0x3C 1984 * 3 104 0x3C 1985 * 4 98 0x3C 1986 * 5 110 0x3B 1987 * 6 104 0x3B 1988 * 7 98 0x3B 1989 * 8 110 0x3A 1990 * 9 104 0x3A 1991 * 10 98 0x3A 1992 * 11 110 0x39 1993 * 12 104 0x39 1994 * 13 98 0x39 1995 * 14 110 0x38 1996 * 15 104 0x38 1997 * 16 98 0x38 1998 * 17 110 0x37 1999 * 18 104 0x37 2000 * 19 98 0x37 2001 * 20 110 0x36 2002 * 21 104 0x36 2003 * 22 98 0x36 2004 * 23 110 0x35 2005 * 24 104 0x35 2006 * 25 98 0x35 2007 * 26 110 0x34 2008 * 27 104 0x34 2009 * 28 98 0x34 2010 * 29 110 0x33 2011 * 30 104 0x33 2012 * 31 98 0x33 2013 * 32 110 0x32 2014 * 33 104 0x32 2015 * 34 98 0x32 2016 * 35 110 0x31 2017 * 36 104 0x31 2018 * 37 98 0x31 2019 * 38 110 0x30 2020 * 39 104 0x30 2021 * 40 98 0x30 2022 * 41 110 0x25 2023 * 42 104 0x25 2024 * 43 98 0x25 2025 * 44 110 0x24 2026 * 45 104 0x24 2027 * 46 98 0x24 2028 * 47 110 0x23 2029 * 48 104 0x23 2030 * 49 98 0x23 2031 * 50 110 0x22 2032 * 51 104 0x18 2033 * 52 98 0x18 2034 * 53 110 0x17 2035 * 54 104 0x17 2036 * 55 98 0x17 2037 * 56 110 0x16 2038 * 57 104 0x16 2039 * 58 98 0x16 2040 * 59 110 0x15 2041 * 60 104 0x15 2042 * 61 98 0x15 2043 * 62 110 0x14 2044 * 63 104 0x14 2045 * 64 98 0x14 2046 * 65 110 0x13 2047 * 66 104 0x13 2048 * 67 98 0x13 2049 * 68 110 0x12 2050 * 69 104 0x08 2051 * 70 98 0x08 2052 * 71 110 0x07 2053 * 72 104 0x07 2054 * 73 98 0x07 2055 * 74 110 0x06 2056 * 75 104 0x06 2057 * 76 98 0x06 2058 * 77 110 0x05 2059 * 78 104 0x05 2060 * 79 98 0x05 2061 * 80 110 0x04 2062 * 81 104 0x04 2063 * 82 98 0x04 2064 * 83 110 0x03 2065 * 84 104 0x03 2066 * 85 98 0x03 2067 * 86 110 0x02 2068 * 87 104 0x02 2069 * 88 98 0x02 2070 * 89 110 0x01 2071 * 90 104 0x01 2072 * 91 98 0x01 2073 * 92 110 0x00 2074 * 93 104 0x00 2075 * 94 98 0x00 2076 * 95 93 0x00 2077 * 96 88 0x00 2078 * 97 83 0x00 2079 * 98 78 0x00 2080 */ 2081 2082 /* 2083 * Sanity checks and default values for EEPROM regulatory levels. 2084 * If EEPROM values fall outside MIN/MAX range, use default values. 2085 * 2086 * Regulatory limits refer to the maximum average txpower allowed by 2087 * regulatory agencies in the geographies in which the device is meant 2088 * to be operated. These limits are SKU-specific (i.e. geography-specific), 2089 * and channel-specific; each channel has an individual regulatory limit 2090 * listed in the EEPROM. 2091 * 2092 * Units are in half-dBm (i.e. "34" means 17 dBm). 2093 */ 2094 #define IWK_TX_POWER_DEFAULT_REGULATORY_24 (34) 2095 #define IWK_TX_POWER_DEFAULT_REGULATORY_52 (34) 2096 #define IWK_TX_POWER_REGULATORY_MIN (0) 2097 #define IWK_TX_POWER_REGULATORY_MAX (34) 2098 2099 /* 2100 * Sanity checks and default values for EEPROM saturation levels. 2101 * If EEPROM values fall outside MIN/MAX range, use default values. 2102 * 2103 * Saturation is the highest level that the output power amplifier can produce 2104 * without significant clipping distortion. This is a "peak" power level. 2105 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK) 2106 * require differing amounts of backoff, relative to their average power output, 2107 * in order to avoid clipping distortion. 2108 * 2109 * Driver must make sure that it is violating neither the saturation limit, 2110 * nor the regulatory limit, when calculating Tx power settings for various 2111 * rates. 2112 * 2113 * Units are in half-dBm (i.e. "38" means 19 dBm). 2114 */ 2115 #define IWK_TX_POWER_DEFAULT_SATURATION_24 (38) 2116 #define IWK_TX_POWER_DEFAULT_SATURATION_52 (38) 2117 #define IWK_TX_POWER_SATURATION_MIN (20) 2118 #define IWK_TX_POWER_SATURATION_MAX (50) 2119 2120 /* 2121 * dv *0.4 = dt; so that 5 degrees temperature diff equals 2122 * 12.5 in voltage diff 2123 */ 2124 #define IWK_TX_TEMPERATURE_UPDATE_LIMIT 9 2125 2126 #define IWK_INVALID_CHANNEL (0xffffffff) 2127 #define IWK_TX_POWER_REGITRY_BIT (2) 2128 2129 #define MIN_IWK_TX_POWER_CALIB_DUR (100) 2130 #define IWK_CCK_FROM_OFDM_POWER_DIFF (-5) 2131 #define IWK_CCK_FROM_OFDM_INDEX_DIFF (9) 2132 2133 /* 2134 * Number of entries in the gain table 2135 */ 2136 #define POWER_GAIN_NUM_ENTRIES 78 2137 #define TX_POW_MAX_SESSION_NUM 5 2138 2139 /* 2140 * timeout equivalent to 3 minutes 2141 */ 2142 #define TX_IWK_TIMELIMIT_NOCALIB 1800000000 2143 2144 /* 2145 * Kedron TX_CALIB_STATES 2146 */ 2147 #define IWK_TX_CALIB_STATE_SEND_TX 0x00000001 2148 #define IWK_TX_CALIB_WAIT_TX_RESPONSE 0x00000002 2149 #define IWK_TX_CALIB_ENABLED 0x00000004 2150 #define IWK_TX_CALIB_XVT_ON 0x00000008 2151 #define IWK_TX_CALIB_TEMPERATURE_CORRECT 0x00000010 2152 #define IWK_TX_CALIB_WORKING_WITH_XVT 0x00000020 2153 #define IWK_TX_CALIB_XVT_PERIODICAL 0x00000040 2154 2155 #define NUM_IWK_TX_CALIB_SETTINS 5 /* Number of tx correction groups */ 2156 2157 #define IWK_MIN_POWER_IN_VP_TABLE 1 /* 0.5dBm multiplied by 2 */ 2158 /* 20dBm - multiplied by 2 - because entries are for each 0.5dBm */ 2159 #define IWK_MAX_POWER_IN_VP_TABLE 40 2160 #define IWK_STEP_IN_VP_TABLE 1 /* 0.5dB - multiplied by 2 */ 2161 #define IWK_NUM_POINTS_IN_VPTABLE \ 2162 (1 + IWK_MAX_POWER_IN_VP_TABLE - IWK_MIN_POWER_IN_VP_TABLE) 2163 2164 #define MIN_TX_GAIN_INDEX (0) 2165 #define MAX_TX_GAIN_INDEX_52GHZ (98) 2166 #define MIN_TX_GAIN_52GHZ (98) 2167 #define MAX_TX_GAIN_INDEX_24GHZ (98) 2168 #define MIN_TX_GAIN_24GHZ (98) 2169 #define MAX_TX_GAIN (0) 2170 2171 /* 2172 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance) 2173 * and thermal Txpower calibration. 2174 * 2175 * When calculating txpower, driver must compensate for current device 2176 * temperature; higher temperature requires higher gain. Driver must calculate 2177 * current temperature (see "4965 temperature calculation"), then compare vs. 2178 * factory calibration temperature in EEPROM; if current temperature is higher 2179 * than factory temperature, driver must *increase* gain by proportions shown 2180 * in table below. If current temperature is lower than factory, driver must 2181 * *decrease* gain. 2182 * 2183 * Different frequency ranges require different compensation, as shown below. 2184 */ 2185 /* 2186 * Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. 2187 */ 2188 #define CALIB_IWK_TX_ATTEN_GR1_FCH 34 2189 #define CALIB_IWK_TX_ATTEN_GR1_LCH 43 2190 2191 /* 2192 * Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. 2193 */ 2194 #define CALIB_IWK_TX_ATTEN_GR2_FCH 44 2195 #define CALIB_IWK_TX_ATTEN_GR2_LCH 70 2196 2197 /* 2198 * Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. 2199 */ 2200 #define CALIB_IWK_TX_ATTEN_GR3_FCH 71 2201 #define CALIB_IWK_TX_ATTEN_GR3_LCH 124 2202 2203 /* 2204 * Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. 2205 */ 2206 #define CALIB_IWK_TX_ATTEN_GR4_FCH 125 2207 #define CALIB_IWK_TX_ATTEN_GR4_LCH 200 2208 2209 /* 2210 * Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. 2211 */ 2212 #define CALIB_IWK_TX_ATTEN_GR5_FCH 1 2213 #define CALIB_IWK_TX_ATTEN_GR5_LCH 20 2214 2215 struct iwk_tx_power { 2216 uint8_t tx_gain; /* gain for analog radio */ 2217 uint8_t dsp_atten; /* gain for DSP */ 2218 }; 2219 2220 struct tx_power_dual_stream { 2221 uint16_t ramon_tx_gain; 2222 uint16_t dsp_predis_atten; 2223 }; 2224 2225 union tx_power_dual_stream_u { 2226 struct tx_power_dual_stream s; 2227 uint32_t dw; 2228 }; 2229 2230 struct iwk_tx_power_db { 2231 union tx_power_dual_stream_u 2232 ht_ofdm_power[POWER_TABLE_NUM_HT_OFDM_ENTRIES]; 2233 union tx_power_dual_stream_u legacy_cck_power; 2234 2235 }; 2236 2237 typedef struct iwk_tx_power_table_cmd { 2238 uint8_t band; 2239 uint8_t channel_normal_width; 2240 uint16_t channel; 2241 struct iwk_tx_power_db tx_power; 2242 } iwk_tx_power_table_cmd_t; 2243 2244 typedef struct iwk_channel_switch_cmd { 2245 uint8_t band; 2246 uint8_t expect_beacon; 2247 uint16_t channel; 2248 uint32_t rxon_flags; 2249 uint32_t rxon_filter_flags; 2250 uint32_t switch_time; 2251 struct iwk_tx_power_db tx_power; 2252 } iwk_channel_switch_cmd_t; 2253 2254 struct iwk_channel_switch_notif { 2255 uint16_t band; 2256 uint16_t channel; 2257 uint32_t status; 2258 }; 2259 2260 /* 2261 * END TXPOWER 2262 */ 2263 2264 /* 2265 * HT flags 2266 */ 2267 #define RXON_FLG_CONTROL_CHANNEL_LOCATION_MSK 0x400000 2268 #define RXON_FLG_CONTROL_CHANNEL_LOC_LOW_MSK 0x000000 2269 #define RXON_FLG_CONTROL_CHANNEL_LOC_HIGH_MSK 0x400000 2270 2271 #define RXON_FLG_HT_OPERATING_MODE_POS (23) 2272 #define RXON_FLG_HT_PROT_MSK 0x800000 2273 #define RXON_FLG_FAT_PROT_MSK 0x1000000 2274 2275 #define RXON_FLG_CHANNEL_MODE_POS (25) 2276 #define RXON_FLG_CHANNEL_MODE_MSK 0x06000000 2277 #define RXON_FLG_CHANNEL_MODE_LEGACY_MSK 0x00000000 2278 #define RXON_FLG_CHANNEL_MODE_PURE_40_MSK 0x02000000 2279 #define RXON_FLG_CHANNEL_MODE_MIXED_MSK 0x04000000 2280 2281 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK (0x1<<0) 2282 #define RXON_RX_CHAIN_VALID_MSK (0x7<<1) 2283 #define RXON_RX_CHAIN_VALID_POS (1) 2284 #define RXON_RX_CHAIN_FORCE_SEL_MSK (0x7<<4) 2285 #define RXON_RX_CHAIN_FORCE_SEL_POS (4) 2286 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK (0x7<<7) 2287 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2288 #define RXON_RX_CHAIN_CNT_MSK (0x3<<10) 2289 #define RXON_RX_CHAIN_CNT_POS (10) 2290 #define RXON_RX_CHAIN_MIMO_CNT_MSK (0x3<<12) 2291 #define RXON_RX_CHAIN_MIMO_CNT_POS (12) 2292 #define RXON_RX_CHAIN_MIMO_FORCE_MSK (0x1<<14) 2293 #define RXON_RX_CHAIN_MIMO_FORCE_POS (14) 2294 2295 #define MCS_DUP_6M_PLCP 0x20 2296 2297 /* 2298 * OFDM HT rate masks 2299 */ 2300 #define R_MCS_6M_MSK 0x1 2301 #define R_MCS_12M_MSK 0x2 2302 #define R_MCS_18M_MSK 0x4 2303 #define R_MCS_24M_MSK 0x8 2304 #define R_MCS_36M_MSK 0x10 2305 #define R_MCS_48M_MSK 0x20 2306 #define R_MCS_54M_MSK 0x40 2307 #define R_MCS_60M_MSK 0x80 2308 #define R_MCS_12M_DUAL_MSK 0x100 2309 #define R_MCS_24M_DUAL_MSK 0x200 2310 #define R_MCS_36M_DUAL_MSK 0x400 2311 #define R_MCS_48M_DUAL_MSK 0x800 2312 2313 #define RATE_MCS_CODE_MSK 0x7 2314 #define RATE_MCS_MIMO_POS 3 2315 #define RATE_MCS_MIMO_MSK 0x8 2316 #define RATE_MCS_HT_DUP_POS 5 2317 #define RATE_MCS_HT_DUP_MSK 0x20 2318 #define RATE_MCS_FLAGS_POS 8 2319 #define RATE_MCS_HT_POS 8 2320 #define RATE_MCS_HT_MSK 0x100 2321 #define RATE_MCS_CCK_POS 9 2322 #define RATE_MCS_CCK_MSK 0x200 2323 #define RATE_MCS_GF_POS 10 2324 #define RATE_MCS_GF_MSK 0x400 2325 2326 #define RATE_MCS_FAT_POS 11 2327 #define RATE_MCS_FAT_MSK 0x800 2328 #define RATE_MCS_DUP_POS 12 2329 #define RATE_MCS_DUP_MSK 0x1000 2330 #define RATE_MCS_SGI_POS 13 2331 #define RATE_MCS_SGI_MSK 0x2000 2332 2333 #define EEPROM_SEM_TIMEOUT 10 2334 #define EEPROM_SEM_RETRY_LIMIT 1000 2335 2336 /* 2337 * Antenna masks: 2338 * bit14:15 01 B inactive, A active 2339 * 10 B active, A inactive 2340 * 11 Both active 2341 */ 2342 #define RATE_MCS_ANT_A_POS 14 2343 #define RATE_MCS_ANT_B_POS 15 2344 #define RATE_MCS_ANT_A_MSK 0x4000 2345 #define RATE_MCS_ANT_B_MSK 0x8000 2346 #define RATE_MCS_ANT_AB_MSK 0xc000 2347 2348 #define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A)) 2349 #define is_siso(tbl) (((tbl) == LQ_SISO)) 2350 #define is_mimo(tbl) (((tbl) == LQ_MIMO)) 2351 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl)) 2352 #define is_a_band(tbl) (((tbl) == LQ_A)) 2353 #define is_g_and(tbl) (((tbl) == LQ_G)) 2354 2355 /* 2356 * RS_NEW_API: only TLC_RTS remains and moved to bit 0 2357 */ 2358 #define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1<<0) 2359 2360 #define LINK_QUAL_AC_NUM 4 2361 #define LINK_QUAL_MAX_RETRY_NUM 16 2362 2363 #define LINK_QUAL_ANT_A_MSK (1<<0) 2364 #define LINK_QUAL_ANT_B_MSK (1<<1) 2365 #define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK) 2366 2367 struct iwk_link_qual_general_params { 2368 uint8_t flags; 2369 uint8_t mimo_delimiter; 2370 uint8_t single_stream_ant_msk; 2371 uint8_t dual_stream_ant_msk; 2372 uint8_t start_rate_index[LINK_QUAL_AC_NUM]; 2373 }; 2374 2375 struct iwk_link_qual_agg_params { 2376 uint16_t agg_time_limit; 2377 uint8_t agg_dis_start_th; 2378 uint8_t agg_frame_cnt_limit; 2379 uint32_t reserved; 2380 }; 2381 2382 typedef struct iwk_link_quality_cmd { 2383 uint8_t sta_id; 2384 uint8_t reserved1; 2385 uint16_t control; 2386 struct iwk_link_qual_general_params general_params; 2387 struct iwk_link_qual_agg_params agg_params; 2388 uint32_t rate_n_flags[LINK_QUAL_MAX_RETRY_NUM]; 2389 uint32_t reserved2; 2390 } iwk_link_quality_cmd_t; 2391 2392 typedef struct iwk_rx_phy_res { 2393 uint8_t non_cfg_phy_cnt; /* non configurable DSP phy data byte count */ 2394 uint8_t cfg_phy_cnt; /* configurable DSP phy data byte count */ 2395 uint8_t stat_id; /* configurable DSP phy data set ID */ 2396 uint8_t reserved1; 2397 uint32_t timestampl; /* TSF at on air rise */ 2398 uint32_t timestamph; 2399 uint32_t beacon_time_stamp; /* beacon at on-air rise */ 2400 uint16_t phy_flags; /* general phy flags: band, modulation, ... */ 2401 uint16_t channel; /* channel number */ 2402 uint16_t non_cfg_phy[RX_RES_PHY_CNT]; /* upto 14 phy entries */ 2403 uint32_t reserved2; 2404 struct iwk_rate rate; /* rate in ucode internal format */ 2405 uint16_t byte_count; /* frame's byte-count */ 2406 uint16_t reserved3; 2407 } iwk_rx_phy_res_t; 2408 2409 struct iwk_rx_mpdu_res_start { 2410 uint16_t byte_count; 2411 uint16_t reserved; 2412 }; 2413 2414 #define IWK_AGC_DB_MASK (0x3f80) /* MASK(7,13) */ 2415 #define IWK_AGC_DB_POS (7) 2416 2417 /* 2418 * Fixed (non-configurable) rx data from phy 2419 */ 2420 struct iwk_rx_non_cfg_phy { 2421 uint16_t ant_selection; /* ant A bit 4, ant B bit 5, ant C bit 6 */ 2422 uint16_t agc_info; /* agc code 0:6, agc dB 7:13, reserved 14:15 */ 2423 uint8_t rssi_info[6]; /* we use even entries, 0/2/4 for A/B/C rssi */ 2424 uint8_t pad[2]; 2425 }; 2426 2427 /* 2428 * Byte Count Table Entry 2429 * 2430 * Bit fields: 2431 * 15-12: reserved 2432 * 11- 0: total to-be-transmitted byte count of frame (does not include command) 2433 */ 2434 struct iwk_queue_byte_cnt_entry { 2435 uint16_t val; 2436 }; 2437 2438 /* 2439 * Byte Count table 2440 * 2441 * Each Tx queue uses a byte-count table containing 320 entries: 2442 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that 2443 * duplicate the first 64 entries (to avoid wrap-around within a Tx window; 2444 * max Tx window is 64 TFDs). 2445 * 2446 * When driver sets up a new TFD, it must also enter the total byte count 2447 * of the frame to be transmitted into the corresponding entry in the byte 2448 * count table for the chosen Tx queue. If the TFD index is 0-63, the driver 2449 * must duplicate the byte count entry in corresponding index 256-319. 2450 * 2451 * "dont_care" padding puts each byte count table on a 1024-byte boundary; 2452 * 4965 assumes tables are separated by 1024 bytes. 2453 */ 2454 struct iwk_sched_queue_byte_cnt_tbl { 2455 struct iwk_queue_byte_cnt_entry tfd_offset[IWK_QUEUE_SIZE + 2456 IWK_MAX_WIN_SIZE]; 2457 uint8_t dont_care[1024 - (IWK_QUEUE_SIZE + IWK_MAX_WIN_SIZE) * 2458 sizeof (uint16_t)]; 2459 }; 2460 2461 /* 2462 * struct iwk_shared, handshake area for Tx and Rx 2463 * 2464 * For convenience in allocating memory, this structure combines 2 areas of 2465 * DRAM which must be shared between driver and 4965. These do not need to 2466 * be combined, if better allocation would result from keeping them separate: 2467 * TODO: Split these; carried over from 3945, doesn't work well for 4965. 2468 * 2469 * 1) The Tx byte count tables occupy 1024 bytes each (16 KBytes total for 2470 * 16 queues). Driver uses SCD_DRAM_BASE_ADDR to tell 4965 where to find 2471 * the first of these tables. 4965 assumes tables are 1024 bytes apart. 2472 * 2473 * 2) The Rx status (val0 and val1) occupies only 8 bytes. Driver uses 2474 * FH_RSCSR_CHNL0_STTS_WPTR_REG to tell 4965 where to find this area. 2475 * Driver reads val0 to determine the latest Receive Buffer Descriptor (RBD) 2476 * that has been filled by the 4965. 2477 * 2478 * Bit fields val0: 2479 * 31-12: Not used 2480 * 11- 0: Index of last filled Rx buffer descriptor (4965 writes, driver reads) 2481 * 2482 * Bit fields val1: 2483 * 31- 0: Not used 2484 */ 2485 typedef struct iwk_shared { 2486 struct iwk_sched_queue_byte_cnt_tbl 2487 queues_byte_cnt_tbls[IWK_NUM_QUEUES]; 2488 uint32_t val0; 2489 uint32_t val1; 2490 uint32_t padding1; /* so that allocation will be aligned to 16B */ 2491 uint32_t padding2; 2492 } iwk_shared_t; 2493 2494 2495 /* 2496 * struct iwk_tfd_frame_data 2497 * 2498 * Describes up to 2 buffers containing (contiguous) portions of a Tx frame. 2499 * Each buffer must be on dword boundary. 2500 * Up to 10 iwk_tfd_frame_data structures, describing up to 20 buffers, 2501 * may be filled within a TFD (iwk_tfd_frame). 2502 * 2503 * Bit fields in tb1_addr: 2504 * 31- 0: Tx buffer 1 address bits [31:0] 2505 * 2506 * Bit fields in val1: 2507 * 31-16: Tx buffer 2 address bits [15:0] 2508 * 15- 4: Tx buffer 1 length (bytes) 2509 * 3- 0: Tx buffer 1 address bits [32:32] 2510 * 2511 * Bit fields in val2: 2512 * 31-20: Tx buffer 2 length (bytes) 2513 * 19- 0: Tx buffer 2 address bits [35:16] 2514 */ 2515 struct iwk_tfd_frame_data { 2516 uint32_t tb1_addr; 2517 uint32_t val1; 2518 uint32_t val2; 2519 }; 2520 2521 typedef struct iwk_tx_desc { 2522 uint32_t val0; 2523 struct iwk_tfd_frame_data pa[10]; 2524 uint32_t reserved; 2525 } iwk_tx_desc_t; 2526 2527 typedef struct iwk_tx_stat { 2528 uint8_t frame_count; 2529 uint8_t bt_kill_count; 2530 uint8_t nrts; 2531 uint8_t ntries; 2532 struct iwk_rate rate; 2533 uint16_t duration; 2534 uint16_t reserved; 2535 uint32_t pa_power1; 2536 uint32_t pa_power2; 2537 uint32_t status; 2538 } iwk_tx_stat_t; 2539 2540 struct iwk_cmd_header { 2541 uint8_t type; 2542 uint8_t flags; 2543 uint8_t idx; 2544 uint8_t qid; 2545 }; 2546 2547 typedef struct iwk_rx_desc { 2548 uint32_t len; 2549 struct iwk_cmd_header hdr; 2550 } iwk_rx_desc_t; 2551 2552 typedef struct iwk_rx_stat { 2553 uint8_t len; 2554 uint8_t id; 2555 uint8_t rssi; /* received signal strength */ 2556 uint8_t agc; /* access gain control */ 2557 uint16_t signal; 2558 uint16_t noise; 2559 } iwk_rx_stat_t; 2560 2561 typedef struct iwk_rx_head { 2562 uint16_t chan; 2563 uint16_t flags; 2564 uint8_t reserved; 2565 uint8_t rate; 2566 uint16_t len; 2567 } iwk_rx_head_t; 2568 2569 typedef struct iwk_rx_tail { 2570 uint32_t flags; 2571 uint32_t timestampl; 2572 uint32_t timestamph; 2573 uint32_t tbeacon; 2574 } iwk_rx_tail_t; 2575 2576 enum { 2577 IWK_AP_ID = 0, 2578 IWK_MULTICAST_ID, 2579 IWK_STA_ID, 2580 IWK_BROADCAST_ID = 31, 2581 IWK_STATION_COUNT = 32, 2582 IWK_INVALID_STATION 2583 }; 2584 2585 /* 2586 * key flags 2587 */ 2588 enum { 2589 STA_KEY_FLG_ENCRYPT_MSK = 0x7, 2590 STA_KEY_FLG_NO_ENC = 0x0, 2591 STA_KEY_FLG_WEP = 0x1, 2592 STA_KEY_FLG_CCMP = 0x2, 2593 STA_KEY_FLG_TKIP = 0x3, 2594 2595 STA_KEY_FLG_KEYID_POS = 8, 2596 STA_KEY_FLG_INVALID = 0x0800, 2597 }; 2598 2599 /* 2600 * modify flags 2601 */ 2602 enum { 2603 STA_MODIFY_KEY_MASK = 0x01, 2604 STA_MODIFY_TID_DISABLE_TX = 0x02, 2605 STA_MODIFY_TX_RATE_MSK = 0x04 2606 }; 2607 2608 enum { 2609 RX_RES_STATUS_NO_CRC32_ERROR = (1 << 0), 2610 RX_RES_STATUS_NO_RXE_OVERFLOW = (1 << 1), 2611 }; 2612 2613 enum { 2614 RX_RES_PHY_FLAGS_BAND_24_MSK = (1 << 0), 2615 RX_RES_PHY_FLAGS_MOD_CCK_MSK = (1 << 1), 2616 RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK = (1 << 2), 2617 RX_RES_PHY_FLAGS_NARROW_BAND_MSK = (1 << 3), 2618 RX_RES_PHY_FLAGS_ANTENNA_MSK = 0xf0, 2619 2620 RX_RES_STATUS_SEC_TYPE_MSK = (0x7 << 8), 2621 RX_RES_STATUS_SEC_TYPE_NONE = (STA_KEY_FLG_NO_ENC << 8), 2622 RX_RES_STATUS_SEC_TYPE_WEP = (STA_KEY_FLG_WEP << 8), 2623 RX_RES_STATUS_SEC_TYPE_TKIP = (STA_KEY_FLG_TKIP << 8), 2624 RX_RES_STATUS_SEC_TYPE_CCMP = (STA_KEY_FLG_CCMP << 8), 2625 2626 RX_RES_STATUS_DECRYPT_TYPE_MSK = (0x3 << 11), 2627 RX_RES_STATUS_NOT_DECRYPT = (0x0 << 11), 2628 RX_RES_STATUS_DECRYPT_OK = (0x3 << 11), 2629 RX_RES_STATUS_BAD_ICV_MIC = (0x1 << 11), 2630 RX_RES_STATUS_BAD_KEY_TTAK = (0x2 << 11), 2631 }; 2632 2633 enum { 2634 REPLY_ALIVE = 0x1, 2635 REPLY_ERROR = 0x2, 2636 2637 /* RXON state commands */ 2638 REPLY_RXON = 0x10, 2639 REPLY_RXON_ASSOC = 0x11, 2640 REPLY_QOS_PARAM = 0x13, 2641 REPLY_RXON_TIMING = 0x14, 2642 2643 /* Multi-Station support */ 2644 REPLY_ADD_STA = 0x18, 2645 2646 /* RX, TX */ 2647 2648 REPLY_TX = 0x1c, 2649 2650 /* timers commands */ 2651 REPLY_BCON = 0x27, 2652 2653 REPLY_SHUTDOWN = 0x40, 2654 2655 /* MISC commands */ 2656 REPLY_RATE_SCALE = 0x47, 2657 REPLY_LEDS_CMD = 0x48, 2658 REPLY_TX_LINK_QUALITY_CMD = 0x4e, 2659 2660 /* 802.11h related */ 2661 RADAR_NOTIFICATION = 0x70, 2662 REPLY_QUIET_CMD = 0x71, 2663 REPLY_CHANNEL_SWITCH = 0x72, 2664 CHANNEL_SWITCH_NOTIFICATION = 0x73, 2665 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74, 2666 SPECTRUM_MEASURE_NOTIFICATION = 0x75, 2667 2668 /* Power Management *** */ 2669 POWER_TABLE_CMD = 0x77, 2670 PM_SLEEP_NOTIFICATION = 0x7A, 2671 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B, 2672 2673 /* Scan commands and notifications */ 2674 REPLY_SCAN_CMD = 0x80, 2675 REPLY_SCAN_ABORT_CMD = 0x81, 2676 2677 SCAN_START_NOTIFICATION = 0x82, 2678 SCAN_RESULTS_NOTIFICATION = 0x83, 2679 SCAN_COMPLETE_NOTIFICATION = 0x84, 2680 2681 /* IBSS/AP commands */ 2682 BEACON_NOTIFICATION = 0x90, 2683 REPLY_TX_BEACON = 0x91, 2684 WHO_IS_AWAKE_NOTIFICATION = 0x94, 2685 2686 QUIET_NOTIFICATION = 0x96, 2687 REPLY_TX_PWR_TABLE_CMD = 0x97, 2688 MEASURE_ABORT_NOTIFICATION = 0x99, 2689 2690 REPLY_CALIBRATION_TUNE = 0x9a, 2691 2692 /* BT config command */ 2693 REPLY_BT_CONFIG = 0x9b, 2694 REPLY_STATISTICS_CMD = 0x9c, 2695 STATISTICS_NOTIFICATION = 0x9d, 2696 2697 /* RF-KILL commands and notifications *** */ 2698 REPLY_CARD_STATE_CMD = 0xa0, 2699 CARD_STATE_NOTIFICATION = 0xa1, 2700 2701 /* Missed beacons notification */ 2702 MISSED_BEACONS_NOTIFICATION = 0xa2, 2703 MISSED_BEACONS_NOTIFICATION_TH_CMD = 0xa3, 2704 2705 REPLY_CT_KILL_CONFIG_CMD = 0xa4, 2706 SENSITIVITY_CMD = 0xa8, 2707 REPLY_PHY_CALIBRATION_CMD = 0xb0, 2708 REPLY_4965_RX = 0xc3, 2709 REPLY_RX_PHY_CMD = 0xc0, 2710 REPLY_RX_MPDU_CMD = 0xc1, 2711 REPLY_COMPRESSED_BA = 0xc5, 2712 REPLY_MAX = 0xff 2713 }; 2714 2715 typedef struct iwk_cmd { 2716 struct iwk_cmd_header hdr; 2717 uint8_t data[1024]; 2718 } iwk_cmd_t; 2719 2720 /* 2721 * Alive Command & Response 2722 */ 2723 #define UCODE_VALID_OK (0x1) 2724 #define INITIALIZE_SUBTYPE (9) 2725 2726 struct iwk_alive_resp { 2727 uint8_t ucode_minor; 2728 uint8_t ucode_major; 2729 uint16_t reserved1; 2730 uint8_t sw_rev[8]; 2731 uint8_t ver_type; 2732 uint8_t ver_subtype; 2733 uint16_t reserved2; 2734 uint32_t log_event_table_ptr; 2735 uint32_t error_event_table_ptr; 2736 uint32_t timestamp; 2737 uint32_t is_valid; 2738 }; 2739 2740 struct iwk_init_alive_resp { 2741 struct iwk_alive_resp s; 2742 /* calibration values from "initialize" uCode */ 2743 uint32_t voltage; /* signed */ 2744 uint32_t therm_r1[2]; /* signed 1st for normal, 2nd for FAT channel */ 2745 uint32_t therm_r2[2]; /* signed */ 2746 uint32_t therm_r3[2]; /* signed */ 2747 uint32_t therm_r4[2]; /* signed */ 2748 /* 2749 * signed MIMO gain comp, 5 freq groups, 2 Tx chains 2750 */ 2751 uint32_t tx_atten[5][2]; 2752 }; 2753 2754 /* 2755 * Rx config defines & structure 2756 */ 2757 /* 2758 * rx_config device types 2759 */ 2760 enum { 2761 RXON_DEV_TYPE_AP = 1, 2762 RXON_DEV_TYPE_ESS = 3, 2763 RXON_DEV_TYPE_IBSS = 4, 2764 RXON_DEV_TYPE_SNIFFER = 6, 2765 }; 2766 2767 /* 2768 * rx_config flags 2769 */ 2770 enum { 2771 /* band & modulation selection */ 2772 RXON_FLG_BAND_24G_MSK = (1 << 0), 2773 RXON_FLG_CCK_MSK = (1 << 1), 2774 /* auto detection enable */ 2775 RXON_FLG_AUTO_DETECT_MSK = (1 << 2), 2776 /* TGg protection when tx */ 2777 RXON_FLG_TGG_PROTECT_MSK = (1 << 3), 2778 /* cck short slot & preamble */ 2779 RXON_FLG_SHORT_SLOT_MSK = (1 << 4), 2780 RXON_FLG_SHORT_PREAMBLE_MSK = (1 << 5), 2781 /* antenna selection */ 2782 RXON_FLG_DIS_DIV_MSK = (1 << 7), 2783 RXON_FLG_ANT_SEL_MSK = 0x0f00, 2784 RXON_FLG_ANT_A_MSK = (1 << 8), 2785 RXON_FLG_ANT_B_MSK = (1 << 9), 2786 /* radar detection enable */ 2787 RXON_FLG_RADAR_DETECT_MSK = (1 << 12), 2788 RXON_FLG_TGJ_NARROW_BAND_MSK = (1 << 13), 2789 /* 2790 * rx response to host with 8-byte TSF 2791 * (according to ON_AIR deassertion) 2792 */ 2793 RXON_FLG_TSF2HOST_MSK = (1 << 15) 2794 }; 2795 2796 /* 2797 * rx_config filter flags 2798 */ 2799 enum { 2800 /* accept all data frames */ 2801 RXON_FILTER_PROMISC_MSK = (1 << 0), 2802 /* pass control & management to host */ 2803 RXON_FILTER_CTL2HOST_MSK = (1 << 1), 2804 /* accept multi-cast */ 2805 RXON_FILTER_ACCEPT_GRP_MSK = (1 << 2), 2806 /* don't decrypt uni-cast frames */ 2807 RXON_FILTER_DIS_DECRYPT_MSK = (1 << 3), 2808 /* don't decrypt multi-cast frames */ 2809 RXON_FILTER_DIS_GRP_DECRYPT_MSK = (1 << 4), 2810 /* STA is associated */ 2811 RXON_FILTER_ASSOC_MSK = (1 << 5), 2812 /* transfer to host non bssid beacons in associated state */ 2813 RXON_FILTER_BCON_AWARE_MSK = (1 << 6) 2814 }; 2815 2816 2817 /* 2818 * structure for RXON Command & Response 2819 */ 2820 typedef struct iwk_rxon_cmd { 2821 uint8_t node_addr[IEEE80211_ADDR_LEN]; 2822 uint16_t reserved1; 2823 uint8_t bssid[IEEE80211_ADDR_LEN]; 2824 uint16_t reserved2; 2825 uint8_t wlap_bssid[IEEE80211_ADDR_LEN]; 2826 uint16_t reserved3; 2827 uint8_t dev_type; 2828 uint8_t air_propagation; 2829 uint16_t rx_chain; 2830 uint8_t ofdm_basic_rates; 2831 uint8_t cck_basic_rates; 2832 uint16_t assoc_id; 2833 uint32_t flags; 2834 uint32_t filter_flags; 2835 uint16_t chan; 2836 uint8_t ofdm_ht_single_stream_basic_rates; 2837 uint8_t ofdm_ht_dual_stream_basic_rates; 2838 } iwk_rxon_cmd_t; 2839 2840 typedef struct iwk_compressed_ba_resp { 2841 uint32_t sta_addr_lo32; 2842 uint16_t sta_addr_hi16; 2843 uint16_t reserved; 2844 uint8_t sta_id; 2845 uint8_t tid; 2846 uint16_t ba_seq_ctl; 2847 uint32_t ba_bitmap0; 2848 uint32_t ba_bitmap1; 2849 uint16_t scd_flow; 2850 uint16_t scd_ssn; 2851 } iwk_compressed_ba_resp_t; 2852 2853 #define PHY_CALIBRATE_DIFF_GAIN_CMD (7) 2854 #define HD_TABLE_SIZE (11) 2855 2856 /* 2857 * Param table within SENSITIVITY_CMD 2858 */ 2859 #define HD_MIN_ENERGY_CCK_DET_INDEX (0) 2860 #define HD_MIN_ENERGY_OFDM_DET_INDEX (1) 2861 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2) 2862 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3) 2863 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4) 2864 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5) 2865 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6) 2866 #define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7) 2867 #define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8) 2868 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9) 2869 #define HD_OFDM_ENERGY_TH_IN_INDEX (10) 2870 2871 typedef struct iwk_sensitivity_cmd { 2872 uint16_t control; 2873 uint16_t table[HD_TABLE_SIZE]; 2874 } iwk_sensitivity_cmd_t; 2875 2876 typedef struct iwk_calibration_cmd { 2877 uint8_t opCode; 2878 uint8_t flags; 2879 uint16_t reserved; 2880 char *diff_gain_a; 2881 char *diff_gain_b; 2882 char *diff_gain_c; 2883 uint8_t reserved1; 2884 } iwk_calibation_cmd_t; 2885 2886 typedef struct iwk_missed_beacon_notif { 2887 uint32_t consequtive_missed_beacons; 2888 uint32_t total_missed_becons; 2889 uint32_t num_expected_beacons; 2890 uint32_t num_recvd_beacons; 2891 } iwk_missed_beacon_notif_t; 2892 2893 typedef struct iwk_ct_kill_config { 2894 uint32_t reserved; 2895 uint32_t critical_temperature_M; 2896 uint32_t critical_temperature_R; 2897 } iwk_ct_kill_config_t; 2898 2899 /* 2900 * structure for command IWK_CMD_ASSOCIATE 2901 */ 2902 typedef struct iwk_assoc { 2903 uint32_t flags; 2904 uint32_t filter; 2905 uint8_t ofdm_mask; 2906 uint8_t cck_mask; 2907 uint8_t ofdm_ht_single_stream_basic_rates; 2908 uint8_t ofdm_ht_dual_stream_basic_rates; 2909 uint16_t rx_chain_select_flags; 2910 uint16_t reserved; 2911 } iwk_assoc_t; 2912 2913 /* 2914 * structure for command IWK_CMD_SET_WME 2915 */ 2916 typedef struct iwk_wme_setup { 2917 uint32_t flags; 2918 struct { 2919 uint16_t cwmin; 2920 uint16_t cwmax; 2921 uint8_t aifsn; 2922 uint8_t reserved; 2923 uint16_t txop; 2924 } ac[WME_NUM_AC]; 2925 } iwk_wme_setup_t; 2926 2927 /* 2928 * structure for command IWK_CMD_TSF 2929 */ 2930 typedef struct iwk_cmd_tsf { 2931 uint32_t timestampl; 2932 uint32_t timestamph; 2933 uint16_t bintval; 2934 uint16_t atim; 2935 uint32_t binitval; 2936 uint16_t lintval; 2937 uint16_t reserved; 2938 } iwk_cmd_tsf_t; 2939 2940 /* 2941 * structure for IWK_CMD_ADD_NODE 2942 */ 2943 typedef struct iwk_add_sta { 2944 uint8_t control; 2945 uint8_t reserved1[3]; 2946 uint8_t bssid[IEEE80211_ADDR_LEN]; 2947 uint16_t reserved2; 2948 uint8_t id; 2949 uint8_t sta_mask; 2950 uint16_t reserved3; 2951 uint16_t key_flags; 2952 uint8_t tkip; 2953 uint8_t reserved4; 2954 uint16_t ttak[5]; 2955 uint8_t keyp; 2956 uint8_t reserved5; 2957 uint8_t key[16]; 2958 uint32_t flags; 2959 uint32_t mask; 2960 uint16_t tid; 2961 union { 2962 struct { 2963 uint8_t rate; 2964 uint8_t flags; 2965 } s; 2966 uint16_t rate_n_flags; 2967 } tx_rate; 2968 uint8_t add_imm; 2969 uint8_t del_imm; 2970 uint16_t add_imm_start; 2971 uint32_t reserved7; 2972 } iwk_add_sta_t; 2973 2974 /* 2975 * Tx flags 2976 */ 2977 enum { 2978 TX_CMD_FLG_RTS_MSK = (1 << 1), 2979 TX_CMD_FLG_CTS_MSK = (1 << 2), 2980 TX_CMD_FLG_ACK_MSK = (1 << 3), 2981 TX_CMD_FLG_STA_RATE_MSK = (1 << 4), 2982 TX_CMD_FLG_IMM_BA_RSP_MASK = (1 << 6), 2983 TX_CMD_FLG_FULL_TXOP_PROT_MSK = (1 << 7), 2984 TX_CMD_FLG_ANT_SEL_MSK = 0xf00, 2985 TX_CMD_FLG_ANT_A_MSK = (1 << 8), 2986 TX_CMD_FLG_ANT_B_MSK = (1 << 9), 2987 2988 /* ucode ignores BT priority for this frame */ 2989 TX_CMD_FLG_BT_DIS_MSK = (1 << 12), 2990 2991 /* ucode overrides sequence control */ 2992 TX_CMD_FLG_SEQ_CTL_MSK = (1 << 13), 2993 2994 /* signal that this frame is non-last MPDU */ 2995 TX_CMD_FLG_MORE_FRAG_MSK = (1 << 14), 2996 2997 /* calculate TSF in outgoing frame */ 2998 TX_CMD_FLG_TSF_MSK = (1 << 16), 2999 3000 /* activate TX calibration. */ 3001 TX_CMD_FLG_CALIB_MSK = (1 << 17), 3002 3003 /* 3004 * signals that 2 bytes pad was inserted 3005 * after the MAC header 3006 */ 3007 TX_CMD_FLG_MH_PAD_MSK = (1 << 20), 3008 3009 /* HCCA-AP - disable duration overwriting. */ 3010 TX_CMD_FLG_DUR_MSK = (1 << 25), 3011 }; 3012 3013 /* 3014 * TX command security control 3015 */ 3016 #define TX_CMD_SEC_CCM 0x2 3017 #define TX_CMD_SEC_TKIP 0x3 3018 3019 /* 3020 * structure for command IWK_CMD_TX_DATA 3021 */ 3022 typedef struct iwk_tx_cmd { 3023 uint16_t len; 3024 uint16_t next_frame_len; 3025 uint32_t tx_flags; 3026 struct iwk_dram_scratch scratch; 3027 struct iwk_rate rate; 3028 uint8_t sta_id; 3029 uint8_t sec_ctl; 3030 uint8_t initial_rate_index; 3031 uint8_t reserved; 3032 uint8_t key[16]; 3033 uint16_t next_frame_flags; 3034 uint16_t reserved2; 3035 union { 3036 uint32_t life_time; 3037 uint32_t attempt; 3038 } stop_time; 3039 uint32_t dram_lsb_ptr; 3040 uint8_t dram_msb_ptr; 3041 uint8_t rts_retry_limit; 3042 uint8_t data_retry_limit; 3043 uint8_t tid_tspec; 3044 union { 3045 uint16_t pm_frame_timeout; 3046 uint16_t attempt_duration; 3047 } timeout; 3048 uint16_t driver_txop; 3049 } iwk_tx_cmd_t; 3050 3051 /* 3052 * LEDs Command & Response 3053 * REPLY_LEDS_CMD = 0x48 (command, has simple generic response) 3054 * 3055 * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field), 3056 * this command turns it on or off, or sets up a periodic blinking cycle. 3057 */ 3058 typedef struct iwk_led_cmd { 3059 uint32_t interval; /* "interval" in uSec */ 3060 uint8_t id; /* 1: Activity, 2: Link, 3: Tech */ 3061 /* 3062 * # intervals off while blinking; 3063 * "0", with > 0 "on" value, turns LED on 3064 */ 3065 uint8_t off; 3066 /* 3067 * # intervals on while blinking; 3068 * "0", regardless of "off", turns LED off 3069 */ 3070 uint8_t on; 3071 uint8_t reserved; 3072 } iwk_led_cmd_t; 3073 3074 /* 3075 * structure for IWK_CMD_SET_POWER_MODE 3076 */ 3077 typedef struct iwk_powertable_cmd { 3078 uint16_t flags; 3079 uint8_t keep_alive_seconds; 3080 uint8_t debug_flags; 3081 uint32_t rx_timeout; 3082 uint32_t tx_timeout; 3083 uint32_t sleep[5]; 3084 uint32_t keep_alive_beacons; 3085 } iwk_powertable_cmd_t; 3086 3087 struct iwk_ssid_ie { 3088 uint8_t id; 3089 uint8_t len; 3090 uint8_t ssid[32]; 3091 }; 3092 /* 3093 * structure for command IWK_CMD_SCAN 3094 */ 3095 typedef struct iwk_scan_hdr { 3096 uint16_t len; 3097 uint8_t reserved1; 3098 uint8_t nchan; 3099 /* 3100 * dwell only this long on quiet chnl 3101 * (active scan) 3102 */ 3103 uint16_t quiet_time; 3104 uint16_t quiet_plcp_th; /* quiet chnl is < this # pkts (typ. 1) */ 3105 uint16_t good_crc_th; /* passive -> active promotion threshold */ 3106 uint16_t rx_chain; 3107 /* 3108 * max usec to be out of associated (service) 3109 * chnl 3110 */ 3111 uint32_t max_out_time; 3112 /* 3113 * pause scan this long when returning to svc 3114 * chnl. 3115 * 3945 -- 31:24 # beacons, 19:0 additional usec, 3116 * 4965 -- 31:22 # beacons, 21:0 additional usec. 3117 */ 3118 uint32_t suspend_time; 3119 uint32_t flags; 3120 uint32_t filter_flags; 3121 struct iwk_tx_cmd tx_cmd; 3122 struct iwk_ssid_ie direct_scan[4]; 3123 /* followed by probe request body */ 3124 /* followed by nchan x iwk_scan_chan */ 3125 } iwk_scan_hdr_t; 3126 3127 typedef struct iwk_scan_chan { 3128 uint8_t type; 3129 uint8_t chan; 3130 struct iwk_tx_power tpc; 3131 uint16_t active_dwell; /* dwell time */ 3132 uint16_t passive_dwell; /* dwell time */ 3133 } iwk_scan_chan_t; 3134 3135 /* 3136 * structure for IWK_CMD_BLUETOOTH 3137 */ 3138 typedef struct iwk_bt_cmd { 3139 uint8_t flags; 3140 uint8_t lead_time; 3141 uint8_t max_kill; 3142 uint8_t reserved; 3143 uint32_t kill_ack_mask; 3144 uint32_t kill_cts_mask; 3145 } iwk_bt_cmd_t; 3146 3147 /* 3148 * firmware image header 3149 */ 3150 typedef struct iwk_firmware_hdr { 3151 uint32_t version; 3152 uint32_t textsz; 3153 uint32_t datasz; 3154 uint32_t init_textsz; 3155 uint32_t init_datasz; 3156 uint32_t bootsz; 3157 } iwk_firmware_hdr_t; 3158 3159 /* 3160 * structure for IWK_START_SCAN notification 3161 */ 3162 typedef struct iwk_start_scan { 3163 uint32_t timestampl; 3164 uint32_t timestamph; 3165 uint32_t tbeacon; 3166 uint8_t chan; 3167 uint8_t band; 3168 uint16_t reserved; 3169 uint32_t status; 3170 } iwk_start_scan_t; 3171 3172 3173 #define IWK_READ(sc, reg) \ 3174 ddi_get32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg))) 3175 3176 #define IWK_WRITE(sc, reg, val) \ 3177 ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val)) 3178 3179 #ifdef __cplusplus 3180 } 3181 #endif 3182 3183 #endif /* _IWK_HW_H_ */ 3184