1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2007, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * For the avoidance of doubt, except that if any license choice other 13 * than GPL or LGPL is available it will apply instead, Sun elects to 14 * use only the General Public License version 2 (GPLv2) at this time 15 * for any software where a choice of GPL license versions is made 16 * available with the language indicating that GPLv2 or any later 17 * version may be used, or where a choice of which version of the GPL 18 * is applied is otherwise unspecified. 19 */ 20 21 /* 22 * This file is provided under a dual BSD/GPLv2 license. When using or 23 * redistributing this file, you may do so under either license. 24 * 25 * GPL LICENSE SUMMARY 26 * 27 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. 28 * 29 * This program is free software; you can redistribute it and/or modify 30 * it under the terms of version 2 of the GNU Geeral Public License as 31 * published by the Free Software Foundation. 32 * 33 * This program is distributed in the hope that it will be useful, but 34 * WITHOUT ANY WARRANTY; without even the implied warranty of 35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 36 * General Public License for more details. 37 * 38 * You should have received a copy of the GNU General Public License 39 * along with this program; if not, write to the Free Software 40 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 41 * USA 42 * 43 * The full GNU General Public License is included in this distribution 44 * in the file called LICENSE.GPL. 45 * 46 * Contact Information: 47 * James P. Ketrenos <ipw2100-admin@linux.intel.com> 48 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 49 * 50 * BSD LICENSE 51 * 52 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. 53 * All rights reserved. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 59 * * Redistributions of source code must retain the above copyright 60 * notice, this list of conditions and the following disclaimer. 61 * * Redistributions in binary form must reproduce the above copyright 62 * notice, this list of conditions and the following disclaimer in 63 * the documentation and/or other materials provided with the 64 * distribution. 65 * * Neither the name Intel Corporation nor the names of its 66 * contributors may be used to endorse or promote products derived 67 * from this software without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 70 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 71 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 72 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 73 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 74 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 75 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 76 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 77 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 79 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 80 */ 81 82 #ifndef _IWK_HW_H_ 83 #define _IWK_HW_H_ 84 85 #pragma ident "%Z%%M% %I% %E% SMI" 86 87 #ifdef __cplusplus 88 extern "C" { 89 #endif 90 91 /* 92 * maximum scatter/gather 93 */ 94 #define IWK_MAX_SCATTER (10) 95 96 /* 97 * Flow Handler Definitions 98 */ 99 #define FH_MEM_LOWER_BOUND (0x1000) 100 #define FH_MEM_UPPER_BOUND (0x1EF0) 101 102 #define IWK_FH_REGS_LOWER_BOUND (0x1000) 103 #define IWK_FH_REGS_UPPER_BOUND (0x2000) 104 105 /* 106 * TFDB Area - TFDs buffer table 107 */ 108 #define FH_MEM_TFDB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x000) 109 #define FH_MEM_TFDB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 110 111 /* 112 * channels 0 - 8 113 */ 114 #define FH_MEM_TFDB_CHNL_BUF0(x) (FH_MEM_TFDB_LOWER_BOUND + (x) * 0x100) 115 #define FH_MEM_TFDB_CHNL_BUF1(x) (FH_MEM_TFDB_LOWER_BOUND + 0x80 + (x) * 0x100) 116 117 /* 118 * TFDIB Area - TFD Immediate Buffer 119 */ 120 #define FH_MEM_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 121 #define FH_MEM_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) 122 123 /* 124 * channels 0 - 10 125 */ 126 #define FH_MEM_TFDIB_CHNL(x) (FH_MEM_TFDIB_LOWER_BOUND + (x) * 0x8) 127 128 /* 129 * TFDIB registers used in Service Mode 130 */ 131 #define FH_MEM_TFDIB_CHNL9_REG0 (FH_MEM_TFDIB_CHNL(9)) 132 #define FH_MEM_TFDIB_CHNL9_REG1 (FH_MEM_TFDIB_CHNL(9) + 4) 133 #define FH_MEM_TFDIB_CHNL10_REG0 (FH_MEM_TFDIB_CHNL(10)) 134 #define FH_MEM_TFDIB_CHNL10_REG1 (FH_MEM_TFDIB_CHNL(10) + 4) 135 136 /* 137 * Tx service channels 138 */ 139 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MASK (0xFFFFFFFF) 140 #define FH_MEM_TFDIB_DRAM_ADDR_MSB_MASK (0xF00000000) 141 #define FH_MEM_TFDIB_TB_LENGTH_MASK (0x0001FFFF) /* bits 16:0 */ 142 143 #define FH_MEM_TFDIB_DRAM_ADDR_LSB_BITSHIFT (0) 144 #define FH_MEM_TFDIB_DRAM_ADDR_MSB_BITSHIFT (32) 145 #define FH_MEM_TFDIB_TB_LENGTH_BITSHIFT (0) 146 147 #define FH_MEM_TFDIB_REG0_ADDR_MASK (0xFFFFFFFF) 148 #define FH_MEM_TFDIB_REG1_ADDR_MASK (0xF0000000) 149 #define FH_MEM_TFDIB_REG1_LENGTH_MASK (0x0001FFFF) 150 151 #define FH_MEM_TFDIB_REG0_ADDR_BITSHIFT (0) 152 #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT (28) 153 #define FH_MEM_TFDIB_REG1_LENGTH_BITSHIFT (0) 154 155 /* 156 * TRB Area - Transmit Request Buffers 157 */ 158 #define FH_MEM_TRB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x0958) 159 #define FH_MEM_TRB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x0980) 160 161 /* 162 * channels 0 - 8 163 */ 164 #define FH_MEM_TRB_CHNL(x) (FH_MEM_TRB_LOWER_BOUND + (x) * 0x4) 165 166 /* 167 * Keep-Warm (KW) buffer base address. 168 * 169 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the 170 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 171 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host 172 * from going into a power-savings mode that would cause higher DRAM latency, 173 * and possible data over/under-runs, before all Tx/Rx is complete. 174 * 175 * Driver loads IWK_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 176 * of the buffer, which must be 4K aligned. Once this is set up, the 4965 177 * automatically invokes keep-warm accesses when normal accesses might not 178 * be sufficient to maintain fast DRAM response. 179 * 180 * Bit fields: 181 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 182 */ 183 #define IWK_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) 184 185 /* 186 * STAGB Area - Scheduler TAG Buffer 187 */ 188 #define FH_MEM_STAGB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x980) 189 #define FH_MEM_STAGB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 190 191 /* 192 * channels 0 - 8 193 */ 194 #define FH_MEM_STAGB_0(x) (FH_MEM_STAGB_LOWER_BOUND + (x) * 0x8) 195 #define FH_MEM_STAGB_1(x) (FH_MEM_STAGB_LOWER_BOUND + 0x4 + (x) * 0x8) 196 197 /* 198 * Tx service channels 199 */ 200 #define FH_MEM_SRAM_ADDR_9 (FH_MEM_STAGB_LOWER_BOUND + 0x048) 201 #define FH_MEM_SRAM_ADDR_10 (FH_MEM_STAGB_LOWER_BOUND + 0x04C) 202 203 #define FH_MEM_STAGB_SRAM_ADDR_MASK (0x00FFFFFF) 204 205 /* 206 * TFD Circular Buffers Base (CBBC) addresses 207 * 208 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident 209 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 210 * (see struct iwk_tfd_frame). These 16 pointer registers are offset by 0x04 211 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 212 * aligned (address bits 0-7 must be 0). 213 * 214 * Bit fields in each pointer register: 215 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 216 */ 217 #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 218 #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 219 220 /* 221 * queues 0 - 15 222 */ 223 #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4) 224 225 /* 226 * TAGR Area - TAG reconstruct table 227 */ 228 #define FH_MEM_TAGR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 229 #define FH_MEM_TAGR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA70) 230 231 /* 232 * TDBGR Area - Tx Debug Registers 233 */ 234 #define FH_MEM_TDBGR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x0A70) 235 #define FH_MEM_TDBGR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x0B20) 236 237 /* 238 * channels 0 - 10 239 */ 240 #define FH_MEM_TDBGR_CHNL(x) (FH_MEM_TDBGR_LOWER_BOUND + (x) * 0x10) 241 242 #define FH_MEM_TDBGR_CHNL_REG_0(x) (FH_MEM_TDBGR_CHNL(x)) 243 #define FH_MEM_TDBGR_CHNL_REG_1(x) (FH_MEM_TDBGR_CHNL_REG_0(x) + 0x4) 244 245 #define FH_MEM_TDBGR_CHNL_BYTES_TO_FIFO_MASK (0x000FFFFF) 246 #define FH_MEM_TDBGR_CHNL_BYTES_TO_FIFO_BITSHIFT (0) 247 248 /* 249 * RDBUF Area 250 */ 251 #define FH_MEM_RDBUF_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) 252 #define FH_MEM_RDBUF_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 253 #define FH_MEM_RDBUF_CHNL0 (FH_MEM_RDBUF_LOWER_BOUND) 254 255 /* 256 * Rx SRAM Control and Status Registers (RSCSR) 257 * 258 * These registers provide handshake between driver and 4965 for the Rx queue 259 * (this queue handles *all* command responses, notifications, Rx data, etc. 260 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx 261 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 262 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 263 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 264 * mapping between RBDs and RBs. 265 * 266 * Driver must allocate host DRAM memory for the following, and set the 267 * physical address of each into 4965 registers: 268 * 269 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 270 * entries (although any power of 2, up to 4096, is selectable by driver). 271 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 272 * (typically 4K, although 8K or 16K are also selectable by driver). 273 * Driver sets up RB size and number of RBDs in the CB via Rx config 274 * register FH_MEM_RCSR_CHNL0_CONFIG_REG. 275 * 276 * Bit fields within one RBD: 277 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned. 278 * 279 * Driver sets physical address [35:8] of base of RBD circular buffer 280 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 281 * 282 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers 283 * (RBs) have been filled, via a "write pointer", actually the index of 284 * the RB's corresponding RBD within the circular buffer. Driver sets 285 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 286 * 287 * Bit fields in lower dword of Rx status buffer (upper dword not used 288 * by driver; see struct iwk_shared, val0): 289 * 31-12: Not used by driver 290 * 11- 0: Index of last filled Rx buffer descriptor 291 * (4965 writes, driver reads this value) 292 * 293 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must 294 * enter pointers to these RBs into contiguous RBD circular buffer entries, 295 * and update the 4965's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 296 * 297 * This "write" index corresponds to the *next* RBD that the driver will make 298 * available, i.e. one RBD past the the tail of the ready-to-fill RBDs within 299 * the circular buffer. This value should initially be 0 (before preparing any 300 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 301 * wrap back to 0 at the end of the circular buffer (but don't wrap before 302 * "read" index has advanced past 1! See below). 303 * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 304 * 305 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular 306 * buffer), it updates the Rx status buffer in DRAM, 2) described above, 307 * to tell the driver the index of the latest filled RBD. The driver must 308 * read this "read" index from DRAM after receiving an Rx interrupt from 4965. 309 * 310 * The driver must also internally keep track of a third index, which is the 311 * next RBD to process. When receiving an Rx interrupt, driver should process 312 * all filled but unprocessed RBs up to, but not including, the RB 313 * corresponding to the "read" index. For example, if "read" index becomes "1", 314 * driver may process the RB pointed to by RBD 0. Depending on volume of 315 * traffic, there may be many RBs to process. 316 * 317 * If read index == write index, 4965 thinks there is no room to put new data. 318 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 319 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 320 * and "read" indexes; that is, make sure that there are no more than 254 321 * buffers waiting to be filled. 322 */ 323 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 324 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 325 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) 326 #define FH_MEM_RSCSR_CHNL1 (FH_MEM_RSCSR_LOWER_BOUND + 0x020) 327 328 /* 329 * Physical base address of 8-byte Rx Status buffer. 330 * Bit fields: 331 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 332 */ 333 334 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) 335 336 /* 337 * Physical base address of Rx Buffer Descriptor Circular Buffer. 338 * Bit fields: 339 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 340 */ 341 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) 342 343 /* 344 * Rx write pointer (index, really!). 345 * Bit fields: 346 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 347 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 348 */ 349 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) 350 #define FH_RSCSR_CHNL0_RBDCB_RPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) 351 352 #define FH_RSCSR_FRAME_SIZE_MASK (0x00000FFF) /* bits 0-11 */ 353 354 /* 355 * RSCSR registers used in Service mode 356 */ 357 #define FH_RSCSR_CHNL1_RB_WPTR_REG (FH_MEM_RSCSR_CHNL1) 358 #define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_REG (FH_MEM_RSCSR_CHNL1 + 0x004) 359 #define FH_RSCSR_CHNL1_RB_CHUNK_NUM_REG (FH_MEM_RSCSR_CHNL1 + 0x008) 360 #define FH_RSCSR_CHNL1_SRAM_ADDR_REG (FH_MEM_RSCSR_CHNL1 + 0x00C) 361 362 /* 363 * Rx Config/Status Registers (RCSR) 364 * Rx Config Reg for channel 0 (only channel used) 365 * 366 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 367 * normal operation (see bit fields). 368 * 369 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 370 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for 371 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 372 * 373 * Bit fields: 374 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 375 * '10' operate normally 376 * 29-24: reserved 377 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 378 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 379 * 19-18: reserved 380 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 381 * '10' 12K, '11' 16K. 382 * 15-14: reserved 383 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 384 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 385 * typical value 0x10 (about 1/2 msec) 386 * 3- 0: reserved 387 */ 388 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 389 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) 390 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) 391 #define FH_MEM_RCSR_CHNL1 (FH_MEM_RCSR_LOWER_BOUND + 0x020) 392 393 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) 394 #define FH_MEM_RCSR_CHNL0_CREDIT_REG (FH_MEM_RCSR_CHNL0 + 0x004) 395 #define FH_MEM_RCSR_CHNL0_RBD_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x008) 396 #define FH_MEM_RCSR_CHNL0_RB_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x00C) 397 #define FH_MEM_RCSR_CHNL0_RXPD_STTS_REG (FH_MEM_RCSR_CHNL0 + 0x010) 398 399 #define FH_MEM_RCSR_CHNL0_RBD_STTS_FRAME_RB_CNT_MASK (0x7FFFFFF0) 400 401 /* 402 * RCSR registers used in Service mode 403 */ 404 #define FH_MEM_RCSR_CHNL1_CONFIG_REG (FH_MEM_RCSR_CHNL1) 405 #define FH_MEM_RCSR_CHNL1_RB_STTS_REG (FH_MEM_RCSR_CHNL1 + 0x00C) 406 #define FH_MEM_RCSR_CHNL1_RX_PD_STTS_REG (FH_MEM_RCSR_CHNL1 + 0x010) 407 408 /* 409 * Rx Shared Status Registers (RSSR) 410 * 411 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG), 412 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 413 * 414 * Bit fields: 415 * 24: 1 = Channel 0 is idle 416 * 417 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain 418 * default values that should not be altered by the driver. 419 */ 420 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) 421 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 422 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) 423 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) 424 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008) 425 426 /* 427 * Transmit DMA Channel Control/Status Registers (TCSR) 428 * 429 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels 430 * supported in hardware; config regs are separated by 0x20 bytes. 431 * 432 * To use a Tx DMA channel, driver must initialize its 433 * IWK_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 434 * 435 * IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 436 * IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 437 * 438 * All other bits should be 0. 439 * 440 * Bit fields: 441 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 442 * '10' operate normally 443 * 29- 4: Reserved, set to "0" 444 * 3: Enable internal DMA requests (1, normal operation), disable (0) 445 * 2- 0: Reserved, set to "0" 446 */ 447 #define IWK_FH_TCSR_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xD00) 448 #define IWK_FH_TCSR_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xE60) 449 450 #define IWK_FH_TCSR_CHNL_NUM (7) 451 #define IWK_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 452 (IWK_FH_TCSR_LOWER_BOUND + 0x20 * _chnl) 453 #define IWK_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 454 (IWK_FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x4) 455 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 456 (IWK_FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x8) 457 458 /* 459 * Tx Shared Status Registers (TSSR) 460 * 461 * After stopping Tx DMA channel (writing 0 to 462 * IWK_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 463 * IWK_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 464 * (channel's buffers empty | no pending requests). 465 * 466 * Bit fields: 467 * 31-24: 1 = Channel buffers empty (channel 7:0) 468 * 23-16: 1 = No pending requests (channel 7:0) 469 */ 470 #define IWK_FH_TSSR_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xEA0) 471 #define IWK_FH_TSSR_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0xEC0) 472 473 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG (IWK_FH_TSSR_LOWER_BOUND + 0x008) 474 #define IWK_FH_TSSR_TX_STATUS_REG (IWK_FH_TSSR_LOWER_BOUND + 0x010) 475 476 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) 477 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) 478 479 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_64B (0x00000000) 480 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) 481 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_256B (0x00000800) 482 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_512B (0x00000C00) 483 484 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) 485 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) 486 487 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) 488 #define IWK_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) 489 490 #define IWK_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \ 491 ((1 << (_chnl)) << 24) 492 #define IWK_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \ 493 ((1 << (_chnl)) << 16) 494 495 #define IWK_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \ 496 (IWK_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \ 497 IWK_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl)) 498 499 /* 500 * SRVC 501 */ 502 #define IWK_FH_SRVC_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x9C8) 503 #define IWK_FH_SRVC_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x9D0) 504 505 #define IWK_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 506 (IWK_FH_SRVC_LOWER_BOUND + (_chnl - 9) * 0x4) 507 508 /* 509 * TFDIB 510 */ 511 #define IWK_FH_TFDIB_LOWER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x900) 512 #define IWK_FH_TFDIB_UPPER_BOUND (IWK_FH_REGS_LOWER_BOUND + 0x958) 513 514 #define IWK_FH_TFDIB_CTRL0_REG(_chnl) \ 515 (IWK_FH_TFDIB_LOWER_BOUND + 0x8 * _chnl) 516 #define IWK_FH_TFDIB_CTRL1_REG(_chnl) \ 517 (IWK_FH_TFDIB_LOWER_BOUND + 0x8 * _chnl + 0x4) 518 519 #define IWK_FH_SRVC_CHNL (9) 520 #define IWK_FH_TFDIB_CTRL1_REG_POS_MSB (28) 521 522 /* 523 * Debug Monitor Area 524 */ 525 #define FH_MEM_DM_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEE0) 526 #define FH_MEM_DM_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEF0) 527 #define FH_MEM_DM_CONTROL_MASK_REG (FH_MEM_DM_LOWER_BOUND) 528 #define FH_MEM_DM_CONTROL_START_REG (FH_MEM_DM_LOWER_BOUND + 0x004) 529 #define FH_MEM_DM_CONTROL_STATUS_REG (FH_MEM_DM_LOWER_BOUND + 0x008) 530 #define FH_MEM_DM_MONITOR_REG (FH_MEM_DM_LOWER_BOUND + 0x00C) 531 532 #define FH_TB1_ADDR_LOW_MASK (0xFFFFFFFF) /* bits 31:0 */ 533 #define FH_TB1_ADDR_HIGH_MASK (0xF00000000) /* bits 35:32 */ 534 #define FH_TB2_ADDR_LOW_MASK (0x0000FFFF) /* bits 15:0 */ 535 #define FH_TB2_ADDR_HIGH_MASK (0xFFFFF0000) /* bits 35:16 */ 536 537 #define FH_TB1_ADDR_LOW_BITSHIFT (0) 538 #define FH_TB1_ADDR_HIGH_BITSHIFT (32) 539 #define FH_TB2_ADDR_LOW_BITSHIFT (0) 540 #define FH_TB2_ADDR_HIGH_BITSHIFT (16) 541 542 #define FH_TB1_LENGTH_MASK (0x00000FFF) /* bits 11:0 */ 543 #define FH_TB2_LENGTH_MASK (0x00000FFF) /* bits 11:0 */ 544 545 /* 546 * number of FH channels including 2 service mode 547 */ 548 #define NUM_OF_FH_CHANNELS (10) 549 550 /* 551 * ctrl field bitology 552 */ 553 #define FH_TFD_CTRL_PADDING_MASK (0xC0000000) /* bits 31:30 */ 554 #define FH_TFD_CTRL_NUMTB_MASK (0x1F000000) /* bits 28:24 */ 555 556 #define FH_TFD_CTRL_PADDING_BITSHIFT (30) 557 #define FH_TFD_CTRL_NUMTB_BITSHIFT (24) 558 559 #define FH_TFD_GET_NUM_TBS(ctrl) \ 560 ((ctrl & FH_TFD_CTRL_NUMTB_MASK) >> FH_TFD_CTRL_NUMTB_BITSHIFT) 561 #define FH_TFD_GET_PADDING(ctrl) \ 562 ((ctrl & FH_TFD_CTRL_PADDING_MASK) >> FH_TFD_CTRL_PADDING_BITSHIFT) 563 564 /* TCSR: tx_config register values */ 565 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 566 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) 567 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_ARC (0x00000002) 568 569 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) 570 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) 571 572 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 573 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 574 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 575 576 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 577 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 578 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 579 580 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 581 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 582 #define IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 583 584 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 585 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 586 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 587 588 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) 589 590 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 591 #define IWK_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 592 593 /* 594 * CBB table 595 */ 596 #define FH_CBB_ADDR_MASK 0x0FFFFFFF /* bits 27:0 */ 597 #define FH_CBB_ADDR_BIT_SHIFT (8) 598 599 /* 600 * RCSR: channel 0 rx_config register defines 601 */ 602 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ 603 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */ 604 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */ 605 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */ 606 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */ 607 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */ 608 609 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20) 610 #define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16) 611 612 #define FH_RCSR_GET_RDBC_SIZE(reg) \ 613 ((reg & FH_RCSR_RX_CONFIG_RDBC_SIZE_MASK) >> \ 614 FH_RCSR_RX_CONFIG_RDBC_SIZE_BITSHIFT) 615 616 /* 617 * RCSR: channel 1 rx_config register defines 618 */ 619 #define FH_RCSR_CHNL1_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ 620 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_MASK (0x00003000) /* bits 12-13 */ 621 622 /* 623 * RCSR: rx_config register values 624 */ 625 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 626 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 627 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 628 #define FH_RCSR_RX_CONFIG_SINGLE_FRAME_MODE (0x00008000) 629 630 #define FH_RCSR_RX_CONFIG_RDRBD_DISABLE_VAL (0x00000000) 631 #define FH_RCSR_RX_CONFIG_RDRBD_ENABLE_VAL (0x20000000) 632 633 #define IWK_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 634 635 /* 636 * RCSR channel 0 config register values 637 */ 638 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 639 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 640 641 /* 642 * RCSR channel 1 config register values 643 */ 644 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 645 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 646 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_RTC_VAL (0x00002000) 647 #define FH_RCSR_CHNL1_RX_CONFIG_IRQ_DEST_INT_HOST_RTC_VAL (0x00003000) 648 649 /* 650 * RCSR: rb status register defines 651 */ 652 #define FH_RCSR_RB_BYTE_TO_SEND_MASK (0x0001FFFF) /* bits 0-16 */ 653 654 /* 655 * RSCSR: defs used in normal mode 656 */ 657 #define FH_RSCSR_CHNL0_RBDCB_WPTR_MASK (0x00000FFF) /* bits 0-11 */ 658 659 /* 660 * RSCSR: defs used in service mode 661 */ 662 #define FH_RSCSR_CHNL1_SRAM_ADDR_MASK (0x00FFFFFF) /* bits 0-23 */ 663 #define FH_RSCSR_CHNL1_RB_WPTR_MASK (0x0FFFFFFF) /* bits 0-27 */ 664 #define FH_RSCSR_CHNL1_RB_WPTR_OFFSET_MASK (0x000000FF) /* bits 0-7 */ 665 666 /* 667 * RSSR: RX Enable Error IRQ to Driver register defines 668 */ 669 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV_NO_RBD (0x00400000) /* bit 22 */ 670 671 #define FH_DRAM2SRAM_DRAM_ADDR_HIGH_MASK (0xFFFFFFF00) /* bits 8-35 */ 672 #define FH_DRAM2SRAM_DRAM_ADDR_LOW_MASK (0x000000FF) /* bits 0-7 */ 673 674 #define FH_DRAM2SRAM_DRAM_ADDR_HIGH_BITSHIFT (8) /* bits 8-35 */ 675 676 /* 677 * RX DRAM status regs definitions 678 */ 679 #define FH_RX_RB_NUM_MASK (0x00000FFF) /* bits 0-11 */ 680 #define FH_RX_FRAME_NUM_MASK (0x0FFF0000) /* bits 16-27 */ 681 682 #define FH_RX_RB_NUM_BITSHIFT (0) 683 #define FH_RX_FRAME_NUM_BITSHIFT (16) 684 685 /* 686 * Tx Scheduler 687 * 688 * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs 689 * (Transmit Frame Descriptors) from up to 16 circular queues resident in 690 * host DRAM. It steers each frame's Tx command (which contains the frame 691 * data) through one of up to 7 prioritized Tx DMA FIFO channels within the 692 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 693 * but one DMA channel may take input from several queues. 694 * 695 * Tx DMA channels have dedicated purposes. For 4965, and are used as follows: 696 * BMC TODO: CONFIRM channel assignments, esp for 0/1 697 * 698 * 0 -- EDCA BK (background) frames, lowest priority 699 * 1 -- EDCA BE (best effort) frames, normal priority 700 * 2 -- EDCA VI (video) frames, higher priority 701 * 3 -- EDCA VO (voice) and management frames, highest priority 702 * 4 -- Commands (e.g. RXON, etc.) 703 * 5 -- HCCA short frames 704 * 6 -- HCCA long frames 705 * 7 -- not used by driver (device-internal only) 706 * 707 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 708 * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to 709 * support 11n aggregation via EDCA DMA channels. BMC confirm. 710 * 711 * The driver sets up each queue to work in one of two modes: 712 * 713 * 1) Scheduler-Ack, in which the scheduler automatically supports a 714 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 715 * contains TFDs for a unique combination of Recipient Address (RA) 716 * and Traffic Identifier (TID), that is, traffic of a given 717 * Quality-Of-Service (QOS) priority, destined for a single station. 718 * 719 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 720 * each frame within the BA window, including whether it's been transmitted, 721 * and whether it's been acknowledged by the receiving station. The device 722 * automatically processes block-acks received from the receiving STA, 723 * and reschedules un-acked frames to be retransmitted (successful 724 * Tx completion may end up being out-of-order). 725 * 726 * The driver must maintain the queue's Byte Count table in host DRAM 727 * (struct iwk_sched_queue_byte_cnt_tbl) for this mode. 728 * This mode does not support fragmentation. 729 * 730 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 731 * The device may automatically retry Tx, but will retry only one frame 732 * at a time, until receiving ACK from receiving station, or reaching 733 * retry limit and giving up. 734 * 735 * The command queue (#4) must use this mode! 736 * This mode does not require use of the Byte Count table in host DRAM. 737 * 738 * Driver controls scheduler operation via 3 means: 739 * 1) Scheduler registers 740 * 2) Shared scheduler data base in internal 4956 SRAM 741 * 3) Shared data in host DRAM 742 * 743 * Initialization: 744 * 745 * When loading, driver should allocate memory for: 746 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 747 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 748 * (1024 bytes for each queue). 749 * 750 * After receiving "Alive" response from uCode, driver must initialize 751 * the following (especially for queue #4, the command queue, otherwise 752 * the driver can't issue commands!): 753 * 754 * 1) 4965's scheduler data base area in SRAM: 755 * a) Read SRAM address of data base area from SCD_SRAM_BASE_ADDR 756 * b) Clear and Init SCD_CONTEXT_DATA_OFFSET area (size 128 bytes) 757 * c) Clear SCD_TX_STTS_BITMAP_OFFSET area (size 256 bytes) 758 * d) Clear (BMC and init?) SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) 759 * 760 * 2) Init SCD_DRAM_BASE_ADDR with physical base of Tx byte count circular 761 * buffer array, allocated by driver in host DRAM. 762 * 763 * 3) 764 */ 765 766 /* 767 * Max Tx window size is the max number of contiguous TFDs that the scheduler 768 * can keep track of at one time when creating block-ack chains of frames. 769 * Note that "64" matches the number of ack bits in a block-ack. 770 * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize 771 * SCD_CONTEXT_QUEUE_OFFSET(x) values. 772 */ 773 #define SCD_WIN_SIZE 64 774 #define SCD_FRAME_LIMIT 10 775 776 /* 777 * Memory mapped registers ... access via HBUS_TARG_PRPH regs 778 */ 779 #define SCD_START_OFFSET 0xa02c00 780 781 /* 782 * 4965 tells driver SRAM address for internal scheduler structs via this reg. 783 * Value is valid only after "Alive" response from uCode. 784 */ 785 #define SCD_SRAM_BASE_ADDR (SCD_START_OFFSET + 0x0) 786 787 /* 788 * Driver may need to update queue-empty bits after changing queue's 789 * write and read pointers (indexes) during (re-)initialization (i.e. when 790 * scheduler is not tracking what's happening). 791 * Bit fields: 792 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit 793 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty 794 * NOTE BMC: THIS REGISTER NOT USED BY LINUX DRIVER. 795 */ 796 #define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4) 797 798 /* 799 * Physical base address of array of byte count (BC) circular buffers (CBs). 800 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode. 801 * This register points to BC CB for queue 0, must be on 1024-byte boundary. 802 * Others are spaced by 1024 bytes. 803 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. 804 * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff). 805 * Bit fields: 806 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned. 807 */ 808 #define SCD_DRAM_BASE_ADDR (SCD_START_OFFSET + 0x10) 809 #define SCD_AIT (SCD_START_OFFSET + 0x18) 810 811 /* 812 * Enables any/all Tx DMA/FIFO channels. 813 * Scheduler generates requests for only the active channels. 814 * Set this to 0xff to enable all 8 channels (normal usage). 815 * Bit fields: 816 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7 817 */ 818 #define SCD_TXFACT (SCD_START_OFFSET + 0x1c) 819 820 /* 821 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue. 822 * Initialized and updated by driver as new TFDs are added to queue. 823 * NOTE: If using Block Ack, index must correspond to frame's 824 * Start Sequence Number; index = (SSN & 0xff) 825 * NOTE BMC: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses? 826 */ 827 #define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4) 828 829 /* 830 * Queue (x) Read Pointers (indexes, really!), one for each Tx queue. 831 * For FIFO mode, index indicates next frame to transmit. 832 * For Scheduler-ACK mode, index indicates first frame in Tx window. 833 * Initialized by driver, updated by scheduler. 834 */ 835 #define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4) 836 #define SCD_SETQUEUENUM (SCD_START_OFFSET + 0xa4) 837 #define SCD_SET_TXSTAT_TXED (SCD_START_OFFSET + 0xa8) 838 #define SCD_SET_TXSTAT_DONE (SCD_START_OFFSET + 0xac) 839 #define SCD_SET_TXSTAT_NOT_SCHD (SCD_START_OFFSET + 0xb0) 840 #define SCD_DECREASE_CREDIT (SCD_START_OFFSET + 0xb4) 841 #define SCD_DECREASE_SCREDIT (SCD_START_OFFSET + 0xb8) 842 #define SCD_LOAD_CREDIT (SCD_START_OFFSET + 0xbc) 843 #define SCD_LOAD_SCREDIT (SCD_START_OFFSET + 0xc0) 844 #define SCD_BAR (SCD_START_OFFSET + 0xc4) 845 #define SCD_BAR_DW0 (SCD_START_OFFSET + 0xc8) 846 #define SCD_BAR_DW1 (SCD_START_OFFSET + 0xcc) 847 848 /* 849 * Select which queues work in chain mode (1) vs. not (0). 850 * Use chain mode to build chains of aggregated frames. 851 * Bit fields: 852 * 31-16: Reserved 853 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time 854 * NOTE: If driver sets up queue for chain mode, it should be also set up 855 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x). 856 */ 857 #define SCD_QUEUECHAIN_SEL (SCD_START_OFFSET + 0xd0) 858 #define SCD_QUERY_REQ (SCD_START_OFFSET + 0xd8) 859 #define SCD_QUERY_RES (SCD_START_OFFSET + 0xdc) 860 #define SCD_PENDING_FRAMES (SCD_START_OFFSET + 0xe0) 861 862 /* 863 * Select which queues interrupt driver when read pointer (index) increments. 864 * Bit fields: 865 * 31-16: Reserved 866 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled 867 * NOTE BMC: THIS FUNCTIONALITY IS APPARENTLY A NO-OP. 868 */ 869 #define SCD_INTERRUPT_MASK (SCD_START_OFFSET + 0xe4) 870 #define SCD_INTERRUPT_THRESHOLD (SCD_START_OFFSET + 0xe8) 871 #define SCD_QUERY_MIN_FRAME_SIZE (SCD_START_OFFSET + 0x100) 872 873 /* 874 * Queue search status registers. One for each queue. 875 * Sets up queue mode and assigns queue to Tx DMA channel. 876 * Bit fields: 877 * 19-10: Write mask/enable bits for bits 0-9 878 * 9: Driver should init to "0" 879 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0). 880 * Driver should init to "1" for aggregation mode, or "0" otherwise. 881 * 7-6: Driver should init to "0" 882 * 5: Window Size Left; indicates whether scheduler can request 883 * another TFD, based on window size, etc. Driver should init 884 * this bit to "1" for aggregation mode, or "0" for non-agg. 885 * 4-1: Tx FIFO to use (range 0-7). 886 * 0: Queue is active (1), not active (0). 887 * Other bits should be written as "0" 888 * 889 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled 890 * via SCD_QUEUECHAIN_SEL. 891 */ 892 #define SCD_QUEUE_STATUS_BITS(x) (SCD_START_OFFSET + 0x104 + (x) * 4) 893 894 /* 895 * 4965 internal SRAM structures for scheduler, shared with driver ... 896 * Driver should clear and initialize the following areas after receiving 897 * "Alive" response from 4965 uCode, i.e. after initial 898 * uCode load, or after a uCode load done for error recovery: 899 * 900 * SCD_CONTEXT_DATA_OFFSET (size 128 bytes) 901 * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes) 902 * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) 903 * 904 * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR. 905 * All OFFSET values must be added to this base address. 906 * Use HBUS_TARG_MEM_* registers to access SRAM. 907 */ 908 909 /* 910 * Queue context. One 8-byte entry for each of 16 queues. 911 * 912 * Driver should clear this entire area (size 0x80) to 0 after receiving 913 * "Alive" notification from uCode. Additionally, driver should init 914 * each queue's entry as follows: 915 * 916 * LS Dword bit fields: 917 * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64. 918 * 919 * MS Dword bit fields: 920 * 16-22: Frame limit. Driver should init to 10 (0xa). 921 * 922 * Driver should init all other bits to 0. 923 * 924 * Init must be done after driver receives "Alive" response from 4965 uCode, 925 * and when setting up queue for aggregation. 926 */ 927 #define SCD_CONTEXT_DATA_OFFSET 0x380 928 929 /* 930 * Tx Status Bitmap 931 * 932 * Driver should clear this entire area (size 0x100) to 0 after receiving 933 * "Alive" notification from uCode. Area is used only by device itself; 934 * no other support (besides clearing) is required from driver. 935 */ 936 #define SCD_TX_STTS_BITMAP_OFFSET 0x400 937 938 /* 939 * RAxTID to queue translation mapping. 940 * 941 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be 942 * for only one combination of receiver address (RA) and traffic ID (TID), i.e. 943 * one QOS priority level destined for one station (for this link, not final 944 * destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit mappings, 945 * one for each of the 16 queues. If queue is not in Scheduler-ACK mode, the 946 * device ignores the mapping value. 947 * 948 * Bit fields, for each 16-bit map: 949 * 15-9: Reserved, set to 0 950 * 8-4: Index into device's station table for recipient station 951 * 3-0: Traffic ID (tid), range 0-15 952 * 953 * Driver should clear this entire area (size 32 bytes) to 0 after receiving 954 * "Alive" notification from uCode. To update a 16-bit map value, driver 955 * must read a dword-aligned value from device SRAM, replace the 16-bit map 956 * value of interest, and write the dword value back into device SRAM. 957 */ 958 #define SCD_TRANSLATE_TBL_OFFSET 0x500 959 #define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) 960 #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ 961 ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) 962 963 /* 964 * Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". 965 */ 966 #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ 967 ((1<<(hi))|((1<<(hi))-(1<<(lo)))) 968 969 #define SCD_MODE_REG_BIT_SEARCH_MODE (1<<0) 970 #define SCD_MODE_REG_BIT_SBYP_MODE (1<<1) 971 972 #define SCD_TXFIFO_POS_TID (0) 973 #define SCD_TXFIFO_POS_RA (4) 974 #define SCD_QUEUE_STTS_REG_POS_ACTIVE (0) 975 #define SCD_QUEUE_STTS_REG_POS_TXF (1) 976 #define SCD_QUEUE_STTS_REG_POS_WSL (5) 977 #define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) 978 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) 979 #define SCD_QUEUE_STTS_REG_MSK (0x0007FC00) 980 981 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 982 983 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) 984 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) 985 #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 986 #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 987 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 988 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 989 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 990 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 991 992 #define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010) 993 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) 994 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 995 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 996 #define CSR_HW_IF_CONFIG_REG_EEP_SEM (0x00200000) 997 998 /* IWK-END */ 999 1000 #define RX_RES_PHY_CNT 14 1001 1002 #define STATISTICS_FLG_CLEAR (0x1) 1003 #define STATISTICS_FLG_DISABLE_NOTIFICATION (0x2) 1004 1005 #define STATISTICS_REPLY_FLG_CLEAR (0x1) 1006 #define STATISTICS_REPLY_FLG_BAND_24G_MSK (0x2) 1007 #define STATISTICS_REPLY_FLG_TGJ_NARROW_BAND_MSK (0x4) 1008 #define STATISTICS_REPLY_FLG_FAT_MODE_MSK (0x8) 1009 #define RX_PHY_FLAGS_ANTENNAE_OFFSET (4) 1010 #define RX_PHY_FLAGS_ANTENNAE_MASK (0x70) 1011 1012 /* 1013 * Register and values 1014 */ 1015 #define CSR_BASE (0x0) 1016 #define HBUS_BASE (0x400) 1017 1018 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) 1019 1020 /* 1021 * CSR (control and status registers) 1022 */ 1023 #define CSR_SW_VER (CSR_BASE+0x000) 1024 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ 1025 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ 1026 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ 1027 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ 1028 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */ 1029 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ 1030 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */ 1031 #define CSR_GP_CNTRL (CSR_BASE+0x024) 1032 /* 0x028 - reserved */ 1033 #define CSR_EEPROM_REG (CSR_BASE+0x02c) 1034 #define CSR_EEPROM_GP (CSR_BASE+0x030) 1035 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) 1036 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) 1037 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) 1038 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) 1039 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) 1040 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) 1041 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 1042 1043 /* 1044 * BSM (Bootstrap State Machine) 1045 */ 1046 #define BSM_BASE (CSR_BASE + 0x3400) 1047 1048 #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */ 1049 #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */ 1050 #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */ 1051 #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */ 1052 #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */ 1053 1054 /* 1055 * pointers and size regs for bootstrap load and data SRAM save 1056 */ 1057 #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090) 1058 #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094) 1059 #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098) 1060 #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C) 1061 1062 /* 1063 * BSM special memory, stays powered during power-save sleeps 1064 */ 1065 #define BSM_SRAM_LOWER_BOUND (CSR_BASE + 0x3800) 1066 #define BSM_SRAM_SIZE (1024) 1067 1068 1069 /* 1070 * card static random access memory (SRAM) for processor data and instructs 1071 */ 1072 #define RTC_INST_LOWER_BOUND (0x00000) 1073 #define ALM_RTC_INST_UPPER_BOUND (0x14000) 1074 1075 #define RTC_DATA_LOWER_BOUND (0x800000) 1076 #define ALM_RTC_DATA_UPPER_BOUND (0x808000) 1077 1078 /* 1079 * HBUS (Host-side bus) 1080 */ 1081 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) 1082 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) 1083 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) 1084 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) 1085 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) 1086 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) 1087 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) 1088 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) 1089 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) 1090 1091 /* 1092 * HW I/F configuration 1093 */ 1094 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100) 1095 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200) 1096 #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) 1097 #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) 1098 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) 1099 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) 1100 1101 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 1102 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 1103 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 1104 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 1105 1106 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 1107 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 1108 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 1109 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 1110 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER 1111 1112 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) 1113 1114 /* 1115 * interrupt flags in INTA, set by uCode or hardware (e.g. dma), 1116 * acknowledged (reset) by host writing "1" to flagged bits. 1117 */ 1118 #define BIT_INT_FH_RX \ 1119 (((uint32_t)1) << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 1120 #define BIT_INT_ERR (1<<29) /* DMA hardware error FH_INT[31] */ 1121 #define BIT_INT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ 1122 #define BIT_INT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ 1123 #define BIT_INT_SWERROR (1<<25) /* uCode error */ 1124 #define BIT_INT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 1125 #define BIT_INT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ 1126 #define BIT_INT_SW_RX (1<<3) /* Rx, command responses, 3945 */ 1127 #define BIT_INT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ 1128 #define BIT_INT_ALIVE (1<<0) /* uCode interrupts once it initializes */ 1129 1130 #define CSR_INI_SET_MASK (BIT_INT_FH_RX | \ 1131 BIT_INT_ERR | \ 1132 BIT_INT_FH_TX | \ 1133 BIT_INT_SWERROR | \ 1134 BIT_INT_RF_KILL | \ 1135 BIT_INT_SW_RX | \ 1136 BIT_INT_WAKEUP | \ 1137 BIT_INT_ALIVE) 1138 1139 /* 1140 * interrupt flags in FH (flow handler) (PCI busmaster DMA) 1141 */ 1142 #define BIT_FH_INT_ERR (((uint32_t)1) << 31) /* Error */ 1143 #define BIT_FH_INT_HI_PRIOR (1<<30) /* High priority Rx,bypass coalescing */ 1144 #define BIT_FH_INT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */ 1145 #define BIT_FH_INT_RX_CHNL1 (1<<17) /* Rx channel 1 */ 1146 #define BIT_FH_INT_RX_CHNL0 (1<<16) /* Rx channel 0 */ 1147 #define BIT_FH_INT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */ 1148 #define BIT_FH_INT_TX_CHNL1 (1<<1) /* Tx channel 1 */ 1149 #define BIT_FH_INT_TX_CHNL0 (1<<0) /* Tx channel 0 */ 1150 1151 #define FH_INT_RX_MASK (BIT_FH_INT_HI_PRIOR | \ 1152 BIT_FH_INT_RX_CHNL2 | \ 1153 BIT_FH_INT_RX_CHNL1 | \ 1154 BIT_FH_INT_RX_CHNL0) 1155 1156 #define FH_INT_TX_MASK (BIT_FH_INT_TX_CHNL6 | \ 1157 BIT_FH_INT_TX_CHNL1 | \ 1158 BIT_FH_INT_TX_CHNL0) 1159 1160 /* 1161 * RESET 1162 */ 1163 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 1164 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 1165 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 1166 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 1167 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 1168 1169 /* 1170 * GP (general purpose) CONTROL 1171 */ 1172 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 1173 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 1174 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 1175 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 1176 1177 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 1178 1179 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 1180 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 1181 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 1182 1183 /* 1184 * APMG (power management) constants 1185 */ 1186 #define APMG_CLK_CTRL_REG (0x003000) 1187 #define ALM_APMG_CLK_EN (0x003004) 1188 #define ALM_APMG_CLK_DIS (0x003008) 1189 #define ALM_APMG_PS_CTL (0x00300c) 1190 #define ALM_APMG_PCIDEV_STT (0x003010) 1191 #define ALM_APMG_RFKILL (0x003014) 1192 #define ALM_APMG_LARC_INT (0x00301c) 1193 #define ALM_APMG_LARC_INT_MSK (0x003020) 1194 1195 #define APMG_CLK_REG_VAL_DMA_CLK_RQT (0x00000200) 1196 #define APMG_CLK_REG_VAL_BSM_CLK_RQT (0x00000800) 1197 1198 #define APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ (0x04000000) 1199 1200 #define APMG_DEV_STATE_REG_VAL_L1_ACTIVE_DISABLE (0x00000800) 1201 1202 #define APMG_PS_CTRL_REG_MSK_POWER_SRC (0x03000000) 1203 #define APMG_PS_CTRL_REG_VAL_POWER_SRC_VMAIN (0x00000000) 1204 #define APMG_PS_CTRL_REG_VAL_POWER_SRC_VAUX (0x01000000) 1205 1206 /* 1207 * BSM (bootstrap state machine) 1208 */ 1209 /* 1210 * start boot load now 1211 */ 1212 #define BSM_WR_CTRL_REG_BIT_START (0x80000000) 1213 /* 1214 * enable boot after power up 1215 */ 1216 #define BSM_WR_CTRL_REG_BIT_START_EN (0x40000000) 1217 1218 /* 1219 * DBM 1220 */ 1221 #define ALM_FH_SRVC_CHNL (6) 1222 1223 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20) 1224 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4) 1225 1226 #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000) 1227 1228 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000) 1229 1230 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000) 1231 1232 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000) 1233 1234 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000) 1235 1236 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000) 1237 1238 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1239 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) 1240 1241 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) 1242 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) 1243 1244 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1245 1246 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1247 1248 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1249 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1250 1251 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000) 1252 1253 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) 1254 1255 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) 1256 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) 1257 1258 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) 1259 1260 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) 1261 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) 1262 1263 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) 1264 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) 1265 1266 #define ALM_TB_MAX_BYTES_COUNT (0xFFF0) 1267 1268 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \ 1269 ((1LU << _channel) << 24) 1270 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \ 1271 ((1LU << _channel) << 16) 1272 1273 #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \ 1274 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \ 1275 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel)) 1276 #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ 1277 #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ 1278 1279 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 1280 1281 #define TFD_QUEUE_MIN 0 1282 #define TFD_QUEUE_MAX 6 1283 #define TFD_QUEUE_SIZE_MAX (256) 1284 1285 /* 1286 * spectrum and channel data structures 1287 */ 1288 #define IWK_NUM_SCAN_RATES (2) 1289 1290 #define IWK_SCAN_FLAG_24GHZ (1<<0) 1291 #define IWK_SCAN_FLAG_52GHZ (1<<1) 1292 #define IWK_SCAN_FLAG_ACTIVE (1<<2) 1293 #define IWK_SCAN_FLAG_DIRECT (1<<3) 1294 1295 #define IWK_MAX_CMD_SIZE 1024 1296 1297 #define IWK_DEFAULT_TX_RETRY 15 1298 #define IWK_MAX_TX_RETRY 16 1299 1300 #define RFD_SIZE 4 1301 #define NUM_TFD_CHUNKS 4 1302 1303 #define RX_QUEUE_SIZE 256 1304 #define RX_QUEUE_SIZE_LOG 8 1305 1306 /* 1307 * TX Queue Flag Definitions 1308 */ 1309 /* 1310 * use short preamble 1311 */ 1312 #define DCT_FLAG_LONG_PREAMBLE 0x00 1313 #define DCT_FLAG_SHORT_PREAMBLE 0x04 1314 1315 /* 1316 * ACK rx is expected to follow 1317 */ 1318 #define DCT_FLAG_ACK_REQD 0x80 1319 1320 #define IWK_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24 1321 #define IWK_MB_ROAMING_THRESHOLD_DEFAULT 8 1322 #define IWK_REAL_RATE_RX_PACKET_THRESHOLD 300 1323 1324 /* 1325 * QoS definitions 1326 */ 1327 #define CW_MIN_OFDM 15 1328 #define CW_MAX_OFDM 1023 1329 #define CW_MIN_CCK 31 1330 #define CW_MAX_CCK 1023 1331 1332 #define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM 1333 #define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM 1334 #define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1) 1335 #define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1) 1336 1337 #define QOS_TX0_CW_MIN_CCK CW_MIN_CCK 1338 #define QOS_TX1_CW_MIN_CCK CW_MIN_CCK 1339 #define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1) 1340 #define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1) 1341 1342 #define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM 1343 #define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM 1344 #define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM 1345 #define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1) 1346 1347 #define QOS_TX0_CW_MAX_CCK CW_MAX_CCK 1348 #define QOS_TX1_CW_MAX_CCK CW_MAX_CCK 1349 #define QOS_TX2_CW_MAX_CCK CW_MIN_CCK 1350 #define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1) 1351 1352 #define QOS_TX0_AIFS (3) 1353 #define QOS_TX1_AIFS (7) 1354 #define QOS_TX2_AIFS (2) 1355 #define QOS_TX3_AIFS (2) 1356 1357 #define QOS_TX0_ACM 0 1358 #define QOS_TX1_ACM 0 1359 #define QOS_TX2_ACM 0 1360 #define QOS_TX3_ACM 0 1361 1362 #define QOS_TX0_TXOP_LIMIT_CCK 0 1363 #define QOS_TX1_TXOP_LIMIT_CCK 0 1364 #define QOS_TX2_TXOP_LIMIT_CCK 6016 1365 #define QOS_TX3_TXOP_LIMIT_CCK 3264 1366 1367 #define QOS_TX0_TXOP_LIMIT_OFDM 0 1368 #define QOS_TX1_TXOP_LIMIT_OFDM 0 1369 #define QOS_TX2_TXOP_LIMIT_OFDM 3008 1370 #define QOS_TX3_TXOP_LIMIT_OFDM 1504 1371 1372 #define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM 1373 #define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM 1374 #define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM 1375 #define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM 1376 1377 #define DEF_TX0_CW_MIN_CCK CW_MIN_CCK 1378 #define DEF_TX1_CW_MIN_CCK CW_MIN_CCK 1379 #define DEF_TX2_CW_MIN_CCK CW_MIN_CCK 1380 #define DEF_TX3_CW_MIN_CCK CW_MIN_CCK 1381 1382 #define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM 1383 #define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM 1384 #define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM 1385 #define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM 1386 1387 #define DEF_TX0_CW_MAX_CCK CW_MAX_CCK 1388 #define DEF_TX1_CW_MAX_CCK CW_MAX_CCK 1389 #define DEF_TX2_CW_MAX_CCK CW_MAX_CCK 1390 #define DEF_TX3_CW_MAX_CCK CW_MAX_CCK 1391 1392 #define DEF_TX0_AIFS (2) 1393 #define DEF_TX1_AIFS (2) 1394 #define DEF_TX2_AIFS (2) 1395 #define DEF_TX3_AIFS (2) 1396 1397 #define DEF_TX0_ACM (0) 1398 #define DEF_TX1_ACM (0) 1399 #define DEF_TX2_ACM (0) 1400 #define DEF_TX3_ACM (0) 1401 1402 #define DEF_TX0_TXOP_LIMIT_CCK (0) 1403 #define DEF_TX1_TXOP_LIMIT_CCK (0) 1404 #define DEF_TX2_TXOP_LIMIT_CCK (0) 1405 #define DEF_TX3_TXOP_LIMIT_CCK (0) 1406 1407 #define DEF_TX0_TXOP_LIMIT_OFDM (0) 1408 #define DEF_TX1_TXOP_LIMIT_OFDM (0) 1409 #define DEF_TX2_TXOP_LIMIT_OFDM (0) 1410 #define DEF_TX3_TXOP_LIMIT_OFDM (0) 1411 1412 #define QOS_QOS_SETS (3) 1413 #define QOS_PARAM_SET_ACTIVE (0) 1414 #define QOS_PARAM_SET_DEF_CCK (1) 1415 #define QOS_PARAM_SET_DEF_OFDM (2) 1416 1417 #define CTRL_QOS_NO_ACK (0x0020) 1418 #define DCT_FLAG_EXT_QOS_ENABLED (0x10) 1419 1420 #define IWK_TX_QUEUE_AC0 (0) 1421 #define IWK_TX_QUEUE_AC1 (1) 1422 #define IWK_TX_QUEUE_AC2 (2) 1423 #define IWK_TX_QUEUE_AC3 (3) 1424 #define IWK_TX_QUEUE_HCCA_1 (5) 1425 #define IWK_TX_QUEUE_HCCA_2 (6) 1426 1427 #define U32_PAD(n) ((4-(n%4))%4) 1428 1429 #define AC_BE_TID_MASK 0x9 /* TID 0 and 3 */ 1430 #define AC_BK_TID_MASK 0x6 /* TID 1 and 2 */ 1431 1432 /* 1433 * Generic queue structure 1434 * 1435 * Contains common data for Rx and Tx queues 1436 */ 1437 #define TFD_CTL_COUNT_SET(n) (n<<24) 1438 #define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7) 1439 #define TFD_CTL_PAD_SET(n) (n<<28) 1440 #define TFD_CTL_PAD_GET(ctl) (ctl>>28) 1441 1442 #define TFD_TX_CMD_SLOTS 64 1443 #define TFD_CMD_SLOTS 32 1444 1445 /* 1446 * Tx/Rx Queues 1447 * 1448 * Most communication between driver and 4965 is via queues of data buffers. 1449 * For example, all commands that the driver issues to device's embedded 1450 * controller (uCode) are via the command queue (one of the Tx queues). All 1451 * uCode command responses/replies/notifications, including Rx frames, are 1452 * conveyed from uCode to driver via the Rx queue. 1453 * 1454 * Most support for these queues, including handshake support, resides in 1455 * structures in host DRAM, shared between the driver and the device. When 1456 * allocating this memory, the driver must make sure that data written by 1457 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's 1458 * cache memory), so DRAM and cache are consistent, and the device can 1459 * immediately see changes made by the driver. 1460 * 1461 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via 1462 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array 1463 * in DRAM containing 256 Transmit Frame Descriptors (TFDs). 1464 */ 1465 #define IWK_MAX_WIN_SIZE 64 1466 #define IWK_QUEUE_SIZE 256 1467 #define IWK_NUM_FIFOS 7 1468 #define IWK_NUM_QUEUES 16 1469 #define IWK_CMD_QUEUE_NUM 4 1470 #define IWK_KW_SIZE 0x1000 /* 4k */ 1471 1472 struct iwk_rate { 1473 union { 1474 struct { 1475 uint8_t rate; 1476 uint8_t flags; 1477 uint16_t ext_flags; 1478 } s; 1479 uint32_t rate_n_flags; 1480 } r; 1481 }; 1482 1483 struct iwk_dram_scratch { 1484 uint8_t try_cnt; 1485 uint8_t bt_kill_cnt; 1486 uint16_t reserved; 1487 }; 1488 1489 /* 1490 * START TEMPERATURE 1491 */ 1492 /* 1493 * 4965 temperature calculation. 1494 * 1495 * The driver must calculate the device temperature before calculating 1496 * a txpower setting (amplifier gain is temperature dependent). The 1497 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration 1498 * values used for the life of the driver, and one of which (R4) is the 1499 * real-time temperature indicator. 1500 * 1501 * uCode provides all 4 values to the driver via the "initialize alive" 1502 * notification (see struct iwk_init_alive_resp). After the runtime uCode 1503 * image loads, uCode updates the R4 value via statistics notifications 1504 * (see STATISTICS_NOTIFICATION), which occur after each received beacon 1505 * when associated, or can be requested via REPLY_STATISTICS_CMD. 1506 * 1507 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver 1508 * must sign-extend to 32 bits before applying formula below. 1509 * 1510 * Formula: 1511 * 1512 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8 1513 * 1514 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is 1515 * an additional correction, which should be centered around 0 degrees 1516 * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for 1517 * centering the 97/100 correction around 0 degrees K. 1518 * 1519 * Add 273 to Kelvin value to find degrees Celsius, for comparing current 1520 * temperature with factory-measured temperatures when calculating txpower 1521 * settings. 1522 */ 1523 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 1524 #define TEMPERATURE_CALIB_A_VAL 259 1525 1526 /* 1527 * Limit range of calculated temperature to be between these Kelvin values 1528 */ 1529 #define IWK_TX_POWER_TEMPERATURE_MIN (263) 1530 #define IWK_TX_POWER_TEMPERATURE_MAX (410) 1531 1532 #define IWK_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ 1533 (((t) < IWK_TX_POWER_TEMPERATURE_MIN) || \ 1534 ((t) > IWK_TX_POWER_TEMPERATURE_MAX)) 1535 1536 /* 1537 * END TEMPERATURE 1538 */ 1539 1540 /* 1541 * START TXPOWER 1542 */ 1543 /* 1544 * 4965 txpower calculations rely on information from three sources: 1545 * 1546 * 1) EEPROM 1547 * 2) "initialize" alive notification 1548 * 3) statistics notifications 1549 * 1550 * EEPROM data consists of: 1551 * 1552 * 1) Regulatory information (max txpower and channel usage flags) is provided 1553 * separately for each channel that can possibly supported by 4965. 1554 * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz 1555 * (legacy) channels. 1556 * 1557 * See struct iwk_eeprom_channel for format, and struct iwk_eeprom for 1558 * locations in EEPROM. 1559 * 1560 * 2) Factory txpower calibration information is provided separately for 1561 * sub-bands of contiguous channels. 2.4GHz has just one sub-band, 1562 * but 5 GHz has several sub-bands. 1563 * 1564 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided. 1565 * 1566 * See struct iwk_eeprom_calib_info (and the tree of structures contained 1567 * within it) for format, and struct iwk_eeprom for locations in EEPROM. 1568 * 1569 * "Initialization alive" notification (see struct iwk_init_alive_resp) 1570 * consists of: 1571 * 1572 * 1) Temperature calculation parameters. 1573 * 1574 * 2) Power supply voltage measurement. 1575 * 1576 * 3) Tx gain compensation to balance 2 transmitters for MIMO use. 1577 * 1578 * Statistics notifications deliver: 1579 * 1580 * 1) Current values for temperature param R4. 1581 */ 1582 1583 /* 1584 * To calculate a txpower setting for a given desired target txpower, channel, 1585 * modulation bit rate, and transmitter chain (4965 has 2 transmitters to 1586 * support MIMO and transmit diversity), driver must do the following: 1587 * 1588 * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel. 1589 * Do not exceed regulatory limit; reduce target txpower if necessary. 1590 * 1591 * If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), 1592 * 2 transmitters will be used simultaneously; driver must reduce the 1593 * regulatory limit by 3 dB (half-power) for each transmitter, so the 1594 * combined total output of the 2 transmitters is within regulatory limits. 1595 * 1596 * 1597 * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by 1598 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]); 1599 * reduce target txpower if necessary. 1600 * 1601 * Backoff values below are in 1/2 dB units (equivalent to steps in 1602 * txpower gain tables): 1603 * 1604 * OFDM 6 - 36 MBit: 10 steps (5 dB) 1605 * OFDM 48 MBit: 15 steps (7.5 dB) 1606 * OFDM 54 MBit: 17 steps (8.5 dB) 1607 * OFDM 60 MBit: 20 steps (10 dB) 1608 * CCK all rates: 10 steps (5 dB) 1609 * 1610 * Backoff values apply to saturation txpower on a per-transmitter basis; 1611 * when using MIMO (2 transmitters), each transmitter uses the same 1612 * saturation level provided in EEPROM, and the same backoff values; 1613 * no reduction (such as with regulatory txpower limits) is required. 1614 * 1615 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel 1616 * widths and 40 Mhz (.11n fat) channel widths; there is no separate 1617 * factory measurement for fat channels. 1618 * 1619 * The result of this step is the final target txpower. The rest of 1620 * the steps figure out the proper settings for the device. 1621 * 1622 * 1623 * 3) Determine (EEPROM) calibration subband for the target channel, by 1624 * comparing against first and last channels in each subband 1625 * (see struct iwk_eeprom_calib_subband_info). 1626 * 1627 * 1628 * 4) Linearly interpolate (EEPROM) factory calibration measurement sets, 1629 * referencing the 2 factory-measured (sample) channels within the subband. 1630 * 1631 * Interpolation is based on difference between target channel's frequency 1632 * and the sample channels' frequencies. Since channel numbers are based 1633 * on frequency (5 MHz between each channel number), this is equivalent 1634 * to interpolating based on channel number differences. 1635 * 1636 * Note that the sample channels may or may not be the channels at the 1637 * edges of the subband. The target channel may be "outside" of the 1638 * span of the sampled channels. 1639 * 1640 * Driver may choose the pair (for 2 Tx chains) of measurements (see 1641 * struct iwk_eeprom_calib_ch_info) for which the actual measured 1642 * txpower comes closest to the desired txpower. Usually, though, 1643 * the middle set of measurements is closest to the regulatory limits, 1644 * and is therefore a good choice for all txpower calculations. 1645 * 1646 * Driver should interpolate both members of the chosen measurement pair, 1647 * i.e. for both Tx chains (radio transmitters), unless the driver knows 1648 * that only one of the chains will be used (e.g. only one tx antenna 1649 * connected, but this should be unusual). 1650 * 1651 * Driver should interpolate factory values for temperature, gain table 1652 * index, and actual power. The power amplifier detector values are 1653 * not used by the driver. 1654 * 1655 * If the target channel happens to be one of the sample channels, the 1656 * results should agree with the sample channel's measurements! 1657 * 1658 * 1659 * 5) Find difference between desired txpower and (interpolated) 1660 * factory-measured txpower. Using (interpolated) factory gain table index 1661 * as a starting point, adjust this index lower to increase txpower, 1662 * or higher to decrease txpower, until the target txpower is reached. 1663 * Each step in the gain table is 1/2 dB. 1664 * 1665 * For example, if factory measured txpower is 16 dBm, and target txpower 1666 * is 13 dBm, add 6 steps to the factory gain index to reduce txpower 1667 * by 3 dB. 1668 * 1669 * 1670 * 6) Find difference between current device temperature and (interpolated) 1671 * factory-measured temperature for sub-band. Factory values are in 1672 * degrees Celsius. To calculate current temperature, see comments for 1673 * "4965 temperature calculation". 1674 * 1675 * If current temperature is higher than factory temperature, driver must 1676 * increase gain (lower gain table index), and vice versa. 1677 * 1678 * Temperature affects gain differently for different channels: 1679 * 1680 * 2.4 GHz all channels: 3.5 degrees per half-dB step 1681 * 5 GHz channels 34-43: 4.5 degrees per half-dB step 1682 * 5 GHz channels >= 44: 4.0 degrees per half-dB step 1683 * 1684 * NOTE: Temperature can increase rapidly when transmitting, especially 1685 * with heavy traffic at high txpowers. Driver should update 1686 * temperature calculations often under these conditions to 1687 * maintain strong txpower in the face of rising temperature. 1688 * 1689 * 1690 * 7) Find difference between current power supply voltage indicator 1691 * (from "initialize alive") and factory-measured power supply voltage 1692 * indicator (EEPROM). 1693 * 1694 * If the current voltage is higher (indicator is lower) than factory 1695 * voltage, gain should be reduced (gain table index increased) by: 1696 * 1697 * (eeprom - current) / 7 1698 * 1699 * If the current voltage is lower (indicator is higher) than factory 1700 * voltage, gain should be increased (gain table index decreased) by: 1701 * 1702 * 2 * (current - eeprom) / 7 1703 * 1704 * If number of index steps in either direction turns out to be > 2, 1705 * something is wrong ... just use 0. 1706 * 1707 * NOTE: Voltage compensation is independent of band/channel. 1708 * 1709 * NOTE: "Initialize" uCode measures current voltage, which is assumed 1710 * to be constant after this initial measurement. Voltage 1711 * compensation for txpower (number of steps in gain table) 1712 * may be calculated once and used until the next uCode bootload. 1713 * 1714 * 1715 * 8) If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), 1716 * adjust txpower for each transmitter chain, so txpower is balanced 1717 * between the two chains. There are 5 pairs of tx_atten[group][chain] 1718 * values in "initialize alive", one pair for each of 5 channel ranges: 1719 * 1720 * Group 0: 5 GHz channel 34-43 1721 * Group 1: 5 GHz channel 44-70 1722 * Group 2: 5 GHz channel 71-124 1723 * Group 3: 5 GHz channel 125-200 1724 * Group 4: 2.4 GHz all channels 1725 * 1726 * Add the tx_atten[group][chain] value to the index for the target chain. 1727 * The values are signed, but are in pairs of 0 and a non-negative number, 1728 * so as to reduce gain (if necessary) of the "hotter" channel. This 1729 * avoids any need to double-check for regulatory compliance after 1730 * this step. 1731 * 1732 * 1733 * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation 1734 * value to the index: 1735 * 1736 * Hardware rev B: 9 steps (4.5 dB) 1737 * Hardware rev C: 5 steps (2.5 dB) 1738 * 1739 * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, 1740 * bits [3:2], 1 = B, 2 = C. 1741 * 1742 * NOTE: This compensation is in addition to any saturation backoff that 1743 * might have been applied in an earlier step. 1744 * 1745 * 1746 * 10) Select the gain table, based on band (2.4 vs 5 GHz). 1747 * 1748 * Limit the adjusted index to stay within the table! 1749 * 1750 * 1751 * 11) Read gain table entries for DSP and radio gain, place into appropriate 1752 * location(s) in command. 1753 */ 1754 1755 enum { 1756 HT_IE_EXT_CHANNEL_NONE = 0, 1757 HT_IE_EXT_CHANNEL_ABOVE, 1758 HT_IE_EXT_CHANNEL_INVALID, 1759 HT_IE_EXT_CHANNEL_BELOW, 1760 HT_IE_EXT_CHANNEL_MAX 1761 }; 1762 1763 enum { 1764 CALIB_CH_GROUP_1 = 0, 1765 CALIB_CH_GROUP_2 = 1, 1766 CALIB_CH_GROUP_3 = 2, 1767 CALIB_CH_GROUP_4 = 3, 1768 CALIB_CH_GROUP_5 = 4, 1769 CALIB_CH_GROUP_MAX 1770 }; 1771 1772 #define POWER_TABLE_NUM_HT_OFDM_ENTRIES (32) 1773 1774 /* 1775 * Temperature calibration offset is 3% 0C in Kelvin 1776 */ 1777 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 1778 #define TEMPERATURE_CALIB_A_VAL 259 1779 1780 #define IWK_TX_POWER_TEMPERATURE_MIN (263) 1781 #define IWK_TX_POWER_TEMPERATURE_MAX (410) 1782 1783 #define IWK_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ 1784 (((t) < IWK_TX_POWER_TEMPERATURE_MIN) || \ 1785 ((t) > IWK_TX_POWER_TEMPERATURE_MAX)) 1786 1787 #define IWK_TX_POWER_ILLEGAL_TEMPERATURE (300) 1788 1789 #define IWK_TX_POWER_TEMPERATURE_DIFFERENCE (2) 1790 1791 /* 1792 * When MIMO is used (2 transmitters operating simultaneously), driver should 1793 * limit each transmitter to deliver a max of 3 dB below the regulatory limit 1794 * for the device. That is, half power for each transmitter, so total power 1795 * is within regulatory limits. 1796 * 1797 * The value "6" represents number of steps in gain table to reduce power. 1798 * Each step is 1/2 dB. 1799 */ 1800 #define IWK_TX_POWER_MIMO_REGULATORY_COMPENSATION (6) 1801 1802 /* 1803 * Limit range of txpower output target to be between these values 1804 */ 1805 #define IWK_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */ 1806 #define IWK_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */ 1807 1808 /* 1809 * timeout equivalent to 3 minutes 1810 */ 1811 #define IWK_TX_POWER_TIMELIMIT_NOCALIB 1800000000 1812 1813 /* 1814 * CCK gain compensation. 1815 * 1816 * When calculating txpowers for CCK, after making sure that the target power 1817 * is within regulatory and saturation limits, driver must additionally 1818 * back off gain by adding these values to the gain table index. 1819 */ 1820 #define IWK_TX_POWER_CCK_COMPENSATION (9) 1821 #define IWK_TX_POWER_CCK_COMPENSATION_B_STEP (9) 1822 #define IWK_TX_POWER_CCK_COMPENSATION_C_STEP (5) 1823 1824 /* 1825 * 4965 power supply voltage compensation 1826 */ 1827 #define TX_POWER_IWK_VOLTAGE_CODES_PER_03V (7) 1828 1829 /* 1830 * Gain tables. 1831 * 1832 * The following tables contain pair of values for setting txpower, i.e. 1833 * gain settings for the output of the device's digital signal processor (DSP), 1834 * and for the analog gain structure of the transmitter. 1835 * 1836 * Each entry in the gain tables represents a step of 1/2 dB. Note that these 1837 * are *relative* steps, not indications of absolute output power. Output 1838 * power varies with temperature, voltage, and channel frequency, and also 1839 * requires consideration of average power (to satisfy regulatory constraints), 1840 * and peak power (to avoid distortion of the output signal). 1841 * 1842 * Each entry contains two values: 1843 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained 1844 * linear value that multiplies the output of the digital signal processor, 1845 * before being sent to the analog radio. 1846 * 2) Radio gain. This sets the analog gain of the radio Tx path. 1847 * It is a coarser setting, and behaves in a logarithmic (dB) fashion. 1848 * 1849 * EEPROM contains factory calibration data for txpower. This maps actual 1850 * measured txpower levels to gain settings in the "well known" tables 1851 * below ("well-known" means here that both factory calibration *and* the 1852 * driver work with the same table). 1853 * 1854 * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table 1855 * has an extension (into negative indexes), in case the driver needs to 1856 * boost power setting for high device temperatures (higher than would be 1857 * present during factory calibration). A 5 Ghz EEPROM index of "40" 1858 * corresponds to the 49th entry in the table used by the driver. 1859 */ 1860 #define MIN_TX_GAIN_INDEX (0) 1861 #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) 1862 #define MAX_TX_GAIN_INDEX_52GHZ (98) 1863 #define MIN_TX_GAIN_52GHZ (98) 1864 #define MAX_TX_GAIN_INDEX_24GHZ (98) 1865 #define MIN_TX_GAIN_24GHZ (98) 1866 #define MAX_TX_GAIN (0) 1867 #define MAX_TX_GAIN_52GHZ_EXT (-9) 1868 1869 /* 1870 * 2.4 GHz gain table 1871 * 1872 * Index Dsp gain Radio gain 1873 * 0 110 0x3f 1874 * 1 104 0x3f 1875 * 2 98 0x3f 1876 * 3 110 0x3e 1877 * 4 104 0x3e 1878 * 5 98 0x3e 1879 * 6 110 0x3d 1880 * 7 104 0x3d 1881 * 8 98 0x3d 1882 * 9 110 0x3c 1883 * 10 104 0x3c 1884 * 11 98 0x3c 1885 * 12 110 0x3b 1886 * 13 104 0x3b 1887 * 14 98 0x3b 1888 * 15 110 0x3a 1889 * 16 104 0x3a 1890 * 17 98 0x3a 1891 * 18 110 0x39 1892 * 19 104 0x39 1893 * 20 98 0x39 1894 * 21 110 0x38 1895 * 22 104 0x38 1896 * 23 98 0x38 1897 * 24 110 0x37 1898 * 25 104 0x37 1899 * 26 98 0x37 1900 * 27 110 0x36 1901 * 28 104 0x36 1902 * 29 98 0x36 1903 * 30 110 0x35 1904 * 31 104 0x35 1905 * 32 98 0x35 1906 * 33 110 0x34 1907 * 34 104 0x34 1908 * 35 98 0x34 1909 * 36 110 0x33 1910 * 37 104 0x33 1911 * 38 98 0x33 1912 * 39 110 0x32 1913 * 40 104 0x32 1914 * 41 98 0x32 1915 * 42 110 0x31 1916 * 43 104 0x31 1917 * 44 98 0x31 1918 * 45 110 0x30 1919 * 46 104 0x30 1920 * 47 98 0x30 1921 * 48 110 0x6 1922 * 49 104 0x6 1923 * 50 98 0x6 1924 * 51 110 0x5 1925 * 52 104 0x5 1926 * 53 98 0x5 1927 * 54 110 0x4 1928 * 55 104 0x4 1929 * 56 98 0x4 1930 * 57 110 0x3 1931 * 58 104 0x3 1932 * 59 98 0x3 1933 * 60 110 0x2 1934 * 61 104 0x2 1935 * 62 98 0x2 1936 * 63 110 0x1 1937 * 64 104 0x1 1938 * 65 98 0x1 1939 * 66 110 0x0 1940 * 67 104 0x0 1941 * 68 98 0x0 1942 * 69 97 0 1943 * 70 96 0 1944 * 71 95 0 1945 * 72 94 0 1946 * 73 93 0 1947 * 74 92 0 1948 * 75 91 0 1949 * 76 90 0 1950 * 77 89 0 1951 * 78 88 0 1952 * 79 87 0 1953 * 80 86 0 1954 * 81 85 0 1955 * 82 84 0 1956 * 83 83 0 1957 * 84 82 0 1958 * 85 81 0 1959 * 86 80 0 1960 * 87 79 0 1961 * 88 78 0 1962 * 89 77 0 1963 * 90 76 0 1964 * 91 75 0 1965 * 92 74 0 1966 * 93 73 0 1967 * 94 72 0 1968 * 95 71 0 1969 * 96 70 0 1970 * 97 69 0 1971 * 98 68 0 1972 */ 1973 1974 /* 1975 * 5 GHz gain table 1976 * 1977 * Index Dsp gain Radio gain 1978 * -9 123 0x3F 1979 * -8 117 0x3F 1980 * -7 110 0x3F 1981 * -6 104 0x3F 1982 * -5 98 0x3F 1983 * -4 110 0x3E 1984 * -3 104 0x3E 1985 * -2 98 0x3E 1986 * -1 110 0x3D 1987 * 0 104 0x3D 1988 * 1 98 0x3D 1989 * 2 110 0x3C 1990 * 3 104 0x3C 1991 * 4 98 0x3C 1992 * 5 110 0x3B 1993 * 6 104 0x3B 1994 * 7 98 0x3B 1995 * 8 110 0x3A 1996 * 9 104 0x3A 1997 * 10 98 0x3A 1998 * 11 110 0x39 1999 * 12 104 0x39 2000 * 13 98 0x39 2001 * 14 110 0x38 2002 * 15 104 0x38 2003 * 16 98 0x38 2004 * 17 110 0x37 2005 * 18 104 0x37 2006 * 19 98 0x37 2007 * 20 110 0x36 2008 * 21 104 0x36 2009 * 22 98 0x36 2010 * 23 110 0x35 2011 * 24 104 0x35 2012 * 25 98 0x35 2013 * 26 110 0x34 2014 * 27 104 0x34 2015 * 28 98 0x34 2016 * 29 110 0x33 2017 * 30 104 0x33 2018 * 31 98 0x33 2019 * 32 110 0x32 2020 * 33 104 0x32 2021 * 34 98 0x32 2022 * 35 110 0x31 2023 * 36 104 0x31 2024 * 37 98 0x31 2025 * 38 110 0x30 2026 * 39 104 0x30 2027 * 40 98 0x30 2028 * 41 110 0x25 2029 * 42 104 0x25 2030 * 43 98 0x25 2031 * 44 110 0x24 2032 * 45 104 0x24 2033 * 46 98 0x24 2034 * 47 110 0x23 2035 * 48 104 0x23 2036 * 49 98 0x23 2037 * 50 110 0x22 2038 * 51 104 0x18 2039 * 52 98 0x18 2040 * 53 110 0x17 2041 * 54 104 0x17 2042 * 55 98 0x17 2043 * 56 110 0x16 2044 * 57 104 0x16 2045 * 58 98 0x16 2046 * 59 110 0x15 2047 * 60 104 0x15 2048 * 61 98 0x15 2049 * 62 110 0x14 2050 * 63 104 0x14 2051 * 64 98 0x14 2052 * 65 110 0x13 2053 * 66 104 0x13 2054 * 67 98 0x13 2055 * 68 110 0x12 2056 * 69 104 0x08 2057 * 70 98 0x08 2058 * 71 110 0x07 2059 * 72 104 0x07 2060 * 73 98 0x07 2061 * 74 110 0x06 2062 * 75 104 0x06 2063 * 76 98 0x06 2064 * 77 110 0x05 2065 * 78 104 0x05 2066 * 79 98 0x05 2067 * 80 110 0x04 2068 * 81 104 0x04 2069 * 82 98 0x04 2070 * 83 110 0x03 2071 * 84 104 0x03 2072 * 85 98 0x03 2073 * 86 110 0x02 2074 * 87 104 0x02 2075 * 88 98 0x02 2076 * 89 110 0x01 2077 * 90 104 0x01 2078 * 91 98 0x01 2079 * 92 110 0x00 2080 * 93 104 0x00 2081 * 94 98 0x00 2082 * 95 93 0x00 2083 * 96 88 0x00 2084 * 97 83 0x00 2085 * 98 78 0x00 2086 */ 2087 2088 /* 2089 * Sanity checks and default values for EEPROM regulatory levels. 2090 * If EEPROM values fall outside MIN/MAX range, use default values. 2091 * 2092 * Regulatory limits refer to the maximum average txpower allowed by 2093 * regulatory agencies in the geographies in which the device is meant 2094 * to be operated. These limits are SKU-specific (i.e. geography-specific), 2095 * and channel-specific; each channel has an individual regulatory limit 2096 * listed in the EEPROM. 2097 * 2098 * Units are in half-dBm (i.e. "34" means 17 dBm). 2099 */ 2100 #define IWK_TX_POWER_DEFAULT_REGULATORY_24 (34) 2101 #define IWK_TX_POWER_DEFAULT_REGULATORY_52 (34) 2102 #define IWK_TX_POWER_REGULATORY_MIN (0) 2103 #define IWK_TX_POWER_REGULATORY_MAX (34) 2104 2105 /* 2106 * Sanity checks and default values for EEPROM saturation levels. 2107 * If EEPROM values fall outside MIN/MAX range, use default values. 2108 * 2109 * Saturation is the highest level that the output power amplifier can produce 2110 * without significant clipping distortion. This is a "peak" power level. 2111 * Different types of modulation (i.e. various "rates", and OFDM vs. CCK) 2112 * require differing amounts of backoff, relative to their average power output, 2113 * in order to avoid clipping distortion. 2114 * 2115 * Driver must make sure that it is violating neither the saturation limit, 2116 * nor the regulatory limit, when calculating Tx power settings for various 2117 * rates. 2118 * 2119 * Units are in half-dBm (i.e. "38" means 19 dBm). 2120 */ 2121 #define IWK_TX_POWER_DEFAULT_SATURATION_24 (38) 2122 #define IWK_TX_POWER_DEFAULT_SATURATION_52 (38) 2123 #define IWK_TX_POWER_SATURATION_MIN (20) 2124 #define IWK_TX_POWER_SATURATION_MAX (50) 2125 2126 /* 2127 * dv *0.4 = dt; so that 5 degrees temperature diff equals 2128 * 12.5 in voltage diff 2129 */ 2130 #define IWK_TX_TEMPERATURE_UPDATE_LIMIT 9 2131 2132 #define IWK_INVALID_CHANNEL (0xffffffff) 2133 #define IWK_TX_POWER_REGITRY_BIT (2) 2134 2135 #define MIN_IWK_TX_POWER_CALIB_DUR (100) 2136 #define IWK_CCK_FROM_OFDM_POWER_DIFF (-5) 2137 #define IWK_CCK_FROM_OFDM_INDEX_DIFF (9) 2138 2139 /* 2140 * Number of entries in the gain table 2141 */ 2142 #define POWER_GAIN_NUM_ENTRIES 78 2143 #define TX_POW_MAX_SESSION_NUM 5 2144 2145 /* 2146 * timeout equivalent to 3 minutes 2147 */ 2148 #define TX_IWK_TIMELIMIT_NOCALIB 1800000000 2149 2150 /* 2151 * Kedron TX_CALIB_STATES 2152 */ 2153 #define IWK_TX_CALIB_STATE_SEND_TX 0x00000001 2154 #define IWK_TX_CALIB_WAIT_TX_RESPONSE 0x00000002 2155 #define IWK_TX_CALIB_ENABLED 0x00000004 2156 #define IWK_TX_CALIB_XVT_ON 0x00000008 2157 #define IWK_TX_CALIB_TEMPERATURE_CORRECT 0x00000010 2158 #define IWK_TX_CALIB_WORKING_WITH_XVT 0x00000020 2159 #define IWK_TX_CALIB_XVT_PERIODICAL 0x00000040 2160 2161 #define NUM_IWK_TX_CALIB_SETTINS 5 /* Number of tx correction groups */ 2162 2163 #define IWK_MIN_POWER_IN_VP_TABLE 1 /* 0.5dBm multiplied by 2 */ 2164 /* 20dBm - multiplied by 2 - because entries are for each 0.5dBm */ 2165 #define IWK_MAX_POWER_IN_VP_TABLE 40 2166 #define IWK_STEP_IN_VP_TABLE 1 /* 0.5dB - multiplied by 2 */ 2167 #define IWK_NUM_POINTS_IN_VPTABLE \ 2168 (1 + IWK_MAX_POWER_IN_VP_TABLE - IWK_MIN_POWER_IN_VP_TABLE) 2169 2170 #define MIN_TX_GAIN_INDEX (0) 2171 #define MAX_TX_GAIN_INDEX_52GHZ (98) 2172 #define MIN_TX_GAIN_52GHZ (98) 2173 #define MAX_TX_GAIN_INDEX_24GHZ (98) 2174 #define MIN_TX_GAIN_24GHZ (98) 2175 #define MAX_TX_GAIN (0) 2176 2177 /* 2178 * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance) 2179 * and thermal Txpower calibration. 2180 * 2181 * When calculating txpower, driver must compensate for current device 2182 * temperature; higher temperature requires higher gain. Driver must calculate 2183 * current temperature (see "4965 temperature calculation"), then compare vs. 2184 * factory calibration temperature in EEPROM; if current temperature is higher 2185 * than factory temperature, driver must *increase* gain by proportions shown 2186 * in table below. If current temperature is lower than factory, driver must 2187 * *decrease* gain. 2188 * 2189 * Different frequency ranges require different compensation, as shown below. 2190 */ 2191 /* 2192 * Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. 2193 */ 2194 #define CALIB_IWK_TX_ATTEN_GR1_FCH 34 2195 #define CALIB_IWK_TX_ATTEN_GR1_LCH 43 2196 2197 /* 2198 * Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. 2199 */ 2200 #define CALIB_IWK_TX_ATTEN_GR2_FCH 44 2201 #define CALIB_IWK_TX_ATTEN_GR2_LCH 70 2202 2203 /* 2204 * Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. 2205 */ 2206 #define CALIB_IWK_TX_ATTEN_GR3_FCH 71 2207 #define CALIB_IWK_TX_ATTEN_GR3_LCH 124 2208 2209 /* 2210 * Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. 2211 */ 2212 #define CALIB_IWK_TX_ATTEN_GR4_FCH 125 2213 #define CALIB_IWK_TX_ATTEN_GR4_LCH 200 2214 2215 /* 2216 * Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. 2217 */ 2218 #define CALIB_IWK_TX_ATTEN_GR5_FCH 1 2219 #define CALIB_IWK_TX_ATTEN_GR5_LCH 20 2220 2221 struct iwk_tx_power { 2222 uint8_t tx_gain; /* gain for analog radio */ 2223 uint8_t dsp_atten; /* gain for DSP */ 2224 }; 2225 2226 struct tx_power_dual_stream { 2227 uint16_t ramon_tx_gain; 2228 uint16_t dsp_predis_atten; 2229 }; 2230 2231 union tx_power_dual_stream_u { 2232 struct tx_power_dual_stream s; 2233 uint32_t dw; 2234 }; 2235 2236 struct iwk_tx_power_db { 2237 union tx_power_dual_stream_u 2238 ht_ofdm_power[POWER_TABLE_NUM_HT_OFDM_ENTRIES]; 2239 union tx_power_dual_stream_u legacy_cck_power; 2240 2241 }; 2242 2243 typedef struct iwk_tx_power_table_cmd { 2244 uint8_t band; 2245 uint8_t channel_normal_width; 2246 uint16_t channel; 2247 struct iwk_tx_power_db tx_power; 2248 } iwk_tx_power_table_cmd_t; 2249 2250 typedef struct iwk_channel_switch_cmd { 2251 uint8_t band; 2252 uint8_t expect_beacon; 2253 uint16_t channel; 2254 uint32_t rxon_flags; 2255 uint32_t rxon_filter_flags; 2256 uint32_t switch_time; 2257 struct iwk_tx_power_db tx_power; 2258 } iwk_channel_switch_cmd_t; 2259 2260 struct iwk_channel_switch_notif { 2261 uint16_t band; 2262 uint16_t channel; 2263 uint32_t status; 2264 }; 2265 2266 /* 2267 * END TXPOWER 2268 */ 2269 2270 /* 2271 * HT flags 2272 */ 2273 #define RXON_FLG_CONTROL_CHANNEL_LOCATION_MSK 0x400000 2274 #define RXON_FLG_CONTROL_CHANNEL_LOC_LOW_MSK 0x000000 2275 #define RXON_FLG_CONTROL_CHANNEL_LOC_HIGH_MSK 0x400000 2276 2277 #define RXON_FLG_HT_OPERATING_MODE_POS (23) 2278 #define RXON_FLG_HT_PROT_MSK 0x800000 2279 #define RXON_FLG_FAT_PROT_MSK 0x1000000 2280 2281 #define RXON_FLG_CHANNEL_MODE_POS (25) 2282 #define RXON_FLG_CHANNEL_MODE_MSK 0x06000000 2283 #define RXON_FLG_CHANNEL_MODE_LEGACY_MSK 0x00000000 2284 #define RXON_FLG_CHANNEL_MODE_PURE_40_MSK 0x02000000 2285 #define RXON_FLG_CHANNEL_MODE_MIXED_MSK 0x04000000 2286 2287 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK (0x1<<0) 2288 #define RXON_RX_CHAIN_VALID_MSK (0x7<<1) 2289 #define RXON_RX_CHAIN_VALID_POS (1) 2290 #define RXON_RX_CHAIN_FORCE_SEL_MSK (0x7<<4) 2291 #define RXON_RX_CHAIN_FORCE_SEL_POS (4) 2292 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK (0x7<<7) 2293 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2294 #define RXON_RX_CHAIN_CNT_MSK (0x3<<10) 2295 #define RXON_RX_CHAIN_CNT_POS (10) 2296 #define RXON_RX_CHAIN_MIMO_CNT_MSK (0x3<<12) 2297 #define RXON_RX_CHAIN_MIMO_CNT_POS (12) 2298 #define RXON_RX_CHAIN_MIMO_FORCE_MSK (0x1<<14) 2299 #define RXON_RX_CHAIN_MIMO_FORCE_POS (14) 2300 2301 #define MCS_DUP_6M_PLCP 0x20 2302 2303 /* 2304 * OFDM HT rate masks 2305 */ 2306 #define R_MCS_6M_MSK 0x1 2307 #define R_MCS_12M_MSK 0x2 2308 #define R_MCS_18M_MSK 0x4 2309 #define R_MCS_24M_MSK 0x8 2310 #define R_MCS_36M_MSK 0x10 2311 #define R_MCS_48M_MSK 0x20 2312 #define R_MCS_54M_MSK 0x40 2313 #define R_MCS_60M_MSK 0x80 2314 #define R_MCS_12M_DUAL_MSK 0x100 2315 #define R_MCS_24M_DUAL_MSK 0x200 2316 #define R_MCS_36M_DUAL_MSK 0x400 2317 #define R_MCS_48M_DUAL_MSK 0x800 2318 2319 #define RATE_MCS_CODE_MSK 0x7 2320 #define RATE_MCS_MIMO_POS 3 2321 #define RATE_MCS_MIMO_MSK 0x8 2322 #define RATE_MCS_HT_DUP_POS 5 2323 #define RATE_MCS_HT_DUP_MSK 0x20 2324 #define RATE_MCS_FLAGS_POS 8 2325 #define RATE_MCS_HT_POS 8 2326 #define RATE_MCS_HT_MSK 0x100 2327 #define RATE_MCS_CCK_POS 9 2328 #define RATE_MCS_CCK_MSK 0x200 2329 #define RATE_MCS_GF_POS 10 2330 #define RATE_MCS_GF_MSK 0x400 2331 2332 #define RATE_MCS_FAT_POS 11 2333 #define RATE_MCS_FAT_MSK 0x800 2334 #define RATE_MCS_DUP_POS 12 2335 #define RATE_MCS_DUP_MSK 0x1000 2336 #define RATE_MCS_SGI_POS 13 2337 #define RATE_MCS_SGI_MSK 0x2000 2338 2339 #define EEPROM_SEM_TIMEOUT 10 2340 #define EEPROM_SEM_RETRY_LIMIT 1000 2341 2342 /* 2343 * Antenna masks: 2344 * bit14:15 01 B inactive, A active 2345 * 10 B active, A inactive 2346 * 11 Both active 2347 */ 2348 #define RATE_MCS_ANT_A_POS 14 2349 #define RATE_MCS_ANT_B_POS 15 2350 #define RATE_MCS_ANT_A_MSK 0x4000 2351 #define RATE_MCS_ANT_B_MSK 0x8000 2352 #define RATE_MCS_ANT_AB_MSK 0xc000 2353 2354 #define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A)) 2355 #define is_siso(tbl) (((tbl) == LQ_SISO)) 2356 #define is_mimo(tbl) (((tbl) == LQ_MIMO)) 2357 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl)) 2358 #define is_a_band(tbl) (((tbl) == LQ_A)) 2359 #define is_g_and(tbl) (((tbl) == LQ_G)) 2360 2361 /* 2362 * RS_NEW_API: only TLC_RTS remains and moved to bit 0 2363 */ 2364 #define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1<<0) 2365 2366 #define LINK_QUAL_AC_NUM 4 2367 #define LINK_QUAL_MAX_RETRY_NUM 16 2368 2369 #define LINK_QUAL_ANT_A_MSK (1<<0) 2370 #define LINK_QUAL_ANT_B_MSK (1<<1) 2371 #define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK) 2372 2373 struct iwk_link_qual_general_params { 2374 uint8_t flags; 2375 uint8_t mimo_delimiter; 2376 uint8_t single_stream_ant_msk; 2377 uint8_t dual_stream_ant_msk; 2378 uint8_t start_rate_index[LINK_QUAL_AC_NUM]; 2379 }; 2380 2381 struct iwk_link_qual_agg_params { 2382 uint16_t agg_time_limit; 2383 uint8_t agg_dis_start_th; 2384 uint8_t agg_frame_cnt_limit; 2385 uint32_t reserved; 2386 }; 2387 2388 typedef struct iwk_link_quality_cmd { 2389 uint8_t sta_id; 2390 uint8_t reserved1; 2391 uint16_t control; 2392 struct iwk_link_qual_general_params general_params; 2393 struct iwk_link_qual_agg_params agg_params; 2394 uint32_t rate_n_flags[LINK_QUAL_MAX_RETRY_NUM]; 2395 uint32_t reserved2; 2396 } iwk_link_quality_cmd_t; 2397 2398 typedef struct iwk_rx_phy_res { 2399 uint8_t non_cfg_phy_cnt; /* non configurable DSP phy data byte count */ 2400 uint8_t cfg_phy_cnt; /* configurable DSP phy data byte count */ 2401 uint8_t stat_id; /* configurable DSP phy data set ID */ 2402 uint8_t reserved1; 2403 uint32_t timestampl; /* TSF at on air rise */ 2404 uint32_t timestamph; 2405 uint32_t beacon_time_stamp; /* beacon at on-air rise */ 2406 uint16_t phy_flags; /* general phy flags: band, modulation, ... */ 2407 uint16_t channel; /* channel number */ 2408 uint16_t non_cfg_phy[RX_RES_PHY_CNT]; /* upto 14 phy entries */ 2409 uint32_t reserved2; 2410 struct iwk_rate rate; /* rate in ucode internal format */ 2411 uint16_t byte_count; /* frame's byte-count */ 2412 uint16_t reserved3; 2413 } iwk_rx_phy_res_t; 2414 2415 struct iwk_rx_mpdu_res_start { 2416 uint16_t byte_count; 2417 uint16_t reserved; 2418 }; 2419 2420 #define IWK_AGC_DB_MASK (0x3f80) /* MASK(7,13) */ 2421 #define IWK_AGC_DB_POS (7) 2422 2423 /* 2424 * Fixed (non-configurable) rx data from phy 2425 */ 2426 struct iwk_rx_non_cfg_phy { 2427 uint16_t ant_selection; /* ant A bit 4, ant B bit 5, ant C bit 6 */ 2428 uint16_t agc_info; /* agc code 0:6, agc dB 7:13, reserved 14:15 */ 2429 uint8_t rssi_info[6]; /* we use even entries, 0/2/4 for A/B/C rssi */ 2430 uint8_t pad[2]; 2431 }; 2432 2433 /* 2434 * Byte Count Table Entry 2435 * 2436 * Bit fields: 2437 * 15-12: reserved 2438 * 11- 0: total to-be-transmitted byte count of frame (does not include command) 2439 */ 2440 struct iwk_queue_byte_cnt_entry { 2441 uint16_t val; 2442 }; 2443 2444 /* 2445 * Byte Count table 2446 * 2447 * Each Tx queue uses a byte-count table containing 320 entries: 2448 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that 2449 * duplicate the first 64 entries (to avoid wrap-around within a Tx window; 2450 * max Tx window is 64 TFDs). 2451 * 2452 * When driver sets up a new TFD, it must also enter the total byte count 2453 * of the frame to be transmitted into the corresponding entry in the byte 2454 * count table for the chosen Tx queue. If the TFD index is 0-63, the driver 2455 * must duplicate the byte count entry in corresponding index 256-319. 2456 * 2457 * "dont_care" padding puts each byte count table on a 1024-byte boundary; 2458 * 4965 assumes tables are separated by 1024 bytes. 2459 */ 2460 struct iwk_sched_queue_byte_cnt_tbl { 2461 struct iwk_queue_byte_cnt_entry tfd_offset[IWK_QUEUE_SIZE + 2462 IWK_MAX_WIN_SIZE]; 2463 uint8_t dont_care[1024 - (IWK_QUEUE_SIZE + IWK_MAX_WIN_SIZE) * 2464 sizeof (uint16_t)]; 2465 }; 2466 2467 /* 2468 * struct iwk_shared, handshake area for Tx and Rx 2469 * 2470 * For convenience in allocating memory, this structure combines 2 areas of 2471 * DRAM which must be shared between driver and 4965. These do not need to 2472 * be combined, if better allocation would result from keeping them separate: 2473 * TODO: Split these; carried over from 3945, doesn't work well for 4965. 2474 * 2475 * 1) The Tx byte count tables occupy 1024 bytes each (16 KBytes total for 2476 * 16 queues). Driver uses SCD_DRAM_BASE_ADDR to tell 4965 where to find 2477 * the first of these tables. 4965 assumes tables are 1024 bytes apart. 2478 * 2479 * 2) The Rx status (val0 and val1) occupies only 8 bytes. Driver uses 2480 * FH_RSCSR_CHNL0_STTS_WPTR_REG to tell 4965 where to find this area. 2481 * Driver reads val0 to determine the latest Receive Buffer Descriptor (RBD) 2482 * that has been filled by the 4965. 2483 * 2484 * Bit fields val0: 2485 * 31-12: Not used 2486 * 11- 0: Index of last filled Rx buffer descriptor (4965 writes, driver reads) 2487 * 2488 * Bit fields val1: 2489 * 31- 0: Not used 2490 */ 2491 typedef struct iwk_shared { 2492 struct iwk_sched_queue_byte_cnt_tbl 2493 queues_byte_cnt_tbls[IWK_NUM_QUEUES]; 2494 uint32_t val0; 2495 uint32_t val1; 2496 uint32_t padding1; /* so that allocation will be aligned to 16B */ 2497 uint32_t padding2; 2498 } iwk_shared_t; 2499 2500 2501 /* 2502 * struct iwk_tfd_frame_data 2503 * 2504 * Describes up to 2 buffers containing (contiguous) portions of a Tx frame. 2505 * Each buffer must be on dword boundary. 2506 * Up to 10 iwk_tfd_frame_data structures, describing up to 20 buffers, 2507 * may be filled within a TFD (iwk_tfd_frame). 2508 * 2509 * Bit fields in tb1_addr: 2510 * 31- 0: Tx buffer 1 address bits [31:0] 2511 * 2512 * Bit fields in val1: 2513 * 31-16: Tx buffer 2 address bits [15:0] 2514 * 15- 4: Tx buffer 1 length (bytes) 2515 * 3- 0: Tx buffer 1 address bits [32:32] 2516 * 2517 * Bit fields in val2: 2518 * 31-20: Tx buffer 2 length (bytes) 2519 * 19- 0: Tx buffer 2 address bits [35:16] 2520 */ 2521 struct iwk_tfd_frame_data { 2522 uint32_t tb1_addr; 2523 uint32_t val1; 2524 uint32_t val2; 2525 }; 2526 2527 typedef struct iwk_tx_desc { 2528 uint32_t val0; 2529 struct iwk_tfd_frame_data pa[10]; 2530 uint32_t reserved; 2531 } iwk_tx_desc_t; 2532 2533 typedef struct iwk_tx_stat { 2534 uint8_t frame_count; 2535 uint8_t bt_kill_count; 2536 uint8_t nrts; 2537 uint8_t ntries; 2538 struct iwk_rate rate; 2539 uint16_t duration; 2540 uint16_t reserved; 2541 uint32_t pa_power1; 2542 uint32_t pa_power2; 2543 uint32_t status; 2544 } iwk_tx_stat_t; 2545 2546 struct iwk_cmd_header { 2547 uint8_t type; 2548 uint8_t flags; 2549 uint8_t idx; 2550 uint8_t qid; 2551 }; 2552 2553 typedef struct iwk_rx_desc { 2554 uint32_t len; 2555 struct iwk_cmd_header hdr; 2556 } iwk_rx_desc_t; 2557 2558 typedef struct iwk_rx_stat { 2559 uint8_t len; 2560 uint8_t id; 2561 uint8_t rssi; /* received signal strength */ 2562 uint8_t agc; /* access gain control */ 2563 uint16_t signal; 2564 uint16_t noise; 2565 } iwk_rx_stat_t; 2566 2567 typedef struct iwk_rx_head { 2568 uint16_t chan; 2569 uint16_t flags; 2570 uint8_t reserved; 2571 uint8_t rate; 2572 uint16_t len; 2573 } iwk_rx_head_t; 2574 2575 typedef struct iwk_rx_tail { 2576 uint32_t flags; 2577 uint32_t timestampl; 2578 uint32_t timestamph; 2579 uint32_t tbeacon; 2580 } iwk_rx_tail_t; 2581 2582 enum { 2583 IWK_AP_ID = 0, 2584 IWK_MULTICAST_ID, 2585 IWK_STA_ID, 2586 IWK_BROADCAST_ID = 31, 2587 IWK_STATION_COUNT = 32, 2588 IWK_INVALID_STATION 2589 }; 2590 2591 /* 2592 * key flags 2593 */ 2594 enum { 2595 STA_KEY_FLG_ENCRYPT_MSK = 0x7, 2596 STA_KEY_FLG_NO_ENC = 0x0, 2597 STA_KEY_FLG_WEP = 0x1, 2598 STA_KEY_FLG_CCMP = 0x2, 2599 STA_KEY_FLG_TKIP = 0x3, 2600 2601 STA_KEY_FLG_KEYID_POS = 8, 2602 STA_KEY_FLG_INVALID = 0x0800, 2603 }; 2604 2605 /* 2606 * modify flags 2607 */ 2608 enum { 2609 STA_MODIFY_KEY_MASK = 0x01, 2610 STA_MODIFY_TID_DISABLE_TX = 0x02, 2611 STA_MODIFY_TX_RATE_MSK = 0x04 2612 }; 2613 2614 enum { 2615 RX_RES_STATUS_NO_CRC32_ERROR = (1 << 0), 2616 RX_RES_STATUS_NO_RXE_OVERFLOW = (1 << 1), 2617 }; 2618 2619 enum { 2620 RX_RES_PHY_FLAGS_BAND_24_MSK = (1 << 0), 2621 RX_RES_PHY_FLAGS_MOD_CCK_MSK = (1 << 1), 2622 RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK = (1 << 2), 2623 RX_RES_PHY_FLAGS_NARROW_BAND_MSK = (1 << 3), 2624 RX_RES_PHY_FLAGS_ANTENNA_MSK = 0xf0, 2625 2626 RX_RES_STATUS_SEC_TYPE_MSK = (0x7 << 8), 2627 RX_RES_STATUS_SEC_TYPE_NONE = (STA_KEY_FLG_NO_ENC << 8), 2628 RX_RES_STATUS_SEC_TYPE_WEP = (STA_KEY_FLG_WEP << 8), 2629 RX_RES_STATUS_SEC_TYPE_TKIP = (STA_KEY_FLG_TKIP << 8), 2630 RX_RES_STATUS_SEC_TYPE_CCMP = (STA_KEY_FLG_CCMP << 8), 2631 2632 RX_RES_STATUS_DECRYPT_TYPE_MSK = (0x3 << 11), 2633 RX_RES_STATUS_NOT_DECRYPT = (0x0 << 11), 2634 RX_RES_STATUS_DECRYPT_OK = (0x3 << 11), 2635 RX_RES_STATUS_BAD_ICV_MIC = (0x1 << 11), 2636 RX_RES_STATUS_BAD_KEY_TTAK = (0x2 << 11), 2637 }; 2638 2639 enum { 2640 REPLY_ALIVE = 0x1, 2641 REPLY_ERROR = 0x2, 2642 2643 /* RXON state commands */ 2644 REPLY_RXON = 0x10, 2645 REPLY_RXON_ASSOC = 0x11, 2646 REPLY_QOS_PARAM = 0x13, 2647 REPLY_RXON_TIMING = 0x14, 2648 2649 /* Multi-Station support */ 2650 REPLY_ADD_STA = 0x18, 2651 2652 /* RX, TX */ 2653 2654 REPLY_TX = 0x1c, 2655 2656 /* timers commands */ 2657 REPLY_BCON = 0x27, 2658 2659 REPLY_SHUTDOWN = 0x40, 2660 2661 /* MISC commands */ 2662 REPLY_RATE_SCALE = 0x47, 2663 REPLY_LEDS_CMD = 0x48, 2664 REPLY_TX_LINK_QUALITY_CMD = 0x4e, 2665 2666 /* 802.11h related */ 2667 RADAR_NOTIFICATION = 0x70, 2668 REPLY_QUIET_CMD = 0x71, 2669 REPLY_CHANNEL_SWITCH = 0x72, 2670 CHANNEL_SWITCH_NOTIFICATION = 0x73, 2671 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74, 2672 SPECTRUM_MEASURE_NOTIFICATION = 0x75, 2673 2674 /* Power Management *** */ 2675 POWER_TABLE_CMD = 0x77, 2676 PM_SLEEP_NOTIFICATION = 0x7A, 2677 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B, 2678 2679 /* Scan commands and notifications */ 2680 REPLY_SCAN_CMD = 0x80, 2681 REPLY_SCAN_ABORT_CMD = 0x81, 2682 2683 SCAN_START_NOTIFICATION = 0x82, 2684 SCAN_RESULTS_NOTIFICATION = 0x83, 2685 SCAN_COMPLETE_NOTIFICATION = 0x84, 2686 2687 /* IBSS/AP commands */ 2688 BEACON_NOTIFICATION = 0x90, 2689 REPLY_TX_BEACON = 0x91, 2690 WHO_IS_AWAKE_NOTIFICATION = 0x94, 2691 2692 QUIET_NOTIFICATION = 0x96, 2693 REPLY_TX_PWR_TABLE_CMD = 0x97, 2694 MEASURE_ABORT_NOTIFICATION = 0x99, 2695 2696 REPLY_CALIBRATION_TUNE = 0x9a, 2697 2698 /* BT config command */ 2699 REPLY_BT_CONFIG = 0x9b, 2700 REPLY_STATISTICS_CMD = 0x9c, 2701 STATISTICS_NOTIFICATION = 0x9d, 2702 2703 /* RF-KILL commands and notifications *** */ 2704 REPLY_CARD_STATE_CMD = 0xa0, 2705 CARD_STATE_NOTIFICATION = 0xa1, 2706 2707 /* Missed beacons notification */ 2708 MISSED_BEACONS_NOTIFICATION = 0xa2, 2709 MISSED_BEACONS_NOTIFICATION_TH_CMD = 0xa3, 2710 2711 REPLY_CT_KILL_CONFIG_CMD = 0xa4, 2712 SENSITIVITY_CMD = 0xa8, 2713 REPLY_PHY_CALIBRATION_CMD = 0xb0, 2714 REPLY_4965_RX = 0xc3, 2715 REPLY_RX_PHY_CMD = 0xc0, 2716 REPLY_RX_MPDU_CMD = 0xc1, 2717 REPLY_COMPRESSED_BA = 0xc5, 2718 REPLY_MAX = 0xff 2719 }; 2720 2721 typedef struct iwk_cmd { 2722 struct iwk_cmd_header hdr; 2723 uint8_t data[1024]; 2724 } iwk_cmd_t; 2725 2726 /* 2727 * Alive Command & Response 2728 */ 2729 #define UCODE_VALID_OK (0x1) 2730 #define INITIALIZE_SUBTYPE (9) 2731 2732 struct iwk_alive_resp { 2733 uint8_t ucode_minor; 2734 uint8_t ucode_major; 2735 uint16_t reserved1; 2736 uint8_t sw_rev[8]; 2737 uint8_t ver_type; 2738 uint8_t ver_subtype; 2739 uint16_t reserved2; 2740 uint32_t log_event_table_ptr; 2741 uint32_t error_event_table_ptr; 2742 uint32_t timestamp; 2743 uint32_t is_valid; 2744 }; 2745 2746 struct iwk_init_alive_resp { 2747 struct iwk_alive_resp s; 2748 /* calibration values from "initialize" uCode */ 2749 uint32_t voltage; /* signed */ 2750 uint32_t therm_r1[2]; /* signed 1st for normal, 2nd for FAT channel */ 2751 uint32_t therm_r2[2]; /* signed */ 2752 uint32_t therm_r3[2]; /* signed */ 2753 uint32_t therm_r4[2]; /* signed */ 2754 /* 2755 * signed MIMO gain comp, 5 freq groups, 2 Tx chains 2756 */ 2757 uint32_t tx_atten[5][2]; 2758 }; 2759 2760 /* 2761 * Rx config defines & structure 2762 */ 2763 /* 2764 * rx_config device types 2765 */ 2766 enum { 2767 RXON_DEV_TYPE_AP = 1, 2768 RXON_DEV_TYPE_ESS = 3, 2769 RXON_DEV_TYPE_IBSS = 4, 2770 RXON_DEV_TYPE_SNIFFER = 6, 2771 }; 2772 2773 /* 2774 * rx_config flags 2775 */ 2776 enum { 2777 /* band & modulation selection */ 2778 RXON_FLG_BAND_24G_MSK = (1 << 0), 2779 RXON_FLG_CCK_MSK = (1 << 1), 2780 /* auto detection enable */ 2781 RXON_FLG_AUTO_DETECT_MSK = (1 << 2), 2782 /* TGg protection when tx */ 2783 RXON_FLG_TGG_PROTECT_MSK = (1 << 3), 2784 /* cck short slot & preamble */ 2785 RXON_FLG_SHORT_SLOT_MSK = (1 << 4), 2786 RXON_FLG_SHORT_PREAMBLE_MSK = (1 << 5), 2787 /* antenna selection */ 2788 RXON_FLG_DIS_DIV_MSK = (1 << 7), 2789 RXON_FLG_ANT_SEL_MSK = 0x0f00, 2790 RXON_FLG_ANT_A_MSK = (1 << 8), 2791 RXON_FLG_ANT_B_MSK = (1 << 9), 2792 /* radar detection enable */ 2793 RXON_FLG_RADAR_DETECT_MSK = (1 << 12), 2794 RXON_FLG_TGJ_NARROW_BAND_MSK = (1 << 13), 2795 /* 2796 * rx response to host with 8-byte TSF 2797 * (according to ON_AIR deassertion) 2798 */ 2799 RXON_FLG_TSF2HOST_MSK = (1 << 15) 2800 }; 2801 2802 /* 2803 * rx_config filter flags 2804 */ 2805 enum { 2806 /* accept all data frames */ 2807 RXON_FILTER_PROMISC_MSK = (1 << 0), 2808 /* pass control & management to host */ 2809 RXON_FILTER_CTL2HOST_MSK = (1 << 1), 2810 /* accept multi-cast */ 2811 RXON_FILTER_ACCEPT_GRP_MSK = (1 << 2), 2812 /* don't decrypt uni-cast frames */ 2813 RXON_FILTER_DIS_DECRYPT_MSK = (1 << 3), 2814 /* don't decrypt multi-cast frames */ 2815 RXON_FILTER_DIS_GRP_DECRYPT_MSK = (1 << 4), 2816 /* STA is associated */ 2817 RXON_FILTER_ASSOC_MSK = (1 << 5), 2818 /* transfer to host non bssid beacons in associated state */ 2819 RXON_FILTER_BCON_AWARE_MSK = (1 << 6) 2820 }; 2821 2822 2823 /* 2824 * structure for RXON Command & Response 2825 */ 2826 typedef struct iwk_rxon_cmd { 2827 uint8_t node_addr[IEEE80211_ADDR_LEN]; 2828 uint16_t reserved1; 2829 uint8_t bssid[IEEE80211_ADDR_LEN]; 2830 uint16_t reserved2; 2831 uint8_t wlap_bssid[IEEE80211_ADDR_LEN]; 2832 uint16_t reserved3; 2833 uint8_t dev_type; 2834 uint8_t air_propagation; 2835 uint16_t rx_chain; 2836 uint8_t ofdm_basic_rates; 2837 uint8_t cck_basic_rates; 2838 uint16_t assoc_id; 2839 uint32_t flags; 2840 uint32_t filter_flags; 2841 uint16_t chan; 2842 uint8_t ofdm_ht_single_stream_basic_rates; 2843 uint8_t ofdm_ht_dual_stream_basic_rates; 2844 } iwk_rxon_cmd_t; 2845 2846 typedef struct iwk_compressed_ba_resp { 2847 uint32_t sta_addr_lo32; 2848 uint16_t sta_addr_hi16; 2849 uint16_t reserved; 2850 uint8_t sta_id; 2851 uint8_t tid; 2852 uint16_t ba_seq_ctl; 2853 uint32_t ba_bitmap0; 2854 uint32_t ba_bitmap1; 2855 uint16_t scd_flow; 2856 uint16_t scd_ssn; 2857 } iwk_compressed_ba_resp_t; 2858 2859 #define PHY_CALIBRATE_DIFF_GAIN_CMD (7) 2860 #define HD_TABLE_SIZE (11) 2861 2862 /* 2863 * Param table within SENSITIVITY_CMD 2864 */ 2865 #define HD_MIN_ENERGY_CCK_DET_INDEX (0) 2866 #define HD_MIN_ENERGY_OFDM_DET_INDEX (1) 2867 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2) 2868 #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3) 2869 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4) 2870 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5) 2871 #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6) 2872 #define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7) 2873 #define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8) 2874 #define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9) 2875 #define HD_OFDM_ENERGY_TH_IN_INDEX (10) 2876 2877 typedef struct iwk_sensitivity_cmd { 2878 uint16_t control; 2879 uint16_t table[HD_TABLE_SIZE]; 2880 } iwk_sensitivity_cmd_t; 2881 2882 typedef struct iwk_calibration_cmd { 2883 uint8_t opCode; 2884 uint8_t flags; 2885 uint16_t reserved; 2886 char *diff_gain_a; 2887 char *diff_gain_b; 2888 char *diff_gain_c; 2889 uint8_t reserved1; 2890 } iwk_calibation_cmd_t; 2891 2892 typedef struct iwk_missed_beacon_notif { 2893 uint32_t consequtive_missed_beacons; 2894 uint32_t total_missed_becons; 2895 uint32_t num_expected_beacons; 2896 uint32_t num_recvd_beacons; 2897 } iwk_missed_beacon_notif_t; 2898 2899 typedef struct iwk_ct_kill_config { 2900 uint32_t reserved; 2901 uint32_t critical_temperature_M; 2902 uint32_t critical_temperature_R; 2903 } iwk_ct_kill_config_t; 2904 2905 /* 2906 * structure for command IWK_CMD_ASSOCIATE 2907 */ 2908 typedef struct iwk_assoc { 2909 uint32_t flags; 2910 uint32_t filter; 2911 uint8_t ofdm_mask; 2912 uint8_t cck_mask; 2913 uint8_t ofdm_ht_single_stream_basic_rates; 2914 uint8_t ofdm_ht_dual_stream_basic_rates; 2915 uint16_t rx_chain_select_flags; 2916 uint16_t reserved; 2917 } iwk_assoc_t; 2918 2919 /* 2920 * structure for command IWK_CMD_SET_WME 2921 */ 2922 typedef struct iwk_wme_setup { 2923 uint32_t flags; 2924 struct { 2925 uint16_t cwmin; 2926 uint16_t cwmax; 2927 uint8_t aifsn; 2928 uint8_t reserved; 2929 uint16_t txop; 2930 } ac[WME_NUM_AC]; 2931 } iwk_wme_setup_t; 2932 2933 /* 2934 * structure for command IWK_CMD_TSF 2935 */ 2936 typedef struct iwk_cmd_tsf { 2937 uint32_t timestampl; 2938 uint32_t timestamph; 2939 uint16_t bintval; 2940 uint16_t atim; 2941 uint32_t binitval; 2942 uint16_t lintval; 2943 uint16_t reserved; 2944 } iwk_cmd_tsf_t; 2945 2946 /* 2947 * structure for IWK_CMD_ADD_NODE 2948 */ 2949 typedef struct iwk_add_sta { 2950 uint8_t control; 2951 uint8_t reserved1[3]; 2952 uint8_t bssid[IEEE80211_ADDR_LEN]; 2953 uint16_t reserved2; 2954 uint8_t id; 2955 uint8_t sta_mask; 2956 uint16_t reserved3; 2957 uint16_t key_flags; 2958 uint8_t tkip; 2959 uint8_t reserved4; 2960 uint16_t ttak[5]; 2961 uint8_t keyp; 2962 uint8_t reserved5; 2963 uint8_t key[16]; 2964 uint32_t flags; 2965 uint32_t mask; 2966 uint16_t tid; 2967 union { 2968 struct { 2969 uint8_t rate; 2970 uint8_t flags; 2971 } s; 2972 uint16_t rate_n_flags; 2973 } tx_rate; 2974 uint8_t add_imm; 2975 uint8_t del_imm; 2976 uint16_t add_imm_start; 2977 uint32_t reserved7; 2978 } iwk_add_sta_t; 2979 2980 /* 2981 * Tx flags 2982 */ 2983 enum { 2984 TX_CMD_FLG_RTS_MSK = (1 << 1), 2985 TX_CMD_FLG_CTS_MSK = (1 << 2), 2986 TX_CMD_FLG_ACK_MSK = (1 << 3), 2987 TX_CMD_FLG_STA_RATE_MSK = (1 << 4), 2988 TX_CMD_FLG_IMM_BA_RSP_MASK = (1 << 6), 2989 TX_CMD_FLG_FULL_TXOP_PROT_MSK = (1 << 7), 2990 TX_CMD_FLG_ANT_SEL_MSK = 0xf00, 2991 TX_CMD_FLG_ANT_A_MSK = (1 << 8), 2992 TX_CMD_FLG_ANT_B_MSK = (1 << 9), 2993 2994 /* ucode ignores BT priority for this frame */ 2995 TX_CMD_FLG_BT_DIS_MSK = (1 << 12), 2996 2997 /* ucode overrides sequence control */ 2998 TX_CMD_FLG_SEQ_CTL_MSK = (1 << 13), 2999 3000 /* signal that this frame is non-last MPDU */ 3001 TX_CMD_FLG_MORE_FRAG_MSK = (1 << 14), 3002 3003 /* calculate TSF in outgoing frame */ 3004 TX_CMD_FLG_TSF_MSK = (1 << 16), 3005 3006 /* activate TX calibration. */ 3007 TX_CMD_FLG_CALIB_MSK = (1 << 17), 3008 3009 /* 3010 * signals that 2 bytes pad was inserted 3011 * after the MAC header 3012 */ 3013 TX_CMD_FLG_MH_PAD_MSK = (1 << 20), 3014 3015 /* HCCA-AP - disable duration overwriting. */ 3016 TX_CMD_FLG_DUR_MSK = (1 << 25), 3017 }; 3018 3019 /* 3020 * TX command security control 3021 */ 3022 #define TX_CMD_SEC_CCM 0x2 3023 #define TX_CMD_SEC_TKIP 0x3 3024 3025 /* 3026 * structure for command IWK_CMD_TX_DATA 3027 */ 3028 typedef struct iwk_tx_cmd { 3029 uint16_t len; 3030 uint16_t next_frame_len; 3031 uint32_t tx_flags; 3032 struct iwk_dram_scratch scratch; 3033 struct iwk_rate rate; 3034 uint8_t sta_id; 3035 uint8_t sec_ctl; 3036 uint8_t initial_rate_index; 3037 uint8_t reserved; 3038 uint8_t key[16]; 3039 uint16_t next_frame_flags; 3040 uint16_t reserved2; 3041 union { 3042 uint32_t life_time; 3043 uint32_t attempt; 3044 } stop_time; 3045 uint32_t dram_lsb_ptr; 3046 uint8_t dram_msb_ptr; 3047 uint8_t rts_retry_limit; 3048 uint8_t data_retry_limit; 3049 uint8_t tid_tspec; 3050 union { 3051 uint16_t pm_frame_timeout; 3052 uint16_t attempt_duration; 3053 } timeout; 3054 uint16_t driver_txop; 3055 } iwk_tx_cmd_t; 3056 3057 /* 3058 * LEDs Command & Response 3059 * REPLY_LEDS_CMD = 0x48 (command, has simple generic response) 3060 * 3061 * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field), 3062 * this command turns it on or off, or sets up a periodic blinking cycle. 3063 */ 3064 typedef struct iwk_led_cmd { 3065 uint32_t interval; /* "interval" in uSec */ 3066 uint8_t id; /* 1: Activity, 2: Link, 3: Tech */ 3067 /* 3068 * # intervals off while blinking; 3069 * "0", with > 0 "on" value, turns LED on 3070 */ 3071 uint8_t off; 3072 /* 3073 * # intervals on while blinking; 3074 * "0", regardless of "off", turns LED off 3075 */ 3076 uint8_t on; 3077 uint8_t reserved; 3078 } iwk_led_cmd_t; 3079 3080 /* 3081 * structure for IWK_CMD_SET_POWER_MODE 3082 */ 3083 typedef struct iwk_powertable_cmd { 3084 uint16_t flags; 3085 uint8_t keep_alive_seconds; 3086 uint8_t debug_flags; 3087 uint32_t rx_timeout; 3088 uint32_t tx_timeout; 3089 uint32_t sleep[5]; 3090 uint32_t keep_alive_beacons; 3091 } iwk_powertable_cmd_t; 3092 3093 struct iwk_ssid_ie { 3094 uint8_t id; 3095 uint8_t len; 3096 uint8_t ssid[32]; 3097 }; 3098 /* 3099 * structure for command IWK_CMD_SCAN 3100 */ 3101 typedef struct iwk_scan_hdr { 3102 uint16_t len; 3103 uint8_t reserved1; 3104 uint8_t nchan; 3105 /* 3106 * dwell only this long on quiet chnl 3107 * (active scan) 3108 */ 3109 uint16_t quiet_time; 3110 uint16_t quiet_plcp_th; /* quiet chnl is < this # pkts (typ. 1) */ 3111 uint16_t good_crc_th; /* passive -> active promotion threshold */ 3112 uint16_t rx_chain; 3113 /* 3114 * max usec to be out of associated (service) 3115 * chnl 3116 */ 3117 uint32_t max_out_time; 3118 /* 3119 * pause scan this long when returning to svc 3120 * chnl. 3121 * 3945 -- 31:24 # beacons, 19:0 additional usec, 3122 * 4965 -- 31:22 # beacons, 21:0 additional usec. 3123 */ 3124 uint32_t suspend_time; 3125 uint32_t flags; 3126 uint32_t filter_flags; 3127 struct iwk_tx_cmd tx_cmd; 3128 struct iwk_ssid_ie direct_scan[4]; 3129 /* followed by probe request body */ 3130 /* followed by nchan x iwk_scan_chan */ 3131 } iwk_scan_hdr_t; 3132 3133 typedef struct iwk_scan_chan { 3134 uint8_t type; 3135 uint8_t chan; 3136 struct iwk_tx_power tpc; 3137 uint16_t active_dwell; /* dwell time */ 3138 uint16_t passive_dwell; /* dwell time */ 3139 } iwk_scan_chan_t; 3140 3141 /* 3142 * structure for IWK_CMD_BLUETOOTH 3143 */ 3144 typedef struct iwk_bt_cmd { 3145 uint8_t flags; 3146 uint8_t lead_time; 3147 uint8_t max_kill; 3148 uint8_t reserved; 3149 uint32_t kill_ack_mask; 3150 uint32_t kill_cts_mask; 3151 } iwk_bt_cmd_t; 3152 3153 /* 3154 * firmware image header 3155 */ 3156 typedef struct iwk_firmware_hdr { 3157 uint32_t version; 3158 uint32_t textsz; 3159 uint32_t datasz; 3160 uint32_t init_textsz; 3161 uint32_t init_datasz; 3162 uint32_t bootsz; 3163 } iwk_firmware_hdr_t; 3164 3165 /* 3166 * structure for IWK_START_SCAN notification 3167 */ 3168 typedef struct iwk_start_scan { 3169 uint32_t timestampl; 3170 uint32_t timestamph; 3171 uint32_t tbeacon; 3172 uint8_t chan; 3173 uint8_t band; 3174 uint16_t reserved; 3175 uint32_t status; 3176 } iwk_start_scan_t; 3177 3178 3179 #define IWK_READ(sc, reg) \ 3180 ddi_get32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg))) 3181 3182 #define IWK_WRITE(sc, reg, val) \ 3183 ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val)) 3184 3185 #ifdef __cplusplus 3186 } 3187 #endif 3188 3189 #endif /* _IWK_HW_H_ */ 3190