1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2024 Oxide Computer Company 14 */ 15 16 #ifndef _IGC_OSDEP_H 17 #define _IGC_OSDEP_H 18 19 /* 20 * Definitions that are required for the igc core code. 21 */ 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* 28 * The common code requires the following headers. 29 */ 30 #include <sys/stdbool.h> 31 #include <sys/sunddi.h> 32 33 /* 34 * It requires the following due to what we have declared. 35 */ 36 #include <sys/types.h> 37 #include <sys/ddi.h> 38 #include <sys/bitext.h> 39 40 /* 41 * We redeclare the forward struct igc_hw here because this is required to be 42 * included for igc_hw.h. 43 */ 44 struct igc_hw; 45 46 /* 47 * The following typedefs allow for the types in the core code to be defined in 48 * terms of types that we actually use. 49 */ 50 typedef uint8_t u8; 51 typedef uint16_t u16; 52 typedef uint32_t u32; 53 typedef uint64_t u64; 54 typedef int32_t s32; 55 typedef uint16_t __le16; 56 typedef uint32_t __le32; 57 typedef uint64_t __le64; 58 59 /* 60 * Register read and write APIs. While these are in all caps because they are 61 * conventionally macros, we implement them as functions in igc_osdep.c. 62 */ 63 extern uint32_t IGC_READ_REG(struct igc_hw *, uint32_t); 64 extern void IGC_WRITE_REG(struct igc_hw *, uint32_t, uint32_t); 65 extern void IGC_WRITE_REG_ARRAY(struct igc_hw *, uint32_t, uint32_t, uint32_t); 66 67 /* 68 * This is the implementation of a flush command which forces certain PCIe 69 * transaction ordering to complete. 70 */ 71 #define IGC_WRITE_FLUSH(hw) IGC_READ_REG(hw, IGC_STATUS) 72 73 /* 74 * Delay variants. The semantics in the common code and Linux use non-sleeping 75 * delay variants. It's not really clear that we should be spinning for 76 * miliseconds, but for now, that's what we end up doing. 77 */ 78 #define usec_delay(x) drv_usecwait(x) 79 #define usec_delay_irq(x) drv_usecwait(x) 80 #define msec_delay(x) drv_usecwait((x) * 1000) 81 #define msec_delay_irq(x) drv_usecwait((x) * 1000) 82 83 /* 84 * Debugging macros that the common code expects to exist. Because of how these 85 * are used, we need to define something lest we generate empty body warnings. 86 */ 87 extern void igc_core_log(struct igc_hw *, const char *, ...); 88 #define DEBUGOUT(str) igc_core_log(hw, str) 89 #define DEBUGOUT1(str, d1) igc_core_log(hw, str, d1) 90 #define DEBUGOUT2(str, d1, d2) igc_core_log(hw, str, d1, d2) 91 #define DEBUGFUNC(str) igc_core_log(hw, str) 92 93 /* 94 * The following defines registers or register values that should be defined by 95 * the core code, but are not right now. As such, we define them here to 96 * minimize the diffs that are required in the core code. 97 */ 98 99 /* 100 * Used in the IGC_EECD register to indicate that a flash device is present. 101 */ 102 #define IGC_EECD_EE_DET (1 << 19) 103 104 /* 105 * Starting positions of the IVAR queue regions. 106 */ 107 #define IGC_IVAR_RX0_START 0 108 #define IGC_IVAR_TX0_START 8 109 #define IGC_IVAR_RX1_START 16 110 #define IGC_IVAR_TX1_START 24 111 #define IGC_IVAR_ENT_LEN 8 112 113 /* 114 * The I225 has the exact same LED controls that the other parts have. There are 115 * three LEDs defined in the IC which are initialized by firmware and controlled 116 * through the classic LEDCTL register just like igb/e1000g. While the register 117 * is in igc_regs.h, the actual values for the modes in igc_defines.h do not 118 * match the I225 Ethernet Controller Datasheet. They match older parts without 119 * 2.5 GbE support. See I225/6 Datasheet v2.6.7 Section 3.4 'Configurable LED 120 * Outputs'. 121 */ 122 typedef enum { 123 I225_LED_M_ON = 0, 124 I225_LED_M_OFF, 125 I225_LED_M_LINK_UP, 126 I225_LED_M_FILTER_ACT, 127 I225_LED_M_LINK_ACT, 128 I225_LED_M_LINK_10, 129 I225_LED_M_LINK_100, 130 I225_LED_M_LINK_1000, 131 I225_LED_M_LINK_2500, 132 I225_LED_M_SDP, 133 I225_LED_M_PAUSE, 134 I225_LED_M_ACT, 135 I225_LED_M_LINK_10_100, 136 I225_LED_M_LINK_100_1000, 137 I225_LED_M_LINK_1000_2500, 138 I225_LED_M_LINK_100_2500, 139 } i225_led_mode_t; 140 141 /* 142 * The LED registers are organized into three groups that repeat. Register 143 * manipulation functions are defined in igc.c. The following are constants for 144 * the various registers. 145 */ 146 #define IGC_I225_NLEDS 3 147 #define IGC_LEDCTL_GLOB_BLINK_200MS 0 148 #define IGC_LEDCTL_GLOB_BLINK_83MS 1 149 150 /* 151 * IEEE MMD Status register 7.33 access. These definitions are done in the style 152 * of igc_defines.h, where this phy is missing. We should eventually update the 153 * mii layer headers to know about this. See IEEE Table 45-386 'MultiGBASE-T AN 154 * status 1 register'. 155 */ 156 #define ANEG_MULTIGBT_AN_STS1 0x0021 /* MULTI GBT Status 1 register */ 157 #define MMD_AN_STS1_LP_40T_FRT (1 << 0) 158 #define MMD_AN_STS1_LP_10T_FRT (1 << 1) 159 #define MMD_AN_STS1_LP_25T_FRT (1 << 2) 160 #define MMD_AN_STS1_LP_2P5T_FRT (1 << 3) 161 #define MMD_AN_STS1_LP_5T_FRT (1 << 4) 162 #define MMD_AN_STS1_LP_2P5T_CAP (1 << 5) 163 #define MMD_AN_STS1_LP_5T_CAP (1 << 6) 164 #define MMD_AN_STS1_LP_25T_CAP (1 << 7) 165 #define MMD_AN_STS1_LP_40T_CAP (1 << 8) 166 #define MMD_AN_STS1_LP_10T_PMA (1 << 9) 167 #define MMD_AN_STS1_LP_LOOP_TIME (1 << 10) 168 #define MMD_AN_STS1_LP_10T_CAP (1 << 11) 169 #define MMD_AN_STS1_LP_REM_STS (1 << 12) 170 #define MMD_AN_STS1_LP_LOC_STS (1 << 13) 171 #define MMD_AN_STS1_LP_MSC_RES (1 << 14) 172 #define MMD_AN_STS1_LP_MSC_FLT (1 << 15) 173 174 /* 175 * Reserved bits in the RXDCTL register that must be preserved. The I210 176 * datasheet indicates that it leverages bits 24:21 and then 31:27. There are 177 * other reserved portions by they are explicitly write 0. 178 */ 179 #define IGC_RXDCTL_PRESERVE 0xf9e00000 180 181 /* 182 * Missing setters for the various prefetch, host, and write-back thresholds. 183 */ 184 #define IGC_RXDCTL_SET_PTHRESH(r, v) bitset32(r, 4, 0, v) 185 #define IGC_RXDCTL_SET_HTHRESH(r, v) bitset32(r, 12, 8, v) 186 #define IGC_RXDCTL_SET_WTHRESH(r, v) bitset32(r, 20, 16, v) 187 188 /* 189 * Missing setters for the tx varaint. We assume that this uses the shorter I210 190 * 5-bit range as opposed to the I217 6-bit range. Given we don't set anything 191 * much higher than this, this is the best we can do. In general this is more 192 * I210-like than I217-like. 193 */ 194 #define IGC_TXDCTL_SET_PTHRESH(r, v) bitset32(r, 4, 0, v) 195 #define IGC_TXDCTL_SET_HTHRESH(r, v) bitset32(r, 13, 8, v) 196 #define IGC_TXDCTL_SET_WTHRESH(r, v) bitset32(r, 20, 16, v) 197 198 #ifdef __cplusplus 199 } 200 #endif 201 202 #endif /* _IGC_OSDEP_H */ 203