1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include "igc_api.h" 8 9 static s32 igc_init_nvm_params_i225(struct igc_hw *hw); 10 static s32 igc_init_mac_params_i225(struct igc_hw *hw); 11 static s32 igc_init_phy_params_i225(struct igc_hw *hw); 12 static s32 igc_reset_hw_i225(struct igc_hw *hw); 13 static s32 igc_acquire_nvm_i225(struct igc_hw *hw); 14 static void igc_release_nvm_i225(struct igc_hw *hw); 15 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw); 16 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words, 17 u16 *data); 18 static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw); 19 20 /** 21 * igc_init_nvm_params_i225 - Init NVM func ptrs. 22 * @hw: pointer to the HW structure 23 **/ 24 static s32 igc_init_nvm_params_i225(struct igc_hw *hw) 25 { 26 struct igc_nvm_info *nvm = &hw->nvm; 27 u32 eecd = IGC_READ_REG(hw, IGC_EECD); 28 u16 size; 29 30 DEBUGFUNC("igc_init_nvm_params_i225"); 31 32 size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >> 33 IGC_EECD_SIZE_EX_SHIFT); 34 /* 35 * Added to a constant, "size" becomes the left-shift value 36 * for setting word_size. 37 */ 38 size += NVM_WORD_SIZE_BASE_SHIFT; 39 40 /* Just in case size is out of range, cap it to the largest 41 * EEPROM size supported 42 */ 43 if (size > 15) 44 size = 15; 45 46 nvm->word_size = 1 << size; 47 nvm->opcode_bits = 8; 48 nvm->delay_usec = 1; 49 nvm->type = igc_nvm_eeprom_spi; 50 51 52 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 53 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 54 16 : 8; 55 56 if (nvm->word_size == (1 << 15)) 57 nvm->page_size = 128; 58 59 nvm->ops.acquire = igc_acquire_nvm_i225; 60 nvm->ops.release = igc_release_nvm_i225; 61 if (igc_get_flash_presence_i225(hw)) { 62 hw->nvm.type = igc_nvm_flash_hw; 63 nvm->ops.read = igc_read_nvm_srrd_i225; 64 nvm->ops.write = igc_write_nvm_srwr_i225; 65 nvm->ops.validate = igc_validate_nvm_checksum_i225; 66 nvm->ops.update = igc_update_nvm_checksum_i225; 67 } else { 68 hw->nvm.type = igc_nvm_invm; 69 nvm->ops.write = igc_null_write_nvm; 70 nvm->ops.validate = igc_null_ops_generic; 71 nvm->ops.update = igc_null_ops_generic; 72 } 73 74 return IGC_SUCCESS; 75 } 76 77 /** 78 * igc_init_mac_params_i225 - Init MAC func ptrs. 79 * @hw: pointer to the HW structure 80 **/ 81 static s32 igc_init_mac_params_i225(struct igc_hw *hw) 82 { 83 struct igc_mac_info *mac = &hw->mac; 84 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225; 85 86 DEBUGFUNC("igc_init_mac_params_i225"); 87 88 /* Initialize function pointer */ 89 igc_init_mac_ops_generic(hw); 90 91 /* Set media type */ 92 hw->phy.media_type = igc_media_type_copper; 93 /* Set mta register count */ 94 mac->mta_reg_count = 128; 95 /* Set rar entry count */ 96 mac->rar_entry_count = IGC_RAR_ENTRIES_BASE; 97 98 /* reset */ 99 mac->ops.reset_hw = igc_reset_hw_i225; 100 /* hw initialization */ 101 mac->ops.init_hw = igc_init_hw_i225; 102 /* link setup */ 103 mac->ops.setup_link = igc_setup_link_generic; 104 /* check for link */ 105 mac->ops.check_for_link = igc_check_for_link_i225; 106 /* link info */ 107 mac->ops.get_link_up_info = igc_get_speed_and_duplex_copper_generic; 108 /* acquire SW_FW sync */ 109 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225; 110 /* release SW_FW sync */ 111 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225; 112 113 /* Allow a single clear of the SW semaphore on I225 */ 114 dev_spec->clear_semaphore_once = true; 115 mac->ops.setup_physical_interface = igc_setup_copper_link_i225; 116 117 /* Set if part includes ASF firmware */ 118 mac->asf_firmware_present = true; 119 120 /* multicast address update */ 121 mac->ops.update_mc_addr_list = igc_update_mc_addr_list_generic; 122 123 mac->ops.write_vfta = igc_write_vfta_generic; 124 125 return IGC_SUCCESS; 126 } 127 128 /** 129 * igc_init_phy_params_i225 - Init PHY func ptrs. 130 * @hw: pointer to the HW structure 131 **/ 132 static s32 igc_init_phy_params_i225(struct igc_hw *hw) 133 { 134 struct igc_phy_info *phy = &hw->phy; 135 s32 ret_val = IGC_SUCCESS; 136 137 DEBUGFUNC("igc_init_phy_params_i225"); 138 139 140 if (hw->phy.media_type != igc_media_type_copper) { 141 phy->type = igc_phy_none; 142 goto out; 143 } 144 145 phy->ops.power_up = igc_power_up_phy_copper; 146 phy->ops.power_down = igc_power_down_phy_copper_base; 147 148 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500; 149 150 phy->reset_delay_us = 100; 151 152 phy->ops.acquire = igc_acquire_phy_base; 153 phy->ops.check_reset_block = igc_check_reset_block_generic; 154 phy->ops.release = igc_release_phy_base; 155 phy->ops.reset = igc_phy_hw_reset_generic; 156 phy->ops.read_reg = igc_read_phy_reg_gpy; 157 phy->ops.write_reg = igc_write_phy_reg_gpy; 158 159 /* Make sure the PHY is in a good state. Several people have reported 160 * firmware leaving the PHY's page select register set to something 161 * other than the default of zero, which causes the PHY ID read to 162 * access something other than the intended register. 163 */ 164 ret_val = hw->phy.ops.reset(hw); 165 if (ret_val) 166 goto out; 167 168 ret_val = igc_get_phy_id(hw); 169 phy->type = igc_phy_i225; 170 171 out: 172 return ret_val; 173 } 174 175 /** 176 * igc_reset_hw_i225 - Reset hardware 177 * @hw: pointer to the HW structure 178 * 179 * This resets the hardware into a known state. 180 **/ 181 static s32 igc_reset_hw_i225(struct igc_hw *hw) 182 { 183 u32 ctrl; 184 s32 ret_val; 185 186 DEBUGFUNC("igc_reset_hw_i225"); 187 188 /* 189 * Prevent the PCI-E bus from sticking if there is no TLP connection 190 * on the last TLP read/write transaction when MAC is reset. 191 */ 192 ret_val = igc_disable_pcie_master_generic(hw); 193 if (ret_val) 194 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 195 196 DEBUGOUT("Masking off all interrupts\n"); 197 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 198 199 IGC_WRITE_REG(hw, IGC_RCTL, 0); 200 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP); 201 IGC_WRITE_FLUSH(hw); 202 203 msec_delay(10); 204 205 ctrl = IGC_READ_REG(hw, IGC_CTRL); 206 207 DEBUGOUT("Issuing a global reset to MAC\n"); 208 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); 209 210 ret_val = igc_get_auto_rd_done_generic(hw); 211 if (ret_val) { 212 /* 213 * When auto config read does not complete, do not 214 * return with an error. This can happen in situations 215 * where there is no eeprom and prevents getting link. 216 */ 217 DEBUGOUT("Auto Read Done did not complete\n"); 218 } 219 220 /* Clear any pending interrupt events. */ 221 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 222 IGC_READ_REG(hw, IGC_ICR); 223 224 /* Install any alternate MAC address into RAR0 */ 225 ret_val = igc_check_alt_mac_addr_generic(hw); 226 227 return ret_val; 228 } 229 230 /* igc_acquire_nvm_i225 - Request for access to EEPROM 231 * @hw: pointer to the HW structure 232 * 233 * Acquire the necessary semaphores for exclusive access to the EEPROM. 234 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 235 * Return successful if access grant bit set, else clear the request for 236 * EEPROM access and return -IGC_ERR_NVM (-1). 237 */ 238 static s32 igc_acquire_nvm_i225(struct igc_hw *hw) 239 { 240 s32 ret_val; 241 242 DEBUGFUNC("igc_acquire_nvm_i225"); 243 244 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); 245 246 return ret_val; 247 } 248 249 /* igc_release_nvm_i225 - Release exclusive access to EEPROM 250 * @hw: pointer to the HW structure 251 * 252 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 253 * then release the semaphores acquired. 254 */ 255 static void igc_release_nvm_i225(struct igc_hw *hw) 256 { 257 DEBUGFUNC("igc_release_nvm_i225"); 258 259 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); 260 } 261 262 /* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore 263 * @hw: pointer to the HW structure 264 * @mask: specifies which semaphore to acquire 265 * 266 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 267 * will also specify which port we're acquiring the lock for. 268 */ 269 s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask) 270 { 271 u32 swfw_sync; 272 u32 swmask = mask; 273 u32 fwmask = mask << 16; 274 s32 ret_val = IGC_SUCCESS; 275 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 276 277 DEBUGFUNC("igc_acquire_swfw_sync_i225"); 278 279 while (i < timeout) { 280 if (igc_get_hw_semaphore_i225(hw)) { 281 ret_val = -IGC_ERR_SWFW_SYNC; 282 goto out; 283 } 284 285 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); 286 if (!(swfw_sync & (fwmask | swmask))) 287 break; 288 289 /* Firmware currently using resource (fwmask) 290 * or other software thread using resource (swmask) 291 */ 292 igc_put_hw_semaphore_generic(hw); 293 msec_delay_irq(5); 294 i++; 295 } 296 297 if (i == timeout) { 298 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 299 ret_val = -IGC_ERR_SWFW_SYNC; 300 goto out; 301 } 302 303 swfw_sync |= swmask; 304 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); 305 306 igc_put_hw_semaphore_generic(hw); 307 308 out: 309 return ret_val; 310 } 311 312 /* igc_release_swfw_sync_i225 - Release SW/FW semaphore 313 * @hw: pointer to the HW structure 314 * @mask: specifies which semaphore to acquire 315 * 316 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 317 * will also specify which port we're releasing the lock for. 318 */ 319 void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask) 320 { 321 u32 swfw_sync; 322 323 DEBUGFUNC("igc_release_swfw_sync_i225"); 324 325 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS) 326 ; /* Empty */ 327 328 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); 329 swfw_sync &= ~mask; 330 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); 331 332 igc_put_hw_semaphore_generic(hw); 333 } 334 335 /* 336 * igc_setup_copper_link_i225 - Configure copper link settings 337 * @hw: pointer to the HW structure 338 * 339 * Configures the link for auto-neg or forced speed and duplex. Then we check 340 * for link, once link is established calls to configure collision distance 341 * and flow control are called. 342 */ 343 s32 igc_setup_copper_link_i225(struct igc_hw *hw) 344 { 345 u32 phpm_reg; 346 s32 ret_val; 347 u32 ctrl; 348 349 DEBUGFUNC("igc_setup_copper_link_i225"); 350 351 ctrl = IGC_READ_REG(hw, IGC_CTRL); 352 ctrl |= IGC_CTRL_SLU; 353 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); 354 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 355 356 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM); 357 phpm_reg &= ~IGC_I225_PHPM_GO_LINKD; 358 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg); 359 360 ret_val = igc_setup_copper_link_generic(hw); 361 362 return ret_val; 363 } 364 365 /* igc_get_hw_semaphore_i225 - Acquire hardware semaphore 366 * @hw: pointer to the HW structure 367 * 368 * Acquire the HW semaphore to access the PHY or NVM 369 */ 370 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw) 371 { 372 u32 swsm; 373 s32 timeout = hw->nvm.word_size + 1; 374 s32 i = 0; 375 376 DEBUGFUNC("igc_get_hw_semaphore_i225"); 377 378 /* Get the SW semaphore */ 379 while (i < timeout) { 380 swsm = IGC_READ_REG(hw, IGC_SWSM); 381 if (!(swsm & IGC_SWSM_SMBI)) 382 break; 383 384 usec_delay(50); 385 i++; 386 } 387 388 if (i == timeout) { 389 /* In rare circumstances, the SW semaphore may already be held 390 * unintentionally. Clear the semaphore once before giving up. 391 */ 392 if (hw->dev_spec._i225.clear_semaphore_once) { 393 hw->dev_spec._i225.clear_semaphore_once = false; 394 igc_put_hw_semaphore_generic(hw); 395 for (i = 0; i < timeout; i++) { 396 swsm = IGC_READ_REG(hw, IGC_SWSM); 397 if (!(swsm & IGC_SWSM_SMBI)) 398 break; 399 400 usec_delay(50); 401 } 402 } 403 404 /* If we do not have the semaphore here, we have to give up. */ 405 if (i == timeout) { 406 DEBUGOUT("Driver can't access device -\n"); 407 DEBUGOUT("SMBI bit is set.\n"); 408 return -IGC_ERR_NVM; 409 } 410 } 411 412 /* Get the FW semaphore. */ 413 for (i = 0; i < timeout; i++) { 414 swsm = IGC_READ_REG(hw, IGC_SWSM); 415 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); 416 417 /* Semaphore acquired if bit latched */ 418 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) 419 break; 420 421 usec_delay(50); 422 } 423 424 if (i == timeout) { 425 /* Release semaphores */ 426 igc_put_hw_semaphore_generic(hw); 427 DEBUGOUT("Driver can't access the NVM\n"); 428 return -IGC_ERR_NVM; 429 } 430 431 return IGC_SUCCESS; 432 } 433 434 /* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register 435 * @hw: pointer to the HW structure 436 * @offset: offset of word in the Shadow Ram to read 437 * @words: number of words to read 438 * @data: word read from the Shadow Ram 439 * 440 * Reads a 16 bit word from the Shadow Ram using the EERD register. 441 * Uses necessary synchronization semaphores. 442 */ 443 s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words, 444 u16 *data) 445 { 446 s32 status = IGC_SUCCESS; 447 u16 i, count; 448 449 DEBUGFUNC("igc_read_nvm_srrd_i225"); 450 451 /* We cannot hold synchronization semaphores for too long, 452 * because of forceful takeover procedure. However it is more efficient 453 * to read in bursts than synchronizing access for each word. 454 */ 455 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { 456 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? 457 IGC_EERD_EEWR_MAX_COUNT : (words - i); 458 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 459 status = igc_read_nvm_eerd(hw, offset, count, 460 data + i); 461 hw->nvm.ops.release(hw); 462 } else { 463 status = IGC_ERR_SWFW_SYNC; 464 } 465 466 if (status != IGC_SUCCESS) 467 break; 468 } 469 470 return status; 471 } 472 473 /* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR 474 * @hw: pointer to the HW structure 475 * @offset: offset within the Shadow RAM to be written to 476 * @words: number of words to write 477 * @data: 16 bit word(s) to be written to the Shadow RAM 478 * 479 * Writes data to Shadow RAM at offset using EEWR register. 480 * 481 * If igc_update_nvm_checksum is not called after this function , the 482 * data will not be committed to FLASH and also Shadow RAM will most likely 483 * contain an invalid checksum. 484 * 485 * If error code is returned, data and Shadow RAM may be inconsistent - buffer 486 * partially written. 487 */ 488 s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words, 489 u16 *data) 490 { 491 s32 status = IGC_SUCCESS; 492 u16 i, count; 493 494 DEBUGFUNC("igc_write_nvm_srwr_i225"); 495 496 /* We cannot hold synchronization semaphores for too long, 497 * because of forceful takeover procedure. However it is more efficient 498 * to write in bursts than synchronizing access for each word. 499 */ 500 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { 501 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? 502 IGC_EERD_EEWR_MAX_COUNT : (words - i); 503 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 504 status = __igc_write_nvm_srwr(hw, offset, count, 505 data + i); 506 hw->nvm.ops.release(hw); 507 } else { 508 status = IGC_ERR_SWFW_SYNC; 509 } 510 511 if (status != IGC_SUCCESS) 512 break; 513 } 514 515 return status; 516 } 517 518 /* __igc_write_nvm_srwr - Write to Shadow Ram using EEWR 519 * @hw: pointer to the HW structure 520 * @offset: offset within the Shadow Ram to be written to 521 * @words: number of words to write 522 * @data: 16 bit word(s) to be written to the Shadow Ram 523 * 524 * Writes data to Shadow Ram at offset using EEWR register. 525 * 526 * If igc_update_nvm_checksum is not called after this function , the 527 * Shadow Ram will most likely contain an invalid checksum. 528 */ 529 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words, 530 u16 *data) 531 { 532 struct igc_nvm_info *nvm = &hw->nvm; 533 u32 i, k, eewr = 0; 534 u32 attempts = 100000; 535 s32 ret_val = IGC_SUCCESS; 536 537 DEBUGFUNC("__igc_write_nvm_srwr"); 538 539 /* A check for invalid values: offset too large, too many words, 540 * too many words for the offset, and not enough words. 541 */ 542 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 543 (words == 0)) { 544 DEBUGOUT("nvm parameter(s) out of bounds\n"); 545 ret_val = -IGC_ERR_NVM; 546 goto out; 547 } 548 549 for (i = 0; i < words; i++) { 550 eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) | 551 (data[i] << IGC_NVM_RW_REG_DATA) | 552 IGC_NVM_RW_REG_START; 553 554 IGC_WRITE_REG(hw, IGC_SRWR, eewr); 555 556 for (k = 0; k < attempts; k++) { 557 if (IGC_NVM_RW_REG_DONE & 558 IGC_READ_REG(hw, IGC_SRWR)) { 559 ret_val = IGC_SUCCESS; 560 break; 561 } 562 usec_delay(5); 563 } 564 565 if (ret_val != IGC_SUCCESS) { 566 DEBUGOUT("Shadow RAM write EEWR timed out\n"); 567 break; 568 } 569 } 570 571 out: 572 return ret_val; 573 } 574 575 /* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum 576 * @hw: pointer to the HW structure 577 * 578 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 579 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 580 */ 581 s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw) 582 { 583 s32 status = IGC_SUCCESS; 584 s32 (*read_op_ptr)(struct igc_hw *, u16, u16, u16 *); 585 586 DEBUGFUNC("igc_validate_nvm_checksum_i225"); 587 588 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 589 /* Replace the read function with semaphore grabbing with 590 * the one that skips this for a while. 591 * We have semaphore taken already here. 592 */ 593 read_op_ptr = hw->nvm.ops.read; 594 hw->nvm.ops.read = igc_read_nvm_eerd; 595 596 status = igc_validate_nvm_checksum_generic(hw); 597 598 /* Revert original read operation. */ 599 hw->nvm.ops.read = read_op_ptr; 600 601 hw->nvm.ops.release(hw); 602 } else { 603 status = IGC_ERR_SWFW_SYNC; 604 } 605 606 return status; 607 } 608 609 /* igc_update_nvm_checksum_i225 - Update EEPROM checksum 610 * @hw: pointer to the HW structure 611 * 612 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 613 * up to the checksum. Then calculates the EEPROM checksum and writes the 614 * value to the EEPROM. Next commit EEPROM data onto the Flash. 615 */ 616 s32 igc_update_nvm_checksum_i225(struct igc_hw *hw) 617 { 618 s32 ret_val; 619 u16 checksum = 0; 620 u16 i, nvm_data; 621 622 DEBUGFUNC("igc_update_nvm_checksum_i225"); 623 624 /* Read the first word from the EEPROM. If this times out or fails, do 625 * not continue or we could be in for a very long wait while every 626 * EEPROM read fails 627 */ 628 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data); 629 if (ret_val != IGC_SUCCESS) { 630 DEBUGOUT("EEPROM read failed\n"); 631 goto out; 632 } 633 634 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 635 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read 636 * because we do not want to take the synchronization 637 * semaphores twice here. 638 */ 639 640 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 641 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data); 642 if (ret_val) { 643 hw->nvm.ops.release(hw); 644 DEBUGOUT("NVM Read Error while updating\n"); 645 DEBUGOUT("checksum.\n"); 646 goto out; 647 } 648 checksum += nvm_data; 649 } 650 checksum = (u16)NVM_SUM - checksum; 651 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, 652 &checksum); 653 if (ret_val != IGC_SUCCESS) { 654 hw->nvm.ops.release(hw); 655 DEBUGOUT("NVM Write Error while updating checksum.\n"); 656 goto out; 657 } 658 659 hw->nvm.ops.release(hw); 660 661 ret_val = igc_update_flash_i225(hw); 662 } else { 663 ret_val = IGC_ERR_SWFW_SYNC; 664 } 665 out: 666 return ret_val; 667 } 668 669 /* igc_get_flash_presence_i225 - Check if flash device is detected. 670 * @hw: pointer to the HW structure 671 */ 672 bool igc_get_flash_presence_i225(struct igc_hw *hw) 673 { 674 u32 eec = 0; 675 bool ret_val = false; 676 677 DEBUGFUNC("igc_get_flash_presence_i225"); 678 679 eec = IGC_READ_REG(hw, IGC_EECD); 680 681 if (eec & IGC_EECD_FLASH_DETECTED_I225) 682 ret_val = true; 683 684 return ret_val; 685 } 686 687 /* igc_set_flsw_flash_burst_counter_i225 - sets FLSW NVM Burst 688 * Counter in FLSWCNT register. 689 * 690 * @hw: pointer to the HW structure 691 * @burst_counter: size in bytes of the Flash burst to read or write 692 */ 693 s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, 694 u32 burst_counter) 695 { 696 s32 ret_val = IGC_SUCCESS; 697 698 DEBUGFUNC("igc_set_flsw_flash_burst_counter_i225"); 699 700 /* Validate input data */ 701 if (burst_counter < IGC_I225_SHADOW_RAM_SIZE) { 702 /* Write FLSWCNT - burst counter */ 703 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter); 704 } else { 705 ret_val = IGC_ERR_INVALID_ARGUMENT; 706 } 707 708 return ret_val; 709 } 710 711 /* igc_write_erase_flash_command_i225 - write/erase to a sector 712 * region on a given address. 713 * 714 * @hw: pointer to the HW structure 715 * @opcode: opcode to be used for the write command 716 * @address: the offset to write into the FLASH image 717 */ 718 s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode, 719 u32 address) 720 { 721 u32 flswctl = 0; 722 s32 timeout = IGC_NVM_GRANT_ATTEMPTS; 723 s32 ret_val = IGC_SUCCESS; 724 725 DEBUGFUNC("igc_write_erase_flash_command_i225"); 726 727 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 728 /* Polling done bit on FLSWCTL register */ 729 while (timeout) { 730 if (flswctl & IGC_FLSWCTL_DONE) 731 break; 732 usec_delay(5); 733 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 734 timeout--; 735 } 736 737 if (!timeout) { 738 DEBUGOUT("Flash transaction was not done\n"); 739 return -IGC_ERR_NVM; 740 } 741 742 /* Build and issue command on FLSWCTL register */ 743 flswctl = address | opcode; 744 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl); 745 746 /* Check if issued command is valid on FLSWCTL register */ 747 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 748 if (!(flswctl & IGC_FLSWCTL_CMDV)) { 749 DEBUGOUT("Write flash command failed\n"); 750 ret_val = IGC_ERR_INVALID_ARGUMENT; 751 } 752 753 return ret_val; 754 } 755 756 /* igc_update_flash_i225 - Commit EEPROM to the flash 757 * if fw_valid_bit is set, FW is active. setting FLUPD bit in EEC 758 * register makes the FW load the internal shadow RAM into the flash. 759 * Otherwise, fw_valid_bit is 0. if FL_SECU.block_prtotected_sw = 0 760 * then FW is not active so the SW is responsible shadow RAM dump. 761 * 762 * @hw: pointer to the HW structure 763 */ 764 s32 igc_update_flash_i225(struct igc_hw *hw) 765 { 766 u16 current_offset_data = 0; 767 u32 block_sw_protect = 1; 768 u16 base_address = 0x0; 769 u32 i, fw_valid_bit; 770 u16 current_offset; 771 s32 ret_val = 0; 772 u32 flup; 773 774 DEBUGFUNC("igc_update_flash_i225"); 775 776 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) & 777 IGC_FLSECU_BLK_SW_ACCESS_I225; 778 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) & 779 IGC_FWSM_FW_VALID_I225; 780 if (fw_valid_bit) { 781 ret_val = igc_pool_flash_update_done_i225(hw); 782 if (ret_val == -IGC_ERR_NVM) { 783 DEBUGOUT("Flash update time out\n"); 784 goto out; 785 } 786 787 flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225; 788 IGC_WRITE_REG(hw, IGC_EECD, flup); 789 790 ret_val = igc_pool_flash_update_done_i225(hw); 791 if (ret_val == IGC_SUCCESS) 792 DEBUGOUT("Flash update complete\n"); 793 else 794 DEBUGOUT("Flash update time out\n"); 795 } else if (!block_sw_protect) { 796 /* FW is not active and security protection is disabled. 797 * therefore, SW is in charge of shadow RAM dump. 798 * Check which sector is valid. if sector 0 is valid, 799 * base address remains 0x0. otherwise, sector 1 is 800 * valid and it's base address is 0x1000 801 */ 802 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225) 803 base_address = 0x1000; 804 805 /* Valid sector erase */ 806 ret_val = igc_write_erase_flash_command_i225(hw, 807 IGC_I225_ERASE_CMD_OPCODE, 808 base_address); 809 if (!ret_val) { 810 DEBUGOUT("Sector erase failed\n"); 811 goto out; 812 } 813 814 current_offset = base_address; 815 816 /* Write */ 817 for (i = 0; i < IGC_I225_SHADOW_RAM_SIZE / 2; i++) { 818 /* Set burst write length */ 819 ret_val = igc_set_flsw_flash_burst_counter_i225(hw, 820 0x2); 821 if (ret_val != IGC_SUCCESS) 822 break; 823 824 /* Set address and opcode */ 825 ret_val = igc_write_erase_flash_command_i225(hw, 826 IGC_I225_WRITE_CMD_OPCODE, 827 2 * current_offset); 828 if (ret_val != IGC_SUCCESS) 829 break; 830 831 ret_val = igc_read_nvm_eerd(hw, current_offset, 832 1, ¤t_offset_data); 833 if (ret_val) { 834 DEBUGOUT("Failed to read from EEPROM\n"); 835 goto out; 836 } 837 838 /* Write CurrentOffseData to FLSWDATA register */ 839 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA, 840 current_offset_data); 841 current_offset++; 842 843 /* Wait till operation has finished */ 844 ret_val = igc_poll_eerd_eewr_done(hw, 845 IGC_NVM_POLL_READ); 846 if (ret_val) 847 break; 848 849 usec_delay(1000); 850 } 851 } 852 out: 853 return ret_val; 854 } 855 856 /* igc_pool_flash_update_done_i225 - Pool FLUDONE status. 857 * @hw: pointer to the HW structure 858 */ 859 s32 igc_pool_flash_update_done_i225(struct igc_hw *hw) 860 { 861 s32 ret_val = -IGC_ERR_NVM; 862 u32 i, reg; 863 864 DEBUGFUNC("igc_pool_flash_update_done_i225"); 865 866 for (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) { 867 reg = IGC_READ_REG(hw, IGC_EECD); 868 if (reg & IGC_EECD_FLUDONE_I225) { 869 ret_val = IGC_SUCCESS; 870 break; 871 } 872 usec_delay(5); 873 } 874 875 return ret_val; 876 } 877 878 /* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds. 879 * @hw: pointer to the HW structure 880 * @link: bool indicating link status 881 * 882 * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC 883 * settings, otherwise specify that there is no LTR requirement. 884 */ 885 static s32 igc_set_ltr_i225(struct igc_hw *hw, bool link) 886 { 887 u16 speed, duplex; 888 u32 tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max; 889 s32 size; 890 891 DEBUGFUNC("igc_set_ltr_i225"); 892 893 /* If we do not have link, LTR thresholds are zero. */ 894 if (link) { 895 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 896 897 /* Check if using copper interface with EEE enabled or if the 898 * link speed is 10 Mbps. 899 */ 900 if ((hw->phy.media_type == igc_media_type_copper) && 901 !(hw->dev_spec._i225.eee_disable) && 902 (speed != SPEED_10)) { 903 /* EEE enabled, so send LTRMAX threshold. */ 904 ltrc = IGC_READ_REG(hw, IGC_LTRC) | 905 IGC_LTRC_EEEMS_EN; 906 IGC_WRITE_REG(hw, IGC_LTRC, ltrc); 907 908 /* Calculate tw_system (nsec). */ 909 if (speed == SPEED_100) { 910 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) & 911 IGC_TW_SYSTEM_100_MASK) >> 912 IGC_TW_SYSTEM_100_SHIFT) * 500; 913 } else { 914 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) & 915 IGC_TW_SYSTEM_1000_MASK) * 500; 916 } 917 } else { 918 tw_system = 0; 919 } 920 921 /* Get the Rx packet buffer size. */ 922 size = IGC_READ_REG(hw, IGC_RXPBS) & 923 IGC_RXPBS_SIZE_I225_MASK; 924 925 /* Calculations vary based on DMAC settings. */ 926 if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) { 927 size -= (IGC_READ_REG(hw, IGC_DMACR) & 928 IGC_DMACR_DMACTHR_MASK) >> 929 IGC_DMACR_DMACTHR_SHIFT; 930 /* Convert size to bits. */ 931 size *= 1024 * 8; 932 } else { 933 /* Convert size to bytes, subtract the MTU, and then 934 * convert the size to bits. 935 */ 936 size *= 1024; 937 size -= hw->dev_spec._i225.mtu; 938 size *= 8; 939 } 940 941 if (size < 0) { 942 DEBUGOUT1("Invalid effective Rx buffer size %d\n", 943 size); 944 return -IGC_ERR_CONFIG; 945 } 946 947 /* Calculate the thresholds. Since speed is in Mbps, simplify 948 * the calculation by multiplying size/speed by 1000 for result 949 * to be in nsec before dividing by the scale in nsec. Set the 950 * scale such that the LTR threshold fits in the register. 951 */ 952 ltr_min = (1000 * size) / speed; 953 ltr_max = ltr_min + tw_system; 954 scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 : 955 IGC_LTRMINV_SCALE_32768; 956 scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 : 957 IGC_LTRMAXV_SCALE_32768; 958 ltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768; 959 ltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768; 960 961 /* Only write the LTR thresholds if they differ from before. */ 962 ltrv = IGC_READ_REG(hw, IGC_LTRMINV); 963 if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) { 964 ltrv = IGC_LTRMINV_LSNP_REQ | ltr_min | 965 (scale_min << IGC_LTRMINV_SCALE_SHIFT); 966 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv); 967 } 968 969 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV); 970 if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) { 971 ltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max | 972 (scale_min << IGC_LTRMAXV_SCALE_SHIFT); 973 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv); 974 } 975 } 976 977 return IGC_SUCCESS; 978 } 979 980 /* igc_check_for_link_i225 - Check for link 981 * @hw: pointer to the HW structure 982 * 983 * Checks to see of the link status of the hardware has changed. If a 984 * change in link status has been detected, then we read the PHY registers 985 * to get the current speed/duplex if link exists. 986 */ 987 s32 igc_check_for_link_i225(struct igc_hw *hw) 988 { 989 struct igc_mac_info *mac = &hw->mac; 990 s32 ret_val; 991 bool link = false; 992 993 DEBUGFUNC("igc_check_for_link_i225"); 994 995 /* We only want to go out to the PHY registers to see if 996 * Auto-Neg has completed and/or if our link status has 997 * changed. The get_link_status flag is set upon receiving 998 * a Link Status Change or Rx Sequence Error interrupt. 999 */ 1000 if (!mac->get_link_status) { 1001 ret_val = IGC_SUCCESS; 1002 goto out; 1003 } 1004 1005 /* First we want to see if the MII Status Register reports 1006 * link. If so, then we want to get the current speed/duplex 1007 * of the PHY. 1008 */ 1009 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 1010 if (ret_val) 1011 goto out; 1012 1013 if (!link) 1014 goto out; /* No link detected */ 1015 1016 /* First we want to see if the MII Status Register reports 1017 * link. If so, then we want to get the current speed/duplex 1018 * of the PHY. 1019 */ 1020 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 1021 if (ret_val) 1022 goto out; 1023 1024 if (!link) 1025 goto out; /* No link detected */ 1026 1027 mac->get_link_status = false; 1028 1029 /* Check if there was DownShift, must be checked 1030 * immediately after link-up 1031 */ 1032 igc_check_downshift_generic(hw); 1033 1034 /* If we are forcing speed/duplex, then we simply return since 1035 * we have already determined whether we have link or not. 1036 */ 1037 if (!mac->autoneg) 1038 goto out; 1039 1040 /* Auto-Neg is enabled. Auto Speed Detection takes care 1041 * of MAC speed/duplex configuration. So we only need to 1042 * configure Collision Distance in the MAC. 1043 */ 1044 mac->ops.config_collision_dist(hw); 1045 1046 /* Configure Flow Control now that Auto-Neg has completed. 1047 * First, we need to restore the desired flow control 1048 * settings because we may have had to re-autoneg with a 1049 * different link partner. 1050 */ 1051 ret_val = igc_config_fc_after_link_up_generic(hw); 1052 if (ret_val) 1053 DEBUGOUT("Error configuring flow control\n"); 1054 out: 1055 /* Now that we are aware of our link settings, we can set the LTR 1056 * thresholds. 1057 */ 1058 ret_val = igc_set_ltr_i225(hw, link); 1059 1060 return ret_val; 1061 } 1062 1063 /* igc_init_function_pointers_i225 - Init func ptrs. 1064 * @hw: pointer to the HW structure 1065 * 1066 * Called to initialize all function pointers and parameters. 1067 */ 1068 void igc_init_function_pointers_i225(struct igc_hw *hw) 1069 { 1070 igc_init_mac_ops_generic(hw); 1071 igc_init_phy_ops_generic(hw); 1072 igc_init_nvm_ops_generic(hw); 1073 hw->mac.ops.init_params = igc_init_mac_params_i225; 1074 hw->nvm.ops.init_params = igc_init_nvm_params_i225; 1075 hw->phy.ops.init_params = igc_init_phy_params_i225; 1076 } 1077 1078 /* igc_init_hw_i225 - Init hw for I225 1079 * @hw: pointer to the HW structure 1080 * 1081 * Called to initialize hw for i225 hw family. 1082 */ 1083 s32 igc_init_hw_i225(struct igc_hw *hw) 1084 { 1085 s32 ret_val; 1086 1087 DEBUGFUNC("igc_init_hw_i225"); 1088 1089 ret_val = igc_init_hw_base(hw); 1090 return ret_val; 1091 } 1092 1093 /* 1094 * igc_set_d0_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D0 state 1095 * @hw: pointer to the HW structure 1096 * @active: true to enable LPLU, false to disable 1097 * 1098 * Note: since I225 does not actually support LPLU, this function 1099 * simply enables/disables 1G and 2.5G speeds in D0. 1100 */ 1101 s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active) 1102 { 1103 u32 data; 1104 1105 DEBUGFUNC("igc_set_d0_lplu_state_i225"); 1106 1107 data = IGC_READ_REG(hw, IGC_I225_PHPM); 1108 1109 if (active) { 1110 data |= IGC_I225_PHPM_DIS_1000; 1111 data |= IGC_I225_PHPM_DIS_2500; 1112 } else { 1113 data &= ~IGC_I225_PHPM_DIS_1000; 1114 data &= ~IGC_I225_PHPM_DIS_2500; 1115 } 1116 1117 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); 1118 return IGC_SUCCESS; 1119 } 1120 1121 /* 1122 * igc_set_d3_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D3 state 1123 * @hw: pointer to the HW structure 1124 * @active: true to enable LPLU, false to disable 1125 * 1126 * Note: since I225 does not actually support LPLU, this function 1127 * simply enables/disables 100M, 1G and 2.5G speeds in D3. 1128 */ 1129 s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active) 1130 { 1131 u32 data; 1132 1133 DEBUGFUNC("igc_set_d3_lplu_state_i225"); 1134 1135 data = IGC_READ_REG(hw, IGC_I225_PHPM); 1136 1137 if (active) { 1138 data |= IGC_I225_PHPM_DIS_100_D3; 1139 data |= IGC_I225_PHPM_DIS_1000_D3; 1140 data |= IGC_I225_PHPM_DIS_2500_D3; 1141 } else { 1142 data &= ~IGC_I225_PHPM_DIS_100_D3; 1143 data &= ~IGC_I225_PHPM_DIS_1000_D3; 1144 data &= ~IGC_I225_PHPM_DIS_2500_D3; 1145 } 1146 1147 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); 1148 return IGC_SUCCESS; 1149 } 1150 1151 /** 1152 * igc_set_eee_i225 - Enable/disable EEE support 1153 * @hw: pointer to the HW structure 1154 * @adv2p5G: boolean flag enabling 2.5G EEE advertisement 1155 * @adv1G: boolean flag enabling 1G EEE advertisement 1156 * @adv100M: boolean flag enabling 100M EEE advertisement 1157 * 1158 * Enable/disable EEE based on setting in dev_spec structure. 1159 * 1160 **/ 1161 s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G, 1162 bool adv100M) 1163 { 1164 u32 ipcnfg, eeer; 1165 1166 DEBUGFUNC("igc_set_eee_i225"); 1167 1168 if (hw->mac.type != igc_i225 || 1169 hw->phy.media_type != igc_media_type_copper) 1170 goto out; 1171 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG); 1172 eeer = IGC_READ_REG(hw, IGC_EEER); 1173 1174 /* enable or disable per user setting */ 1175 if (!(hw->dev_spec._i225.eee_disable)) { 1176 u32 eee_su = IGC_READ_REG(hw, IGC_EEE_SU); 1177 1178 if (adv100M) 1179 ipcnfg |= IGC_IPCNFG_EEE_100M_AN; 1180 else 1181 ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN; 1182 1183 if (adv1G) 1184 ipcnfg |= IGC_IPCNFG_EEE_1G_AN; 1185 else 1186 ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN; 1187 1188 if (adv2p5G) 1189 ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN; 1190 else 1191 ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN; 1192 1193 eeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | 1194 IGC_EEER_LPI_FC); 1195 1196 /* This bit should not be set in normal operation. */ 1197 if (eee_su & IGC_EEE_SU_LPI_CLK_STP) 1198 DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 1199 } else { 1200 ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN | 1201 IGC_IPCNFG_EEE_100M_AN); 1202 eeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | 1203 IGC_EEER_LPI_FC); 1204 } 1205 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg); 1206 IGC_WRITE_REG(hw, IGC_EEER, eeer); 1207 IGC_READ_REG(hw, IGC_IPCNFG); 1208 IGC_READ_REG(hw, IGC_EEER); 1209 out: 1210 1211 return IGC_SUCCESS; 1212 } 1213 1214