1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_sw.h" 32 33 static boolean_t igb_tx(igb_tx_ring_t *, mblk_t *); 34 static int igb_tx_copy(igb_tx_ring_t *, tx_control_block_t *, mblk_t *, 35 uint32_t, boolean_t); 36 static int igb_tx_bind(igb_tx_ring_t *, tx_control_block_t *, mblk_t *, 37 uint32_t); 38 static int igb_tx_fill_ring(igb_tx_ring_t *, link_list_t *, hcksum_context_t *); 39 static void igb_save_desc(tx_control_block_t *, uint64_t, size_t); 40 static tx_control_block_t *igb_get_free_list(igb_tx_ring_t *); 41 42 static void igb_get_hcksum_context(mblk_t *, hcksum_context_t *); 43 static boolean_t igb_check_hcksum_context(igb_tx_ring_t *, hcksum_context_t *); 44 static void igb_fill_hcksum_context(struct e1000_adv_tx_context_desc *, 45 hcksum_context_t *); 46 47 #ifndef IGB_DEBUG 48 #pragma inline(igb_save_desc) 49 #pragma inline(igb_get_hcksum_context) 50 #pragma inline(igb_check_hcksum_context) 51 #pragma inline(igb_fill_hcksum_context) 52 #endif 53 54 /* 55 * igb_m_tx 56 * 57 * The GLDv3 interface to call driver's tx routine to transmit 58 * the mblks. 59 */ 60 mblk_t * 61 igb_m_tx(void *arg, mblk_t *mp) 62 { 63 igb_t *igb = (igb_t *)arg; 64 mblk_t *next; 65 igb_tx_ring_t *tx_ring; 66 67 /* 68 * If the adapter is suspended, or it is not started, or the link 69 * is not up, the mblks are simply dropped. 70 */ 71 if (((igb->igb_state & IGB_SUSPENDED) != 0) || 72 ((igb->igb_state & IGB_STARTED) == 0) || 73 (igb->link_state != LINK_STATE_UP)) { 74 /* Free the mblk chain */ 75 while (mp != NULL) { 76 next = mp->b_next; 77 mp->b_next = NULL; 78 79 freemsg(mp); 80 mp = next; 81 } 82 83 return (NULL); 84 } 85 86 /* 87 * Decide which tx ring is used to transmit the packets. 88 * This needs to be updated later to fit the new interface 89 * of the multiple rings support. 90 */ 91 tx_ring = &igb->tx_rings[0]; 92 93 while (mp != NULL) { 94 next = mp->b_next; 95 mp->b_next = NULL; 96 97 if (!igb_tx(tx_ring, mp)) { 98 mp->b_next = next; 99 break; 100 } 101 102 mp = next; 103 } 104 105 return (mp); 106 } 107 108 /* 109 * igb_tx - Main transmit processing 110 * 111 * Called from igb_m_tx with an mblk ready to transmit. this 112 * routine sets up the transmit descriptors and sends data to 113 * the wire. 114 * 115 * One mblk can consist of several fragments, each fragment 116 * will be processed with different methods based on the size. 117 * For the fragments with size less than the bcopy threshold, 118 * they will be processed by using bcopy; otherwise, they will 119 * be processed by using DMA binding. 120 * 121 * To process the mblk, a tx control block is got from the 122 * free list. One tx control block contains one tx buffer, which 123 * is used to copy mblk fragments' data; and one tx DMA handle, 124 * which is used to bind a mblk fragment with DMA resource. 125 * 126 * Several small mblk fragments can be copied into one tx control 127 * block's buffer, and then the buffer will be transmitted with 128 * one tx descriptor. 129 * 130 * A large fragment only binds with one tx control block's DMA 131 * handle, and it can span several tx descriptors for transmitting. 132 * 133 * So to transmit a packet (mblk), several tx control blocks can 134 * be used. After the processing, those tx control blocks will 135 * be put to the work list. 136 */ 137 static boolean_t 138 igb_tx(igb_tx_ring_t *tx_ring, mblk_t *mp) 139 { 140 igb_t *igb = tx_ring->igb; 141 tx_type_t current_flag, next_flag; 142 uint32_t current_len, next_len; 143 uint32_t desc_total; 144 size_t mbsize; 145 int desc_num; 146 boolean_t copy_done, eop; 147 mblk_t *current_mp, *next_mp, *nmp; 148 tx_control_block_t *tcb; 149 hcksum_context_t hcksum_context, *hcksum; 150 link_list_t pending_list; 151 152 /* Get the mblk size */ 153 mbsize = 0; 154 for (nmp = mp; nmp != NULL; nmp = nmp->b_cont) { 155 mbsize += MBLK_LEN(nmp); 156 } 157 158 /* 159 * If the mblk size exceeds the max frame size, 160 * discard this mblk, and return B_TRUE 161 */ 162 if (mbsize > (igb->max_frame_size - ETHERFCSL)) { 163 freemsg(mp); 164 IGB_DEBUGLOG_0(igb, "igb_tx: packet oversize"); 165 return (B_TRUE); 166 } 167 168 /* 169 * Check and recycle tx descriptors. 170 * The recycle threshold here should be selected carefully 171 */ 172 if (tx_ring->tbd_free < tx_ring->recycle_thresh) 173 tx_ring->tx_recycle(tx_ring); 174 175 /* 176 * After the recycling, if the tbd_free is less than the 177 * overload_threshold, assert overload, return B_FALSE; 178 * and we need to re-schedule the tx again. 179 */ 180 if (tx_ring->tbd_free < tx_ring->overload_thresh) { 181 tx_ring->reschedule = B_TRUE; 182 IGB_DEBUG_STAT(tx_ring->stat_overload); 183 return (B_FALSE); 184 } 185 186 /* 187 * The pending_list is a linked list that is used to save 188 * the tx control blocks that have packet data processed 189 * but have not put the data to the tx descriptor ring. 190 * It is used to reduce the lock contention of the tx_lock. 191 */ 192 LINK_LIST_INIT(&pending_list); 193 desc_num = 0; 194 desc_total = 0; 195 196 current_mp = mp; 197 current_len = MBLK_LEN(current_mp); 198 /* 199 * Decide which method to use for the first fragment 200 */ 201 current_flag = (current_len <= tx_ring->copy_thresh) ? 202 USE_COPY : USE_DMA; 203 /* 204 * If the mblk includes several contiguous small fragments, 205 * they may be copied into one buffer. This flag is used to 206 * indicate whether there are pending fragments that need to 207 * be copied to the current tx buffer. 208 * 209 * If this flag is B_TRUE, it indicates that a new tx control 210 * block is needed to process the next fragment using either 211 * copy or DMA binding. 212 * 213 * Otherwise, it indicates that the next fragment will be 214 * copied to the current tx buffer that is maintained by the 215 * current tx control block. No new tx control block is needed. 216 */ 217 copy_done = B_TRUE; 218 while (current_mp) { 219 next_mp = current_mp->b_cont; 220 eop = (next_mp == NULL); /* Last fragment of the packet? */ 221 next_len = eop ? 0: MBLK_LEN(next_mp); 222 223 /* 224 * When the current fragment is an empty fragment, if 225 * the next fragment will still be copied to the current 226 * tx buffer, we cannot skip this fragment here. Because 227 * the copy processing is pending for completion. We have 228 * to process this empty fragment in the tx_copy routine. 229 * 230 * If the copy processing is completed or a DMA binding 231 * processing is just completed, we can just skip this 232 * empty fragment. 233 */ 234 if ((current_len == 0) && (copy_done)) { 235 current_mp = next_mp; 236 current_len = next_len; 237 current_flag = (current_len <= tx_ring->copy_thresh) ? 238 USE_COPY : USE_DMA; 239 continue; 240 } 241 242 if (copy_done) { 243 /* 244 * Get a new tx control block from the free list 245 */ 246 tcb = igb_get_free_list(tx_ring); 247 248 if (tcb == NULL) { 249 IGB_DEBUG_STAT(tx_ring->stat_fail_no_tcb); 250 goto tx_failure; 251 } 252 253 /* 254 * Push the tx control block to the pending list 255 * to avoid using lock too early 256 */ 257 LIST_PUSH_TAIL(&pending_list, &tcb->link); 258 } 259 260 if (current_flag == USE_COPY) { 261 /* 262 * Check whether to use bcopy or DMA binding to process 263 * the next fragment, and if using bcopy, whether we 264 * need to continue copying the next fragment into the 265 * current tx buffer. 266 */ 267 ASSERT((tcb->tx_buf.len + current_len) <= 268 tcb->tx_buf.size); 269 270 if (eop) { 271 /* 272 * This is the last fragment of the packet, so 273 * the copy processing will be completed with 274 * this fragment. 275 */ 276 next_flag = USE_NONE; 277 copy_done = B_TRUE; 278 } else if ((tcb->tx_buf.len + current_len + next_len) > 279 tcb->tx_buf.size) { 280 /* 281 * If the next fragment is too large to be 282 * copied to the current tx buffer, we need 283 * to complete the current copy processing. 284 */ 285 next_flag = (next_len > tx_ring->copy_thresh) ? 286 USE_DMA: USE_COPY; 287 copy_done = B_TRUE; 288 } else if (next_len > tx_ring->copy_thresh) { 289 /* 290 * The next fragment needs to be processed with 291 * DMA binding. So the copy prcessing will be 292 * completed with the current fragment. 293 */ 294 next_flag = USE_DMA; 295 copy_done = B_TRUE; 296 } else { 297 /* 298 * Continue to copy the next fragment to the 299 * current tx buffer. 300 */ 301 next_flag = USE_COPY; 302 copy_done = B_FALSE; 303 } 304 305 desc_num = igb_tx_copy(tx_ring, tcb, current_mp, 306 current_len, copy_done); 307 } else { 308 /* 309 * Check whether to use bcopy or DMA binding to process 310 * the next fragment. 311 */ 312 next_flag = (next_len > tx_ring->copy_thresh) ? 313 USE_DMA: USE_COPY; 314 ASSERT(copy_done == B_TRUE); 315 316 desc_num = igb_tx_bind(tx_ring, tcb, current_mp, 317 current_len); 318 } 319 320 if (desc_num > 0) 321 desc_total += desc_num; 322 else if (desc_num < 0) 323 goto tx_failure; 324 325 current_mp = next_mp; 326 current_len = next_len; 327 current_flag = next_flag; 328 } 329 330 /* 331 * Attach the mblk to the last tx control block 332 */ 333 ASSERT(tcb); 334 ASSERT(tcb->mp == NULL); 335 tcb->mp = mp; 336 337 if (igb->tx_hcksum_enable) { 338 /* 339 * Retrieve checksum context information from the mblk that will 340 * be used to decide whether/how to fill the context descriptor. 341 */ 342 hcksum = &hcksum_context; 343 igb_get_hcksum_context(mp, hcksum); 344 } else { 345 hcksum = NULL; 346 } 347 348 /* 349 * Before fill the tx descriptor ring with the data, we need to 350 * ensure there are adequate free descriptors for transmit 351 * (including one context descriptor). 352 */ 353 if (tx_ring->tbd_free < (desc_total + 1)) { 354 tx_ring->tx_recycle(tx_ring); 355 } 356 357 mutex_enter(&tx_ring->tx_lock); 358 359 /* 360 * If the number of free tx descriptors is not enough for transmit 361 * then return failure. 362 * 363 * Note: we must put this check under the mutex protection to 364 * ensure the correctness when multiple threads access it in 365 * parallel. 366 */ 367 if (tx_ring->tbd_free < (desc_total + 1)) { 368 IGB_DEBUG_STAT(tx_ring->stat_fail_no_tbd); 369 mutex_exit(&tx_ring->tx_lock); 370 goto tx_failure; 371 } 372 373 desc_num = igb_tx_fill_ring(tx_ring, &pending_list, hcksum); 374 375 ASSERT((desc_num == desc_total) || (desc_num == (desc_total + 1))); 376 377 mutex_exit(&tx_ring->tx_lock); 378 379 return (B_TRUE); 380 381 tx_failure: 382 /* 383 * Discard the mblk and free the used resources 384 */ 385 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 386 while (tcb) { 387 tcb->mp = NULL; 388 389 igb_free_tcb(tcb); 390 391 tcb = (tx_control_block_t *) 392 LIST_GET_NEXT(&pending_list, &tcb->link); 393 } 394 395 /* 396 * Return the tx control blocks in the pending list to the free list. 397 */ 398 igb_put_free_list(tx_ring, &pending_list); 399 400 /* Transmit failed, do not drop the mblk, rechedule the transmit */ 401 tx_ring->reschedule = B_TRUE; 402 403 return (B_FALSE); 404 } 405 406 /* 407 * igb_tx_copy 408 * 409 * Copy the mblk fragment to the pre-allocated tx buffer 410 */ 411 static int 412 igb_tx_copy(igb_tx_ring_t *tx_ring, tx_control_block_t *tcb, mblk_t *mp, 413 uint32_t len, boolean_t copy_done) 414 { 415 dma_buffer_t *tx_buf; 416 uint32_t desc_num; 417 _NOTE(ARGUNUSED(tx_ring)); 418 419 tx_buf = &tcb->tx_buf; 420 421 /* 422 * Copy the packet data of the mblk fragment into the 423 * pre-allocated tx buffer, which is maintained by the 424 * tx control block. 425 * 426 * Several mblk fragments can be copied into one tx buffer. 427 * The destination address of the current copied fragment in 428 * the tx buffer is next to the end of the previous copied 429 * fragment. 430 */ 431 if (len > 0) { 432 bcopy(mp->b_rptr, tx_buf->address + tx_buf->len, len); 433 434 tx_buf->len += len; 435 tcb->frag_num++; 436 } 437 438 desc_num = 0; 439 440 /* 441 * If it is the last fragment copied to the current tx buffer, 442 * in other words, if there's no remaining fragment or the remaining 443 * fragment requires a new tx control block to process, we need to 444 * complete the current copy processing by syncing up the current 445 * DMA buffer and saving the descriptor data. 446 */ 447 if (copy_done) { 448 /* 449 * Sync the DMA buffer of the packet data 450 */ 451 DMA_SYNC(tx_buf, DDI_DMA_SYNC_FORDEV); 452 453 tcb->tx_type = USE_COPY; 454 455 /* 456 * Save the address and length to the private data structure 457 * of the tx control block, which will be used to fill the 458 * tx descriptor ring after all the fragments are processed. 459 */ 460 igb_save_desc(tcb, tx_buf->dma_address, tx_buf->len); 461 desc_num++; 462 } 463 464 return (desc_num); 465 } 466 467 /* 468 * igb_tx_bind 469 * 470 * Bind the mblk fragment with DMA 471 */ 472 static int 473 igb_tx_bind(igb_tx_ring_t *tx_ring, tx_control_block_t *tcb, mblk_t *mp, 474 uint32_t len) 475 { 476 int status, i; 477 ddi_dma_cookie_t dma_cookie; 478 uint_t ncookies; 479 int desc_num; 480 481 /* 482 * Use DMA binding to process the mblk fragment 483 */ 484 status = ddi_dma_addr_bind_handle(tcb->tx_dma_handle, NULL, 485 (caddr_t)mp->b_rptr, len, 486 DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_DONTWAIT, 487 0, &dma_cookie, &ncookies); 488 489 if (status != DDI_DMA_MAPPED) { 490 IGB_DEBUG_STAT(tx_ring->stat_fail_dma_bind); 491 return (-1); 492 } 493 494 tcb->frag_num++; 495 tcb->tx_type = USE_DMA; 496 /* 497 * Each fragment can span several cookies. One cookie will have 498 * one tx descriptor to transmit. 499 */ 500 desc_num = 0; 501 for (i = ncookies; i > 0; i--) { 502 /* 503 * Save the address and length to the private data structure 504 * of the tx control block, which will be used to fill the 505 * tx descriptor ring after all the fragments are processed. 506 */ 507 igb_save_desc(tcb, 508 dma_cookie.dmac_laddress, 509 dma_cookie.dmac_size); 510 511 desc_num++; 512 513 if (i > 1) 514 ddi_dma_nextcookie(tcb->tx_dma_handle, &dma_cookie); 515 } 516 517 return (desc_num); 518 } 519 520 /* 521 * igb_get_hcksum_context 522 * 523 * Get the hcksum context information from the mblk 524 */ 525 static void 526 igb_get_hcksum_context(mblk_t *mp, hcksum_context_t *hcksum) 527 { 528 uint32_t start; 529 uint32_t flags; 530 uint32_t len; 531 uint32_t size; 532 uint32_t offset; 533 unsigned char *pos; 534 ushort_t etype; 535 uint32_t mac_hdr_len; 536 uint32_t l4_proto; 537 538 ASSERT(mp != NULL); 539 540 hcksum_retrieve(mp, NULL, NULL, &start, NULL, NULL, NULL, &flags); 541 542 hcksum->hcksum_flags = flags; 543 544 if (flags == 0) 545 return; 546 547 etype = 0; 548 mac_hdr_len = 0; 549 l4_proto = 0; 550 551 /* 552 * Firstly get the position of the ether_type/ether_tpid. 553 * Here we don't assume the ether (VLAN) header is fully included 554 * in one mblk fragment, so we go thourgh the fragments to parse 555 * the ether type. 556 */ 557 size = len = MBLK_LEN(mp); 558 offset = offsetof(struct ether_header, ether_type); 559 while (size <= offset) { 560 mp = mp->b_cont; 561 ASSERT(mp != NULL); 562 len = MBLK_LEN(mp); 563 size += len; 564 } 565 pos = mp->b_rptr + offset + len - size; 566 567 etype = ntohs(*(ushort_t *)(uintptr_t)pos); 568 if (etype == ETHERTYPE_VLAN) { 569 /* 570 * Get the position of the ether_type in VLAN header 571 */ 572 offset = offsetof(struct ether_vlan_header, ether_type); 573 while (size <= offset) { 574 mp = mp->b_cont; 575 ASSERT(mp != NULL); 576 len = MBLK_LEN(mp); 577 size += len; 578 } 579 pos = mp->b_rptr + offset + len - size; 580 581 etype = ntohs(*(ushort_t *)(uintptr_t)pos); 582 mac_hdr_len = sizeof (struct ether_vlan_header); 583 } else { 584 mac_hdr_len = sizeof (struct ether_header); 585 } 586 587 /* 588 * Here we don't assume the IP(V6) header is fully included in 589 * one mblk fragment, so we go thourgh the fragments to parse 590 * the protocol type. 591 */ 592 switch (etype) { 593 case ETHERTYPE_IP: 594 offset = offsetof(ipha_t, ipha_protocol) + mac_hdr_len; 595 while (size <= offset) { 596 mp = mp->b_cont; 597 ASSERT(mp != NULL); 598 len = MBLK_LEN(mp); 599 size += len; 600 } 601 pos = mp->b_rptr + offset + len - size; 602 603 l4_proto = *(uint8_t *)pos; 604 break; 605 case ETHERTYPE_IPV6: 606 offset = offsetof(ip6_t, ip6_nxt) + mac_hdr_len; 607 while (size <= offset) { 608 mp = mp->b_cont; 609 ASSERT(mp != NULL); 610 len = MBLK_LEN(mp); 611 size += len; 612 } 613 pos = mp->b_rptr + offset + len - size; 614 615 l4_proto = *(uint8_t *)pos; 616 break; 617 default: 618 /* Unrecoverable error */ 619 IGB_DEBUGLOG_0(NULL, "Ether type error with tx hcksum"); 620 return; 621 } 622 623 hcksum->mac_hdr_len = mac_hdr_len; 624 hcksum->ip_hdr_len = start; 625 hcksum->l4_proto = l4_proto; 626 } 627 628 /* 629 * igb_check_hcksum_context 630 * 631 * Check if a new context descriptor is needed 632 */ 633 static boolean_t 634 igb_check_hcksum_context(igb_tx_ring_t *tx_ring, hcksum_context_t *hcksum) 635 { 636 hcksum_context_t *last; 637 638 if (hcksum == NULL) 639 return (B_FALSE); 640 641 /* 642 * Compare the checksum data retrieved from the mblk and the 643 * stored checksum data of the last context descriptor. The data 644 * need to be checked are: 645 * hcksum_flags 646 * l4_proto 647 * mac_hdr_len 648 * ip_hdr_len 649 * Either one of the above data is changed, a new context descriptor 650 * will be needed. 651 */ 652 last = &tx_ring->hcksum_context; 653 654 if (hcksum->hcksum_flags != 0) { 655 if ((hcksum->hcksum_flags != last->hcksum_flags) || 656 (hcksum->l4_proto != last->l4_proto) || 657 (hcksum->mac_hdr_len != last->mac_hdr_len) || 658 (hcksum->ip_hdr_len != last->ip_hdr_len)) { 659 660 return (B_TRUE); 661 } 662 } 663 664 return (B_FALSE); 665 } 666 667 /* 668 * igb_fill_hcksum_context 669 * 670 * Fill the context descriptor with hardware checksum informations 671 */ 672 static void 673 igb_fill_hcksum_context(struct e1000_adv_tx_context_desc *ctx_tbd, 674 hcksum_context_t *hcksum) 675 { 676 /* 677 * Fill the context descriptor with the checksum 678 * context information we've got 679 */ 680 ctx_tbd->vlan_macip_lens = hcksum->ip_hdr_len; 681 ctx_tbd->vlan_macip_lens |= hcksum->mac_hdr_len << 682 E1000_ADVTXD_MACLEN_SHIFT; 683 684 ctx_tbd->type_tucmd_mlhl = 685 E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 686 687 if (hcksum->hcksum_flags & HCK_IPV4_HDRCKSUM) 688 ctx_tbd->type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 689 690 if (hcksum->hcksum_flags & HCK_PARTIALCKSUM) { 691 switch (hcksum->l4_proto) { 692 case IPPROTO_TCP: 693 ctx_tbd->type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 694 break; 695 case IPPROTO_UDP: 696 /* 697 * We don't have to explicitly set: 698 * ctx_tbd->type_tucmd_mlhl |= 699 * E1000_ADVTXD_TUCMD_L4T_UDP; 700 * Because E1000_ADVTXD_TUCMD_L4T_UDP == 0b 701 */ 702 break; 703 default: 704 /* Unrecoverable error */ 705 IGB_DEBUGLOG_0(NULL, "L4 type error with tx hcksum"); 706 break; 707 } 708 } 709 710 ctx_tbd->seqnum_seed = 0; 711 ctx_tbd->mss_l4len_idx = 0; 712 } 713 714 /* 715 * igb_tx_fill_ring 716 * 717 * Fill the tx descriptor ring with the data 718 */ 719 static int 720 igb_tx_fill_ring(igb_tx_ring_t *tx_ring, link_list_t *pending_list, 721 hcksum_context_t *hcksum) 722 { 723 struct e1000_hw *hw = &tx_ring->igb->hw; 724 boolean_t load_context; 725 uint32_t index, tcb_index, desc_num; 726 union e1000_adv_tx_desc *tbd, *first_tbd; 727 tx_control_block_t *tcb, *first_tcb; 728 uint32_t hcksum_flags; 729 int i; 730 igb_t *igb = tx_ring->igb; 731 732 ASSERT(mutex_owned(&tx_ring->tx_lock)); 733 734 tbd = NULL; 735 first_tbd = NULL; 736 first_tcb = NULL; 737 desc_num = 0; 738 hcksum_flags = 0; 739 load_context = B_FALSE; 740 741 /* 742 * Get the index of the first tx descriptor that will be filled, 743 * and the index of the first work list item that will be attached 744 * with the first used tx control block in the pending list. 745 * Note: the two indexes are the same. 746 */ 747 index = tx_ring->tbd_tail; 748 tcb_index = tx_ring->tbd_tail; 749 750 if (hcksum != NULL) { 751 hcksum_flags = hcksum->hcksum_flags; 752 753 /* 754 * Check if a new context descriptor is needed for this packet 755 */ 756 load_context = igb_check_hcksum_context(tx_ring, hcksum); 757 if (load_context) { 758 first_tcb = (tx_control_block_t *) 759 LIST_GET_HEAD(pending_list); 760 tbd = &tx_ring->tbd_ring[index]; 761 762 /* 763 * Fill the context descriptor with the 764 * hardware checksum offload informations. 765 */ 766 igb_fill_hcksum_context( 767 (struct e1000_adv_tx_context_desc *)tbd, hcksum); 768 769 index = NEXT_INDEX(index, 1, tx_ring->ring_size); 770 desc_num++; 771 772 /* 773 * Store the checksum context data if 774 * a new context descriptor is added 775 */ 776 tx_ring->hcksum_context = *hcksum; 777 } 778 } 779 780 first_tbd = &tx_ring->tbd_ring[index]; 781 782 /* 783 * Fill tx data descriptors with the data saved in the pending list. 784 * The tx control blocks in the pending list are added to the work list 785 * at the same time. 786 * 787 * The work list is strictly 1:1 corresponding to the descriptor ring. 788 * One item of the work list corresponds to one tx descriptor. Because 789 * one tx control block can span multiple tx descriptors, the tx 790 * control block will be added to the first work list item that 791 * corresponds to the first tx descriptor generated from that tx 792 * control block. 793 */ 794 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 795 while (tcb != NULL) { 796 797 for (i = 0; i < tcb->desc_num; i++) { 798 tbd = &tx_ring->tbd_ring[index]; 799 800 tbd->read.buffer_addr = tcb->desc[i].address; 801 tbd->read.cmd_type_len = tcb->desc[i].length; 802 803 tbd->read.cmd_type_len |= E1000_ADVTXD_DCMD_RS | 804 E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_DATA; 805 806 tbd->read.olinfo_status = 0; 807 808 index = NEXT_INDEX(index, 1, tx_ring->ring_size); 809 desc_num++; 810 } 811 812 if (first_tcb != NULL) { 813 /* 814 * Count the checksum context descriptor for 815 * the first tx control block. 816 */ 817 first_tcb->desc_num++; 818 first_tcb = NULL; 819 } 820 821 /* 822 * Add the tx control block to the work list 823 */ 824 ASSERT(tx_ring->work_list[tcb_index] == NULL); 825 tx_ring->work_list[tcb_index] = tcb; 826 827 tcb_index = index; 828 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 829 } 830 831 /* 832 * The Insert Ethernet CRC (IFCS) bit and the checksum fields are only 833 * valid in the first descriptor of the packet. 834 */ 835 ASSERT(first_tbd != NULL); 836 first_tbd->read.cmd_type_len |= E1000_ADVTXD_DCMD_IFCS; 837 838 /* Set hardware checksum bits */ 839 if (hcksum_flags != 0) { 840 if (hcksum_flags & HCK_IPV4_HDRCKSUM) 841 first_tbd->read.olinfo_status |= 842 E1000_TXD_POPTS_IXSM << 8; 843 if (hcksum_flags & HCK_PARTIALCKSUM) 844 first_tbd->read.olinfo_status |= 845 E1000_TXD_POPTS_TXSM << 8; 846 } 847 848 /* 849 * The last descriptor of packet needs End Of Packet (EOP), 850 * and Report Status (RS) bits set 851 */ 852 ASSERT(tbd != NULL); 853 tbd->read.cmd_type_len |= 854 E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS; 855 856 /* 857 * Sync the DMA buffer of the tx descriptor ring 858 */ 859 DMA_SYNC(&tx_ring->tbd_area, DDI_DMA_SYNC_FORDEV); 860 861 /* 862 * Update the number of the free tx descriptors. 863 * The mutual exclusion between the transmission and the recycling 864 * (for the tx descriptor ring and the work list) is implemented 865 * with the atomic operation on the number of the free tx descriptors. 866 * 867 * Note: we should always decrement the counter tbd_free before 868 * advancing the hardware TDT pointer to avoid the race condition - 869 * before the counter tbd_free is decremented, the transmit of the 870 * tx descriptors has done and the counter tbd_free is increased by 871 * the tx recycling. 872 */ 873 i = igb_atomic_reserve(&tx_ring->tbd_free, desc_num); 874 ASSERT(i >= 0); 875 876 tx_ring->tbd_tail = index; 877 878 /* 879 * Advance the hardware TDT pointer of the tx descriptor ring 880 */ 881 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), index); 882 883 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 884 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 885 } 886 887 return (desc_num); 888 } 889 890 /* 891 * igb_save_desc 892 * 893 * Save the address/length pair to the private array 894 * of the tx control block. The address/length pairs 895 * will be filled into the tx descriptor ring later. 896 */ 897 static void 898 igb_save_desc(tx_control_block_t *tcb, uint64_t address, size_t length) 899 { 900 sw_desc_t *desc; 901 902 desc = &tcb->desc[tcb->desc_num]; 903 desc->address = address; 904 desc->length = length; 905 906 tcb->desc_num++; 907 } 908 909 /* 910 * igb_tx_recycle_legacy 911 * 912 * Recycle the tx descriptors and tx control blocks. 913 * 914 * The work list is traversed to check if the corresponding 915 * tx descriptors have been transmitted. If so, the resources 916 * bound to the tx control blocks will be freed, and those 917 * tx control blocks will be returned to the free list. 918 */ 919 uint32_t 920 igb_tx_recycle_legacy(igb_tx_ring_t *tx_ring) 921 { 922 uint32_t index, last_index; 923 int desc_num; 924 boolean_t desc_done; 925 tx_control_block_t *tcb; 926 link_list_t pending_list; 927 igb_t *igb = tx_ring->igb; 928 929 /* 930 * The mutex_tryenter() is used to avoid unnecessary 931 * lock contention. 932 */ 933 if (mutex_tryenter(&tx_ring->recycle_lock) == 0) 934 return (0); 935 936 ASSERT(tx_ring->tbd_free <= tx_ring->ring_size); 937 938 if (tx_ring->tbd_free == tx_ring->ring_size) { 939 tx_ring->recycle_fail = 0; 940 tx_ring->stall_watchdog = 0; 941 mutex_exit(&tx_ring->recycle_lock); 942 return (0); 943 } 944 945 /* 946 * Sync the DMA buffer of the tx descriptor ring 947 */ 948 DMA_SYNC(&tx_ring->tbd_area, DDI_DMA_SYNC_FORKERNEL); 949 950 if (igb_check_dma_handle( 951 tx_ring->tbd_area.dma_handle) != DDI_FM_OK) { 952 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 953 } 954 955 LINK_LIST_INIT(&pending_list); 956 desc_num = 0; 957 index = tx_ring->tbd_head; /* Index of next tbd/tcb to recycle */ 958 959 tcb = tx_ring->work_list[index]; 960 ASSERT(tcb != NULL); 961 962 desc_done = B_TRUE; 963 while (desc_done && (tcb != NULL)) { 964 965 /* 966 * Get the last tx descriptor of the tx control block. 967 * If the last tx descriptor is done, it is done with 968 * all the tx descriptors of the tx control block. 969 * Then the tx control block and all the corresponding 970 * tx descriptors can be recycled. 971 */ 972 last_index = NEXT_INDEX(index, tcb->desc_num - 1, 973 tx_ring->ring_size); 974 975 /* 976 * Check if the Descriptor Done bit is set 977 */ 978 desc_done = tx_ring->tbd_ring[last_index].wb.status & 979 E1000_TXD_STAT_DD; 980 if (desc_done) { 981 /* 982 * Strip off the tx control block from the work list, 983 * and add it to the pending list. 984 */ 985 tx_ring->work_list[index] = NULL; 986 LIST_PUSH_TAIL(&pending_list, &tcb->link); 987 988 /* 989 * Count the total number of the tx descriptors recycled 990 */ 991 desc_num += tcb->desc_num; 992 993 /* 994 * Advance the index of the tx descriptor ring 995 */ 996 index = NEXT_INDEX(last_index, 1, tx_ring->ring_size); 997 998 tcb = tx_ring->work_list[index]; 999 } 1000 } 1001 1002 /* 1003 * If no tx descriptors are recycled, no need to do more processing 1004 */ 1005 if (desc_num == 0) { 1006 tx_ring->recycle_fail++; 1007 mutex_exit(&tx_ring->recycle_lock); 1008 return (0); 1009 } 1010 1011 tx_ring->recycle_fail = 0; 1012 tx_ring->stall_watchdog = 0; 1013 1014 /* 1015 * Update the head index of the tx descriptor ring 1016 */ 1017 tx_ring->tbd_head = index; 1018 1019 /* 1020 * Update the number of the free tx descriptors with atomic operations 1021 */ 1022 atomic_add_32(&tx_ring->tbd_free, desc_num); 1023 1024 mutex_exit(&tx_ring->recycle_lock); 1025 1026 /* 1027 * Free the resources used by the tx control blocks 1028 * in the pending list 1029 */ 1030 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 1031 while (tcb != NULL) { 1032 /* 1033 * Release the resources occupied by the tx control block 1034 */ 1035 igb_free_tcb(tcb); 1036 1037 tcb = (tx_control_block_t *) 1038 LIST_GET_NEXT(&pending_list, &tcb->link); 1039 } 1040 1041 /* 1042 * Add the tx control blocks in the pending list to the free list. 1043 */ 1044 igb_put_free_list(tx_ring, &pending_list); 1045 1046 return (desc_num); 1047 } 1048 1049 /* 1050 * igb_tx_recycle_head_wb 1051 * 1052 * Check the head write-back, and recycle all the transmitted 1053 * tx descriptors and tx control blocks. 1054 */ 1055 uint32_t 1056 igb_tx_recycle_head_wb(igb_tx_ring_t *tx_ring) 1057 { 1058 uint32_t index; 1059 uint32_t head_wb; 1060 int desc_num; 1061 tx_control_block_t *tcb; 1062 link_list_t pending_list; 1063 igb_t *igb = tx_ring->igb; 1064 1065 /* 1066 * The mutex_tryenter() is used to avoid unnecessary 1067 * lock contention. 1068 */ 1069 if (mutex_tryenter(&tx_ring->recycle_lock) == 0) 1070 return (0); 1071 1072 ASSERT(tx_ring->tbd_free <= tx_ring->ring_size); 1073 1074 if (tx_ring->tbd_free == tx_ring->ring_size) { 1075 tx_ring->recycle_fail = 0; 1076 tx_ring->stall_watchdog = 0; 1077 mutex_exit(&tx_ring->recycle_lock); 1078 return (0); 1079 } 1080 1081 /* 1082 * Sync the DMA buffer of the tx descriptor ring 1083 * 1084 * Note: For head write-back mode, the tx descriptors will not 1085 * be written back, but the head write-back value is stored at 1086 * the last extra tbd at the end of the DMA area, we still need 1087 * to sync the head write-back value for kernel. 1088 * 1089 * DMA_SYNC(&tx_ring->tbd_area, DDI_DMA_SYNC_FORKERNEL); 1090 */ 1091 (void) ddi_dma_sync(tx_ring->tbd_area.dma_handle, 1092 sizeof (union e1000_adv_tx_desc) * tx_ring->ring_size, 1093 sizeof (uint32_t), 1094 DDI_DMA_SYNC_FORKERNEL); 1095 1096 if (igb_check_dma_handle( 1097 tx_ring->tbd_area.dma_handle) != DDI_FM_OK) { 1098 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 1099 } 1100 1101 LINK_LIST_INIT(&pending_list); 1102 desc_num = 0; 1103 index = tx_ring->tbd_head; /* Next index to clean */ 1104 1105 /* 1106 * Get the value of head write-back 1107 */ 1108 head_wb = *tx_ring->tbd_head_wb; 1109 while (index != head_wb) { 1110 tcb = tx_ring->work_list[index]; 1111 ASSERT(tcb != NULL); 1112 1113 if (OFFSET(index, head_wb, tx_ring->ring_size) < 1114 tcb->desc_num) { 1115 /* 1116 * The current tx control block is not 1117 * completely transmitted, stop recycling 1118 */ 1119 break; 1120 } 1121 1122 /* 1123 * Strip off the tx control block from the work list, 1124 * and add it to the pending list. 1125 */ 1126 tx_ring->work_list[index] = NULL; 1127 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1128 1129 /* 1130 * Advance the index of the tx descriptor ring 1131 */ 1132 index = NEXT_INDEX(index, tcb->desc_num, tx_ring->ring_size); 1133 1134 /* 1135 * Count the total number of the tx descriptors recycled 1136 */ 1137 desc_num += tcb->desc_num; 1138 } 1139 1140 /* 1141 * If no tx descriptors are recycled, no need to do more processing 1142 */ 1143 if (desc_num == 0) { 1144 tx_ring->recycle_fail++; 1145 mutex_exit(&tx_ring->recycle_lock); 1146 return (0); 1147 } 1148 1149 tx_ring->recycle_fail = 0; 1150 tx_ring->stall_watchdog = 0; 1151 1152 /* 1153 * Update the head index of the tx descriptor ring 1154 */ 1155 tx_ring->tbd_head = index; 1156 1157 /* 1158 * Update the number of the free tx descriptors with atomic operations 1159 */ 1160 atomic_add_32(&tx_ring->tbd_free, desc_num); 1161 1162 mutex_exit(&tx_ring->recycle_lock); 1163 1164 /* 1165 * Free the resources used by the tx control blocks 1166 * in the pending list 1167 */ 1168 tcb = (tx_control_block_t *)LIST_GET_HEAD(&pending_list); 1169 while (tcb) { 1170 /* 1171 * Release the resources occupied by the tx control block 1172 */ 1173 igb_free_tcb(tcb); 1174 1175 tcb = (tx_control_block_t *) 1176 LIST_GET_NEXT(&pending_list, &tcb->link); 1177 } 1178 1179 /* 1180 * Add the tx control blocks in the pending list to the free list. 1181 */ 1182 igb_put_free_list(tx_ring, &pending_list); 1183 1184 return (desc_num); 1185 } 1186 1187 /* 1188 * igb_free_tcb - free up the tx control block 1189 * 1190 * Free the resources of the tx control block, including 1191 * unbind the previously bound DMA handle, and reset other 1192 * control fields. 1193 */ 1194 void 1195 igb_free_tcb(tx_control_block_t *tcb) 1196 { 1197 switch (tcb->tx_type) { 1198 case USE_COPY: 1199 /* 1200 * Reset the buffer length that is used for copy 1201 */ 1202 tcb->tx_buf.len = 0; 1203 break; 1204 case USE_DMA: 1205 /* 1206 * Release the DMA resource that is used for 1207 * DMA binding. 1208 */ 1209 (void) ddi_dma_unbind_handle(tcb->tx_dma_handle); 1210 break; 1211 default: 1212 break; 1213 } 1214 1215 /* 1216 * Free the mblk 1217 */ 1218 if (tcb->mp != NULL) { 1219 freemsg(tcb->mp); 1220 tcb->mp = NULL; 1221 } 1222 1223 tcb->tx_type = USE_NONE; 1224 tcb->frag_num = 0; 1225 tcb->desc_num = 0; 1226 } 1227 1228 /* 1229 * igb_get_free_list - Get a free tx control block from the free list 1230 * 1231 * The atomic operation on the number of the available tx control block 1232 * in the free list is used to keep this routine mutual exclusive with 1233 * the routine igb_put_check_list. 1234 */ 1235 static tx_control_block_t * 1236 igb_get_free_list(igb_tx_ring_t *tx_ring) 1237 { 1238 tx_control_block_t *tcb; 1239 1240 /* 1241 * Check and update the number of the free tx control block 1242 * in the free list. 1243 */ 1244 if (igb_atomic_reserve(&tx_ring->tcb_free, 1) < 0) 1245 return (NULL); 1246 1247 mutex_enter(&tx_ring->tcb_head_lock); 1248 1249 tcb = tx_ring->free_list[tx_ring->tcb_head]; 1250 ASSERT(tcb != NULL); 1251 tx_ring->free_list[tx_ring->tcb_head] = NULL; 1252 tx_ring->tcb_head = NEXT_INDEX(tx_ring->tcb_head, 1, 1253 tx_ring->free_list_size); 1254 1255 mutex_exit(&tx_ring->tcb_head_lock); 1256 1257 return (tcb); 1258 } 1259 1260 /* 1261 * igb_put_free_list 1262 * 1263 * Put a list of used tx control blocks back to the free list 1264 * 1265 * A mutex is used here to ensure the serialization. The mutual exclusion 1266 * between igb_get_free_list and igb_put_free_list is implemented with 1267 * the atomic operation on the counter tcb_free. 1268 */ 1269 void 1270 igb_put_free_list(igb_tx_ring_t *tx_ring, link_list_t *pending_list) 1271 { 1272 uint32_t index; 1273 int tcb_num; 1274 tx_control_block_t *tcb; 1275 1276 mutex_enter(&tx_ring->tcb_tail_lock); 1277 1278 index = tx_ring->tcb_tail; 1279 1280 tcb_num = 0; 1281 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 1282 while (tcb != NULL) { 1283 ASSERT(tx_ring->free_list[index] == NULL); 1284 tx_ring->free_list[index] = tcb; 1285 1286 tcb_num++; 1287 1288 index = NEXT_INDEX(index, 1, tx_ring->free_list_size); 1289 1290 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list); 1291 } 1292 1293 tx_ring->tcb_tail = index; 1294 1295 /* 1296 * Update the number of the free tx control block 1297 * in the free list. This operation must be placed 1298 * under the protection of the lock. 1299 */ 1300 atomic_add_32(&tx_ring->tcb_free, tcb_num); 1301 1302 mutex_exit(&tx_ring->tcb_tail_lock); 1303 } 1304