1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 28 * Use is subject to license terms. 29 */ 30 31 32 #include "igb_sw.h" 33 34 static char ident[] = "Intel 1Gb Ethernet"; 35 36 /* 37 * Local function protoypes 38 */ 39 static int igb_register_mac(igb_t *); 40 static int igb_identify_hardware(igb_t *); 41 static int igb_regs_map(igb_t *); 42 static void igb_init_properties(igb_t *); 43 static int igb_init_driver_settings(igb_t *); 44 static void igb_init_locks(igb_t *); 45 static void igb_destroy_locks(igb_t *); 46 static int igb_init(igb_t *); 47 static int igb_chip_start(igb_t *); 48 static void igb_chip_stop(igb_t *); 49 static int igb_reset(igb_t *); 50 static void igb_tx_clean(igb_t *); 51 static boolean_t igb_tx_drain(igb_t *); 52 static boolean_t igb_rx_drain(igb_t *); 53 static int igb_alloc_rings(igb_t *); 54 static int igb_init_rings(igb_t *); 55 static void igb_free_rings(igb_t *); 56 static void igb_fini_rings(igb_t *); 57 static void igb_setup_rings(igb_t *); 58 static void igb_setup_rx(igb_t *); 59 static void igb_setup_tx(igb_t *); 60 static void igb_setup_rx_ring(igb_rx_ring_t *); 61 static void igb_setup_tx_ring(igb_tx_ring_t *); 62 static void igb_setup_rss(igb_t *); 63 static void igb_init_unicst(igb_t *); 64 static void igb_setup_multicst(igb_t *); 65 static void igb_get_phy_state(igb_t *); 66 static void igb_get_conf(igb_t *); 67 static int igb_get_prop(igb_t *, char *, int, int, int); 68 static boolean_t igb_is_link_up(igb_t *); 69 static boolean_t igb_link_check(igb_t *); 70 static void igb_local_timer(void *); 71 static void igb_arm_watchdog_timer(igb_t *); 72 static void igb_start_watchdog_timer(igb_t *); 73 static void igb_restart_watchdog_timer(igb_t *); 74 static void igb_stop_watchdog_timer(igb_t *); 75 static void igb_disable_adapter_interrupts(igb_t *); 76 static void igb_enable_adapter_interrupts(igb_t *); 77 static boolean_t is_valid_mac_addr(uint8_t *); 78 static boolean_t igb_stall_check(igb_t *); 79 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 80 static void igb_set_external_loopback(igb_t *); 81 static void igb_set_internal_mac_loopback(igb_t *); 82 static void igb_set_internal_phy_loopback(igb_t *); 83 static void igb_set_internal_serdes_loopback(igb_t *); 84 static boolean_t igb_find_mac_address(igb_t *); 85 static int igb_alloc_intrs(igb_t *); 86 static int igb_alloc_intr_handles(igb_t *, int); 87 static int igb_add_intr_handlers(igb_t *); 88 static void igb_rem_intr_handlers(igb_t *); 89 static void igb_rem_intrs(igb_t *); 90 static int igb_enable_intrs(igb_t *); 91 static int igb_disable_intrs(igb_t *); 92 static void igb_setup_adapter_msix(igb_t *); 93 static uint_t igb_intr_legacy(void *, void *); 94 static uint_t igb_intr_msi(void *, void *); 95 static uint_t igb_intr_rx(void *, void *); 96 static uint_t igb_intr_tx_other(void *, void *); 97 static void igb_intr_rx_work(igb_rx_ring_t *); 98 static void igb_intr_tx_work(igb_tx_ring_t *); 99 static void igb_intr_other_work(igb_t *); 100 static void igb_get_driver_control(struct e1000_hw *); 101 static void igb_release_driver_control(struct e1000_hw *); 102 103 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 104 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 105 static int igb_resume(dev_info_t *); 106 static int igb_suspend(dev_info_t *); 107 static int igb_quiesce(dev_info_t *); 108 static void igb_unconfigure(dev_info_t *, igb_t *); 109 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 110 const void *); 111 static void igb_fm_init(igb_t *); 112 static void igb_fm_fini(igb_t *); 113 114 115 static struct cb_ops igb_cb_ops = { 116 nulldev, /* cb_open */ 117 nulldev, /* cb_close */ 118 nodev, /* cb_strategy */ 119 nodev, /* cb_print */ 120 nodev, /* cb_dump */ 121 nodev, /* cb_read */ 122 nodev, /* cb_write */ 123 nodev, /* cb_ioctl */ 124 nodev, /* cb_devmap */ 125 nodev, /* cb_mmap */ 126 nodev, /* cb_segmap */ 127 nochpoll, /* cb_chpoll */ 128 ddi_prop_op, /* cb_prop_op */ 129 NULL, /* cb_stream */ 130 D_MP | D_HOTPLUG, /* cb_flag */ 131 CB_REV, /* cb_rev */ 132 nodev, /* cb_aread */ 133 nodev /* cb_awrite */ 134 }; 135 136 static struct dev_ops igb_dev_ops = { 137 DEVO_REV, /* devo_rev */ 138 0, /* devo_refcnt */ 139 NULL, /* devo_getinfo */ 140 nulldev, /* devo_identify */ 141 nulldev, /* devo_probe */ 142 igb_attach, /* devo_attach */ 143 igb_detach, /* devo_detach */ 144 nodev, /* devo_reset */ 145 &igb_cb_ops, /* devo_cb_ops */ 146 NULL, /* devo_bus_ops */ 147 ddi_power, /* devo_power */ 148 igb_quiesce, /* devo_quiesce */ 149 }; 150 151 static struct modldrv igb_modldrv = { 152 &mod_driverops, /* Type of module. This one is a driver */ 153 ident, /* Discription string */ 154 &igb_dev_ops, /* driver ops */ 155 }; 156 157 static struct modlinkage igb_modlinkage = { 158 MODREV_1, &igb_modldrv, NULL 159 }; 160 161 /* Access attributes for register mapping */ 162 ddi_device_acc_attr_t igb_regs_acc_attr = { 163 DDI_DEVICE_ATTR_V0, 164 DDI_STRUCTURE_LE_ACC, 165 DDI_STRICTORDER_ACC, 166 DDI_FLAGERR_ACC 167 }; 168 169 #define IGB_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 170 171 static mac_callbacks_t igb_m_callbacks = { 172 IGB_M_CALLBACK_FLAGS, 173 igb_m_stat, 174 igb_m_start, 175 igb_m_stop, 176 igb_m_promisc, 177 igb_m_multicst, 178 igb_m_unicst, 179 igb_m_tx, 180 NULL, 181 igb_m_ioctl, 182 igb_m_getcapab 183 }; 184 185 186 /* 187 * Module Initialization Functions 188 */ 189 190 int 191 _init(void) 192 { 193 int status; 194 195 mac_init_ops(&igb_dev_ops, MODULE_NAME); 196 197 status = mod_install(&igb_modlinkage); 198 199 if (status != DDI_SUCCESS) { 200 mac_fini_ops(&igb_dev_ops); 201 } 202 203 return (status); 204 } 205 206 int 207 _fini(void) 208 { 209 int status; 210 211 status = mod_remove(&igb_modlinkage); 212 213 if (status == DDI_SUCCESS) { 214 mac_fini_ops(&igb_dev_ops); 215 } 216 217 return (status); 218 219 } 220 221 int 222 _info(struct modinfo *modinfop) 223 { 224 int status; 225 226 status = mod_info(&igb_modlinkage, modinfop); 227 228 return (status); 229 } 230 231 /* 232 * igb_attach - driver attach 233 * 234 * This function is the device specific initialization entry 235 * point. This entry point is required and must be written. 236 * The DDI_ATTACH command must be provided in the attach entry 237 * point. When attach() is called with cmd set to DDI_ATTACH, 238 * all normal kernel services (such as kmem_alloc(9F)) are 239 * available for use by the driver. 240 * 241 * The attach() function will be called once for each instance 242 * of the device on the system with cmd set to DDI_ATTACH. 243 * Until attach() succeeds, the only driver entry points which 244 * may be called are open(9E) and getinfo(9E). 245 */ 246 static int 247 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 248 { 249 igb_t *igb; 250 struct igb_osdep *osdep; 251 struct e1000_hw *hw; 252 int instance; 253 254 /* 255 * Check the command and perform corresponding operations 256 */ 257 switch (cmd) { 258 default: 259 return (DDI_FAILURE); 260 261 case DDI_RESUME: 262 return (igb_resume(devinfo)); 263 264 case DDI_ATTACH: 265 break; 266 } 267 268 /* Get the device instance */ 269 instance = ddi_get_instance(devinfo); 270 271 /* Allocate memory for the instance data structure */ 272 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 273 274 igb->dip = devinfo; 275 igb->instance = instance; 276 277 hw = &igb->hw; 278 osdep = &igb->osdep; 279 hw->back = osdep; 280 osdep->igb = igb; 281 282 /* Attach the instance pointer to the dev_info data structure */ 283 ddi_set_driver_private(devinfo, igb); 284 285 286 /* Initialize for fma support */ 287 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 288 0, 0x0f, 289 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 290 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 291 igb_fm_init(igb); 292 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 293 294 /* 295 * Map PCI config space registers 296 */ 297 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 298 igb_error(igb, "Failed to map PCI configurations"); 299 goto attach_fail; 300 } 301 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 302 303 /* 304 * Identify the chipset family 305 */ 306 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 307 igb_error(igb, "Failed to identify hardware"); 308 goto attach_fail; 309 } 310 311 /* 312 * Map device registers 313 */ 314 if (igb_regs_map(igb) != IGB_SUCCESS) { 315 igb_error(igb, "Failed to map device registers"); 316 goto attach_fail; 317 } 318 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 319 320 /* 321 * Initialize driver parameters 322 */ 323 igb_init_properties(igb); 324 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 325 326 /* 327 * Allocate interrupts 328 */ 329 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 330 igb_error(igb, "Failed to allocate interrupts"); 331 goto attach_fail; 332 } 333 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 334 335 /* 336 * Allocate rx/tx rings based on the ring numbers. 337 * The actual numbers of rx/tx rings are decided by the number of 338 * allocated interrupt vectors, so we should allocate the rings after 339 * interrupts are allocated. 340 */ 341 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 342 igb_error(igb, "Failed to allocate rx and tx rings"); 343 goto attach_fail; 344 } 345 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 346 347 /* 348 * Add interrupt handlers 349 */ 350 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 351 igb_error(igb, "Failed to add interrupt handlers"); 352 goto attach_fail; 353 } 354 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 355 356 /* 357 * Initialize driver parameters 358 */ 359 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 360 igb_error(igb, "Failed to initialize driver settings"); 361 goto attach_fail; 362 } 363 364 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 365 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 366 goto attach_fail; 367 } 368 369 /* 370 * Initialize mutexes for this device. 371 * Do this before enabling the interrupt handler and 372 * register the softint to avoid the condition where 373 * interrupt handler can try using uninitialized mutex 374 */ 375 igb_init_locks(igb); 376 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 377 378 /* 379 * Initialize chipset hardware 380 */ 381 if (igb_init(igb) != IGB_SUCCESS) { 382 igb_error(igb, "Failed to initialize adapter"); 383 goto attach_fail; 384 } 385 igb->attach_progress |= ATTACH_PROGRESS_INIT; 386 387 /* 388 * Initialize DMA and hardware settings for rx/tx rings 389 */ 390 if (igb_init_rings(igb) != IGB_SUCCESS) { 391 igb_error(igb, "Failed to initialize rings"); 392 goto attach_fail; 393 } 394 igb->attach_progress |= ATTACH_PROGRESS_INIT_RINGS; 395 396 /* 397 * Initialize statistics 398 */ 399 if (igb_init_stats(igb) != IGB_SUCCESS) { 400 igb_error(igb, "Failed to initialize statistics"); 401 goto attach_fail; 402 } 403 igb->attach_progress |= ATTACH_PROGRESS_STATS; 404 405 /* 406 * Initialize NDD parameters 407 */ 408 if (igb_nd_init(igb) != IGB_SUCCESS) { 409 igb_error(igb, "Failed to initialize ndd"); 410 goto attach_fail; 411 } 412 igb->attach_progress |= ATTACH_PROGRESS_NDD; 413 414 /* 415 * Register the driver to the MAC 416 */ 417 if (igb_register_mac(igb) != IGB_SUCCESS) { 418 igb_error(igb, "Failed to register MAC"); 419 goto attach_fail; 420 } 421 igb->attach_progress |= ATTACH_PROGRESS_MAC; 422 423 /* 424 * Now that mutex locks are initialized, and the chip is also 425 * initialized, enable interrupts. 426 */ 427 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 428 igb_error(igb, "Failed to enable DDI interrupts"); 429 goto attach_fail; 430 } 431 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 432 433 igb->igb_state |= IGB_INITIALIZED; 434 435 return (DDI_SUCCESS); 436 437 attach_fail: 438 igb_unconfigure(devinfo, igb); 439 return (DDI_FAILURE); 440 } 441 442 /* 443 * igb_detach - driver detach 444 * 445 * The detach() function is the complement of the attach routine. 446 * If cmd is set to DDI_DETACH, detach() is used to remove the 447 * state associated with a given instance of a device node 448 * prior to the removal of that instance from the system. 449 * 450 * The detach() function will be called once for each instance 451 * of the device for which there has been a successful attach() 452 * once there are no longer any opens on the device. 453 * 454 * Interrupts routine are disabled, All memory allocated by this 455 * driver are freed. 456 */ 457 static int 458 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 459 { 460 igb_t *igb; 461 462 /* 463 * Check detach command 464 */ 465 switch (cmd) { 466 default: 467 return (DDI_FAILURE); 468 469 case DDI_SUSPEND: 470 return (igb_suspend(devinfo)); 471 472 case DDI_DETACH: 473 break; 474 } 475 476 477 /* 478 * Get the pointer to the driver private data structure 479 */ 480 igb = (igb_t *)ddi_get_driver_private(devinfo); 481 if (igb == NULL) 482 return (DDI_FAILURE); 483 484 /* 485 * Unregister MAC. If failed, we have to fail the detach 486 */ 487 if (mac_unregister(igb->mac_hdl) != 0) { 488 igb_error(igb, "Failed to unregister MAC"); 489 return (DDI_FAILURE); 490 } 491 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 492 493 /* 494 * If the device is still running, it needs to be stopped first. 495 * This check is necessary because under some specific circumstances, 496 * the detach routine can be called without stopping the interface 497 * first. 498 */ 499 mutex_enter(&igb->gen_lock); 500 if (igb->igb_state & IGB_STARTED) { 501 igb->igb_state &= ~IGB_STARTED; 502 igb_stop(igb); 503 mutex_exit(&igb->gen_lock); 504 /* Disable and stop the watchdog timer */ 505 igb_disable_watchdog_timer(igb); 506 } else 507 mutex_exit(&igb->gen_lock); 508 509 /* 510 * Check if there are still rx buffers held by the upper layer. 511 * If so, fail the detach. 512 */ 513 if (!igb_rx_drain(igb)) 514 return (DDI_FAILURE); 515 516 /* 517 * Do the remaining unconfigure routines 518 */ 519 igb_unconfigure(devinfo, igb); 520 521 return (DDI_SUCCESS); 522 } 523 524 /* 525 * quiesce(9E) entry point. 526 * 527 * This function is called when the system is single-threaded at high 528 * PIL with preemption disabled. Therefore, this function must not be 529 * blocked. 530 * 531 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 532 * DDI_FAILURE indicates an error condition and should almost never happen. 533 */ 534 static int 535 igb_quiesce(dev_info_t *devinfo) 536 { 537 igb_t *igb; 538 struct e1000_hw *hw; 539 540 igb = (igb_t *)ddi_get_driver_private(devinfo); 541 542 if (igb == NULL) 543 return (DDI_FAILURE); 544 545 hw = &igb->hw; 546 547 /* 548 * Disable the adapter interrupts 549 */ 550 igb_disable_adapter_interrupts(igb); 551 552 /* Tell firmware driver is no longer in control */ 553 igb_release_driver_control(hw); 554 555 /* 556 * Reset the chipset 557 */ 558 (void) e1000_reset_hw(hw); 559 560 /* 561 * Reset PHY if possible 562 */ 563 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 564 (void) e1000_phy_hw_reset(hw); 565 566 return (DDI_SUCCESS); 567 } 568 569 570 static void 571 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 572 { 573 /* 574 * Disable interrupt 575 */ 576 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 577 (void) igb_disable_intrs(igb); 578 } 579 580 /* 581 * Unregister MAC 582 */ 583 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 584 (void) mac_unregister(igb->mac_hdl); 585 } 586 587 /* 588 * Free ndd parameters 589 */ 590 if (igb->attach_progress & ATTACH_PROGRESS_NDD) { 591 igb_nd_cleanup(igb); 592 } 593 594 /* 595 * Free statistics 596 */ 597 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 598 kstat_delete((kstat_t *)igb->igb_ks); 599 } 600 601 /* 602 * Remove interrupt handlers 603 */ 604 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 605 igb_rem_intr_handlers(igb); 606 } 607 608 /* 609 * Remove interrupts 610 */ 611 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 612 igb_rem_intrs(igb); 613 } 614 615 /* 616 * Remove driver properties 617 */ 618 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 619 (void) ddi_prop_remove_all(devinfo); 620 } 621 622 /* 623 * Release the DMA resources of rx/tx rings 624 */ 625 if (igb->attach_progress & ATTACH_PROGRESS_INIT_RINGS) { 626 igb_fini_rings(igb); 627 } 628 629 /* 630 * Stop the chipset 631 */ 632 if (igb->attach_progress & ATTACH_PROGRESS_INIT) { 633 mutex_enter(&igb->gen_lock); 634 igb_chip_stop(igb); 635 mutex_exit(&igb->gen_lock); 636 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 637 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 638 } 639 640 /* 641 * Free register handle 642 */ 643 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 644 if (igb->osdep.reg_handle != NULL) 645 ddi_regs_map_free(&igb->osdep.reg_handle); 646 } 647 648 /* 649 * Free PCI config handle 650 */ 651 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 652 if (igb->osdep.cfg_handle != NULL) 653 pci_config_teardown(&igb->osdep.cfg_handle); 654 } 655 656 /* 657 * Free locks 658 */ 659 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 660 igb_destroy_locks(igb); 661 } 662 663 /* 664 * Free the rx/tx rings 665 */ 666 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 667 igb_free_rings(igb); 668 } 669 670 /* 671 * Remove FMA 672 */ 673 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 674 igb_fm_fini(igb); 675 } 676 677 /* 678 * Free device specific structure 679 */ 680 e1000_remove_device(&igb->hw); 681 682 /* 683 * Free the driver data structure 684 */ 685 kmem_free(igb, sizeof (igb_t)); 686 687 ddi_set_driver_private(devinfo, NULL); 688 } 689 690 /* 691 * igb_register_mac - Register the driver and its function pointers with 692 * the GLD interface 693 */ 694 static int 695 igb_register_mac(igb_t *igb) 696 { 697 struct e1000_hw *hw = &igb->hw; 698 mac_register_t *mac; 699 int status; 700 701 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 702 return (IGB_FAILURE); 703 704 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 705 mac->m_driver = igb; 706 mac->m_dip = igb->dip; 707 mac->m_src_addr = hw->mac.addr; 708 mac->m_callbacks = &igb_m_callbacks; 709 mac->m_min_sdu = 0; 710 mac->m_max_sdu = igb->max_frame_size - 711 sizeof (struct ether_vlan_header) - ETHERFCSL; 712 mac->m_margin = VLAN_TAGSZ; 713 714 status = mac_register(mac, &igb->mac_hdl); 715 716 mac_free(mac); 717 718 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 719 } 720 721 /* 722 * igb_identify_hardware - Identify the type of the chipset 723 */ 724 static int 725 igb_identify_hardware(igb_t *igb) 726 { 727 struct e1000_hw *hw = &igb->hw; 728 struct igb_osdep *osdep = &igb->osdep; 729 730 /* 731 * Get the device id 732 */ 733 hw->vendor_id = 734 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 735 hw->device_id = 736 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 737 hw->revision_id = 738 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 739 hw->subsystem_device_id = 740 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 741 hw->subsystem_vendor_id = 742 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 743 744 /* 745 * Set the mac type of the adapter based on the device id 746 */ 747 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 748 return (IGB_FAILURE); 749 } 750 751 return (IGB_SUCCESS); 752 } 753 754 /* 755 * igb_regs_map - Map the device registers 756 */ 757 static int 758 igb_regs_map(igb_t *igb) 759 { 760 dev_info_t *devinfo = igb->dip; 761 struct e1000_hw *hw = &igb->hw; 762 struct igb_osdep *osdep = &igb->osdep; 763 off_t mem_size; 764 765 /* 766 * First get the size of device registers to be mapped. 767 */ 768 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 769 return (IGB_FAILURE); 770 } 771 772 /* 773 * Call ddi_regs_map_setup() to map registers 774 */ 775 if ((ddi_regs_map_setup(devinfo, 1, 776 (caddr_t *)&hw->hw_addr, 0, 777 mem_size, &igb_regs_acc_attr, 778 &osdep->reg_handle)) != DDI_SUCCESS) { 779 return (IGB_FAILURE); 780 } 781 782 return (IGB_SUCCESS); 783 } 784 785 /* 786 * igb_init_properties - Initialize driver properties 787 */ 788 static void 789 igb_init_properties(igb_t *igb) 790 { 791 /* 792 * Get conf file properties, including link settings 793 * jumbo frames, ring number, descriptor number, etc. 794 */ 795 igb_get_conf(igb); 796 } 797 798 /* 799 * igb_init_driver_settings - Initialize driver settings 800 * 801 * The settings include hardware function pointers, bus information, 802 * rx/tx rings settings, link state, and any other parameters that 803 * need to be setup during driver initialization. 804 */ 805 static int 806 igb_init_driver_settings(igb_t *igb) 807 { 808 struct e1000_hw *hw = &igb->hw; 809 igb_rx_ring_t *rx_ring; 810 igb_tx_ring_t *tx_ring; 811 uint32_t rx_size; 812 uint32_t tx_size; 813 int i; 814 815 /* 816 * Initialize chipset specific hardware function pointers 817 */ 818 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 819 return (IGB_FAILURE); 820 } 821 822 /* 823 * Get bus information 824 */ 825 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 826 return (IGB_FAILURE); 827 } 828 829 /* 830 * Set rx buffer size 831 * The IP header alignment room is counted in the calculation. 832 * The rx buffer size is in unit of 1K that is required by the 833 * chipset hardware. 834 */ 835 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 836 igb->rx_buf_size = ((rx_size >> 10) + 837 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 838 839 /* 840 * Set tx buffer size 841 */ 842 tx_size = igb->max_frame_size; 843 igb->tx_buf_size = ((tx_size >> 10) + 844 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 845 846 /* 847 * Initialize rx/tx rings parameters 848 */ 849 for (i = 0; i < igb->num_rx_rings; i++) { 850 rx_ring = &igb->rx_rings[i]; 851 rx_ring->index = i; 852 rx_ring->igb = igb; 853 854 rx_ring->ring_size = igb->rx_ring_size; 855 rx_ring->free_list_size = igb->rx_ring_size; 856 rx_ring->copy_thresh = igb->rx_copy_thresh; 857 rx_ring->limit_per_intr = igb->rx_limit_per_intr; 858 } 859 860 for (i = 0; i < igb->num_tx_rings; i++) { 861 tx_ring = &igb->tx_rings[i]; 862 tx_ring->index = i; 863 tx_ring->igb = igb; 864 if (igb->tx_head_wb_enable) 865 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 866 else 867 tx_ring->tx_recycle = igb_tx_recycle_legacy; 868 869 tx_ring->ring_size = igb->tx_ring_size; 870 tx_ring->free_list_size = igb->tx_ring_size + 871 (igb->tx_ring_size >> 1); 872 tx_ring->copy_thresh = igb->tx_copy_thresh; 873 tx_ring->recycle_thresh = igb->tx_recycle_thresh; 874 tx_ring->overload_thresh = igb->tx_overload_thresh; 875 tx_ring->resched_thresh = igb->tx_resched_thresh; 876 } 877 878 /* 879 * Initialize values of interrupt throttling rate 880 */ 881 for (i = 1; i < MAX_NUM_EITR; i++) 882 igb->intr_throttling[i] = igb->intr_throttling[0]; 883 884 /* 885 * The initial link state should be "unknown" 886 */ 887 igb->link_state = LINK_STATE_UNKNOWN; 888 889 return (IGB_SUCCESS); 890 } 891 892 /* 893 * igb_init_locks - Initialize locks 894 */ 895 static void 896 igb_init_locks(igb_t *igb) 897 { 898 igb_rx_ring_t *rx_ring; 899 igb_tx_ring_t *tx_ring; 900 int i; 901 902 for (i = 0; i < igb->num_rx_rings; i++) { 903 rx_ring = &igb->rx_rings[i]; 904 mutex_init(&rx_ring->rx_lock, NULL, 905 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 906 mutex_init(&rx_ring->recycle_lock, NULL, 907 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 908 } 909 910 for (i = 0; i < igb->num_tx_rings; i++) { 911 tx_ring = &igb->tx_rings[i]; 912 mutex_init(&tx_ring->tx_lock, NULL, 913 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 914 mutex_init(&tx_ring->recycle_lock, NULL, 915 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 916 mutex_init(&tx_ring->tcb_head_lock, NULL, 917 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 918 mutex_init(&tx_ring->tcb_tail_lock, NULL, 919 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 920 } 921 922 mutex_init(&igb->gen_lock, NULL, 923 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 924 925 mutex_init(&igb->watchdog_lock, NULL, 926 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 927 } 928 929 /* 930 * igb_destroy_locks - Destroy locks 931 */ 932 static void 933 igb_destroy_locks(igb_t *igb) 934 { 935 igb_rx_ring_t *rx_ring; 936 igb_tx_ring_t *tx_ring; 937 int i; 938 939 for (i = 0; i < igb->num_rx_rings; i++) { 940 rx_ring = &igb->rx_rings[i]; 941 mutex_destroy(&rx_ring->rx_lock); 942 mutex_destroy(&rx_ring->recycle_lock); 943 } 944 945 for (i = 0; i < igb->num_tx_rings; i++) { 946 tx_ring = &igb->tx_rings[i]; 947 mutex_destroy(&tx_ring->tx_lock); 948 mutex_destroy(&tx_ring->recycle_lock); 949 mutex_destroy(&tx_ring->tcb_head_lock); 950 mutex_destroy(&tx_ring->tcb_tail_lock); 951 } 952 953 mutex_destroy(&igb->gen_lock); 954 mutex_destroy(&igb->watchdog_lock); 955 } 956 957 static int 958 igb_resume(dev_info_t *devinfo) 959 { 960 igb_t *igb; 961 962 igb = (igb_t *)ddi_get_driver_private(devinfo); 963 if (igb == NULL) 964 return (DDI_FAILURE); 965 966 mutex_enter(&igb->gen_lock); 967 968 if (igb->igb_state & IGB_STARTED) { 969 if (igb_start(igb) != IGB_SUCCESS) { 970 mutex_exit(&igb->gen_lock); 971 return (DDI_FAILURE); 972 } 973 974 /* 975 * Enable and start the watchdog timer 976 */ 977 igb_enable_watchdog_timer(igb); 978 } 979 980 igb->igb_state &= ~IGB_SUSPENDED; 981 982 mutex_exit(&igb->gen_lock); 983 984 return (DDI_SUCCESS); 985 } 986 987 static int 988 igb_suspend(dev_info_t *devinfo) 989 { 990 igb_t *igb; 991 992 igb = (igb_t *)ddi_get_driver_private(devinfo); 993 if (igb == NULL) 994 return (DDI_FAILURE); 995 996 mutex_enter(&igb->gen_lock); 997 998 igb->igb_state |= IGB_SUSPENDED; 999 1000 igb_stop(igb); 1001 1002 mutex_exit(&igb->gen_lock); 1003 1004 /* 1005 * Disable and stop the watchdog timer 1006 */ 1007 igb_disable_watchdog_timer(igb); 1008 1009 return (DDI_SUCCESS); 1010 } 1011 1012 /* 1013 * igb_init - Initialize the device 1014 */ 1015 static int 1016 igb_init(igb_t *igb) 1017 { 1018 struct e1000_hw *hw = &igb->hw; 1019 uint32_t pba; 1020 uint32_t high_water; 1021 1022 mutex_enter(&igb->gen_lock); 1023 1024 /* 1025 * Reset chipset to put the hardware in a known state 1026 * before we try to do anything with the eeprom 1027 */ 1028 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1029 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1030 goto init_fail; 1031 } 1032 1033 /* 1034 * NVM validation 1035 */ 1036 if (e1000_validate_nvm_checksum(hw) < 0) { 1037 /* 1038 * Some PCI-E parts fail the first check due to 1039 * the link being in sleep state. Call it again, 1040 * if it fails a second time its a real issue. 1041 */ 1042 if (e1000_validate_nvm_checksum(hw) < 0) { 1043 igb_error(igb, 1044 "Invalid NVM checksum. Please contact " 1045 "the vendor to update the NVM."); 1046 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1047 goto init_fail; 1048 } 1049 } 1050 1051 /* 1052 * Set the FIFO size 1053 */ 1054 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1055 E1000_WRITE_REG(hw, E1000_PBA, pba); 1056 1057 /* 1058 * Setup flow control 1059 * 1060 * These parameters set thresholds for the adapter's generation(Tx) 1061 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1062 * settings. Flow control is enabled or disabled in the configuration 1063 * file. 1064 * High-water mark is set down from the top of the rx fifo (not 1065 * sensitive to max_frame_size) and low-water is set just below 1066 * high-water mark. 1067 * The high water mark must be low enough to fit one full frame above 1068 * it in the rx FIFO. Should be the lower of: 1069 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 1070 * frame. 1071 */ 1072 high_water = min(((pba << 10) * 9 / 10), 1073 ((pba << 10) - igb->max_frame_size)); 1074 1075 hw->fc.high_water = high_water & 0xFFF8; 1076 hw->fc.low_water = hw->fc.high_water - 8; 1077 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1078 hw->fc.send_xon = B_TRUE; 1079 1080 /* 1081 * Reset the chipset hardware the second time to validate 1082 * the PBA setting. 1083 */ 1084 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1085 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1086 goto init_fail; 1087 } 1088 1089 /* 1090 * Don't wait for auto-negotiation to complete 1091 */ 1092 hw->phy.autoneg_wait_to_complete = B_FALSE; 1093 1094 /* 1095 * Copper options 1096 */ 1097 if (hw->phy.media_type == e1000_media_type_copper) { 1098 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1099 hw->phy.disable_polarity_correction = B_FALSE; 1100 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1101 } 1102 1103 /* 1104 * Initialize link settings 1105 */ 1106 (void) igb_setup_link(igb, B_FALSE); 1107 1108 /* 1109 * Initialize the chipset hardware 1110 */ 1111 if (igb_chip_start(igb) != IGB_SUCCESS) { 1112 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1113 goto init_fail; 1114 } 1115 1116 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 1117 goto init_fail; 1118 } 1119 1120 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 1121 goto init_fail; 1122 } 1123 1124 mutex_exit(&igb->gen_lock); 1125 return (IGB_SUCCESS); 1126 1127 init_fail: 1128 /* 1129 * Reset PHY if possible 1130 */ 1131 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1132 (void) e1000_phy_hw_reset(hw); 1133 1134 mutex_exit(&igb->gen_lock); 1135 1136 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1137 1138 return (IGB_FAILURE); 1139 } 1140 1141 /* 1142 * igb_init_rings - Allocate DMA resources for all rx/tx rings and 1143 * initialize relevant hardware settings. 1144 */ 1145 static int 1146 igb_init_rings(igb_t *igb) 1147 { 1148 int i; 1149 1150 /* 1151 * Allocate buffers for all the rx/tx rings 1152 */ 1153 if (igb_alloc_dma(igb) != IGB_SUCCESS) 1154 return (IGB_FAILURE); 1155 1156 /* 1157 * Setup the rx/tx rings 1158 */ 1159 mutex_enter(&igb->gen_lock); 1160 1161 for (i = 0; i < igb->num_rx_rings; i++) 1162 mutex_enter(&igb->rx_rings[i].rx_lock); 1163 for (i = 0; i < igb->num_tx_rings; i++) 1164 mutex_enter(&igb->tx_rings[i].tx_lock); 1165 1166 igb_setup_rings(igb); 1167 1168 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1169 mutex_exit(&igb->tx_rings[i].tx_lock); 1170 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1171 mutex_exit(&igb->rx_rings[i].rx_lock); 1172 1173 mutex_exit(&igb->gen_lock); 1174 1175 return (IGB_SUCCESS); 1176 } 1177 1178 /* 1179 * igb_fini_rings - Release DMA resources of all rx/tx rings 1180 */ 1181 static void 1182 igb_fini_rings(igb_t *igb) 1183 { 1184 /* 1185 * Release the DMA/memory resources of rx/tx rings 1186 */ 1187 igb_free_dma(igb); 1188 } 1189 1190 /* 1191 * igb_chip_start - Initialize and start the chipset hardware 1192 */ 1193 static int 1194 igb_chip_start(igb_t *igb) 1195 { 1196 struct e1000_hw *hw = &igb->hw; 1197 int i; 1198 1199 ASSERT(mutex_owned(&igb->gen_lock)); 1200 1201 /* 1202 * Get the mac address 1203 * This function should handle SPARC case correctly. 1204 */ 1205 if (!igb_find_mac_address(igb)) { 1206 igb_error(igb, "Failed to get the mac address"); 1207 return (IGB_FAILURE); 1208 } 1209 1210 /* Validate mac address */ 1211 if (!is_valid_mac_addr(hw->mac.addr)) { 1212 igb_error(igb, "Invalid mac address"); 1213 return (IGB_FAILURE); 1214 } 1215 1216 /* Disable wakeup control by default */ 1217 E1000_WRITE_REG(hw, E1000_WUC, 0); 1218 1219 /* 1220 * Configure/Initialize hardware 1221 */ 1222 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1223 igb_error(igb, "Failed to initialize hardware"); 1224 return (IGB_FAILURE); 1225 } 1226 1227 /* 1228 * Make sure driver has control 1229 */ 1230 igb_get_driver_control(hw); 1231 1232 /* 1233 * Setup MSI-X interrupts 1234 */ 1235 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1236 igb_setup_adapter_msix(igb); 1237 1238 /* 1239 * Initialize unicast addresses. 1240 */ 1241 igb_init_unicst(igb); 1242 1243 /* 1244 * Setup and initialize the mctable structures. 1245 */ 1246 igb_setup_multicst(igb); 1247 1248 /* 1249 * Set interrupt throttling rate 1250 */ 1251 for (i = 0; i < igb->intr_cnt; i++) 1252 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1253 1254 /* Enable PCI-E master */ 1255 if (hw->bus.type == e1000_bus_type_pci_express) { 1256 e1000_enable_pciex_master(hw); 1257 } 1258 1259 /* 1260 * Save the state of the phy 1261 */ 1262 igb_get_phy_state(igb); 1263 1264 return (IGB_SUCCESS); 1265 } 1266 1267 /* 1268 * igb_chip_stop - Stop the chipset hardware 1269 */ 1270 static void 1271 igb_chip_stop(igb_t *igb) 1272 { 1273 struct e1000_hw *hw = &igb->hw; 1274 1275 ASSERT(mutex_owned(&igb->gen_lock)); 1276 1277 /* Tell firmware driver is no longer in control */ 1278 igb_release_driver_control(hw); 1279 1280 /* 1281 * Reset the chipset 1282 */ 1283 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1284 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1285 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1286 } 1287 1288 /* 1289 * Reset PHY if possible 1290 */ 1291 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1292 (void) e1000_phy_hw_reset(hw); 1293 } 1294 1295 /* 1296 * igb_reset - Reset the chipset and restart the driver. 1297 * 1298 * It involves stopping and re-starting the chipset, 1299 * and re-configuring the rx/tx rings. 1300 */ 1301 static int 1302 igb_reset(igb_t *igb) 1303 { 1304 int i; 1305 1306 mutex_enter(&igb->gen_lock); 1307 1308 ASSERT(igb->igb_state & IGB_STARTED); 1309 1310 /* 1311 * Disable the adapter interrupts to stop any rx/tx activities 1312 * before draining pending data and resetting hardware. 1313 */ 1314 igb_disable_adapter_interrupts(igb); 1315 1316 /* 1317 * Drain the pending transmit packets 1318 */ 1319 (void) igb_tx_drain(igb); 1320 1321 for (i = 0; i < igb->num_rx_rings; i++) 1322 mutex_enter(&igb->rx_rings[i].rx_lock); 1323 for (i = 0; i < igb->num_tx_rings; i++) 1324 mutex_enter(&igb->tx_rings[i].tx_lock); 1325 1326 /* 1327 * Stop the chipset hardware 1328 */ 1329 igb_chip_stop(igb); 1330 1331 /* 1332 * Clean the pending tx data/resources 1333 */ 1334 igb_tx_clean(igb); 1335 1336 /* 1337 * Start the chipset hardware 1338 */ 1339 if (igb_chip_start(igb) != IGB_SUCCESS) { 1340 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1341 goto reset_failure; 1342 } 1343 1344 /* 1345 * Setup the rx/tx rings 1346 */ 1347 igb_setup_rings(igb); 1348 1349 /* 1350 * Enable adapter interrupts 1351 * The interrupts must be enabled after the driver state is START 1352 */ 1353 igb_enable_adapter_interrupts(igb); 1354 1355 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1356 goto reset_failure; 1357 1358 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1359 goto reset_failure; 1360 1361 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1362 mutex_exit(&igb->tx_rings[i].tx_lock); 1363 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1364 mutex_exit(&igb->rx_rings[i].rx_lock); 1365 1366 mutex_exit(&igb->gen_lock); 1367 1368 return (IGB_SUCCESS); 1369 1370 reset_failure: 1371 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1372 mutex_exit(&igb->tx_rings[i].tx_lock); 1373 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1374 mutex_exit(&igb->rx_rings[i].rx_lock); 1375 1376 mutex_exit(&igb->gen_lock); 1377 1378 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1379 1380 return (IGB_FAILURE); 1381 } 1382 1383 /* 1384 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1385 */ 1386 static void 1387 igb_tx_clean(igb_t *igb) 1388 { 1389 igb_tx_ring_t *tx_ring; 1390 tx_control_block_t *tcb; 1391 link_list_t pending_list; 1392 uint32_t desc_num; 1393 int i, j; 1394 1395 LINK_LIST_INIT(&pending_list); 1396 1397 for (i = 0; i < igb->num_tx_rings; i++) { 1398 tx_ring = &igb->tx_rings[i]; 1399 1400 mutex_enter(&tx_ring->recycle_lock); 1401 1402 /* 1403 * Clean the pending tx data - the pending packets in the 1404 * work_list that have no chances to be transmitted again. 1405 * 1406 * We must ensure the chipset is stopped or the link is down 1407 * before cleaning the transmit packets. 1408 */ 1409 desc_num = 0; 1410 for (j = 0; j < tx_ring->ring_size; j++) { 1411 tcb = tx_ring->work_list[j]; 1412 if (tcb != NULL) { 1413 desc_num += tcb->desc_num; 1414 1415 tx_ring->work_list[j] = NULL; 1416 1417 igb_free_tcb(tcb); 1418 1419 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1420 } 1421 } 1422 1423 if (desc_num > 0) { 1424 atomic_add_32(&tx_ring->tbd_free, desc_num); 1425 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1426 1427 /* 1428 * Reset the head and tail pointers of the tbd ring; 1429 * Reset the head write-back if it is enabled. 1430 */ 1431 tx_ring->tbd_head = 0; 1432 tx_ring->tbd_tail = 0; 1433 if (igb->tx_head_wb_enable) 1434 *tx_ring->tbd_head_wb = 0; 1435 1436 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1437 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1438 } 1439 1440 mutex_exit(&tx_ring->recycle_lock); 1441 1442 /* 1443 * Add the tx control blocks in the pending list to 1444 * the free list. 1445 */ 1446 igb_put_free_list(tx_ring, &pending_list); 1447 } 1448 } 1449 1450 /* 1451 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1452 */ 1453 static boolean_t 1454 igb_tx_drain(igb_t *igb) 1455 { 1456 igb_tx_ring_t *tx_ring; 1457 boolean_t done; 1458 int i, j; 1459 1460 /* 1461 * Wait for a specific time to allow pending tx packets 1462 * to be transmitted. 1463 * 1464 * Check the counter tbd_free to see if transmission is done. 1465 * No lock protection is needed here. 1466 * 1467 * Return B_TRUE if all pending packets have been transmitted; 1468 * Otherwise return B_FALSE; 1469 */ 1470 for (i = 0; i < TX_DRAIN_TIME; i++) { 1471 1472 done = B_TRUE; 1473 for (j = 0; j < igb->num_tx_rings; j++) { 1474 tx_ring = &igb->tx_rings[j]; 1475 done = done && 1476 (tx_ring->tbd_free == tx_ring->ring_size); 1477 } 1478 1479 if (done) 1480 break; 1481 1482 msec_delay(1); 1483 } 1484 1485 return (done); 1486 } 1487 1488 /* 1489 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1490 */ 1491 static boolean_t 1492 igb_rx_drain(igb_t *igb) 1493 { 1494 igb_rx_ring_t *rx_ring; 1495 boolean_t done; 1496 int i, j; 1497 1498 /* 1499 * Polling the rx free list to check if those rx buffers held by 1500 * the upper layer are released. 1501 * 1502 * Check the counter rcb_free to see if all pending buffers are 1503 * released. No lock protection is needed here. 1504 * 1505 * Return B_TRUE if all pending buffers have been released; 1506 * Otherwise return B_FALSE; 1507 */ 1508 for (i = 0; i < RX_DRAIN_TIME; i++) { 1509 1510 done = B_TRUE; 1511 for (j = 0; j < igb->num_rx_rings; j++) { 1512 rx_ring = &igb->rx_rings[j]; 1513 done = done && 1514 (rx_ring->rcb_free == rx_ring->free_list_size); 1515 } 1516 1517 if (done) 1518 break; 1519 1520 msec_delay(1); 1521 } 1522 1523 return (done); 1524 } 1525 1526 /* 1527 * igb_start - Start the driver/chipset 1528 */ 1529 int 1530 igb_start(igb_t *igb) 1531 { 1532 int i; 1533 1534 ASSERT(mutex_owned(&igb->gen_lock)); 1535 1536 for (i = 0; i < igb->num_rx_rings; i++) 1537 mutex_enter(&igb->rx_rings[i].rx_lock); 1538 for (i = 0; i < igb->num_tx_rings; i++) 1539 mutex_enter(&igb->tx_rings[i].tx_lock); 1540 1541 /* 1542 * Start the chipset hardware 1543 */ 1544 if (igb_chip_start(igb) != IGB_SUCCESS) { 1545 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1546 goto start_failure; 1547 } 1548 1549 /* 1550 * Setup the rx/tx rings 1551 */ 1552 igb_setup_rings(igb); 1553 1554 /* 1555 * Enable adapter interrupts 1556 * The interrupts must be enabled after the driver state is START 1557 */ 1558 igb_enable_adapter_interrupts(igb); 1559 1560 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1561 goto start_failure; 1562 1563 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1564 goto start_failure; 1565 1566 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1567 mutex_exit(&igb->tx_rings[i].tx_lock); 1568 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1569 mutex_exit(&igb->rx_rings[i].rx_lock); 1570 1571 return (IGB_SUCCESS); 1572 1573 start_failure: 1574 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1575 mutex_exit(&igb->tx_rings[i].tx_lock); 1576 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1577 mutex_exit(&igb->rx_rings[i].rx_lock); 1578 1579 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1580 1581 return (IGB_FAILURE); 1582 } 1583 1584 /* 1585 * igb_stop - Stop the driver/chipset 1586 */ 1587 void 1588 igb_stop(igb_t *igb) 1589 { 1590 int i; 1591 1592 ASSERT(mutex_owned(&igb->gen_lock)); 1593 1594 /* 1595 * Disable the adapter interrupts 1596 */ 1597 igb_disable_adapter_interrupts(igb); 1598 1599 /* 1600 * Drain the pending tx packets 1601 */ 1602 (void) igb_tx_drain(igb); 1603 1604 for (i = 0; i < igb->num_rx_rings; i++) 1605 mutex_enter(&igb->rx_rings[i].rx_lock); 1606 for (i = 0; i < igb->num_tx_rings; i++) 1607 mutex_enter(&igb->tx_rings[i].tx_lock); 1608 1609 /* 1610 * Stop the chipset hardware 1611 */ 1612 igb_chip_stop(igb); 1613 1614 /* 1615 * Clean the pending tx data/resources 1616 */ 1617 igb_tx_clean(igb); 1618 1619 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1620 mutex_exit(&igb->tx_rings[i].tx_lock); 1621 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1622 mutex_exit(&igb->rx_rings[i].rx_lock); 1623 1624 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1625 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1626 } 1627 1628 /* 1629 * igb_alloc_rings - Allocate memory space for rx/tx rings 1630 */ 1631 static int 1632 igb_alloc_rings(igb_t *igb) 1633 { 1634 /* 1635 * Allocate memory space for rx rings 1636 */ 1637 igb->rx_rings = kmem_zalloc( 1638 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1639 KM_NOSLEEP); 1640 1641 if (igb->rx_rings == NULL) { 1642 return (IGB_FAILURE); 1643 } 1644 1645 /* 1646 * Allocate memory space for tx rings 1647 */ 1648 igb->tx_rings = kmem_zalloc( 1649 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1650 KM_NOSLEEP); 1651 1652 if (igb->tx_rings == NULL) { 1653 kmem_free(igb->rx_rings, 1654 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1655 igb->rx_rings = NULL; 1656 return (IGB_FAILURE); 1657 } 1658 1659 return (IGB_SUCCESS); 1660 } 1661 1662 /* 1663 * igb_free_rings - Free the memory space of rx/tx rings. 1664 */ 1665 static void 1666 igb_free_rings(igb_t *igb) 1667 { 1668 if (igb->rx_rings != NULL) { 1669 kmem_free(igb->rx_rings, 1670 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1671 igb->rx_rings = NULL; 1672 } 1673 1674 if (igb->tx_rings != NULL) { 1675 kmem_free(igb->tx_rings, 1676 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1677 igb->tx_rings = NULL; 1678 } 1679 } 1680 1681 /* 1682 * igb_setup_rings - Setup rx/tx rings 1683 */ 1684 static void 1685 igb_setup_rings(igb_t *igb) 1686 { 1687 /* 1688 * Setup the rx/tx rings, including the following: 1689 * 1690 * 1. Setup the descriptor ring and the control block buffers; 1691 * 2. Initialize necessary registers for receive/transmit; 1692 * 3. Initialize software pointers/parameters for receive/transmit; 1693 */ 1694 igb_setup_rx(igb); 1695 1696 igb_setup_tx(igb); 1697 1698 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1699 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1700 } 1701 1702 static void 1703 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1704 { 1705 igb_t *igb = rx_ring->igb; 1706 struct e1000_hw *hw = &igb->hw; 1707 rx_control_block_t *rcb; 1708 union e1000_adv_rx_desc *rbd; 1709 uint32_t size; 1710 uint32_t buf_low; 1711 uint32_t buf_high; 1712 uint32_t reg_val; 1713 int i; 1714 1715 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1716 ASSERT(mutex_owned(&igb->gen_lock)); 1717 1718 for (i = 0; i < igb->rx_ring_size; i++) { 1719 rcb = rx_ring->work_list[i]; 1720 rbd = &rx_ring->rbd_ring[i]; 1721 1722 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1723 rbd->read.hdr_addr = NULL; 1724 } 1725 1726 /* 1727 * Initialize the length register 1728 */ 1729 size = rx_ring->ring_size * sizeof (union e1000_adv_rx_desc); 1730 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1731 1732 /* 1733 * Initialize the base address registers 1734 */ 1735 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1736 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1737 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1738 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1739 1740 /* 1741 * Setup head & tail pointers 1742 */ 1743 E1000_WRITE_REG(hw, E1000_RDT(rx_ring->index), rx_ring->ring_size - 1); 1744 E1000_WRITE_REG(hw, E1000_RDH(rx_ring->index), 0); 1745 1746 rx_ring->rbd_next = 0; 1747 1748 /* 1749 * Note: Considering the case that the chipset is being reset 1750 * and there are still some buffers held by the upper layer, 1751 * we should not reset the values of rcb_head, rcb_tail and 1752 * rcb_free; 1753 */ 1754 if (igb->igb_state == IGB_UNKNOWN) { 1755 rx_ring->rcb_head = 0; 1756 rx_ring->rcb_tail = 0; 1757 rx_ring->rcb_free = rx_ring->free_list_size; 1758 } 1759 1760 /* 1761 * Setup the Receive Descriptor Control Register (RXDCTL) 1762 */ 1763 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1764 reg_val |= E1000_RXDCTL_QUEUE_ENABLE; 1765 reg_val &= 0xFFF00000; 1766 reg_val |= 16; /* pthresh */ 1767 reg_val |= 8 << 8; /* hthresh */ 1768 reg_val |= 1 << 16; /* wthresh */ 1769 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), reg_val); 1770 1771 /* 1772 * Setup the Split and Replication Receive Control Register. 1773 * Set the rx buffer size and the advanced descriptor type. 1774 */ 1775 reg_val = (igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1776 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 1777 1778 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), reg_val); 1779 } 1780 1781 static void 1782 igb_setup_rx(igb_t *igb) 1783 { 1784 igb_rx_ring_t *rx_ring; 1785 struct e1000_hw *hw = &igb->hw; 1786 uint32_t reg_val; 1787 int i; 1788 1789 /* 1790 * Setup the Receive Control Register (RCTL), and ENABLE the 1791 * receiver. The initial configuration is to: Enable the receiver, 1792 * accept broadcasts, discard bad packets (and long packets), 1793 * disable VLAN filter checking, set the receive descriptor 1794 * minimum threshold size to 1/2, and the receive buffer size to 1795 * 2k. 1796 */ 1797 reg_val = E1000_RCTL_EN | /* Enable Receive Unit */ 1798 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1799 E1000_RCTL_LPE | /* Large Packet Enable bit */ 1800 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1801 E1000_RCTL_RDMTS_HALF | 1802 E1000_RCTL_SECRC | /* Strip Ethernet CRC */ 1803 E1000_RCTL_LBM_NO; /* Loopback Mode = none */ 1804 1805 E1000_WRITE_REG(hw, E1000_RCTL, reg_val); 1806 1807 /* 1808 * igb_setup_rx_ring must be called after configuring RCTL 1809 */ 1810 for (i = 0; i < igb->num_rx_rings; i++) { 1811 rx_ring = &igb->rx_rings[i]; 1812 igb_setup_rx_ring(rx_ring); 1813 } 1814 1815 /* 1816 * Setup the Rx Long Packet Max Length register 1817 */ 1818 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 1819 1820 /* 1821 * Hardware checksum settings 1822 */ 1823 if (igb->rx_hcksum_enable) { 1824 reg_val = 1825 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 1826 E1000_RXCSUM_IPOFL; /* IP checksum */ 1827 1828 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); 1829 } 1830 1831 /* 1832 * Setup RSS for multiple receive queues 1833 */ 1834 if (igb->num_rx_rings > 1) 1835 igb_setup_rss(igb); 1836 } 1837 1838 static void 1839 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 1840 { 1841 igb_t *igb = tx_ring->igb; 1842 struct e1000_hw *hw = &igb->hw; 1843 uint32_t size; 1844 uint32_t buf_low; 1845 uint32_t buf_high; 1846 uint32_t reg_val; 1847 1848 ASSERT(mutex_owned(&tx_ring->tx_lock)); 1849 ASSERT(mutex_owned(&igb->gen_lock)); 1850 1851 /* 1852 * Initialize the length register 1853 */ 1854 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 1855 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 1856 1857 /* 1858 * Initialize the base address registers 1859 */ 1860 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 1861 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 1862 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 1863 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 1864 1865 /* 1866 * Setup head & tail pointers 1867 */ 1868 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 1869 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 1870 1871 /* 1872 * Setup head write-back 1873 */ 1874 if (igb->tx_head_wb_enable) { 1875 /* 1876 * The memory of the head write-back is allocated using 1877 * the extra tbd beyond the tail of the tbd ring. 1878 */ 1879 tx_ring->tbd_head_wb = (uint32_t *) 1880 ((uintptr_t)tx_ring->tbd_area.address + size); 1881 *tx_ring->tbd_head_wb = 0; 1882 1883 buf_low = (uint32_t) 1884 (tx_ring->tbd_area.dma_address + size); 1885 buf_high = (uint32_t) 1886 ((tx_ring->tbd_area.dma_address + size) >> 32); 1887 1888 /* Set the head write-back enable bit */ 1889 buf_low |= E1000_TX_HEAD_WB_ENABLE; 1890 1891 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 1892 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 1893 1894 /* 1895 * Turn off relaxed ordering for head write back or it will 1896 * cause problems with the tx recycling 1897 */ 1898 reg_val = E1000_READ_REG(hw, 1899 E1000_DCA_TXCTRL(tx_ring->index)); 1900 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 1901 E1000_WRITE_REG(hw, 1902 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 1903 } else { 1904 tx_ring->tbd_head_wb = NULL; 1905 } 1906 1907 tx_ring->tbd_head = 0; 1908 tx_ring->tbd_tail = 0; 1909 tx_ring->tbd_free = tx_ring->ring_size; 1910 1911 /* 1912 * Note: Considering the case that the chipset is being reset, 1913 * and there are still some buffers held by the upper layer, 1914 * we should not reset the values of tcb_head, tcb_tail. 1915 */ 1916 if (igb->igb_state == IGB_UNKNOWN) { 1917 tx_ring->tcb_head = 0; 1918 tx_ring->tcb_tail = 0; 1919 tx_ring->tcb_free = tx_ring->free_list_size; 1920 } else { 1921 ASSERT(tx_ring->tcb_free == tx_ring->free_list_size); 1922 } 1923 1924 /* 1925 * Initialize hardware checksum offload settings 1926 */ 1927 tx_ring->hcksum_context.hcksum_flags = 0; 1928 tx_ring->hcksum_context.ip_hdr_len = 0; 1929 tx_ring->hcksum_context.mac_hdr_len = 0; 1930 tx_ring->hcksum_context.l4_proto = 0; 1931 } 1932 1933 static void 1934 igb_setup_tx(igb_t *igb) 1935 { 1936 igb_tx_ring_t *tx_ring; 1937 struct e1000_hw *hw = &igb->hw; 1938 uint32_t reg_val; 1939 int i; 1940 1941 for (i = 0; i < igb->num_tx_rings; i++) { 1942 tx_ring = &igb->tx_rings[i]; 1943 igb_setup_tx_ring(tx_ring); 1944 } 1945 1946 /* 1947 * Setup the Transmit Control Register (TCTL) 1948 */ 1949 reg_val = E1000_TCTL_PSP | E1000_TCTL_EN | 1950 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 1951 (E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT) | 1952 E1000_TCTL_RTLC; 1953 1954 /* Enable the MULR bit */ 1955 if (hw->bus.type == e1000_bus_type_pci_express) 1956 reg_val |= E1000_TCTL_MULR; 1957 1958 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 1959 1960 /* 1961 * Set the default values for the Tx Inter Packet Gap timer 1962 */ 1963 if (hw->phy.media_type == e1000_media_type_fiber) 1964 reg_val = DEFAULT_82543_TIPG_IPGT_FIBER; 1965 else 1966 reg_val = DEFAULT_82543_TIPG_IPGT_COPPER; 1967 reg_val |= 1968 DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 1969 reg_val |= 1970 DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 1971 1972 E1000_WRITE_REG(hw, E1000_TIPG, reg_val); 1973 } 1974 1975 /* 1976 * igb_setup_rss - Setup receive-side scaling feature 1977 */ 1978 static void 1979 igb_setup_rss(igb_t *igb) 1980 { 1981 struct e1000_hw *hw = &igb->hw; 1982 uint32_t i, mrqc, rxcsum; 1983 int shift; 1984 uint32_t random; 1985 union e1000_reta { 1986 uint32_t dword; 1987 uint8_t bytes[4]; 1988 } reta; 1989 1990 /* Setup the Redirection Table */ 1991 shift = 6; 1992 for (i = 0; i < (32 * 4); i++) { 1993 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 1994 if ((i & 3) == 3) { 1995 E1000_WRITE_REG(hw, 1996 (E1000_RETA(0) + (i & ~3)), reta.dword); 1997 } 1998 } 1999 2000 /* Fill out hash function seeds */ 2001 for (i = 0; i < 10; i++) { 2002 (void) random_get_pseudo_bytes((uint8_t *)&random, 2003 sizeof (uint32_t)); 2004 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2005 } 2006 2007 /* Setup the Multiple Receive Queue Control register */ 2008 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2009 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2010 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2011 E1000_MRQC_RSS_FIELD_IPV6 | 2012 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2013 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2014 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2015 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2016 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2017 2018 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2019 2020 /* 2021 * Disable Packet Checksum to enable RSS for multiple receive queues. 2022 * 2023 * The Packet Checksum is not ethernet CRC. It is another kind of 2024 * checksum offloading provided by the 82575 chipset besides the IP 2025 * header checksum offloading and the TCP/UDP checksum offloading. 2026 * The Packet Checksum is by default computed over the entire packet 2027 * from the first byte of the DA through the last byte of the CRC, 2028 * including the Ethernet and IP headers. 2029 * 2030 * It is a hardware limitation that Packet Checksum is mutually 2031 * exclusive with RSS. 2032 */ 2033 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2034 rxcsum |= E1000_RXCSUM_PCSD; 2035 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2036 } 2037 2038 /* 2039 * igb_init_unicst - Initialize the unicast addresses 2040 */ 2041 static void 2042 igb_init_unicst(igb_t *igb) 2043 { 2044 struct e1000_hw *hw = &igb->hw; 2045 int slot; 2046 2047 /* 2048 * Here we should consider two situations: 2049 * 2050 * 1. Chipset is initialized the first time 2051 * Initialize the multiple unicast addresses, and 2052 * save the default mac address. 2053 * 2054 * 2. Chipset is reset 2055 * Recover the multiple unicast addresses from the 2056 * software data structure to the RAR registers. 2057 */ 2058 if (!igb->unicst_init) { 2059 /* Initialize the multiple unicast addresses */ 2060 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2061 2062 igb->unicst_avail = igb->unicst_total - 1; 2063 2064 /* Store the default mac address */ 2065 e1000_rar_set(hw, hw->mac.addr, 0); 2066 2067 bcopy(hw->mac.addr, igb->unicst_addr[0].mac.addr, 2068 ETHERADDRL); 2069 igb->unicst_addr[0].mac.set = 1; 2070 2071 for (slot = 1; slot < igb->unicst_total; slot++) 2072 igb->unicst_addr[slot].mac.set = 0; 2073 2074 igb->unicst_init = B_TRUE; 2075 } else { 2076 /* Recover the default mac address */ 2077 bcopy(igb->unicst_addr[0].mac.addr, hw->mac.addr, 2078 ETHERADDRL); 2079 2080 /* Store the default mac address */ 2081 e1000_rar_set(hw, hw->mac.addr, 0); 2082 2083 /* Re-configure the RAR registers */ 2084 for (slot = 1; slot < igb->unicst_total; slot++) 2085 e1000_rar_set(hw, 2086 igb->unicst_addr[slot].mac.addr, slot); 2087 } 2088 2089 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2090 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2091 } 2092 2093 /* 2094 * igb_unicst_set - Set the unicast address to the specified slot 2095 */ 2096 int 2097 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2098 mac_addr_slot_t slot) 2099 { 2100 struct e1000_hw *hw = &igb->hw; 2101 2102 ASSERT(mutex_owned(&igb->gen_lock)); 2103 2104 /* 2105 * Save the unicast address in the software data structure 2106 */ 2107 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2108 2109 /* 2110 * Set the unicast address to the RAR register 2111 */ 2112 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2113 2114 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2115 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2116 return (EIO); 2117 } 2118 2119 return (0); 2120 } 2121 2122 /* 2123 * igb_multicst_add - Add a multicst address 2124 */ 2125 int 2126 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2127 { 2128 ASSERT(mutex_owned(&igb->gen_lock)); 2129 2130 if ((multiaddr[0] & 01) == 0) { 2131 return (EINVAL); 2132 } 2133 2134 if (igb->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2135 return (ENOENT); 2136 } 2137 2138 bcopy(multiaddr, 2139 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2140 igb->mcast_count++; 2141 2142 /* 2143 * Update the multicast table in the hardware 2144 */ 2145 igb_setup_multicst(igb); 2146 2147 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2148 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2149 return (EIO); 2150 } 2151 2152 return (0); 2153 } 2154 2155 /* 2156 * igb_multicst_remove - Remove a multicst address 2157 */ 2158 int 2159 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2160 { 2161 int i; 2162 2163 ASSERT(mutex_owned(&igb->gen_lock)); 2164 2165 for (i = 0; i < igb->mcast_count; i++) { 2166 if (bcmp(multiaddr, &igb->mcast_table[i], 2167 ETHERADDRL) == 0) { 2168 for (i++; i < igb->mcast_count; i++) { 2169 igb->mcast_table[i - 1] = 2170 igb->mcast_table[i]; 2171 } 2172 igb->mcast_count--; 2173 break; 2174 } 2175 } 2176 2177 /* 2178 * Update the multicast table in the hardware 2179 */ 2180 igb_setup_multicst(igb); 2181 2182 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2183 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2184 return (EIO); 2185 } 2186 2187 return (0); 2188 } 2189 2190 /* 2191 * igb_setup_multicast - setup multicast data structures 2192 * 2193 * This routine initializes all of the multicast related structures 2194 * and save them in the hardware registers. 2195 */ 2196 static void 2197 igb_setup_multicst(igb_t *igb) 2198 { 2199 uint8_t *mc_addr_list; 2200 uint32_t mc_addr_count; 2201 struct e1000_hw *hw = &igb->hw; 2202 2203 ASSERT(mutex_owned(&igb->gen_lock)); 2204 2205 ASSERT(igb->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES); 2206 2207 mc_addr_list = (uint8_t *)igb->mcast_table; 2208 mc_addr_count = igb->mcast_count; 2209 2210 /* 2211 * Update the multicase addresses to the MTA registers 2212 */ 2213 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2214 igb->unicst_total, hw->mac.rar_entry_count); 2215 } 2216 2217 /* 2218 * igb_get_conf - Get driver configurations set in driver.conf 2219 * 2220 * This routine gets user-configured values out of the configuration 2221 * file igb.conf. 2222 * 2223 * For each configurable value, there is a minimum, a maximum, and a 2224 * default. 2225 * If user does not configure a value, use the default. 2226 * If user configures below the minimum, use the minumum. 2227 * If user configures above the maximum, use the maxumum. 2228 */ 2229 static void 2230 igb_get_conf(igb_t *igb) 2231 { 2232 struct e1000_hw *hw = &igb->hw; 2233 uint32_t default_mtu; 2234 uint32_t flow_control; 2235 2236 /* 2237 * igb driver supports the following user configurations: 2238 * 2239 * Link configurations: 2240 * adv_autoneg_cap 2241 * adv_1000fdx_cap 2242 * adv_100fdx_cap 2243 * adv_100hdx_cap 2244 * adv_10fdx_cap 2245 * adv_10hdx_cap 2246 * Note: 1000hdx is not supported. 2247 * 2248 * Jumbo frame configuration: 2249 * default_mtu 2250 * 2251 * Ethernet flow control configuration: 2252 * flow_control 2253 * 2254 * Multiple rings configurations: 2255 * tx_queue_number 2256 * tx_ring_size 2257 * rx_queue_number 2258 * rx_ring_size 2259 * 2260 * Call igb_get_prop() to get the value for a specific 2261 * configuration parameter. 2262 */ 2263 2264 /* 2265 * Link configurations 2266 */ 2267 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2268 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2269 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2270 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2271 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2272 PROP_ADV_100FDX_CAP, 0, 1, 1); 2273 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2274 PROP_ADV_100HDX_CAP, 0, 1, 1); 2275 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2276 PROP_ADV_10FDX_CAP, 0, 1, 1); 2277 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2278 PROP_ADV_10HDX_CAP, 0, 1, 1); 2279 2280 /* 2281 * Jumbo frame configurations 2282 */ 2283 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2284 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2285 2286 igb->max_frame_size = default_mtu + 2287 sizeof (struct ether_vlan_header) + ETHERFCSL; 2288 2289 /* 2290 * Ethernet flow control configuration 2291 */ 2292 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2293 e1000_fc_none, 4, e1000_fc_full); 2294 if (flow_control == 4) 2295 flow_control = e1000_fc_default; 2296 2297 hw->fc.type = flow_control; 2298 2299 /* 2300 * Multiple rings configurations 2301 */ 2302 igb->num_tx_rings = igb_get_prop(igb, PROP_TX_QUEUE_NUM, 2303 MIN_TX_QUEUE_NUM, MAX_TX_QUEUE_NUM, DEFAULT_TX_QUEUE_NUM); 2304 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2305 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2306 2307 igb->num_rx_rings = igb_get_prop(igb, PROP_RX_QUEUE_NUM, 2308 MIN_RX_QUEUE_NUM, MAX_RX_QUEUE_NUM, DEFAULT_RX_QUEUE_NUM); 2309 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2310 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2311 2312 /* 2313 * Tunable used to force an interrupt type. The only use is 2314 * for testing of the lesser interrupt types. 2315 * 0 = don't force interrupt type 2316 * 1 = force interrupt type MSIX 2317 * 2 = force interrupt type MSI 2318 * 3 = force interrupt type Legacy 2319 */ 2320 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2321 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2322 2323 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2324 0, 1, 1); 2325 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2326 0, 1, 1); 2327 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2328 0, 1, 0); 2329 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2330 0, 1, 1); 2331 2332 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2333 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2334 DEFAULT_TX_COPY_THRESHOLD); 2335 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2336 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2337 DEFAULT_TX_RECYCLE_THRESHOLD); 2338 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2339 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2340 DEFAULT_TX_OVERLOAD_THRESHOLD); 2341 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2342 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2343 DEFAULT_TX_RESCHED_THRESHOLD); 2344 2345 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2346 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2347 DEFAULT_RX_COPY_THRESHOLD); 2348 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2349 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2350 DEFAULT_RX_LIMIT_PER_INTR); 2351 2352 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2353 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2354 DEFAULT_INTR_THROTTLING); 2355 } 2356 2357 /* 2358 * igb_get_prop - Get a property value out of the configuration file igb.conf 2359 * 2360 * Caller provides the name of the property, a default value, a minimum 2361 * value, and a maximum value. 2362 * 2363 * Return configured value of the property, with default, minimum and 2364 * maximum properly applied. 2365 */ 2366 static int 2367 igb_get_prop(igb_t *igb, 2368 char *propname, /* name of the property */ 2369 int minval, /* minimum acceptable value */ 2370 int maxval, /* maximim acceptable value */ 2371 int defval) /* default value */ 2372 { 2373 int value; 2374 2375 /* 2376 * Call ddi_prop_get_int() to read the conf settings 2377 */ 2378 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2379 DDI_PROP_DONTPASS, propname, defval); 2380 2381 if (value > maxval) 2382 value = maxval; 2383 2384 if (value < minval) 2385 value = minval; 2386 2387 return (value); 2388 } 2389 2390 /* 2391 * igb_setup_link - Using the link properties to setup the link 2392 */ 2393 int 2394 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2395 { 2396 struct e1000_mac_info *mac; 2397 struct e1000_phy_info *phy; 2398 boolean_t invalid; 2399 2400 mac = &igb->hw.mac; 2401 phy = &igb->hw.phy; 2402 invalid = B_FALSE; 2403 2404 if (igb->param_adv_autoneg_cap == 1) { 2405 mac->autoneg = B_TRUE; 2406 phy->autoneg_advertised = 0; 2407 2408 /* 2409 * 1000hdx is not supported for autonegotiation 2410 */ 2411 if (igb->param_adv_1000fdx_cap == 1) 2412 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2413 2414 if (igb->param_adv_100fdx_cap == 1) 2415 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2416 2417 if (igb->param_adv_100hdx_cap == 1) 2418 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2419 2420 if (igb->param_adv_10fdx_cap == 1) 2421 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2422 2423 if (igb->param_adv_10hdx_cap == 1) 2424 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2425 2426 if (phy->autoneg_advertised == 0) 2427 invalid = B_TRUE; 2428 } else { 2429 mac->autoneg = B_FALSE; 2430 2431 /* 2432 * 1000fdx and 1000hdx are not supported for forced link 2433 */ 2434 if (igb->param_adv_100fdx_cap == 1) 2435 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2436 else if (igb->param_adv_100hdx_cap == 1) 2437 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2438 else if (igb->param_adv_10fdx_cap == 1) 2439 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2440 else if (igb->param_adv_10hdx_cap == 1) 2441 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2442 else 2443 invalid = B_TRUE; 2444 } 2445 2446 if (invalid) { 2447 igb_notice(igb, "Invalid link settings. Setup link to " 2448 "autonegotiation with full link capabilities."); 2449 mac->autoneg = B_TRUE; 2450 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2451 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2452 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2453 } 2454 2455 if (setup_hw) { 2456 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2457 return (IGB_FAILURE); 2458 } 2459 2460 return (IGB_SUCCESS); 2461 } 2462 2463 2464 /* 2465 * igb_is_link_up - Check if the link is up 2466 */ 2467 static boolean_t 2468 igb_is_link_up(igb_t *igb) 2469 { 2470 struct e1000_hw *hw = &igb->hw; 2471 boolean_t link_up; 2472 2473 ASSERT(mutex_owned(&igb->gen_lock)); 2474 2475 (void) e1000_check_for_link(hw); 2476 2477 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 2478 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 2479 (hw->mac.serdes_has_link))) { 2480 link_up = B_TRUE; 2481 } else { 2482 link_up = B_FALSE; 2483 } 2484 2485 return (link_up); 2486 } 2487 2488 /* 2489 * igb_link_check - Link status processing 2490 */ 2491 static boolean_t 2492 igb_link_check(igb_t *igb) 2493 { 2494 struct e1000_hw *hw = &igb->hw; 2495 uint16_t speed = 0, duplex = 0; 2496 boolean_t link_changed = B_FALSE; 2497 2498 ASSERT(mutex_owned(&igb->gen_lock)); 2499 2500 if (igb_is_link_up(igb)) { 2501 /* 2502 * The Link is up, check whether it was marked as down earlier 2503 */ 2504 if (igb->link_state != LINK_STATE_UP) { 2505 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 2506 igb->link_speed = speed; 2507 igb->link_duplex = duplex; 2508 igb->link_state = LINK_STATE_UP; 2509 igb->link_down_timeout = 0; 2510 link_changed = B_TRUE; 2511 } 2512 } else { 2513 if (igb->link_state != LINK_STATE_DOWN) { 2514 igb->link_speed = 0; 2515 igb->link_duplex = 0; 2516 igb->link_state = LINK_STATE_DOWN; 2517 link_changed = B_TRUE; 2518 } 2519 2520 if (igb->igb_state & IGB_STARTED) { 2521 if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2522 igb->link_down_timeout++; 2523 } else if (igb->link_down_timeout == 2524 MAX_LINK_DOWN_TIMEOUT) { 2525 igb_tx_clean(igb); 2526 igb->link_down_timeout++; 2527 } 2528 } 2529 } 2530 2531 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2532 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2533 2534 return (link_changed); 2535 } 2536 2537 /* 2538 * igb_local_timer - driver watchdog function 2539 * 2540 * This function will handle the transmit stall check, link status check and 2541 * other routines. 2542 */ 2543 static void 2544 igb_local_timer(void *arg) 2545 { 2546 igb_t *igb = (igb_t *)arg; 2547 struct e1000_hw *hw = &igb->hw; 2548 boolean_t link_changed; 2549 2550 if (igb_stall_check(igb)) { 2551 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 2552 igb->reset_count++; 2553 if (igb_reset(igb) == IGB_SUCCESS) 2554 ddi_fm_service_impact(igb->dip, 2555 DDI_SERVICE_RESTORED); 2556 } 2557 2558 mutex_enter(&igb->gen_lock); 2559 link_changed = igb_link_check(igb); 2560 mutex_exit(&igb->gen_lock); 2561 2562 if (link_changed) 2563 mac_link_update(igb->mac_hdl, igb->link_state); 2564 2565 /* 2566 * Set Timer Interrupts 2567 */ 2568 if (igb->intr_type != DDI_INTR_TYPE_MSIX) 2569 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2570 2571 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 2572 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2573 2574 igb_restart_watchdog_timer(igb); 2575 } 2576 2577 /* 2578 * igb_stall_check - check for transmit stall 2579 * 2580 * This function checks if the adapter is stalled (in transmit). 2581 * 2582 * It is called each time the watchdog timeout is invoked. 2583 * If the transmit descriptor reclaim continuously fails, 2584 * the watchdog value will increment by 1. If the watchdog 2585 * value exceeds the threshold, the igb is assumed to 2586 * have stalled and need to be reset. 2587 */ 2588 static boolean_t 2589 igb_stall_check(igb_t *igb) 2590 { 2591 igb_tx_ring_t *tx_ring; 2592 boolean_t result; 2593 int i; 2594 2595 if (igb->link_state != LINK_STATE_UP) 2596 return (B_FALSE); 2597 2598 /* 2599 * If any tx ring is stalled, we'll reset the chipset 2600 */ 2601 result = B_FALSE; 2602 for (i = 0; i < igb->num_tx_rings; i++) { 2603 tx_ring = &igb->tx_rings[i]; 2604 2605 if (tx_ring->recycle_fail > 0) 2606 tx_ring->stall_watchdog++; 2607 else 2608 tx_ring->stall_watchdog = 0; 2609 2610 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 2611 result = B_TRUE; 2612 break; 2613 } 2614 } 2615 2616 if (result) { 2617 tx_ring->stall_watchdog = 0; 2618 tx_ring->recycle_fail = 0; 2619 } 2620 2621 return (result); 2622 } 2623 2624 2625 /* 2626 * is_valid_mac_addr - Check if the mac address is valid 2627 */ 2628 static boolean_t 2629 is_valid_mac_addr(uint8_t *mac_addr) 2630 { 2631 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 2632 const uint8_t addr_test2[6] = 2633 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 2634 2635 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 2636 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 2637 return (B_FALSE); 2638 2639 return (B_TRUE); 2640 } 2641 2642 static boolean_t 2643 igb_find_mac_address(igb_t *igb) 2644 { 2645 struct e1000_hw *hw = &igb->hw; 2646 #ifdef __sparc 2647 uchar_t *bytes; 2648 struct ether_addr sysaddr; 2649 uint_t nelts; 2650 int err; 2651 boolean_t found = B_FALSE; 2652 2653 /* 2654 * The "vendor's factory-set address" may already have 2655 * been extracted from the chip, but if the property 2656 * "local-mac-address" is set we use that instead. 2657 * 2658 * We check whether it looks like an array of 6 2659 * bytes (which it should, if OBP set it). If we can't 2660 * make sense of it this way, we'll ignore it. 2661 */ 2662 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2663 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 2664 if (err == DDI_PROP_SUCCESS) { 2665 if (nelts == ETHERADDRL) { 2666 while (nelts--) 2667 hw->mac.addr[nelts] = bytes[nelts]; 2668 found = B_TRUE; 2669 } 2670 ddi_prop_free(bytes); 2671 } 2672 2673 /* 2674 * Look up the OBP property "local-mac-address?". If the user has set 2675 * 'local-mac-address? = false', use "the system address" instead. 2676 */ 2677 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 2678 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 2679 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 2680 if (localetheraddr(NULL, &sysaddr) != 0) { 2681 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 2682 found = B_TRUE; 2683 } 2684 } 2685 ddi_prop_free(bytes); 2686 } 2687 2688 /* 2689 * Finally(!), if there's a valid "mac-address" property (created 2690 * if we netbooted from this interface), we must use this instead 2691 * of any of the above to ensure that the NFS/install server doesn't 2692 * get confused by the address changing as Solaris takes over! 2693 */ 2694 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2695 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 2696 if (err == DDI_PROP_SUCCESS) { 2697 if (nelts == ETHERADDRL) { 2698 while (nelts--) 2699 hw->mac.addr[nelts] = bytes[nelts]; 2700 found = B_TRUE; 2701 } 2702 ddi_prop_free(bytes); 2703 } 2704 2705 if (found) { 2706 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 2707 return (B_TRUE); 2708 } 2709 #endif 2710 2711 /* 2712 * Read the device MAC address from the EEPROM 2713 */ 2714 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 2715 return (B_FALSE); 2716 2717 return (B_TRUE); 2718 } 2719 2720 #pragma inline(igb_arm_watchdog_timer) 2721 2722 static void 2723 igb_arm_watchdog_timer(igb_t *igb) 2724 { 2725 /* 2726 * Fire a watchdog timer 2727 */ 2728 igb->watchdog_tid = 2729 timeout(igb_local_timer, 2730 (void *)igb, 1 * drv_usectohz(1000000)); 2731 2732 } 2733 2734 /* 2735 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 2736 */ 2737 void 2738 igb_enable_watchdog_timer(igb_t *igb) 2739 { 2740 mutex_enter(&igb->watchdog_lock); 2741 2742 if (!igb->watchdog_enable) { 2743 igb->watchdog_enable = B_TRUE; 2744 igb->watchdog_start = B_TRUE; 2745 igb_arm_watchdog_timer(igb); 2746 } 2747 2748 mutex_exit(&igb->watchdog_lock); 2749 2750 } 2751 2752 /* 2753 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 2754 */ 2755 void 2756 igb_disable_watchdog_timer(igb_t *igb) 2757 { 2758 timeout_id_t tid; 2759 2760 mutex_enter(&igb->watchdog_lock); 2761 2762 igb->watchdog_enable = B_FALSE; 2763 igb->watchdog_start = B_FALSE; 2764 tid = igb->watchdog_tid; 2765 igb->watchdog_tid = 0; 2766 2767 mutex_exit(&igb->watchdog_lock); 2768 2769 if (tid != 0) 2770 (void) untimeout(tid); 2771 2772 } 2773 2774 /* 2775 * igb_start_watchdog_timer - Start the driver watchdog timer 2776 */ 2777 static void 2778 igb_start_watchdog_timer(igb_t *igb) 2779 { 2780 mutex_enter(&igb->watchdog_lock); 2781 2782 if (igb->watchdog_enable) { 2783 if (!igb->watchdog_start) { 2784 igb->watchdog_start = B_TRUE; 2785 igb_arm_watchdog_timer(igb); 2786 } 2787 } 2788 2789 mutex_exit(&igb->watchdog_lock); 2790 } 2791 2792 /* 2793 * igb_restart_watchdog_timer - Restart the driver watchdog timer 2794 */ 2795 static void 2796 igb_restart_watchdog_timer(igb_t *igb) 2797 { 2798 mutex_enter(&igb->watchdog_lock); 2799 2800 if (igb->watchdog_start) 2801 igb_arm_watchdog_timer(igb); 2802 2803 mutex_exit(&igb->watchdog_lock); 2804 } 2805 2806 /* 2807 * igb_stop_watchdog_timer - Stop the driver watchdog timer 2808 */ 2809 static void 2810 igb_stop_watchdog_timer(igb_t *igb) 2811 { 2812 timeout_id_t tid; 2813 2814 mutex_enter(&igb->watchdog_lock); 2815 2816 igb->watchdog_start = B_FALSE; 2817 tid = igb->watchdog_tid; 2818 igb->watchdog_tid = 0; 2819 2820 mutex_exit(&igb->watchdog_lock); 2821 2822 if (tid != 0) 2823 (void) untimeout(tid); 2824 } 2825 2826 /* 2827 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 2828 */ 2829 static void 2830 igb_disable_adapter_interrupts(igb_t *igb) 2831 { 2832 struct e1000_hw *hw = &igb->hw; 2833 2834 /* 2835 * Set the IMC register to mask all the interrupts, 2836 * including the tx interrupts. 2837 */ 2838 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2839 2840 /* 2841 * Additional disabling for MSI-X 2842 */ 2843 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2844 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 2845 E1000_WRITE_REG(hw, E1000_EIAC, 0x0); 2846 } 2847 2848 E1000_WRITE_FLUSH(hw); 2849 } 2850 2851 /* 2852 * igb_enable_adapter_interrupts - Mask/enable all hardware interrupts 2853 */ 2854 static void 2855 igb_enable_adapter_interrupts(igb_t *igb) 2856 { 2857 struct e1000_hw *hw = &igb->hw; 2858 uint32_t reg; 2859 2860 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2861 /* Interrupt enabling for MSI-X */ 2862 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 2863 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 2864 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 2865 2866 /* Enable MSI-X PBA support */ 2867 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2868 reg |= E1000_CTRL_EXT_PBA_CLR; 2869 2870 /* Non-selective interrupt clear-on-read */ 2871 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 2872 2873 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2874 } else { 2875 /* Interrupt enabling for MSI and legacy */ 2876 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 2877 } 2878 2879 E1000_WRITE_FLUSH(hw); 2880 } 2881 2882 /* 2883 * Loopback Support 2884 */ 2885 static lb_property_t lb_normal = 2886 { normal, "normal", IGB_LB_NONE }; 2887 static lb_property_t lb_external = 2888 { external, "External", IGB_LB_EXTERNAL }; 2889 static lb_property_t lb_mac = 2890 { internal, "MAC", IGB_LB_INTERNAL_MAC }; 2891 static lb_property_t lb_phy = 2892 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 2893 static lb_property_t lb_serdes = 2894 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 2895 2896 enum ioc_reply 2897 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 2898 { 2899 lb_info_sz_t *lbsp; 2900 lb_property_t *lbpp; 2901 struct e1000_hw *hw; 2902 uint32_t *lbmp; 2903 uint32_t size; 2904 uint32_t value; 2905 2906 hw = &igb->hw; 2907 2908 if (mp->b_cont == NULL) 2909 return (IOC_INVAL); 2910 2911 switch (iocp->ioc_cmd) { 2912 default: 2913 return (IOC_INVAL); 2914 2915 case LB_GET_INFO_SIZE: 2916 size = sizeof (lb_info_sz_t); 2917 if (iocp->ioc_count != size) 2918 return (IOC_INVAL); 2919 2920 value = sizeof (lb_normal); 2921 value += sizeof (lb_mac); 2922 if (hw->phy.media_type == e1000_media_type_copper) 2923 value += sizeof (lb_phy); 2924 else 2925 value += sizeof (lb_serdes); 2926 value += sizeof (lb_external); 2927 2928 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 2929 *lbsp = value; 2930 break; 2931 2932 case LB_GET_INFO: 2933 value = sizeof (lb_normal); 2934 value += sizeof (lb_mac); 2935 if (hw->phy.media_type == e1000_media_type_copper) 2936 value += sizeof (lb_phy); 2937 else 2938 value += sizeof (lb_serdes); 2939 value += sizeof (lb_external); 2940 2941 size = value; 2942 if (iocp->ioc_count != size) 2943 return (IOC_INVAL); 2944 2945 value = 0; 2946 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 2947 2948 lbpp[value++] = lb_normal; 2949 lbpp[value++] = lb_mac; 2950 if (hw->phy.media_type == e1000_media_type_copper) 2951 lbpp[value++] = lb_phy; 2952 else 2953 lbpp[value++] = lb_serdes; 2954 lbpp[value++] = lb_external; 2955 break; 2956 2957 case LB_GET_MODE: 2958 size = sizeof (uint32_t); 2959 if (iocp->ioc_count != size) 2960 return (IOC_INVAL); 2961 2962 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2963 *lbmp = igb->loopback_mode; 2964 break; 2965 2966 case LB_SET_MODE: 2967 size = 0; 2968 if (iocp->ioc_count != sizeof (uint32_t)) 2969 return (IOC_INVAL); 2970 2971 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2972 if (!igb_set_loopback_mode(igb, *lbmp)) 2973 return (IOC_INVAL); 2974 break; 2975 } 2976 2977 iocp->ioc_count = size; 2978 iocp->ioc_error = 0; 2979 2980 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2981 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2982 return (IOC_INVAL); 2983 } 2984 2985 return (IOC_REPLY); 2986 } 2987 2988 /* 2989 * igb_set_loopback_mode - Setup loopback based on the loopback mode 2990 */ 2991 static boolean_t 2992 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 2993 { 2994 struct e1000_hw *hw; 2995 2996 if (mode == igb->loopback_mode) 2997 return (B_TRUE); 2998 2999 hw = &igb->hw; 3000 3001 igb->loopback_mode = mode; 3002 3003 if (mode == IGB_LB_NONE) { 3004 /* Reset the chip */ 3005 hw->phy.autoneg_wait_to_complete = B_TRUE; 3006 (void) igb_reset(igb); 3007 hw->phy.autoneg_wait_to_complete = B_FALSE; 3008 return (B_TRUE); 3009 } 3010 3011 mutex_enter(&igb->gen_lock); 3012 3013 switch (mode) { 3014 default: 3015 mutex_exit(&igb->gen_lock); 3016 return (B_FALSE); 3017 3018 case IGB_LB_EXTERNAL: 3019 igb_set_external_loopback(igb); 3020 break; 3021 3022 case IGB_LB_INTERNAL_MAC: 3023 igb_set_internal_mac_loopback(igb); 3024 break; 3025 3026 case IGB_LB_INTERNAL_PHY: 3027 igb_set_internal_phy_loopback(igb); 3028 break; 3029 3030 case IGB_LB_INTERNAL_SERDES: 3031 igb_set_internal_serdes_loopback(igb); 3032 break; 3033 } 3034 3035 mutex_exit(&igb->gen_lock); 3036 3037 return (B_TRUE); 3038 } 3039 3040 /* 3041 * igb_set_external_loopback - Set the external loopback mode 3042 */ 3043 static void 3044 igb_set_external_loopback(igb_t *igb) 3045 { 3046 struct e1000_hw *hw; 3047 3048 hw = &igb->hw; 3049 3050 /* Set phy to known state */ 3051 (void) e1000_phy_hw_reset(hw); 3052 3053 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3054 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 3055 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3056 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3057 } 3058 3059 /* 3060 * igb_set_internal_mac_loopback - Set the internal MAC loopback mode 3061 */ 3062 static void 3063 igb_set_internal_mac_loopback(igb_t *igb) 3064 { 3065 struct e1000_hw *hw; 3066 uint32_t ctrl; 3067 uint32_t rctl; 3068 3069 hw = &igb->hw; 3070 3071 /* Set the Receive Control register */ 3072 rctl = E1000_READ_REG(hw, E1000_RCTL); 3073 rctl &= ~E1000_RCTL_LBM_TCVR; 3074 rctl |= E1000_RCTL_LBM_MAC; 3075 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 3076 3077 /* Set the Device Control register */ 3078 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3079 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3080 ctrl |= (E1000_CTRL_SLU | /* Force link up */ 3081 E1000_CTRL_FRCSPD | /* Force speed */ 3082 E1000_CTRL_FRCDPX | /* Force duplex */ 3083 E1000_CTRL_SPD_1000 | /* Force speed to 1000 */ 3084 E1000_CTRL_FD); /* Force full duplex */ 3085 ctrl &= ~E1000_CTRL_ILOS; /* Clear ILOS when there's a link */ 3086 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3087 } 3088 3089 /* 3090 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3091 */ 3092 static void 3093 igb_set_internal_phy_loopback(igb_t *igb) 3094 { 3095 struct e1000_hw *hw; 3096 uint32_t ctrl_ext; 3097 uint16_t phy_ctrl; 3098 uint16_t phy_pconf; 3099 3100 hw = &igb->hw; 3101 3102 /* Set link mode to PHY (00b) in the Extended Control register */ 3103 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3104 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3105 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3106 3107 /* 3108 * Set PHY control register (0x4140): 3109 * Set full duplex mode 3110 * Set loopback bit 3111 * Clear auto-neg enable bit 3112 * Set PHY speed 3113 */ 3114 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3115 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3116 3117 /* Set the link disable bit in the Port Configuration register */ 3118 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3119 phy_pconf |= (uint16_t)1 << 14; 3120 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3121 } 3122 3123 /* 3124 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3125 */ 3126 static void 3127 igb_set_internal_serdes_loopback(igb_t *igb) 3128 { 3129 struct e1000_hw *hw; 3130 uint32_t ctrl_ext; 3131 uint32_t ctrl; 3132 uint32_t pcs_lctl; 3133 uint32_t connsw; 3134 3135 hw = &igb->hw; 3136 3137 /* Set link mode to SerDes (11b) in the Extended Control register */ 3138 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3139 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3140 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3141 3142 /* Configure the SerDes to loopback */ 3143 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3144 3145 /* Set Device Control register */ 3146 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3147 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3148 E1000_CTRL_SLU); /* Force link up */ 3149 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3150 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3151 E1000_CTRL_LRST); /* Clear link reset */ 3152 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3153 3154 /* Set PCS Link Control register */ 3155 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3156 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3157 E1000_PCS_LCTL_FSD | 3158 E1000_PCS_LCTL_FDV_FULL | 3159 E1000_PCS_LCTL_FLV_LINK_UP); 3160 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3161 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3162 3163 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3164 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3165 connsw &= ~E1000_CONNSW_ENRGSRC; 3166 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3167 } 3168 3169 #pragma inline(igb_intr_rx_work) 3170 /* 3171 * igb_intr_rx_work - rx processing of ISR 3172 */ 3173 static void 3174 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3175 { 3176 mblk_t *mp; 3177 3178 mutex_enter(&rx_ring->rx_lock); 3179 mp = igb_rx(rx_ring); 3180 mutex_exit(&rx_ring->rx_lock); 3181 3182 if (mp != NULL) 3183 mac_rx(rx_ring->igb->mac_hdl, NULL, mp); 3184 } 3185 3186 #pragma inline(igb_intr_tx_work) 3187 /* 3188 * igb_intr_tx_work - tx processing of ISR 3189 */ 3190 static void 3191 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3192 { 3193 /* Recycle the tx descriptors */ 3194 tx_ring->tx_recycle(tx_ring); 3195 3196 /* Schedule the re-transmit */ 3197 if (tx_ring->reschedule && 3198 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3199 tx_ring->reschedule = B_FALSE; 3200 mac_tx_update(tx_ring->igb->mac_hdl); 3201 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3202 } 3203 } 3204 3205 #pragma inline(igb_intr_other_work) 3206 /* 3207 * igb_intr_other_work - other processing of ISR 3208 */ 3209 static void 3210 igb_intr_other_work(igb_t *igb) 3211 { 3212 boolean_t link_changed; 3213 3214 igb_stop_watchdog_timer(igb); 3215 3216 mutex_enter(&igb->gen_lock); 3217 3218 /* 3219 * Because we got a link-status-change interrupt, force 3220 * e1000_check_for_link() to look at phy 3221 */ 3222 igb->hw.mac.get_link_status = B_TRUE; 3223 3224 /* igb_link_check takes care of link status change */ 3225 link_changed = igb_link_check(igb); 3226 3227 /* Get new phy state */ 3228 igb_get_phy_state(igb); 3229 3230 mutex_exit(&igb->gen_lock); 3231 3232 if (link_changed) 3233 mac_link_update(igb->mac_hdl, igb->link_state); 3234 3235 igb_start_watchdog_timer(igb); 3236 } 3237 3238 /* 3239 * igb_intr_legacy - Interrupt handler for legacy interrupts 3240 */ 3241 static uint_t 3242 igb_intr_legacy(void *arg1, void *arg2) 3243 { 3244 igb_t *igb = (igb_t *)arg1; 3245 igb_tx_ring_t *tx_ring; 3246 uint32_t icr; 3247 mblk_t *mp; 3248 boolean_t tx_reschedule; 3249 boolean_t link_changed; 3250 uint_t result; 3251 3252 _NOTE(ARGUNUSED(arg2)); 3253 3254 mutex_enter(&igb->gen_lock); 3255 3256 if (igb->igb_state & IGB_SUSPENDED) { 3257 mutex_exit(&igb->gen_lock); 3258 return (DDI_INTR_UNCLAIMED); 3259 } 3260 3261 mp = NULL; 3262 tx_reschedule = B_FALSE; 3263 link_changed = B_FALSE; 3264 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3265 3266 if (icr & E1000_ICR_INT_ASSERTED) { 3267 /* 3268 * E1000_ICR_INT_ASSERTED bit was set: 3269 * Read(Clear) the ICR, claim this interrupt, 3270 * look for work to do. 3271 */ 3272 ASSERT(igb->num_rx_rings == 1); 3273 ASSERT(igb->num_tx_rings == 1); 3274 3275 if (icr & E1000_ICR_RXT0) { 3276 mp = igb_rx(&igb->rx_rings[0]); 3277 } 3278 3279 if (icr & E1000_ICR_TXDW) { 3280 tx_ring = &igb->tx_rings[0]; 3281 3282 /* Recycle the tx descriptors */ 3283 tx_ring->tx_recycle(tx_ring); 3284 3285 /* Schedule the re-transmit */ 3286 tx_reschedule = (tx_ring->reschedule && 3287 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3288 } 3289 3290 if (icr & E1000_ICR_LSC) { 3291 /* 3292 * Because we got a link-status-change interrupt, force 3293 * e1000_check_for_link() to look at phy 3294 */ 3295 igb->hw.mac.get_link_status = B_TRUE; 3296 3297 /* igb_link_check takes care of link status change */ 3298 link_changed = igb_link_check(igb); 3299 3300 /* Get new phy state */ 3301 igb_get_phy_state(igb); 3302 } 3303 3304 result = DDI_INTR_CLAIMED; 3305 } else { 3306 /* 3307 * E1000_ICR_INT_ASSERTED bit was not set: 3308 * Don't claim this interrupt. 3309 */ 3310 result = DDI_INTR_UNCLAIMED; 3311 } 3312 3313 mutex_exit(&igb->gen_lock); 3314 3315 /* 3316 * Do the following work outside of the gen_lock 3317 */ 3318 if (mp != NULL) 3319 mac_rx(igb->mac_hdl, NULL, mp); 3320 3321 if (tx_reschedule) { 3322 tx_ring->reschedule = B_FALSE; 3323 mac_tx_update(igb->mac_hdl); 3324 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3325 } 3326 3327 if (link_changed) 3328 mac_link_update(igb->mac_hdl, igb->link_state); 3329 3330 return (result); 3331 } 3332 3333 /* 3334 * igb_intr_msi - Interrupt handler for MSI 3335 */ 3336 static uint_t 3337 igb_intr_msi(void *arg1, void *arg2) 3338 { 3339 igb_t *igb = (igb_t *)arg1; 3340 uint32_t icr; 3341 3342 _NOTE(ARGUNUSED(arg2)); 3343 3344 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3345 3346 /* 3347 * For MSI interrupt, we have only one vector, 3348 * so we have only one rx ring and one tx ring enabled. 3349 */ 3350 ASSERT(igb->num_rx_rings == 1); 3351 ASSERT(igb->num_tx_rings == 1); 3352 3353 if (icr & E1000_ICR_RXT0) { 3354 igb_intr_rx_work(&igb->rx_rings[0]); 3355 } 3356 3357 if (icr & E1000_ICR_TXDW) { 3358 igb_intr_tx_work(&igb->tx_rings[0]); 3359 } 3360 3361 if (icr & E1000_ICR_LSC) { 3362 igb_intr_other_work(igb); 3363 } 3364 3365 return (DDI_INTR_CLAIMED); 3366 } 3367 3368 /* 3369 * igb_intr_rx - Interrupt handler for rx 3370 */ 3371 static uint_t 3372 igb_intr_rx(void *arg1, void *arg2) 3373 { 3374 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 3375 3376 _NOTE(ARGUNUSED(arg2)); 3377 3378 /* 3379 * Only used via MSI-X vector so don't check cause bits 3380 * and only clean the given ring. 3381 */ 3382 igb_intr_rx_work(rx_ring); 3383 3384 return (DDI_INTR_CLAIMED); 3385 } 3386 3387 /* 3388 * igb_intr_tx_other - Interrupt handler for both tx and other 3389 * 3390 * Always look for Tx cleanup work. Only look for other work if the right 3391 * bits are set in the Interrupt Cause Register. 3392 */ 3393 static uint_t 3394 igb_intr_tx_other(void *arg1, void *arg2) 3395 { 3396 igb_t *igb = (igb_t *)arg1; 3397 uint32_t icr; 3398 3399 _NOTE(ARGUNUSED(arg2)); 3400 3401 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3402 3403 /* 3404 * Always look for Tx cleanup work. We don't have separate 3405 * transmit vectors, so we have only one tx ring enabled. 3406 */ 3407 ASSERT(igb->num_tx_rings == 1); 3408 igb_intr_tx_work(&igb->tx_rings[0]); 3409 3410 /* 3411 * Check for "other" causes. 3412 */ 3413 if (icr & E1000_ICR_LSC) { 3414 igb_intr_other_work(igb); 3415 } 3416 3417 return (DDI_INTR_CLAIMED); 3418 } 3419 3420 /* 3421 * igb_alloc_intrs - Allocate interrupts for the driver 3422 * 3423 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3424 * if not successful, try Legacy. 3425 * igb->intr_force can be used to force sequence to start with 3426 * any of the 3 types. 3427 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3428 */ 3429 static int 3430 igb_alloc_intrs(igb_t *igb) 3431 { 3432 dev_info_t *devinfo; 3433 int intr_types; 3434 int rc; 3435 3436 devinfo = igb->dip; 3437 3438 /* Get supported interrupt types */ 3439 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3440 3441 if (rc != DDI_SUCCESS) { 3442 igb_log(igb, 3443 "Get supported interrupt types failed: %d", rc); 3444 return (IGB_FAILURE); 3445 } 3446 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 3447 3448 igb->intr_type = 0; 3449 3450 /* Install MSI-X interrupts */ 3451 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3452 (igb->intr_force <= IGB_INTR_MSIX)) { 3453 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 3454 3455 if (rc == IGB_SUCCESS) 3456 return (IGB_SUCCESS); 3457 3458 igb_log(igb, 3459 "Allocate MSI-X failed, trying MSI interrupts..."); 3460 } 3461 3462 /* MSI-X not used, force rings to 1 */ 3463 igb->num_rx_rings = 1; 3464 igb->num_tx_rings = 1; 3465 igb_log(igb, 3466 "MSI-X not used, force rx and tx queue number to 1"); 3467 3468 /* Install MSI interrupts */ 3469 if ((intr_types & DDI_INTR_TYPE_MSI) && 3470 (igb->intr_force <= IGB_INTR_MSI)) { 3471 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 3472 3473 if (rc == IGB_SUCCESS) 3474 return (IGB_SUCCESS); 3475 3476 igb_log(igb, 3477 "Allocate MSI failed, trying Legacy interrupts..."); 3478 } 3479 3480 /* Install legacy interrupts */ 3481 if (intr_types & DDI_INTR_TYPE_FIXED) { 3482 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 3483 3484 if (rc == IGB_SUCCESS) 3485 return (IGB_SUCCESS); 3486 3487 igb_log(igb, 3488 "Allocate Legacy interrupts failed"); 3489 } 3490 3491 /* If none of the 3 types succeeded, return failure */ 3492 return (IGB_FAILURE); 3493 } 3494 3495 /* 3496 * igb_alloc_intr_handles - Allocate interrupt handles. 3497 * 3498 * For legacy and MSI, only 1 handle is needed. For MSI-X, 3499 * if fewer than 2 handles are available, return failure. 3500 * Upon success, this sets the number of Rx rings to a number that 3501 * matches the handles available for Rx interrupts. 3502 */ 3503 static int 3504 igb_alloc_intr_handles(igb_t *igb, int intr_type) 3505 { 3506 dev_info_t *devinfo; 3507 int request, count, avail, actual; 3508 int rx_rings, minimum; 3509 int rc; 3510 3511 devinfo = igb->dip; 3512 3513 /* 3514 * Currently only 1 tx ring is supported. More tx rings 3515 * will be supported with future enhancement. 3516 */ 3517 if (igb->num_tx_rings > 1) { 3518 igb->num_tx_rings = 1; 3519 igb_log(igb, 3520 "Use only 1 MSI-X vector for tx, " 3521 "force tx queue number to 1"); 3522 } 3523 3524 switch (intr_type) { 3525 case DDI_INTR_TYPE_FIXED: 3526 request = 1; /* Request 1 legacy interrupt handle */ 3527 minimum = 1; 3528 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 3529 break; 3530 3531 case DDI_INTR_TYPE_MSI: 3532 request = 1; /* Request 1 MSI interrupt handle */ 3533 minimum = 1; 3534 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 3535 break; 3536 3537 case DDI_INTR_TYPE_MSIX: 3538 /* 3539 * Best number of vectors for the adapter is 3540 * # rx rings + # tx rings + 1 for other 3541 * But currently we only support number of vectors of 3542 * # rx rings + 1 for tx & other 3543 */ 3544 request = igb->num_rx_rings + 1; 3545 minimum = 2; 3546 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 3547 break; 3548 3549 default: 3550 igb_log(igb, 3551 "invalid call to igb_alloc_intr_handles(): %d\n", 3552 intr_type); 3553 return (IGB_FAILURE); 3554 } 3555 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 3556 request, minimum); 3557 3558 /* 3559 * Get number of supported interrupts 3560 */ 3561 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 3562 if ((rc != DDI_SUCCESS) || (count < minimum)) { 3563 igb_log(igb, 3564 "Get supported interrupt number failed. " 3565 "Return: %d, count: %d", rc, count); 3566 return (IGB_FAILURE); 3567 } 3568 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 3569 3570 /* 3571 * Get number of available interrupts 3572 */ 3573 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 3574 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 3575 igb_log(igb, 3576 "Get available interrupt number failed. " 3577 "Return: %d, available: %d", rc, avail); 3578 return (IGB_FAILURE); 3579 } 3580 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 3581 3582 if (avail < request) { 3583 igb_log(igb, "Request %d handles, %d available", 3584 request, avail); 3585 request = avail; 3586 } 3587 3588 actual = 0; 3589 igb->intr_cnt = 0; 3590 3591 /* 3592 * Allocate an array of interrupt handles 3593 */ 3594 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3595 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3596 3597 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 3598 request, &actual, DDI_INTR_ALLOC_NORMAL); 3599 if (rc != DDI_SUCCESS) { 3600 igb_log(igb, "Allocate interrupts failed. " 3601 "return: %d, request: %d, actual: %d", 3602 rc, request, actual); 3603 goto alloc_handle_fail; 3604 } 3605 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 3606 3607 igb->intr_cnt = actual; 3608 3609 if (actual < minimum) { 3610 igb_log(igb, "Insufficient interrupt handles allocated: %d", 3611 actual); 3612 goto alloc_handle_fail; 3613 } 3614 3615 /* 3616 * For MSI-X, actual might force us to reduce number of rx rings 3617 */ 3618 if (intr_type == DDI_INTR_TYPE_MSIX) { 3619 rx_rings = actual - 1; 3620 if (rx_rings < igb->num_rx_rings) { 3621 igb_log(igb, 3622 "MSI-X vectors force Rx queue number to %d", 3623 rx_rings); 3624 igb->num_rx_rings = rx_rings; 3625 } 3626 } 3627 3628 /* 3629 * Get priority for first vector, assume remaining are all the same 3630 */ 3631 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3632 if (rc != DDI_SUCCESS) { 3633 igb_log(igb, 3634 "Get interrupt priority failed: %d", rc); 3635 goto alloc_handle_fail; 3636 } 3637 3638 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3639 if (rc != DDI_SUCCESS) { 3640 igb_log(igb, 3641 "Get interrupt cap failed: %d", rc); 3642 goto alloc_handle_fail; 3643 } 3644 3645 igb->intr_type = intr_type; 3646 3647 return (IGB_SUCCESS); 3648 3649 alloc_handle_fail: 3650 igb_rem_intrs(igb); 3651 3652 return (IGB_FAILURE); 3653 } 3654 3655 /* 3656 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 3657 * 3658 * Before adding the interrupt handlers, the interrupt vectors have 3659 * been allocated, and the rx/tx rings have also been allocated. 3660 */ 3661 static int 3662 igb_add_intr_handlers(igb_t *igb) 3663 { 3664 igb_rx_ring_t *rx_ring; 3665 int vector; 3666 int rc; 3667 int i; 3668 3669 vector = 0; 3670 3671 switch (igb->intr_type) { 3672 case DDI_INTR_TYPE_MSIX: 3673 /* Add interrupt handler for tx + other */ 3674 rc = ddi_intr_add_handler(igb->htable[vector], 3675 (ddi_intr_handler_t *)igb_intr_tx_other, 3676 (void *)igb, NULL); 3677 if (rc != DDI_SUCCESS) { 3678 igb_log(igb, 3679 "Add tx/other interrupt handler failed: %d", rc); 3680 return (IGB_FAILURE); 3681 } 3682 vector++; 3683 3684 /* Add interrupt handler for each rx ring */ 3685 for (i = 0; i < igb->num_rx_rings; i++) { 3686 rx_ring = &igb->rx_rings[i]; 3687 3688 rc = ddi_intr_add_handler(igb->htable[vector], 3689 (ddi_intr_handler_t *)igb_intr_rx, 3690 (void *)rx_ring, NULL); 3691 3692 if (rc != DDI_SUCCESS) { 3693 igb_log(igb, 3694 "Add rx interrupt handler failed. " 3695 "return: %d, rx ring: %d", rc, i); 3696 for (vector--; vector >= 0; vector--) { 3697 (void) ddi_intr_remove_handler( 3698 igb->htable[vector]); 3699 } 3700 return (IGB_FAILURE); 3701 } 3702 3703 rx_ring->intr_vector = vector; 3704 3705 vector++; 3706 } 3707 break; 3708 3709 case DDI_INTR_TYPE_MSI: 3710 /* Add interrupt handlers for the only vector */ 3711 rc = ddi_intr_add_handler(igb->htable[vector], 3712 (ddi_intr_handler_t *)igb_intr_msi, 3713 (void *)igb, NULL); 3714 3715 if (rc != DDI_SUCCESS) { 3716 igb_log(igb, 3717 "Add MSI interrupt handler failed: %d", rc); 3718 return (IGB_FAILURE); 3719 } 3720 3721 rx_ring = &igb->rx_rings[0]; 3722 rx_ring->intr_vector = vector; 3723 3724 vector++; 3725 break; 3726 3727 case DDI_INTR_TYPE_FIXED: 3728 /* Add interrupt handlers for the only vector */ 3729 rc = ddi_intr_add_handler(igb->htable[vector], 3730 (ddi_intr_handler_t *)igb_intr_legacy, 3731 (void *)igb, NULL); 3732 3733 if (rc != DDI_SUCCESS) { 3734 igb_log(igb, 3735 "Add legacy interrupt handler failed: %d", rc); 3736 return (IGB_FAILURE); 3737 } 3738 3739 rx_ring = &igb->rx_rings[0]; 3740 rx_ring->intr_vector = vector; 3741 3742 vector++; 3743 break; 3744 3745 default: 3746 return (IGB_FAILURE); 3747 } 3748 3749 ASSERT(vector == igb->intr_cnt); 3750 3751 return (IGB_SUCCESS); 3752 } 3753 3754 /* 3755 * igb_setup_adapter_msix - setup the adapter to use MSI-X interrupts 3756 * 3757 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 3758 */ 3759 static void 3760 igb_setup_adapter_msix(igb_t *igb) 3761 { 3762 uint32_t eims = 0; 3763 int i, vector; 3764 struct e1000_hw *hw = &igb->hw; 3765 3766 /* 3767 * Set vector for Tx + Other causes 3768 * NOTE assumption that there is only one of these and it is vector 0 3769 */ 3770 vector = 0; 3771 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 3772 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 3773 3774 vector++; 3775 for (i = 0; i < igb->num_rx_rings; i++) { 3776 /* 3777 * Set vector for each rx ring 3778 */ 3779 eims = (E1000_EICR_RX_QUEUE0 << i); 3780 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 3781 3782 /* 3783 * Accumulate bits to enable in igb_enable_adapter_interrupts() 3784 */ 3785 igb->eims_mask |= eims; 3786 3787 vector++; 3788 } 3789 3790 ASSERT(vector == igb->intr_cnt); 3791 3792 /* 3793 * Disable IAM for ICR interrupt bits 3794 */ 3795 E1000_WRITE_REG(hw, E1000_IAM, 0); 3796 E1000_WRITE_FLUSH(hw); 3797 } 3798 3799 /* 3800 * igb_rem_intr_handlers - remove the interrupt handlers 3801 */ 3802 static void 3803 igb_rem_intr_handlers(igb_t *igb) 3804 { 3805 int i; 3806 int rc; 3807 3808 for (i = 0; i < igb->intr_cnt; i++) { 3809 rc = ddi_intr_remove_handler(igb->htable[i]); 3810 if (rc != DDI_SUCCESS) { 3811 IGB_DEBUGLOG_1(igb, 3812 "Remove intr handler failed: %d", rc); 3813 } 3814 } 3815 } 3816 3817 /* 3818 * igb_rem_intrs - remove the allocated interrupts 3819 */ 3820 static void 3821 igb_rem_intrs(igb_t *igb) 3822 { 3823 int i; 3824 int rc; 3825 3826 for (i = 0; i < igb->intr_cnt; i++) { 3827 rc = ddi_intr_free(igb->htable[i]); 3828 if (rc != DDI_SUCCESS) { 3829 IGB_DEBUGLOG_1(igb, 3830 "Free intr failed: %d", rc); 3831 } 3832 } 3833 3834 kmem_free(igb->htable, igb->intr_size); 3835 igb->htable = NULL; 3836 } 3837 3838 /* 3839 * igb_enable_intrs - enable all the ddi interrupts 3840 */ 3841 static int 3842 igb_enable_intrs(igb_t *igb) 3843 { 3844 int i; 3845 int rc; 3846 3847 /* Enable interrupts */ 3848 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3849 /* Call ddi_intr_block_enable() for MSI */ 3850 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 3851 if (rc != DDI_SUCCESS) { 3852 igb_log(igb, 3853 "Enable block intr failed: %d", rc); 3854 return (IGB_FAILURE); 3855 } 3856 } else { 3857 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 3858 for (i = 0; i < igb->intr_cnt; i++) { 3859 rc = ddi_intr_enable(igb->htable[i]); 3860 if (rc != DDI_SUCCESS) { 3861 igb_log(igb, 3862 "Enable intr failed: %d", rc); 3863 return (IGB_FAILURE); 3864 } 3865 } 3866 } 3867 3868 return (IGB_SUCCESS); 3869 } 3870 3871 /* 3872 * igb_disable_intrs - disable all the ddi interrupts 3873 */ 3874 static int 3875 igb_disable_intrs(igb_t *igb) 3876 { 3877 int i; 3878 int rc; 3879 3880 /* Disable all interrupts */ 3881 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3882 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 3883 if (rc != DDI_SUCCESS) { 3884 igb_log(igb, 3885 "Disable block intr failed: %d", rc); 3886 return (IGB_FAILURE); 3887 } 3888 } else { 3889 for (i = 0; i < igb->intr_cnt; i++) { 3890 rc = ddi_intr_disable(igb->htable[i]); 3891 if (rc != DDI_SUCCESS) { 3892 igb_log(igb, 3893 "Disable intr failed: %d", rc); 3894 return (IGB_FAILURE); 3895 } 3896 } 3897 } 3898 3899 return (IGB_SUCCESS); 3900 } 3901 3902 /* 3903 * igb_get_phy_state - Get and save the parameters read from PHY registers 3904 */ 3905 static void 3906 igb_get_phy_state(igb_t *igb) 3907 { 3908 struct e1000_hw *hw = &igb->hw; 3909 uint16_t phy_ctrl; 3910 uint16_t phy_status; 3911 uint16_t phy_an_adv; 3912 uint16_t phy_an_exp; 3913 uint16_t phy_ext_status; 3914 uint16_t phy_1000t_ctrl; 3915 uint16_t phy_1000t_status; 3916 uint16_t phy_lp_able; 3917 3918 ASSERT(mutex_owned(&igb->gen_lock)); 3919 3920 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3921 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3922 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 3923 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 3924 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3925 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 3926 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_1000t_status); 3927 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 3928 3929 igb->param_autoneg_cap = 3930 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 3931 igb->param_pause_cap = 3932 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 3933 igb->param_asym_pause_cap = 3934 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 3935 igb->param_1000fdx_cap = ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3936 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 3937 igb->param_1000hdx_cap = ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 3938 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 3939 igb->param_100t4_cap = 3940 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 3941 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 3942 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 3943 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 3944 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 3945 igb->param_10fdx_cap = 3946 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 3947 igb->param_10hdx_cap = 3948 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 3949 igb->param_rem_fault = 3950 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 3951 3952 igb->param_adv_autoneg_cap = hw->mac.autoneg; 3953 igb->param_adv_pause_cap = 3954 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 3955 igb->param_adv_asym_pause_cap = 3956 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 3957 igb->param_adv_1000hdx_cap = 3958 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 3959 igb->param_adv_100t4_cap = 3960 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 3961 igb->param_adv_rem_fault = 3962 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 3963 if (igb->param_adv_autoneg_cap == 1) { 3964 igb->param_adv_1000fdx_cap = 3965 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 3966 igb->param_adv_100fdx_cap = 3967 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 3968 igb->param_adv_100hdx_cap = 3969 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 3970 igb->param_adv_10fdx_cap = 3971 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 3972 igb->param_adv_10hdx_cap = 3973 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 3974 } 3975 3976 igb->param_lp_autoneg_cap = 3977 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 3978 igb->param_lp_pause_cap = 3979 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 3980 igb->param_lp_asym_pause_cap = 3981 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 3982 igb->param_lp_1000fdx_cap = 3983 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 3984 igb->param_lp_1000hdx_cap = 3985 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 3986 igb->param_lp_100t4_cap = 3987 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 3988 igb->param_lp_100fdx_cap = 3989 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 3990 igb->param_lp_100hdx_cap = 3991 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 3992 igb->param_lp_10fdx_cap = 3993 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 3994 igb->param_lp_10hdx_cap = 3995 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 3996 igb->param_lp_rem_fault = 3997 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 3998 } 3999 4000 /* 4001 * igb_get_driver_control 4002 */ 4003 static void 4004 igb_get_driver_control(struct e1000_hw *hw) 4005 { 4006 uint32_t ctrl_ext; 4007 4008 /* Notify firmware that driver is in control of device */ 4009 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4010 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 4011 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4012 } 4013 4014 /* 4015 * igb_release_driver_control 4016 */ 4017 static void 4018 igb_release_driver_control(struct e1000_hw *hw) 4019 { 4020 uint32_t ctrl_ext; 4021 4022 /* Notify firmware that driver is no longer in control of device */ 4023 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4024 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 4025 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4026 } 4027 4028 /* 4029 * igb_atomic_reserve - Atomic decrease operation 4030 */ 4031 int 4032 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 4033 { 4034 uint32_t oldval; 4035 uint32_t newval; 4036 4037 /* ATOMICALLY */ 4038 do { 4039 oldval = *count_p; 4040 if (oldval < n) 4041 return (-1); 4042 newval = oldval - n; 4043 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 4044 4045 return (newval); 4046 } 4047 4048 /* 4049 * FMA support 4050 */ 4051 4052 int 4053 igb_check_acc_handle(ddi_acc_handle_t handle) 4054 { 4055 ddi_fm_error_t de; 4056 4057 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 4058 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 4059 return (de.fme_status); 4060 } 4061 4062 int 4063 igb_check_dma_handle(ddi_dma_handle_t handle) 4064 { 4065 ddi_fm_error_t de; 4066 4067 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 4068 return (de.fme_status); 4069 } 4070 4071 /* 4072 * The IO fault service error handling callback function 4073 */ 4074 /*ARGSUSED*/ 4075 static int 4076 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 4077 { 4078 /* 4079 * as the driver can always deal with an error in any dma or 4080 * access handle, we can just return the fme_status value. 4081 */ 4082 pci_ereport_post(dip, err, NULL); 4083 return (err->fme_status); 4084 } 4085 4086 static void 4087 igb_fm_init(igb_t *igb) 4088 { 4089 ddi_iblock_cookie_t iblk; 4090 int fma_acc_flag, fma_dma_flag; 4091 4092 /* Only register with IO Fault Services if we have some capability */ 4093 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 4094 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 4095 fma_acc_flag = 1; 4096 } else { 4097 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 4098 fma_acc_flag = 0; 4099 } 4100 4101 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 4102 fma_dma_flag = 1; 4103 } else { 4104 fma_dma_flag = 0; 4105 } 4106 4107 (void) igb_set_fma_flags(fma_acc_flag, fma_dma_flag); 4108 4109 if (igb->fm_capabilities) { 4110 4111 /* Register capabilities with IO Fault Services */ 4112 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 4113 4114 /* 4115 * Initialize pci ereport capabilities if ereport capable 4116 */ 4117 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4118 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4119 pci_ereport_setup(igb->dip); 4120 4121 /* 4122 * Register error callback if error callback capable 4123 */ 4124 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4125 ddi_fm_handler_register(igb->dip, 4126 igb_fm_error_cb, (void*) igb); 4127 } 4128 } 4129 4130 static void 4131 igb_fm_fini(igb_t *igb) 4132 { 4133 /* Only unregister FMA capabilities if we registered some */ 4134 if (igb->fm_capabilities) { 4135 4136 /* 4137 * Release any resources allocated by pci_ereport_setup() 4138 */ 4139 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 4140 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4141 pci_ereport_teardown(igb->dip); 4142 4143 /* 4144 * Un-register error callback if error callback capable 4145 */ 4146 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 4147 ddi_fm_handler_unregister(igb->dip); 4148 4149 /* Unregister from IO Fault Services */ 4150 ddi_fm_fini(igb->dip); 4151 } 4152 } 4153 4154 void 4155 igb_fm_ereport(igb_t *igb, char *detail) 4156 { 4157 uint64_t ena; 4158 char buf[FM_MAX_CLASS]; 4159 4160 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 4161 ena = fm_ena_generate(0, FM_ENA_FMT1); 4162 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 4163 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 4164 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 4165 } 4166 } 4167