1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 * Copyright 2013, Nexenta Systems, Inc. All rights reserved. 29 * Copyright 2016 Joyent, Inc. 30 */ 31 32 #include "igb_sw.h" 33 34 static char ident[] = "Intel 1Gb Ethernet"; 35 static char igb_version[] = "igb 2.3.8-ish"; 36 37 /* 38 * Local function protoypes 39 */ 40 static int igb_register_mac(igb_t *); 41 static int igb_identify_hardware(igb_t *); 42 static int igb_regs_map(igb_t *); 43 static void igb_init_properties(igb_t *); 44 static int igb_init_driver_settings(igb_t *); 45 static void igb_init_locks(igb_t *); 46 static void igb_destroy_locks(igb_t *); 47 static int igb_init_mac_address(igb_t *); 48 static int igb_init(igb_t *); 49 static int igb_init_adapter(igb_t *); 50 static void igb_stop_adapter(igb_t *); 51 static int igb_reset(igb_t *); 52 static void igb_tx_clean(igb_t *); 53 static boolean_t igb_tx_drain(igb_t *); 54 static boolean_t igb_rx_drain(igb_t *); 55 static int igb_alloc_rings(igb_t *); 56 static int igb_alloc_rx_data(igb_t *); 57 static void igb_free_rx_data(igb_t *); 58 static void igb_free_rings(igb_t *); 59 static void igb_setup_rings(igb_t *); 60 static void igb_setup_rx(igb_t *); 61 static void igb_setup_tx(igb_t *); 62 static void igb_setup_rx_ring(igb_rx_ring_t *); 63 static void igb_setup_tx_ring(igb_tx_ring_t *); 64 static void igb_setup_rss(igb_t *); 65 static void igb_setup_mac_rss_classify(igb_t *); 66 static void igb_setup_mac_classify(igb_t *); 67 static void igb_init_unicst(igb_t *); 68 static void igb_setup_multicst(igb_t *); 69 static void igb_get_phy_state(igb_t *); 70 static void igb_param_sync(igb_t *); 71 static void igb_get_conf(igb_t *); 72 static int igb_get_prop(igb_t *, char *, int, int, int); 73 static boolean_t igb_is_link_up(igb_t *); 74 static boolean_t igb_link_check(igb_t *); 75 static void igb_local_timer(void *); 76 static void igb_link_timer(void *); 77 static void igb_arm_watchdog_timer(igb_t *); 78 static void igb_start_watchdog_timer(igb_t *); 79 static void igb_restart_watchdog_timer(igb_t *); 80 static void igb_stop_watchdog_timer(igb_t *); 81 static void igb_start_link_timer(igb_t *); 82 static void igb_stop_link_timer(igb_t *); 83 static void igb_disable_adapter_interrupts(igb_t *); 84 static void igb_enable_adapter_interrupts_82575(igb_t *); 85 static void igb_enable_adapter_interrupts_82576(igb_t *); 86 static void igb_enable_adapter_interrupts_82580(igb_t *); 87 static boolean_t is_valid_mac_addr(uint8_t *); 88 static boolean_t igb_stall_check(igb_t *); 89 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 90 static void igb_set_external_loopback(igb_t *); 91 static void igb_set_internal_phy_loopback(igb_t *); 92 static void igb_set_internal_serdes_loopback(igb_t *); 93 static boolean_t igb_find_mac_address(igb_t *); 94 static int igb_alloc_intrs(igb_t *); 95 static int igb_alloc_intr_handles(igb_t *, int); 96 static int igb_add_intr_handlers(igb_t *); 97 static void igb_rem_intr_handlers(igb_t *); 98 static void igb_rem_intrs(igb_t *); 99 static int igb_enable_intrs(igb_t *); 100 static int igb_disable_intrs(igb_t *); 101 static void igb_setup_msix_82575(igb_t *); 102 static void igb_setup_msix_82576(igb_t *); 103 static void igb_setup_msix_82580(igb_t *); 104 static uint_t igb_intr_legacy(void *, void *); 105 static uint_t igb_intr_msi(void *, void *); 106 static uint_t igb_intr_rx(void *, void *); 107 static uint_t igb_intr_tx(void *, void *); 108 static uint_t igb_intr_tx_other(void *, void *); 109 static void igb_intr_rx_work(igb_rx_ring_t *); 110 static void igb_intr_tx_work(igb_tx_ring_t *); 111 static void igb_intr_link_work(igb_t *); 112 static void igb_get_driver_control(struct e1000_hw *); 113 static void igb_release_driver_control(struct e1000_hw *); 114 115 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 116 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 117 static int igb_resume(dev_info_t *); 118 static int igb_suspend(dev_info_t *); 119 static int igb_quiesce(dev_info_t *); 120 static void igb_unconfigure(dev_info_t *, igb_t *); 121 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 122 const void *); 123 static void igb_fm_init(igb_t *); 124 static void igb_fm_fini(igb_t *); 125 static void igb_release_multicast(igb_t *); 126 127 char *igb_priv_props[] = { 128 "_eee_support", 129 "_tx_copy_thresh", 130 "_tx_recycle_thresh", 131 "_tx_overload_thresh", 132 "_tx_resched_thresh", 133 "_rx_copy_thresh", 134 "_rx_limit_per_intr", 135 "_intr_throttling", 136 "_adv_pause_cap", 137 "_adv_asym_pause_cap", 138 NULL 139 }; 140 141 static struct cb_ops igb_cb_ops = { 142 nulldev, /* cb_open */ 143 nulldev, /* cb_close */ 144 nodev, /* cb_strategy */ 145 nodev, /* cb_print */ 146 nodev, /* cb_dump */ 147 nodev, /* cb_read */ 148 nodev, /* cb_write */ 149 nodev, /* cb_ioctl */ 150 nodev, /* cb_devmap */ 151 nodev, /* cb_mmap */ 152 nodev, /* cb_segmap */ 153 nochpoll, /* cb_chpoll */ 154 ddi_prop_op, /* cb_prop_op */ 155 NULL, /* cb_stream */ 156 D_MP | D_HOTPLUG, /* cb_flag */ 157 CB_REV, /* cb_rev */ 158 nodev, /* cb_aread */ 159 nodev /* cb_awrite */ 160 }; 161 162 static struct dev_ops igb_dev_ops = { 163 DEVO_REV, /* devo_rev */ 164 0, /* devo_refcnt */ 165 NULL, /* devo_getinfo */ 166 nulldev, /* devo_identify */ 167 nulldev, /* devo_probe */ 168 igb_attach, /* devo_attach */ 169 igb_detach, /* devo_detach */ 170 nodev, /* devo_reset */ 171 &igb_cb_ops, /* devo_cb_ops */ 172 NULL, /* devo_bus_ops */ 173 ddi_power, /* devo_power */ 174 igb_quiesce, /* devo_quiesce */ 175 }; 176 177 static struct modldrv igb_modldrv = { 178 &mod_driverops, /* Type of module. This one is a driver */ 179 ident, /* Discription string */ 180 &igb_dev_ops, /* driver ops */ 181 }; 182 183 static struct modlinkage igb_modlinkage = { 184 MODREV_1, &igb_modldrv, NULL 185 }; 186 187 /* Access attributes for register mapping */ 188 ddi_device_acc_attr_t igb_regs_acc_attr = { 189 DDI_DEVICE_ATTR_V1, 190 DDI_STRUCTURE_LE_ACC, 191 DDI_STRICTORDER_ACC, 192 DDI_FLAGERR_ACC 193 }; 194 195 #define IGB_M_CALLBACK_FLAGS \ 196 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 197 198 static mac_callbacks_t igb_m_callbacks = { 199 IGB_M_CALLBACK_FLAGS, 200 igb_m_stat, 201 igb_m_start, 202 igb_m_stop, 203 igb_m_promisc, 204 igb_m_multicst, 205 NULL, 206 NULL, 207 NULL, 208 igb_m_ioctl, 209 igb_m_getcapab, 210 NULL, 211 NULL, 212 igb_m_setprop, 213 igb_m_getprop, 214 igb_m_propinfo 215 }; 216 217 /* 218 * Initialize capabilities of each supported adapter type 219 */ 220 static adapter_info_t igb_82575_cap = { 221 /* limits */ 222 4, /* maximum number of rx queues */ 223 1, /* minimum number of rx queues */ 224 4, /* default number of rx queues */ 225 4, /* maximum number of tx queues */ 226 1, /* minimum number of tx queues */ 227 4, /* default number of tx queues */ 228 65535, /* maximum interrupt throttle rate */ 229 0, /* minimum interrupt throttle rate */ 230 200, /* default interrupt throttle rate */ 231 232 /* function pointers */ 233 igb_enable_adapter_interrupts_82575, 234 igb_setup_msix_82575, 235 236 /* capabilities */ 237 (IGB_FLAG_HAS_DCA | /* capability flags */ 238 IGB_FLAG_VMDQ_POOL), 239 240 0xffc00000 /* mask for RXDCTL register */ 241 }; 242 243 static adapter_info_t igb_82576_cap = { 244 /* limits */ 245 16, /* maximum number of rx queues */ 246 1, /* minimum number of rx queues */ 247 4, /* default number of rx queues */ 248 16, /* maximum number of tx queues */ 249 1, /* minimum number of tx queues */ 250 4, /* default number of tx queues */ 251 65535, /* maximum interrupt throttle rate */ 252 0, /* minimum interrupt throttle rate */ 253 200, /* default interrupt throttle rate */ 254 255 /* function pointers */ 256 igb_enable_adapter_interrupts_82576, 257 igb_setup_msix_82576, 258 259 /* capabilities */ 260 (IGB_FLAG_HAS_DCA | /* capability flags */ 261 IGB_FLAG_VMDQ_POOL | 262 IGB_FLAG_NEED_CTX_IDX), 263 264 0xffe00000 /* mask for RXDCTL register */ 265 }; 266 267 static adapter_info_t igb_82580_cap = { 268 /* limits */ 269 8, /* maximum number of rx queues */ 270 1, /* minimum number of rx queues */ 271 4, /* default number of rx queues */ 272 8, /* maximum number of tx queues */ 273 1, /* minimum number of tx queues */ 274 4, /* default number of tx queues */ 275 65535, /* maximum interrupt throttle rate */ 276 0, /* minimum interrupt throttle rate */ 277 200, /* default interrupt throttle rate */ 278 279 /* function pointers */ 280 igb_enable_adapter_interrupts_82580, 281 igb_setup_msix_82580, 282 283 /* capabilities */ 284 (IGB_FLAG_HAS_DCA | /* capability flags */ 285 IGB_FLAG_VMDQ_POOL | 286 IGB_FLAG_NEED_CTX_IDX), 287 288 0xffe00000 /* mask for RXDCTL register */ 289 }; 290 291 static adapter_info_t igb_i350_cap = { 292 /* limits */ 293 8, /* maximum number of rx queues */ 294 1, /* minimum number of rx queues */ 295 4, /* default number of rx queues */ 296 8, /* maximum number of tx queues */ 297 1, /* minimum number of tx queues */ 298 4, /* default number of tx queues */ 299 65535, /* maximum interrupt throttle rate */ 300 0, /* minimum interrupt throttle rate */ 301 200, /* default interrupt throttle rate */ 302 303 /* function pointers */ 304 igb_enable_adapter_interrupts_82580, 305 igb_setup_msix_82580, 306 307 /* capabilities */ 308 (IGB_FLAG_HAS_DCA | /* capability flags */ 309 IGB_FLAG_VMDQ_POOL | 310 IGB_FLAG_NEED_CTX_IDX), 311 312 0xffe00000 /* mask for RXDCTL register */ 313 }; 314 315 static adapter_info_t igb_i210_cap = { 316 /* limits */ 317 4, /* maximum number of rx queues */ 318 1, /* minimum number of rx queues */ 319 4, /* default number of rx queues */ 320 4, /* maximum number of tx queues */ 321 1, /* minimum number of tx queues */ 322 4, /* default number of tx queues */ 323 65535, /* maximum interrupt throttle rate */ 324 0, /* minimum interrupt throttle rate */ 325 200, /* default interrupt throttle rate */ 326 327 /* function pointers */ 328 igb_enable_adapter_interrupts_82580, 329 igb_setup_msix_82580, 330 331 /* capabilities */ 332 (IGB_FLAG_HAS_DCA | /* capability flags */ 333 IGB_FLAG_VMDQ_POOL | 334 IGB_FLAG_NEED_CTX_IDX), 335 336 0xfff00000 /* mask for RXDCTL register */ 337 }; 338 339 static adapter_info_t igb_i354_cap = { 340 /* limits */ 341 8, /* maximum number of rx queues */ 342 1, /* minimum number of rx queues */ 343 4, /* default number of rx queues */ 344 8, /* maximum number of tx queues */ 345 1, /* minimum number of tx queues */ 346 4, /* default number of tx queues */ 347 65535, /* maximum interrupt throttle rate */ 348 0, /* minimum interrupt throttle rate */ 349 200, /* default interrupt throttle rate */ 350 351 /* function pointers */ 352 igb_enable_adapter_interrupts_82580, 353 igb_setup_msix_82580, 354 355 /* capabilities */ 356 (IGB_FLAG_HAS_DCA | /* capability flags */ 357 IGB_FLAG_VMDQ_POOL | 358 IGB_FLAG_NEED_CTX_IDX), 359 360 0xfff00000 /* mask for RXDCTL register */ 361 }; 362 363 /* 364 * Module Initialization Functions 365 */ 366 367 int 368 _init(void) 369 { 370 int status; 371 372 mac_init_ops(&igb_dev_ops, MODULE_NAME); 373 374 status = mod_install(&igb_modlinkage); 375 376 if (status != DDI_SUCCESS) { 377 mac_fini_ops(&igb_dev_ops); 378 } 379 380 return (status); 381 } 382 383 int 384 _fini(void) 385 { 386 int status; 387 388 status = mod_remove(&igb_modlinkage); 389 390 if (status == DDI_SUCCESS) { 391 mac_fini_ops(&igb_dev_ops); 392 } 393 394 return (status); 395 396 } 397 398 int 399 _info(struct modinfo *modinfop) 400 { 401 int status; 402 403 status = mod_info(&igb_modlinkage, modinfop); 404 405 return (status); 406 } 407 408 /* 409 * igb_attach - driver attach 410 * 411 * This function is the device specific initialization entry 412 * point. This entry point is required and must be written. 413 * The DDI_ATTACH command must be provided in the attach entry 414 * point. When attach() is called with cmd set to DDI_ATTACH, 415 * all normal kernel services (such as kmem_alloc(9F)) are 416 * available for use by the driver. 417 * 418 * The attach() function will be called once for each instance 419 * of the device on the system with cmd set to DDI_ATTACH. 420 * Until attach() succeeds, the only driver entry points which 421 * may be called are open(9E) and getinfo(9E). 422 */ 423 static int 424 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 425 { 426 igb_t *igb; 427 struct igb_osdep *osdep; 428 struct e1000_hw *hw; 429 int instance; 430 431 /* 432 * Check the command and perform corresponding operations 433 */ 434 switch (cmd) { 435 default: 436 return (DDI_FAILURE); 437 438 case DDI_RESUME: 439 return (igb_resume(devinfo)); 440 441 case DDI_ATTACH: 442 break; 443 } 444 445 /* Get the device instance */ 446 instance = ddi_get_instance(devinfo); 447 448 /* Allocate memory for the instance data structure */ 449 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 450 451 igb->dip = devinfo; 452 igb->instance = instance; 453 454 hw = &igb->hw; 455 osdep = &igb->osdep; 456 hw->back = osdep; 457 osdep->igb = igb; 458 459 /* Attach the instance pointer to the dev_info data structure */ 460 ddi_set_driver_private(devinfo, igb); 461 462 463 /* Initialize for fma support */ 464 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 465 0, 0x0f, 466 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 467 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 468 igb_fm_init(igb); 469 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 470 471 /* 472 * Map PCI config space registers 473 */ 474 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 475 igb_error(igb, "Failed to map PCI configurations"); 476 goto attach_fail; 477 } 478 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 479 480 /* 481 * Identify the chipset family 482 */ 483 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 484 igb_error(igb, "Failed to identify hardware"); 485 goto attach_fail; 486 } 487 488 /* 489 * Map device registers 490 */ 491 if (igb_regs_map(igb) != IGB_SUCCESS) { 492 igb_error(igb, "Failed to map device registers"); 493 goto attach_fail; 494 } 495 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 496 497 /* 498 * Initialize driver parameters 499 */ 500 igb_init_properties(igb); 501 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 502 503 /* 504 * Allocate interrupts 505 */ 506 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 507 igb_error(igb, "Failed to allocate interrupts"); 508 goto attach_fail; 509 } 510 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 511 512 /* 513 * Allocate rx/tx rings based on the ring numbers. 514 * The actual numbers of rx/tx rings are decided by the number of 515 * allocated interrupt vectors, so we should allocate the rings after 516 * interrupts are allocated. 517 */ 518 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 519 igb_error(igb, "Failed to allocate rx/tx rings or groups"); 520 goto attach_fail; 521 } 522 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 523 524 /* 525 * Add interrupt handlers 526 */ 527 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 528 igb_error(igb, "Failed to add interrupt handlers"); 529 goto attach_fail; 530 } 531 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 532 533 /* 534 * Initialize driver parameters 535 */ 536 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 537 igb_error(igb, "Failed to initialize driver settings"); 538 goto attach_fail; 539 } 540 541 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 542 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 543 goto attach_fail; 544 } 545 546 /* 547 * Initialize mutexes for this device. 548 * Do this before enabling the interrupt handler and 549 * register the softint to avoid the condition where 550 * interrupt handler can try using uninitialized mutex 551 */ 552 igb_init_locks(igb); 553 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 554 555 /* 556 * Initialize the adapter 557 */ 558 if (igb_init(igb) != IGB_SUCCESS) { 559 igb_error(igb, "Failed to initialize adapter"); 560 goto attach_fail; 561 } 562 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 563 564 /* 565 * Initialize statistics 566 */ 567 if (igb_init_stats(igb) != IGB_SUCCESS) { 568 igb_error(igb, "Failed to initialize statistics"); 569 goto attach_fail; 570 } 571 igb->attach_progress |= ATTACH_PROGRESS_STATS; 572 573 /* 574 * Register the driver to the MAC 575 */ 576 if (igb_register_mac(igb) != IGB_SUCCESS) { 577 igb_error(igb, "Failed to register MAC"); 578 goto attach_fail; 579 } 580 igb->attach_progress |= ATTACH_PROGRESS_MAC; 581 582 /* 583 * Now that mutex locks are initialized, and the chip is also 584 * initialized, enable interrupts. 585 */ 586 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 587 igb_error(igb, "Failed to enable DDI interrupts"); 588 goto attach_fail; 589 } 590 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 591 592 igb_log(igb, "%s", igb_version); 593 atomic_or_32(&igb->igb_state, IGB_INITIALIZED); 594 595 /* 596 * Newer models have Energy Efficient Ethernet, let's disable this by 597 * default. 598 */ 599 if (igb->hw.mac.type == e1000_i350) 600 (void) e1000_set_eee_i350(&igb->hw, B_FALSE, B_FALSE); 601 else if (igb->hw.mac.type == e1000_i354) 602 (void) e1000_set_eee_i354(&igb->hw, B_FALSE, B_FALSE); 603 604 return (DDI_SUCCESS); 605 606 attach_fail: 607 igb_unconfigure(devinfo, igb); 608 return (DDI_FAILURE); 609 } 610 611 /* 612 * igb_detach - driver detach 613 * 614 * The detach() function is the complement of the attach routine. 615 * If cmd is set to DDI_DETACH, detach() is used to remove the 616 * state associated with a given instance of a device node 617 * prior to the removal of that instance from the system. 618 * 619 * The detach() function will be called once for each instance 620 * of the device for which there has been a successful attach() 621 * once there are no longer any opens on the device. 622 * 623 * Interrupts routine are disabled, All memory allocated by this 624 * driver are freed. 625 */ 626 static int 627 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 628 { 629 igb_t *igb; 630 631 /* 632 * Check detach command 633 */ 634 switch (cmd) { 635 default: 636 return (DDI_FAILURE); 637 638 case DDI_SUSPEND: 639 return (igb_suspend(devinfo)); 640 641 case DDI_DETACH: 642 break; 643 } 644 645 646 /* 647 * Get the pointer to the driver private data structure 648 */ 649 igb = (igb_t *)ddi_get_driver_private(devinfo); 650 if (igb == NULL) 651 return (DDI_FAILURE); 652 653 /* 654 * Unregister MAC. If failed, we have to fail the detach 655 */ 656 if (mac_unregister(igb->mac_hdl) != 0) { 657 igb_error(igb, "Failed to unregister MAC"); 658 return (DDI_FAILURE); 659 } 660 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 661 662 /* 663 * If the device is still running, it needs to be stopped first. 664 * This check is necessary because under some specific circumstances, 665 * the detach routine can be called without stopping the interface 666 * first. 667 */ 668 mutex_enter(&igb->gen_lock); 669 if (igb->igb_state & IGB_STARTED) { 670 atomic_and_32(&igb->igb_state, ~IGB_STARTED); 671 igb_stop(igb, B_TRUE); 672 mutex_exit(&igb->gen_lock); 673 /* Disable and stop the watchdog timer */ 674 igb_disable_watchdog_timer(igb); 675 } else 676 mutex_exit(&igb->gen_lock); 677 678 /* 679 * Check if there are still rx buffers held by the upper layer. 680 * If so, fail the detach. 681 */ 682 if (!igb_rx_drain(igb)) 683 return (DDI_FAILURE); 684 685 /* 686 * Do the remaining unconfigure routines 687 */ 688 igb_unconfigure(devinfo, igb); 689 690 return (DDI_SUCCESS); 691 } 692 693 /* 694 * quiesce(9E) entry point. 695 * 696 * This function is called when the system is single-threaded at high 697 * PIL with preemption disabled. Therefore, this function must not be 698 * blocked. 699 * 700 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 701 * DDI_FAILURE indicates an error condition and should almost never happen. 702 */ 703 static int 704 igb_quiesce(dev_info_t *devinfo) 705 { 706 igb_t *igb; 707 struct e1000_hw *hw; 708 709 igb = (igb_t *)ddi_get_driver_private(devinfo); 710 711 if (igb == NULL) 712 return (DDI_FAILURE); 713 714 hw = &igb->hw; 715 716 /* 717 * Disable the adapter interrupts 718 */ 719 igb_disable_adapter_interrupts(igb); 720 721 /* Tell firmware driver is no longer in control */ 722 igb_release_driver_control(hw); 723 724 /* 725 * Reset the chipset 726 */ 727 (void) e1000_reset_hw(hw); 728 729 /* 730 * Reset PHY if possible 731 */ 732 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 733 (void) e1000_phy_hw_reset(hw); 734 735 return (DDI_SUCCESS); 736 } 737 738 /* 739 * igb_unconfigure - release all resources held by this instance 740 */ 741 static void 742 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 743 { 744 /* 745 * Disable interrupt 746 */ 747 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 748 (void) igb_disable_intrs(igb); 749 } 750 751 /* 752 * Unregister MAC 753 */ 754 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 755 (void) mac_unregister(igb->mac_hdl); 756 } 757 758 /* 759 * Free statistics 760 */ 761 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 762 kstat_delete((kstat_t *)igb->igb_ks); 763 } 764 765 /* 766 * Remove interrupt handlers 767 */ 768 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 769 igb_rem_intr_handlers(igb); 770 } 771 772 /* 773 * Remove interrupts 774 */ 775 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 776 igb_rem_intrs(igb); 777 } 778 779 /* 780 * Remove driver properties 781 */ 782 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 783 (void) ddi_prop_remove_all(devinfo); 784 } 785 786 /* 787 * Stop the adapter 788 */ 789 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) { 790 mutex_enter(&igb->gen_lock); 791 igb_stop_adapter(igb); 792 mutex_exit(&igb->gen_lock); 793 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 794 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 795 } 796 797 /* 798 * Free multicast table 799 */ 800 igb_release_multicast(igb); 801 802 /* 803 * Free register handle 804 */ 805 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 806 if (igb->osdep.reg_handle != NULL) 807 ddi_regs_map_free(&igb->osdep.reg_handle); 808 } 809 810 /* 811 * Free PCI config handle 812 */ 813 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 814 if (igb->osdep.cfg_handle != NULL) 815 pci_config_teardown(&igb->osdep.cfg_handle); 816 } 817 818 /* 819 * Free locks 820 */ 821 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 822 igb_destroy_locks(igb); 823 } 824 825 /* 826 * Free the rx/tx rings 827 */ 828 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 829 igb_free_rings(igb); 830 } 831 832 /* 833 * Remove FMA 834 */ 835 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 836 igb_fm_fini(igb); 837 } 838 839 /* 840 * Free the driver data structure 841 */ 842 kmem_free(igb, sizeof (igb_t)); 843 844 ddi_set_driver_private(devinfo, NULL); 845 } 846 847 /* 848 * igb_register_mac - Register the driver and its function pointers with 849 * the GLD interface 850 */ 851 static int 852 igb_register_mac(igb_t *igb) 853 { 854 struct e1000_hw *hw = &igb->hw; 855 mac_register_t *mac; 856 int status; 857 858 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 859 return (IGB_FAILURE); 860 861 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 862 mac->m_driver = igb; 863 mac->m_dip = igb->dip; 864 mac->m_src_addr = hw->mac.addr; 865 mac->m_callbacks = &igb_m_callbacks; 866 mac->m_min_sdu = 0; 867 mac->m_max_sdu = igb->max_frame_size - 868 sizeof (struct ether_vlan_header) - ETHERFCSL; 869 mac->m_margin = VLAN_TAGSZ; 870 mac->m_priv_props = igb_priv_props; 871 mac->m_v12n = MAC_VIRT_LEVEL1; 872 873 status = mac_register(mac, &igb->mac_hdl); 874 875 mac_free(mac); 876 877 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 878 } 879 880 /* 881 * igb_identify_hardware - Identify the type of the chipset 882 */ 883 static int 884 igb_identify_hardware(igb_t *igb) 885 { 886 struct e1000_hw *hw = &igb->hw; 887 struct igb_osdep *osdep = &igb->osdep; 888 889 /* 890 * Get the device id 891 */ 892 hw->vendor_id = 893 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 894 hw->device_id = 895 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 896 hw->revision_id = 897 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 898 hw->subsystem_device_id = 899 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 900 hw->subsystem_vendor_id = 901 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 902 903 /* 904 * Set the mac type of the adapter based on the device id 905 */ 906 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 907 return (IGB_FAILURE); 908 } 909 910 /* 911 * Install adapter capabilities based on mac type 912 */ 913 switch (hw->mac.type) { 914 case e1000_82575: 915 igb->capab = &igb_82575_cap; 916 break; 917 case e1000_82576: 918 igb->capab = &igb_82576_cap; 919 break; 920 case e1000_82580: 921 igb->capab = &igb_82580_cap; 922 break; 923 case e1000_i350: 924 igb->capab = &igb_i350_cap; 925 break; 926 case e1000_i210: 927 case e1000_i211: 928 igb->capab = &igb_i210_cap; 929 break; 930 case e1000_i354: 931 igb->capab = &igb_i354_cap; 932 break; 933 default: 934 return (IGB_FAILURE); 935 } 936 937 return (IGB_SUCCESS); 938 } 939 940 /* 941 * igb_regs_map - Map the device registers 942 */ 943 static int 944 igb_regs_map(igb_t *igb) 945 { 946 dev_info_t *devinfo = igb->dip; 947 struct e1000_hw *hw = &igb->hw; 948 struct igb_osdep *osdep = &igb->osdep; 949 off_t mem_size; 950 951 /* 952 * First get the size of device registers to be mapped. 953 */ 954 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) != 955 DDI_SUCCESS) { 956 return (IGB_FAILURE); 957 } 958 959 /* 960 * Call ddi_regs_map_setup() to map registers 961 */ 962 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET, 963 (caddr_t *)&hw->hw_addr, 0, 964 mem_size, &igb_regs_acc_attr, 965 &osdep->reg_handle)) != DDI_SUCCESS) { 966 return (IGB_FAILURE); 967 } 968 969 return (IGB_SUCCESS); 970 } 971 972 /* 973 * igb_init_properties - Initialize driver properties 974 */ 975 static void 976 igb_init_properties(igb_t *igb) 977 { 978 /* 979 * Get conf file properties, including link settings 980 * jumbo frames, ring number, descriptor number, etc. 981 */ 982 igb_get_conf(igb); 983 } 984 985 /* 986 * igb_init_driver_settings - Initialize driver settings 987 * 988 * The settings include hardware function pointers, bus information, 989 * rx/tx rings settings, link state, and any other parameters that 990 * need to be setup during driver initialization. 991 */ 992 static int 993 igb_init_driver_settings(igb_t *igb) 994 { 995 struct e1000_hw *hw = &igb->hw; 996 igb_rx_ring_t *rx_ring; 997 igb_tx_ring_t *tx_ring; 998 uint32_t rx_size; 999 uint32_t tx_size; 1000 int i; 1001 1002 /* 1003 * Initialize chipset specific hardware function pointers 1004 */ 1005 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 1006 return (IGB_FAILURE); 1007 } 1008 1009 /* 1010 * Get bus information 1011 */ 1012 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 1013 return (IGB_FAILURE); 1014 } 1015 1016 /* 1017 * Get the system page size 1018 */ 1019 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1); 1020 1021 /* 1022 * Set rx buffer size 1023 * The IP header alignment room is counted in the calculation. 1024 * The rx buffer size is in unit of 1K that is required by the 1025 * chipset hardware. 1026 */ 1027 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 1028 igb->rx_buf_size = ((rx_size >> 10) + 1029 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 1030 1031 /* 1032 * Set tx buffer size 1033 */ 1034 tx_size = igb->max_frame_size; 1035 igb->tx_buf_size = ((tx_size >> 10) + 1036 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 1037 1038 /* 1039 * Initialize rx/tx rings parameters 1040 */ 1041 for (i = 0; i < igb->num_rx_rings; i++) { 1042 rx_ring = &igb->rx_rings[i]; 1043 rx_ring->index = i; 1044 rx_ring->igb = igb; 1045 } 1046 1047 for (i = 0; i < igb->num_tx_rings; i++) { 1048 tx_ring = &igb->tx_rings[i]; 1049 tx_ring->index = i; 1050 tx_ring->igb = igb; 1051 if (igb->tx_head_wb_enable) 1052 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 1053 else 1054 tx_ring->tx_recycle = igb_tx_recycle_legacy; 1055 1056 tx_ring->ring_size = igb->tx_ring_size; 1057 tx_ring->free_list_size = igb->tx_ring_size + 1058 (igb->tx_ring_size >> 1); 1059 } 1060 1061 /* 1062 * Initialize values of interrupt throttling rates 1063 */ 1064 for (i = 1; i < MAX_NUM_EITR; i++) 1065 igb->intr_throttling[i] = igb->intr_throttling[0]; 1066 1067 /* 1068 * The initial link state should be "unknown" 1069 */ 1070 igb->link_state = LINK_STATE_UNKNOWN; 1071 1072 return (IGB_SUCCESS); 1073 } 1074 1075 /* 1076 * igb_init_locks - Initialize locks 1077 */ 1078 static void 1079 igb_init_locks(igb_t *igb) 1080 { 1081 igb_rx_ring_t *rx_ring; 1082 igb_tx_ring_t *tx_ring; 1083 int i; 1084 1085 for (i = 0; i < igb->num_rx_rings; i++) { 1086 rx_ring = &igb->rx_rings[i]; 1087 mutex_init(&rx_ring->rx_lock, NULL, 1088 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1089 } 1090 1091 for (i = 0; i < igb->num_tx_rings; i++) { 1092 tx_ring = &igb->tx_rings[i]; 1093 mutex_init(&tx_ring->tx_lock, NULL, 1094 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1095 mutex_init(&tx_ring->recycle_lock, NULL, 1096 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1097 mutex_init(&tx_ring->tcb_head_lock, NULL, 1098 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1099 mutex_init(&tx_ring->tcb_tail_lock, NULL, 1100 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1101 } 1102 1103 mutex_init(&igb->gen_lock, NULL, 1104 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1105 1106 mutex_init(&igb->watchdog_lock, NULL, 1107 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1108 1109 mutex_init(&igb->link_lock, NULL, 1110 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1111 } 1112 1113 /* 1114 * igb_destroy_locks - Destroy locks 1115 */ 1116 static void 1117 igb_destroy_locks(igb_t *igb) 1118 { 1119 igb_rx_ring_t *rx_ring; 1120 igb_tx_ring_t *tx_ring; 1121 int i; 1122 1123 for (i = 0; i < igb->num_rx_rings; i++) { 1124 rx_ring = &igb->rx_rings[i]; 1125 mutex_destroy(&rx_ring->rx_lock); 1126 } 1127 1128 for (i = 0; i < igb->num_tx_rings; i++) { 1129 tx_ring = &igb->tx_rings[i]; 1130 mutex_destroy(&tx_ring->tx_lock); 1131 mutex_destroy(&tx_ring->recycle_lock); 1132 mutex_destroy(&tx_ring->tcb_head_lock); 1133 mutex_destroy(&tx_ring->tcb_tail_lock); 1134 } 1135 1136 mutex_destroy(&igb->gen_lock); 1137 mutex_destroy(&igb->watchdog_lock); 1138 mutex_destroy(&igb->link_lock); 1139 } 1140 1141 static int 1142 igb_resume(dev_info_t *devinfo) 1143 { 1144 igb_t *igb; 1145 1146 igb = (igb_t *)ddi_get_driver_private(devinfo); 1147 if (igb == NULL) 1148 return (DDI_FAILURE); 1149 1150 mutex_enter(&igb->gen_lock); 1151 1152 /* 1153 * Enable interrupts 1154 */ 1155 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1156 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 1157 igb_error(igb, "Failed to enable DDI interrupts"); 1158 mutex_exit(&igb->gen_lock); 1159 return (DDI_FAILURE); 1160 } 1161 } 1162 1163 if (igb->igb_state & IGB_STARTED) { 1164 if (igb_start(igb, B_FALSE) != IGB_SUCCESS) { 1165 mutex_exit(&igb->gen_lock); 1166 return (DDI_FAILURE); 1167 } 1168 1169 /* 1170 * Enable and start the watchdog timer 1171 */ 1172 igb_enable_watchdog_timer(igb); 1173 } 1174 1175 atomic_and_32(&igb->igb_state, ~IGB_SUSPENDED); 1176 1177 mutex_exit(&igb->gen_lock); 1178 1179 return (DDI_SUCCESS); 1180 } 1181 1182 static int 1183 igb_suspend(dev_info_t *devinfo) 1184 { 1185 igb_t *igb; 1186 1187 igb = (igb_t *)ddi_get_driver_private(devinfo); 1188 if (igb == NULL) 1189 return (DDI_FAILURE); 1190 1191 mutex_enter(&igb->gen_lock); 1192 1193 atomic_or_32(&igb->igb_state, IGB_SUSPENDED); 1194 1195 /* 1196 * Disable interrupts 1197 */ 1198 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1199 (void) igb_disable_intrs(igb); 1200 } 1201 1202 if (!(igb->igb_state & IGB_STARTED)) { 1203 mutex_exit(&igb->gen_lock); 1204 return (DDI_SUCCESS); 1205 } 1206 1207 igb_stop(igb, B_FALSE); 1208 1209 mutex_exit(&igb->gen_lock); 1210 1211 /* 1212 * Disable and stop the watchdog timer 1213 */ 1214 igb_disable_watchdog_timer(igb); 1215 1216 return (DDI_SUCCESS); 1217 } 1218 1219 static int 1220 igb_init(igb_t *igb) 1221 { 1222 mutex_enter(&igb->gen_lock); 1223 1224 /* 1225 * Initilize the adapter 1226 */ 1227 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1228 mutex_exit(&igb->gen_lock); 1229 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1230 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1231 return (IGB_FAILURE); 1232 } 1233 1234 mutex_exit(&igb->gen_lock); 1235 1236 return (IGB_SUCCESS); 1237 } 1238 1239 /* 1240 * igb_init_mac_address - Initialize the default MAC address 1241 * 1242 * On success, the MAC address is entered in the igb->hw.mac.addr 1243 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive 1244 * address register. 1245 * 1246 * Important side effects: 1247 * 1. adapter is reset - this is required to put it in a known state. 1248 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where 1249 * MAC address and all default settings are stored, so a valid checksum 1250 * is required. 1251 */ 1252 static int 1253 igb_init_mac_address(igb_t *igb) 1254 { 1255 struct e1000_hw *hw = &igb->hw; 1256 1257 ASSERT(mutex_owned(&igb->gen_lock)); 1258 1259 /* 1260 * Reset chipset to put the hardware in a known state 1261 * before we try to get MAC address from NVM. 1262 */ 1263 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1264 igb_error(igb, "Adapter reset failed."); 1265 goto init_mac_fail; 1266 } 1267 1268 /* 1269 * NVM validation 1270 */ 1271 if (((igb->hw.mac.type != e1000_i210) && 1272 (igb->hw.mac.type != e1000_i211)) && 1273 (e1000_validate_nvm_checksum(hw) < 0)) { 1274 /* 1275 * Some PCI-E parts fail the first check due to 1276 * the link being in sleep state. Call it again, 1277 * if it fails a second time its a real issue. 1278 */ 1279 if (e1000_validate_nvm_checksum(hw) < 0) { 1280 igb_error(igb, 1281 "Invalid NVM checksum. Please contact " 1282 "the vendor to update the NVM."); 1283 goto init_mac_fail; 1284 } 1285 } 1286 1287 /* 1288 * Get the mac address 1289 * This function should handle SPARC case correctly. 1290 */ 1291 if (!igb_find_mac_address(igb)) { 1292 igb_error(igb, "Failed to get the mac address"); 1293 goto init_mac_fail; 1294 } 1295 1296 /* Validate mac address */ 1297 if (!is_valid_mac_addr(hw->mac.addr)) { 1298 igb_error(igb, "Invalid mac address"); 1299 goto init_mac_fail; 1300 } 1301 1302 return (IGB_SUCCESS); 1303 1304 init_mac_fail: 1305 return (IGB_FAILURE); 1306 } 1307 1308 /* 1309 * igb_init_adapter - Initialize the adapter 1310 */ 1311 static int 1312 igb_init_adapter(igb_t *igb) 1313 { 1314 struct e1000_hw *hw = &igb->hw; 1315 uint32_t pba; 1316 int oemid[2]; 1317 uint16_t nvmword; 1318 uint32_t hwm; 1319 uint32_t default_mtu; 1320 u8 pbanum[E1000_PBANUM_LENGTH]; 1321 char eepromver[5]; /* f.ff */ 1322 int i; 1323 1324 ASSERT(mutex_owned(&igb->gen_lock)); 1325 1326 /* 1327 * In order to obtain the default MAC address, this will reset the 1328 * adapter and validate the NVM that the address and many other 1329 * default settings come from. 1330 */ 1331 if (igb_init_mac_address(igb) != IGB_SUCCESS) { 1332 igb_error(igb, "Failed to initialize MAC address"); 1333 goto init_adapter_fail; 1334 } 1335 1336 /* 1337 * Packet Buffer Allocation (PBA) 1338 * Writing PBA sets the receive portion of the buffer 1339 * the remainder is used for the transmit buffer. 1340 */ 1341 switch (hw->mac.type) { 1342 case e1000_82575: 1343 pba = E1000_PBA_32K; 1344 break; 1345 case e1000_82576: 1346 pba = E1000_READ_REG(hw, E1000_RXPBS); 1347 pba &= E1000_RXPBS_SIZE_MASK_82576; 1348 break; 1349 case e1000_82580: 1350 case e1000_i350: 1351 case e1000_i354: 1352 pba = E1000_READ_REG(hw, E1000_RXPBS); 1353 pba = e1000_rxpbs_adjust_82580(pba); 1354 break; 1355 case e1000_i210: 1356 case e1000_i211: 1357 pba = E1000_PBA_34K; 1358 default: 1359 break; 1360 } 1361 1362 /* Special needs in case of Jumbo frames */ 1363 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 1364 MIN_MTU, MAX_MTU, DEFAULT_MTU); 1365 if ((hw->mac.type == e1000_82575) && (default_mtu > ETHERMTU)) { 1366 u32 tx_space, min_tx, min_rx; 1367 pba = E1000_READ_REG(hw, E1000_PBA); 1368 tx_space = pba >> 16; 1369 pba &= 0xffff; 1370 min_tx = (igb->max_frame_size + 1371 sizeof (struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 1372 min_tx = roundup(min_tx, 1024); 1373 min_tx >>= 10; 1374 min_rx = igb->max_frame_size; 1375 min_rx = roundup(min_rx, 1024); 1376 min_rx >>= 10; 1377 if (tx_space < min_tx && 1378 ((min_tx - tx_space) < pba)) { 1379 pba = pba - (min_tx - tx_space); 1380 /* 1381 * if short on rx space, rx wins 1382 * and must trump tx adjustment 1383 */ 1384 if (pba < min_rx) 1385 pba = min_rx; 1386 } 1387 E1000_WRITE_REG(hw, E1000_PBA, pba); 1388 } 1389 1390 DEBUGOUT1("igb_init: pba=%dK", pba); 1391 1392 /* 1393 * These parameters control the automatic generation (Tx) and 1394 * response (Rx) to Ethernet PAUSE frames. 1395 * - High water mark should allow for at least two frames to be 1396 * received after sending an XOFF. 1397 * - Low water mark works best when it is very near the high water mark. 1398 * This allows the receiver to restart by sending XON when it has 1399 * drained a bit. 1400 */ 1401 hwm = min(((pba << 10) * 9 / 10), 1402 ((pba << 10) - 2 * igb->max_frame_size)); 1403 1404 if (hw->mac.type < e1000_82576) { 1405 hw->fc.high_water = hwm & 0xFFF8; /* 8-byte granularity */ 1406 hw->fc.low_water = hw->fc.high_water - 8; 1407 } else { 1408 hw->fc.high_water = hwm & 0xFFF0; /* 16-byte granularity */ 1409 hw->fc.low_water = hw->fc.high_water - 16; 1410 } 1411 1412 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1413 hw->fc.send_xon = B_TRUE; 1414 1415 (void) e1000_validate_mdi_setting(hw); 1416 1417 /* 1418 * Reset the chipset hardware the second time to put PBA settings 1419 * into effect. 1420 */ 1421 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1422 igb_error(igb, "Second reset failed"); 1423 goto init_adapter_fail; 1424 } 1425 1426 /* 1427 * Don't wait for auto-negotiation to complete 1428 */ 1429 hw->phy.autoneg_wait_to_complete = B_FALSE; 1430 1431 /* 1432 * Copper options 1433 */ 1434 if (hw->phy.media_type == e1000_media_type_copper) { 1435 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1436 hw->phy.disable_polarity_correction = B_FALSE; 1437 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1438 } 1439 1440 /* 1441 * Initialize link settings 1442 */ 1443 (void) igb_setup_link(igb, B_FALSE); 1444 1445 /* 1446 * Configure/Initialize hardware 1447 */ 1448 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1449 igb_error(igb, "Failed to initialize hardware"); 1450 goto init_adapter_fail; 1451 } 1452 1453 /* 1454 * Start the link setup timer 1455 */ 1456 igb_start_link_timer(igb); 1457 1458 /* 1459 * Disable wakeup control by default 1460 */ 1461 E1000_WRITE_REG(hw, E1000_WUC, 0); 1462 1463 /* 1464 * Record phy info in hw struct 1465 */ 1466 (void) e1000_get_phy_info(hw); 1467 1468 /* 1469 * Make sure driver has control 1470 */ 1471 igb_get_driver_control(hw); 1472 1473 /* 1474 * Restore LED settings to the default from EEPROM 1475 * to meet the standard for Sun platforms. 1476 */ 1477 (void) e1000_cleanup_led(hw); 1478 1479 /* 1480 * Setup MSI-X interrupts 1481 */ 1482 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1483 igb->capab->setup_msix(igb); 1484 1485 /* 1486 * Initialize unicast addresses. 1487 */ 1488 igb_init_unicst(igb); 1489 1490 /* 1491 * Setup and initialize the mctable structures. 1492 */ 1493 igb_setup_multicst(igb); 1494 1495 /* 1496 * Set interrupt throttling rate 1497 */ 1498 for (i = 0; i < igb->intr_cnt; i++) 1499 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1500 1501 /* 1502 * Read identifying information and place in devinfo. 1503 */ 1504 nvmword = 0xffff; 1505 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_0, 1, &nvmword); 1506 oemid[0] = (int)nvmword; 1507 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_1, 1, &nvmword); 1508 oemid[1] = (int)nvmword; 1509 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, igb->dip, 1510 "oem-identifier", oemid, 2); 1511 1512 pbanum[0] = '\0'; 1513 (void) e1000_read_pba_string(&igb->hw, pbanum, sizeof (pbanum)); 1514 if (*pbanum != '\0') { 1515 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip, 1516 "printed-board-assembly", (char *)pbanum); 1517 } 1518 1519 nvmword = 0xffff; 1520 (void) e1000_read_nvm(&igb->hw, NVM_VERSION, 1, &nvmword); 1521 if ((nvmword & 0xf00) == 0) { 1522 (void) snprintf(eepromver, sizeof (eepromver), "%x.%x", 1523 (nvmword & 0xf000) >> 12, (nvmword & 0xff)); 1524 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip, 1525 "nvm-version", eepromver); 1526 } 1527 1528 /* 1529 * Save the state of the phy 1530 */ 1531 igb_get_phy_state(igb); 1532 1533 igb_param_sync(igb); 1534 1535 return (IGB_SUCCESS); 1536 1537 init_adapter_fail: 1538 /* 1539 * Reset PHY if possible 1540 */ 1541 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1542 (void) e1000_phy_hw_reset(hw); 1543 1544 return (IGB_FAILURE); 1545 } 1546 1547 /* 1548 * igb_stop_adapter - Stop the adapter 1549 */ 1550 static void 1551 igb_stop_adapter(igb_t *igb) 1552 { 1553 struct e1000_hw *hw = &igb->hw; 1554 1555 ASSERT(mutex_owned(&igb->gen_lock)); 1556 1557 /* Stop the link setup timer */ 1558 igb_stop_link_timer(igb); 1559 1560 /* Tell firmware driver is no longer in control */ 1561 igb_release_driver_control(hw); 1562 1563 /* 1564 * Reset the chipset 1565 */ 1566 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1567 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1568 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1569 } 1570 1571 /* 1572 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient 1573 */ 1574 } 1575 1576 /* 1577 * igb_reset - Reset the chipset and restart the driver. 1578 * 1579 * It involves stopping and re-starting the chipset, 1580 * and re-configuring the rx/tx rings. 1581 */ 1582 static int 1583 igb_reset(igb_t *igb) 1584 { 1585 int i; 1586 1587 mutex_enter(&igb->gen_lock); 1588 1589 ASSERT(igb->igb_state & IGB_STARTED); 1590 atomic_and_32(&igb->igb_state, ~IGB_STARTED); 1591 1592 /* 1593 * Disable the adapter interrupts to stop any rx/tx activities 1594 * before draining pending data and resetting hardware. 1595 */ 1596 igb_disable_adapter_interrupts(igb); 1597 1598 /* 1599 * Drain the pending transmit packets 1600 */ 1601 (void) igb_tx_drain(igb); 1602 1603 for (i = 0; i < igb->num_rx_rings; i++) 1604 mutex_enter(&igb->rx_rings[i].rx_lock); 1605 for (i = 0; i < igb->num_tx_rings; i++) 1606 mutex_enter(&igb->tx_rings[i].tx_lock); 1607 1608 /* 1609 * Stop the adapter 1610 */ 1611 igb_stop_adapter(igb); 1612 1613 /* 1614 * Clean the pending tx data/resources 1615 */ 1616 igb_tx_clean(igb); 1617 1618 /* 1619 * Start the adapter 1620 */ 1621 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1622 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1623 goto reset_failure; 1624 } 1625 1626 /* 1627 * Setup the rx/tx rings 1628 */ 1629 igb->tx_ring_init = B_FALSE; 1630 igb_setup_rings(igb); 1631 1632 atomic_and_32(&igb->igb_state, ~(IGB_ERROR | IGB_STALL)); 1633 1634 /* 1635 * Enable adapter interrupts 1636 * The interrupts must be enabled after the driver state is START 1637 */ 1638 igb->capab->enable_intr(igb); 1639 1640 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1641 goto reset_failure; 1642 1643 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1644 goto reset_failure; 1645 1646 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1647 mutex_exit(&igb->tx_rings[i].tx_lock); 1648 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1649 mutex_exit(&igb->rx_rings[i].rx_lock); 1650 1651 atomic_or_32(&igb->igb_state, IGB_STARTED); 1652 1653 mutex_exit(&igb->gen_lock); 1654 1655 return (IGB_SUCCESS); 1656 1657 reset_failure: 1658 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1659 mutex_exit(&igb->tx_rings[i].tx_lock); 1660 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1661 mutex_exit(&igb->rx_rings[i].rx_lock); 1662 1663 mutex_exit(&igb->gen_lock); 1664 1665 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1666 1667 return (IGB_FAILURE); 1668 } 1669 1670 /* 1671 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1672 */ 1673 static void 1674 igb_tx_clean(igb_t *igb) 1675 { 1676 igb_tx_ring_t *tx_ring; 1677 tx_control_block_t *tcb; 1678 link_list_t pending_list; 1679 uint32_t desc_num; 1680 int i, j; 1681 1682 LINK_LIST_INIT(&pending_list); 1683 1684 for (i = 0; i < igb->num_tx_rings; i++) { 1685 tx_ring = &igb->tx_rings[i]; 1686 1687 mutex_enter(&tx_ring->recycle_lock); 1688 1689 /* 1690 * Clean the pending tx data - the pending packets in the 1691 * work_list that have no chances to be transmitted again. 1692 * 1693 * We must ensure the chipset is stopped or the link is down 1694 * before cleaning the transmit packets. 1695 */ 1696 desc_num = 0; 1697 for (j = 0; j < tx_ring->ring_size; j++) { 1698 tcb = tx_ring->work_list[j]; 1699 if (tcb != NULL) { 1700 desc_num += tcb->desc_num; 1701 1702 tx_ring->work_list[j] = NULL; 1703 1704 igb_free_tcb(tcb); 1705 1706 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1707 } 1708 } 1709 1710 if (desc_num > 0) { 1711 atomic_add_32(&tx_ring->tbd_free, desc_num); 1712 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1713 1714 /* 1715 * Reset the head and tail pointers of the tbd ring; 1716 * Reset the head write-back if it is enabled. 1717 */ 1718 tx_ring->tbd_head = 0; 1719 tx_ring->tbd_tail = 0; 1720 if (igb->tx_head_wb_enable) 1721 *tx_ring->tbd_head_wb = 0; 1722 1723 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1724 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1725 } 1726 1727 mutex_exit(&tx_ring->recycle_lock); 1728 1729 /* 1730 * Add the tx control blocks in the pending list to 1731 * the free list. 1732 */ 1733 igb_put_free_list(tx_ring, &pending_list); 1734 } 1735 } 1736 1737 /* 1738 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1739 */ 1740 static boolean_t 1741 igb_tx_drain(igb_t *igb) 1742 { 1743 igb_tx_ring_t *tx_ring; 1744 boolean_t done; 1745 int i, j; 1746 1747 /* 1748 * Wait for a specific time to allow pending tx packets 1749 * to be transmitted. 1750 * 1751 * Check the counter tbd_free to see if transmission is done. 1752 * No lock protection is needed here. 1753 * 1754 * Return B_TRUE if all pending packets have been transmitted; 1755 * Otherwise return B_FALSE; 1756 */ 1757 for (i = 0; i < TX_DRAIN_TIME; i++) { 1758 1759 done = B_TRUE; 1760 for (j = 0; j < igb->num_tx_rings; j++) { 1761 tx_ring = &igb->tx_rings[j]; 1762 done = done && 1763 (tx_ring->tbd_free == tx_ring->ring_size); 1764 } 1765 1766 if (done) 1767 break; 1768 1769 msec_delay(1); 1770 } 1771 1772 return (done); 1773 } 1774 1775 /* 1776 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1777 */ 1778 static boolean_t 1779 igb_rx_drain(igb_t *igb) 1780 { 1781 boolean_t done; 1782 int i; 1783 1784 /* 1785 * Polling the rx free list to check if those rx buffers held by 1786 * the upper layer are released. 1787 * 1788 * Check the counter rcb_free to see if all pending buffers are 1789 * released. No lock protection is needed here. 1790 * 1791 * Return B_TRUE if all pending buffers have been released; 1792 * Otherwise return B_FALSE; 1793 */ 1794 for (i = 0; i < RX_DRAIN_TIME; i++) { 1795 done = (igb->rcb_pending == 0); 1796 1797 if (done) 1798 break; 1799 1800 msec_delay(1); 1801 } 1802 1803 return (done); 1804 } 1805 1806 /* 1807 * igb_start - Start the driver/chipset 1808 */ 1809 int 1810 igb_start(igb_t *igb, boolean_t alloc_buffer) 1811 { 1812 int i; 1813 1814 ASSERT(mutex_owned(&igb->gen_lock)); 1815 1816 if (alloc_buffer) { 1817 if (igb_alloc_rx_data(igb) != IGB_SUCCESS) { 1818 igb_error(igb, 1819 "Failed to allocate software receive rings"); 1820 return (IGB_FAILURE); 1821 } 1822 1823 /* Allocate buffers for all the rx/tx rings */ 1824 if (igb_alloc_dma(igb) != IGB_SUCCESS) { 1825 igb_error(igb, "Failed to allocate DMA resource"); 1826 return (IGB_FAILURE); 1827 } 1828 1829 igb->tx_ring_init = B_TRUE; 1830 } else { 1831 igb->tx_ring_init = B_FALSE; 1832 } 1833 1834 for (i = 0; i < igb->num_rx_rings; i++) 1835 mutex_enter(&igb->rx_rings[i].rx_lock); 1836 for (i = 0; i < igb->num_tx_rings; i++) 1837 mutex_enter(&igb->tx_rings[i].tx_lock); 1838 1839 /* 1840 * Start the adapter 1841 */ 1842 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) { 1843 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1844 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1845 goto start_failure; 1846 } 1847 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 1848 } 1849 1850 /* 1851 * Setup the rx/tx rings 1852 */ 1853 igb_setup_rings(igb); 1854 1855 /* 1856 * Enable adapter interrupts 1857 * The interrupts must be enabled after the driver state is START 1858 */ 1859 igb->capab->enable_intr(igb); 1860 1861 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1862 goto start_failure; 1863 1864 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1865 goto start_failure; 1866 1867 if (igb->hw.mac.type == e1000_i350) 1868 (void) e1000_set_eee_i350(&igb->hw, B_FALSE, B_FALSE); 1869 else if (igb->hw.mac.type == e1000_i354) 1870 (void) e1000_set_eee_i354(&igb->hw, B_FALSE, B_FALSE); 1871 1872 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1873 mutex_exit(&igb->tx_rings[i].tx_lock); 1874 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1875 mutex_exit(&igb->rx_rings[i].rx_lock); 1876 1877 return (IGB_SUCCESS); 1878 1879 start_failure: 1880 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1881 mutex_exit(&igb->tx_rings[i].tx_lock); 1882 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1883 mutex_exit(&igb->rx_rings[i].rx_lock); 1884 1885 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1886 1887 return (IGB_FAILURE); 1888 } 1889 1890 /* 1891 * igb_stop - Stop the driver/chipset 1892 */ 1893 void 1894 igb_stop(igb_t *igb, boolean_t free_buffer) 1895 { 1896 int i; 1897 1898 ASSERT(mutex_owned(&igb->gen_lock)); 1899 1900 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER; 1901 1902 /* 1903 * Disable the adapter interrupts 1904 */ 1905 igb_disable_adapter_interrupts(igb); 1906 1907 /* 1908 * Drain the pending tx packets 1909 */ 1910 (void) igb_tx_drain(igb); 1911 1912 for (i = 0; i < igb->num_rx_rings; i++) 1913 mutex_enter(&igb->rx_rings[i].rx_lock); 1914 for (i = 0; i < igb->num_tx_rings; i++) 1915 mutex_enter(&igb->tx_rings[i].tx_lock); 1916 1917 /* 1918 * Stop the adapter 1919 */ 1920 igb_stop_adapter(igb); 1921 1922 /* 1923 * Clean the pending tx data/resources 1924 */ 1925 igb_tx_clean(igb); 1926 1927 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1928 mutex_exit(&igb->tx_rings[i].tx_lock); 1929 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1930 mutex_exit(&igb->rx_rings[i].rx_lock); 1931 1932 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1933 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1934 1935 if (igb->link_state == LINK_STATE_UP) { 1936 igb->link_state = LINK_STATE_UNKNOWN; 1937 mac_link_update(igb->mac_hdl, igb->link_state); 1938 } 1939 1940 if (free_buffer) { 1941 /* 1942 * Release the DMA/memory resources of rx/tx rings 1943 */ 1944 igb_free_dma(igb); 1945 igb_free_rx_data(igb); 1946 } 1947 } 1948 1949 /* 1950 * igb_alloc_rings - Allocate memory space for rx/tx rings 1951 */ 1952 static int 1953 igb_alloc_rings(igb_t *igb) 1954 { 1955 /* 1956 * Allocate memory space for rx rings 1957 */ 1958 igb->rx_rings = kmem_zalloc( 1959 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1960 KM_NOSLEEP); 1961 1962 if (igb->rx_rings == NULL) { 1963 return (IGB_FAILURE); 1964 } 1965 1966 /* 1967 * Allocate memory space for tx rings 1968 */ 1969 igb->tx_rings = kmem_zalloc( 1970 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1971 KM_NOSLEEP); 1972 1973 if (igb->tx_rings == NULL) { 1974 kmem_free(igb->rx_rings, 1975 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1976 igb->rx_rings = NULL; 1977 return (IGB_FAILURE); 1978 } 1979 1980 /* 1981 * Allocate memory space for rx ring groups 1982 */ 1983 igb->rx_groups = kmem_zalloc( 1984 sizeof (igb_rx_group_t) * igb->num_rx_groups, 1985 KM_NOSLEEP); 1986 1987 if (igb->rx_groups == NULL) { 1988 kmem_free(igb->rx_rings, 1989 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1990 kmem_free(igb->tx_rings, 1991 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1992 igb->rx_rings = NULL; 1993 igb->tx_rings = NULL; 1994 return (IGB_FAILURE); 1995 } 1996 1997 return (IGB_SUCCESS); 1998 } 1999 2000 /* 2001 * igb_free_rings - Free the memory space of rx/tx rings. 2002 */ 2003 static void 2004 igb_free_rings(igb_t *igb) 2005 { 2006 if (igb->rx_rings != NULL) { 2007 kmem_free(igb->rx_rings, 2008 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 2009 igb->rx_rings = NULL; 2010 } 2011 2012 if (igb->tx_rings != NULL) { 2013 kmem_free(igb->tx_rings, 2014 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 2015 igb->tx_rings = NULL; 2016 } 2017 2018 if (igb->rx_groups != NULL) { 2019 kmem_free(igb->rx_groups, 2020 sizeof (igb_rx_group_t) * igb->num_rx_groups); 2021 igb->rx_groups = NULL; 2022 } 2023 } 2024 2025 static int 2026 igb_alloc_rx_data(igb_t *igb) 2027 { 2028 igb_rx_ring_t *rx_ring; 2029 int i; 2030 2031 for (i = 0; i < igb->num_rx_rings; i++) { 2032 rx_ring = &igb->rx_rings[i]; 2033 if (igb_alloc_rx_ring_data(rx_ring) != IGB_SUCCESS) 2034 goto alloc_rx_rings_failure; 2035 } 2036 return (IGB_SUCCESS); 2037 2038 alloc_rx_rings_failure: 2039 igb_free_rx_data(igb); 2040 return (IGB_FAILURE); 2041 } 2042 2043 static void 2044 igb_free_rx_data(igb_t *igb) 2045 { 2046 igb_rx_ring_t *rx_ring; 2047 igb_rx_data_t *rx_data; 2048 int i; 2049 2050 for (i = 0; i < igb->num_rx_rings; i++) { 2051 rx_ring = &igb->rx_rings[i]; 2052 2053 mutex_enter(&igb->rx_pending_lock); 2054 rx_data = rx_ring->rx_data; 2055 2056 if (rx_data != NULL) { 2057 rx_data->flag |= IGB_RX_STOPPED; 2058 2059 if (rx_data->rcb_pending == 0) { 2060 igb_free_rx_ring_data(rx_data); 2061 rx_ring->rx_data = NULL; 2062 } 2063 } 2064 2065 mutex_exit(&igb->rx_pending_lock); 2066 } 2067 } 2068 2069 /* 2070 * igb_setup_rings - Setup rx/tx rings 2071 */ 2072 static void 2073 igb_setup_rings(igb_t *igb) 2074 { 2075 /* 2076 * Setup the rx/tx rings, including the following: 2077 * 2078 * 1. Setup the descriptor ring and the control block buffers; 2079 * 2. Initialize necessary registers for receive/transmit; 2080 * 3. Initialize software pointers/parameters for receive/transmit; 2081 */ 2082 igb_setup_rx(igb); 2083 2084 igb_setup_tx(igb); 2085 } 2086 2087 static void 2088 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 2089 { 2090 igb_t *igb = rx_ring->igb; 2091 igb_rx_data_t *rx_data = rx_ring->rx_data; 2092 struct e1000_hw *hw = &igb->hw; 2093 rx_control_block_t *rcb; 2094 union e1000_adv_rx_desc *rbd; 2095 uint32_t size; 2096 uint32_t buf_low; 2097 uint32_t buf_high; 2098 uint32_t rxdctl; 2099 int i; 2100 2101 ASSERT(mutex_owned(&rx_ring->rx_lock)); 2102 ASSERT(mutex_owned(&igb->gen_lock)); 2103 2104 /* 2105 * Initialize descriptor ring with buffer addresses 2106 */ 2107 for (i = 0; i < igb->rx_ring_size; i++) { 2108 rcb = rx_data->work_list[i]; 2109 rbd = &rx_data->rbd_ring[i]; 2110 2111 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 2112 rbd->read.hdr_addr = NULL; 2113 } 2114 2115 /* 2116 * Initialize the base address registers 2117 */ 2118 buf_low = (uint32_t)rx_data->rbd_area.dma_address; 2119 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32); 2120 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 2121 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 2122 2123 /* 2124 * Initialize the length register 2125 */ 2126 size = rx_data->ring_size * sizeof (union e1000_adv_rx_desc); 2127 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 2128 2129 /* 2130 * Initialize buffer size & descriptor type 2131 */ 2132 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), 2133 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 2134 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF)); 2135 2136 /* 2137 * Setup the Receive Descriptor Control Register (RXDCTL) 2138 */ 2139 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 2140 rxdctl &= igb->capab->rxdctl_mask; 2141 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 2142 rxdctl |= 16; /* pthresh */ 2143 rxdctl |= 8 << 8; /* hthresh */ 2144 rxdctl |= 1 << 16; /* wthresh */ 2145 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl); 2146 2147 rx_data->rbd_next = 0; 2148 } 2149 2150 static void 2151 igb_setup_rx(igb_t *igb) 2152 { 2153 igb_rx_ring_t *rx_ring; 2154 igb_rx_data_t *rx_data; 2155 igb_rx_group_t *rx_group; 2156 struct e1000_hw *hw = &igb->hw; 2157 uint32_t rctl, rxcsum; 2158 uint32_t ring_per_group; 2159 int i; 2160 2161 /* 2162 * Setup the Receive Control Register (RCTL), and enable the 2163 * receiver. The initial configuration is to: enable the receiver, 2164 * accept broadcasts, discard bad packets, accept long packets, 2165 * disable VLAN filter checking, and set receive buffer size to 2166 * 2k. For 82575, also set the receive descriptor minimum 2167 * threshold size to 1/2 the ring. 2168 */ 2169 rctl = E1000_READ_REG(hw, E1000_RCTL); 2170 2171 /* 2172 * Clear the field used for wakeup control. This driver doesn't do 2173 * wakeup but leave this here for completeness. 2174 */ 2175 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2176 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 2177 2178 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 2179 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 2180 E1000_RCTL_LPE | /* Large Packet Enable */ 2181 /* Multicast filter offset */ 2182 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 2183 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */ 2184 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 2185 2186 for (i = 0; i < igb->num_rx_groups; i++) { 2187 rx_group = &igb->rx_groups[i]; 2188 rx_group->index = i; 2189 rx_group->igb = igb; 2190 } 2191 2192 /* 2193 * Set up all rx descriptor rings - must be called before receive unit 2194 * enabled. 2195 */ 2196 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2197 for (i = 0; i < igb->num_rx_rings; i++) { 2198 rx_ring = &igb->rx_rings[i]; 2199 igb_setup_rx_ring(rx_ring); 2200 2201 /* 2202 * Map a ring to a group by assigning a group index 2203 */ 2204 rx_ring->group_index = i / ring_per_group; 2205 } 2206 2207 /* 2208 * Setup the Rx Long Packet Max Length register 2209 */ 2210 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 2211 2212 /* 2213 * Hardware checksum settings 2214 */ 2215 if (igb->rx_hcksum_enable) { 2216 rxcsum = 2217 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 2218 E1000_RXCSUM_IPOFL; /* IP checksum */ 2219 2220 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2221 } 2222 2223 /* 2224 * Setup classify and RSS for multiple receive queues 2225 */ 2226 switch (igb->vmdq_mode) { 2227 case E1000_VMDQ_OFF: 2228 /* 2229 * One ring group, only RSS is needed when more than 2230 * one ring enabled. 2231 */ 2232 if (igb->num_rx_rings > 1) 2233 igb_setup_rss(igb); 2234 break; 2235 case E1000_VMDQ_MAC: 2236 /* 2237 * Multiple groups, each group has one ring, 2238 * only the MAC classification is needed. 2239 */ 2240 igb_setup_mac_classify(igb); 2241 break; 2242 case E1000_VMDQ_MAC_RSS: 2243 /* 2244 * Multiple groups and multiple rings, both 2245 * MAC classification and RSS are needed. 2246 */ 2247 igb_setup_mac_rss_classify(igb); 2248 break; 2249 } 2250 2251 /* 2252 * Enable the receive unit - must be done after all 2253 * the rx setup above. 2254 */ 2255 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2256 2257 /* 2258 * Initialize all adapter ring head & tail pointers - must 2259 * be done after receive unit is enabled 2260 */ 2261 for (i = 0; i < igb->num_rx_rings; i++) { 2262 rx_ring = &igb->rx_rings[i]; 2263 rx_data = rx_ring->rx_data; 2264 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 2265 E1000_WRITE_REG(hw, E1000_RDT(i), rx_data->ring_size - 1); 2266 } 2267 2268 /* 2269 * 82575 with manageability enabled needs a special flush to make 2270 * sure the fifos start clean. 2271 */ 2272 if ((hw->mac.type == e1000_82575) && 2273 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) { 2274 e1000_rx_fifo_flush_82575(hw); 2275 } 2276 } 2277 2278 static void 2279 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 2280 { 2281 igb_t *igb = tx_ring->igb; 2282 struct e1000_hw *hw = &igb->hw; 2283 uint32_t size; 2284 uint32_t buf_low; 2285 uint32_t buf_high; 2286 uint32_t reg_val; 2287 2288 ASSERT(mutex_owned(&tx_ring->tx_lock)); 2289 ASSERT(mutex_owned(&igb->gen_lock)); 2290 2291 2292 /* 2293 * Initialize the length register 2294 */ 2295 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 2296 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 2297 2298 /* 2299 * Initialize the base address registers 2300 */ 2301 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 2302 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 2303 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 2304 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 2305 2306 /* 2307 * Setup head & tail pointers 2308 */ 2309 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 2310 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 2311 2312 /* 2313 * Setup head write-back 2314 */ 2315 if (igb->tx_head_wb_enable) { 2316 /* 2317 * The memory of the head write-back is allocated using 2318 * the extra tbd beyond the tail of the tbd ring. 2319 */ 2320 tx_ring->tbd_head_wb = (uint32_t *) 2321 ((uintptr_t)tx_ring->tbd_area.address + size); 2322 *tx_ring->tbd_head_wb = 0; 2323 2324 buf_low = (uint32_t) 2325 (tx_ring->tbd_area.dma_address + size); 2326 buf_high = (uint32_t) 2327 ((tx_ring->tbd_area.dma_address + size) >> 32); 2328 2329 /* Set the head write-back enable bit */ 2330 buf_low |= E1000_TX_HEAD_WB_ENABLE; 2331 2332 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 2333 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 2334 2335 /* 2336 * Turn off relaxed ordering for head write back or it will 2337 * cause problems with the tx recycling 2338 */ 2339 reg_val = E1000_READ_REG(hw, 2340 E1000_DCA_TXCTRL(tx_ring->index)); 2341 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 2342 E1000_WRITE_REG(hw, 2343 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 2344 } else { 2345 tx_ring->tbd_head_wb = NULL; 2346 } 2347 2348 tx_ring->tbd_head = 0; 2349 tx_ring->tbd_tail = 0; 2350 tx_ring->tbd_free = tx_ring->ring_size; 2351 2352 if (igb->tx_ring_init == B_TRUE) { 2353 tx_ring->tcb_head = 0; 2354 tx_ring->tcb_tail = 0; 2355 tx_ring->tcb_free = tx_ring->free_list_size; 2356 } 2357 2358 /* 2359 * Enable TXDCTL per queue 2360 */ 2361 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index)); 2362 reg_val |= E1000_TXDCTL_QUEUE_ENABLE; 2363 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val); 2364 2365 /* 2366 * Initialize hardware checksum offload settings 2367 */ 2368 bzero(&tx_ring->tx_context, sizeof (tx_context_t)); 2369 } 2370 2371 static void 2372 igb_setup_tx(igb_t *igb) 2373 { 2374 igb_tx_ring_t *tx_ring; 2375 struct e1000_hw *hw = &igb->hw; 2376 uint32_t reg_val; 2377 int i; 2378 2379 for (i = 0; i < igb->num_tx_rings; i++) { 2380 tx_ring = &igb->tx_rings[i]; 2381 igb_setup_tx_ring(tx_ring); 2382 } 2383 2384 /* 2385 * Setup the Transmit Control Register (TCTL) 2386 */ 2387 reg_val = E1000_READ_REG(hw, E1000_TCTL); 2388 reg_val &= ~E1000_TCTL_CT; 2389 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2390 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2391 2392 /* Enable transmits */ 2393 reg_val |= E1000_TCTL_EN; 2394 2395 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 2396 } 2397 2398 /* 2399 * igb_setup_rss - Setup receive-side scaling feature 2400 */ 2401 static void 2402 igb_setup_rss(igb_t *igb) 2403 { 2404 struct e1000_hw *hw = &igb->hw; 2405 uint32_t i, mrqc, rxcsum; 2406 int shift = 0; 2407 uint32_t random; 2408 union e1000_reta { 2409 uint32_t dword; 2410 uint8_t bytes[4]; 2411 } reta; 2412 2413 /* Setup the Redirection Table */ 2414 if (hw->mac.type == e1000_82576) { 2415 shift = 3; 2416 } else if (hw->mac.type == e1000_82575) { 2417 shift = 6; 2418 } 2419 for (i = 0; i < (32 * 4); i++) { 2420 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 2421 if ((i & 3) == 3) { 2422 E1000_WRITE_REG(hw, 2423 (E1000_RETA(0) + (i & ~3)), reta.dword); 2424 } 2425 } 2426 2427 /* Fill out hash function seeds */ 2428 for (i = 0; i < 10; i++) { 2429 (void) random_get_pseudo_bytes((uint8_t *)&random, 2430 sizeof (uint32_t)); 2431 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2432 } 2433 2434 /* Setup the Multiple Receive Queue Control register */ 2435 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2436 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2437 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2438 E1000_MRQC_RSS_FIELD_IPV6 | 2439 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2440 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2441 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2442 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2443 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2444 2445 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2446 2447 /* 2448 * Disable Packet Checksum to enable RSS for multiple receive queues. 2449 * 2450 * The Packet Checksum is not ethernet CRC. It is another kind of 2451 * checksum offloading provided by the 82575 chipset besides the IP 2452 * header checksum offloading and the TCP/UDP checksum offloading. 2453 * The Packet Checksum is by default computed over the entire packet 2454 * from the first byte of the DA through the last byte of the CRC, 2455 * including the Ethernet and IP headers. 2456 * 2457 * It is a hardware limitation that Packet Checksum is mutually 2458 * exclusive with RSS. 2459 */ 2460 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2461 rxcsum |= E1000_RXCSUM_PCSD; 2462 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2463 } 2464 2465 /* 2466 * igb_setup_mac_rss_classify - Setup MAC classification and rss 2467 */ 2468 static void 2469 igb_setup_mac_rss_classify(igb_t *igb) 2470 { 2471 struct e1000_hw *hw = &igb->hw; 2472 uint32_t i, mrqc, vmdctl, rxcsum; 2473 uint32_t ring_per_group; 2474 int shift_group0, shift_group1; 2475 uint32_t random; 2476 union e1000_reta { 2477 uint32_t dword; 2478 uint8_t bytes[4]; 2479 } reta; 2480 2481 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2482 2483 /* Setup the Redirection Table, it is shared between two groups */ 2484 shift_group0 = 2; 2485 shift_group1 = 6; 2486 for (i = 0; i < (32 * 4); i++) { 2487 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) | 2488 ((ring_per_group + (i % ring_per_group)) << shift_group1); 2489 if ((i & 3) == 3) { 2490 E1000_WRITE_REG(hw, 2491 (E1000_RETA(0) + (i & ~3)), reta.dword); 2492 } 2493 } 2494 2495 /* Fill out hash function seeds */ 2496 for (i = 0; i < 10; i++) { 2497 (void) random_get_pseudo_bytes((uint8_t *)&random, 2498 sizeof (uint32_t)); 2499 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2500 } 2501 2502 /* 2503 * Setup the Multiple Receive Queue Control register, 2504 * enable VMDq based on packet destination MAC address and RSS. 2505 */ 2506 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP; 2507 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2508 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2509 E1000_MRQC_RSS_FIELD_IPV6 | 2510 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2511 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2512 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2513 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2514 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2515 2516 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2517 2518 2519 /* Define the default group and default queues */ 2520 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE; 2521 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl); 2522 2523 /* 2524 * Disable Packet Checksum to enable RSS for multiple receive queues. 2525 * 2526 * The Packet Checksum is not ethernet CRC. It is another kind of 2527 * checksum offloading provided by the 82575 chipset besides the IP 2528 * header checksum offloading and the TCP/UDP checksum offloading. 2529 * The Packet Checksum is by default computed over the entire packet 2530 * from the first byte of the DA through the last byte of the CRC, 2531 * including the Ethernet and IP headers. 2532 * 2533 * It is a hardware limitation that Packet Checksum is mutually 2534 * exclusive with RSS. 2535 */ 2536 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2537 rxcsum |= E1000_RXCSUM_PCSD; 2538 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2539 } 2540 2541 /* 2542 * igb_setup_mac_classify - Setup MAC classification feature 2543 */ 2544 static void 2545 igb_setup_mac_classify(igb_t *igb) 2546 { 2547 struct e1000_hw *hw = &igb->hw; 2548 uint32_t mrqc, rxcsum; 2549 2550 /* 2551 * Setup the Multiple Receive Queue Control register, 2552 * enable VMDq based on packet destination MAC address. 2553 */ 2554 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP; 2555 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2556 2557 /* 2558 * Disable Packet Checksum to enable RSS for multiple receive queues. 2559 * 2560 * The Packet Checksum is not ethernet CRC. It is another kind of 2561 * checksum offloading provided by the 82575 chipset besides the IP 2562 * header checksum offloading and the TCP/UDP checksum offloading. 2563 * The Packet Checksum is by default computed over the entire packet 2564 * from the first byte of the DA through the last byte of the CRC, 2565 * including the Ethernet and IP headers. 2566 * 2567 * It is a hardware limitation that Packet Checksum is mutually 2568 * exclusive with RSS. 2569 */ 2570 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2571 rxcsum |= E1000_RXCSUM_PCSD; 2572 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2573 2574 } 2575 2576 /* 2577 * igb_init_unicst - Initialize the unicast addresses 2578 */ 2579 static void 2580 igb_init_unicst(igb_t *igb) 2581 { 2582 struct e1000_hw *hw = &igb->hw; 2583 int slot; 2584 2585 /* 2586 * Here we should consider two situations: 2587 * 2588 * 1. Chipset is initialized the first time 2589 * Initialize the multiple unicast addresses, and 2590 * save the default MAC address. 2591 * 2592 * 2. Chipset is reset 2593 * Recover the multiple unicast addresses from the 2594 * software data structure to the RAR registers. 2595 */ 2596 2597 /* 2598 * Clear the default MAC address in the RAR0 rgister, 2599 * which is loaded from EEPROM when system boot or chipreset, 2600 * this will cause the conficts with add_mac/rem_mac entry 2601 * points when VMDq is enabled. For this reason, the RAR0 2602 * must be cleared for both cases mentioned above. 2603 */ 2604 e1000_rar_clear(hw, 0); 2605 2606 if (!igb->unicst_init) { 2607 2608 /* Initialize the multiple unicast addresses */ 2609 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2610 igb->unicst_avail = igb->unicst_total; 2611 2612 for (slot = 0; slot < igb->unicst_total; slot++) 2613 igb->unicst_addr[slot].mac.set = 0; 2614 2615 igb->unicst_init = B_TRUE; 2616 } else { 2617 /* Re-configure the RAR registers */ 2618 for (slot = 0; slot < igb->unicst_total; slot++) { 2619 (void) e1000_rar_set_vmdq(hw, 2620 igb->unicst_addr[slot].mac.addr, 2621 slot, igb->vmdq_mode, 2622 igb->unicst_addr[slot].mac.group_index); 2623 } 2624 } 2625 } 2626 2627 /* 2628 * igb_unicst_find - Find the slot for the specified unicast address 2629 */ 2630 int 2631 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr) 2632 { 2633 int slot; 2634 2635 ASSERT(mutex_owned(&igb->gen_lock)); 2636 2637 for (slot = 0; slot < igb->unicst_total; slot++) { 2638 if (bcmp(igb->unicst_addr[slot].mac.addr, 2639 mac_addr, ETHERADDRL) == 0) 2640 return (slot); 2641 } 2642 2643 return (-1); 2644 } 2645 2646 /* 2647 * igb_unicst_set - Set the unicast address to the specified slot 2648 */ 2649 int 2650 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2651 int slot) 2652 { 2653 struct e1000_hw *hw = &igb->hw; 2654 2655 ASSERT(mutex_owned(&igb->gen_lock)); 2656 2657 /* 2658 * Save the unicast address in the software data structure 2659 */ 2660 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2661 2662 /* 2663 * Set the unicast address to the RAR register 2664 */ 2665 (void) e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2666 2667 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2668 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2669 return (EIO); 2670 } 2671 2672 return (0); 2673 } 2674 2675 /* 2676 * igb_multicst_add - Add a multicst address 2677 */ 2678 int 2679 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2680 { 2681 struct ether_addr *new_table; 2682 size_t new_len; 2683 size_t old_len; 2684 2685 ASSERT(mutex_owned(&igb->gen_lock)); 2686 2687 if ((multiaddr[0] & 01) == 0) { 2688 igb_error(igb, "Illegal multicast address"); 2689 return (EINVAL); 2690 } 2691 2692 if (igb->mcast_count >= igb->mcast_max_num) { 2693 igb_error(igb, "Adapter requested more than %d mcast addresses", 2694 igb->mcast_max_num); 2695 return (ENOENT); 2696 } 2697 2698 if (igb->mcast_count == igb->mcast_alloc_count) { 2699 old_len = igb->mcast_alloc_count * 2700 sizeof (struct ether_addr); 2701 new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) * 2702 sizeof (struct ether_addr); 2703 2704 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2705 if (new_table == NULL) { 2706 igb_error(igb, 2707 "Not enough memory to alloc mcast table"); 2708 return (ENOMEM); 2709 } 2710 2711 if (igb->mcast_table != NULL) { 2712 bcopy(igb->mcast_table, new_table, old_len); 2713 kmem_free(igb->mcast_table, old_len); 2714 } 2715 igb->mcast_alloc_count += MCAST_ALLOC_COUNT; 2716 igb->mcast_table = new_table; 2717 } 2718 2719 bcopy(multiaddr, 2720 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2721 igb->mcast_count++; 2722 2723 /* 2724 * Update the multicast table in the hardware 2725 */ 2726 igb_setup_multicst(igb); 2727 2728 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2729 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2730 return (EIO); 2731 } 2732 2733 return (0); 2734 } 2735 2736 /* 2737 * igb_multicst_remove - Remove a multicst address 2738 */ 2739 int 2740 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2741 { 2742 struct ether_addr *new_table; 2743 size_t new_len; 2744 size_t old_len; 2745 int i; 2746 2747 ASSERT(mutex_owned(&igb->gen_lock)); 2748 2749 for (i = 0; i < igb->mcast_count; i++) { 2750 if (bcmp(multiaddr, &igb->mcast_table[i], 2751 ETHERADDRL) == 0) { 2752 for (i++; i < igb->mcast_count; i++) { 2753 igb->mcast_table[i - 1] = 2754 igb->mcast_table[i]; 2755 } 2756 igb->mcast_count--; 2757 break; 2758 } 2759 } 2760 2761 if ((igb->mcast_alloc_count - igb->mcast_count) > 2762 MCAST_ALLOC_COUNT) { 2763 old_len = igb->mcast_alloc_count * 2764 sizeof (struct ether_addr); 2765 new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) * 2766 sizeof (struct ether_addr); 2767 2768 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2769 if (new_table != NULL) { 2770 bcopy(igb->mcast_table, new_table, new_len); 2771 kmem_free(igb->mcast_table, old_len); 2772 igb->mcast_alloc_count -= MCAST_ALLOC_COUNT; 2773 igb->mcast_table = new_table; 2774 } 2775 } 2776 2777 /* 2778 * Update the multicast table in the hardware 2779 */ 2780 igb_setup_multicst(igb); 2781 2782 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2783 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2784 return (EIO); 2785 } 2786 2787 return (0); 2788 } 2789 2790 static void 2791 igb_release_multicast(igb_t *igb) 2792 { 2793 if (igb->mcast_table != NULL) { 2794 kmem_free(igb->mcast_table, 2795 igb->mcast_alloc_count * sizeof (struct ether_addr)); 2796 igb->mcast_table = NULL; 2797 } 2798 } 2799 2800 /* 2801 * igb_setup_multicast - setup multicast data structures 2802 * 2803 * This routine initializes all of the multicast related structures 2804 * and save them in the hardware registers. 2805 */ 2806 static void 2807 igb_setup_multicst(igb_t *igb) 2808 { 2809 uint8_t *mc_addr_list; 2810 uint32_t mc_addr_count; 2811 struct e1000_hw *hw = &igb->hw; 2812 2813 ASSERT(mutex_owned(&igb->gen_lock)); 2814 ASSERT(igb->mcast_count <= igb->mcast_max_num); 2815 2816 mc_addr_list = (uint8_t *)igb->mcast_table; 2817 mc_addr_count = igb->mcast_count; 2818 2819 /* 2820 * Update the multicase addresses to the MTA registers 2821 */ 2822 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count); 2823 } 2824 2825 /* 2826 * igb_get_conf - Get driver configurations set in driver.conf 2827 * 2828 * This routine gets user-configured values out of the configuration 2829 * file igb.conf. 2830 * 2831 * For each configurable value, there is a minimum, a maximum, and a 2832 * default. 2833 * If user does not configure a value, use the default. 2834 * If user configures below the minimum, use the minumum. 2835 * If user configures above the maximum, use the maxumum. 2836 */ 2837 static void 2838 igb_get_conf(igb_t *igb) 2839 { 2840 struct e1000_hw *hw = &igb->hw; 2841 uint32_t default_mtu; 2842 uint32_t flow_control; 2843 uint32_t ring_per_group; 2844 int i; 2845 2846 /* 2847 * igb driver supports the following user configurations: 2848 * 2849 * Link configurations: 2850 * adv_autoneg_cap 2851 * adv_1000fdx_cap 2852 * adv_100fdx_cap 2853 * adv_100hdx_cap 2854 * adv_10fdx_cap 2855 * adv_10hdx_cap 2856 * Note: 1000hdx is not supported. 2857 * 2858 * Jumbo frame configuration: 2859 * default_mtu 2860 * 2861 * Ethernet flow control configuration: 2862 * flow_control 2863 * 2864 * Multiple rings configurations: 2865 * tx_queue_number 2866 * tx_ring_size 2867 * rx_queue_number 2868 * rx_ring_size 2869 * 2870 * Call igb_get_prop() to get the value for a specific 2871 * configuration parameter. 2872 */ 2873 2874 /* 2875 * Link configurations 2876 */ 2877 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2878 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2879 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2880 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2881 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2882 PROP_ADV_100FDX_CAP, 0, 1, 1); 2883 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2884 PROP_ADV_100HDX_CAP, 0, 1, 1); 2885 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2886 PROP_ADV_10FDX_CAP, 0, 1, 1); 2887 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2888 PROP_ADV_10HDX_CAP, 0, 1, 1); 2889 2890 /* 2891 * Jumbo frame configurations 2892 */ 2893 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2894 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2895 2896 igb->max_frame_size = default_mtu + 2897 sizeof (struct ether_vlan_header) + ETHERFCSL; 2898 2899 /* 2900 * Ethernet flow control configuration 2901 */ 2902 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2903 e1000_fc_none, 4, e1000_fc_full); 2904 if (flow_control == 4) 2905 flow_control = e1000_fc_default; 2906 2907 hw->fc.requested_mode = flow_control; 2908 2909 /* 2910 * Multiple rings configurations 2911 */ 2912 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2913 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2914 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2915 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2916 2917 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0); 2918 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM, 2919 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM); 2920 /* 2921 * Currently we do not support VMDq for 82576 and 82580. 2922 * If it is e1000_82576, set num_rx_groups to 1. 2923 */ 2924 if (hw->mac.type >= e1000_82576) 2925 igb->num_rx_groups = 1; 2926 2927 if (igb->mr_enable) { 2928 igb->num_tx_rings = igb->capab->def_tx_que_num; 2929 igb->num_rx_rings = igb->capab->def_rx_que_num; 2930 } else { 2931 igb->num_tx_rings = 1; 2932 igb->num_rx_rings = 1; 2933 2934 if (igb->num_rx_groups > 1) { 2935 igb_error(igb, 2936 "Invalid rx groups number. Please enable multiple " 2937 "rings first"); 2938 igb->num_rx_groups = 1; 2939 } 2940 } 2941 2942 /* 2943 * Check the divisibility between rx rings and rx groups. 2944 */ 2945 for (i = igb->num_rx_groups; i > 0; i--) { 2946 if ((igb->num_rx_rings % i) == 0) 2947 break; 2948 } 2949 if (i != igb->num_rx_groups) { 2950 igb_error(igb, 2951 "Invalid rx groups number. Downgrade the rx group " 2952 "number to %d.", i); 2953 igb->num_rx_groups = i; 2954 } 2955 2956 /* 2957 * Get the ring number per group. 2958 */ 2959 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2960 2961 if (igb->num_rx_groups == 1) { 2962 /* 2963 * One rx ring group, the rx ring number is num_rx_rings. 2964 */ 2965 igb->vmdq_mode = E1000_VMDQ_OFF; 2966 } else if (ring_per_group == 1) { 2967 /* 2968 * Multiple rx groups, each group has one rx ring. 2969 */ 2970 igb->vmdq_mode = E1000_VMDQ_MAC; 2971 } else { 2972 /* 2973 * Multiple groups and multiple rings. 2974 */ 2975 igb->vmdq_mode = E1000_VMDQ_MAC_RSS; 2976 } 2977 2978 /* 2979 * Tunable used to force an interrupt type. The only use is 2980 * for testing of the lesser interrupt types. 2981 * 0 = don't force interrupt type 2982 * 1 = force interrupt type MSIX 2983 * 2 = force interrupt type MSI 2984 * 3 = force interrupt type Legacy 2985 */ 2986 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2987 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2988 2989 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2990 0, 1, 1); 2991 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2992 0, 1, 1); 2993 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2994 0, 1, 1); 2995 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2996 0, 1, 1); 2997 2998 /* 2999 * igb LSO needs the tx h/w checksum support. 3000 * Here LSO will be disabled if tx h/w checksum has been disabled. 3001 */ 3002 if (igb->tx_hcksum_enable == B_FALSE) 3003 igb->lso_enable = B_FALSE; 3004 3005 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 3006 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 3007 DEFAULT_TX_COPY_THRESHOLD); 3008 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 3009 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3010 DEFAULT_TX_RECYCLE_THRESHOLD); 3011 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 3012 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 3013 DEFAULT_TX_OVERLOAD_THRESHOLD); 3014 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 3015 MIN_TX_RESCHED_THRESHOLD, 3016 MIN(igb->tx_ring_size, MAX_TX_RESCHED_THRESHOLD), 3017 igb->tx_ring_size > DEFAULT_TX_RESCHED_THRESHOLD ? 3018 DEFAULT_TX_RESCHED_THRESHOLD : DEFAULT_TX_RESCHED_THRESHOLD_LOW); 3019 3020 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 3021 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 3022 DEFAULT_RX_COPY_THRESHOLD); 3023 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 3024 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 3025 DEFAULT_RX_LIMIT_PER_INTR); 3026 3027 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 3028 igb->capab->min_intr_throttle, 3029 igb->capab->max_intr_throttle, 3030 igb->capab->def_intr_throttle); 3031 3032 /* 3033 * Max number of multicast addresses 3034 */ 3035 igb->mcast_max_num = 3036 igb_get_prop(igb, PROP_MCAST_MAX_NUM, 3037 MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM); 3038 } 3039 3040 /* 3041 * igb_get_prop - Get a property value out of the configuration file igb.conf 3042 * 3043 * Caller provides the name of the property, a default value, a minimum 3044 * value, and a maximum value. 3045 * 3046 * Return configured value of the property, with default, minimum and 3047 * maximum properly applied. 3048 */ 3049 static int 3050 igb_get_prop(igb_t *igb, 3051 char *propname, /* name of the property */ 3052 int minval, /* minimum acceptable value */ 3053 int maxval, /* maximim acceptable value */ 3054 int defval) /* default value */ 3055 { 3056 int value; 3057 3058 /* 3059 * Call ddi_prop_get_int() to read the conf settings 3060 */ 3061 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 3062 DDI_PROP_DONTPASS, propname, defval); 3063 3064 if (value > maxval) 3065 value = maxval; 3066 3067 if (value < minval) 3068 value = minval; 3069 3070 return (value); 3071 } 3072 3073 /* 3074 * igb_setup_link - Using the link properties to setup the link 3075 */ 3076 int 3077 igb_setup_link(igb_t *igb, boolean_t setup_hw) 3078 { 3079 struct e1000_mac_info *mac; 3080 struct e1000_phy_info *phy; 3081 boolean_t invalid; 3082 3083 mac = &igb->hw.mac; 3084 phy = &igb->hw.phy; 3085 invalid = B_FALSE; 3086 3087 if (igb->param_adv_autoneg_cap == 1) { 3088 mac->autoneg = B_TRUE; 3089 phy->autoneg_advertised = 0; 3090 3091 /* 3092 * 1000hdx is not supported for autonegotiation 3093 */ 3094 if (igb->param_adv_1000fdx_cap == 1) 3095 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3096 3097 if (igb->param_adv_100fdx_cap == 1) 3098 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3099 3100 if (igb->param_adv_100hdx_cap == 1) 3101 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3102 3103 if (igb->param_adv_10fdx_cap == 1) 3104 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3105 3106 if (igb->param_adv_10hdx_cap == 1) 3107 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3108 3109 if (phy->autoneg_advertised == 0) 3110 invalid = B_TRUE; 3111 } else { 3112 mac->autoneg = B_FALSE; 3113 3114 /* 3115 * 1000fdx and 1000hdx are not supported for forced link 3116 */ 3117 if (igb->param_adv_100fdx_cap == 1) 3118 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3119 else if (igb->param_adv_100hdx_cap == 1) 3120 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3121 else if (igb->param_adv_10fdx_cap == 1) 3122 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3123 else if (igb->param_adv_10hdx_cap == 1) 3124 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3125 else 3126 invalid = B_TRUE; 3127 } 3128 3129 if (invalid) { 3130 igb_notice(igb, "Invalid link settings. Setup link to " 3131 "autonegotiation with full link capabilities."); 3132 mac->autoneg = B_TRUE; 3133 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3134 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3135 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3136 } 3137 3138 if (setup_hw) { 3139 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 3140 return (IGB_FAILURE); 3141 } 3142 3143 return (IGB_SUCCESS); 3144 } 3145 3146 3147 /* 3148 * igb_is_link_up - Check if the link is up 3149 */ 3150 static boolean_t 3151 igb_is_link_up(igb_t *igb) 3152 { 3153 struct e1000_hw *hw = &igb->hw; 3154 boolean_t link_up = B_FALSE; 3155 3156 ASSERT(mutex_owned(&igb->gen_lock)); 3157 3158 /* 3159 * get_link_status is set in the interrupt handler on link-status-change 3160 * or rx sequence error interrupt. get_link_status will stay 3161 * false until the e1000_check_for_link establishes link only 3162 * for copper adapters. 3163 */ 3164 switch (hw->phy.media_type) { 3165 case e1000_media_type_copper: 3166 if (hw->mac.get_link_status) { 3167 (void) e1000_check_for_link(hw); 3168 link_up = !hw->mac.get_link_status; 3169 } else { 3170 link_up = B_TRUE; 3171 } 3172 break; 3173 case e1000_media_type_fiber: 3174 (void) e1000_check_for_link(hw); 3175 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 3176 break; 3177 case e1000_media_type_internal_serdes: 3178 (void) e1000_check_for_link(hw); 3179 link_up = hw->mac.serdes_has_link; 3180 break; 3181 } 3182 3183 return (link_up); 3184 } 3185 3186 /* 3187 * igb_link_check - Link status processing 3188 */ 3189 static boolean_t 3190 igb_link_check(igb_t *igb) 3191 { 3192 struct e1000_hw *hw = &igb->hw; 3193 uint16_t speed = 0, duplex = 0; 3194 boolean_t link_changed = B_FALSE; 3195 3196 ASSERT(mutex_owned(&igb->gen_lock)); 3197 3198 if (igb_is_link_up(igb)) { 3199 /* 3200 * The Link is up, check whether it was marked as down earlier 3201 */ 3202 if (igb->link_state != LINK_STATE_UP) { 3203 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3204 igb->link_speed = speed; 3205 igb->link_duplex = duplex; 3206 igb->link_state = LINK_STATE_UP; 3207 link_changed = B_TRUE; 3208 if (!igb->link_complete) 3209 igb_stop_link_timer(igb); 3210 } 3211 } else if (igb->link_complete) { 3212 if (igb->link_state != LINK_STATE_DOWN) { 3213 igb->link_speed = 0; 3214 igb->link_duplex = 0; 3215 igb->link_state = LINK_STATE_DOWN; 3216 link_changed = B_TRUE; 3217 } 3218 } 3219 3220 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3221 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3222 return (B_FALSE); 3223 } 3224 3225 return (link_changed); 3226 } 3227 3228 /* 3229 * igb_local_timer - driver watchdog function 3230 * 3231 * This function will handle the hardware stall check, link status 3232 * check and other routines. 3233 */ 3234 static void 3235 igb_local_timer(void *arg) 3236 { 3237 igb_t *igb = (igb_t *)arg; 3238 boolean_t link_changed = B_FALSE; 3239 3240 if (igb->igb_state & IGB_ERROR) { 3241 igb->reset_count++; 3242 if (igb_reset(igb) == IGB_SUCCESS) 3243 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED); 3244 3245 igb_restart_watchdog_timer(igb); 3246 return; 3247 } 3248 3249 if (igb_stall_check(igb) || (igb->igb_state & IGB_STALL)) { 3250 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 3251 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 3252 igb->reset_count++; 3253 if (igb_reset(igb) == IGB_SUCCESS) 3254 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED); 3255 3256 igb_restart_watchdog_timer(igb); 3257 return; 3258 } 3259 3260 mutex_enter(&igb->gen_lock); 3261 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED)) 3262 link_changed = igb_link_check(igb); 3263 mutex_exit(&igb->gen_lock); 3264 3265 if (link_changed) 3266 mac_link_update(igb->mac_hdl, igb->link_state); 3267 3268 igb_restart_watchdog_timer(igb); 3269 } 3270 3271 /* 3272 * igb_link_timer - link setup timer function 3273 * 3274 * It is called when the timer for link setup is expired, which indicates 3275 * the completion of the link setup. The link state will not be updated 3276 * until the link setup is completed. And the link state will not be sent 3277 * to the upper layer through mac_link_update() in this function. It will 3278 * be updated in the local timer routine or the interrupts service routine 3279 * after the interface is started (plumbed). 3280 */ 3281 static void 3282 igb_link_timer(void *arg) 3283 { 3284 igb_t *igb = (igb_t *)arg; 3285 3286 mutex_enter(&igb->link_lock); 3287 igb->link_complete = B_TRUE; 3288 igb->link_tid = 0; 3289 mutex_exit(&igb->link_lock); 3290 } 3291 /* 3292 * igb_stall_check - check for transmit stall 3293 * 3294 * This function checks if the adapter is stalled (in transmit). 3295 * 3296 * It is called each time the watchdog timeout is invoked. 3297 * If the transmit descriptor reclaim continuously fails, 3298 * the watchdog value will increment by 1. If the watchdog 3299 * value exceeds the threshold, the igb is assumed to 3300 * have stalled and need to be reset. 3301 */ 3302 static boolean_t 3303 igb_stall_check(igb_t *igb) 3304 { 3305 igb_tx_ring_t *tx_ring; 3306 struct e1000_hw *hw = &igb->hw; 3307 boolean_t result; 3308 int i; 3309 3310 if (igb->link_state != LINK_STATE_UP) 3311 return (B_FALSE); 3312 3313 /* 3314 * If any tx ring is stalled, we'll reset the chipset 3315 */ 3316 result = B_FALSE; 3317 for (i = 0; i < igb->num_tx_rings; i++) { 3318 tx_ring = &igb->tx_rings[i]; 3319 3320 if (tx_ring->recycle_fail > 0) 3321 tx_ring->stall_watchdog++; 3322 else 3323 tx_ring->stall_watchdog = 0; 3324 3325 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 3326 result = B_TRUE; 3327 if (hw->mac.type == e1000_82580) { 3328 hw->dev_spec._82575.global_device_reset 3329 = B_TRUE; 3330 } 3331 break; 3332 } 3333 } 3334 3335 if (result) { 3336 tx_ring->stall_watchdog = 0; 3337 tx_ring->recycle_fail = 0; 3338 } 3339 3340 return (result); 3341 } 3342 3343 3344 /* 3345 * is_valid_mac_addr - Check if the mac address is valid 3346 */ 3347 static boolean_t 3348 is_valid_mac_addr(uint8_t *mac_addr) 3349 { 3350 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3351 const uint8_t addr_test2[6] = 3352 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3353 3354 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3355 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3356 return (B_FALSE); 3357 3358 return (B_TRUE); 3359 } 3360 3361 static boolean_t 3362 igb_find_mac_address(igb_t *igb) 3363 { 3364 struct e1000_hw *hw = &igb->hw; 3365 #ifdef __sparc 3366 uchar_t *bytes; 3367 struct ether_addr sysaddr; 3368 uint_t nelts; 3369 int err; 3370 boolean_t found = B_FALSE; 3371 3372 /* 3373 * The "vendor's factory-set address" may already have 3374 * been extracted from the chip, but if the property 3375 * "local-mac-address" is set we use that instead. 3376 * 3377 * We check whether it looks like an array of 6 3378 * bytes (which it should, if OBP set it). If we can't 3379 * make sense of it this way, we'll ignore it. 3380 */ 3381 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3382 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3383 if (err == DDI_PROP_SUCCESS) { 3384 if (nelts == ETHERADDRL) { 3385 while (nelts--) 3386 hw->mac.addr[nelts] = bytes[nelts]; 3387 found = B_TRUE; 3388 } 3389 ddi_prop_free(bytes); 3390 } 3391 3392 /* 3393 * Look up the OBP property "local-mac-address?". If the user has set 3394 * 'local-mac-address? = false', use "the system address" instead. 3395 */ 3396 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 3397 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3398 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3399 if (localetheraddr(NULL, &sysaddr) != 0) { 3400 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 3401 found = B_TRUE; 3402 } 3403 } 3404 ddi_prop_free(bytes); 3405 } 3406 3407 /* 3408 * Finally(!), if there's a valid "mac-address" property (created 3409 * if we netbooted from this interface), we must use this instead 3410 * of any of the above to ensure that the NFS/install server doesn't 3411 * get confused by the address changing as Solaris takes over! 3412 */ 3413 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3414 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3415 if (err == DDI_PROP_SUCCESS) { 3416 if (nelts == ETHERADDRL) { 3417 while (nelts--) 3418 hw->mac.addr[nelts] = bytes[nelts]; 3419 found = B_TRUE; 3420 } 3421 ddi_prop_free(bytes); 3422 } 3423 3424 if (found) { 3425 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 3426 return (B_TRUE); 3427 } 3428 #endif 3429 3430 /* 3431 * Read the device MAC address from the EEPROM 3432 */ 3433 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 3434 return (B_FALSE); 3435 3436 return (B_TRUE); 3437 } 3438 3439 #pragma inline(igb_arm_watchdog_timer) 3440 3441 static void 3442 igb_arm_watchdog_timer(igb_t *igb) 3443 { 3444 /* 3445 * Fire a watchdog timer 3446 */ 3447 igb->watchdog_tid = 3448 timeout(igb_local_timer, 3449 (void *)igb, 1 * drv_usectohz(1000000)); 3450 3451 } 3452 3453 /* 3454 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 3455 */ 3456 void 3457 igb_enable_watchdog_timer(igb_t *igb) 3458 { 3459 mutex_enter(&igb->watchdog_lock); 3460 3461 if (!igb->watchdog_enable) { 3462 igb->watchdog_enable = B_TRUE; 3463 igb->watchdog_start = B_TRUE; 3464 igb_arm_watchdog_timer(igb); 3465 } 3466 3467 mutex_exit(&igb->watchdog_lock); 3468 3469 } 3470 3471 /* 3472 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 3473 */ 3474 void 3475 igb_disable_watchdog_timer(igb_t *igb) 3476 { 3477 timeout_id_t tid; 3478 3479 mutex_enter(&igb->watchdog_lock); 3480 3481 igb->watchdog_enable = B_FALSE; 3482 igb->watchdog_start = B_FALSE; 3483 tid = igb->watchdog_tid; 3484 igb->watchdog_tid = 0; 3485 3486 mutex_exit(&igb->watchdog_lock); 3487 3488 if (tid != 0) 3489 (void) untimeout(tid); 3490 3491 } 3492 3493 /* 3494 * igb_start_watchdog_timer - Start the driver watchdog timer 3495 */ 3496 static void 3497 igb_start_watchdog_timer(igb_t *igb) 3498 { 3499 mutex_enter(&igb->watchdog_lock); 3500 3501 if (igb->watchdog_enable) { 3502 if (!igb->watchdog_start) { 3503 igb->watchdog_start = B_TRUE; 3504 igb_arm_watchdog_timer(igb); 3505 } 3506 } 3507 3508 mutex_exit(&igb->watchdog_lock); 3509 } 3510 3511 /* 3512 * igb_restart_watchdog_timer - Restart the driver watchdog timer 3513 */ 3514 static void 3515 igb_restart_watchdog_timer(igb_t *igb) 3516 { 3517 mutex_enter(&igb->watchdog_lock); 3518 3519 if (igb->watchdog_start) 3520 igb_arm_watchdog_timer(igb); 3521 3522 mutex_exit(&igb->watchdog_lock); 3523 } 3524 3525 /* 3526 * igb_stop_watchdog_timer - Stop the driver watchdog timer 3527 */ 3528 static void 3529 igb_stop_watchdog_timer(igb_t *igb) 3530 { 3531 timeout_id_t tid; 3532 3533 mutex_enter(&igb->watchdog_lock); 3534 3535 igb->watchdog_start = B_FALSE; 3536 tid = igb->watchdog_tid; 3537 igb->watchdog_tid = 0; 3538 3539 mutex_exit(&igb->watchdog_lock); 3540 3541 if (tid != 0) 3542 (void) untimeout(tid); 3543 } 3544 3545 /* 3546 * igb_start_link_timer - Start the link setup timer 3547 */ 3548 static void 3549 igb_start_link_timer(struct igb *igb) 3550 { 3551 struct e1000_hw *hw = &igb->hw; 3552 clock_t link_timeout; 3553 3554 if (hw->mac.autoneg) 3555 link_timeout = PHY_AUTO_NEG_LIMIT * 3556 drv_usectohz(100000); 3557 else 3558 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 3559 3560 mutex_enter(&igb->link_lock); 3561 if (hw->phy.autoneg_wait_to_complete) { 3562 igb->link_complete = B_TRUE; 3563 } else { 3564 igb->link_complete = B_FALSE; 3565 igb->link_tid = timeout(igb_link_timer, (void *)igb, 3566 link_timeout); 3567 } 3568 mutex_exit(&igb->link_lock); 3569 } 3570 3571 /* 3572 * igb_stop_link_timer - Stop the link setup timer 3573 */ 3574 static void 3575 igb_stop_link_timer(struct igb *igb) 3576 { 3577 timeout_id_t tid; 3578 3579 mutex_enter(&igb->link_lock); 3580 igb->link_complete = B_TRUE; 3581 tid = igb->link_tid; 3582 igb->link_tid = 0; 3583 mutex_exit(&igb->link_lock); 3584 3585 if (tid != 0) 3586 (void) untimeout(tid); 3587 } 3588 3589 /* 3590 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 3591 */ 3592 static void 3593 igb_disable_adapter_interrupts(igb_t *igb) 3594 { 3595 struct e1000_hw *hw = &igb->hw; 3596 3597 /* 3598 * Set the IMC register to mask all the interrupts, 3599 * including the tx interrupts. 3600 */ 3601 E1000_WRITE_REG(hw, E1000_IMC, ~0); 3602 E1000_WRITE_REG(hw, E1000_IAM, 0); 3603 3604 /* 3605 * Additional disabling for MSI-X 3606 */ 3607 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3608 E1000_WRITE_REG(hw, E1000_EIMC, ~0); 3609 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3610 E1000_WRITE_REG(hw, E1000_EIAM, 0); 3611 } 3612 3613 E1000_WRITE_FLUSH(hw); 3614 } 3615 3616 /* 3617 * igb_enable_adapter_interrupts_82580 - Enable NIC interrupts for 82580 3618 */ 3619 static void 3620 igb_enable_adapter_interrupts_82580(igb_t *igb) 3621 { 3622 struct e1000_hw *hw = &igb->hw; 3623 3624 /* Clear any pending interrupts */ 3625 (void) E1000_READ_REG(hw, E1000_ICR); 3626 igb->ims_mask |= E1000_IMS_DRSTA; 3627 3628 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3629 3630 /* Interrupt enabling for MSI-X */ 3631 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3632 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3633 igb->ims_mask = (E1000_IMS_LSC | E1000_IMS_DRSTA); 3634 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask); 3635 } else { /* Interrupt enabling for MSI and legacy */ 3636 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3637 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3638 igb->ims_mask |= E1000_IMS_DRSTA; 3639 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask); 3640 } 3641 3642 /* Disable auto-mask for ICR interrupt bits */ 3643 E1000_WRITE_REG(hw, E1000_IAM, 0); 3644 3645 E1000_WRITE_FLUSH(hw); 3646 } 3647 3648 /* 3649 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576 3650 */ 3651 static void 3652 igb_enable_adapter_interrupts_82576(igb_t *igb) 3653 { 3654 struct e1000_hw *hw = &igb->hw; 3655 3656 /* Clear any pending interrupts */ 3657 (void) E1000_READ_REG(hw, E1000_ICR); 3658 3659 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3660 3661 /* Interrupt enabling for MSI-X */ 3662 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3663 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3664 igb->ims_mask = E1000_IMS_LSC; 3665 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3666 } else { 3667 /* Interrupt enabling for MSI and legacy */ 3668 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3669 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3670 E1000_WRITE_REG(hw, E1000_IMS, 3671 (IMS_ENABLE_MASK | E1000_IMS_TXQE)); 3672 } 3673 3674 /* Disable auto-mask for ICR interrupt bits */ 3675 E1000_WRITE_REG(hw, E1000_IAM, 0); 3676 3677 E1000_WRITE_FLUSH(hw); 3678 } 3679 3680 /* 3681 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575 3682 */ 3683 static void 3684 igb_enable_adapter_interrupts_82575(igb_t *igb) 3685 { 3686 struct e1000_hw *hw = &igb->hw; 3687 uint32_t reg; 3688 3689 /* Clear any pending interrupts */ 3690 (void) E1000_READ_REG(hw, E1000_ICR); 3691 3692 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3693 /* Interrupt enabling for MSI-X */ 3694 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3695 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3696 igb->ims_mask = E1000_IMS_LSC; 3697 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3698 3699 /* Enable MSI-X PBA support */ 3700 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3701 reg |= E1000_CTRL_EXT_PBA_CLR; 3702 3703 /* Non-selective interrupt clear-on-read */ 3704 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 3705 3706 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3707 } else { 3708 /* Interrupt enabling for MSI and legacy */ 3709 igb->ims_mask = IMS_ENABLE_MASK; 3710 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3711 } 3712 3713 E1000_WRITE_FLUSH(hw); 3714 } 3715 3716 /* 3717 * Loopback Support 3718 */ 3719 static lb_property_t lb_normal = 3720 { normal, "normal", IGB_LB_NONE }; 3721 static lb_property_t lb_external = 3722 { external, "External", IGB_LB_EXTERNAL }; 3723 static lb_property_t lb_phy = 3724 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 3725 static lb_property_t lb_serdes = 3726 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 3727 3728 enum ioc_reply 3729 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 3730 { 3731 lb_info_sz_t *lbsp; 3732 lb_property_t *lbpp; 3733 struct e1000_hw *hw; 3734 uint32_t *lbmp; 3735 uint32_t size; 3736 uint32_t value; 3737 3738 hw = &igb->hw; 3739 3740 if (mp->b_cont == NULL) 3741 return (IOC_INVAL); 3742 3743 switch (iocp->ioc_cmd) { 3744 default: 3745 return (IOC_INVAL); 3746 3747 case LB_GET_INFO_SIZE: 3748 size = sizeof (lb_info_sz_t); 3749 if (iocp->ioc_count != size) 3750 return (IOC_INVAL); 3751 3752 value = sizeof (lb_normal); 3753 if (hw->phy.media_type == e1000_media_type_copper) 3754 value += sizeof (lb_phy); 3755 else 3756 value += sizeof (lb_serdes); 3757 value += sizeof (lb_external); 3758 3759 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 3760 *lbsp = value; 3761 break; 3762 3763 case LB_GET_INFO: 3764 value = sizeof (lb_normal); 3765 if (hw->phy.media_type == e1000_media_type_copper) 3766 value += sizeof (lb_phy); 3767 else 3768 value += sizeof (lb_serdes); 3769 value += sizeof (lb_external); 3770 3771 size = value; 3772 if (iocp->ioc_count != size) 3773 return (IOC_INVAL); 3774 3775 value = 0; 3776 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 3777 3778 lbpp[value++] = lb_normal; 3779 if (hw->phy.media_type == e1000_media_type_copper) 3780 lbpp[value++] = lb_phy; 3781 else 3782 lbpp[value++] = lb_serdes; 3783 lbpp[value++] = lb_external; 3784 break; 3785 3786 case LB_GET_MODE: 3787 size = sizeof (uint32_t); 3788 if (iocp->ioc_count != size) 3789 return (IOC_INVAL); 3790 3791 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3792 *lbmp = igb->loopback_mode; 3793 break; 3794 3795 case LB_SET_MODE: 3796 size = 0; 3797 if (iocp->ioc_count != sizeof (uint32_t)) 3798 return (IOC_INVAL); 3799 3800 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3801 if (!igb_set_loopback_mode(igb, *lbmp)) 3802 return (IOC_INVAL); 3803 break; 3804 } 3805 3806 iocp->ioc_count = size; 3807 iocp->ioc_error = 0; 3808 3809 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3810 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3811 return (IOC_INVAL); 3812 } 3813 3814 return (IOC_REPLY); 3815 } 3816 3817 /* 3818 * igb_set_loopback_mode - Setup loopback based on the loopback mode 3819 */ 3820 static boolean_t 3821 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 3822 { 3823 struct e1000_hw *hw; 3824 int i; 3825 3826 if (mode == igb->loopback_mode) 3827 return (B_TRUE); 3828 3829 hw = &igb->hw; 3830 3831 igb->loopback_mode = mode; 3832 3833 if (mode == IGB_LB_NONE) { 3834 /* Reset the chip */ 3835 hw->phy.autoneg_wait_to_complete = B_TRUE; 3836 (void) igb_reset(igb); 3837 hw->phy.autoneg_wait_to_complete = B_FALSE; 3838 return (B_TRUE); 3839 } 3840 3841 mutex_enter(&igb->gen_lock); 3842 3843 switch (mode) { 3844 default: 3845 mutex_exit(&igb->gen_lock); 3846 return (B_FALSE); 3847 3848 case IGB_LB_EXTERNAL: 3849 igb_set_external_loopback(igb); 3850 break; 3851 3852 case IGB_LB_INTERNAL_PHY: 3853 igb_set_internal_phy_loopback(igb); 3854 break; 3855 3856 case IGB_LB_INTERNAL_SERDES: 3857 igb_set_internal_serdes_loopback(igb); 3858 break; 3859 } 3860 3861 mutex_exit(&igb->gen_lock); 3862 3863 /* 3864 * When external loopback is set, wait up to 1000ms to get the link up. 3865 * According to test, 1000ms can work and it's an experimental value. 3866 */ 3867 if (mode == IGB_LB_EXTERNAL) { 3868 for (i = 0; i <= 10; i++) { 3869 mutex_enter(&igb->gen_lock); 3870 (void) igb_link_check(igb); 3871 mutex_exit(&igb->gen_lock); 3872 3873 if (igb->link_state == LINK_STATE_UP) 3874 break; 3875 3876 msec_delay(100); 3877 } 3878 3879 if (igb->link_state != LINK_STATE_UP) { 3880 /* 3881 * Does not support external loopback. 3882 * Reset driver to loopback none. 3883 */ 3884 igb->loopback_mode = IGB_LB_NONE; 3885 3886 /* Reset the chip */ 3887 hw->phy.autoneg_wait_to_complete = B_TRUE; 3888 (void) igb_reset(igb); 3889 hw->phy.autoneg_wait_to_complete = B_FALSE; 3890 3891 IGB_DEBUGLOG_0(igb, "Set external loopback failed, " 3892 "reset to loopback none."); 3893 3894 return (B_FALSE); 3895 } 3896 } 3897 3898 return (B_TRUE); 3899 } 3900 3901 /* 3902 * igb_set_external_loopback - Set the external loopback mode 3903 */ 3904 static void 3905 igb_set_external_loopback(igb_t *igb) 3906 { 3907 struct e1000_hw *hw; 3908 uint32_t ctrl_ext; 3909 3910 hw = &igb->hw; 3911 3912 /* Set link mode to PHY (00b) in the Extended Control register */ 3913 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3914 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3915 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3916 3917 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3918 (void) e1000_write_phy_reg(hw, 0x9, 0x1a00); 3919 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3920 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3921 } 3922 3923 /* 3924 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3925 */ 3926 static void 3927 igb_set_internal_phy_loopback(igb_t *igb) 3928 { 3929 struct e1000_hw *hw; 3930 uint32_t ctrl_ext; 3931 uint16_t phy_ctrl; 3932 uint16_t phy_pconf; 3933 3934 hw = &igb->hw; 3935 3936 /* Set link mode to PHY (00b) in the Extended Control register */ 3937 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3938 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3939 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3940 3941 /* 3942 * Set PHY control register (0x4140): 3943 * Set full duplex mode 3944 * Set loopback bit 3945 * Clear auto-neg enable bit 3946 * Set PHY speed 3947 */ 3948 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3949 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3950 3951 /* Set the link disable bit in the Port Configuration register */ 3952 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3953 phy_pconf |= (uint16_t)1 << 14; 3954 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3955 } 3956 3957 /* 3958 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3959 */ 3960 static void 3961 igb_set_internal_serdes_loopback(igb_t *igb) 3962 { 3963 struct e1000_hw *hw; 3964 uint32_t ctrl_ext; 3965 uint32_t ctrl; 3966 uint32_t pcs_lctl; 3967 uint32_t connsw; 3968 3969 hw = &igb->hw; 3970 3971 /* Set link mode to SerDes (11b) in the Extended Control register */ 3972 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3973 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3974 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3975 3976 /* Configure the SerDes to loopback */ 3977 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3978 3979 /* Set Device Control register */ 3980 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3981 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3982 E1000_CTRL_SLU); /* Force link up */ 3983 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3984 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3985 E1000_CTRL_LRST); /* Clear link reset */ 3986 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3987 3988 /* Set PCS Link Control register */ 3989 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3990 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3991 E1000_PCS_LCTL_FSD | 3992 E1000_PCS_LCTL_FDV_FULL | 3993 E1000_PCS_LCTL_FLV_LINK_UP); 3994 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3995 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3996 3997 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3998 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3999 connsw &= ~E1000_CONNSW_ENRGSRC; 4000 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 4001 } 4002 4003 #pragma inline(igb_intr_rx_work) 4004 /* 4005 * igb_intr_rx_work - rx processing of ISR 4006 */ 4007 static void 4008 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 4009 { 4010 mblk_t *mp; 4011 4012 mutex_enter(&rx_ring->rx_lock); 4013 mp = igb_rx(rx_ring, IGB_NO_POLL); 4014 mutex_exit(&rx_ring->rx_lock); 4015 4016 if (mp != NULL) 4017 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp, 4018 rx_ring->ring_gen_num); 4019 } 4020 4021 #pragma inline(igb_intr_tx_work) 4022 /* 4023 * igb_intr_tx_work - tx processing of ISR 4024 */ 4025 static void 4026 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 4027 { 4028 igb_t *igb = tx_ring->igb; 4029 4030 /* Recycle the tx descriptors */ 4031 tx_ring->tx_recycle(tx_ring); 4032 4033 /* Schedule the re-transmit */ 4034 if (tx_ring->reschedule && 4035 (tx_ring->tbd_free >= igb->tx_resched_thresh)) { 4036 tx_ring->reschedule = B_FALSE; 4037 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle); 4038 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 4039 } 4040 } 4041 4042 #pragma inline(igb_intr_link_work) 4043 /* 4044 * igb_intr_link_work - link-status-change processing of ISR 4045 */ 4046 static void 4047 igb_intr_link_work(igb_t *igb) 4048 { 4049 boolean_t link_changed; 4050 4051 igb_stop_watchdog_timer(igb); 4052 4053 mutex_enter(&igb->gen_lock); 4054 4055 /* 4056 * Because we got a link-status-change interrupt, force 4057 * e1000_check_for_link() to look at phy 4058 */ 4059 igb->hw.mac.get_link_status = B_TRUE; 4060 4061 /* igb_link_check takes care of link status change */ 4062 link_changed = igb_link_check(igb); 4063 4064 /* Get new phy state */ 4065 igb_get_phy_state(igb); 4066 4067 mutex_exit(&igb->gen_lock); 4068 4069 if (link_changed) 4070 mac_link_update(igb->mac_hdl, igb->link_state); 4071 4072 igb_start_watchdog_timer(igb); 4073 } 4074 4075 /* 4076 * igb_intr_legacy - Interrupt handler for legacy interrupts 4077 */ 4078 static uint_t 4079 igb_intr_legacy(void *arg1, void *arg2) 4080 { 4081 igb_t *igb = (igb_t *)arg1; 4082 igb_tx_ring_t *tx_ring; 4083 uint32_t icr; 4084 mblk_t *mp; 4085 boolean_t tx_reschedule; 4086 boolean_t link_changed; 4087 uint_t result; 4088 4089 _NOTE(ARGUNUSED(arg2)); 4090 4091 mutex_enter(&igb->gen_lock); 4092 4093 if (igb->igb_state & IGB_SUSPENDED) { 4094 mutex_exit(&igb->gen_lock); 4095 return (DDI_INTR_UNCLAIMED); 4096 } 4097 4098 mp = NULL; 4099 tx_reschedule = B_FALSE; 4100 link_changed = B_FALSE; 4101 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4102 4103 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4104 mutex_exit(&igb->gen_lock); 4105 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4106 atomic_or_32(&igb->igb_state, IGB_ERROR); 4107 return (DDI_INTR_UNCLAIMED); 4108 } 4109 4110 if (icr & E1000_ICR_INT_ASSERTED) { 4111 /* 4112 * E1000_ICR_INT_ASSERTED bit was set: 4113 * Read(Clear) the ICR, claim this interrupt, 4114 * look for work to do. 4115 */ 4116 ASSERT(igb->num_rx_rings == 1); 4117 ASSERT(igb->num_tx_rings == 1); 4118 4119 /* Make sure all interrupt causes cleared */ 4120 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 4121 4122 if (icr & E1000_ICR_RXT0) { 4123 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL); 4124 } 4125 4126 if (icr & E1000_ICR_TXDW) { 4127 tx_ring = &igb->tx_rings[0]; 4128 4129 /* Recycle the tx descriptors */ 4130 tx_ring->tx_recycle(tx_ring); 4131 4132 /* Schedule the re-transmit */ 4133 tx_reschedule = (tx_ring->reschedule && 4134 (tx_ring->tbd_free >= igb->tx_resched_thresh)); 4135 } 4136 4137 if (icr & E1000_ICR_LSC) { 4138 /* 4139 * Because we got a link-status-change interrupt, force 4140 * e1000_check_for_link() to look at phy 4141 */ 4142 igb->hw.mac.get_link_status = B_TRUE; 4143 4144 /* igb_link_check takes care of link status change */ 4145 link_changed = igb_link_check(igb); 4146 4147 /* Get new phy state */ 4148 igb_get_phy_state(igb); 4149 } 4150 4151 if (icr & E1000_ICR_DRSTA) { 4152 /* 82580 Full Device Reset needed */ 4153 atomic_or_32(&igb->igb_state, IGB_STALL); 4154 } 4155 4156 result = DDI_INTR_CLAIMED; 4157 } else { 4158 /* 4159 * E1000_ICR_INT_ASSERTED bit was not set: 4160 * Don't claim this interrupt. 4161 */ 4162 result = DDI_INTR_UNCLAIMED; 4163 } 4164 4165 mutex_exit(&igb->gen_lock); 4166 4167 /* 4168 * Do the following work outside of the gen_lock 4169 */ 4170 if (mp != NULL) 4171 mac_rx(igb->mac_hdl, NULL, mp); 4172 4173 if (tx_reschedule) { 4174 tx_ring->reschedule = B_FALSE; 4175 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle); 4176 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 4177 } 4178 4179 if (link_changed) 4180 mac_link_update(igb->mac_hdl, igb->link_state); 4181 4182 return (result); 4183 } 4184 4185 /* 4186 * igb_intr_msi - Interrupt handler for MSI 4187 */ 4188 static uint_t 4189 igb_intr_msi(void *arg1, void *arg2) 4190 { 4191 igb_t *igb = (igb_t *)arg1; 4192 uint32_t icr; 4193 4194 _NOTE(ARGUNUSED(arg2)); 4195 4196 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4197 4198 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4199 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4200 atomic_or_32(&igb->igb_state, IGB_ERROR); 4201 return (DDI_INTR_CLAIMED); 4202 } 4203 4204 /* Make sure all interrupt causes cleared */ 4205 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 4206 4207 /* 4208 * For MSI interrupt, we have only one vector, 4209 * so we have only one rx ring and one tx ring enabled. 4210 */ 4211 ASSERT(igb->num_rx_rings == 1); 4212 ASSERT(igb->num_tx_rings == 1); 4213 4214 if (icr & E1000_ICR_RXT0) { 4215 igb_intr_rx_work(&igb->rx_rings[0]); 4216 } 4217 4218 if (icr & E1000_ICR_TXDW) { 4219 igb_intr_tx_work(&igb->tx_rings[0]); 4220 } 4221 4222 if (icr & E1000_ICR_LSC) { 4223 igb_intr_link_work(igb); 4224 } 4225 4226 if (icr & E1000_ICR_DRSTA) { 4227 /* 82580 Full Device Reset needed */ 4228 atomic_or_32(&igb->igb_state, IGB_STALL); 4229 } 4230 4231 return (DDI_INTR_CLAIMED); 4232 } 4233 4234 /* 4235 * igb_intr_rx - Interrupt handler for rx 4236 */ 4237 static uint_t 4238 igb_intr_rx(void *arg1, void *arg2) 4239 { 4240 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 4241 4242 _NOTE(ARGUNUSED(arg2)); 4243 4244 /* 4245 * Only used via MSI-X vector so don't check cause bits 4246 * and only clean the given ring. 4247 */ 4248 igb_intr_rx_work(rx_ring); 4249 4250 return (DDI_INTR_CLAIMED); 4251 } 4252 4253 /* 4254 * igb_intr_tx - Interrupt handler for tx 4255 */ 4256 static uint_t 4257 igb_intr_tx(void *arg1, void *arg2) 4258 { 4259 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1; 4260 4261 _NOTE(ARGUNUSED(arg2)); 4262 4263 /* 4264 * Only used via MSI-X vector so don't check cause bits 4265 * and only clean the given ring. 4266 */ 4267 igb_intr_tx_work(tx_ring); 4268 4269 return (DDI_INTR_CLAIMED); 4270 } 4271 4272 /* 4273 * igb_intr_tx_other - Interrupt handler for both tx and other 4274 * 4275 */ 4276 static uint_t 4277 igb_intr_tx_other(void *arg1, void *arg2) 4278 { 4279 igb_t *igb = (igb_t *)arg1; 4280 uint32_t icr; 4281 4282 _NOTE(ARGUNUSED(arg2)); 4283 4284 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4285 4286 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4287 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4288 atomic_or_32(&igb->igb_state, IGB_ERROR); 4289 return (DDI_INTR_CLAIMED); 4290 } 4291 4292 /* 4293 * Look for tx reclaiming work first. Remember, in the 4294 * case of only interrupt sharing, only one tx ring is 4295 * used 4296 */ 4297 igb_intr_tx_work(&igb->tx_rings[0]); 4298 4299 /* 4300 * Check for "other" causes. 4301 */ 4302 if (icr & E1000_ICR_LSC) { 4303 igb_intr_link_work(igb); 4304 } 4305 4306 /* 4307 * The DOUTSYNC bit indicates a tx packet dropped because 4308 * DMA engine gets "out of sync". There isn't a real fix 4309 * for this. The Intel recommendation is to count the number 4310 * of occurrences so user can detect when it is happening. 4311 * The issue is non-fatal and there's no recovery action 4312 * available. 4313 */ 4314 if (icr & E1000_ICR_DOUTSYNC) { 4315 IGB_STAT(igb->dout_sync); 4316 } 4317 4318 if (icr & E1000_ICR_DRSTA) { 4319 /* 82580 Full Device Reset needed */ 4320 atomic_or_32(&igb->igb_state, IGB_STALL); 4321 } 4322 4323 return (DDI_INTR_CLAIMED); 4324 } 4325 4326 /* 4327 * igb_alloc_intrs - Allocate interrupts for the driver 4328 * 4329 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 4330 * if not successful, try Legacy. 4331 * igb->intr_force can be used to force sequence to start with 4332 * any of the 3 types. 4333 * If MSI-X is not used, number of tx/rx rings is forced to 1. 4334 */ 4335 static int 4336 igb_alloc_intrs(igb_t *igb) 4337 { 4338 dev_info_t *devinfo; 4339 int intr_types; 4340 int rc; 4341 4342 devinfo = igb->dip; 4343 4344 /* Get supported interrupt types */ 4345 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4346 4347 if (rc != DDI_SUCCESS) { 4348 igb_log(igb, 4349 "Get supported interrupt types failed: %d", rc); 4350 return (IGB_FAILURE); 4351 } 4352 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 4353 4354 igb->intr_type = 0; 4355 4356 /* Install MSI-X interrupts */ 4357 if ((intr_types & DDI_INTR_TYPE_MSIX) && 4358 (igb->intr_force <= IGB_INTR_MSIX)) { 4359 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 4360 4361 if (rc == IGB_SUCCESS) 4362 return (IGB_SUCCESS); 4363 4364 igb_log(igb, 4365 "Allocate MSI-X failed, trying MSI interrupts..."); 4366 } 4367 4368 /* MSI-X not used, force rings to 1 */ 4369 igb->num_rx_rings = 1; 4370 igb->num_tx_rings = 1; 4371 igb_log(igb, 4372 "MSI-X not used, force rx and tx queue number to 1"); 4373 4374 /* Install MSI interrupts */ 4375 if ((intr_types & DDI_INTR_TYPE_MSI) && 4376 (igb->intr_force <= IGB_INTR_MSI)) { 4377 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 4378 4379 if (rc == IGB_SUCCESS) 4380 return (IGB_SUCCESS); 4381 4382 igb_log(igb, 4383 "Allocate MSI failed, trying Legacy interrupts..."); 4384 } 4385 4386 /* Install legacy interrupts */ 4387 if (intr_types & DDI_INTR_TYPE_FIXED) { 4388 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 4389 4390 if (rc == IGB_SUCCESS) 4391 return (IGB_SUCCESS); 4392 4393 igb_log(igb, 4394 "Allocate Legacy interrupts failed"); 4395 } 4396 4397 /* If none of the 3 types succeeded, return failure */ 4398 return (IGB_FAILURE); 4399 } 4400 4401 /* 4402 * igb_alloc_intr_handles - Allocate interrupt handles. 4403 * 4404 * For legacy and MSI, only 1 handle is needed. For MSI-X, 4405 * if fewer than 2 handles are available, return failure. 4406 * Upon success, this sets the number of Rx rings to a number that 4407 * matches the handles available for Rx interrupts. 4408 */ 4409 static int 4410 igb_alloc_intr_handles(igb_t *igb, int intr_type) 4411 { 4412 dev_info_t *devinfo; 4413 int orig, request, count, avail, actual; 4414 int diff, minimum; 4415 int rc; 4416 4417 devinfo = igb->dip; 4418 4419 switch (intr_type) { 4420 case DDI_INTR_TYPE_FIXED: 4421 request = 1; /* Request 1 legacy interrupt handle */ 4422 minimum = 1; 4423 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 4424 break; 4425 4426 case DDI_INTR_TYPE_MSI: 4427 request = 1; /* Request 1 MSI interrupt handle */ 4428 minimum = 1; 4429 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 4430 break; 4431 4432 case DDI_INTR_TYPE_MSIX: 4433 /* 4434 * Number of vectors for the adapter is 4435 * # rx rings + # tx rings 4436 * One of tx vectors is for tx & other 4437 */ 4438 request = igb->num_rx_rings + igb->num_tx_rings; 4439 orig = request; 4440 minimum = 2; 4441 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 4442 break; 4443 4444 default: 4445 igb_log(igb, 4446 "invalid call to igb_alloc_intr_handles(): %d\n", 4447 intr_type); 4448 return (IGB_FAILURE); 4449 } 4450 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 4451 request, minimum); 4452 4453 /* 4454 * Get number of supported interrupts 4455 */ 4456 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4457 if ((rc != DDI_SUCCESS) || (count < minimum)) { 4458 igb_log(igb, 4459 "Get supported interrupt number failed. " 4460 "Return: %d, count: %d", rc, count); 4461 return (IGB_FAILURE); 4462 } 4463 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 4464 4465 /* 4466 * Get number of available interrupts 4467 */ 4468 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4469 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 4470 igb_log(igb, 4471 "Get available interrupt number failed. " 4472 "Return: %d, available: %d", rc, avail); 4473 return (IGB_FAILURE); 4474 } 4475 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 4476 4477 if (avail < request) { 4478 igb_log(igb, "Request %d handles, %d available", 4479 request, avail); 4480 request = avail; 4481 } 4482 4483 actual = 0; 4484 igb->intr_cnt = 0; 4485 4486 /* 4487 * Allocate an array of interrupt handles 4488 */ 4489 igb->intr_size = request * sizeof (ddi_intr_handle_t); 4490 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 4491 4492 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 4493 request, &actual, DDI_INTR_ALLOC_NORMAL); 4494 if (rc != DDI_SUCCESS) { 4495 igb_log(igb, "Allocate interrupts failed. " 4496 "return: %d, request: %d, actual: %d", 4497 rc, request, actual); 4498 goto alloc_handle_fail; 4499 } 4500 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 4501 4502 igb->intr_cnt = actual; 4503 4504 if (actual < minimum) { 4505 igb_log(igb, "Insufficient interrupt handles allocated: %d", 4506 actual); 4507 goto alloc_handle_fail; 4508 } 4509 4510 /* 4511 * For MSI-X, actual might force us to reduce number of tx & rx rings 4512 */ 4513 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) { 4514 diff = orig - actual; 4515 if (diff < igb->num_tx_rings) { 4516 igb_log(igb, 4517 "MSI-X vectors force Tx queue number to %d", 4518 igb->num_tx_rings - diff); 4519 igb->num_tx_rings -= diff; 4520 } else { 4521 igb_log(igb, 4522 "MSI-X vectors force Tx queue number to 1"); 4523 igb->num_tx_rings = 1; 4524 4525 igb_log(igb, 4526 "MSI-X vectors force Rx queue number to %d", 4527 actual - 1); 4528 igb->num_rx_rings = actual - 1; 4529 } 4530 } 4531 4532 /* 4533 * Get priority for first vector, assume remaining are all the same 4534 */ 4535 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 4536 if (rc != DDI_SUCCESS) { 4537 igb_log(igb, 4538 "Get interrupt priority failed: %d", rc); 4539 goto alloc_handle_fail; 4540 } 4541 4542 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 4543 if (rc != DDI_SUCCESS) { 4544 igb_log(igb, 4545 "Get interrupt cap failed: %d", rc); 4546 goto alloc_handle_fail; 4547 } 4548 4549 igb->intr_type = intr_type; 4550 4551 return (IGB_SUCCESS); 4552 4553 alloc_handle_fail: 4554 igb_rem_intrs(igb); 4555 4556 return (IGB_FAILURE); 4557 } 4558 4559 /* 4560 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 4561 * 4562 * Before adding the interrupt handlers, the interrupt vectors have 4563 * been allocated, and the rx/tx rings have also been allocated. 4564 */ 4565 static int 4566 igb_add_intr_handlers(igb_t *igb) 4567 { 4568 igb_rx_ring_t *rx_ring; 4569 igb_tx_ring_t *tx_ring; 4570 int vector; 4571 int rc; 4572 int i; 4573 4574 vector = 0; 4575 4576 switch (igb->intr_type) { 4577 case DDI_INTR_TYPE_MSIX: 4578 /* Add interrupt handler for tx + other */ 4579 tx_ring = &igb->tx_rings[0]; 4580 rc = ddi_intr_add_handler(igb->htable[vector], 4581 (ddi_intr_handler_t *)igb_intr_tx_other, 4582 (void *)igb, NULL); 4583 4584 if (rc != DDI_SUCCESS) { 4585 igb_log(igb, 4586 "Add tx/other interrupt handler failed: %d", rc); 4587 return (IGB_FAILURE); 4588 } 4589 tx_ring->intr_vector = vector; 4590 vector++; 4591 4592 /* Add interrupt handler for each rx ring */ 4593 for (i = 0; i < igb->num_rx_rings; i++) { 4594 rx_ring = &igb->rx_rings[i]; 4595 4596 rc = ddi_intr_add_handler(igb->htable[vector], 4597 (ddi_intr_handler_t *)igb_intr_rx, 4598 (void *)rx_ring, NULL); 4599 4600 if (rc != DDI_SUCCESS) { 4601 igb_log(igb, 4602 "Add rx interrupt handler failed. " 4603 "return: %d, rx ring: %d", rc, i); 4604 for (vector--; vector >= 0; vector--) { 4605 (void) ddi_intr_remove_handler( 4606 igb->htable[vector]); 4607 } 4608 return (IGB_FAILURE); 4609 } 4610 4611 rx_ring->intr_vector = vector; 4612 4613 vector++; 4614 } 4615 4616 /* Add interrupt handler for each tx ring from 2nd ring */ 4617 for (i = 1; i < igb->num_tx_rings; i++) { 4618 tx_ring = &igb->tx_rings[i]; 4619 4620 rc = ddi_intr_add_handler(igb->htable[vector], 4621 (ddi_intr_handler_t *)igb_intr_tx, 4622 (void *)tx_ring, NULL); 4623 4624 if (rc != DDI_SUCCESS) { 4625 igb_log(igb, 4626 "Add tx interrupt handler failed. " 4627 "return: %d, tx ring: %d", rc, i); 4628 for (vector--; vector >= 0; vector--) { 4629 (void) ddi_intr_remove_handler( 4630 igb->htable[vector]); 4631 } 4632 return (IGB_FAILURE); 4633 } 4634 4635 tx_ring->intr_vector = vector; 4636 4637 vector++; 4638 } 4639 4640 break; 4641 4642 case DDI_INTR_TYPE_MSI: 4643 /* Add interrupt handlers for the only vector */ 4644 rc = ddi_intr_add_handler(igb->htable[vector], 4645 (ddi_intr_handler_t *)igb_intr_msi, 4646 (void *)igb, NULL); 4647 4648 if (rc != DDI_SUCCESS) { 4649 igb_log(igb, 4650 "Add MSI interrupt handler failed: %d", rc); 4651 return (IGB_FAILURE); 4652 } 4653 4654 rx_ring = &igb->rx_rings[0]; 4655 rx_ring->intr_vector = vector; 4656 4657 vector++; 4658 break; 4659 4660 case DDI_INTR_TYPE_FIXED: 4661 /* Add interrupt handlers for the only vector */ 4662 rc = ddi_intr_add_handler(igb->htable[vector], 4663 (ddi_intr_handler_t *)igb_intr_legacy, 4664 (void *)igb, NULL); 4665 4666 if (rc != DDI_SUCCESS) { 4667 igb_log(igb, 4668 "Add legacy interrupt handler failed: %d", rc); 4669 return (IGB_FAILURE); 4670 } 4671 4672 rx_ring = &igb->rx_rings[0]; 4673 rx_ring->intr_vector = vector; 4674 4675 vector++; 4676 break; 4677 4678 default: 4679 return (IGB_FAILURE); 4680 } 4681 4682 ASSERT(vector == igb->intr_cnt); 4683 4684 return (IGB_SUCCESS); 4685 } 4686 4687 /* 4688 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts 4689 * 4690 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 4691 */ 4692 static void 4693 igb_setup_msix_82575(igb_t *igb) 4694 { 4695 uint32_t eims = 0; 4696 int i, vector; 4697 struct e1000_hw *hw = &igb->hw; 4698 4699 /* 4700 * Set vector for tx ring 0 and other causes. 4701 * NOTE assumption that it is vector 0. 4702 */ 4703 vector = 0; 4704 4705 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 4706 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 4707 vector++; 4708 4709 for (i = 0; i < igb->num_rx_rings; i++) { 4710 /* 4711 * Set vector for each rx ring 4712 */ 4713 eims = (E1000_EICR_RX_QUEUE0 << i); 4714 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4715 4716 /* 4717 * Accumulate bits to enable in 4718 * igb_enable_adapter_interrupts_82575() 4719 */ 4720 igb->eims_mask |= eims; 4721 4722 vector++; 4723 } 4724 4725 for (i = 1; i < igb->num_tx_rings; i++) { 4726 /* 4727 * Set vector for each tx ring from 2nd tx ring 4728 */ 4729 eims = (E1000_EICR_TX_QUEUE0 << i); 4730 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4731 4732 /* 4733 * Accumulate bits to enable in 4734 * igb_enable_adapter_interrupts_82575() 4735 */ 4736 igb->eims_mask |= eims; 4737 4738 vector++; 4739 } 4740 4741 ASSERT(vector == igb->intr_cnt); 4742 4743 /* 4744 * Disable IAM for ICR interrupt bits 4745 */ 4746 E1000_WRITE_REG(hw, E1000_IAM, 0); 4747 E1000_WRITE_FLUSH(hw); 4748 } 4749 4750 /* 4751 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts 4752 * 4753 * 82576 uses a table based method for assigning vectors. Each queue has a 4754 * single entry in the table to which we write a vector number along with a 4755 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors 4756 * take a different position in the 4-byte register depending on whether 4757 * they are numbered above or below 8. 4758 */ 4759 static void 4760 igb_setup_msix_82576(igb_t *igb) 4761 { 4762 struct e1000_hw *hw = &igb->hw; 4763 uint32_t ivar, index, vector; 4764 int i; 4765 4766 /* must enable msi-x capability before IVAR settings */ 4767 E1000_WRITE_REG(hw, E1000_GPIE, 4768 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR)); 4769 4770 /* 4771 * Set vector for tx ring 0 and other causes. 4772 * NOTE assumption that it is vector 0. 4773 * This is also interdependent with installation of interrupt service 4774 * routines in igb_add_intr_handlers(). 4775 */ 4776 4777 /* assign "other" causes to vector 0 */ 4778 vector = 0; 4779 ivar = ((vector | E1000_IVAR_VALID) << 8); 4780 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4781 4782 /* assign tx ring 0 to vector 0 */ 4783 ivar = ((vector | E1000_IVAR_VALID) << 8); 4784 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4785 4786 /* prepare to enable tx & other interrupt causes */ 4787 igb->eims_mask = (1 << vector); 4788 4789 vector ++; 4790 for (i = 0; i < igb->num_rx_rings; i++) { 4791 /* 4792 * Set vector for each rx ring 4793 */ 4794 index = (i & 0x7); 4795 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4796 4797 if (i < 8) { 4798 /* vector goes into low byte of register */ 4799 ivar = ivar & 0xFFFFFF00; 4800 ivar |= (vector | E1000_IVAR_VALID); 4801 } else { 4802 /* vector goes into third byte of register */ 4803 ivar = ivar & 0xFF00FFFF; 4804 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4805 } 4806 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4807 4808 /* Accumulate interrupt-cause bits to enable */ 4809 igb->eims_mask |= (1 << vector); 4810 4811 vector ++; 4812 } 4813 4814 for (i = 1; i < igb->num_tx_rings; i++) { 4815 /* 4816 * Set vector for each tx ring from 2nd tx ring. 4817 * Note assumption that tx vectors numericall follow rx vectors. 4818 */ 4819 index = (i & 0x7); 4820 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4821 4822 if (i < 8) { 4823 /* vector goes into second byte of register */ 4824 ivar = ivar & 0xFFFF00FF; 4825 ivar |= ((vector | E1000_IVAR_VALID) << 8); 4826 } else { 4827 /* vector goes into fourth byte of register */ 4828 ivar = ivar & 0x00FFFFFF; 4829 ivar |= (vector | E1000_IVAR_VALID) << 24; 4830 } 4831 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4832 4833 /* Accumulate interrupt-cause bits to enable */ 4834 igb->eims_mask |= (1 << vector); 4835 4836 vector ++; 4837 } 4838 4839 ASSERT(vector == igb->intr_cnt); 4840 } 4841 4842 /* 4843 * igb_setup_msix_82580 - setup 82580 adapter to use MSI-X interrupts 4844 * 4845 * 82580 uses same table approach at 82576 but has fewer entries. Each 4846 * queue has a single entry in the table to which we write a vector number 4847 * along with a "valid" bit. Vectors take a different position in the 4848 * register depending on * whether * they are numbered above or below 4. 4849 */ 4850 static void 4851 igb_setup_msix_82580(igb_t *igb) 4852 { 4853 struct e1000_hw *hw = &igb->hw; 4854 uint32_t ivar, index, vector; 4855 int i; 4856 4857 /* must enable msi-x capability before IVAR settings */ 4858 E1000_WRITE_REG(hw, E1000_GPIE, (E1000_GPIE_MSIX_MODE | 4859 E1000_GPIE_PBA | E1000_GPIE_NSICR | E1000_GPIE_EIAME)); 4860 /* 4861 * Set vector for tx ring 0 and other causes. 4862 * NOTE assumption that it is vector 0. 4863 * This is also interdependent with installation of interrupt service 4864 * routines in igb_add_intr_handlers(). 4865 */ 4866 4867 /* assign "other" causes to vector 0 */ 4868 vector = 0; 4869 ivar = ((vector | E1000_IVAR_VALID) << 8); 4870 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4871 4872 /* assign tx ring 0 to vector 0 */ 4873 ivar = ((vector | E1000_IVAR_VALID) << 8); 4874 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4875 4876 /* prepare to enable tx & other interrupt causes */ 4877 igb->eims_mask = (1 << vector); 4878 4879 vector ++; 4880 4881 for (i = 0; i < igb->num_rx_rings; i++) { 4882 /* 4883 * Set vector for each rx ring 4884 */ 4885 index = (i >> 1); 4886 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4887 4888 if (i & 1) { 4889 /* vector goes into third byte of register */ 4890 ivar = ivar & 0xFF00FFFF; 4891 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4892 } else { 4893 /* vector goes into low byte of register */ 4894 ivar = ivar & 0xFFFFFF00; 4895 ivar |= (vector | E1000_IVAR_VALID); 4896 } 4897 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4898 4899 /* Accumulate interrupt-cause bits to enable */ 4900 igb->eims_mask |= (1 << vector); 4901 4902 vector ++; 4903 } 4904 4905 for (i = 1; i < igb->num_tx_rings; i++) { 4906 /* 4907 * Set vector for each tx ring from 2nd tx ring. 4908 * Note assumption that tx vectors numericall follow rx vectors. 4909 */ 4910 index = (i >> 1); 4911 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4912 4913 if (i & 1) { 4914 /* vector goes into high byte of register */ 4915 ivar = ivar & 0x00FFFFFF; 4916 ivar |= ((vector | E1000_IVAR_VALID) << 24); 4917 } else { 4918 /* vector goes into second byte of register */ 4919 ivar = ivar & 0xFFFF00FF; 4920 ivar |= (vector | E1000_IVAR_VALID) << 8; 4921 } 4922 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4923 4924 /* Accumulate interrupt-cause bits to enable */ 4925 igb->eims_mask |= (1 << vector); 4926 4927 vector ++; 4928 } 4929 ASSERT(vector == igb->intr_cnt); 4930 } 4931 4932 /* 4933 * igb_rem_intr_handlers - remove the interrupt handlers 4934 */ 4935 static void 4936 igb_rem_intr_handlers(igb_t *igb) 4937 { 4938 int i; 4939 int rc; 4940 4941 for (i = 0; i < igb->intr_cnt; i++) { 4942 rc = ddi_intr_remove_handler(igb->htable[i]); 4943 if (rc != DDI_SUCCESS) { 4944 IGB_DEBUGLOG_1(igb, 4945 "Remove intr handler failed: %d", rc); 4946 } 4947 } 4948 } 4949 4950 /* 4951 * igb_rem_intrs - remove the allocated interrupts 4952 */ 4953 static void 4954 igb_rem_intrs(igb_t *igb) 4955 { 4956 int i; 4957 int rc; 4958 4959 for (i = 0; i < igb->intr_cnt; i++) { 4960 rc = ddi_intr_free(igb->htable[i]); 4961 if (rc != DDI_SUCCESS) { 4962 IGB_DEBUGLOG_1(igb, 4963 "Free intr failed: %d", rc); 4964 } 4965 } 4966 4967 kmem_free(igb->htable, igb->intr_size); 4968 igb->htable = NULL; 4969 } 4970 4971 /* 4972 * igb_enable_intrs - enable all the ddi interrupts 4973 */ 4974 static int 4975 igb_enable_intrs(igb_t *igb) 4976 { 4977 int i; 4978 int rc; 4979 4980 /* Enable interrupts */ 4981 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4982 /* Call ddi_intr_block_enable() for MSI */ 4983 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 4984 if (rc != DDI_SUCCESS) { 4985 igb_log(igb, 4986 "Enable block intr failed: %d", rc); 4987 return (IGB_FAILURE); 4988 } 4989 } else { 4990 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4991 for (i = 0; i < igb->intr_cnt; i++) { 4992 rc = ddi_intr_enable(igb->htable[i]); 4993 if (rc != DDI_SUCCESS) { 4994 igb_log(igb, 4995 "Enable intr failed: %d", rc); 4996 return (IGB_FAILURE); 4997 } 4998 } 4999 } 5000 5001 return (IGB_SUCCESS); 5002 } 5003 5004 /* 5005 * igb_disable_intrs - disable all the ddi interrupts 5006 */ 5007 static int 5008 igb_disable_intrs(igb_t *igb) 5009 { 5010 int i; 5011 int rc; 5012 5013 /* Disable all interrupts */ 5014 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 5015 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 5016 if (rc != DDI_SUCCESS) { 5017 igb_log(igb, 5018 "Disable block intr failed: %d", rc); 5019 return (IGB_FAILURE); 5020 } 5021 } else { 5022 for (i = 0; i < igb->intr_cnt; i++) { 5023 rc = ddi_intr_disable(igb->htable[i]); 5024 if (rc != DDI_SUCCESS) { 5025 igb_log(igb, 5026 "Disable intr failed: %d", rc); 5027 return (IGB_FAILURE); 5028 } 5029 } 5030 } 5031 5032 return (IGB_SUCCESS); 5033 } 5034 5035 /* 5036 * igb_get_phy_state - Get and save the parameters read from PHY registers 5037 */ 5038 static void 5039 igb_get_phy_state(igb_t *igb) 5040 { 5041 struct e1000_hw *hw = &igb->hw; 5042 uint16_t phy_ctrl; 5043 uint16_t phy_status; 5044 uint16_t phy_an_adv; 5045 uint16_t phy_an_exp; 5046 uint16_t phy_ext_status; 5047 uint16_t phy_1000t_ctrl; 5048 uint16_t phy_1000t_status; 5049 uint16_t phy_lp_able; 5050 5051 ASSERT(mutex_owned(&igb->gen_lock)); 5052 5053 if (hw->phy.media_type == e1000_media_type_copper) { 5054 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5055 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 5056 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 5057 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 5058 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 5059 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 5060 (void) e1000_read_phy_reg(hw, 5061 PHY_1000T_STATUS, &phy_1000t_status); 5062 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 5063 5064 igb->param_autoneg_cap = 5065 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5066 igb->param_pause_cap = 5067 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5068 igb->param_asym_pause_cap = 5069 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5070 igb->param_1000fdx_cap = 5071 ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5072 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5073 igb->param_1000hdx_cap = 5074 ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5075 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5076 igb->param_100t4_cap = 5077 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5078 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 5079 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5080 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 5081 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5082 igb->param_10fdx_cap = 5083 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5084 igb->param_10hdx_cap = 5085 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5086 igb->param_rem_fault = 5087 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 5088 5089 igb->param_adv_autoneg_cap = hw->mac.autoneg; 5090 igb->param_adv_pause_cap = 5091 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5092 igb->param_adv_asym_pause_cap = 5093 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5094 igb->param_adv_1000hdx_cap = 5095 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5096 igb->param_adv_100t4_cap = 5097 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5098 igb->param_adv_rem_fault = 5099 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 5100 if (igb->param_adv_autoneg_cap == 1) { 5101 igb->param_adv_1000fdx_cap = 5102 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5103 igb->param_adv_100fdx_cap = 5104 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5105 igb->param_adv_100hdx_cap = 5106 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5107 igb->param_adv_10fdx_cap = 5108 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5109 igb->param_adv_10hdx_cap = 5110 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5111 } 5112 5113 igb->param_lp_autoneg_cap = 5114 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5115 igb->param_lp_pause_cap = 5116 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5117 igb->param_lp_asym_pause_cap = 5118 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5119 igb->param_lp_1000fdx_cap = 5120 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5121 igb->param_lp_1000hdx_cap = 5122 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5123 igb->param_lp_100t4_cap = 5124 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5125 igb->param_lp_100fdx_cap = 5126 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5127 igb->param_lp_100hdx_cap = 5128 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5129 igb->param_lp_10fdx_cap = 5130 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5131 igb->param_lp_10hdx_cap = 5132 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5133 igb->param_lp_rem_fault = 5134 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 5135 } else { 5136 /* 5137 * 1Gig Fiber adapter only offers 1Gig Full Duplex. 5138 */ 5139 igb->param_autoneg_cap = 0; 5140 igb->param_pause_cap = 1; 5141 igb->param_asym_pause_cap = 1; 5142 igb->param_1000fdx_cap = 1; 5143 igb->param_1000hdx_cap = 0; 5144 igb->param_100t4_cap = 0; 5145 igb->param_100fdx_cap = 0; 5146 igb->param_100hdx_cap = 0; 5147 igb->param_10fdx_cap = 0; 5148 igb->param_10hdx_cap = 0; 5149 5150 igb->param_adv_autoneg_cap = 0; 5151 igb->param_adv_pause_cap = 1; 5152 igb->param_adv_asym_pause_cap = 1; 5153 igb->param_adv_1000fdx_cap = 1; 5154 igb->param_adv_1000hdx_cap = 0; 5155 igb->param_adv_100t4_cap = 0; 5156 igb->param_adv_100fdx_cap = 0; 5157 igb->param_adv_100hdx_cap = 0; 5158 igb->param_adv_10fdx_cap = 0; 5159 igb->param_adv_10hdx_cap = 0; 5160 5161 igb->param_lp_autoneg_cap = 0; 5162 igb->param_lp_pause_cap = 0; 5163 igb->param_lp_asym_pause_cap = 0; 5164 igb->param_lp_1000fdx_cap = 0; 5165 igb->param_lp_1000hdx_cap = 0; 5166 igb->param_lp_100t4_cap = 0; 5167 igb->param_lp_100fdx_cap = 0; 5168 igb->param_lp_100hdx_cap = 0; 5169 igb->param_lp_10fdx_cap = 0; 5170 igb->param_lp_10hdx_cap = 0; 5171 igb->param_lp_rem_fault = 0; 5172 } 5173 } 5174 5175 /* 5176 * synchronize the adv* and en* parameters. 5177 * 5178 * See comments in <sys/dld.h> for details of the *_en_* 5179 * parameters. The usage of ndd for setting adv parameters will 5180 * synchronize all the en parameters with the e1000g parameters, 5181 * implicitly disabling any settings made via dladm. 5182 */ 5183 static void 5184 igb_param_sync(igb_t *igb) 5185 { 5186 igb->param_en_1000fdx_cap = igb->param_adv_1000fdx_cap; 5187 igb->param_en_1000hdx_cap = igb->param_adv_1000hdx_cap; 5188 igb->param_en_100t4_cap = igb->param_adv_100t4_cap; 5189 igb->param_en_100fdx_cap = igb->param_adv_100fdx_cap; 5190 igb->param_en_100hdx_cap = igb->param_adv_100hdx_cap; 5191 igb->param_en_10fdx_cap = igb->param_adv_10fdx_cap; 5192 igb->param_en_10hdx_cap = igb->param_adv_10hdx_cap; 5193 } 5194 5195 /* 5196 * igb_get_driver_control 5197 */ 5198 static void 5199 igb_get_driver_control(struct e1000_hw *hw) 5200 { 5201 uint32_t ctrl_ext; 5202 5203 /* Notify firmware that driver is in control of device */ 5204 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5205 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 5206 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5207 } 5208 5209 /* 5210 * igb_release_driver_control 5211 */ 5212 static void 5213 igb_release_driver_control(struct e1000_hw *hw) 5214 { 5215 uint32_t ctrl_ext; 5216 5217 /* Notify firmware that driver is no longer in control of device */ 5218 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5219 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 5220 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5221 } 5222 5223 /* 5224 * igb_atomic_reserve - Atomic decrease operation 5225 */ 5226 int 5227 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 5228 { 5229 uint32_t oldval; 5230 uint32_t newval; 5231 5232 /* ATOMICALLY */ 5233 do { 5234 oldval = *count_p; 5235 if (oldval < n) 5236 return (-1); 5237 newval = oldval - n; 5238 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 5239 5240 return (newval); 5241 } 5242 5243 /* 5244 * FMA support 5245 */ 5246 5247 int 5248 igb_check_acc_handle(ddi_acc_handle_t handle) 5249 { 5250 ddi_fm_error_t de; 5251 5252 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5253 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5254 return (de.fme_status); 5255 } 5256 5257 int 5258 igb_check_dma_handle(ddi_dma_handle_t handle) 5259 { 5260 ddi_fm_error_t de; 5261 5262 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5263 return (de.fme_status); 5264 } 5265 5266 /* 5267 * The IO fault service error handling callback function 5268 */ 5269 /*ARGSUSED*/ 5270 static int 5271 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5272 { 5273 /* 5274 * as the driver can always deal with an error in any dma or 5275 * access handle, we can just return the fme_status value. 5276 */ 5277 pci_ereport_post(dip, err, NULL); 5278 return (err->fme_status); 5279 } 5280 5281 static void 5282 igb_fm_init(igb_t *igb) 5283 { 5284 ddi_iblock_cookie_t iblk; 5285 int fma_dma_flag; 5286 5287 /* Only register with IO Fault Services if we have some capability */ 5288 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5289 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5290 } else { 5291 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5292 } 5293 5294 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5295 fma_dma_flag = 1; 5296 } else { 5297 fma_dma_flag = 0; 5298 } 5299 5300 (void) igb_set_fma_flags(fma_dma_flag); 5301 5302 if (igb->fm_capabilities) { 5303 5304 /* Register capabilities with IO Fault Services */ 5305 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 5306 5307 /* 5308 * Initialize pci ereport capabilities if ereport capable 5309 */ 5310 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 5311 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5312 pci_ereport_setup(igb->dip); 5313 5314 /* 5315 * Register error callback if error callback capable 5316 */ 5317 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5318 ddi_fm_handler_register(igb->dip, 5319 igb_fm_error_cb, (void*) igb); 5320 } 5321 } 5322 5323 static void 5324 igb_fm_fini(igb_t *igb) 5325 { 5326 /* Only unregister FMA capabilities if we registered some */ 5327 if (igb->fm_capabilities) { 5328 5329 /* 5330 * Release any resources allocated by pci_ereport_setup() 5331 */ 5332 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 5333 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5334 pci_ereport_teardown(igb->dip); 5335 5336 /* 5337 * Un-register error callback if error callback capable 5338 */ 5339 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5340 ddi_fm_handler_unregister(igb->dip); 5341 5342 /* Unregister from IO Fault Services */ 5343 ddi_fm_fini(igb->dip); 5344 } 5345 } 5346 5347 void 5348 igb_fm_ereport(igb_t *igb, char *detail) 5349 { 5350 uint64_t ena; 5351 char buf[FM_MAX_CLASS]; 5352 5353 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5354 ena = fm_ena_generate(0, FM_ENA_FMT1); 5355 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 5356 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 5357 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5358 } 5359 } 5360