1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/ddi.h> 30 #include <sys/inline.h> 31 #include <sys/conf.h> 32 #include <sys/sunddi.h> 33 #include <sys/sunndi.h> 34 #include <sys/i8042.h> 35 #include <sys/kmem.h> 36 #include <sys/promif.h> /* for prom_printf */ 37 #include <sys/note.h> 38 39 /* 40 * Note: For x86, this driver is used to create keyboard/mouse nodes when 41 * booting with ACPI enumeration turned off (acpi-enum=off). 42 */ 43 44 /* 45 * Unfortunately, soft interrupts are implemented poorly. Each additional 46 * soft interrupt user impacts the performance of all existing soft interrupt 47 * users. This is not the case on SPARC, however. 48 */ 49 #ifdef __sparc 50 #define USE_SOFT_INTRS 51 #else 52 #undef USE_SOFT_INTRS 53 #endif 54 55 /* 56 * The command bytes are different for x86 and for SPARC because on x86, 57 * all modern 8042s can properly translate scan code set 2 codes to 58 * scan code set 1. On SPARC systems that have 8042s (e.g. Tadpole laptops), 59 * setting the "translation" bit in the command byte has no effect. 60 * This is potentially dangerous if, in the future, new SPARC systems uses 8042s 61 * that implement the scan code translation when the translation bit is set. 62 * 63 * On SPARC, kb8042 will attempt to detect which scan code set the keyboard 64 * is using. In order for that code to work, the real scan code set must be the 65 * set that is returned by the keyboard (and not a different set that is 66 * translated by the 8042). (e.g. If the translation bit were enabled here, 67 * and the keyboard returned scan code set 2 when kb8042 queried it, kb8042 68 * would not be able to know with certainty that the scan codes it will receive 69 * are set 2 scancodes, or set 1 translations made by the 8042). 70 */ 71 72 /* 73 * 8042 Command Byte Layout: 74 * 75 * 0x80: 0 = Reserved, must be zero. 76 * 0x40: 1 = Translate to XT codes. (0=No translation) 77 * 0x20: 1 = Disable aux (mouse) port. (0=Enable port) 78 * 0x10: 1 = Disable main (keyboard) port. (0=Enable port) 79 * 0x08: 0 = Reserved, must be zero. 80 * 0x04: 1 = System flag, 1 means passed self-test. 81 * Caution: setting this bit to zero causes some 82 * systems (HP Kayak XA) to fail to reboot without 83 * a hard reset. 84 * 0x02: 0 = Disable aux port interrupts. (1=Enable aux port interrupts) 85 * 0x01: 0 = Disable main port interrupts. (1=Enable main port interrupts) 86 * 87 */ 88 #if defined(__sparc) 89 #define I8042_CMD_DISABLE_ALL 0x34 90 #define I8042_CMD_ENABLE_ALL 0x07 91 #elif defined(__i386) || defined(__amd64) 92 #define I8042_CMD_DISABLE_ALL 0x74 93 #define I8042_CMD_ENABLE_ALL 0x47 94 #endif 95 96 #define BUFSIZ 64 97 98 /* 99 * Child nodes, used to determine which to create at bus_config time 100 */ 101 #define I8042_KEYBOARD 2 102 #define I8042_MOUSE 1 103 104 enum i8042_ports { 105 MAIN_PORT = 0, 106 AUX_PORT 107 }; 108 109 #define NUM_PORTS 2 110 111 /* 112 * Only register at most MAX_INTERRUPTS interrupt handlers, 113 * regardless of the number of interrupts in the prom node. 114 * This is important, as registering for all interrupts on 115 * some systems (e.g. Tadpole laptops) results in a flood 116 * of spurious interrupts (for Tadpole, the first 2 interrupts 117 * are for the keyboard and mouse, respectively, and the 118 * third is for a proprietary device that is also accessed 119 * via the same I/O addresses.) 120 */ 121 #define MAX_INTERRUPTS 2 122 123 /* 124 * One of these for each port - main (keyboard) and aux (mouse). 125 */ 126 struct i8042_port { 127 boolean_t initialized; 128 dev_info_t *dip; 129 int inumber; 130 enum i8042_ports which; /* main or aux port */ 131 #if defined(USE_SOFT_INTRS) 132 ddi_softint_handle_t soft_hdl; 133 boolean_t soft_intr_enabled; 134 #else 135 kmutex_t intr_mutex; 136 #endif 137 uint_t (*intr_func)(caddr_t arg1, caddr_t arg2); 138 caddr_t intr_arg1; 139 caddr_t intr_arg2; 140 struct i8042 *i8042_global; 141 /* 142 * wptr is next byte to write 143 */ 144 int wptr; 145 /* 146 * rptr is next byte to read, == wptr means empty 147 * NB: At full, one byte is unused. 148 */ 149 int rptr; 150 int overruns; 151 unsigned char buf[BUFSIZ]; 152 }; 153 154 /* 155 * Describes entire 8042 device. 156 */ 157 struct i8042 { 158 dev_info_t *dip; 159 struct i8042_port i8042_ports[NUM_PORTS]; 160 kmutex_t i8042_mutex; 161 kmutex_t i8042_out_mutex; 162 boolean_t initialized; 163 ddi_acc_handle_t io_handle; 164 uint8_t *io_addr; 165 int nintrs; 166 ddi_iblock_cookie_t *iblock_cookies; 167 uint_t init_state; 168 /* Initialization states: */ 169 #define I8042_INIT_BASIC 0x00000001 170 #define I8042_INIT_REGS_MAPPED 0x00000002 171 #define I8042_INIT_MUTEXES 0x00000004 172 #define I8042_INIT_INTRS_ENABLED 0x00000010 173 uint_t intrs_added; 174 #ifdef __sparc 175 timeout_id_t timeout_id; 176 #endif 177 }; 178 179 /* 180 * i8042 hardware register definitions 181 */ 182 183 /* 184 * These are I/O registers, relative to the device's base (normally 0x60). 185 */ 186 #define I8042_DATA 0x00 /* read/write data here */ 187 #define I8042_STAT 0x04 /* read status here */ 188 #define I8042_CMD 0x04 /* write commands here */ 189 190 /* 191 * These are bits in I8042_STAT. 192 */ 193 #define I8042_STAT_OUTBF 0x01 /* Output (to host) buffer full */ 194 #define I8042_STAT_INBF 0x02 /* Input (from host) buffer full */ 195 #define I8042_STAT_AUXBF 0x20 /* Output buffer data is from aux */ 196 197 /* 198 * These are commands to the i8042 itself (as distinct from the devices 199 * attached to it). 200 */ 201 #define I8042_CMD_RCB 0x20 /* Read command byte (we don't use) */ 202 #define I8042_CMD_WCB 0x60 /* Write command byte */ 203 #define I8042_CMD_WRITE_AUX 0xD4 /* Send next data byte to aux port */ 204 205 /* 206 * Maximum number of times to loop while clearing pending data from the 207 * keyboard controller. 208 */ 209 #define MAX_JUNK_ITERATIONS 1000 210 211 /* 212 * Maximum time to wait for the keyboard to become ready to accept data 213 * (maximum time = MAX_WAIT_ITERATIONS * USECS_PER_WAIT (default is 250ms)) 214 */ 215 #define MAX_WAIT_ITERATIONS 25000 216 #define USECS_PER_WAIT 10 217 218 219 #ifdef __sparc 220 221 #define PLATFORM_MATCH(s) (strncmp(ddi_get_name(ddi_root_node()), \ 222 (s), strlen(s)) == 0) 223 224 /* 225 * On some older SPARC platforms that have problems with the 226 * interrupt line attached to the PS/2 keyboard/mouse, it 227 * may be necessary to change the operating mode of the nexus 228 * to a polling-based (instead of interrupt-based) method. 229 * this variable is present to enable a worst-case workaround so 230 * owners of these systems can still retain a working keyboard. 231 * 232 * The `i8042_polled_mode' variable can be used to force polled 233 * mode for platforms that have this issue, but for which 234 * automatic relief is not implemented. 235 * 236 * In the off chance that one of the platforms is misidentified 237 * as requiried polling mode, `i8042_force_interrupt_mode' can 238 * be set to force the nexus to use interrupts. 239 */ 240 #define I8042_MIN_POLL_INTERVAL 1000 /* usecs */ 241 int i8042_poll_interval = 8000; /* usecs */ 242 int i8042_fast_poll_interval; /* usecs */ 243 int i8042_slow_poll_interval; /* usecs */ 244 245 boolean_t i8042_polled_mode = B_FALSE; 246 boolean_t i8042_force_interrupt_mode = B_FALSE; 247 #endif /* __sparc */ 248 249 int max_wait_iterations = MAX_WAIT_ITERATIONS; 250 251 /* 252 * function prototypes for bus ops routines: 253 */ 254 static int i8042_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 255 off_t offset, off_t len, caddr_t *addrp); 256 static int i8042_ctlops(dev_info_t *dip, dev_info_t *rdip, 257 ddi_ctl_enum_t op, void *arg, void *result); 258 259 /* 260 * function prototypes for dev ops routines: 261 */ 262 static int i8042_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 263 static int i8042_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 264 static int i8042_intr_ops(dev_info_t *dip, dev_info_t *rdip, 265 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 266 static int i8042_bus_config(dev_info_t *, uint_t, ddi_bus_config_op_t, 267 void *, dev_info_t **); 268 static int i8042_bus_unconfig(dev_info_t *, uint_t, 269 ddi_bus_config_op_t, void *); 270 #ifdef __sparc 271 static int i8042_build_interrupts_property(dev_info_t *dip); 272 static boolean_t i8042_is_polling_platform(void); 273 #endif 274 275 /* 276 * bus ops and dev ops structures: 277 */ 278 static struct bus_ops i8042_bus_ops = { 279 BUSO_REV, 280 i8042_map, 281 NULL, 282 NULL, 283 NULL, 284 NULL, /* ddi_map_fault */ 285 NULL, /* ddi_dma_map */ 286 NULL, /* ddi_dma_allochdl */ 287 NULL, /* ddi_dma_freehdl */ 288 NULL, /* ddi_dma_bindhdl */ 289 NULL, /* ddi_dma_unbindhdl */ 290 NULL, /* ddi_dma_flush */ 291 NULL, /* ddi_dma_win */ 292 NULL, /* ddi_dma_mctl */ 293 i8042_ctlops, 294 ddi_bus_prop_op, 295 NULL, /* (*bus_get_eventcookie)(); */ 296 NULL, /* (*bus_add_eventcall)(); */ 297 NULL, /* (*bus_remove_eventcall)(); */ 298 NULL, /* (*bus_post_event)(); */ 299 NULL, /* bus_intr_ctl */ 300 i8042_bus_config, /* bus_config */ 301 i8042_bus_unconfig, /* bus_unconfig */ 302 NULL, /* bus_fm_init */ 303 NULL, /* bus_fm_fini */ 304 NULL, /* bus_fm_access_enter */ 305 NULL, /* bus_fm_access_exit */ 306 NULL, /* bus_power */ 307 i8042_intr_ops /* bus_intr_op */ 308 }; 309 310 static struct dev_ops i8042_ops = { 311 DEVO_REV, 312 0, 313 ddi_no_info, 314 nulldev, 315 0, 316 i8042_attach, 317 i8042_detach, 318 nodev, 319 (struct cb_ops *)0, 320 &i8042_bus_ops 321 }; 322 323 324 /* 325 * module definitions: 326 */ 327 #include <sys/modctl.h> 328 extern struct mod_ops mod_driverops; 329 330 static struct modldrv modldrv = { 331 &mod_driverops, /* Type of module. This one is a driver */ 332 "i8042 nexus driver %I%", /* Name of module. */ 333 &i8042_ops, /* driver ops */ 334 }; 335 336 static struct modlinkage modlinkage = { 337 MODREV_1, (void *)&modldrv, NULL 338 }; 339 340 int 341 _init(void) 342 { 343 int e; 344 345 /* 346 * Install the module. 347 */ 348 e = mod_install(&modlinkage); 349 return (e); 350 } 351 352 int 353 _fini(void) 354 { 355 int e; 356 357 /* 358 * Remove the module. 359 */ 360 e = mod_remove(&modlinkage); 361 if (e != 0) 362 return (e); 363 364 return (e); 365 } 366 367 int 368 _info(struct modinfo *modinfop) 369 { 370 return (mod_info(&modlinkage, modinfop)); 371 } 372 373 #define DRIVER_NAME(dip) ddi_driver_name(dip) 374 375 static void i8042_timeout(void *arg); 376 static unsigned int i8042_intr(caddr_t arg); 377 static void i8042_write_command_byte(struct i8042 *, unsigned char); 378 static uint8_t i8042_get8(ddi_acc_impl_t *handlep, uint8_t *addr); 379 static void i8042_put8(ddi_acc_impl_t *handlep, uint8_t *addr, 380 uint8_t value); 381 static void i8042_send(struct i8042 *global, int reg, unsigned char cmd); 382 383 unsigned int i8042_unclaimed_interrupts = 0; 384 385 static int 386 i8042_cleanup(struct i8042 *global) 387 { 388 int which_port, i; 389 struct i8042_port *port; 390 391 ASSERT(global != NULL); 392 393 if (global->initialized == B_TRUE) { 394 /* 395 * If any children still have regs mapped or interrupts 396 * registered, return immediate failure (and do nothing). 397 */ 398 mutex_enter(&global->i8042_mutex); 399 400 for (which_port = 0; which_port < NUM_PORTS; which_port++) { 401 port = &global->i8042_ports[which_port]; 402 403 if (port->initialized == B_TRUE) { 404 mutex_exit(&global->i8042_mutex); 405 return (DDI_FAILURE); 406 } 407 #if defined(USE_SOFT_INTRS) 408 if (port->soft_hdl != 0) { 409 mutex_exit(&global->i8042_mutex); 410 return (DDI_FAILURE); 411 } 412 #else 413 mutex_enter(&port->intr_mutex); 414 if (port->intr_func != NULL) { 415 mutex_exit(&port->intr_mutex); 416 mutex_exit(&global->i8042_mutex); 417 return (DDI_FAILURE); 418 } 419 mutex_exit(&port->intr_mutex); 420 #endif 421 } 422 global->initialized = B_FALSE; 423 424 mutex_exit(&global->i8042_mutex); 425 } 426 427 #ifdef __sparc 428 /* If there may be an outstanding timeout, cancel it */ 429 if (global->timeout_id != 0) { 430 (void) untimeout(global->timeout_id); 431 } 432 #endif 433 434 /* Stop the controller from generating interrupts */ 435 if (global->init_state & I8042_INIT_INTRS_ENABLED) 436 i8042_write_command_byte(global, I8042_CMD_DISABLE_ALL); 437 438 if (global->intrs_added) { 439 /* 440 * Remove the interrupts in the reverse order in 441 * which they were added 442 */ 443 for (i = global->nintrs - 1; i >= 0; i--) { 444 if (global->intrs_added & (1 << i)) 445 ddi_remove_intr(global->dip, i, 446 global->iblock_cookies[i]); 447 } 448 } 449 450 if (global->init_state & I8042_INIT_MUTEXES) { 451 #ifndef USE_SOFT_INTRS 452 for (which_port = 0; which_port < NUM_PORTS; which_port++) { 453 port = &global->i8042_ports[which_port]; 454 mutex_destroy(&port->intr_mutex); 455 } 456 #endif 457 mutex_destroy(&global->i8042_out_mutex); 458 mutex_destroy(&global->i8042_mutex); 459 } 460 461 if (global->init_state & I8042_INIT_REGS_MAPPED) 462 ddi_regs_map_free(&global->io_handle); 463 464 if (global->init_state & I8042_INIT_BASIC) { 465 ddi_set_driver_private(global->dip, (caddr_t)NULL); 466 if (global->nintrs > 0) { 467 kmem_free(global->iblock_cookies, global->nintrs * 468 sizeof (ddi_iblock_cookie_t)); 469 } 470 kmem_free(global, sizeof (struct i8042)); 471 } 472 473 return (DDI_SUCCESS); 474 } 475 476 #define OBF_WAIT_COUNT 1000 /* in granules of 10uS */ 477 478 /* 479 * Wait for the 8042 to fill the 'output' (from 8042 to host) 480 * buffer. If 8042 fails to fill the output buffer within an 481 * allowed time, return 1 (which means there is no data available), 482 * otherwise return 0 483 */ 484 static int 485 i8042_wait_obf(struct i8042 *global) 486 { 487 int timer = 0; 488 489 while (!(ddi_get8(global->io_handle, global->io_addr + I8042_STAT) & 490 I8042_STAT_OUTBF)) { 491 if (++timer > OBF_WAIT_COUNT) 492 return (1); 493 drv_usecwait(10); 494 } 495 return (0); 496 } 497 498 /* 499 * Drain all queued bytes from the 8042. 500 * Return 0 for no error, <> 0 if there was an error. 501 */ 502 static int 503 i8042_purge_outbuf(struct i8042 *global) 504 { 505 int i; 506 507 for (i = 0; i < MAX_JUNK_ITERATIONS; i++) { 508 if (i8042_wait_obf(global)) 509 break; 510 (void) ddi_get8(global->io_handle, 511 global->io_addr + I8042_DATA); 512 } 513 514 /* 515 * If we hit the maximum number of iterations, then there 516 * was a serious problem (e.g. our hardware may not be 517 * present or working properly). 518 */ 519 return (i == MAX_JUNK_ITERATIONS); 520 } 521 522 static int 523 i8042_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 524 { 525 struct i8042_port *port; 526 enum i8042_ports which_port; 527 int i; 528 static ddi_device_acc_attr_t attr = { 529 DDI_DEVICE_ATTR_V0, 530 DDI_NEVERSWAP_ACC, 531 DDI_STRICTORDER_ACC, 532 }; 533 struct i8042 *global; 534 #ifdef __sparc 535 int interval; 536 #endif 537 538 switch (cmd) { 539 case DDI_RESUME: 540 #ifdef __sparc 541 global = (struct i8042 *)ddi_get_driver_private(dip); 542 i8042_write_command_byte(global, I8042_CMD_ENABLE_ALL); 543 #endif 544 return (DDI_SUCCESS); 545 546 case DDI_ATTACH: 547 /* Handled in the main function block */ 548 break; 549 550 default: 551 return (DDI_FAILURE); 552 } 553 554 /* 555 * DDI_ATTACH processing 556 */ 557 558 global = (struct i8042 *)kmem_zalloc(sizeof (struct i8042), KM_SLEEP); 559 ddi_set_driver_private(dip, (caddr_t)global); 560 global->dip = dip; 561 global->initialized = B_FALSE; 562 563 global->init_state |= I8042_INIT_BASIC; 564 565 if (ddi_regs_map_setup(dip, 0, (caddr_t *)&global->io_addr, 566 (offset_t)0, (offset_t)0, &attr, &global->io_handle) 567 != DDI_SUCCESS) 568 goto fail; 569 570 global->init_state |= I8042_INIT_REGS_MAPPED; 571 572 /* 573 * Get the number of interrupts for this nexus 574 */ 575 if (ddi_dev_nintrs(dip, &global->nintrs) == DDI_FAILURE) 576 goto fail; 577 578 #ifdef __sparc 579 if ((i8042_polled_mode || i8042_is_polling_platform()) && 580 !i8042_force_interrupt_mode) { 581 /* 582 * If we're on a platform that has known 583 * interrupt issues with the keyboard/mouse, 584 * use polled mode. 585 */ 586 i8042_polled_mode = B_TRUE; 587 global->nintrs = 0; 588 } else if (global->nintrs == 0) { 589 /* 590 * If there are no interrupts on the i8042 node, 591 * we may be on a brain-dead platform that only 592 * has interrupts properties on i8042's children 593 * (e.g. some UltraII-based boards) 594 * In this case, scan first-level children, and 595 * build a list of interrupts that each child uses, 596 * then create an `interrupts' property on the nexus node 597 * that contains the interrupts used by all children 598 */ 599 if (i8042_build_interrupts_property(dip) == DDI_FAILURE || 600 ddi_dev_nintrs(dip, &global->nintrs) == DDI_FAILURE || 601 global->nintrs == 0) { 602 cmn_err(CE_WARN, "i8042#%d: No interrupts defined!", 603 ddi_get_instance(global->dip)); 604 goto fail; 605 } 606 } 607 #else 608 if (global->nintrs == 0) { 609 cmn_err(CE_WARN, "i8042#%d: No interrupts defined!", 610 ddi_get_instance(global->dip)); 611 goto fail; 612 } 613 #endif 614 615 if (global->nintrs > MAX_INTERRUPTS) 616 global->nintrs = MAX_INTERRUPTS; 617 618 if (global->nintrs > 0) { 619 global->iblock_cookies = kmem_zalloc(global->nintrs * 620 sizeof (ddi_iblock_cookie_t), KM_NOSLEEP); 621 622 for (i = 0; i < global->nintrs; i++) { 623 if (ddi_get_iblock_cookie(dip, i, 624 &global->iblock_cookies[i]) != DDI_SUCCESS) 625 goto fail; 626 } 627 } else 628 global->iblock_cookies = NULL; 629 630 mutex_init(&global->i8042_mutex, NULL, MUTEX_DRIVER, 631 (global->nintrs > 0) ? global->iblock_cookies[0] : NULL); 632 633 mutex_init(&global->i8042_out_mutex, NULL, MUTEX_DRIVER, NULL); 634 635 for (which_port = 0; which_port < NUM_PORTS; ++which_port) { 636 port = &global->i8042_ports[which_port]; 637 port->initialized = B_FALSE; 638 port->i8042_global = global; 639 port->which = which_port; 640 #if defined(USE_SOFT_INTRS) 641 port->soft_hdl = 0; 642 #else 643 /* 644 * Assume that the interrupt block cookie for port <n> 645 * is iblock_cookies[<n>] (a 1:1 mapping). If there are not 646 * enough interrupts to cover the number of ports, use 647 * the cookie from interrupt 0. 648 */ 649 if (global->nintrs > 0) 650 mutex_init(&port->intr_mutex, NULL, MUTEX_DRIVER, 651 global->iblock_cookies[(which_port < global->nintrs) 652 ? which_port : 0]); 653 else 654 mutex_init(&port->intr_mutex, NULL, MUTEX_DRIVER, NULL); 655 656 #endif 657 } 658 659 global->init_state |= I8042_INIT_MUTEXES; 660 661 /* 662 * Disable input and interrupts from both the main and aux ports. 663 * 664 * It is difficult if not impossible to read the command byte in 665 * a completely clean way. Reading the command byte may cause 666 * an interrupt, and there is no way to suppress interrupts without 667 * writing the command byte. On a PC we might rely on the fact 668 * that IRQ 1 is disabled and guaranteed not shared, but on 669 * other platforms the interrupt line might be shared and so 670 * causing an interrupt could be bad. 671 * 672 * Since we can't read the command byte and update it, we 673 * just set it to static values. 674 */ 675 i8042_write_command_byte(global, I8042_CMD_DISABLE_ALL); 676 677 global->init_state &= ~I8042_INIT_INTRS_ENABLED; 678 679 /* Discard any junk data that may have been left around */ 680 if (i8042_purge_outbuf(global) != 0) 681 goto fail; 682 683 /* 684 * Assume the number of interrupts is less that the number of 685 * bits in the variable used to keep track of which interrupt 686 * was added. 687 */ 688 ASSERT(global->nintrs <= (sizeof (global->intrs_added) * NBBY)); 689 690 for (i = 0; i < global->nintrs; i++) { 691 /* 692 * The 8042 handles all interrupts, because all 693 * device access goes through the same I/O addresses. 694 */ 695 if (ddi_add_intr(dip, i, 696 (ddi_iblock_cookie_t *)NULL, 697 (ddi_idevice_cookie_t *)NULL, 698 i8042_intr, (caddr_t)global) != DDI_SUCCESS) 699 goto fail; 700 701 global->intrs_added |= (1 << i); 702 } 703 704 global->initialized = B_TRUE; 705 706 /* 707 * Enable the main and aux data ports and interrupts 708 */ 709 i8042_write_command_byte(global, I8042_CMD_ENABLE_ALL); 710 global->init_state |= I8042_INIT_INTRS_ENABLED; 711 712 #ifdef __sparc 713 if (i8042_polled_mode) { 714 /* 715 * Do not allow anyone to set the polling interval 716 * to an interval more frequent than I8042_MIN_POLL_INTERVAL -- 717 * it could hose the system. 718 */ 719 interval = i8042_poll_interval; 720 if (interval < I8042_MIN_POLL_INTERVAL) 721 interval = I8042_MIN_POLL_INTERVAL; 722 i8042_fast_poll_interval = interval; 723 i8042_slow_poll_interval = interval << 3; 724 725 global->timeout_id = timeout(i8042_timeout, global, 726 drv_usectohz(i8042_slow_poll_interval)); 727 } 728 #endif 729 730 return (DDI_SUCCESS); 731 732 fail: 733 /* cleanup will succeed because no children have attached yet */ 734 (void) i8042_cleanup(global); 735 return (DDI_FAILURE); 736 } 737 738 /*ARGSUSED*/ 739 static int 740 i8042_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 741 { 742 struct i8042 *global = (struct i8042 *)ddi_get_driver_private(dip); 743 744 ASSERT(global != NULL); 745 746 switch (cmd) { 747 case DDI_SUSPEND: 748 /* 749 * Do not disable the keyboard controller for x86 suspend, as 750 * the keyboard can be used to bring the system out of 751 * suspend. 752 */ 753 #ifdef __sparc 754 /* Disable interrupts and controller devices before suspend */ 755 i8042_write_command_byte(global, I8042_CMD_DISABLE_ALL); 756 #endif 757 return (DDI_SUCCESS); 758 759 case DDI_DETACH: 760 /* DETACH can only succeed if cleanup succeeds */ 761 return (i8042_cleanup(global)); 762 763 default: 764 return (DDI_FAILURE); 765 } 766 } 767 768 /* 769 * The primary interface to us from our children is via virtual registers. 770 * This is the entry point that allows our children to "map" these 771 * virtual registers. 772 */ 773 static int 774 i8042_map( 775 dev_info_t *dip, 776 dev_info_t *rdip, 777 ddi_map_req_t *mp, 778 off_t offset, 779 off_t len, 780 caddr_t *addrp) 781 { 782 struct i8042_port *port; 783 struct i8042 *global; 784 enum i8042_ports which_port; 785 int *iprop; 786 unsigned int iprop_len; 787 int rnumber; 788 ddi_acc_hdl_t *handle; 789 ddi_acc_impl_t *ap; 790 791 global = ddi_get_driver_private(dip); 792 793 switch (mp->map_type) { 794 case DDI_MT_REGSPEC: 795 which_port = *(int *)mp->map_obj.rp; 796 break; 797 798 case DDI_MT_RNUMBER: 799 rnumber = mp->map_obj.rnumber; 800 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, rdip, 801 DDI_PROP_DONTPASS, "reg", &iprop, &iprop_len) != 802 DDI_SUCCESS) { 803 #if defined(DEBUG) 804 cmn_err(CE_WARN, "%s #%d: Missing 'reg' on %s@%s", 805 DRIVER_NAME(dip), ddi_get_instance(dip), 806 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 807 #endif 808 return (DDI_FAILURE); 809 } 810 #if defined(DEBUG) 811 if (iprop_len != 1) { 812 cmn_err(CE_WARN, "%s #%d: Malformed 'reg' on %s@%s", 813 DRIVER_NAME(dip), ddi_get_instance(dip), 814 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 815 return (DDI_FAILURE); 816 } 817 if (rnumber < 0 || rnumber >= iprop_len) { 818 cmn_err(CE_WARN, "%s #%d: bad map request for %s@%s", 819 DRIVER_NAME(dip), ddi_get_instance(dip), 820 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 821 return (DDI_FAILURE); 822 } 823 #endif 824 which_port = iprop[rnumber]; 825 ddi_prop_free((void *)iprop); 826 #if defined(DEBUG) 827 if (which_port != MAIN_PORT && which_port != AUX_PORT) { 828 cmn_err(CE_WARN, 829 "%s #%d: bad 'reg' value %d on %s@%s", 830 DRIVER_NAME(dip), ddi_get_instance(dip), 831 which_port, 832 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 833 return (DDI_FAILURE); 834 } 835 #endif 836 break; 837 838 default: 839 #if defined(DEBUG) 840 cmn_err(CE_WARN, "%s #%d: unknown map type %d for %s@%s", 841 DRIVER_NAME(dip), ddi_get_instance(dip), 842 mp->map_type, 843 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 844 #endif 845 return (DDI_FAILURE); 846 } 847 848 #if defined(DEBUG) 849 if (offset != 0 || len != 0) { 850 cmn_err(CE_WARN, 851 "%s #%d: partial mapping attempt for %s@%s ignored", 852 DRIVER_NAME(dip), ddi_get_instance(dip), 853 ddi_node_name(rdip), ddi_get_name_addr(rdip)); 854 } 855 #endif 856 857 port = &global->i8042_ports[which_port]; 858 859 switch (mp->map_op) { 860 case DDI_MO_MAP_LOCKED: 861 #if defined(USE_SOFT_INTRS) 862 port->soft_intr_enabled = B_FALSE; 863 #else 864 port->intr_func = NULL; 865 #endif 866 port->wptr = 0; 867 port->rptr = 0; 868 port->dip = dip; 869 port->inumber = 0; 870 port->initialized = B_TRUE; 871 872 handle = mp->map_handlep; 873 handle->ah_bus_private = port; 874 handle->ah_addr = 0; 875 ap = (ddi_acc_impl_t *)handle->ah_platform_private; 876 /* 877 * Only single get/put 8 is supported on this "bus". 878 */ 879 ap->ahi_put8 = i8042_put8; 880 ap->ahi_get8 = i8042_get8; 881 ap->ahi_put16 = NULL; 882 ap->ahi_get16 = NULL; 883 ap->ahi_put32 = NULL; 884 ap->ahi_get32 = NULL; 885 ap->ahi_put64 = NULL; 886 ap->ahi_get64 = NULL; 887 ap->ahi_rep_put8 = NULL; 888 ap->ahi_rep_get8 = NULL; 889 ap->ahi_rep_put16 = NULL; 890 ap->ahi_rep_get16 = NULL; 891 ap->ahi_rep_put32 = NULL; 892 ap->ahi_rep_get32 = NULL; 893 ap->ahi_rep_put64 = NULL; 894 ap->ahi_rep_get64 = NULL; 895 *addrp = 0; 896 return (DDI_SUCCESS); 897 898 case DDI_MO_UNMAP: 899 port->initialized = B_FALSE; 900 return (DDI_SUCCESS); 901 902 default: 903 cmn_err(CE_WARN, "%s: map operation %d not supported", 904 DRIVER_NAME(dip), mp->map_op); 905 return (DDI_FAILURE); 906 } 907 } 908 909 #ifdef __sparc 910 static void 911 i8042_timeout(void *arg) 912 { 913 struct i8042 *i8042_p = (struct i8042 *)arg; 914 int interval; 915 916 /* 917 * Allow the polling speed to be changed on the fly -- 918 * catch it here and update the intervals used. 919 */ 920 if (i8042_fast_poll_interval != i8042_poll_interval) { 921 interval = i8042_poll_interval; 922 if (interval < I8042_MIN_POLL_INTERVAL) 923 interval = I8042_MIN_POLL_INTERVAL; 924 i8042_fast_poll_interval = interval; 925 i8042_slow_poll_interval = interval << 3; 926 } 927 928 /* 929 * If the ISR returned true, start polling at a faster rate to 930 * increate responsiveness. Once the keyboard or mouse go idle, 931 * the ISR will return UNCLAIMED, and we'll go back to the slower 932 * polling rate. This gives some positive hysteresis (but not 933 * negative, since we go back to the slower polling interval after 934 * only one UNCLAIMED). This has shown to be responsive enough, 935 * even for fast typers. 936 */ 937 interval = (i8042_intr((caddr_t)i8042_p) == DDI_INTR_CLAIMED) ? 938 i8042_fast_poll_interval : i8042_slow_poll_interval; 939 940 if (i8042_polled_mode) 941 i8042_p->timeout_id = timeout(i8042_timeout, arg, 942 drv_usectohz(interval)); 943 else 944 i8042_p->timeout_id = 0; 945 } 946 #endif 947 948 /* 949 * i8042 hardware interrupt routine. Called for both main and aux port 950 * interrupts. 951 */ 952 static unsigned int 953 i8042_intr(caddr_t arg) 954 { 955 struct i8042 *global = (struct i8042 *)arg; 956 enum i8042_ports which_port; 957 unsigned char stat; 958 unsigned char byte; 959 int new_wptr; 960 struct i8042_port *port; 961 962 mutex_enter(&global->i8042_mutex); 963 964 stat = ddi_get8(global->io_handle, global->io_addr + I8042_STAT); 965 966 if (! (stat & I8042_STAT_OUTBF)) { 967 ++i8042_unclaimed_interrupts; 968 mutex_exit(&global->i8042_mutex); 969 return (DDI_INTR_UNCLAIMED); 970 } 971 972 byte = ddi_get8(global->io_handle, global->io_addr + I8042_DATA); 973 974 which_port = (stat & I8042_STAT_AUXBF) ? AUX_PORT : MAIN_PORT; 975 976 port = &global->i8042_ports[which_port]; 977 978 if (! port->initialized) { 979 mutex_exit(&global->i8042_mutex); 980 return (DDI_INTR_CLAIMED); 981 } 982 983 new_wptr = (port->wptr + 1) % BUFSIZ; 984 if (new_wptr == port->rptr) { 985 port->overruns++; 986 #if defined(DEBUG) 987 if (port->overruns % 50 == 1) { 988 cmn_err(CE_WARN, "i8042/%d: %d overruns\n", 989 which_port, port->overruns); 990 } 991 #endif 992 mutex_exit(&global->i8042_mutex); 993 return (DDI_INTR_CLAIMED); 994 } 995 996 port->buf[port->wptr] = byte; 997 port->wptr = new_wptr; 998 999 #if defined(USE_SOFT_INTRS) 1000 if (port->soft_intr_enabled) 1001 (void) ddi_intr_trigger_softint(port->soft_hdl, 1002 port->intr_arg2); 1003 #endif 1004 1005 mutex_exit(&global->i8042_mutex); 1006 1007 #if !defined(USE_SOFT_INTRS) 1008 mutex_enter(&port->intr_mutex); 1009 if (port->intr_func != NULL) 1010 port->intr_func(port->intr_arg1, NULL); 1011 mutex_exit(&port->intr_mutex); 1012 #endif 1013 1014 return (DDI_INTR_CLAIMED); 1015 } 1016 1017 static void 1018 i8042_write_command_byte(struct i8042 *global, unsigned char cb) 1019 { 1020 mutex_enter(&global->i8042_out_mutex); 1021 i8042_send(global, I8042_CMD, I8042_CMD_WCB); 1022 i8042_send(global, I8042_DATA, cb); 1023 mutex_exit(&global->i8042_out_mutex); 1024 } 1025 1026 /* 1027 * Send a byte to either the i8042 command or data register, depending on 1028 * the argument. 1029 */ 1030 static void 1031 i8042_send(struct i8042 *global, int reg, unsigned char val) 1032 { 1033 uint8_t stat; 1034 int tries = 0; 1035 1036 /* 1037 * First, wait for the i8042 to be ready to accept data. 1038 */ 1039 /*CONSTANTCONDITION*/ 1040 while (1) { 1041 stat = ddi_get8(global->io_handle, 1042 global->io_addr + I8042_STAT); 1043 1044 if ((stat & I8042_STAT_INBF) == 0) { 1045 ddi_put8(global->io_handle, global->io_addr+reg, val); 1046 break; 1047 } 1048 1049 /* Don't wait unless we're going to check again */ 1050 if (++tries >= max_wait_iterations) 1051 break; 1052 else 1053 drv_usecwait(USECS_PER_WAIT); 1054 } 1055 1056 #ifdef DEBUG 1057 if (tries >= MAX_WAIT_ITERATIONS) 1058 cmn_err(CE_WARN, "i8042_send: timeout!"); 1059 #endif 1060 } 1061 1062 /* 1063 * Here's the interface to the virtual registers on the device. 1064 * 1065 * Normal interrupt-driven I/O: 1066 * 1067 * I8042_INT_INPUT_AVAIL (r/o) 1068 * Interrupt mode input bytes available? Zero = No. 1069 * I8042_INT_INPUT_DATA (r/o) 1070 * Fetch interrupt mode input byte. 1071 * I8042_INT_OUTPUT_DATA (w/o) 1072 * Interrupt mode output byte. 1073 * 1074 * Polled I/O, used by (e.g.) kmdb, when normal system services are 1075 * unavailable: 1076 * 1077 * I8042_POLL_INPUT_AVAIL (r/o) 1078 * Polled mode input bytes available? Zero = No. 1079 * I8042_POLL_INPUT_DATA (r/o) 1080 * Polled mode input byte. 1081 * I8042_POLL_OUTPUT_DATA (w/o) 1082 * Polled mode output byte. 1083 * 1084 * Note that in polled mode we cannot use cmn_err; only prom_printf is safe. 1085 */ 1086 static uint8_t 1087 i8042_get8(ddi_acc_impl_t *handlep, uint8_t *addr) 1088 { 1089 struct i8042_port *port; 1090 struct i8042 *global; 1091 uint8_t ret; 1092 ddi_acc_hdl_t *h; 1093 uint8_t stat; 1094 1095 h = (ddi_acc_hdl_t *)handlep; 1096 1097 port = (struct i8042_port *)h->ah_bus_private; 1098 global = port->i8042_global; 1099 1100 switch ((uintptr_t)addr) { 1101 case I8042_INT_INPUT_AVAIL: 1102 mutex_enter(&global->i8042_mutex); 1103 ret = port->rptr != port->wptr; 1104 mutex_exit(&global->i8042_mutex); 1105 return (ret); 1106 1107 case I8042_INT_INPUT_DATA: 1108 mutex_enter(&global->i8042_mutex); 1109 1110 if (port->rptr != port->wptr) { 1111 ret = port->buf[port->rptr]; 1112 port->rptr = (port->rptr + 1) % BUFSIZ; 1113 } else { 1114 #if defined(DEBUG) 1115 cmn_err(CE_WARN, 1116 "i8042: Tried to read from empty buffer"); 1117 #endif 1118 ret = 0; 1119 } 1120 1121 1122 mutex_exit(&global->i8042_mutex); 1123 1124 break; 1125 1126 #if defined(DEBUG) 1127 case I8042_INT_OUTPUT_DATA: 1128 case I8042_POLL_OUTPUT_DATA: 1129 cmn_err(CE_WARN, "i8042: read of write-only register 0x%p", 1130 (void *)addr); 1131 ret = 0; 1132 break; 1133 #endif 1134 1135 case I8042_POLL_INPUT_AVAIL: 1136 if (port->rptr != port->wptr) 1137 return (B_TRUE); 1138 for (;;) { 1139 stat = ddi_get8(global->io_handle, 1140 global->io_addr + I8042_STAT); 1141 if ((stat & I8042_STAT_OUTBF) == 0) 1142 return (B_FALSE); 1143 switch (port->which) { 1144 case MAIN_PORT: 1145 if ((stat & I8042_STAT_AUXBF) == 0) 1146 return (B_TRUE); 1147 break; 1148 case AUX_PORT: 1149 if ((stat & I8042_STAT_AUXBF) != 0) 1150 return (B_TRUE); 1151 break; 1152 default: 1153 cmn_err(CE_WARN, "data from unknown port: %d", 1154 port->which); 1155 } 1156 /* 1157 * Data for wrong port pending; discard it. 1158 */ 1159 (void) ddi_get8(global->io_handle, 1160 global->io_addr + I8042_DATA); 1161 } 1162 1163 /* NOTREACHED */ 1164 1165 case I8042_POLL_INPUT_DATA: 1166 if (port->rptr != port->wptr) { 1167 ret = port->buf[port->rptr]; 1168 port->rptr = (port->rptr + 1) % BUFSIZ; 1169 return (ret); 1170 } 1171 1172 stat = ddi_get8(global->io_handle, 1173 global->io_addr + I8042_STAT); 1174 if ((stat & I8042_STAT_OUTBF) == 0) { 1175 #if defined(DEBUG) 1176 prom_printf("I8042_POLL_INPUT_DATA: no data!\n"); 1177 #endif 1178 return (0); 1179 } 1180 ret = ddi_get8(global->io_handle, 1181 global->io_addr + I8042_DATA); 1182 switch (port->which) { 1183 case MAIN_PORT: 1184 if ((stat & I8042_STAT_AUXBF) == 0) 1185 return (ret); 1186 break; 1187 case AUX_PORT: 1188 if ((stat & I8042_STAT_AUXBF) != 0) 1189 return (ret); 1190 break; 1191 } 1192 #if defined(DEBUG) 1193 prom_printf("I8042_POLL_INPUT_DATA: data for wrong port!\n"); 1194 #endif 1195 return (0); 1196 1197 default: 1198 #if defined(DEBUG) 1199 cmn_err(CE_WARN, "i8042: read of undefined register 0x%p", 1200 (void *)addr); 1201 #endif 1202 ret = 0; 1203 break; 1204 } 1205 return (ret); 1206 } 1207 1208 static void 1209 i8042_put8(ddi_acc_impl_t *handlep, uint8_t *addr, uint8_t value) 1210 { 1211 struct i8042_port *port; 1212 struct i8042 *global; 1213 ddi_acc_hdl_t *h; 1214 1215 h = (ddi_acc_hdl_t *)handlep; 1216 1217 port = (struct i8042_port *)h->ah_bus_private; 1218 global = port->i8042_global; 1219 1220 switch ((uintptr_t)addr) { 1221 case I8042_INT_OUTPUT_DATA: 1222 case I8042_POLL_OUTPUT_DATA: 1223 1224 if ((uintptr_t)addr == I8042_INT_OUTPUT_DATA) 1225 mutex_enter(&global->i8042_out_mutex); 1226 1227 if (port->which == AUX_PORT) 1228 i8042_send(global, I8042_CMD, I8042_CMD_WRITE_AUX); 1229 1230 i8042_send(global, I8042_DATA, value); 1231 1232 if ((uintptr_t)addr == I8042_INT_OUTPUT_DATA) 1233 mutex_exit(&global->i8042_out_mutex); 1234 break; 1235 1236 1237 #if defined(DEBUG) 1238 case I8042_INT_INPUT_AVAIL: 1239 case I8042_INT_INPUT_DATA: 1240 case I8042_POLL_INPUT_AVAIL: 1241 case I8042_POLL_INPUT_DATA: 1242 cmn_err(CE_WARN, "i8042: write of read-only register 0x%p", 1243 (void *)addr); 1244 break; 1245 1246 default: 1247 cmn_err(CE_WARN, "i8042: read of undefined register 0x%p", 1248 (void *)addr); 1249 break; 1250 #endif 1251 } 1252 } 1253 1254 1255 /* ARGSUSED */ 1256 static int 1257 i8042_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1258 ddi_intr_handle_impl_t *hdlp, void *result) 1259 { 1260 struct i8042_port *port; 1261 #if defined(USE_SOFT_INTRS) 1262 struct i8042 *global; 1263 int ret; 1264 #endif 1265 1266 switch (intr_op) { 1267 case DDI_INTROP_SUPPORTED_TYPES: 1268 *(int *)result = DDI_INTR_TYPE_FIXED; 1269 break; 1270 case DDI_INTROP_GETCAP: 1271 if (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result) 1272 == DDI_FAILURE) 1273 *(int *)result = 0; 1274 break; 1275 case DDI_INTROP_NINTRS: 1276 case DDI_INTROP_NAVAIL: 1277 *(int *)result = 1; 1278 break; 1279 case DDI_INTROP_ALLOC: 1280 *(int *)result = hdlp->ih_scratch1; 1281 break; 1282 case DDI_INTROP_FREE: 1283 break; 1284 case DDI_INTROP_GETPRI: 1285 /* Hard coding it for x86 */ 1286 *(int *)result = 5; 1287 break; 1288 case DDI_INTROP_ADDISR: 1289 port = ddi_get_parent_data(rdip); 1290 1291 #if defined(USE_SOFT_INTRS) 1292 global = port->i8042_global; 1293 ret = ddi_intr_add_softint(rdip, &port->soft_hdl, 1294 I8042_SOFTINT_PRI, hdlp->ih_cb_func, hdlp->ih_cb_arg1); 1295 1296 if (ret != DDI_SUCCESS) { 1297 #if defined(DEBUG) 1298 cmn_err(CE_WARN, "%s #%d: " 1299 "Cannot add soft interrupt for %s #%d, ret=%d.", 1300 DRIVER_NAME(dip), ddi_get_instance(dip), 1301 DRIVER_NAME(rdip), ddi_get_instance(rdip), ret); 1302 #endif /* defined(DEBUG) */ 1303 return (ret); 1304 } 1305 1306 #else /* defined(USE_SOFT_INTRS) */ 1307 mutex_enter(&port->intr_mutex); 1308 port->intr_func = hdlp->ih_cb_func; 1309 port->intr_arg1 = hdlp->ih_cb_arg1; 1310 port->intr_arg2 = hdlp->ih_cb_arg2; 1311 mutex_exit(&port->intr_mutex); 1312 #endif /* defined(USE_SOFT_INTRS) */ 1313 break; 1314 case DDI_INTROP_REMISR: 1315 port = ddi_get_parent_data(rdip); 1316 1317 #if defined(USE_SOFT_INTRS) 1318 global = port->i8042_global; 1319 mutex_enter(&global->i8042_mutex); 1320 port->soft_hdl = 0; 1321 mutex_exit(&global->i8042_mutex); 1322 #else /* defined(USE_SOFT_INTRS) */ 1323 mutex_enter(&port->intr_mutex); 1324 port->intr_func = NULL; 1325 mutex_exit(&port->intr_mutex); 1326 #endif /* defined(USE_SOFT_INTRS) */ 1327 break; 1328 case DDI_INTROP_ENABLE: 1329 port = ddi_get_parent_data(rdip); 1330 #if defined(USE_SOFT_INTRS) 1331 global = port->i8042_global; 1332 mutex_enter(&global->i8042_mutex); 1333 port->soft_intr_enabled = B_TRUE; 1334 if (port->wptr != port->rptr) 1335 (void) ddi_intr_trigger_softint(port->soft_hdl, 1336 port->intr_arg2); 1337 mutex_exit(&global->i8042_mutex); 1338 #else /* defined(USE_SOFT_INTRS) */ 1339 mutex_enter(&port->intr_mutex); 1340 if (port->wptr != port->rptr) 1341 port->intr_func(port->intr_arg1, port->intr_arg2); 1342 mutex_exit(&port->intr_mutex); 1343 #endif /* defined(USE_SOFT_INTRS) */ 1344 break; 1345 case DDI_INTROP_DISABLE: 1346 #if defined(USE_SOFT_INTRS) 1347 port = ddi_get_parent_data(rdip); 1348 global = port->i8042_global; 1349 mutex_enter(&global->i8042_mutex); 1350 port->soft_intr_enabled = B_FALSE; 1351 (void) ddi_intr_remove_softint(port->soft_hdl); 1352 mutex_exit(&global->i8042_mutex); 1353 #endif /* defined(USE_SOFT_INTRS) */ 1354 break; 1355 default: 1356 return (DDI_FAILURE); 1357 } 1358 1359 return (DDI_SUCCESS); 1360 } 1361 1362 static int 1363 i8042_ctlops(dev_info_t *dip, dev_info_t *rdip, 1364 ddi_ctl_enum_t op, void *arg, void *result) 1365 { 1366 int *iprop; 1367 unsigned int iprop_len; 1368 int which_port; 1369 char name[16]; 1370 struct i8042 *global; 1371 dev_info_t *child; 1372 1373 global = ddi_get_driver_private(dip); 1374 1375 switch (op) { 1376 case DDI_CTLOPS_INITCHILD: 1377 child = (dev_info_t *)arg; 1378 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, 1379 DDI_PROP_DONTPASS, "reg", &iprop, &iprop_len) != 1380 DDI_SUCCESS) { 1381 #if defined(DEBUG) 1382 cmn_err(CE_WARN, "%s #%d: Missing 'reg' on %s@???", 1383 DRIVER_NAME(dip), ddi_get_instance(dip), 1384 ddi_node_name(child)); 1385 #endif 1386 return (DDI_FAILURE); 1387 } 1388 which_port = iprop[0]; 1389 ddi_prop_free((void *)iprop); 1390 1391 (void) sprintf(name, "%d", which_port); 1392 ddi_set_name_addr(child, name); 1393 ddi_set_parent_data(child, 1394 (caddr_t)&global->i8042_ports[which_port]); 1395 return (DDI_SUCCESS); 1396 1397 case DDI_CTLOPS_UNINITCHILD: 1398 child = (dev_info_t *)arg; 1399 ddi_set_name_addr(child, NULL); 1400 ddi_set_parent_data(child, NULL); 1401 return (DDI_SUCCESS); 1402 1403 case DDI_CTLOPS_REPORTDEV: 1404 cmn_err(CE_CONT, "?8042 device: %s@%s, %s # %d\n", 1405 ddi_node_name(rdip), ddi_get_name_addr(rdip), 1406 DRIVER_NAME(rdip), ddi_get_instance(rdip)); 1407 return (DDI_SUCCESS); 1408 1409 default: 1410 return (ddi_ctlops(dip, rdip, op, arg, result)); 1411 } 1412 /* NOTREACHED */ 1413 } 1414 1415 #if defined(__i386) || defined(__amd64) 1416 static dev_info_t * 1417 i8042_devi_findchild_by_node_name(dev_info_t *pdip, char *nodename) 1418 { 1419 dev_info_t *child; 1420 1421 ASSERT(DEVI_BUSY_OWNED(pdip)); 1422 1423 if (nodename == NULL) { 1424 return ((dev_info_t *)NULL); 1425 } 1426 1427 for (child = ddi_get_child(pdip); child != NULL; 1428 child = ddi_get_next_sibling(child)) { 1429 1430 if (strcmp(ddi_node_name(child), nodename) == 0) 1431 break; 1432 } 1433 return (child); 1434 } 1435 1436 static void 1437 alloc_kb_mouse(dev_info_t *i8042_dip, int nodes_needed) 1438 { 1439 dev_info_t *xdip; 1440 int acpi_off = 0; 1441 char *acpi_prop; 1442 1443 /* don't alloc unless acpi is off */ 1444 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 1445 DDI_PROP_DONTPASS, "acpi-enum", &acpi_prop) == DDI_PROP_SUCCESS) { 1446 if (strcmp("off", acpi_prop) == 0) { 1447 acpi_off = 1; 1448 } 1449 ddi_prop_free(acpi_prop); 1450 } 1451 if (acpi_off == 0) { 1452 return; 1453 } 1454 1455 if (nodes_needed & I8042_MOUSE) { 1456 /* mouse */ 1457 ndi_devi_alloc_sleep(i8042_dip, "mouse", 1458 (pnode_t)DEVI_SID_NODEID, &xdip); 1459 (void) ndi_prop_update_int(DDI_DEV_T_NONE, xdip, 1460 "reg", 1); 1461 (void) ndi_prop_update_int(DDI_DEV_T_NONE, xdip, 1462 "interrupts", 2); 1463 (void) ndi_prop_update_string(DDI_DEV_T_NONE, xdip, 1464 "compatible", "pnpPNP,f03"); 1465 /* 1466 * The device_type property does not matter on SPARC. Retain it 1467 * on x86 for compatibility with the previous pseudo-prom. 1468 */ 1469 (void) ndi_prop_update_string(DDI_DEV_T_NONE, xdip, 1470 "device_type", "mouse"); 1471 (void) ndi_devi_bind_driver(xdip, 0); 1472 } 1473 1474 if (nodes_needed & I8042_KEYBOARD) { 1475 /* keyboard */ 1476 ndi_devi_alloc_sleep(i8042_dip, "keyboard", 1477 (pnode_t)DEVI_SID_NODEID, &xdip); 1478 (void) ndi_prop_update_int(DDI_DEV_T_NONE, xdip, 1479 "reg", 0); 1480 (void) ndi_prop_update_int(DDI_DEV_T_NONE, xdip, 1481 "interrupts", 1); 1482 (void) ndi_prop_update_string(DDI_DEV_T_NONE, xdip, 1483 "compatible", "pnpPNP,303"); 1484 (void) ndi_prop_update_string(DDI_DEV_T_NONE, xdip, 1485 "device_type", "keyboard"); 1486 (void) ndi_devi_bind_driver(xdip, 0); 1487 } 1488 } 1489 #endif 1490 1491 static int 1492 i8042_bus_config(dev_info_t *parent, uint_t flags, 1493 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 1494 { 1495 #if defined(__i386) || defined(__amd64) 1496 int nodes_needed = 0; 1497 int circ; 1498 1499 /* 1500 * On x86 systems, if ACPI is disabled, the only way the 1501 * keyboard and mouse can be enumerated is by creating them 1502 * manually. The following code searches for the existence of 1503 * the keyboard and mouse nodes and creates them if they are not 1504 * found. 1505 */ 1506 ndi_devi_enter(parent, &circ); 1507 if (i8042_devi_findchild_by_node_name(parent, "keyboard") == NULL) 1508 nodes_needed |= I8042_KEYBOARD; 1509 if (i8042_devi_findchild_by_node_name(parent, "mouse") == NULL) 1510 nodes_needed |= I8042_MOUSE; 1511 1512 /* If the mouse and keyboard nodes do not already exist, create them */ 1513 if (nodes_needed) 1514 alloc_kb_mouse(parent, nodes_needed); 1515 ndi_devi_exit(parent, circ); 1516 #endif 1517 return (ndi_busop_bus_config(parent, flags, op, arg, childp, 0)); 1518 } 1519 1520 static int 1521 i8042_bus_unconfig(dev_info_t *parent, uint_t flags, 1522 ddi_bus_config_op_t op, void *arg) 1523 { 1524 /* 1525 * The NDI_UNCONFIG flag allows the reference count on this nexus to be 1526 * decremented when children's drivers are unloaded, enabling the nexus 1527 * itself to be unloaded. 1528 */ 1529 return (ndi_busop_bus_unconfig(parent, flags | NDI_UNCONFIG, op, arg)); 1530 } 1531 1532 #ifdef __sparc 1533 static int 1534 i8042_build_interrupts_property(dev_info_t *dip) 1535 { 1536 dev_info_t *child = ddi_get_child(dip); 1537 uint_t nintr; 1538 int *intrs = NULL; 1539 int interrupts[MAX_INTERRUPTS]; 1540 int i = 0; 1541 1542 /* Walk the children of this node, scanning for interrupts properties */ 1543 while (child != NULL && i < MAX_INTERRUPTS) { 1544 1545 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, 1546 DDI_PROP_DONTPASS, "interrupts", &intrs, &nintr) 1547 == DDI_PROP_SUCCESS && intrs != NULL) { 1548 1549 while (nintr > 0 && i < MAX_INTERRUPTS) { 1550 interrupts[i++] = intrs[--nintr]; 1551 } 1552 ddi_prop_free(intrs); 1553 } 1554 1555 child = ddi_get_next_sibling(child); 1556 } 1557 1558 if (ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, "interrupts", 1559 interrupts, i) != DDI_PROP_SUCCESS) { 1560 1561 return (DDI_FAILURE); 1562 } 1563 1564 /* 1565 * Oh, the humanity. On the platforms on which we need to 1566 * synthesize an interrupts property, we ALSO need to update the 1567 * device_type property, and set it to "serial" in order for the 1568 * correct interrupt PIL to be chosen by the framework. 1569 */ 1570 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, "device_type", "serial") 1571 != DDI_PROP_SUCCESS) { 1572 1573 return (DDI_FAILURE); 1574 } 1575 1576 return (DDI_SUCCESS); 1577 } 1578 1579 static boolean_t 1580 i8042_is_polling_platform(void) 1581 { 1582 /* 1583 * Returns true if this platform is one of the platforms 1584 * that has interrupt issues with the PS/2 keyboard/mouse. 1585 */ 1586 if (PLATFORM_MATCH("SUNW,UltraAX-")) 1587 return (B_TRUE); 1588 else 1589 return (B_FALSE); 1590 } 1591 #endif 1592