1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved. 14 * Copyright (c) 2017, Joyent, Inc. 15 * Copyright 2017 Tegile Systems, Inc. All rights reserved. 16 */ 17 18 /* 19 * Please see i40e_main.c for an introduction to the device driver, its layout, 20 * and more. 21 */ 22 23 #ifndef _I40E_SW_H 24 #define _I40E_SW_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include <sys/types.h> 31 #include <sys/conf.h> 32 #include <sys/debug.h> 33 #include <sys/stropts.h> 34 #include <sys/stream.h> 35 #include <sys/strsun.h> 36 #include <sys/strlog.h> 37 #include <sys/kmem.h> 38 #include <sys/stat.h> 39 #include <sys/kstat.h> 40 #include <sys/modctl.h> 41 #include <sys/errno.h> 42 #include <sys/dlpi.h> 43 #include <sys/mac_provider.h> 44 #include <sys/mac_ether.h> 45 #include <sys/vlan.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/pci.h> 49 #include <sys/pcie.h> 50 #include <sys/sdt.h> 51 #include <sys/ethernet.h> 52 #include <sys/pattr.h> 53 #include <sys/strsubr.h> 54 #include <sys/netlb.h> 55 #include <sys/random.h> 56 #include <inet/common.h> 57 #include <inet/tcp.h> 58 #include <inet/ip.h> 59 #include <inet/mi.h> 60 #include <inet/nd.h> 61 #include <netinet/udp.h> 62 #include <netinet/sctp.h> 63 #include <sys/bitmap.h> 64 #include <sys/cpuvar.h> 65 #include <sys/ddifm.h> 66 #include <sys/fm/protocol.h> 67 #include <sys/fm/util.h> 68 #include <sys/disp.h> 69 #include <sys/fm/io/ddi.h> 70 #include <sys/list.h> 71 #include <sys/debug.h> 72 #include <sys/sdt.h> 73 #include "i40e_type.h" 74 #include "i40e_osdep.h" 75 #include "i40e_prototype.h" 76 #include "i40e_xregs.h" 77 78 #define I40E_MODULE_NAME "i40e" 79 80 #define I40E_ADAPTER_REGSET 1 81 82 /* 83 * Configuration constants. Note that the hardware defines a minimum bound of 32 84 * descriptors and requires that the programming of the descriptor lengths be 85 * aligned in units of 32 descriptors. 86 */ 87 #define I40E_MIN_TX_RING_SIZE 64 88 #define I40E_MAX_TX_RING_SIZE 4096 89 #define I40E_DEF_TX_RING_SIZE 1024 90 91 #define I40E_MIN_RX_RING_SIZE 64 92 #define I40E_MAX_RX_RING_SIZE 4096 93 #define I40E_DEF_RX_RING_SIZE 1024 94 95 #define I40E_DESC_ALIGN 32 96 97 /* 98 * Sizes used for asynchronous processing of the adminq. We allocate a fixed 99 * size buffer for each instance of the device during attach time, rather than 100 * allocating and freeing one during interrupt processing. 101 * 102 * We also define the descriptor size of the admin queue here. 103 */ 104 #define I40E_ADMINQ_BUFSZ 4096 105 #define I40E_MAX_ADMINQ_SIZE 1024 106 #define I40E_DEF_ADMINQ_SIZE 256 107 108 /* 109 * Note, while the min and maximum values are based upon the sizing of the ring 110 * itself, the default is taken from ixgbe without much thought. It's basically 111 * been cargo culted. See i40e_transceiver.c for a bit more information. 112 */ 113 #define I40E_MIN_RX_LIMIT_PER_INTR 16 114 #define I40E_MAX_RX_LIMIT_PER_INTR 4096 115 #define I40E_DEF_RX_LIMIT_PER_INTR 256 116 117 /* 118 * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728. 119 * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN 120 * header size (18 bytes) to get the actual maximum frame we can use. If 121 * different adapters end up with different sizes, we should make this value a 122 * bit more dynamic. 123 */ 124 #define I40E_MAX_MTU 9706 125 #define I40E_MIN_MTU ETHERMIN 126 #define I40E_DEF_MTU ETHERMTU 127 128 /* 129 * Interrupt throttling related values. Interrupt throttling values are defined 130 * in two microsecond increments. Note that a value of zero basically says do no 131 * ITR activity. A helpful way to think about these is that setting the ITR to a 132 * value will allow a certain number of interrupts per second. 133 * 134 * Our default values for RX allow 20k interrupts per second while our default 135 * values for TX allow for 5k interrupts per second. For other class interrupts, 136 * we limit ourselves to a rate of 2k/s. 137 */ 138 #define I40E_MIN_ITR 0x0000 139 #define I40E_MAX_ITR 0x0FF0 140 #define I40E_DEF_RX_ITR 0x0019 141 #define I40E_DEF_TX_ITR 0x0064 142 #define I40E_DEF_OTHER_ITR 0x00FA 143 144 /* 145 * Indexes into the three ITR registers that we have. 146 */ 147 typedef enum i40e_itr_index { 148 I40E_ITR_INDEX_RX = 0x0, 149 I40E_ITR_INDEX_TX = 0x1, 150 I40E_ITR_INDEX_OTHER = 0x2, 151 I40E_ITR_INDEX_NONE = 0x3 152 } i40e_itr_index_t; 153 154 /* 155 * Table 1-5 of the PRM notes that LSO supports up to 256 KB. 156 */ 157 #define I40E_LSO_MAXLEN (256 * 1024) 158 159 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */ 160 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */ 161 162 /* 163 * All the other queue types for are defined by the common code. However, this 164 * is the constant to indicate that it's terminated. 165 */ 166 #define I40E_QUEUE_TYPE_EOL 0x7FF 167 168 /* 169 * See the comments in i40e_transceiver.c as to the purpose of this value and 170 * how it's used to ensure that the IP header is eventually aligned when it's 171 * received by the OS. 172 */ 173 #define I40E_BUF_IPHDR_ALIGNMENT 2 174 175 /* 176 * The XL710 controller has a limit of eight buffers being allowed to be used 177 * for the transmission of a single frame. This is defined in 8.4.1 - Transmit 178 * Packet in System Memory. 179 */ 180 #define I40E_TX_MAX_COOKIE 8 181 182 /* 183 * Sizing to determine the amount of available descriptors at which we'll 184 * consider ourselves blocked. Also, when we have these available, we'll then 185 * consider ourselves available to transmit to MAC again. Strictly speaking, the 186 * MAX is based on the ring size. The default sizing is based on ixgbe. 187 */ 188 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE 189 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH 190 191 /* 192 * Sizing for DMA thresholds. These are used to indicate whether or not we 193 * should perform a bcopy or a DMA binding of a given message block. The range 194 * allows for setting things such that we'll always do a bcopy (a high value) or 195 * always perform a DMA binding (a low value). 196 */ 197 #define I40E_MIN_RX_DMA_THRESH 0 198 #define I40E_DEF_RX_DMA_THRESH 256 199 #define I40E_MAX_RX_DMA_THRESH INT32_MAX 200 201 #define I40E_MIN_TX_DMA_THRESH 0 202 #define I40E_DEF_TX_DMA_THRESH 256 203 #define I40E_MAX_TX_DMA_THRESH INT32_MAX 204 205 /* 206 * Resource sizing counts. There are various aspects of hardware where we may 207 * have some variable number of elements that we need to handle. Such as the 208 * hardware capabilities and switch capacities. We cannot know a priori how many 209 * elements to do, so instead we take a starting guess and then will grow it up 210 * to an upper bound on a number of elements, to limit memory consumption in 211 * case of a hardware bug. 212 */ 213 #define I40E_HW_CAP_DEFAULT 40 214 #define I40E_SWITCH_CAP_DEFAULT 25 215 216 /* 217 * Host Memory Context related constants. 218 */ 219 #define I40E_HMC_RX_CTX_UNIT 128 220 #define I40E_HMC_RX_DBUFF_MIN 1024 221 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128) 222 #define I40E_HMC_RX_DTYPE_NOSPLIT 0 223 #define I40E_HMC_RX_DSIZE_32BYTE 1 224 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1 225 #define I40E_HMC_RX_FC_DISABLE 0 226 #define I40E_HMC_RX_L2TAGORDER 1 227 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0 228 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0 229 #define I40E_HMC_RX_TPH_DISABLE 0 230 #define I40E_HMC_RX_LOWRXQ_NOINTR 0 231 #define I40E_HMC_RX_PREFENA 1 232 233 #define I40E_HMC_TX_CTX_UNIT 128 234 #define I40E_HMC_TX_NEW_CONTEXT 1 235 #define I40E_HMC_TX_FC_DISABLE 0 236 #define I40E_HMC_TX_TS_DISABLE 0 237 #define I40E_HMC_TX_FD_DISABLE 0 238 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0 239 #define I40E_HMC_TX_WB_ENABLE 1 240 #define I40E_HMC_TX_TPH_DISABLE 0 241 242 /* 243 * Whenever we establish and create a VSI, we need to assign some number of 244 * queues that it's allowed to access from the PF. Because we only have a single 245 * VSI per PF at this time, we assign it all the queues. 246 * 247 * Many of the devices support what's called Data-center Bridging. Which is a 248 * feature that we don't have much use of at this time. However, we still need 249 * to fill in this information. We follow the guidance of the note in Table 7-80 250 * which talks about bytes 62-77. It says that if we don't want to assign 251 * anything to traffic classes, we should set the field to zero. Effectively 252 * this means that everything in the system is assigned to traffic class zero. 253 */ 254 #define I40E_ASSIGN_ALL_QUEUES 0 255 #define I40E_TRAFFIC_CLASS_NO_QUEUES 0 256 257 /* 258 * This defines the error mask that we care about from rx descriptors. Currently 259 * we're only concerned with the general errors and oversize errors. 260 */ 261 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \ 262 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)) 263 264 /* 265 * Property sizing macros for firmware versions, etc. They need to be large 266 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x. 267 */ 268 #define I40E_DDI_PROP_LEN 64 269 270 /* 271 * We currently consolidate some overrides that we use in the code here. These 272 * will be gone in the fullness of time, but as we're bringing up the device, 273 * this is what we use. 274 */ 275 #define I40E_GROUP_MAX 1 276 #define I40E_TRQPAIR_MAX 1 277 278 #define I40E_GROUP_NOMSIX 1 279 #define I40E_TRQPAIR_NOMSIX 1 280 281 /* 282 * It seems reasonable to cast this to void because the only reason that we 283 * should be getting a DDI_FAILURE is due to the fact that we specify addresses 284 * out of range. Because we specify no offset or address, it shouldn't happen. 285 */ 286 #ifdef DEBUG 287 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \ 288 (handle)->dmab_dma_handle, 0, 0, \ 289 (flag))) 290 #else /* !DEBUG */ 291 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \ 292 (handle)->dmab_dma_handle, 0, 0, \ 293 (flag))) 294 #endif /* DEBUG */ 295 296 /* 297 * Constants related to ring startup and teardown. These refer to the amount of 298 * time that we're willing to wait for a ring to spin up and spin down. 299 */ 300 #define I40E_RING_WAIT_NTRIES 10 301 #define I40E_RING_WAIT_PAUSE 10 /* ms */ 302 303 /* 304 * Printed Board Assembly (PBA) length. These are derived from Table 6-2. 305 */ 306 #define I40E_PBANUM_LENGTH 12 307 #define I40E_PBANUM_STRLEN 13 308 309 /* 310 * Define the maximum number of queues for a traffic class. These values come 311 * from the 'Number and offset of queue pairs per TCs' section of the 'Add VSI 312 * Command Buffer' table. For the 710 controller family this is table 7-62 313 * (r2.5) and for the 722 this is table 38-216 (r2.0). 314 */ 315 #define I40E_710_MAX_TC_QUEUES 64 316 #define I40E_722_MAX_TC_QUEUES 128 317 318 /* 319 * Define the size of the HLUT table size. The HLUT table can either be 128 or 320 * 512 bytes. We always set the table size to be 512 bytes in i40e_chip_start(). 321 * Note, this should not be confused with the common code's macro 322 * I40E_HASH_LUT_SIZE_512 which is the bit pattern needed to tell the card to 323 * use a 512 byte HLUT. 324 */ 325 #define I40E_HLUT_TABLE_SIZE 512 326 327 /* 328 * Bit flags for attach_progress 329 */ 330 typedef enum i40e_attach_state { 331 I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */ 332 I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */ 333 I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */ 334 I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */ 335 I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */ 336 I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */ 337 I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */ 338 I40E_ATTACH_INIT = 0x0080, /* Device initialized */ 339 I40E_ATTACH_STATS = 0x0200, /* Kstats created */ 340 I40E_ATTACH_MAC = 0x0800, /* MAC registered */ 341 I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */ 342 I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */ 343 I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */ 344 } i40e_attach_state_t; 345 346 347 /* 348 * State flags that what's going on in in the device. Some of these state flags 349 * indicate some aspirational work that needs to happen in the driver. 350 * 351 * I40E_UNKNOWN: The device has yet to be started. 352 * I40E_INITIALIZED: The device has been fully attached. 353 * I40E_STARTED: The device has come out of the GLDV3 start routine. 354 * I40E_SUSPENDED: The device is suspended and I/O among other things 355 * should not occur. This happens because of an actual 356 * DDI_SUSPEND or interrupt adjustments. 357 * I40E_STALL: The tx stall detection logic has found a stall. 358 * I40E_OVERTEMP: The device has encountered a temperature alarm. 359 * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we 360 * shouldn't be manipulating their state. 361 * I40E_ERROR: We've detected an FM error and degraded the device. 362 */ 363 typedef enum i40e_state { 364 I40E_UNKNOWN = 0x00, 365 I40E_INITIALIZED = 0x01, 366 I40E_STARTED = 0x02, 367 I40E_SUSPENDED = 0x04, 368 I40E_STALL = 0x08, 369 I40E_OVERTEMP = 0x20, 370 I40E_INTR_ADJUST = 0x40, 371 I40E_ERROR = 0x80 372 } i40e_state_t; 373 374 375 /* 376 * Definitions for common Intel things that we use and some slightly more usable 377 * names. 378 */ 379 typedef struct i40e_hw i40e_hw_t; 380 typedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t; 381 382 /* 383 * Handles and addresses of DMA buffers. 384 */ 385 typedef struct i40e_dma_buffer { 386 caddr_t dmab_address; /* Virtual address */ 387 uint64_t dmab_dma_address; /* DMA (Hardware) address */ 388 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */ 389 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */ 390 size_t dmab_size; /* Buffer size */ 391 size_t dmab_len; /* Data length in the buffer */ 392 } i40e_dma_buffer_t; 393 394 /* 395 * RX Control Block 396 */ 397 typedef struct i40e_rx_control_block { 398 mblk_t *rcb_mp; 399 uint32_t rcb_ref; 400 i40e_dma_buffer_t rcb_dma; 401 frtn_t rcb_free_rtn; 402 struct i40e_rx_data *rcb_rxd; 403 } i40e_rx_control_block_t; 404 405 typedef enum { 406 I40E_TX_NONE, 407 I40E_TX_COPY, 408 I40E_TX_DMA 409 } i40e_tx_type_t; 410 411 typedef struct i40e_tx_desc i40e_tx_desc_t; 412 typedef union i40e_32byte_rx_desc i40e_rx_desc_t; 413 414 typedef struct i40e_tx_control_block { 415 struct i40e_tx_control_block *tcb_next; 416 mblk_t *tcb_mp; 417 i40e_tx_type_t tcb_type; 418 ddi_dma_handle_t tcb_dma_handle; 419 i40e_dma_buffer_t tcb_dma; 420 } i40e_tx_control_block_t; 421 422 /* 423 * Receive ring data (used below). 424 */ 425 typedef struct i40e_rx_data { 426 struct i40e *rxd_i40e; 427 428 /* 429 * RX descriptor ring definitions 430 */ 431 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */ 432 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */ 433 uint32_t rxd_desc_next; /* Index of next rx desc */ 434 435 /* 436 * RX control block list definitions 437 */ 438 kmutex_t rxd_free_lock; /* Lock to protect free data */ 439 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */ 440 i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */ 441 i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */ 442 uint32_t rxd_rcb_free; /* Number of free rcbs */ 443 444 /* 445 * RX software ring settings 446 */ 447 uint32_t rxd_ring_size; /* Rx descriptor ring size */ 448 uint32_t rxd_free_list_size; /* Rx free list size */ 449 450 /* 451 * RX outstanding data. This is used to keep track of outstanding loaned 452 * descriptors after we've shut down receiving information. Note these 453 * are protected by the i40e_t`i40e_rx_pending_lock. 454 */ 455 uint32_t rxd_rcb_pending; 456 boolean_t rxd_shutdown; 457 } i40e_rx_data_t; 458 459 /* 460 * Structures for unicast and multicast addresses. Note that we keep the VSI id 461 * around for unicast addresses, since they may belong to different VSIs. 462 * However, since all multicast addresses belong to the default VSI, we don't 463 * duplicate that information. 464 */ 465 typedef struct i40e_uaddr { 466 uint8_t iua_mac[ETHERADDRL]; 467 int iua_vsi; 468 } i40e_uaddr_t; 469 470 typedef struct i40e_maddr { 471 uint8_t ima_mac[ETHERADDRL]; 472 } i40e_maddr_t; 473 474 /* 475 * Collection of RX statistics on a given queue. 476 */ 477 typedef struct i40e_rxq_stat { 478 /* 479 * The i40e hardware does not maintain statistics on a per-ring basis, 480 * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we 481 * need to maintain our own stats for packets and bytes. 482 */ 483 kstat_named_t irxs_bytes; /* Bytes in on queue */ 484 kstat_named_t irxs_packets; /* Packets in on queue */ 485 486 /* 487 * The following set of stats cover non-checksum data path issues. 488 */ 489 kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */ 490 kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */ 491 kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */ 492 kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */ 493 kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */ 494 495 /* 496 * The following set of statistics covers rx checksum related activity. 497 * These are all primarily set in i40e_rx_hcksum. If rx checksum 498 * activity is disabled, then these should all be zero. 499 */ 500 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */ 501 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */ 502 kstat_named_t irxs_hck_unknown; /* !pinfo.known */ 503 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */ 504 kstat_named_t irxs_hck_iperr; /* IPE error bit set */ 505 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */ 506 kstat_named_t irxs_hck_l4err; /* L4E error bit set */ 507 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */ 508 kstat_named_t irxs_hck_set; /* Total times we set cksum */ 509 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */ 510 } i40e_rxq_stat_t; 511 512 /* 513 * Collection of TX Statistics on a given queue 514 */ 515 typedef struct i40e_txq_stat { 516 kstat_named_t itxs_bytes; /* Bytes out on queue */ 517 kstat_named_t itxs_packets; /* Packets out on queue */ 518 kstat_named_t itxs_descriptors; /* Descriptors issued */ 519 kstat_named_t itxs_recycled; /* Descriptors reclaimed */ 520 /* 521 * Various failure conditions. 522 */ 523 kstat_named_t itxs_hck_meoifail; /* ether offload failures */ 524 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */ 525 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */ 526 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */ 527 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */ 528 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */ 529 530 kstat_named_t itxs_err_notcb; /* No tcb's available */ 531 kstat_named_t itxs_err_nodescs; /* No tcb's available */ 532 kstat_named_t itxs_err_context; /* Total context failures */ 533 534 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */ 535 } i40e_txq_stat_t; 536 537 /* 538 * An instance of an XL710 transmit/receive queue pair. This currently 539 * represents a combination of both a transmit and receive ring, though they 540 * should really be split apart into separate logical structures. Unfortunately, 541 * during initial work we mistakenly joined them together. 542 */ 543 typedef struct i40e_trqpair { 544 struct i40e *itrq_i40e; 545 546 /* Receive-side structures. */ 547 kmutex_t itrq_rx_lock; 548 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */ 549 i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */ 550 uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */ 551 uint32_t itrq_index; /* Queue index in the PF */ 552 uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */ 553 boolean_t itrq_intr_poll; /* True when polling */ 554 555 /* Receive-side stats. */ 556 i40e_rxq_stat_t itrq_rxstat; 557 kstat_t *itrq_rxkstat; 558 559 /* Transmit-side structures. */ 560 kmutex_t itrq_tx_lock; 561 mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */ 562 uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */ 563 boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */ 564 565 /* 566 * TX data sizing 567 */ 568 uint32_t itrq_tx_ring_size; 569 uint32_t itrq_tx_free_list_size; 570 571 /* 572 * TX descriptor ring data 573 */ 574 i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */ 575 i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */ 576 volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */ 577 uint32_t itrq_desc_head; /* Last index hw freed */ 578 uint32_t itrq_desc_tail; /* Index of next free desc */ 579 uint32_t itrq_desc_free; /* Number of free descriptors */ 580 581 /* 582 * TX control block (tcb) data 583 */ 584 kmutex_t itrq_tcb_lock; 585 i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */ 586 i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */ 587 i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */ 588 uint32_t itrq_tcb_free; /* Count of free tcb */ 589 590 /* Transmit-side stats. */ 591 i40e_txq_stat_t itrq_txstat; 592 kstat_t *itrq_txkstat; 593 594 } i40e_trqpair_t; 595 596 /* 597 * VSI statistics. 598 * 599 * This mirrors the i40e_eth_stats structure but transforms it into a kstat. 600 * Note that the stock statistic structure also includes entries for tx 601 * discards. However, this is not actually implemented for the VSI (see Table 602 * 7-221), hence why we don't include the member which would always have a value 603 * of zero. This choice was made to minimize confusion to someone looking at 604 * these, as a value of zero does not necessarily equate to the fact that it's 605 * not implemented. 606 */ 607 typedef struct i40e_vsi_stats { 608 uint64_t ivs_rx_bytes; /* gorc */ 609 uint64_t ivs_rx_unicast; /* uprc */ 610 uint64_t ivs_rx_multicast; /* mprc */ 611 uint64_t ivs_rx_broadcast; /* bprc */ 612 uint64_t ivs_rx_discards; /* rdpc */ 613 uint64_t ivs_rx_unknown_protocol; /* rupp */ 614 uint64_t ivs_tx_bytes; /* gotc */ 615 uint64_t ivs_tx_unicast; /* uptc */ 616 uint64_t ivs_tx_multicast; /* mptc */ 617 uint64_t ivs_tx_broadcast; /* bptc */ 618 uint64_t ivs_tx_errors; /* tepc */ 619 } i40e_vsi_stats_t; 620 621 typedef struct i40e_vsi_kstats { 622 kstat_named_t ivk_rx_bytes; 623 kstat_named_t ivk_rx_unicast; 624 kstat_named_t ivk_rx_multicast; 625 kstat_named_t ivk_rx_broadcast; 626 kstat_named_t ivk_rx_discards; 627 kstat_named_t ivk_rx_unknown_protocol; 628 kstat_named_t ivk_tx_bytes; 629 kstat_named_t ivk_tx_unicast; 630 kstat_named_t ivk_tx_multicast; 631 kstat_named_t ivk_tx_broadcast; 632 kstat_named_t ivk_tx_errors; 633 } i40e_vsi_kstats_t; 634 635 /* 636 * For pf statistics, we opt not to use the standard statistics as defined by 637 * the Intel common code. This also currently combines statistics that are 638 * global across the entire device. 639 */ 640 typedef struct i40e_pf_stats { 641 uint64_t ips_rx_bytes; /* gorc */ 642 uint64_t ips_rx_unicast; /* uprc */ 643 uint64_t ips_rx_multicast; /* mprc */ 644 uint64_t ips_rx_broadcast; /* bprc */ 645 uint64_t ips_tx_bytes; /* gotc */ 646 uint64_t ips_tx_unicast; /* uptc */ 647 uint64_t ips_tx_multicast; /* mptc */ 648 uint64_t ips_tx_broadcast; /* bptc */ 649 650 uint64_t ips_rx_size_64; /* prc64 */ 651 uint64_t ips_rx_size_127; /* prc127 */ 652 uint64_t ips_rx_size_255; /* prc255 */ 653 uint64_t ips_rx_size_511; /* prc511 */ 654 uint64_t ips_rx_size_1023; /* prc1023 */ 655 uint64_t ips_rx_size_1522; /* prc1522 */ 656 uint64_t ips_rx_size_9522; /* prc9522 */ 657 658 uint64_t ips_tx_size_64; /* ptc64 */ 659 uint64_t ips_tx_size_127; /* ptc127 */ 660 uint64_t ips_tx_size_255; /* ptc255 */ 661 uint64_t ips_tx_size_511; /* ptc511 */ 662 uint64_t ips_tx_size_1023; /* ptc1023 */ 663 uint64_t ips_tx_size_1522; /* ptc1522 */ 664 uint64_t ips_tx_size_9522; /* ptc9522 */ 665 666 uint64_t ips_link_xon_rx; /* lxonrxc */ 667 uint64_t ips_link_xoff_rx; /* lxoffrxc */ 668 uint64_t ips_link_xon_tx; /* lxontxc */ 669 uint64_t ips_link_xoff_tx; /* lxofftxc */ 670 uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */ 671 uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */ 672 uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */ 673 uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */ 674 uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 675 676 uint64_t ips_crc_errors; /* crcerrs */ 677 uint64_t ips_illegal_bytes; /* illerrc */ 678 uint64_t ips_mac_local_faults; /* mlfc */ 679 uint64_t ips_mac_remote_faults; /* mrfc */ 680 uint64_t ips_rx_length_errors; /* rlec */ 681 uint64_t ips_rx_undersize; /* ruc */ 682 uint64_t ips_rx_fragments; /* rfc */ 683 uint64_t ips_rx_oversize; /* roc */ 684 uint64_t ips_rx_jabber; /* rjc */ 685 uint64_t ips_rx_discards; /* rdpc */ 686 uint64_t ips_rx_vm_discards; /* ldpc */ 687 uint64_t ips_rx_short_discards; /* mspdc */ 688 uint64_t ips_tx_dropped_link_down; /* tdold */ 689 uint64_t ips_rx_unknown_protocol; /* rupp */ 690 uint64_t ips_rx_err1; /* rxerr1 */ 691 uint64_t ips_rx_err2; /* rxerr2 */ 692 } i40e_pf_stats_t; 693 694 typedef struct i40e_pf_kstats { 695 kstat_named_t ipk_rx_bytes; /* gorc */ 696 kstat_named_t ipk_rx_unicast; /* uprc */ 697 kstat_named_t ipk_rx_multicast; /* mprc */ 698 kstat_named_t ipk_rx_broadcast; /* bprc */ 699 kstat_named_t ipk_tx_bytes; /* gotc */ 700 kstat_named_t ipk_tx_unicast; /* uptc */ 701 kstat_named_t ipk_tx_multicast; /* mptc */ 702 kstat_named_t ipk_tx_broadcast; /* bptc */ 703 704 kstat_named_t ipk_rx_size_64; /* prc64 */ 705 kstat_named_t ipk_rx_size_127; /* prc127 */ 706 kstat_named_t ipk_rx_size_255; /* prc255 */ 707 kstat_named_t ipk_rx_size_511; /* prc511 */ 708 kstat_named_t ipk_rx_size_1023; /* prc1023 */ 709 kstat_named_t ipk_rx_size_1522; /* prc1522 */ 710 kstat_named_t ipk_rx_size_9522; /* prc9522 */ 711 712 kstat_named_t ipk_tx_size_64; /* ptc64 */ 713 kstat_named_t ipk_tx_size_127; /* ptc127 */ 714 kstat_named_t ipk_tx_size_255; /* ptc255 */ 715 kstat_named_t ipk_tx_size_511; /* ptc511 */ 716 kstat_named_t ipk_tx_size_1023; /* ptc1023 */ 717 kstat_named_t ipk_tx_size_1522; /* ptc1522 */ 718 kstat_named_t ipk_tx_size_9522; /* ptc9522 */ 719 720 kstat_named_t ipk_link_xon_rx; /* lxonrxc */ 721 kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */ 722 kstat_named_t ipk_link_xon_tx; /* lxontxc */ 723 kstat_named_t ipk_link_xoff_tx; /* lxofftxc */ 724 kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */ 725 kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */ 726 kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */ 727 kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */ 728 kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 729 730 kstat_named_t ipk_crc_errors; /* crcerrs */ 731 kstat_named_t ipk_illegal_bytes; /* illerrc */ 732 kstat_named_t ipk_mac_local_faults; /* mlfc */ 733 kstat_named_t ipk_mac_remote_faults; /* mrfc */ 734 kstat_named_t ipk_rx_length_errors; /* rlec */ 735 kstat_named_t ipk_rx_undersize; /* ruc */ 736 kstat_named_t ipk_rx_fragments; /* rfc */ 737 kstat_named_t ipk_rx_oversize; /* roc */ 738 kstat_named_t ipk_rx_jabber; /* rjc */ 739 kstat_named_t ipk_rx_discards; /* rdpc */ 740 kstat_named_t ipk_rx_vm_discards; /* ldpc */ 741 kstat_named_t ipk_rx_short_discards; /* mspdc */ 742 kstat_named_t ipk_tx_dropped_link_down; /* tdold */ 743 kstat_named_t ipk_rx_unknown_protocol; /* rupp */ 744 kstat_named_t ipk_rx_err1; /* rxerr1 */ 745 kstat_named_t ipk_rx_err2; /* rxerr2 */ 746 } i40e_pf_kstats_t; 747 748 /* 749 * Resources that are pooled and specific to a given i40e_t. 750 */ 751 typedef struct i40e_func_rsrc { 752 uint_t ifr_nrx_queue; 753 uint_t ifr_nrx_queue_used; 754 uint_t ifr_ntx_queue; 755 uint_t ifr_trx_queue_used; 756 uint_t ifr_nvsis; 757 uint_t ifr_nvsis_used; 758 uint_t ifr_nmacfilt; 759 uint_t ifr_nmacfilt_used; 760 uint_t ifr_nmcastfilt; 761 uint_t ifr_nmcastfilt_used; 762 } i40e_func_rsrc_t; 763 764 /* 765 * Main i40e per-instance state. 766 */ 767 typedef struct i40e { 768 list_node_t i40e_glink; /* Global list link */ 769 list_node_t i40e_dlink; /* Device list link */ 770 kmutex_t i40e_general_lock; /* General device lock */ 771 772 /* 773 * General Data and management 774 */ 775 dev_info_t *i40e_dip; 776 int i40e_instance; 777 int i40e_fm_capabilities; 778 uint_t i40e_state; 779 i40e_attach_state_t i40e_attach_progress; 780 mac_handle_t i40e_mac_hdl; 781 ddi_periodic_t i40e_periodic_id; 782 783 /* 784 * Pointers to common code data structures and memory for the common 785 * code. 786 */ 787 struct i40e_hw i40e_hw_space; 788 struct i40e_osdep i40e_osdep_space; 789 struct i40e_aq_get_phy_abilities_resp i40e_phy; 790 void *i40e_aqbuf; 791 792 /* 793 * Device state, switch information, and resources. 794 */ 795 int i40e_vsi_id; 796 uint16_t i40e_vsi_num; 797 struct i40e_device *i40e_device; 798 i40e_func_rsrc_t i40e_resources; 799 uint16_t i40e_switch_rsrc_alloc; 800 uint16_t i40e_switch_rsrc_actual; 801 i40e_switch_rsrc_t *i40e_switch_rsrcs; 802 i40e_uaddr_t *i40e_uaddrs; 803 i40e_maddr_t *i40e_maddrs; 804 int i40e_mcast_promisc_count; 805 boolean_t i40e_promisc_on; 806 link_state_t i40e_link_state; 807 uint32_t i40e_link_speed; /* In Mbps */ 808 link_duplex_t i40e_link_duplex; 809 uint_t i40e_sdu; 810 uint_t i40e_frame_max; 811 812 /* 813 * Transmit and receive information, tunables, and MAC info. 814 */ 815 i40e_trqpair_t *i40e_trqpairs; 816 boolean_t i40e_mr_enable; 817 int i40e_num_trqpairs; 818 uint_t i40e_other_itr; 819 820 int i40e_num_rx_groups; 821 int i40e_num_rx_descs; 822 mac_group_handle_t i40e_rx_group_handle; 823 uint32_t i40e_rx_ring_size; 824 uint32_t i40e_rx_buf_size; 825 boolean_t i40e_rx_hcksum_enable; 826 uint32_t i40e_rx_dma_min; 827 uint32_t i40e_rx_limit_per_intr; 828 uint_t i40e_rx_itr; 829 830 int i40e_num_tx_descs; 831 uint32_t i40e_tx_ring_size; 832 uint32_t i40e_tx_buf_size; 833 uint32_t i40e_tx_block_thresh; 834 boolean_t i40e_tx_hcksum_enable; 835 uint32_t i40e_tx_dma_min; 836 uint_t i40e_tx_itr; 837 838 /* 839 * Interrupt state 840 */ 841 uint_t i40e_intr_pri; 842 uint_t i40e_intr_force; 843 uint_t i40e_intr_type; 844 int i40e_intr_cap; 845 uint32_t i40e_intr_count; 846 uint32_t i40e_intr_count_max; 847 uint32_t i40e_intr_count_min; 848 size_t i40e_intr_size; 849 ddi_intr_handle_t *i40e_intr_handles; 850 ddi_cb_handle_t i40e_callback_handle; 851 852 /* 853 * DMA attributes. See i40e_transceiver.c for why we have copies of them 854 * in the i40e_t. 855 */ 856 ddi_dma_attr_t i40e_static_dma_attr; 857 ddi_dma_attr_t i40e_txbind_dma_attr; 858 ddi_device_acc_attr_t i40e_desc_acc_attr; 859 ddi_device_acc_attr_t i40e_buf_acc_attr; 860 861 /* 862 * The following two fields are used to protect and keep track of 863 * outstanding, loaned buffers to MAC. If we have these, we can't 864 * detach as we have active DMA memory outstanding. 865 */ 866 kmutex_t i40e_rx_pending_lock; 867 kcondvar_t i40e_rx_pending_cv; 868 uint32_t i40e_rx_pending; 869 870 /* 871 * PF statistics and VSI statistics. 872 */ 873 kmutex_t i40e_stat_lock; 874 kstat_t *i40e_pf_kstat; 875 kstat_t *i40e_vsi_kstat; 876 i40e_pf_stats_t i40e_pf_stat; 877 i40e_vsi_stats_t i40e_vsi_stat; 878 uint16_t i40e_vsi_stat_id; 879 880 /* 881 * Misc. stats and counters that should maybe one day be kstats. 882 */ 883 uint64_t i40e_s_link_status_errs; 884 uint32_t i40e_s_link_status_lasterr; 885 886 /* 887 * LED information. Note this state is only modified in 888 * i40e_gld_set_led() which is protected by MAC's serializer lock. 889 */ 890 uint32_t i40e_led_status; 891 boolean_t i40e_led_saved; 892 } i40e_t; 893 894 /* 895 * The i40e_device represents a PCI device which encapsulates multiple physical 896 * functions which are represented as an i40e_t. This is used to track the use 897 * of pooled resources throughout all of the various devices. 898 */ 899 typedef struct i40e_device { 900 list_node_t id_link; 901 dev_info_t *id_parent; 902 uint_t id_pci_bus; 903 uint_t id_pci_device; 904 uint_t id_nfuncs; /* Total number of functions */ 905 uint_t id_nreg; /* Total number present */ 906 list_t id_i40e_list; /* List of i40e_t's registered */ 907 i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */ 908 uint_t id_rsrcs_alloc; /* Total allocated resources */ 909 uint_t id_rsrcs_act; /* Actual number of resources */ 910 } i40e_device_t; 911 912 /* Values for the interrupt forcing on the NIC. */ 913 #define I40E_INTR_NONE 0 914 #define I40E_INTR_MSIX 1 915 #define I40E_INTR_MSI 2 916 #define I40E_INTR_LEGACY 3 917 918 /* Hint that we don't want to do any polling... */ 919 #define I40E_POLL_NULL -1 920 921 /* 922 * Logging functions. 923 */ 924 /*PRINTFLIKE2*/ 925 extern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 926 /*PRINTFLIKE2*/ 927 extern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 928 /*PRINTFLIKE2*/ 929 extern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 930 931 /* 932 * General link handling functions. 933 */ 934 extern void i40e_link_check(i40e_t *); 935 extern void i40e_update_mtu(i40e_t *); 936 937 /* 938 * FMA functions. 939 */ 940 extern int i40e_check_acc_handle(ddi_acc_handle_t); 941 extern int i40e_check_dma_handle(ddi_dma_handle_t); 942 extern void i40e_fm_ereport(i40e_t *, char *); 943 944 /* 945 * Interrupt handlers and interrupt handler setup. 946 */ 947 extern void i40e_intr_chip_init(i40e_t *); 948 extern void i40e_intr_chip_fini(i40e_t *); 949 extern uint_t i40e_intr_msix(void *, void *); 950 extern uint_t i40e_intr_msi(void *, void *); 951 extern uint_t i40e_intr_legacy(void *, void *); 952 extern void i40e_intr_io_enable_all(i40e_t *); 953 extern void i40e_intr_io_disable_all(i40e_t *); 954 extern void i40e_intr_io_clear_cause(i40e_t *); 955 extern void i40e_intr_rx_queue_disable(i40e_trqpair_t *); 956 extern void i40e_intr_rx_queue_enable(i40e_trqpair_t *); 957 extern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t); 958 959 /* 960 * Receive-side functions 961 */ 962 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int); 963 extern mblk_t *i40e_ring_rx_poll(void *, int); 964 extern void i40e_rx_recycle(caddr_t); 965 966 /* 967 * Transmit-side functions 968 */ 969 mblk_t *i40e_ring_tx(void *, mblk_t *); 970 extern void i40e_tx_recycle_ring(i40e_trqpair_t *); 971 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *); 972 973 /* 974 * Statistics functions. 975 */ 976 extern boolean_t i40e_stats_init(i40e_t *); 977 extern void i40e_stats_fini(i40e_t *); 978 extern boolean_t i40e_stat_vsi_init(i40e_t *); 979 extern void i40e_stat_vsi_fini(i40e_t *); 980 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *); 981 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *); 982 extern int i40e_m_stat(void *, uint_t, uint64_t *); 983 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 984 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 985 986 /* 987 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code. 988 */ 989 extern boolean_t i40e_register_mac(i40e_t *); 990 extern boolean_t i40e_start(i40e_t *, boolean_t); 991 extern void i40e_stop(i40e_t *, boolean_t); 992 993 /* 994 * DMA & buffer functions and attributes 995 */ 996 extern void i40e_init_dma_attrs(i40e_t *, boolean_t); 997 extern boolean_t i40e_alloc_ring_mem(i40e_t *); 998 extern void i40e_free_ring_mem(i40e_t *, boolean_t); 999 1000 #ifdef __cplusplus 1001 } 1002 #endif 1003 1004 #endif /* _I40E_SW_H */ 1005