1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved. 14 * Copyright 2019 Joyent, Inc. 15 * Copyright 2017 Tegile Systems, Inc. All rights reserved. 16 */ 17 18 /* 19 * Please see i40e_main.c for an introduction to the device driver, its layout, 20 * and more. 21 */ 22 23 #ifndef _I40E_SW_H 24 #define _I40E_SW_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include <sys/types.h> 31 #include <sys/conf.h> 32 #include <sys/debug.h> 33 #include <sys/stropts.h> 34 #include <sys/stream.h> 35 #include <sys/strsun.h> 36 #include <sys/strlog.h> 37 #include <sys/kmem.h> 38 #include <sys/stat.h> 39 #include <sys/kstat.h> 40 #include <sys/modctl.h> 41 #include <sys/errno.h> 42 #include <sys/dlpi.h> 43 #include <sys/mac_provider.h> 44 #include <sys/mac_ether.h> 45 #include <sys/vlan.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/pci.h> 49 #include <sys/pcie.h> 50 #include <sys/sdt.h> 51 #include <sys/ethernet.h> 52 #include <sys/pattr.h> 53 #include <sys/strsubr.h> 54 #include <sys/netlb.h> 55 #include <sys/random.h> 56 #include <inet/common.h> 57 #include <inet/tcp.h> 58 #include <inet/ip.h> 59 #include <inet/mi.h> 60 #include <inet/nd.h> 61 #include <netinet/udp.h> 62 #include <netinet/sctp.h> 63 #include <sys/bitmap.h> 64 #include <sys/cpuvar.h> 65 #include <sys/ddifm.h> 66 #include <sys/fm/protocol.h> 67 #include <sys/fm/util.h> 68 #include <sys/disp.h> 69 #include <sys/fm/io/ddi.h> 70 #include <sys/list.h> 71 #include <sys/debug.h> 72 #include <sys/sdt.h> 73 #include <sys/ddi_ufm.h> 74 #include "i40e_type.h" 75 #include "i40e_osdep.h" 76 #include "i40e_prototype.h" 77 #include "i40e_xregs.h" 78 79 #define I40E_MODULE_NAME "i40e" 80 81 #define I40E_ADAPTER_REGSET 1 82 83 /* 84 * Configuration constants. Note that the hardware defines a minimum bound of 32 85 * descriptors and requires that the programming of the descriptor lengths be 86 * aligned in units of 32 descriptors. 87 */ 88 #define I40E_MIN_TX_RING_SIZE 64 89 #define I40E_MAX_TX_RING_SIZE 4096 90 #define I40E_DEF_TX_RING_SIZE 1024 91 92 #define I40E_MIN_RX_RING_SIZE 64 93 #define I40E_MAX_RX_RING_SIZE 4096 94 #define I40E_DEF_RX_RING_SIZE 1024 95 96 #define I40E_DESC_ALIGN 32 97 98 /* 99 * Sizes used for asynchronous processing of the adminq. We allocate a fixed 100 * size buffer for each instance of the device during attach time, rather than 101 * allocating and freeing one during interrupt processing. 102 * 103 * We also define the descriptor size of the admin queue here. 104 */ 105 #define I40E_ADMINQ_BUFSZ 4096 106 #define I40E_MAX_ADMINQ_SIZE 1024 107 #define I40E_DEF_ADMINQ_SIZE 256 108 109 /* 110 * Note, while the min and maximum values are based upon the sizing of the ring 111 * itself, the default is taken from ixgbe without much thought. It's basically 112 * been cargo culted. See i40e_transceiver.c for a bit more information. 113 */ 114 #define I40E_MIN_RX_LIMIT_PER_INTR 16 115 #define I40E_MAX_RX_LIMIT_PER_INTR 4096 116 #define I40E_DEF_RX_LIMIT_PER_INTR 256 117 118 /* 119 * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728. 120 * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN 121 * header size (18 bytes) to get the actual maximum frame we can use. If 122 * different adapters end up with different sizes, we should make this value a 123 * bit more dynamic. 124 */ 125 #define I40E_MAX_MTU 9706 126 #define I40E_MIN_MTU ETHERMIN 127 #define I40E_DEF_MTU ETHERMTU 128 129 /* 130 * Interrupt throttling related values. Interrupt throttling values are defined 131 * in two microsecond increments. Note that a value of zero basically says do no 132 * ITR activity. A helpful way to think about these is that setting the ITR to a 133 * value will allow a certain number of interrupts per second. 134 * 135 * Our default values for RX allow 20k interrupts per second while our default 136 * values for TX allow for 5k interrupts per second. For other class interrupts, 137 * we limit ourselves to a rate of 2k/s. 138 */ 139 #define I40E_MIN_ITR 0x0000 140 #define I40E_MAX_ITR 0x0FF0 141 #define I40E_DEF_RX_ITR 0x0019 142 #define I40E_DEF_TX_ITR 0x0064 143 #define I40E_DEF_OTHER_ITR 0x00FA 144 145 /* 146 * Indexes into the three ITR registers that we have. 147 */ 148 typedef enum i40e_itr_index { 149 I40E_ITR_INDEX_RX = 0x0, 150 I40E_ITR_INDEX_TX = 0x1, 151 I40E_ITR_INDEX_OTHER = 0x2, 152 I40E_ITR_INDEX_NONE = 0x3 153 } i40e_itr_index_t; 154 155 /* 156 * The hardware claims to support LSO up to 256 KB, but due to the limitations 157 * imposed by the IP header for non-jumbo frames, we cap it at 64 KB. 158 */ 159 #define I40E_LSO_MAXLEN (64 * 1024) 160 161 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */ 162 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */ 163 164 /* 165 * All the other queue types for are defined by the common code. However, this 166 * is the constant to indicate that it's terminated. 167 */ 168 #define I40E_QUEUE_TYPE_EOL 0x7FF 169 170 /* 171 * See the comments in i40e_transceiver.c as to the purpose of this value and 172 * how it's used to ensure that the IP header is eventually aligned when it's 173 * received by the OS. 174 */ 175 #define I40E_BUF_IPHDR_ALIGNMENT 2 176 177 /* 178 * The XL710 controller has a total of eight buffers available for the 179 * transmission of any single frame. This is defined in 8.4.1 - Transmit 180 * Packet in System Memory. 181 */ 182 #define I40E_TX_MAX_COOKIE 8 183 184 /* 185 * An LSO frame can be as large as 64KB, so we allow a DMA bind to span more 186 * cookies than a non-LSO frame. The key here to is to select a value such 187 * that once the HW has chunked up the LSO frame into MSS-sized segments that no 188 * single segment spans more than 8 cookies (see comments for 189 * I40E_TX_MAX_COOKIE) 190 */ 191 #define I40E_TX_LSO_MAX_COOKIE 32 192 193 /* 194 * Sizing to determine the amount of available descriptors at which we'll 195 * consider ourselves blocked. Also, when we have these available, we'll then 196 * consider ourselves available to transmit to MAC again. Strictly speaking, the 197 * MAX is based on the ring size. The default sizing is based on ixgbe. 198 */ 199 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE 200 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH 201 202 /* 203 * Sizing for DMA thresholds. These are used to indicate whether or not we 204 * should perform a bcopy or a DMA binding of a given message block. The range 205 * allows for setting things such that we'll always do a bcopy (a high value) or 206 * always perform a DMA binding (a low value). 207 */ 208 #define I40E_MIN_RX_DMA_THRESH 0 209 #define I40E_DEF_RX_DMA_THRESH 256 210 #define I40E_MAX_RX_DMA_THRESH INT32_MAX 211 212 #define I40E_MIN_TX_DMA_THRESH 0 213 #define I40E_DEF_TX_DMA_THRESH 256 214 #define I40E_MAX_TX_DMA_THRESH INT32_MAX 215 216 /* 217 * The max size of each individual tx buffer is 16KB - 1. 218 * See table 8-17 219 */ 220 #define I40E_MAX_TX_BUFSZ 0x0000000000003FFFull 221 222 /* 223 * Resource sizing counts. There are various aspects of hardware where we may 224 * have some variable number of elements that we need to handle. Such as the 225 * hardware capabilities and switch capacities. We cannot know a priori how many 226 * elements to do, so instead we take a starting guess and then will grow it up 227 * to an upper bound on a number of elements, to limit memory consumption in 228 * case of a hardware bug. 229 */ 230 #define I40E_HW_CAP_DEFAULT 40 231 #define I40E_SWITCH_CAP_DEFAULT 25 232 233 /* 234 * Host Memory Context related constants. 235 */ 236 #define I40E_HMC_RX_CTX_UNIT 128 237 #define I40E_HMC_RX_DBUFF_MIN 1024 238 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128) 239 #define I40E_HMC_RX_DTYPE_NOSPLIT 0 240 #define I40E_HMC_RX_DSIZE_32BYTE 1 241 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1 242 #define I40E_HMC_RX_FC_DISABLE 0 243 #define I40E_HMC_RX_L2TAGORDER 1 244 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0 245 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0 246 #define I40E_HMC_RX_TPH_DISABLE 0 247 #define I40E_HMC_RX_LOWRXQ_NOINTR 0 248 #define I40E_HMC_RX_PREFENA 1 249 250 #define I40E_HMC_TX_CTX_UNIT 128 251 #define I40E_HMC_TX_NEW_CONTEXT 1 252 #define I40E_HMC_TX_FC_DISABLE 0 253 #define I40E_HMC_TX_TS_DISABLE 0 254 #define I40E_HMC_TX_FD_DISABLE 0 255 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0 256 #define I40E_HMC_TX_WB_ENABLE 1 257 #define I40E_HMC_TX_TPH_DISABLE 0 258 259 /* 260 * This defines the error mask that we care about from rx descriptors. Currently 261 * we're only concerned with the general errors and oversize errors. 262 */ 263 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \ 264 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)) 265 266 /* 267 * Property sizing macros for firmware versions, etc. They need to be large 268 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x. 269 */ 270 #define I40E_DDI_PROP_LEN 64 271 272 /* 273 * Place an artificial limit on the max number of groups. The X710 274 * series supports up to 384 VSIs to be partitioned across PFs as the 275 * driver sees fit. But until we support more interrupts this seems 276 * like a good place to start. 277 */ 278 #define I40E_GROUP_MAX 32 279 280 #define I40E_GROUP_NOMSIX 1 281 #define I40E_TRQPAIR_NOMSIX 1 282 283 /* 284 * It seems reasonable to cast this to void because the only reason that we 285 * should be getting a DDI_FAILURE is due to the fact that we specify addresses 286 * out of range. Because we specify no offset or address, it shouldn't happen. 287 */ 288 #ifdef DEBUG 289 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \ 290 (handle)->dmab_dma_handle, 0, 0, \ 291 (flag))) 292 #else /* !DEBUG */ 293 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \ 294 (handle)->dmab_dma_handle, 0, 0, \ 295 (flag))) 296 #endif /* DEBUG */ 297 298 /* 299 * Constants related to ring startup and teardown. These refer to the amount of 300 * time that we're willing to wait for a ring to spin up and spin down. 301 */ 302 #define I40E_RING_WAIT_NTRIES 10 303 #define I40E_RING_WAIT_PAUSE 10 /* ms */ 304 305 /* 306 * Printed Board Assembly (PBA) length. These are derived from Table 6-2. 307 */ 308 #define I40E_PBANUM_LENGTH 12 309 #define I40E_PBANUM_STRLEN 13 310 311 /* 312 * Define the maximum number of queues for a traffic class. These values come 313 * from the 'Number and offset of queue pairs per TCs' section of the 'Add VSI 314 * Command Buffer' table. For the 710 controller family this is table 7-62 315 * (r2.5) and for the 722 this is table 38-216 (r2.0). 316 */ 317 #define I40E_710_MAX_TC_QUEUES 64 318 #define I40E_722_MAX_TC_QUEUES 128 319 320 /* 321 * Define the size of the HLUT table size. The HLUT table can either be 128 or 322 * 512 bytes. We always set the table size to be 512 bytes in i40e_chip_start(). 323 * Note, this should not be confused with the common code's macro 324 * I40E_HASH_LUT_SIZE_512 which is the bit pattern needed to tell the card to 325 * use a 512 byte HLUT. 326 */ 327 #define I40E_HLUT_TABLE_SIZE 512 328 329 /* 330 * Bit flags for attach_progress 331 */ 332 typedef enum i40e_attach_state { 333 I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */ 334 I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */ 335 I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */ 336 I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */ 337 I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */ 338 I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */ 339 I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */ 340 I40E_ATTACH_INIT = 0x0080, /* Device initialized */ 341 I40E_ATTACH_STATS = 0x0200, /* Kstats created */ 342 I40E_ATTACH_MAC = 0x0800, /* MAC registered */ 343 I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */ 344 I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */ 345 I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */ 346 I40E_ATTACH_UFM_INIT = 0x8000, /* DDI UFM initialized */ 347 } i40e_attach_state_t; 348 349 350 /* 351 * State flags that what's going on in in the device. Some of these state flags 352 * indicate some aspirational work that needs to happen in the driver. 353 * 354 * I40E_UNKNOWN: The device has yet to be started. 355 * I40E_INITIALIZED: The device has been fully attached. 356 * I40E_STARTED: The device has come out of the GLDV3 start routine. 357 * I40E_SUSPENDED: The device is suspended and I/O among other things 358 * should not occur. This happens because of an actual 359 * DDI_SUSPEND or interrupt adjustments. 360 * I40E_STALL: The tx stall detection logic has found a stall. 361 * I40E_OVERTEMP: The device has encountered a temperature alarm. 362 * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we 363 * shouldn't be manipulating their state. 364 * I40E_ERROR: We've detected an FM error and degraded the device. 365 */ 366 typedef enum i40e_state { 367 I40E_UNKNOWN = 0x00, 368 I40E_INITIALIZED = 0x01, 369 I40E_STARTED = 0x02, 370 I40E_SUSPENDED = 0x04, 371 I40E_STALL = 0x08, 372 I40E_OVERTEMP = 0x20, 373 I40E_INTR_ADJUST = 0x40, 374 I40E_ERROR = 0x80 375 } i40e_state_t; 376 377 378 /* 379 * Definitions for common Intel things that we use and some slightly more usable 380 * names. 381 */ 382 typedef struct i40e_hw i40e_hw_t; 383 typedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t; 384 385 /* 386 * Handles and addresses of DMA buffers. 387 */ 388 typedef struct i40e_dma_buffer { 389 caddr_t dmab_address; /* Virtual address */ 390 uint64_t dmab_dma_address; /* DMA (Hardware) address */ 391 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */ 392 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */ 393 size_t dmab_size; /* Buffer size */ 394 size_t dmab_len; /* Data length in the buffer */ 395 } i40e_dma_buffer_t; 396 397 /* 398 * RX Control Block 399 */ 400 typedef struct i40e_rx_control_block { 401 mblk_t *rcb_mp; 402 uint32_t rcb_ref; 403 i40e_dma_buffer_t rcb_dma; 404 frtn_t rcb_free_rtn; 405 struct i40e_rx_data *rcb_rxd; 406 } i40e_rx_control_block_t; 407 408 typedef enum { 409 I40E_TX_NONE, 410 I40E_TX_COPY, 411 I40E_TX_DMA, 412 I40E_TX_DESC, 413 } i40e_tx_type_t; 414 415 typedef struct i40e_tx_desc i40e_tx_desc_t; 416 typedef struct i40e_tx_context_desc i40e_tx_context_desc_t; 417 typedef union i40e_32byte_rx_desc i40e_rx_desc_t; 418 419 struct i40e_dma_bind_info { 420 caddr_t dbi_paddr; 421 size_t dbi_len; 422 }; 423 424 typedef struct i40e_tx_control_block { 425 struct i40e_tx_control_block *tcb_next; 426 mblk_t *tcb_mp; 427 i40e_tx_type_t tcb_type; 428 ddi_dma_handle_t tcb_dma_handle; 429 ddi_dma_handle_t tcb_lso_dma_handle; 430 i40e_dma_buffer_t tcb_dma; 431 struct i40e_dma_bind_info *tcb_bind_info; 432 uint_t tcb_bind_ncookies; 433 boolean_t tcb_used_lso; 434 } i40e_tx_control_block_t; 435 436 /* 437 * Receive ring data (used below). 438 */ 439 typedef struct i40e_rx_data { 440 struct i40e *rxd_i40e; 441 442 /* 443 * RX descriptor ring definitions 444 */ 445 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */ 446 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */ 447 uint32_t rxd_desc_next; /* Index of next rx desc */ 448 449 /* 450 * RX control block list definitions 451 */ 452 kmutex_t rxd_free_lock; /* Lock to protect free data */ 453 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */ 454 i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */ 455 i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */ 456 uint32_t rxd_rcb_free; /* Number of free rcbs */ 457 458 /* 459 * RX software ring settings 460 */ 461 uint32_t rxd_ring_size; /* Rx descriptor ring size */ 462 uint32_t rxd_free_list_size; /* Rx free list size */ 463 464 /* 465 * RX outstanding data. This is used to keep track of outstanding loaned 466 * descriptors after we've shut down receiving information. Note these 467 * are protected by the i40e_t`i40e_rx_pending_lock. 468 */ 469 uint32_t rxd_rcb_pending; 470 boolean_t rxd_shutdown; 471 } i40e_rx_data_t; 472 473 /* 474 * Structures for unicast and multicast addresses. Note that we keep the VSI id 475 * around for unicast addresses, since they may belong to different VSIs. 476 * However, since all multicast addresses belong to the default VSI, we don't 477 * duplicate that information. 478 */ 479 typedef struct i40e_uaddr { 480 uint8_t iua_mac[ETHERADDRL]; 481 int iua_vsi; 482 } i40e_uaddr_t; 483 484 typedef struct i40e_maddr { 485 uint8_t ima_mac[ETHERADDRL]; 486 } i40e_maddr_t; 487 488 /* 489 * Collection of RX statistics on a given queue. 490 */ 491 typedef struct i40e_rxq_stat { 492 /* 493 * The i40e hardware does not maintain statistics on a per-ring basis, 494 * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we 495 * need to maintain our own stats for packets and bytes. 496 */ 497 kstat_named_t irxs_bytes; /* Bytes in on queue */ 498 kstat_named_t irxs_packets; /* Packets in on queue */ 499 500 /* 501 * The following set of stats cover non-checksum data path issues. 502 */ 503 kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */ 504 kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */ 505 kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */ 506 kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */ 507 kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */ 508 509 /* 510 * The following set of statistics covers rx checksum related activity. 511 * These are all primarily set in i40e_rx_hcksum. If rx checksum 512 * activity is disabled, then these should all be zero. 513 */ 514 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */ 515 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */ 516 kstat_named_t irxs_hck_unknown; /* !pinfo.known */ 517 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */ 518 kstat_named_t irxs_hck_iperr; /* IPE error bit set */ 519 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */ 520 kstat_named_t irxs_hck_l4err; /* L4E error bit set */ 521 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */ 522 kstat_named_t irxs_hck_set; /* Total times we set cksum */ 523 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */ 524 } i40e_rxq_stat_t; 525 526 /* 527 * Collection of TX Statistics on a given queue 528 */ 529 typedef struct i40e_txq_stat { 530 kstat_named_t itxs_bytes; /* Bytes out on queue */ 531 kstat_named_t itxs_packets; /* Packets out on queue */ 532 kstat_named_t itxs_descriptors; /* Descriptors issued */ 533 kstat_named_t itxs_recycled; /* Descriptors reclaimed */ 534 kstat_named_t itxs_force_copy; /* non-TSO force copy */ 535 kstat_named_t itxs_tso_force_copy; /* TSO force copy */ 536 /* 537 * Various failure conditions. 538 */ 539 kstat_named_t itxs_hck_meoifail; /* ether offload failures */ 540 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */ 541 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */ 542 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */ 543 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */ 544 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */ 545 kstat_named_t itxs_lso_nohck; /* Missing offloads for LSO */ 546 kstat_named_t itxs_bind_fails; /* DMA bind failures */ 547 kstat_named_t itxs_tx_short; /* Tx chain too short */ 548 549 kstat_named_t itxs_err_notcb; /* No tcb's available */ 550 kstat_named_t itxs_err_nodescs; /* No tcb's available */ 551 kstat_named_t itxs_err_context; /* Total context failures */ 552 553 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */ 554 } i40e_txq_stat_t; 555 556 /* 557 * An instance of an XL710 transmit/receive queue pair. This currently 558 * represents a combination of both a transmit and receive ring, though they 559 * should really be split apart into separate logical structures. Unfortunately, 560 * during initial work we mistakenly joined them together. 561 */ 562 typedef struct i40e_trqpair { 563 struct i40e *itrq_i40e; 564 565 /* Receive-side structures. */ 566 kmutex_t itrq_rx_lock; 567 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */ 568 i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */ 569 uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */ 570 uint32_t itrq_index; /* Queue index in the PF */ 571 uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */ 572 boolean_t itrq_intr_poll; /* True when polling */ 573 574 /* Receive-side stats. */ 575 i40e_rxq_stat_t itrq_rxstat; 576 kstat_t *itrq_rxkstat; 577 578 /* Transmit-side structures. */ 579 kmutex_t itrq_tx_lock; 580 mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */ 581 uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */ 582 boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */ 583 584 /* 585 * TX data sizing 586 */ 587 uint32_t itrq_tx_ring_size; 588 uint32_t itrq_tx_free_list_size; 589 590 /* 591 * TX descriptor ring data 592 */ 593 i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */ 594 i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */ 595 volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */ 596 uint32_t itrq_desc_head; /* Last index hw freed */ 597 uint32_t itrq_desc_tail; /* Index of next free desc */ 598 uint32_t itrq_desc_free; /* Number of free descriptors */ 599 600 /* 601 * TX control block (tcb) data 602 */ 603 kmutex_t itrq_tcb_lock; 604 i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */ 605 i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */ 606 i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */ 607 uint32_t itrq_tcb_free; /* Count of free tcb */ 608 609 /* Transmit-side stats. */ 610 i40e_txq_stat_t itrq_txstat; 611 kstat_t *itrq_txkstat; 612 613 } i40e_trqpair_t; 614 615 /* 616 * VSI statistics. 617 * 618 * This mirrors the i40e_eth_stats structure but transforms it into a kstat. 619 * Note that the stock statistic structure also includes entries for tx 620 * discards. However, this is not actually implemented for the VSI (see Table 621 * 7-221), hence why we don't include the member which would always have a value 622 * of zero. This choice was made to minimize confusion to someone looking at 623 * these, as a value of zero does not necessarily equate to the fact that it's 624 * not implemented. 625 */ 626 typedef struct i40e_vsi_stats { 627 uint64_t ivs_rx_bytes; /* gorc */ 628 uint64_t ivs_rx_unicast; /* uprc */ 629 uint64_t ivs_rx_multicast; /* mprc */ 630 uint64_t ivs_rx_broadcast; /* bprc */ 631 uint64_t ivs_rx_discards; /* rdpc */ 632 uint64_t ivs_rx_unknown_protocol; /* rupp */ 633 uint64_t ivs_tx_bytes; /* gotc */ 634 uint64_t ivs_tx_unicast; /* uptc */ 635 uint64_t ivs_tx_multicast; /* mptc */ 636 uint64_t ivs_tx_broadcast; /* bptc */ 637 uint64_t ivs_tx_errors; /* tepc */ 638 } i40e_vsi_stats_t; 639 640 typedef struct i40e_vsi_kstats { 641 kstat_named_t ivk_rx_bytes; 642 kstat_named_t ivk_rx_unicast; 643 kstat_named_t ivk_rx_multicast; 644 kstat_named_t ivk_rx_broadcast; 645 kstat_named_t ivk_rx_discards; 646 kstat_named_t ivk_rx_unknown_protocol; 647 kstat_named_t ivk_tx_bytes; 648 kstat_named_t ivk_tx_unicast; 649 kstat_named_t ivk_tx_multicast; 650 kstat_named_t ivk_tx_broadcast; 651 kstat_named_t ivk_tx_errors; 652 } i40e_vsi_kstats_t; 653 654 /* 655 * For pf statistics, we opt not to use the standard statistics as defined by 656 * the Intel common code. This also currently combines statistics that are 657 * global across the entire device. 658 */ 659 typedef struct i40e_pf_stats { 660 uint64_t ips_rx_bytes; /* gorc */ 661 uint64_t ips_rx_unicast; /* uprc */ 662 uint64_t ips_rx_multicast; /* mprc */ 663 uint64_t ips_rx_broadcast; /* bprc */ 664 uint64_t ips_tx_bytes; /* gotc */ 665 uint64_t ips_tx_unicast; /* uptc */ 666 uint64_t ips_tx_multicast; /* mptc */ 667 uint64_t ips_tx_broadcast; /* bptc */ 668 669 uint64_t ips_rx_size_64; /* prc64 */ 670 uint64_t ips_rx_size_127; /* prc127 */ 671 uint64_t ips_rx_size_255; /* prc255 */ 672 uint64_t ips_rx_size_511; /* prc511 */ 673 uint64_t ips_rx_size_1023; /* prc1023 */ 674 uint64_t ips_rx_size_1522; /* prc1522 */ 675 uint64_t ips_rx_size_9522; /* prc9522 */ 676 677 uint64_t ips_tx_size_64; /* ptc64 */ 678 uint64_t ips_tx_size_127; /* ptc127 */ 679 uint64_t ips_tx_size_255; /* ptc255 */ 680 uint64_t ips_tx_size_511; /* ptc511 */ 681 uint64_t ips_tx_size_1023; /* ptc1023 */ 682 uint64_t ips_tx_size_1522; /* ptc1522 */ 683 uint64_t ips_tx_size_9522; /* ptc9522 */ 684 685 uint64_t ips_link_xon_rx; /* lxonrxc */ 686 uint64_t ips_link_xoff_rx; /* lxoffrxc */ 687 uint64_t ips_link_xon_tx; /* lxontxc */ 688 uint64_t ips_link_xoff_tx; /* lxofftxc */ 689 uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */ 690 uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */ 691 uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */ 692 uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */ 693 uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 694 695 uint64_t ips_crc_errors; /* crcerrs */ 696 uint64_t ips_illegal_bytes; /* illerrc */ 697 uint64_t ips_mac_local_faults; /* mlfc */ 698 uint64_t ips_mac_remote_faults; /* mrfc */ 699 uint64_t ips_rx_length_errors; /* rlec */ 700 uint64_t ips_rx_undersize; /* ruc */ 701 uint64_t ips_rx_fragments; /* rfc */ 702 uint64_t ips_rx_oversize; /* roc */ 703 uint64_t ips_rx_jabber; /* rjc */ 704 uint64_t ips_rx_discards; /* rdpc */ 705 uint64_t ips_rx_vm_discards; /* ldpc */ 706 uint64_t ips_rx_short_discards; /* mspdc */ 707 uint64_t ips_tx_dropped_link_down; /* tdold */ 708 uint64_t ips_rx_unknown_protocol; /* rupp */ 709 uint64_t ips_rx_err1; /* rxerr1 */ 710 uint64_t ips_rx_err2; /* rxerr2 */ 711 } i40e_pf_stats_t; 712 713 typedef struct i40e_pf_kstats { 714 kstat_named_t ipk_rx_bytes; /* gorc */ 715 kstat_named_t ipk_rx_unicast; /* uprc */ 716 kstat_named_t ipk_rx_multicast; /* mprc */ 717 kstat_named_t ipk_rx_broadcast; /* bprc */ 718 kstat_named_t ipk_tx_bytes; /* gotc */ 719 kstat_named_t ipk_tx_unicast; /* uptc */ 720 kstat_named_t ipk_tx_multicast; /* mptc */ 721 kstat_named_t ipk_tx_broadcast; /* bptc */ 722 723 kstat_named_t ipk_rx_size_64; /* prc64 */ 724 kstat_named_t ipk_rx_size_127; /* prc127 */ 725 kstat_named_t ipk_rx_size_255; /* prc255 */ 726 kstat_named_t ipk_rx_size_511; /* prc511 */ 727 kstat_named_t ipk_rx_size_1023; /* prc1023 */ 728 kstat_named_t ipk_rx_size_1522; /* prc1522 */ 729 kstat_named_t ipk_rx_size_9522; /* prc9522 */ 730 731 kstat_named_t ipk_tx_size_64; /* ptc64 */ 732 kstat_named_t ipk_tx_size_127; /* ptc127 */ 733 kstat_named_t ipk_tx_size_255; /* ptc255 */ 734 kstat_named_t ipk_tx_size_511; /* ptc511 */ 735 kstat_named_t ipk_tx_size_1023; /* ptc1023 */ 736 kstat_named_t ipk_tx_size_1522; /* ptc1522 */ 737 kstat_named_t ipk_tx_size_9522; /* ptc9522 */ 738 739 kstat_named_t ipk_link_xon_rx; /* lxonrxc */ 740 kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */ 741 kstat_named_t ipk_link_xon_tx; /* lxontxc */ 742 kstat_named_t ipk_link_xoff_tx; /* lxofftxc */ 743 kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */ 744 kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */ 745 kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */ 746 kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */ 747 kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 748 749 kstat_named_t ipk_crc_errors; /* crcerrs */ 750 kstat_named_t ipk_illegal_bytes; /* illerrc */ 751 kstat_named_t ipk_mac_local_faults; /* mlfc */ 752 kstat_named_t ipk_mac_remote_faults; /* mrfc */ 753 kstat_named_t ipk_rx_length_errors; /* rlec */ 754 kstat_named_t ipk_rx_undersize; /* ruc */ 755 kstat_named_t ipk_rx_fragments; /* rfc */ 756 kstat_named_t ipk_rx_oversize; /* roc */ 757 kstat_named_t ipk_rx_jabber; /* rjc */ 758 kstat_named_t ipk_rx_discards; /* rdpc */ 759 kstat_named_t ipk_rx_vm_discards; /* ldpc */ 760 kstat_named_t ipk_rx_short_discards; /* mspdc */ 761 kstat_named_t ipk_tx_dropped_link_down; /* tdold */ 762 kstat_named_t ipk_rx_unknown_protocol; /* rupp */ 763 kstat_named_t ipk_rx_err1; /* rxerr1 */ 764 kstat_named_t ipk_rx_err2; /* rxerr2 */ 765 } i40e_pf_kstats_t; 766 767 /* 768 * Resources that are pooled and specific to a given i40e_t. 769 */ 770 typedef struct i40e_func_rsrc { 771 uint_t ifr_nrx_queue; 772 uint_t ifr_nrx_queue_used; 773 uint_t ifr_ntx_queue; 774 uint_t ifr_trx_queue_used; 775 uint_t ifr_nvsis; 776 uint_t ifr_nvsis_used; 777 uint_t ifr_nmacfilt; 778 uint_t ifr_nmacfilt_used; 779 uint_t ifr_nmcastfilt; 780 uint_t ifr_nmcastfilt_used; 781 } i40e_func_rsrc_t; 782 783 typedef struct i40e_vsi { 784 uint16_t iv_seid; 785 uint16_t iv_number; 786 kstat_t *iv_kstats; 787 i40e_vsi_stats_t iv_stats; 788 uint16_t iv_stats_id; 789 } i40e_vsi_t; 790 791 /* 792 * While irg_index and irg_grp_hdl aren't used anywhere, they are 793 * still useful for debugging. 794 */ 795 typedef struct i40e_rx_group { 796 uint32_t irg_index; /* index in i40e_rx_groups[] */ 797 uint16_t irg_vsi_seid; /* SEID of VSI for this group */ 798 mac_group_handle_t irg_grp_hdl; /* handle to mac_group_t */ 799 struct i40e *irg_i40e; /* ref to i40e_t */ 800 } i40e_rx_group_t; 801 802 /* 803 * Main i40e per-instance state. 804 */ 805 typedef struct i40e { 806 list_node_t i40e_glink; /* Global list link */ 807 list_node_t i40e_dlink; /* Device list link */ 808 kmutex_t i40e_general_lock; /* General device lock */ 809 810 /* 811 * General Data and management 812 */ 813 dev_info_t *i40e_dip; 814 int i40e_instance; 815 int i40e_fm_capabilities; 816 uint_t i40e_state; 817 i40e_attach_state_t i40e_attach_progress; 818 mac_handle_t i40e_mac_hdl; 819 ddi_periodic_t i40e_periodic_id; 820 821 /* 822 * Pointers to common code data structures and memory for the common 823 * code. 824 */ 825 struct i40e_hw i40e_hw_space; 826 struct i40e_osdep i40e_osdep_space; 827 struct i40e_aq_get_phy_abilities_resp i40e_phy; 828 void *i40e_aqbuf; 829 830 #define I40E_DEF_VSI_IDX 0 831 #define I40E_DEF_VSI(i40e) ((i40e)->i40e_vsis[I40E_DEF_VSI_IDX]) 832 #define I40E_DEF_VSI_SEID(i40e) (I40E_DEF_VSI(i40e).iv_seid) 833 834 /* 835 * Device state, switch information, and resources. 836 */ 837 i40e_vsi_t i40e_vsis[I40E_GROUP_MAX]; 838 uint16_t i40e_mac_seid; /* SEID of physical MAC */ 839 uint16_t i40e_veb_seid; /* switch atop MAC (SEID) */ 840 uint16_t i40e_vsi_avail; /* VSIs avail to this PF */ 841 uint16_t i40e_vsi_used; /* VSIs used by this PF */ 842 struct i40e_device *i40e_device; 843 i40e_func_rsrc_t i40e_resources; 844 uint16_t i40e_switch_rsrc_alloc; 845 uint16_t i40e_switch_rsrc_actual; 846 i40e_switch_rsrc_t *i40e_switch_rsrcs; 847 i40e_uaddr_t *i40e_uaddrs; 848 i40e_maddr_t *i40e_maddrs; 849 int i40e_mcast_promisc_count; 850 boolean_t i40e_promisc_on; 851 link_state_t i40e_link_state; 852 uint32_t i40e_link_speed; /* In Mbps */ 853 link_duplex_t i40e_link_duplex; 854 uint_t i40e_sdu; 855 uint_t i40e_frame_max; 856 857 /* 858 * Transmit and receive information, tunables, and MAC info. 859 */ 860 i40e_trqpair_t *i40e_trqpairs; 861 boolean_t i40e_mr_enable; 862 uint_t i40e_num_trqpairs; /* total TRQPs (per PF) */ 863 uint_t i40e_num_trqpairs_per_vsi; /* TRQPs per VSI */ 864 uint_t i40e_other_itr; 865 866 i40e_rx_group_t *i40e_rx_groups; 867 uint_t i40e_num_rx_groups; 868 int i40e_num_rx_descs; 869 uint32_t i40e_rx_ring_size; 870 uint32_t i40e_rx_buf_size; 871 boolean_t i40e_rx_hcksum_enable; 872 uint32_t i40e_rx_dma_min; 873 uint32_t i40e_rx_limit_per_intr; 874 uint_t i40e_rx_itr; 875 876 int i40e_num_tx_descs; 877 uint32_t i40e_tx_ring_size; 878 uint32_t i40e_tx_buf_size; 879 uint32_t i40e_tx_block_thresh; 880 boolean_t i40e_tx_hcksum_enable; 881 boolean_t i40e_tx_lso_enable; 882 uint32_t i40e_tx_dma_min; 883 uint_t i40e_tx_itr; 884 885 /* 886 * Interrupt state 887 */ 888 uint_t i40e_intr_pri; 889 uint_t i40e_intr_force; 890 uint_t i40e_intr_type; 891 int i40e_intr_cap; 892 uint32_t i40e_intr_count; 893 uint32_t i40e_intr_count_max; 894 uint32_t i40e_intr_count_min; 895 size_t i40e_intr_size; 896 ddi_intr_handle_t *i40e_intr_handles; 897 ddi_cb_handle_t i40e_callback_handle; 898 899 /* 900 * DMA attributes. See i40e_transceiver.c for why we have copies of them 901 * in the i40e_t. 902 */ 903 ddi_dma_attr_t i40e_static_dma_attr; 904 ddi_dma_attr_t i40e_txbind_dma_attr; 905 ddi_dma_attr_t i40e_txbind_lso_dma_attr; 906 ddi_device_acc_attr_t i40e_desc_acc_attr; 907 ddi_device_acc_attr_t i40e_buf_acc_attr; 908 909 /* 910 * The following two fields are used to protect and keep track of 911 * outstanding, loaned buffers to MAC. If we have these, we can't 912 * detach as we have active DMA memory outstanding. 913 */ 914 kmutex_t i40e_rx_pending_lock; 915 kcondvar_t i40e_rx_pending_cv; 916 uint32_t i40e_rx_pending; 917 918 /* 919 * PF statistics and VSI statistics. 920 */ 921 kmutex_t i40e_stat_lock; 922 kstat_t *i40e_pf_kstat; 923 i40e_pf_stats_t i40e_pf_stat; 924 925 /* 926 * Misc. stats and counters that should maybe one day be kstats. 927 */ 928 uint64_t i40e_s_link_status_errs; 929 uint32_t i40e_s_link_status_lasterr; 930 931 /* 932 * LED information. Note this state is only modified in 933 * i40e_gld_set_led() which is protected by MAC's serializer lock. 934 */ 935 uint32_t i40e_led_status; 936 boolean_t i40e_led_saved; 937 938 /* DDI UFM handle */ 939 ddi_ufm_handle_t *i40e_ufmh; 940 } i40e_t; 941 942 /* 943 * The i40e_device represents a PCI device which encapsulates multiple physical 944 * functions which are represented as an i40e_t. This is used to track the use 945 * of pooled resources throughout all of the various devices. 946 */ 947 typedef struct i40e_device { 948 list_node_t id_link; 949 dev_info_t *id_parent; 950 uint_t id_pci_bus; 951 uint_t id_pci_device; 952 uint_t id_nfuncs; /* Total number of functions */ 953 uint_t id_nreg; /* Total number present */ 954 list_t id_i40e_list; /* List of i40e_t's registered */ 955 i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */ 956 uint_t id_rsrcs_alloc; /* Total allocated resources */ 957 uint_t id_rsrcs_act; /* Actual number of resources */ 958 } i40e_device_t; 959 960 /* Values for the interrupt forcing on the NIC. */ 961 #define I40E_INTR_NONE 0 962 #define I40E_INTR_MSIX 1 963 #define I40E_INTR_MSI 2 964 #define I40E_INTR_LEGACY 3 965 966 /* Hint that we don't want to do any polling... */ 967 #define I40E_POLL_NULL -1 968 969 /* 970 * Logging functions. 971 */ 972 /*PRINTFLIKE2*/ 973 extern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 974 /*PRINTFLIKE2*/ 975 extern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 976 /*PRINTFLIKE2*/ 977 extern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 978 979 /* 980 * General link handling functions. 981 */ 982 extern void i40e_link_check(i40e_t *); 983 extern void i40e_update_mtu(i40e_t *); 984 985 /* 986 * FMA functions. 987 */ 988 extern int i40e_check_acc_handle(ddi_acc_handle_t); 989 extern int i40e_check_dma_handle(ddi_dma_handle_t); 990 extern void i40e_fm_ereport(i40e_t *, char *); 991 992 /* 993 * Interrupt handlers and interrupt handler setup. 994 */ 995 extern void i40e_intr_chip_init(i40e_t *); 996 extern void i40e_intr_chip_fini(i40e_t *); 997 extern uint_t i40e_intr_msix(void *, void *); 998 extern uint_t i40e_intr_msi(void *, void *); 999 extern uint_t i40e_intr_legacy(void *, void *); 1000 extern void i40e_intr_io_enable_all(i40e_t *); 1001 extern void i40e_intr_io_disable_all(i40e_t *); 1002 extern void i40e_intr_io_clear_cause(i40e_t *); 1003 extern void i40e_intr_rx_queue_disable(i40e_trqpair_t *); 1004 extern void i40e_intr_rx_queue_enable(i40e_trqpair_t *); 1005 extern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t); 1006 1007 /* 1008 * Receive-side functions 1009 */ 1010 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int); 1011 extern mblk_t *i40e_ring_rx_poll(void *, int); 1012 extern void i40e_rx_recycle(caddr_t); 1013 1014 /* 1015 * Transmit-side functions 1016 */ 1017 mblk_t *i40e_ring_tx(void *, mblk_t *); 1018 extern void i40e_tx_recycle_ring(i40e_trqpair_t *); 1019 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *); 1020 1021 /* 1022 * Statistics functions. 1023 */ 1024 extern boolean_t i40e_stats_init(i40e_t *); 1025 extern void i40e_stats_fini(i40e_t *); 1026 extern boolean_t i40e_stat_vsi_init(i40e_t *, uint_t); 1027 extern void i40e_stat_vsi_fini(i40e_t *, uint_t); 1028 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *); 1029 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *); 1030 extern int i40e_m_stat(void *, uint_t, uint64_t *); 1031 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1032 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1033 1034 /* 1035 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code. 1036 */ 1037 extern boolean_t i40e_register_mac(i40e_t *); 1038 extern boolean_t i40e_start(i40e_t *, boolean_t); 1039 extern void i40e_stop(i40e_t *, boolean_t); 1040 1041 /* 1042 * DMA & buffer functions and attributes 1043 */ 1044 extern void i40e_init_dma_attrs(i40e_t *, boolean_t); 1045 extern boolean_t i40e_alloc_ring_mem(i40e_t *); 1046 extern void i40e_free_ring_mem(i40e_t *, boolean_t); 1047 1048 #ifdef __cplusplus 1049 } 1050 #endif 1051 1052 #endif /* _I40E_SW_H */ 1053