1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved. 14 * Copyright 2016 Joyent, Inc. 15 */ 16 17 /* 18 * Please see i40e_main.c for an introduction to the device driver, its layout, 19 * and more. 20 */ 21 22 #ifndef _I40E_SW_H 23 #define _I40E_SW_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #include <sys/types.h> 30 #include <sys/conf.h> 31 #include <sys/debug.h> 32 #include <sys/stropts.h> 33 #include <sys/stream.h> 34 #include <sys/strsun.h> 35 #include <sys/strlog.h> 36 #include <sys/kmem.h> 37 #include <sys/stat.h> 38 #include <sys/kstat.h> 39 #include <sys/modctl.h> 40 #include <sys/errno.h> 41 #include <sys/dlpi.h> 42 #include <sys/mac_provider.h> 43 #include <sys/mac_ether.h> 44 #include <sys/vlan.h> 45 #include <sys/ddi.h> 46 #include <sys/sunddi.h> 47 #include <sys/pci.h> 48 #include <sys/pcie.h> 49 #include <sys/sdt.h> 50 #include <sys/ethernet.h> 51 #include <sys/pattr.h> 52 #include <sys/strsubr.h> 53 #include <sys/netlb.h> 54 #include <sys/random.h> 55 #include <inet/common.h> 56 #include <inet/tcp.h> 57 #include <inet/ip.h> 58 #include <inet/mi.h> 59 #include <inet/nd.h> 60 #include <netinet/udp.h> 61 #include <netinet/sctp.h> 62 #include <sys/bitmap.h> 63 #include <sys/cpuvar.h> 64 #include <sys/ddifm.h> 65 #include <sys/fm/protocol.h> 66 #include <sys/fm/util.h> 67 #include <sys/disp.h> 68 #include <sys/fm/io/ddi.h> 69 #include <sys/list.h> 70 #include <sys/debug.h> 71 #include <sys/sdt.h> 72 #include "i40e_type.h" 73 #include "i40e_osdep.h" 74 #include "i40e_prototype.h" 75 #include "i40e_xregs.h" 76 77 #define I40E_MODULE_NAME "i40e" 78 79 #define I40E_ADAPTER_REGSET 1 80 81 /* 82 * Configuration constants. Note that the hardware defines a minimum bound of 32 83 * descriptors and requires that the programming of the descriptor lengths be 84 * aligned in units of 32 descriptors. 85 */ 86 #define I40E_MIN_TX_RING_SIZE 64 87 #define I40E_MAX_TX_RING_SIZE 4096 88 #define I40E_DEF_TX_RING_SIZE 1024 89 90 #define I40E_MIN_RX_RING_SIZE 64 91 #define I40E_MAX_RX_RING_SIZE 4096 92 #define I40E_DEF_RX_RING_SIZE 1024 93 94 #define I40E_DESC_ALIGN 32 95 96 /* 97 * Sizes used for asynchronous processing of the adminq. We allocate a fixed 98 * size buffer for each instance of the device during attach time, rather than 99 * allocating and freeing one during interrupt processing. 100 * 101 * We also define the descriptor size of the admin queue here. 102 */ 103 #define I40E_ADMINQ_BUFSZ 4096 104 #define I40E_MAX_ADMINQ_SIZE 1024 105 #define I40E_DEF_ADMINQ_SIZE 256 106 107 /* 108 * Note, while the min and maximum values are based upon the sizing of the ring 109 * itself, the default is taken from ixgbe without much thought. It's basically 110 * been cargo culted. See i40e_transceiver.c for a bit more information. 111 */ 112 #define I40E_MIN_RX_LIMIT_PER_INTR 16 113 #define I40E_MAX_RX_LIMIT_PER_INTR 4096 114 #define I40E_DEF_RX_LIMIT_PER_INTR 256 115 116 /* 117 * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728. 118 * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN 119 * header size (18 bytes) to get the actual maximum frame we can use. If 120 * different adapters end up with different sizes, we should make this value a 121 * bit more dynamic. 122 */ 123 #define I40E_MAX_MTU 9706 124 #define I40E_MIN_MTU ETHERMIN 125 #define I40E_DEF_MTU ETHERMTU 126 127 /* 128 * Interrupt throttling related values. Interrupt throttling values are defined 129 * in two microsecond increments. Note that a value of zero basically says do no 130 * ITR activity. A helpful way to think about these is that setting the ITR to a 131 * value will allow a certain number of interrupts per second. 132 * 133 * Our default values for RX allow 20k interrupts per second while our default 134 * values for TX allow for 5k interrupts per second. For other class interrupts, 135 * we limit ourselves to a rate of 2k/s. 136 */ 137 #define I40E_MIN_ITR 0x0000 138 #define I40E_MAX_ITR 0x0FF0 139 #define I40E_DEF_RX_ITR 0x0019 140 #define I40E_DEF_TX_ITR 0x0064 141 #define I40E_DEF_OTHER_ITR 0x00FA 142 143 /* 144 * Indexes into the three ITR registers that we have. 145 */ 146 typedef enum i40e_itr_index { 147 I40E_ITR_INDEX_RX = 0x0, 148 I40E_ITR_INDEX_TX = 0x1, 149 I40E_ITR_INDEX_OTHER = 0x2, 150 I40E_ITR_INDEX_NONE = 0x3 151 } i40e_itr_index_t; 152 153 154 /* 155 * Table 1-5 of the PRM notes that LSO supports up to 256 KB. 156 */ 157 #define I40E_LSO_MAXLEN (256 * 1024) 158 159 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */ 160 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */ 161 162 /* 163 * All the other queue types for are defined by the common code. However, this 164 * is the constant to indicate that it's terminated. 165 */ 166 #define I40E_QUEUE_TYPE_EOL 0x7FF 167 168 /* 169 * See the comments in i40e_transceiver.c as to the purpose of this value and 170 * how it's used to ensure that the IP header is eventually aligned when it's 171 * received by the OS. 172 */ 173 #define I40E_BUF_IPHDR_ALIGNMENT 2 174 175 /* 176 * The XL710 controller has a limit of eight buffers being allowed to be used 177 * for the transmission of a single frame. This is defined in 8.4.1 - Transmit 178 * Packet in System Memory. 179 */ 180 #define I40E_TX_MAX_COOKIE 8 181 182 /* 183 * Sizing to determine the amount of available descriptors at which we'll 184 * consider ourselves blocked. Also, when we have these available, we'll then 185 * consider ourselves available to transmit to MAC again. Strictly speaking, the 186 * MAX is based on the ring size. The default sizing is based on ixgbe. 187 */ 188 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE 189 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH 190 191 /* 192 * Sizing for DMA thresholds. These are used to indicate whether or not we 193 * should perform a bcopy or a DMA binding of a given message block. The range 194 * allows for setting things such that we'll always do a bcopy (a high value) or 195 * always perform a DMA binding (a low value). 196 */ 197 #define I40E_MIN_RX_DMA_THRESH 0 198 #define I40E_DEF_RX_DMA_THRESH 256 199 #define I40E_MAX_RX_DMA_THRESH INT32_MAX 200 201 #define I40E_MIN_TX_DMA_THRESH 0 202 #define I40E_DEF_TX_DMA_THRESH 256 203 #define I40E_MAX_TX_DMA_THRESH INT32_MAX 204 205 /* 206 * Resource sizing counts. There are various aspects of hardware where we may 207 * have some variable number of elements that we need to handle. Such as the 208 * hardware capabilities and switch capacities. We cannot know a priori how many 209 * elements to do, so instead we take a starting guess and then will grow it up 210 * to an upper bound on a number of elements, to limit memory consumption in 211 * case of a hardware bug. 212 */ 213 #define I40E_HW_CAP_DEFAULT 40 214 #define I40E_SWITCH_CAP_DEFAULT 25 215 216 /* 217 * Host Memory Context related constants. 218 */ 219 #define I40E_HMC_RX_CTX_UNIT 128 220 #define I40E_HMC_RX_DBUFF_MIN 1024 221 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128) 222 #define I40E_HMC_RX_DTYPE_NOSPLIT 0 223 #define I40E_HMC_RX_DSIZE_32BYTE 1 224 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1 225 #define I40E_HMC_RX_FC_DISABLE 0 226 #define I40E_HMC_RX_L2TAGORDER 1 227 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0 228 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0 229 #define I40E_HMC_RX_TPH_DISABLE 0 230 #define I40E_HMC_RX_LOWRXQ_NOINTR 0 231 #define I40E_HMC_RX_PREFENA 1 232 233 #define I40E_HMC_TX_CTX_UNIT 128 234 #define I40E_HMC_TX_NEW_CONTEXT 1 235 #define I40E_HMC_TX_FC_DISABLE 0 236 #define I40E_HMC_TX_TS_DISABLE 0 237 #define I40E_HMC_TX_FD_DISABLE 0 238 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0 239 #define I40E_HMC_TX_WB_ENABLE 1 240 #define I40E_HMC_TX_TPH_DISABLE 0 241 242 /* 243 * Whenever we establish and create a VSI, we need to assign some number of 244 * queues that it's allowed to access from the PF. Because we only have a single 245 * VSI per PF at this time, we assign it all the queues. 246 * 247 * Many of the devices support what's called Data-center Bridging. Which is a 248 * feature that we don't have much use of at this time. However, we still need 249 * to fill in this information. We follow the guidance of the note in Table 7-80 250 * which talks about bytes 62-77. It says that if we don't want to assign 251 * anything to traffic classes, we should set the field to zero. Effectively 252 * this means that everything in the system is assigned to traffic class zero. 253 */ 254 #define I40E_ASSIGN_ALL_QUEUES 0 255 #define I40E_TRAFFIC_CLASS_NO_QUEUES 0 256 257 /* 258 * This defines the error mask that we care about from rx descriptors. Currently 259 * we're only concerned with the general errors and oversize errors. 260 */ 261 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \ 262 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)) 263 264 /* 265 * Property sizing macros for firmware versions, etc. They need to be large 266 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x. 267 */ 268 #define I40E_DDI_PROP_LEN 64 269 270 /* 271 * We currently consolidate some overrides that we use in the code here. These 272 * will be gone in the fullness of time, but as we're bringing up the device, 273 * this is what we use. 274 */ 275 #define I40E_GROUP_MAX 1 276 #define I40E_TRQPAIR_MAX 1 277 278 #define I40E_GROUP_NOMSIX 1 279 #define I40E_TRQPAIR_NOMSIX 1 280 281 /* 282 * It seems reasonable to cast this to void because the only reason that we 283 * should be getting a DDI_FAILURE is due to the fact that we specify addresses 284 * out of range. Because we specify no offset or address, it shouldn't happen. 285 */ 286 #ifdef DEBUG 287 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \ 288 (handle)->dmab_dma_handle, 0, 0, \ 289 (flag))) 290 #else /* !DEBUG */ 291 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \ 292 (handle)->dmab_dma_handle, 0, 0, \ 293 (flag))) 294 #endif /* DEBUG */ 295 296 /* 297 * Constants related to ring startup and teardown. These refer to the amount of 298 * time that we're willing to wait for a ring to spin up and spin down. 299 */ 300 #define I40E_RING_WAIT_NTRIES 10 301 #define I40E_RING_WAIT_PAUSE 10 /* ms */ 302 303 /* 304 * Bit flags for attach_progress 305 */ 306 typedef enum i40e_attach_state { 307 I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */ 308 I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */ 309 I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */ 310 I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */ 311 I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */ 312 I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */ 313 I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */ 314 I40E_ATTACH_INIT = 0x0080, /* Device initialized */ 315 I40E_ATTACH_STATS = 0x0200, /* Kstats created */ 316 I40E_ATTACH_MAC = 0x0800, /* MAC registered */ 317 I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */ 318 I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */ 319 I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */ 320 } i40e_attach_state_t; 321 322 323 /* 324 * State flags that what's going on in in the device. Some of these state flags 325 * indicate some aspirational work that needs to happen in the driver. 326 * 327 * I40E_UNKNOWN: The device has yet to be started. 328 * I40E_INITIALIZED: The device has been fully attached. 329 * I40E_STARTED: The device has come out of the GLDV3 start routine. 330 * I40E_SUSPENDED: The device is suspended and I/O among other things 331 * should not occur. This happens because of an actual 332 * DDI_SUSPEND or interrupt adjustments. 333 * I40E_STALL: The tx stall detection logic has found a stall. 334 * I40E_OVERTEMP: The device has encountered a temperature alarm. 335 * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we 336 * shouldn't be manipulating their state. 337 * I40E_ERROR: We've detected an FM error and degraded the device. 338 */ 339 typedef enum i40e_state { 340 I40E_UNKNOWN = 0x00, 341 I40E_INITIALIZED = 0x01, 342 I40E_STARTED = 0x02, 343 I40E_SUSPENDED = 0x04, 344 I40E_STALL = 0x08, 345 I40E_OVERTEMP = 0x20, 346 I40E_INTR_ADJUST = 0x40, 347 I40E_ERROR = 0x80 348 } i40e_state_t; 349 350 351 /* 352 * Definitions for common Intel things that we use and some slightly more usable 353 * names. 354 */ 355 typedef struct i40e_hw i40e_hw_t; 356 typedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t; 357 358 /* 359 * Handles and addresses of DMA buffers. 360 */ 361 typedef struct i40e_dma_buffer { 362 caddr_t dmab_address; /* Virtual address */ 363 uint64_t dmab_dma_address; /* DMA (Hardware) address */ 364 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */ 365 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */ 366 size_t dmab_size; /* Buffer size */ 367 size_t dmab_len; /* Data length in the buffer */ 368 } i40e_dma_buffer_t; 369 370 /* 371 * RX Control Block 372 */ 373 typedef struct i40e_rx_control_block { 374 mblk_t *rcb_mp; 375 uint32_t rcb_ref; 376 i40e_dma_buffer_t rcb_dma; 377 frtn_t rcb_free_rtn; 378 struct i40e_rx_data *rcb_rxd; 379 } i40e_rx_control_block_t; 380 381 typedef enum { 382 I40E_TX_NONE, 383 I40E_TX_COPY, 384 I40E_TX_DMA 385 } i40e_tx_type_t; 386 387 typedef struct i40e_tx_desc i40e_tx_desc_t; 388 typedef union i40e_32byte_rx_desc i40e_rx_desc_t; 389 390 typedef struct i40e_tx_control_block { 391 struct i40e_tx_control_block *tcb_next; 392 mblk_t *tcb_mp; 393 i40e_tx_type_t tcb_type; 394 ddi_dma_handle_t tcb_dma_handle; 395 i40e_dma_buffer_t tcb_dma; 396 } i40e_tx_control_block_t; 397 398 /* 399 * Receive ring data (used below). 400 */ 401 typedef struct i40e_rx_data { 402 struct i40e *rxd_i40e; 403 404 /* 405 * RX descriptor ring definitions 406 */ 407 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */ 408 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */ 409 uint32_t rxd_desc_next; /* Index of next rx desc */ 410 411 /* 412 * RX control block list definitions 413 */ 414 kmutex_t rxd_free_lock; /* Lock to protect free data */ 415 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */ 416 i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */ 417 i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */ 418 uint32_t rxd_rcb_free; /* Number of free rcbs */ 419 420 /* 421 * RX software ring settings 422 */ 423 uint32_t rxd_ring_size; /* Rx descriptor ring size */ 424 uint32_t rxd_free_list_size; /* Rx free list size */ 425 426 /* 427 * RX outstanding data. This is used to keep track of outstanding loaned 428 * descriptors after we've shut down receiving information. Note these 429 * are protected by the i40e_t`i40e_rx_pending_lock. 430 */ 431 uint32_t rxd_rcb_pending; 432 boolean_t rxd_shutdown; 433 } i40e_rx_data_t; 434 435 /* 436 * Structures for unicast and multicast addresses. Note that we keep the VSI id 437 * around for unicast addresses, since they may belong to different VSIs. 438 * However, since all multicast addresses belong to the default VSI, we don't 439 * duplicate that information. 440 */ 441 typedef struct i40e_uaddr { 442 uint8_t iua_mac[ETHERADDRL]; 443 int iua_vsi; 444 } i40e_uaddr_t; 445 446 typedef struct i40e_maddr { 447 uint8_t ima_mac[ETHERADDRL]; 448 } i40e_maddr_t; 449 450 /* 451 * Collection of RX statistics on a given queue. 452 */ 453 typedef struct i40e_rxq_stat { 454 /* 455 * The i40e hardware does not maintain statistics on a per-ring basis, 456 * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we 457 * need to maintain our own stats for packets and bytes. 458 */ 459 kstat_named_t irxs_bytes; /* Bytes in on queue */ 460 kstat_named_t irxs_packets; /* Packets in on queue */ 461 462 /* 463 * The following set of stats cover non-checksum data path issues. 464 */ 465 kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */ 466 kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */ 467 kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */ 468 kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */ 469 kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */ 470 471 /* 472 * The following set of statistics covers rx checksum related activity. 473 * These are all primarily set in i40e_rx_hcksum. If rx checksum 474 * activity is disabled, then these should all be zero. 475 */ 476 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */ 477 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */ 478 kstat_named_t irxs_hck_unknown; /* !pinfo.known */ 479 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */ 480 kstat_named_t irxs_hck_iperr; /* IPE error bit set */ 481 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */ 482 kstat_named_t irxs_hck_l4err; /* L4E error bit set */ 483 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */ 484 kstat_named_t irxs_hck_set; /* Total times we set cksum */ 485 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */ 486 } i40e_rxq_stat_t; 487 488 /* 489 * Collection of TX Statistics on a given queue 490 */ 491 typedef struct i40e_txq_stat { 492 kstat_named_t itxs_bytes; /* Bytes out on queue */ 493 kstat_named_t itxs_packets; /* Packets out on queue */ 494 kstat_named_t itxs_descriptors; /* Descriptors issued */ 495 kstat_named_t itxs_recycled; /* Descriptors reclaimed */ 496 /* 497 * Various failure conditions. 498 */ 499 kstat_named_t itxs_hck_meoifail; /* ether offload failures */ 500 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */ 501 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */ 502 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */ 503 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */ 504 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */ 505 506 kstat_named_t itxs_err_notcb; /* No tcb's available */ 507 kstat_named_t itxs_err_nodescs; /* No tcb's available */ 508 kstat_named_t itxs_err_context; /* Total context failures */ 509 510 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */ 511 } i40e_txq_stat_t; 512 513 /* 514 * An instance of an XL710 transmit/receive queue pair. This currently 515 * represents a combination of both a transmit and receive ring, though they 516 * should really be split apart into separate logical structures. Unfortunately, 517 * during initial work we mistakenly joined them together. 518 */ 519 typedef struct i40e_trqpair { 520 struct i40e *itrq_i40e; 521 522 /* Receive-side structures. */ 523 kmutex_t itrq_rx_lock; 524 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */ 525 i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */ 526 uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */ 527 uint32_t itrq_index; /* Queue index in the PF */ 528 uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */ 529 530 /* Receive-side stats. */ 531 i40e_rxq_stat_t itrq_rxstat; 532 kstat_t *itrq_rxkstat; 533 534 /* Transmit-side structures. */ 535 kmutex_t itrq_tx_lock; 536 mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */ 537 uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */ 538 boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */ 539 540 /* 541 * TX data sizing 542 */ 543 uint32_t itrq_tx_ring_size; 544 uint32_t itrq_tx_free_list_size; 545 546 /* 547 * TX descriptor ring data 548 */ 549 i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */ 550 i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */ 551 volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */ 552 uint32_t itrq_desc_head; /* Last index hw freed */ 553 uint32_t itrq_desc_tail; /* Index of next free desc */ 554 uint32_t itrq_desc_free; /* Number of free descriptors */ 555 556 /* 557 * TX control block (tcb) data 558 */ 559 kmutex_t itrq_tcb_lock; 560 i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */ 561 i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */ 562 i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */ 563 uint32_t itrq_tcb_free; /* Count of free tcb */ 564 565 /* Transmit-side stats. */ 566 i40e_txq_stat_t itrq_txstat; 567 kstat_t *itrq_txkstat; 568 569 } i40e_trqpair_t; 570 571 /* 572 * VSI statistics. 573 * 574 * This mirrors the i40e_eth_stats structure but transforms it into a kstat. 575 * Note that the stock statistic structure also includes entries for tx 576 * discards. However, this is not actually implemented for the VSI (see Table 577 * 7-221), hence why we don't include the member which would always have a value 578 * of zero. This choice was made to minimize confusion to someone looking at 579 * these, as a value of zero does not necessarily equate to the fact that it's 580 * not implemented. 581 */ 582 typedef struct i40e_vsi_stats { 583 uint64_t ivs_rx_bytes; /* gorc */ 584 uint64_t ivs_rx_unicast; /* uprc */ 585 uint64_t ivs_rx_multicast; /* mprc */ 586 uint64_t ivs_rx_broadcast; /* bprc */ 587 uint64_t ivs_rx_discards; /* rdpc */ 588 uint64_t ivs_rx_unknown_protocol; /* rupp */ 589 uint64_t ivs_tx_bytes; /* gotc */ 590 uint64_t ivs_tx_unicast; /* uptc */ 591 uint64_t ivs_tx_multicast; /* mptc */ 592 uint64_t ivs_tx_broadcast; /* bptc */ 593 uint64_t ivs_tx_errors; /* tepc */ 594 } i40e_vsi_stats_t; 595 596 typedef struct i40e_vsi_kstats { 597 kstat_named_t ivk_rx_bytes; 598 kstat_named_t ivk_rx_unicast; 599 kstat_named_t ivk_rx_multicast; 600 kstat_named_t ivk_rx_broadcast; 601 kstat_named_t ivk_rx_discards; 602 kstat_named_t ivk_rx_unknown_protocol; 603 kstat_named_t ivk_tx_bytes; 604 kstat_named_t ivk_tx_unicast; 605 kstat_named_t ivk_tx_multicast; 606 kstat_named_t ivk_tx_broadcast; 607 kstat_named_t ivk_tx_errors; 608 } i40e_vsi_kstats_t; 609 610 /* 611 * For pf statistics, we opt not to use the standard statistics as defined by 612 * the Intel common code. This also currently combines statistics that are 613 * global across the entire device. 614 */ 615 typedef struct i40e_pf_stats { 616 uint64_t ips_rx_bytes; /* gorc */ 617 uint64_t ips_rx_unicast; /* uprc */ 618 uint64_t ips_rx_multicast; /* mprc */ 619 uint64_t ips_rx_broadcast; /* bprc */ 620 uint64_t ips_tx_bytes; /* gotc */ 621 uint64_t ips_tx_unicast; /* uptc */ 622 uint64_t ips_tx_multicast; /* mptc */ 623 uint64_t ips_tx_broadcast; /* bptc */ 624 625 uint64_t ips_rx_size_64; /* prc64 */ 626 uint64_t ips_rx_size_127; /* prc127 */ 627 uint64_t ips_rx_size_255; /* prc255 */ 628 uint64_t ips_rx_size_511; /* prc511 */ 629 uint64_t ips_rx_size_1023; /* prc1023 */ 630 uint64_t ips_rx_size_1522; /* prc1522 */ 631 uint64_t ips_rx_size_9522; /* prc9522 */ 632 633 uint64_t ips_tx_size_64; /* ptc64 */ 634 uint64_t ips_tx_size_127; /* ptc127 */ 635 uint64_t ips_tx_size_255; /* ptc255 */ 636 uint64_t ips_tx_size_511; /* ptc511 */ 637 uint64_t ips_tx_size_1023; /* ptc1023 */ 638 uint64_t ips_tx_size_1522; /* ptc1522 */ 639 uint64_t ips_tx_size_9522; /* ptc9522 */ 640 641 uint64_t ips_link_xon_rx; /* lxonrxc */ 642 uint64_t ips_link_xoff_rx; /* lxoffrxc */ 643 uint64_t ips_link_xon_tx; /* lxontxc */ 644 uint64_t ips_link_xoff_tx; /* lxofftxc */ 645 uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */ 646 uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */ 647 uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */ 648 uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */ 649 uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 650 651 uint64_t ips_crc_errors; /* crcerrs */ 652 uint64_t ips_illegal_bytes; /* illerrc */ 653 uint64_t ips_mac_local_faults; /* mlfc */ 654 uint64_t ips_mac_remote_faults; /* mrfc */ 655 uint64_t ips_rx_length_errors; /* rlec */ 656 uint64_t ips_rx_undersize; /* ruc */ 657 uint64_t ips_rx_fragments; /* rfc */ 658 uint64_t ips_rx_oversize; /* roc */ 659 uint64_t ips_rx_jabber; /* rjc */ 660 uint64_t ips_rx_discards; /* rdpc */ 661 uint64_t ips_rx_vm_discards; /* ldpc */ 662 uint64_t ips_rx_short_discards; /* mspdc */ 663 uint64_t ips_tx_dropped_link_down; /* tdold */ 664 uint64_t ips_rx_unknown_protocol; /* rupp */ 665 uint64_t ips_rx_err1; /* rxerr1 */ 666 uint64_t ips_rx_err2; /* rxerr2 */ 667 } i40e_pf_stats_t; 668 669 typedef struct i40e_pf_kstats { 670 kstat_named_t ipk_rx_bytes; /* gorc */ 671 kstat_named_t ipk_rx_unicast; /* uprc */ 672 kstat_named_t ipk_rx_multicast; /* mprc */ 673 kstat_named_t ipk_rx_broadcast; /* bprc */ 674 kstat_named_t ipk_tx_bytes; /* gotc */ 675 kstat_named_t ipk_tx_unicast; /* uptc */ 676 kstat_named_t ipk_tx_multicast; /* mptc */ 677 kstat_named_t ipk_tx_broadcast; /* bptc */ 678 679 kstat_named_t ipk_rx_size_64; /* prc64 */ 680 kstat_named_t ipk_rx_size_127; /* prc127 */ 681 kstat_named_t ipk_rx_size_255; /* prc255 */ 682 kstat_named_t ipk_rx_size_511; /* prc511 */ 683 kstat_named_t ipk_rx_size_1023; /* prc1023 */ 684 kstat_named_t ipk_rx_size_1522; /* prc1522 */ 685 kstat_named_t ipk_rx_size_9522; /* prc9522 */ 686 687 kstat_named_t ipk_tx_size_64; /* ptc64 */ 688 kstat_named_t ipk_tx_size_127; /* ptc127 */ 689 kstat_named_t ipk_tx_size_255; /* ptc255 */ 690 kstat_named_t ipk_tx_size_511; /* ptc511 */ 691 kstat_named_t ipk_tx_size_1023; /* ptc1023 */ 692 kstat_named_t ipk_tx_size_1522; /* ptc1522 */ 693 kstat_named_t ipk_tx_size_9522; /* ptc9522 */ 694 695 kstat_named_t ipk_link_xon_rx; /* lxonrxc */ 696 kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */ 697 kstat_named_t ipk_link_xon_tx; /* lxontxc */ 698 kstat_named_t ipk_link_xoff_tx; /* lxofftxc */ 699 kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */ 700 kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */ 701 kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */ 702 kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */ 703 kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 704 705 kstat_named_t ipk_crc_errors; /* crcerrs */ 706 kstat_named_t ipk_illegal_bytes; /* illerrc */ 707 kstat_named_t ipk_mac_local_faults; /* mlfc */ 708 kstat_named_t ipk_mac_remote_faults; /* mrfc */ 709 kstat_named_t ipk_rx_length_errors; /* rlec */ 710 kstat_named_t ipk_rx_undersize; /* ruc */ 711 kstat_named_t ipk_rx_fragments; /* rfc */ 712 kstat_named_t ipk_rx_oversize; /* roc */ 713 kstat_named_t ipk_rx_jabber; /* rjc */ 714 kstat_named_t ipk_rx_discards; /* rdpc */ 715 kstat_named_t ipk_rx_vm_discards; /* ldpc */ 716 kstat_named_t ipk_rx_short_discards; /* mspdc */ 717 kstat_named_t ipk_tx_dropped_link_down; /* tdold */ 718 kstat_named_t ipk_rx_unknown_protocol; /* rupp */ 719 kstat_named_t ipk_rx_err1; /* rxerr1 */ 720 kstat_named_t ipk_rx_err2; /* rxerr2 */ 721 } i40e_pf_kstats_t; 722 723 /* 724 * Resources that are pooled and specific to a given i40e_t. 725 */ 726 typedef struct i40e_func_rsrc { 727 uint_t ifr_nrx_queue; 728 uint_t ifr_nrx_queue_used; 729 uint_t ifr_ntx_queue; 730 uint_t ifr_trx_queue_used; 731 uint_t ifr_nvsis; 732 uint_t ifr_nvsis_used; 733 uint_t ifr_nmacfilt; 734 uint_t ifr_nmacfilt_used; 735 uint_t ifr_nmcastfilt; 736 uint_t ifr_nmcastfilt_used; 737 } i40e_func_rsrc_t; 738 739 /* 740 * Main i40e per-instance state. 741 */ 742 typedef struct i40e { 743 list_node_t i40e_glink; /* Global list link */ 744 list_node_t i40e_dlink; /* Device list link */ 745 kmutex_t i40e_general_lock; /* General device lock */ 746 747 /* 748 * General Data and management 749 */ 750 dev_info_t *i40e_dip; 751 int i40e_instance; 752 int i40e_fm_capabilities; 753 uint_t i40e_state; 754 i40e_attach_state_t i40e_attach_progress; 755 mac_handle_t i40e_mac_hdl; 756 ddi_periodic_t i40e_periodic_id; 757 758 /* 759 * Pointers to common code data structures and memory for the common 760 * code. 761 */ 762 struct i40e_hw i40e_hw_space; 763 struct i40e_osdep i40e_osdep_space; 764 struct i40e_aq_get_phy_abilities_resp i40e_phy; 765 void *i40e_aqbuf; 766 767 /* 768 * Device state, switch information, and resources. 769 */ 770 int i40e_vsi_id; 771 struct i40e_device *i40e_device; 772 i40e_func_rsrc_t i40e_resources; 773 uint16_t i40e_switch_rsrc_alloc; 774 uint16_t i40e_switch_rsrc_actual; 775 i40e_switch_rsrc_t *i40e_switch_rsrcs; 776 i40e_uaddr_t *i40e_uaddrs; 777 i40e_maddr_t *i40e_maddrs; 778 int i40e_mcast_promisc_count; 779 boolean_t i40e_promisc_on; 780 link_state_t i40e_link_state; 781 uint32_t i40e_link_speed; /* In Mbps */ 782 link_duplex_t i40e_link_duplex; 783 uint_t i40e_sdu; 784 uint_t i40e_frame_max; 785 786 /* 787 * Transmit and receive information, tunables, and MAC info. 788 */ 789 i40e_trqpair_t *i40e_trqpairs; 790 boolean_t i40e_mr_enable; 791 int i40e_num_trqpairs; 792 uint_t i40e_other_itr; 793 794 int i40e_num_rx_groups; 795 int i40e_num_rx_descs; 796 mac_group_handle_t i40e_rx_group_handle; 797 uint32_t i40e_rx_ring_size; 798 uint32_t i40e_rx_buf_size; 799 boolean_t i40e_rx_hcksum_enable; 800 uint32_t i40e_rx_dma_min; 801 uint32_t i40e_rx_limit_per_intr; 802 uint_t i40e_rx_itr; 803 804 int i40e_num_tx_descs; 805 uint32_t i40e_tx_ring_size; 806 uint32_t i40e_tx_buf_size; 807 uint32_t i40e_tx_block_thresh; 808 boolean_t i40e_tx_hcksum_enable; 809 uint32_t i40e_tx_dma_min; 810 uint_t i40e_tx_itr; 811 812 /* 813 * Interrupt state 814 * 815 * Note that the use of a single boolean_t for i40e_intr_poll isn't 816 * really the best design. When we have more than a single ring on the 817 * device working, we'll transition to using something more 818 * sophisticated. 819 */ 820 uint_t i40e_intr_pri; 821 uint_t i40e_intr_force; 822 uint_t i40e_intr_type; 823 int i40e_intr_cap; 824 uint32_t i40e_intr_count; 825 uint32_t i40e_intr_count_max; 826 uint32_t i40e_intr_count_min; 827 size_t i40e_intr_size; 828 ddi_intr_handle_t *i40e_intr_handles; 829 ddi_cb_handle_t i40e_callback_handle; 830 boolean_t i40e_intr_poll; 831 832 /* 833 * DMA attributes. See i40e_transceiver.c for why we have copies of them 834 * in the i40e_t. 835 */ 836 ddi_dma_attr_t i40e_static_dma_attr; 837 ddi_dma_attr_t i40e_txbind_dma_attr; 838 ddi_device_acc_attr_t i40e_desc_acc_attr; 839 ddi_device_acc_attr_t i40e_buf_acc_attr; 840 841 /* 842 * The following two fields are used to protect and keep track of 843 * outstanding, loaned buffers to MAC. If we have these, we can't 844 * detach as we have active DMA memory outstanding. 845 */ 846 kmutex_t i40e_rx_pending_lock; 847 kcondvar_t i40e_rx_pending_cv; 848 uint32_t i40e_rx_pending; 849 850 /* 851 * PF statistics and VSI statistics. 852 */ 853 kmutex_t i40e_stat_lock; 854 kstat_t *i40e_pf_kstat; 855 kstat_t *i40e_vsi_kstat; 856 i40e_pf_stats_t i40e_pf_stat; 857 i40e_vsi_stats_t i40e_vsi_stat; 858 uint16_t i40e_vsi_stat_id; 859 860 /* 861 * Misc. stats and counters that should maybe one day be kstats. 862 */ 863 uint64_t i40e_s_link_status_errs; 864 uint32_t i40e_s_link_status_lasterr; 865 } i40e_t; 866 867 /* 868 * The i40e_device represents a PCI device which encapsulates multiple physical 869 * functions which are represented as an i40e_t. This is used to track the use 870 * of pooled resources throughout all of the various devices. 871 */ 872 typedef struct i40e_device { 873 list_node_t id_link; 874 dev_info_t *id_parent; 875 uint_t id_pci_bus; 876 uint_t id_pci_device; 877 uint_t id_nfuncs; /* Total number of functions */ 878 uint_t id_nreg; /* Total number present */ 879 list_t id_i40e_list; /* List of i40e_t's registered */ 880 i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */ 881 uint_t id_rsrcs_alloc; /* Total allocated resources */ 882 uint_t id_rsrcs_act; /* Actual number of resources */ 883 } i40e_device_t; 884 885 /* Values for the interrupt forcing on the NIC. */ 886 #define I40E_INTR_NONE 0 887 #define I40E_INTR_MSIX 1 888 #define I40E_INTR_MSI 2 889 #define I40E_INTR_LEGACY 3 890 891 /* Hint that we don't want to do any polling... */ 892 #define I40E_POLL_NULL -1 893 894 /* 895 * Logging functions. 896 */ 897 /*PRINTFLIKE2*/ 898 extern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 899 /*PRINTFLIKE2*/ 900 extern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 901 /*PRINTFLIKE2*/ 902 extern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 903 904 /* 905 * General link handling functions. 906 */ 907 extern void i40e_link_check(i40e_t *); 908 extern void i40e_update_mtu(i40e_t *); 909 910 /* 911 * FMA functions. 912 */ 913 extern int i40e_check_acc_handle(ddi_acc_handle_t); 914 extern int i40e_check_dma_handle(ddi_dma_handle_t); 915 extern void i40e_fm_ereport(i40e_t *, char *); 916 917 /* 918 * Interrupt handlers and interrupt handler setup. 919 */ 920 extern void i40e_intr_chip_init(i40e_t *); 921 extern void i40e_intr_chip_fini(i40e_t *); 922 extern uint_t i40e_intr_msix(void *, void *); 923 extern uint_t i40e_intr_msi(void *, void *); 924 extern uint_t i40e_intr_legacy(void *, void *); 925 extern void i40e_intr_io_enable_all(i40e_t *); 926 extern void i40e_intr_io_disable_all(i40e_t *); 927 extern void i40e_intr_io_clear_cause(i40e_t *); 928 extern void i40e_intr_rx_queue_disable(i40e_t *, uint_t); 929 extern void i40e_intr_rx_queue_enable(i40e_t *, uint_t); 930 extern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t); 931 932 /* 933 * Receive-side functions 934 */ 935 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int); 936 extern mblk_t *i40e_ring_rx_poll(void *, int); 937 extern void i40e_rx_recycle(caddr_t); 938 939 /* 940 * Transmit-side functions 941 */ 942 mblk_t *i40e_ring_tx(void *, mblk_t *); 943 extern void i40e_tx_recycle_ring(i40e_trqpair_t *); 944 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *); 945 946 /* 947 * Statistics functions. 948 */ 949 extern boolean_t i40e_stats_init(i40e_t *); 950 extern void i40e_stats_fini(i40e_t *); 951 extern boolean_t i40e_stat_vsi_init(i40e_t *); 952 extern void i40e_stat_vsi_fini(i40e_t *); 953 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *); 954 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *); 955 extern int i40e_m_stat(void *, uint_t, uint64_t *); 956 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 957 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 958 959 /* 960 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code. 961 */ 962 extern boolean_t i40e_register_mac(i40e_t *); 963 extern boolean_t i40e_start(i40e_t *, boolean_t); 964 extern void i40e_stop(i40e_t *, boolean_t); 965 966 /* 967 * DMA & buffer functions and attributes 968 */ 969 extern void i40e_init_dma_attrs(i40e_t *, boolean_t); 970 extern boolean_t i40e_alloc_ring_mem(i40e_t *); 971 extern void i40e_free_ring_mem(i40e_t *, boolean_t); 972 973 #ifdef __cplusplus 974 } 975 #endif 976 977 #endif /* _I40E_SW_H */ 978