1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved. 14 * Copyright 2016 Joyent, Inc. 15 * Copyright 2017 Tegile Systems, Inc. All rights reserved. 16 */ 17 18 /* 19 * Please see i40e_main.c for an introduction to the device driver, its layout, 20 * and more. 21 */ 22 23 #ifndef _I40E_SW_H 24 #define _I40E_SW_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include <sys/types.h> 31 #include <sys/conf.h> 32 #include <sys/debug.h> 33 #include <sys/stropts.h> 34 #include <sys/stream.h> 35 #include <sys/strsun.h> 36 #include <sys/strlog.h> 37 #include <sys/kmem.h> 38 #include <sys/stat.h> 39 #include <sys/kstat.h> 40 #include <sys/modctl.h> 41 #include <sys/errno.h> 42 #include <sys/dlpi.h> 43 #include <sys/mac_provider.h> 44 #include <sys/mac_ether.h> 45 #include <sys/vlan.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/pci.h> 49 #include <sys/pcie.h> 50 #include <sys/sdt.h> 51 #include <sys/ethernet.h> 52 #include <sys/pattr.h> 53 #include <sys/strsubr.h> 54 #include <sys/netlb.h> 55 #include <sys/random.h> 56 #include <inet/common.h> 57 #include <inet/tcp.h> 58 #include <inet/ip.h> 59 #include <inet/mi.h> 60 #include <inet/nd.h> 61 #include <netinet/udp.h> 62 #include <netinet/sctp.h> 63 #include <sys/bitmap.h> 64 #include <sys/cpuvar.h> 65 #include <sys/ddifm.h> 66 #include <sys/fm/protocol.h> 67 #include <sys/fm/util.h> 68 #include <sys/disp.h> 69 #include <sys/fm/io/ddi.h> 70 #include <sys/list.h> 71 #include <sys/debug.h> 72 #include <sys/sdt.h> 73 #include "i40e_type.h" 74 #include "i40e_osdep.h" 75 #include "i40e_prototype.h" 76 #include "i40e_xregs.h" 77 78 #define I40E_MODULE_NAME "i40e" 79 80 #define I40E_ADAPTER_REGSET 1 81 82 /* 83 * Configuration constants. Note that the hardware defines a minimum bound of 32 84 * descriptors and requires that the programming of the descriptor lengths be 85 * aligned in units of 32 descriptors. 86 */ 87 #define I40E_MIN_TX_RING_SIZE 64 88 #define I40E_MAX_TX_RING_SIZE 4096 89 #define I40E_DEF_TX_RING_SIZE 1024 90 91 #define I40E_MIN_RX_RING_SIZE 64 92 #define I40E_MAX_RX_RING_SIZE 4096 93 #define I40E_DEF_RX_RING_SIZE 1024 94 95 #define I40E_DESC_ALIGN 32 96 97 /* 98 * Sizes used for asynchronous processing of the adminq. We allocate a fixed 99 * size buffer for each instance of the device during attach time, rather than 100 * allocating and freeing one during interrupt processing. 101 * 102 * We also define the descriptor size of the admin queue here. 103 */ 104 #define I40E_ADMINQ_BUFSZ 4096 105 #define I40E_MAX_ADMINQ_SIZE 1024 106 #define I40E_DEF_ADMINQ_SIZE 256 107 108 /* 109 * Note, while the min and maximum values are based upon the sizing of the ring 110 * itself, the default is taken from ixgbe without much thought. It's basically 111 * been cargo culted. See i40e_transceiver.c for a bit more information. 112 */ 113 #define I40E_MIN_RX_LIMIT_PER_INTR 16 114 #define I40E_MAX_RX_LIMIT_PER_INTR 4096 115 #define I40E_DEF_RX_LIMIT_PER_INTR 256 116 117 /* 118 * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728. 119 * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN 120 * header size (18 bytes) to get the actual maximum frame we can use. If 121 * different adapters end up with different sizes, we should make this value a 122 * bit more dynamic. 123 */ 124 #define I40E_MAX_MTU 9706 125 #define I40E_MIN_MTU ETHERMIN 126 #define I40E_DEF_MTU ETHERMTU 127 128 /* 129 * Interrupt throttling related values. Interrupt throttling values are defined 130 * in two microsecond increments. Note that a value of zero basically says do no 131 * ITR activity. A helpful way to think about these is that setting the ITR to a 132 * value will allow a certain number of interrupts per second. 133 * 134 * Our default values for RX allow 20k interrupts per second while our default 135 * values for TX allow for 5k interrupts per second. For other class interrupts, 136 * we limit ourselves to a rate of 2k/s. 137 */ 138 #define I40E_MIN_ITR 0x0000 139 #define I40E_MAX_ITR 0x0FF0 140 #define I40E_DEF_RX_ITR 0x0019 141 #define I40E_DEF_TX_ITR 0x0064 142 #define I40E_DEF_OTHER_ITR 0x00FA 143 144 /* 145 * Indexes into the three ITR registers that we have. 146 */ 147 typedef enum i40e_itr_index { 148 I40E_ITR_INDEX_RX = 0x0, 149 I40E_ITR_INDEX_TX = 0x1, 150 I40E_ITR_INDEX_OTHER = 0x2, 151 I40E_ITR_INDEX_NONE = 0x3 152 } i40e_itr_index_t; 153 154 155 /* 156 * Table 1-5 of the PRM notes that LSO supports up to 256 KB. 157 */ 158 #define I40E_LSO_MAXLEN (256 * 1024) 159 160 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */ 161 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */ 162 163 /* 164 * All the other queue types for are defined by the common code. However, this 165 * is the constant to indicate that it's terminated. 166 */ 167 #define I40E_QUEUE_TYPE_EOL 0x7FF 168 169 /* 170 * See the comments in i40e_transceiver.c as to the purpose of this value and 171 * how it's used to ensure that the IP header is eventually aligned when it's 172 * received by the OS. 173 */ 174 #define I40E_BUF_IPHDR_ALIGNMENT 2 175 176 /* 177 * The XL710 controller has a limit of eight buffers being allowed to be used 178 * for the transmission of a single frame. This is defined in 8.4.1 - Transmit 179 * Packet in System Memory. 180 */ 181 #define I40E_TX_MAX_COOKIE 8 182 183 /* 184 * Sizing to determine the amount of available descriptors at which we'll 185 * consider ourselves blocked. Also, when we have these available, we'll then 186 * consider ourselves available to transmit to MAC again. Strictly speaking, the 187 * MAX is based on the ring size. The default sizing is based on ixgbe. 188 */ 189 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE 190 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH 191 192 /* 193 * Sizing for DMA thresholds. These are used to indicate whether or not we 194 * should perform a bcopy or a DMA binding of a given message block. The range 195 * allows for setting things such that we'll always do a bcopy (a high value) or 196 * always perform a DMA binding (a low value). 197 */ 198 #define I40E_MIN_RX_DMA_THRESH 0 199 #define I40E_DEF_RX_DMA_THRESH 256 200 #define I40E_MAX_RX_DMA_THRESH INT32_MAX 201 202 #define I40E_MIN_TX_DMA_THRESH 0 203 #define I40E_DEF_TX_DMA_THRESH 256 204 #define I40E_MAX_TX_DMA_THRESH INT32_MAX 205 206 /* 207 * Resource sizing counts. There are various aspects of hardware where we may 208 * have some variable number of elements that we need to handle. Such as the 209 * hardware capabilities and switch capacities. We cannot know a priori how many 210 * elements to do, so instead we take a starting guess and then will grow it up 211 * to an upper bound on a number of elements, to limit memory consumption in 212 * case of a hardware bug. 213 */ 214 #define I40E_HW_CAP_DEFAULT 40 215 #define I40E_SWITCH_CAP_DEFAULT 25 216 217 /* 218 * Host Memory Context related constants. 219 */ 220 #define I40E_HMC_RX_CTX_UNIT 128 221 #define I40E_HMC_RX_DBUFF_MIN 1024 222 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128) 223 #define I40E_HMC_RX_DTYPE_NOSPLIT 0 224 #define I40E_HMC_RX_DSIZE_32BYTE 1 225 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1 226 #define I40E_HMC_RX_FC_DISABLE 0 227 #define I40E_HMC_RX_L2TAGORDER 1 228 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0 229 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0 230 #define I40E_HMC_RX_TPH_DISABLE 0 231 #define I40E_HMC_RX_LOWRXQ_NOINTR 0 232 #define I40E_HMC_RX_PREFENA 1 233 234 #define I40E_HMC_TX_CTX_UNIT 128 235 #define I40E_HMC_TX_NEW_CONTEXT 1 236 #define I40E_HMC_TX_FC_DISABLE 0 237 #define I40E_HMC_TX_TS_DISABLE 0 238 #define I40E_HMC_TX_FD_DISABLE 0 239 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0 240 #define I40E_HMC_TX_WB_ENABLE 1 241 #define I40E_HMC_TX_TPH_DISABLE 0 242 243 /* 244 * Whenever we establish and create a VSI, we need to assign some number of 245 * queues that it's allowed to access from the PF. Because we only have a single 246 * VSI per PF at this time, we assign it all the queues. 247 * 248 * Many of the devices support what's called Data-center Bridging. Which is a 249 * feature that we don't have much use of at this time. However, we still need 250 * to fill in this information. We follow the guidance of the note in Table 7-80 251 * which talks about bytes 62-77. It says that if we don't want to assign 252 * anything to traffic classes, we should set the field to zero. Effectively 253 * this means that everything in the system is assigned to traffic class zero. 254 */ 255 #define I40E_ASSIGN_ALL_QUEUES 0 256 #define I40E_TRAFFIC_CLASS_NO_QUEUES 0 257 258 /* 259 * This defines the error mask that we care about from rx descriptors. Currently 260 * we're only concerned with the general errors and oversize errors. 261 */ 262 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \ 263 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)) 264 265 /* 266 * Property sizing macros for firmware versions, etc. They need to be large 267 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x. 268 */ 269 #define I40E_DDI_PROP_LEN 64 270 271 /* 272 * We currently consolidate some overrides that we use in the code here. These 273 * will be gone in the fullness of time, but as we're bringing up the device, 274 * this is what we use. 275 */ 276 #define I40E_GROUP_MAX 1 277 #define I40E_TRQPAIR_MAX 1 278 279 #define I40E_GROUP_NOMSIX 1 280 #define I40E_TRQPAIR_NOMSIX 1 281 282 /* 283 * It seems reasonable to cast this to void because the only reason that we 284 * should be getting a DDI_FAILURE is due to the fact that we specify addresses 285 * out of range. Because we specify no offset or address, it shouldn't happen. 286 */ 287 #ifdef DEBUG 288 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \ 289 (handle)->dmab_dma_handle, 0, 0, \ 290 (flag))) 291 #else /* !DEBUG */ 292 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \ 293 (handle)->dmab_dma_handle, 0, 0, \ 294 (flag))) 295 #endif /* DEBUG */ 296 297 /* 298 * Constants related to ring startup and teardown. These refer to the amount of 299 * time that we're willing to wait for a ring to spin up and spin down. 300 */ 301 #define I40E_RING_WAIT_NTRIES 10 302 #define I40E_RING_WAIT_PAUSE 10 /* ms */ 303 304 /* 305 * Bit flags for attach_progress 306 */ 307 typedef enum i40e_attach_state { 308 I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */ 309 I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */ 310 I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */ 311 I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */ 312 I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */ 313 I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */ 314 I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */ 315 I40E_ATTACH_INIT = 0x0080, /* Device initialized */ 316 I40E_ATTACH_STATS = 0x0200, /* Kstats created */ 317 I40E_ATTACH_MAC = 0x0800, /* MAC registered */ 318 I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */ 319 I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */ 320 I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */ 321 } i40e_attach_state_t; 322 323 324 /* 325 * State flags that what's going on in in the device. Some of these state flags 326 * indicate some aspirational work that needs to happen in the driver. 327 * 328 * I40E_UNKNOWN: The device has yet to be started. 329 * I40E_INITIALIZED: The device has been fully attached. 330 * I40E_STARTED: The device has come out of the GLDV3 start routine. 331 * I40E_SUSPENDED: The device is suspended and I/O among other things 332 * should not occur. This happens because of an actual 333 * DDI_SUSPEND or interrupt adjustments. 334 * I40E_STALL: The tx stall detection logic has found a stall. 335 * I40E_OVERTEMP: The device has encountered a temperature alarm. 336 * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we 337 * shouldn't be manipulating their state. 338 * I40E_ERROR: We've detected an FM error and degraded the device. 339 */ 340 typedef enum i40e_state { 341 I40E_UNKNOWN = 0x00, 342 I40E_INITIALIZED = 0x01, 343 I40E_STARTED = 0x02, 344 I40E_SUSPENDED = 0x04, 345 I40E_STALL = 0x08, 346 I40E_OVERTEMP = 0x20, 347 I40E_INTR_ADJUST = 0x40, 348 I40E_ERROR = 0x80 349 } i40e_state_t; 350 351 352 /* 353 * Definitions for common Intel things that we use and some slightly more usable 354 * names. 355 */ 356 typedef struct i40e_hw i40e_hw_t; 357 typedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t; 358 359 /* 360 * Handles and addresses of DMA buffers. 361 */ 362 typedef struct i40e_dma_buffer { 363 caddr_t dmab_address; /* Virtual address */ 364 uint64_t dmab_dma_address; /* DMA (Hardware) address */ 365 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */ 366 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */ 367 size_t dmab_size; /* Buffer size */ 368 size_t dmab_len; /* Data length in the buffer */ 369 } i40e_dma_buffer_t; 370 371 /* 372 * RX Control Block 373 */ 374 typedef struct i40e_rx_control_block { 375 mblk_t *rcb_mp; 376 uint32_t rcb_ref; 377 i40e_dma_buffer_t rcb_dma; 378 frtn_t rcb_free_rtn; 379 struct i40e_rx_data *rcb_rxd; 380 } i40e_rx_control_block_t; 381 382 typedef enum { 383 I40E_TX_NONE, 384 I40E_TX_COPY, 385 I40E_TX_DMA 386 } i40e_tx_type_t; 387 388 typedef struct i40e_tx_desc i40e_tx_desc_t; 389 typedef union i40e_32byte_rx_desc i40e_rx_desc_t; 390 391 typedef struct i40e_tx_control_block { 392 struct i40e_tx_control_block *tcb_next; 393 mblk_t *tcb_mp; 394 i40e_tx_type_t tcb_type; 395 ddi_dma_handle_t tcb_dma_handle; 396 i40e_dma_buffer_t tcb_dma; 397 } i40e_tx_control_block_t; 398 399 /* 400 * Receive ring data (used below). 401 */ 402 typedef struct i40e_rx_data { 403 struct i40e *rxd_i40e; 404 405 /* 406 * RX descriptor ring definitions 407 */ 408 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */ 409 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */ 410 uint32_t rxd_desc_next; /* Index of next rx desc */ 411 412 /* 413 * RX control block list definitions 414 */ 415 kmutex_t rxd_free_lock; /* Lock to protect free data */ 416 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */ 417 i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */ 418 i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */ 419 uint32_t rxd_rcb_free; /* Number of free rcbs */ 420 421 /* 422 * RX software ring settings 423 */ 424 uint32_t rxd_ring_size; /* Rx descriptor ring size */ 425 uint32_t rxd_free_list_size; /* Rx free list size */ 426 427 /* 428 * RX outstanding data. This is used to keep track of outstanding loaned 429 * descriptors after we've shut down receiving information. Note these 430 * are protected by the i40e_t`i40e_rx_pending_lock. 431 */ 432 uint32_t rxd_rcb_pending; 433 boolean_t rxd_shutdown; 434 } i40e_rx_data_t; 435 436 /* 437 * Structures for unicast and multicast addresses. Note that we keep the VSI id 438 * around for unicast addresses, since they may belong to different VSIs. 439 * However, since all multicast addresses belong to the default VSI, we don't 440 * duplicate that information. 441 */ 442 typedef struct i40e_uaddr { 443 uint8_t iua_mac[ETHERADDRL]; 444 int iua_vsi; 445 } i40e_uaddr_t; 446 447 typedef struct i40e_maddr { 448 uint8_t ima_mac[ETHERADDRL]; 449 } i40e_maddr_t; 450 451 /* 452 * Collection of RX statistics on a given queue. 453 */ 454 typedef struct i40e_rxq_stat { 455 /* 456 * The i40e hardware does not maintain statistics on a per-ring basis, 457 * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we 458 * need to maintain our own stats for packets and bytes. 459 */ 460 kstat_named_t irxs_bytes; /* Bytes in on queue */ 461 kstat_named_t irxs_packets; /* Packets in on queue */ 462 463 /* 464 * The following set of stats cover non-checksum data path issues. 465 */ 466 kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */ 467 kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */ 468 kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */ 469 kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */ 470 kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */ 471 472 /* 473 * The following set of statistics covers rx checksum related activity. 474 * These are all primarily set in i40e_rx_hcksum. If rx checksum 475 * activity is disabled, then these should all be zero. 476 */ 477 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */ 478 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */ 479 kstat_named_t irxs_hck_unknown; /* !pinfo.known */ 480 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */ 481 kstat_named_t irxs_hck_iperr; /* IPE error bit set */ 482 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */ 483 kstat_named_t irxs_hck_l4err; /* L4E error bit set */ 484 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */ 485 kstat_named_t irxs_hck_set; /* Total times we set cksum */ 486 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */ 487 } i40e_rxq_stat_t; 488 489 /* 490 * Collection of TX Statistics on a given queue 491 */ 492 typedef struct i40e_txq_stat { 493 kstat_named_t itxs_bytes; /* Bytes out on queue */ 494 kstat_named_t itxs_packets; /* Packets out on queue */ 495 kstat_named_t itxs_descriptors; /* Descriptors issued */ 496 kstat_named_t itxs_recycled; /* Descriptors reclaimed */ 497 /* 498 * Various failure conditions. 499 */ 500 kstat_named_t itxs_hck_meoifail; /* ether offload failures */ 501 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */ 502 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */ 503 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */ 504 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */ 505 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */ 506 507 kstat_named_t itxs_err_notcb; /* No tcb's available */ 508 kstat_named_t itxs_err_nodescs; /* No tcb's available */ 509 kstat_named_t itxs_err_context; /* Total context failures */ 510 511 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */ 512 } i40e_txq_stat_t; 513 514 /* 515 * An instance of an XL710 transmit/receive queue pair. This currently 516 * represents a combination of both a transmit and receive ring, though they 517 * should really be split apart into separate logical structures. Unfortunately, 518 * during initial work we mistakenly joined them together. 519 */ 520 typedef struct i40e_trqpair { 521 struct i40e *itrq_i40e; 522 523 /* Receive-side structures. */ 524 kmutex_t itrq_rx_lock; 525 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */ 526 i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */ 527 uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */ 528 uint32_t itrq_index; /* Queue index in the PF */ 529 uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */ 530 boolean_t itrq_intr_poll; /* True when polling */ 531 532 /* Receive-side stats. */ 533 i40e_rxq_stat_t itrq_rxstat; 534 kstat_t *itrq_rxkstat; 535 536 /* Transmit-side structures. */ 537 kmutex_t itrq_tx_lock; 538 mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */ 539 uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */ 540 boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */ 541 542 /* 543 * TX data sizing 544 */ 545 uint32_t itrq_tx_ring_size; 546 uint32_t itrq_tx_free_list_size; 547 548 /* 549 * TX descriptor ring data 550 */ 551 i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */ 552 i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */ 553 volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */ 554 uint32_t itrq_desc_head; /* Last index hw freed */ 555 uint32_t itrq_desc_tail; /* Index of next free desc */ 556 uint32_t itrq_desc_free; /* Number of free descriptors */ 557 558 /* 559 * TX control block (tcb) data 560 */ 561 kmutex_t itrq_tcb_lock; 562 i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */ 563 i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */ 564 i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */ 565 uint32_t itrq_tcb_free; /* Count of free tcb */ 566 567 /* Transmit-side stats. */ 568 i40e_txq_stat_t itrq_txstat; 569 kstat_t *itrq_txkstat; 570 571 } i40e_trqpair_t; 572 573 /* 574 * VSI statistics. 575 * 576 * This mirrors the i40e_eth_stats structure but transforms it into a kstat. 577 * Note that the stock statistic structure also includes entries for tx 578 * discards. However, this is not actually implemented for the VSI (see Table 579 * 7-221), hence why we don't include the member which would always have a value 580 * of zero. This choice was made to minimize confusion to someone looking at 581 * these, as a value of zero does not necessarily equate to the fact that it's 582 * not implemented. 583 */ 584 typedef struct i40e_vsi_stats { 585 uint64_t ivs_rx_bytes; /* gorc */ 586 uint64_t ivs_rx_unicast; /* uprc */ 587 uint64_t ivs_rx_multicast; /* mprc */ 588 uint64_t ivs_rx_broadcast; /* bprc */ 589 uint64_t ivs_rx_discards; /* rdpc */ 590 uint64_t ivs_rx_unknown_protocol; /* rupp */ 591 uint64_t ivs_tx_bytes; /* gotc */ 592 uint64_t ivs_tx_unicast; /* uptc */ 593 uint64_t ivs_tx_multicast; /* mptc */ 594 uint64_t ivs_tx_broadcast; /* bptc */ 595 uint64_t ivs_tx_errors; /* tepc */ 596 } i40e_vsi_stats_t; 597 598 typedef struct i40e_vsi_kstats { 599 kstat_named_t ivk_rx_bytes; 600 kstat_named_t ivk_rx_unicast; 601 kstat_named_t ivk_rx_multicast; 602 kstat_named_t ivk_rx_broadcast; 603 kstat_named_t ivk_rx_discards; 604 kstat_named_t ivk_rx_unknown_protocol; 605 kstat_named_t ivk_tx_bytes; 606 kstat_named_t ivk_tx_unicast; 607 kstat_named_t ivk_tx_multicast; 608 kstat_named_t ivk_tx_broadcast; 609 kstat_named_t ivk_tx_errors; 610 } i40e_vsi_kstats_t; 611 612 /* 613 * For pf statistics, we opt not to use the standard statistics as defined by 614 * the Intel common code. This also currently combines statistics that are 615 * global across the entire device. 616 */ 617 typedef struct i40e_pf_stats { 618 uint64_t ips_rx_bytes; /* gorc */ 619 uint64_t ips_rx_unicast; /* uprc */ 620 uint64_t ips_rx_multicast; /* mprc */ 621 uint64_t ips_rx_broadcast; /* bprc */ 622 uint64_t ips_tx_bytes; /* gotc */ 623 uint64_t ips_tx_unicast; /* uptc */ 624 uint64_t ips_tx_multicast; /* mptc */ 625 uint64_t ips_tx_broadcast; /* bptc */ 626 627 uint64_t ips_rx_size_64; /* prc64 */ 628 uint64_t ips_rx_size_127; /* prc127 */ 629 uint64_t ips_rx_size_255; /* prc255 */ 630 uint64_t ips_rx_size_511; /* prc511 */ 631 uint64_t ips_rx_size_1023; /* prc1023 */ 632 uint64_t ips_rx_size_1522; /* prc1522 */ 633 uint64_t ips_rx_size_9522; /* prc9522 */ 634 635 uint64_t ips_tx_size_64; /* ptc64 */ 636 uint64_t ips_tx_size_127; /* ptc127 */ 637 uint64_t ips_tx_size_255; /* ptc255 */ 638 uint64_t ips_tx_size_511; /* ptc511 */ 639 uint64_t ips_tx_size_1023; /* ptc1023 */ 640 uint64_t ips_tx_size_1522; /* ptc1522 */ 641 uint64_t ips_tx_size_9522; /* ptc9522 */ 642 643 uint64_t ips_link_xon_rx; /* lxonrxc */ 644 uint64_t ips_link_xoff_rx; /* lxoffrxc */ 645 uint64_t ips_link_xon_tx; /* lxontxc */ 646 uint64_t ips_link_xoff_tx; /* lxofftxc */ 647 uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */ 648 uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */ 649 uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */ 650 uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */ 651 uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 652 653 uint64_t ips_crc_errors; /* crcerrs */ 654 uint64_t ips_illegal_bytes; /* illerrc */ 655 uint64_t ips_mac_local_faults; /* mlfc */ 656 uint64_t ips_mac_remote_faults; /* mrfc */ 657 uint64_t ips_rx_length_errors; /* rlec */ 658 uint64_t ips_rx_undersize; /* ruc */ 659 uint64_t ips_rx_fragments; /* rfc */ 660 uint64_t ips_rx_oversize; /* roc */ 661 uint64_t ips_rx_jabber; /* rjc */ 662 uint64_t ips_rx_discards; /* rdpc */ 663 uint64_t ips_rx_vm_discards; /* ldpc */ 664 uint64_t ips_rx_short_discards; /* mspdc */ 665 uint64_t ips_tx_dropped_link_down; /* tdold */ 666 uint64_t ips_rx_unknown_protocol; /* rupp */ 667 uint64_t ips_rx_err1; /* rxerr1 */ 668 uint64_t ips_rx_err2; /* rxerr2 */ 669 } i40e_pf_stats_t; 670 671 typedef struct i40e_pf_kstats { 672 kstat_named_t ipk_rx_bytes; /* gorc */ 673 kstat_named_t ipk_rx_unicast; /* uprc */ 674 kstat_named_t ipk_rx_multicast; /* mprc */ 675 kstat_named_t ipk_rx_broadcast; /* bprc */ 676 kstat_named_t ipk_tx_bytes; /* gotc */ 677 kstat_named_t ipk_tx_unicast; /* uptc */ 678 kstat_named_t ipk_tx_multicast; /* mptc */ 679 kstat_named_t ipk_tx_broadcast; /* bptc */ 680 681 kstat_named_t ipk_rx_size_64; /* prc64 */ 682 kstat_named_t ipk_rx_size_127; /* prc127 */ 683 kstat_named_t ipk_rx_size_255; /* prc255 */ 684 kstat_named_t ipk_rx_size_511; /* prc511 */ 685 kstat_named_t ipk_rx_size_1023; /* prc1023 */ 686 kstat_named_t ipk_rx_size_1522; /* prc1522 */ 687 kstat_named_t ipk_rx_size_9522; /* prc9522 */ 688 689 kstat_named_t ipk_tx_size_64; /* ptc64 */ 690 kstat_named_t ipk_tx_size_127; /* ptc127 */ 691 kstat_named_t ipk_tx_size_255; /* ptc255 */ 692 kstat_named_t ipk_tx_size_511; /* ptc511 */ 693 kstat_named_t ipk_tx_size_1023; /* ptc1023 */ 694 kstat_named_t ipk_tx_size_1522; /* ptc1522 */ 695 kstat_named_t ipk_tx_size_9522; /* ptc9522 */ 696 697 kstat_named_t ipk_link_xon_rx; /* lxonrxc */ 698 kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */ 699 kstat_named_t ipk_link_xon_tx; /* lxontxc */ 700 kstat_named_t ipk_link_xoff_tx; /* lxofftxc */ 701 kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */ 702 kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */ 703 kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */ 704 kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */ 705 kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 706 707 kstat_named_t ipk_crc_errors; /* crcerrs */ 708 kstat_named_t ipk_illegal_bytes; /* illerrc */ 709 kstat_named_t ipk_mac_local_faults; /* mlfc */ 710 kstat_named_t ipk_mac_remote_faults; /* mrfc */ 711 kstat_named_t ipk_rx_length_errors; /* rlec */ 712 kstat_named_t ipk_rx_undersize; /* ruc */ 713 kstat_named_t ipk_rx_fragments; /* rfc */ 714 kstat_named_t ipk_rx_oversize; /* roc */ 715 kstat_named_t ipk_rx_jabber; /* rjc */ 716 kstat_named_t ipk_rx_discards; /* rdpc */ 717 kstat_named_t ipk_rx_vm_discards; /* ldpc */ 718 kstat_named_t ipk_rx_short_discards; /* mspdc */ 719 kstat_named_t ipk_tx_dropped_link_down; /* tdold */ 720 kstat_named_t ipk_rx_unknown_protocol; /* rupp */ 721 kstat_named_t ipk_rx_err1; /* rxerr1 */ 722 kstat_named_t ipk_rx_err2; /* rxerr2 */ 723 } i40e_pf_kstats_t; 724 725 /* 726 * Resources that are pooled and specific to a given i40e_t. 727 */ 728 typedef struct i40e_func_rsrc { 729 uint_t ifr_nrx_queue; 730 uint_t ifr_nrx_queue_used; 731 uint_t ifr_ntx_queue; 732 uint_t ifr_trx_queue_used; 733 uint_t ifr_nvsis; 734 uint_t ifr_nvsis_used; 735 uint_t ifr_nmacfilt; 736 uint_t ifr_nmacfilt_used; 737 uint_t ifr_nmcastfilt; 738 uint_t ifr_nmcastfilt_used; 739 } i40e_func_rsrc_t; 740 741 /* 742 * Main i40e per-instance state. 743 */ 744 typedef struct i40e { 745 list_node_t i40e_glink; /* Global list link */ 746 list_node_t i40e_dlink; /* Device list link */ 747 kmutex_t i40e_general_lock; /* General device lock */ 748 749 /* 750 * General Data and management 751 */ 752 dev_info_t *i40e_dip; 753 int i40e_instance; 754 int i40e_fm_capabilities; 755 uint_t i40e_state; 756 i40e_attach_state_t i40e_attach_progress; 757 mac_handle_t i40e_mac_hdl; 758 ddi_periodic_t i40e_periodic_id; 759 760 /* 761 * Pointers to common code data structures and memory for the common 762 * code. 763 */ 764 struct i40e_hw i40e_hw_space; 765 struct i40e_osdep i40e_osdep_space; 766 struct i40e_aq_get_phy_abilities_resp i40e_phy; 767 void *i40e_aqbuf; 768 769 /* 770 * Device state, switch information, and resources. 771 */ 772 int i40e_vsi_id; 773 uint16_t i40e_vsi_num; 774 struct i40e_device *i40e_device; 775 i40e_func_rsrc_t i40e_resources; 776 uint16_t i40e_switch_rsrc_alloc; 777 uint16_t i40e_switch_rsrc_actual; 778 i40e_switch_rsrc_t *i40e_switch_rsrcs; 779 i40e_uaddr_t *i40e_uaddrs; 780 i40e_maddr_t *i40e_maddrs; 781 int i40e_mcast_promisc_count; 782 boolean_t i40e_promisc_on; 783 link_state_t i40e_link_state; 784 uint32_t i40e_link_speed; /* In Mbps */ 785 link_duplex_t i40e_link_duplex; 786 uint_t i40e_sdu; 787 uint_t i40e_frame_max; 788 789 /* 790 * Transmit and receive information, tunables, and MAC info. 791 */ 792 i40e_trqpair_t *i40e_trqpairs; 793 boolean_t i40e_mr_enable; 794 int i40e_num_trqpairs; 795 uint_t i40e_other_itr; 796 797 int i40e_num_rx_groups; 798 int i40e_num_rx_descs; 799 mac_group_handle_t i40e_rx_group_handle; 800 uint32_t i40e_rx_ring_size; 801 uint32_t i40e_rx_buf_size; 802 boolean_t i40e_rx_hcksum_enable; 803 uint32_t i40e_rx_dma_min; 804 uint32_t i40e_rx_limit_per_intr; 805 uint_t i40e_rx_itr; 806 807 int i40e_num_tx_descs; 808 uint32_t i40e_tx_ring_size; 809 uint32_t i40e_tx_buf_size; 810 uint32_t i40e_tx_block_thresh; 811 boolean_t i40e_tx_hcksum_enable; 812 uint32_t i40e_tx_dma_min; 813 uint_t i40e_tx_itr; 814 815 /* 816 * Interrupt state 817 */ 818 uint_t i40e_intr_pri; 819 uint_t i40e_intr_force; 820 uint_t i40e_intr_type; 821 int i40e_intr_cap; 822 uint32_t i40e_intr_count; 823 uint32_t i40e_intr_count_max; 824 uint32_t i40e_intr_count_min; 825 size_t i40e_intr_size; 826 ddi_intr_handle_t *i40e_intr_handles; 827 ddi_cb_handle_t i40e_callback_handle; 828 829 /* 830 * DMA attributes. See i40e_transceiver.c for why we have copies of them 831 * in the i40e_t. 832 */ 833 ddi_dma_attr_t i40e_static_dma_attr; 834 ddi_dma_attr_t i40e_txbind_dma_attr; 835 ddi_device_acc_attr_t i40e_desc_acc_attr; 836 ddi_device_acc_attr_t i40e_buf_acc_attr; 837 838 /* 839 * The following two fields are used to protect and keep track of 840 * outstanding, loaned buffers to MAC. If we have these, we can't 841 * detach as we have active DMA memory outstanding. 842 */ 843 kmutex_t i40e_rx_pending_lock; 844 kcondvar_t i40e_rx_pending_cv; 845 uint32_t i40e_rx_pending; 846 847 /* 848 * PF statistics and VSI statistics. 849 */ 850 kmutex_t i40e_stat_lock; 851 kstat_t *i40e_pf_kstat; 852 kstat_t *i40e_vsi_kstat; 853 i40e_pf_stats_t i40e_pf_stat; 854 i40e_vsi_stats_t i40e_vsi_stat; 855 uint16_t i40e_vsi_stat_id; 856 857 /* 858 * Misc. stats and counters that should maybe one day be kstats. 859 */ 860 uint64_t i40e_s_link_status_errs; 861 uint32_t i40e_s_link_status_lasterr; 862 } i40e_t; 863 864 /* 865 * The i40e_device represents a PCI device which encapsulates multiple physical 866 * functions which are represented as an i40e_t. This is used to track the use 867 * of pooled resources throughout all of the various devices. 868 */ 869 typedef struct i40e_device { 870 list_node_t id_link; 871 dev_info_t *id_parent; 872 uint_t id_pci_bus; 873 uint_t id_pci_device; 874 uint_t id_nfuncs; /* Total number of functions */ 875 uint_t id_nreg; /* Total number present */ 876 list_t id_i40e_list; /* List of i40e_t's registered */ 877 i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */ 878 uint_t id_rsrcs_alloc; /* Total allocated resources */ 879 uint_t id_rsrcs_act; /* Actual number of resources */ 880 } i40e_device_t; 881 882 /* Values for the interrupt forcing on the NIC. */ 883 #define I40E_INTR_NONE 0 884 #define I40E_INTR_MSIX 1 885 #define I40E_INTR_MSI 2 886 #define I40E_INTR_LEGACY 3 887 888 /* Hint that we don't want to do any polling... */ 889 #define I40E_POLL_NULL -1 890 891 /* 892 * Logging functions. 893 */ 894 /*PRINTFLIKE2*/ 895 extern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 896 /*PRINTFLIKE2*/ 897 extern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 898 /*PRINTFLIKE2*/ 899 extern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 900 901 /* 902 * General link handling functions. 903 */ 904 extern void i40e_link_check(i40e_t *); 905 extern void i40e_update_mtu(i40e_t *); 906 907 /* 908 * FMA functions. 909 */ 910 extern int i40e_check_acc_handle(ddi_acc_handle_t); 911 extern int i40e_check_dma_handle(ddi_dma_handle_t); 912 extern void i40e_fm_ereport(i40e_t *, char *); 913 914 /* 915 * Interrupt handlers and interrupt handler setup. 916 */ 917 extern void i40e_intr_chip_init(i40e_t *); 918 extern void i40e_intr_chip_fini(i40e_t *); 919 extern uint_t i40e_intr_msix(void *, void *); 920 extern uint_t i40e_intr_msi(void *, void *); 921 extern uint_t i40e_intr_legacy(void *, void *); 922 extern void i40e_intr_io_enable_all(i40e_t *); 923 extern void i40e_intr_io_disable_all(i40e_t *); 924 extern void i40e_intr_io_clear_cause(i40e_t *); 925 extern void i40e_intr_rx_queue_disable(i40e_t *, uint_t); 926 extern void i40e_intr_rx_queue_enable(i40e_t *, uint_t); 927 extern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t); 928 929 /* 930 * Receive-side functions 931 */ 932 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int); 933 extern mblk_t *i40e_ring_rx_poll(void *, int); 934 extern void i40e_rx_recycle(caddr_t); 935 936 /* 937 * Transmit-side functions 938 */ 939 mblk_t *i40e_ring_tx(void *, mblk_t *); 940 extern void i40e_tx_recycle_ring(i40e_trqpair_t *); 941 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *); 942 943 /* 944 * Statistics functions. 945 */ 946 extern boolean_t i40e_stats_init(i40e_t *); 947 extern void i40e_stats_fini(i40e_t *); 948 extern boolean_t i40e_stat_vsi_init(i40e_t *); 949 extern void i40e_stat_vsi_fini(i40e_t *); 950 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *); 951 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *); 952 extern int i40e_m_stat(void *, uint_t, uint64_t *); 953 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 954 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 955 956 /* 957 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code. 958 */ 959 extern boolean_t i40e_register_mac(i40e_t *); 960 extern boolean_t i40e_start(i40e_t *, boolean_t); 961 extern void i40e_stop(i40e_t *, boolean_t); 962 963 /* 964 * DMA & buffer functions and attributes 965 */ 966 extern void i40e_init_dma_attrs(i40e_t *, boolean_t); 967 extern boolean_t i40e_alloc_ring_mem(i40e_t *); 968 extern void i40e_free_ring_mem(i40e_t *, boolean_t); 969 970 #ifdef __cplusplus 971 } 972 #endif 973 974 #endif /* _I40E_SW_H */ 975