1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved. 14 * Copyright (c) 2017, Joyent, Inc. 15 * Copyright 2017 Tegile Systems, Inc. All rights reserved. 16 */ 17 18 /* 19 * Please see i40e_main.c for an introduction to the device driver, its layout, 20 * and more. 21 */ 22 23 #ifndef _I40E_SW_H 24 #define _I40E_SW_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 #include <sys/types.h> 31 #include <sys/conf.h> 32 #include <sys/debug.h> 33 #include <sys/stropts.h> 34 #include <sys/stream.h> 35 #include <sys/strsun.h> 36 #include <sys/strlog.h> 37 #include <sys/kmem.h> 38 #include <sys/stat.h> 39 #include <sys/kstat.h> 40 #include <sys/modctl.h> 41 #include <sys/errno.h> 42 #include <sys/dlpi.h> 43 #include <sys/mac_provider.h> 44 #include <sys/mac_ether.h> 45 #include <sys/vlan.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/pci.h> 49 #include <sys/pcie.h> 50 #include <sys/sdt.h> 51 #include <sys/ethernet.h> 52 #include <sys/pattr.h> 53 #include <sys/strsubr.h> 54 #include <sys/netlb.h> 55 #include <sys/random.h> 56 #include <inet/common.h> 57 #include <inet/tcp.h> 58 #include <inet/ip.h> 59 #include <inet/mi.h> 60 #include <inet/nd.h> 61 #include <netinet/udp.h> 62 #include <netinet/sctp.h> 63 #include <sys/bitmap.h> 64 #include <sys/cpuvar.h> 65 #include <sys/ddifm.h> 66 #include <sys/fm/protocol.h> 67 #include <sys/fm/util.h> 68 #include <sys/disp.h> 69 #include <sys/fm/io/ddi.h> 70 #include <sys/list.h> 71 #include <sys/debug.h> 72 #include <sys/sdt.h> 73 #include "i40e_type.h" 74 #include "i40e_osdep.h" 75 #include "i40e_prototype.h" 76 #include "i40e_xregs.h" 77 78 #define I40E_MODULE_NAME "i40e" 79 80 #define I40E_ADAPTER_REGSET 1 81 82 /* 83 * Configuration constants. Note that the hardware defines a minimum bound of 32 84 * descriptors and requires that the programming of the descriptor lengths be 85 * aligned in units of 32 descriptors. 86 */ 87 #define I40E_MIN_TX_RING_SIZE 64 88 #define I40E_MAX_TX_RING_SIZE 4096 89 #define I40E_DEF_TX_RING_SIZE 1024 90 91 #define I40E_MIN_RX_RING_SIZE 64 92 #define I40E_MAX_RX_RING_SIZE 4096 93 #define I40E_DEF_RX_RING_SIZE 1024 94 95 #define I40E_DESC_ALIGN 32 96 97 /* 98 * Sizes used for asynchronous processing of the adminq. We allocate a fixed 99 * size buffer for each instance of the device during attach time, rather than 100 * allocating and freeing one during interrupt processing. 101 * 102 * We also define the descriptor size of the admin queue here. 103 */ 104 #define I40E_ADMINQ_BUFSZ 4096 105 #define I40E_MAX_ADMINQ_SIZE 1024 106 #define I40E_DEF_ADMINQ_SIZE 256 107 108 /* 109 * Note, while the min and maximum values are based upon the sizing of the ring 110 * itself, the default is taken from ixgbe without much thought. It's basically 111 * been cargo culted. See i40e_transceiver.c for a bit more information. 112 */ 113 #define I40E_MIN_RX_LIMIT_PER_INTR 16 114 #define I40E_MAX_RX_LIMIT_PER_INTR 4096 115 #define I40E_DEF_RX_LIMIT_PER_INTR 256 116 117 /* 118 * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728. 119 * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN 120 * header size (18 bytes) to get the actual maximum frame we can use. If 121 * different adapters end up with different sizes, we should make this value a 122 * bit more dynamic. 123 */ 124 #define I40E_MAX_MTU 9706 125 #define I40E_MIN_MTU ETHERMIN 126 #define I40E_DEF_MTU ETHERMTU 127 128 /* 129 * Interrupt throttling related values. Interrupt throttling values are defined 130 * in two microsecond increments. Note that a value of zero basically says do no 131 * ITR activity. A helpful way to think about these is that setting the ITR to a 132 * value will allow a certain number of interrupts per second. 133 * 134 * Our default values for RX allow 20k interrupts per second while our default 135 * values for TX allow for 5k interrupts per second. For other class interrupts, 136 * we limit ourselves to a rate of 2k/s. 137 */ 138 #define I40E_MIN_ITR 0x0000 139 #define I40E_MAX_ITR 0x0FF0 140 #define I40E_DEF_RX_ITR 0x0019 141 #define I40E_DEF_TX_ITR 0x0064 142 #define I40E_DEF_OTHER_ITR 0x00FA 143 144 /* 145 * Indexes into the three ITR registers that we have. 146 */ 147 typedef enum i40e_itr_index { 148 I40E_ITR_INDEX_RX = 0x0, 149 I40E_ITR_INDEX_TX = 0x1, 150 I40E_ITR_INDEX_OTHER = 0x2, 151 I40E_ITR_INDEX_NONE = 0x3 152 } i40e_itr_index_t; 153 154 155 /* 156 * Table 1-5 of the PRM notes that LSO supports up to 256 KB. 157 */ 158 #define I40E_LSO_MAXLEN (256 * 1024) 159 160 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */ 161 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */ 162 163 /* 164 * All the other queue types for are defined by the common code. However, this 165 * is the constant to indicate that it's terminated. 166 */ 167 #define I40E_QUEUE_TYPE_EOL 0x7FF 168 169 /* 170 * See the comments in i40e_transceiver.c as to the purpose of this value and 171 * how it's used to ensure that the IP header is eventually aligned when it's 172 * received by the OS. 173 */ 174 #define I40E_BUF_IPHDR_ALIGNMENT 2 175 176 /* 177 * The XL710 controller has a limit of eight buffers being allowed to be used 178 * for the transmission of a single frame. This is defined in 8.4.1 - Transmit 179 * Packet in System Memory. 180 */ 181 #define I40E_TX_MAX_COOKIE 8 182 183 /* 184 * Sizing to determine the amount of available descriptors at which we'll 185 * consider ourselves blocked. Also, when we have these available, we'll then 186 * consider ourselves available to transmit to MAC again. Strictly speaking, the 187 * MAX is based on the ring size. The default sizing is based on ixgbe. 188 */ 189 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE 190 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH 191 192 /* 193 * Sizing for DMA thresholds. These are used to indicate whether or not we 194 * should perform a bcopy or a DMA binding of a given message block. The range 195 * allows for setting things such that we'll always do a bcopy (a high value) or 196 * always perform a DMA binding (a low value). 197 */ 198 #define I40E_MIN_RX_DMA_THRESH 0 199 #define I40E_DEF_RX_DMA_THRESH 256 200 #define I40E_MAX_RX_DMA_THRESH INT32_MAX 201 202 #define I40E_MIN_TX_DMA_THRESH 0 203 #define I40E_DEF_TX_DMA_THRESH 256 204 #define I40E_MAX_TX_DMA_THRESH INT32_MAX 205 206 /* 207 * Resource sizing counts. There are various aspects of hardware where we may 208 * have some variable number of elements that we need to handle. Such as the 209 * hardware capabilities and switch capacities. We cannot know a priori how many 210 * elements to do, so instead we take a starting guess and then will grow it up 211 * to an upper bound on a number of elements, to limit memory consumption in 212 * case of a hardware bug. 213 */ 214 #define I40E_HW_CAP_DEFAULT 40 215 #define I40E_SWITCH_CAP_DEFAULT 25 216 217 /* 218 * Host Memory Context related constants. 219 */ 220 #define I40E_HMC_RX_CTX_UNIT 128 221 #define I40E_HMC_RX_DBUFF_MIN 1024 222 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128) 223 #define I40E_HMC_RX_DTYPE_NOSPLIT 0 224 #define I40E_HMC_RX_DSIZE_32BYTE 1 225 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1 226 #define I40E_HMC_RX_FC_DISABLE 0 227 #define I40E_HMC_RX_L2TAGORDER 1 228 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0 229 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0 230 #define I40E_HMC_RX_TPH_DISABLE 0 231 #define I40E_HMC_RX_LOWRXQ_NOINTR 0 232 #define I40E_HMC_RX_PREFENA 1 233 234 #define I40E_HMC_TX_CTX_UNIT 128 235 #define I40E_HMC_TX_NEW_CONTEXT 1 236 #define I40E_HMC_TX_FC_DISABLE 0 237 #define I40E_HMC_TX_TS_DISABLE 0 238 #define I40E_HMC_TX_FD_DISABLE 0 239 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0 240 #define I40E_HMC_TX_WB_ENABLE 1 241 #define I40E_HMC_TX_TPH_DISABLE 0 242 243 /* 244 * Whenever we establish and create a VSI, we need to assign some number of 245 * queues that it's allowed to access from the PF. Because we only have a single 246 * VSI per PF at this time, we assign it all the queues. 247 * 248 * Many of the devices support what's called Data-center Bridging. Which is a 249 * feature that we don't have much use of at this time. However, we still need 250 * to fill in this information. We follow the guidance of the note in Table 7-80 251 * which talks about bytes 62-77. It says that if we don't want to assign 252 * anything to traffic classes, we should set the field to zero. Effectively 253 * this means that everything in the system is assigned to traffic class zero. 254 */ 255 #define I40E_ASSIGN_ALL_QUEUES 0 256 #define I40E_TRAFFIC_CLASS_NO_QUEUES 0 257 258 /* 259 * This defines the error mask that we care about from rx descriptors. Currently 260 * we're only concerned with the general errors and oversize errors. 261 */ 262 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \ 263 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)) 264 265 /* 266 * Property sizing macros for firmware versions, etc. They need to be large 267 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x. 268 */ 269 #define I40E_DDI_PROP_LEN 64 270 271 /* 272 * We currently consolidate some overrides that we use in the code here. These 273 * will be gone in the fullness of time, but as we're bringing up the device, 274 * this is what we use. 275 */ 276 #define I40E_GROUP_MAX 1 277 #define I40E_TRQPAIR_MAX 1 278 279 #define I40E_GROUP_NOMSIX 1 280 #define I40E_TRQPAIR_NOMSIX 1 281 282 /* 283 * It seems reasonable to cast this to void because the only reason that we 284 * should be getting a DDI_FAILURE is due to the fact that we specify addresses 285 * out of range. Because we specify no offset or address, it shouldn't happen. 286 */ 287 #ifdef DEBUG 288 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \ 289 (handle)->dmab_dma_handle, 0, 0, \ 290 (flag))) 291 #else /* !DEBUG */ 292 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \ 293 (handle)->dmab_dma_handle, 0, 0, \ 294 (flag))) 295 #endif /* DEBUG */ 296 297 /* 298 * Constants related to ring startup and teardown. These refer to the amount of 299 * time that we're willing to wait for a ring to spin up and spin down. 300 */ 301 #define I40E_RING_WAIT_NTRIES 10 302 #define I40E_RING_WAIT_PAUSE 10 /* ms */ 303 304 /* 305 * Printed Board Assembly (PBA) length. These are derived from Table 6-2. 306 */ 307 #define I40E_PBANUM_LENGTH 12 308 #define I40E_PBANUM_STRLEN 13 309 310 /* 311 * Define the maximum size of a number of queues for a traffic class. While this 312 * would ideally be a part of the common code parts, because it's not at this 313 * time, we define it here. 314 */ 315 #define I40E_AQ_VSI_TC_QUE_SIZE_MAX (1 << 0x6) 316 317 /* 318 * Bit flags for attach_progress 319 */ 320 typedef enum i40e_attach_state { 321 I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */ 322 I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */ 323 I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */ 324 I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */ 325 I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */ 326 I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */ 327 I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */ 328 I40E_ATTACH_INIT = 0x0080, /* Device initialized */ 329 I40E_ATTACH_STATS = 0x0200, /* Kstats created */ 330 I40E_ATTACH_MAC = 0x0800, /* MAC registered */ 331 I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */ 332 I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */ 333 I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */ 334 } i40e_attach_state_t; 335 336 337 /* 338 * State flags that what's going on in in the device. Some of these state flags 339 * indicate some aspirational work that needs to happen in the driver. 340 * 341 * I40E_UNKNOWN: The device has yet to be started. 342 * I40E_INITIALIZED: The device has been fully attached. 343 * I40E_STARTED: The device has come out of the GLDV3 start routine. 344 * I40E_SUSPENDED: The device is suspended and I/O among other things 345 * should not occur. This happens because of an actual 346 * DDI_SUSPEND or interrupt adjustments. 347 * I40E_STALL: The tx stall detection logic has found a stall. 348 * I40E_OVERTEMP: The device has encountered a temperature alarm. 349 * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we 350 * shouldn't be manipulating their state. 351 * I40E_ERROR: We've detected an FM error and degraded the device. 352 */ 353 typedef enum i40e_state { 354 I40E_UNKNOWN = 0x00, 355 I40E_INITIALIZED = 0x01, 356 I40E_STARTED = 0x02, 357 I40E_SUSPENDED = 0x04, 358 I40E_STALL = 0x08, 359 I40E_OVERTEMP = 0x20, 360 I40E_INTR_ADJUST = 0x40, 361 I40E_ERROR = 0x80 362 } i40e_state_t; 363 364 365 /* 366 * Definitions for common Intel things that we use and some slightly more usable 367 * names. 368 */ 369 typedef struct i40e_hw i40e_hw_t; 370 typedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t; 371 372 /* 373 * Handles and addresses of DMA buffers. 374 */ 375 typedef struct i40e_dma_buffer { 376 caddr_t dmab_address; /* Virtual address */ 377 uint64_t dmab_dma_address; /* DMA (Hardware) address */ 378 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */ 379 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */ 380 size_t dmab_size; /* Buffer size */ 381 size_t dmab_len; /* Data length in the buffer */ 382 } i40e_dma_buffer_t; 383 384 /* 385 * RX Control Block 386 */ 387 typedef struct i40e_rx_control_block { 388 mblk_t *rcb_mp; 389 uint32_t rcb_ref; 390 i40e_dma_buffer_t rcb_dma; 391 frtn_t rcb_free_rtn; 392 struct i40e_rx_data *rcb_rxd; 393 } i40e_rx_control_block_t; 394 395 typedef enum { 396 I40E_TX_NONE, 397 I40E_TX_COPY, 398 I40E_TX_DMA 399 } i40e_tx_type_t; 400 401 typedef struct i40e_tx_desc i40e_tx_desc_t; 402 typedef union i40e_32byte_rx_desc i40e_rx_desc_t; 403 404 typedef struct i40e_tx_control_block { 405 struct i40e_tx_control_block *tcb_next; 406 mblk_t *tcb_mp; 407 i40e_tx_type_t tcb_type; 408 ddi_dma_handle_t tcb_dma_handle; 409 i40e_dma_buffer_t tcb_dma; 410 } i40e_tx_control_block_t; 411 412 /* 413 * Receive ring data (used below). 414 */ 415 typedef struct i40e_rx_data { 416 struct i40e *rxd_i40e; 417 418 /* 419 * RX descriptor ring definitions 420 */ 421 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */ 422 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */ 423 uint32_t rxd_desc_next; /* Index of next rx desc */ 424 425 /* 426 * RX control block list definitions 427 */ 428 kmutex_t rxd_free_lock; /* Lock to protect free data */ 429 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */ 430 i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */ 431 i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */ 432 uint32_t rxd_rcb_free; /* Number of free rcbs */ 433 434 /* 435 * RX software ring settings 436 */ 437 uint32_t rxd_ring_size; /* Rx descriptor ring size */ 438 uint32_t rxd_free_list_size; /* Rx free list size */ 439 440 /* 441 * RX outstanding data. This is used to keep track of outstanding loaned 442 * descriptors after we've shut down receiving information. Note these 443 * are protected by the i40e_t`i40e_rx_pending_lock. 444 */ 445 uint32_t rxd_rcb_pending; 446 boolean_t rxd_shutdown; 447 } i40e_rx_data_t; 448 449 /* 450 * Structures for unicast and multicast addresses. Note that we keep the VSI id 451 * around for unicast addresses, since they may belong to different VSIs. 452 * However, since all multicast addresses belong to the default VSI, we don't 453 * duplicate that information. 454 */ 455 typedef struct i40e_uaddr { 456 uint8_t iua_mac[ETHERADDRL]; 457 int iua_vsi; 458 } i40e_uaddr_t; 459 460 typedef struct i40e_maddr { 461 uint8_t ima_mac[ETHERADDRL]; 462 } i40e_maddr_t; 463 464 /* 465 * Collection of RX statistics on a given queue. 466 */ 467 typedef struct i40e_rxq_stat { 468 /* 469 * The i40e hardware does not maintain statistics on a per-ring basis, 470 * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we 471 * need to maintain our own stats for packets and bytes. 472 */ 473 kstat_named_t irxs_bytes; /* Bytes in on queue */ 474 kstat_named_t irxs_packets; /* Packets in on queue */ 475 476 /* 477 * The following set of stats cover non-checksum data path issues. 478 */ 479 kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */ 480 kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */ 481 kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */ 482 kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */ 483 kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */ 484 485 /* 486 * The following set of statistics covers rx checksum related activity. 487 * These are all primarily set in i40e_rx_hcksum. If rx checksum 488 * activity is disabled, then these should all be zero. 489 */ 490 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */ 491 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */ 492 kstat_named_t irxs_hck_unknown; /* !pinfo.known */ 493 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */ 494 kstat_named_t irxs_hck_iperr; /* IPE error bit set */ 495 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */ 496 kstat_named_t irxs_hck_l4err; /* L4E error bit set */ 497 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */ 498 kstat_named_t irxs_hck_set; /* Total times we set cksum */ 499 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */ 500 } i40e_rxq_stat_t; 501 502 /* 503 * Collection of TX Statistics on a given queue 504 */ 505 typedef struct i40e_txq_stat { 506 kstat_named_t itxs_bytes; /* Bytes out on queue */ 507 kstat_named_t itxs_packets; /* Packets out on queue */ 508 kstat_named_t itxs_descriptors; /* Descriptors issued */ 509 kstat_named_t itxs_recycled; /* Descriptors reclaimed */ 510 /* 511 * Various failure conditions. 512 */ 513 kstat_named_t itxs_hck_meoifail; /* ether offload failures */ 514 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */ 515 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */ 516 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */ 517 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */ 518 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */ 519 520 kstat_named_t itxs_err_notcb; /* No tcb's available */ 521 kstat_named_t itxs_err_nodescs; /* No tcb's available */ 522 kstat_named_t itxs_err_context; /* Total context failures */ 523 524 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */ 525 } i40e_txq_stat_t; 526 527 /* 528 * An instance of an XL710 transmit/receive queue pair. This currently 529 * represents a combination of both a transmit and receive ring, though they 530 * should really be split apart into separate logical structures. Unfortunately, 531 * during initial work we mistakenly joined them together. 532 */ 533 typedef struct i40e_trqpair { 534 struct i40e *itrq_i40e; 535 536 /* Receive-side structures. */ 537 kmutex_t itrq_rx_lock; 538 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */ 539 i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */ 540 uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */ 541 uint32_t itrq_index; /* Queue index in the PF */ 542 uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */ 543 boolean_t itrq_intr_poll; /* True when polling */ 544 545 /* Receive-side stats. */ 546 i40e_rxq_stat_t itrq_rxstat; 547 kstat_t *itrq_rxkstat; 548 549 /* Transmit-side structures. */ 550 kmutex_t itrq_tx_lock; 551 mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */ 552 uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */ 553 boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */ 554 555 /* 556 * TX data sizing 557 */ 558 uint32_t itrq_tx_ring_size; 559 uint32_t itrq_tx_free_list_size; 560 561 /* 562 * TX descriptor ring data 563 */ 564 i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */ 565 i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */ 566 volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */ 567 uint32_t itrq_desc_head; /* Last index hw freed */ 568 uint32_t itrq_desc_tail; /* Index of next free desc */ 569 uint32_t itrq_desc_free; /* Number of free descriptors */ 570 571 /* 572 * TX control block (tcb) data 573 */ 574 kmutex_t itrq_tcb_lock; 575 i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */ 576 i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */ 577 i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */ 578 uint32_t itrq_tcb_free; /* Count of free tcb */ 579 580 /* Transmit-side stats. */ 581 i40e_txq_stat_t itrq_txstat; 582 kstat_t *itrq_txkstat; 583 584 } i40e_trqpair_t; 585 586 /* 587 * VSI statistics. 588 * 589 * This mirrors the i40e_eth_stats structure but transforms it into a kstat. 590 * Note that the stock statistic structure also includes entries for tx 591 * discards. However, this is not actually implemented for the VSI (see Table 592 * 7-221), hence why we don't include the member which would always have a value 593 * of zero. This choice was made to minimize confusion to someone looking at 594 * these, as a value of zero does not necessarily equate to the fact that it's 595 * not implemented. 596 */ 597 typedef struct i40e_vsi_stats { 598 uint64_t ivs_rx_bytes; /* gorc */ 599 uint64_t ivs_rx_unicast; /* uprc */ 600 uint64_t ivs_rx_multicast; /* mprc */ 601 uint64_t ivs_rx_broadcast; /* bprc */ 602 uint64_t ivs_rx_discards; /* rdpc */ 603 uint64_t ivs_rx_unknown_protocol; /* rupp */ 604 uint64_t ivs_tx_bytes; /* gotc */ 605 uint64_t ivs_tx_unicast; /* uptc */ 606 uint64_t ivs_tx_multicast; /* mptc */ 607 uint64_t ivs_tx_broadcast; /* bptc */ 608 uint64_t ivs_tx_errors; /* tepc */ 609 } i40e_vsi_stats_t; 610 611 typedef struct i40e_vsi_kstats { 612 kstat_named_t ivk_rx_bytes; 613 kstat_named_t ivk_rx_unicast; 614 kstat_named_t ivk_rx_multicast; 615 kstat_named_t ivk_rx_broadcast; 616 kstat_named_t ivk_rx_discards; 617 kstat_named_t ivk_rx_unknown_protocol; 618 kstat_named_t ivk_tx_bytes; 619 kstat_named_t ivk_tx_unicast; 620 kstat_named_t ivk_tx_multicast; 621 kstat_named_t ivk_tx_broadcast; 622 kstat_named_t ivk_tx_errors; 623 } i40e_vsi_kstats_t; 624 625 /* 626 * For pf statistics, we opt not to use the standard statistics as defined by 627 * the Intel common code. This also currently combines statistics that are 628 * global across the entire device. 629 */ 630 typedef struct i40e_pf_stats { 631 uint64_t ips_rx_bytes; /* gorc */ 632 uint64_t ips_rx_unicast; /* uprc */ 633 uint64_t ips_rx_multicast; /* mprc */ 634 uint64_t ips_rx_broadcast; /* bprc */ 635 uint64_t ips_tx_bytes; /* gotc */ 636 uint64_t ips_tx_unicast; /* uptc */ 637 uint64_t ips_tx_multicast; /* mptc */ 638 uint64_t ips_tx_broadcast; /* bptc */ 639 640 uint64_t ips_rx_size_64; /* prc64 */ 641 uint64_t ips_rx_size_127; /* prc127 */ 642 uint64_t ips_rx_size_255; /* prc255 */ 643 uint64_t ips_rx_size_511; /* prc511 */ 644 uint64_t ips_rx_size_1023; /* prc1023 */ 645 uint64_t ips_rx_size_1522; /* prc1522 */ 646 uint64_t ips_rx_size_9522; /* prc9522 */ 647 648 uint64_t ips_tx_size_64; /* ptc64 */ 649 uint64_t ips_tx_size_127; /* ptc127 */ 650 uint64_t ips_tx_size_255; /* ptc255 */ 651 uint64_t ips_tx_size_511; /* ptc511 */ 652 uint64_t ips_tx_size_1023; /* ptc1023 */ 653 uint64_t ips_tx_size_1522; /* ptc1522 */ 654 uint64_t ips_tx_size_9522; /* ptc9522 */ 655 656 uint64_t ips_link_xon_rx; /* lxonrxc */ 657 uint64_t ips_link_xoff_rx; /* lxoffrxc */ 658 uint64_t ips_link_xon_tx; /* lxontxc */ 659 uint64_t ips_link_xoff_tx; /* lxofftxc */ 660 uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */ 661 uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */ 662 uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */ 663 uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */ 664 uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 665 666 uint64_t ips_crc_errors; /* crcerrs */ 667 uint64_t ips_illegal_bytes; /* illerrc */ 668 uint64_t ips_mac_local_faults; /* mlfc */ 669 uint64_t ips_mac_remote_faults; /* mrfc */ 670 uint64_t ips_rx_length_errors; /* rlec */ 671 uint64_t ips_rx_undersize; /* ruc */ 672 uint64_t ips_rx_fragments; /* rfc */ 673 uint64_t ips_rx_oversize; /* roc */ 674 uint64_t ips_rx_jabber; /* rjc */ 675 uint64_t ips_rx_discards; /* rdpc */ 676 uint64_t ips_rx_vm_discards; /* ldpc */ 677 uint64_t ips_rx_short_discards; /* mspdc */ 678 uint64_t ips_tx_dropped_link_down; /* tdold */ 679 uint64_t ips_rx_unknown_protocol; /* rupp */ 680 uint64_t ips_rx_err1; /* rxerr1 */ 681 uint64_t ips_rx_err2; /* rxerr2 */ 682 } i40e_pf_stats_t; 683 684 typedef struct i40e_pf_kstats { 685 kstat_named_t ipk_rx_bytes; /* gorc */ 686 kstat_named_t ipk_rx_unicast; /* uprc */ 687 kstat_named_t ipk_rx_multicast; /* mprc */ 688 kstat_named_t ipk_rx_broadcast; /* bprc */ 689 kstat_named_t ipk_tx_bytes; /* gotc */ 690 kstat_named_t ipk_tx_unicast; /* uptc */ 691 kstat_named_t ipk_tx_multicast; /* mptc */ 692 kstat_named_t ipk_tx_broadcast; /* bptc */ 693 694 kstat_named_t ipk_rx_size_64; /* prc64 */ 695 kstat_named_t ipk_rx_size_127; /* prc127 */ 696 kstat_named_t ipk_rx_size_255; /* prc255 */ 697 kstat_named_t ipk_rx_size_511; /* prc511 */ 698 kstat_named_t ipk_rx_size_1023; /* prc1023 */ 699 kstat_named_t ipk_rx_size_1522; /* prc1522 */ 700 kstat_named_t ipk_rx_size_9522; /* prc9522 */ 701 702 kstat_named_t ipk_tx_size_64; /* ptc64 */ 703 kstat_named_t ipk_tx_size_127; /* ptc127 */ 704 kstat_named_t ipk_tx_size_255; /* ptc255 */ 705 kstat_named_t ipk_tx_size_511; /* ptc511 */ 706 kstat_named_t ipk_tx_size_1023; /* ptc1023 */ 707 kstat_named_t ipk_tx_size_1522; /* ptc1522 */ 708 kstat_named_t ipk_tx_size_9522; /* ptc9522 */ 709 710 kstat_named_t ipk_link_xon_rx; /* lxonrxc */ 711 kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */ 712 kstat_named_t ipk_link_xon_tx; /* lxontxc */ 713 kstat_named_t ipk_link_xoff_tx; /* lxofftxc */ 714 kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */ 715 kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */ 716 kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */ 717 kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */ 718 kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 719 720 kstat_named_t ipk_crc_errors; /* crcerrs */ 721 kstat_named_t ipk_illegal_bytes; /* illerrc */ 722 kstat_named_t ipk_mac_local_faults; /* mlfc */ 723 kstat_named_t ipk_mac_remote_faults; /* mrfc */ 724 kstat_named_t ipk_rx_length_errors; /* rlec */ 725 kstat_named_t ipk_rx_undersize; /* ruc */ 726 kstat_named_t ipk_rx_fragments; /* rfc */ 727 kstat_named_t ipk_rx_oversize; /* roc */ 728 kstat_named_t ipk_rx_jabber; /* rjc */ 729 kstat_named_t ipk_rx_discards; /* rdpc */ 730 kstat_named_t ipk_rx_vm_discards; /* ldpc */ 731 kstat_named_t ipk_rx_short_discards; /* mspdc */ 732 kstat_named_t ipk_tx_dropped_link_down; /* tdold */ 733 kstat_named_t ipk_rx_unknown_protocol; /* rupp */ 734 kstat_named_t ipk_rx_err1; /* rxerr1 */ 735 kstat_named_t ipk_rx_err2; /* rxerr2 */ 736 } i40e_pf_kstats_t; 737 738 /* 739 * Resources that are pooled and specific to a given i40e_t. 740 */ 741 typedef struct i40e_func_rsrc { 742 uint_t ifr_nrx_queue; 743 uint_t ifr_nrx_queue_used; 744 uint_t ifr_ntx_queue; 745 uint_t ifr_trx_queue_used; 746 uint_t ifr_nvsis; 747 uint_t ifr_nvsis_used; 748 uint_t ifr_nmacfilt; 749 uint_t ifr_nmacfilt_used; 750 uint_t ifr_nmcastfilt; 751 uint_t ifr_nmcastfilt_used; 752 } i40e_func_rsrc_t; 753 754 /* 755 * Main i40e per-instance state. 756 */ 757 typedef struct i40e { 758 list_node_t i40e_glink; /* Global list link */ 759 list_node_t i40e_dlink; /* Device list link */ 760 kmutex_t i40e_general_lock; /* General device lock */ 761 762 /* 763 * General Data and management 764 */ 765 dev_info_t *i40e_dip; 766 int i40e_instance; 767 int i40e_fm_capabilities; 768 uint_t i40e_state; 769 i40e_attach_state_t i40e_attach_progress; 770 mac_handle_t i40e_mac_hdl; 771 ddi_periodic_t i40e_periodic_id; 772 773 /* 774 * Pointers to common code data structures and memory for the common 775 * code. 776 */ 777 struct i40e_hw i40e_hw_space; 778 struct i40e_osdep i40e_osdep_space; 779 struct i40e_aq_get_phy_abilities_resp i40e_phy; 780 void *i40e_aqbuf; 781 782 /* 783 * Device state, switch information, and resources. 784 */ 785 int i40e_vsi_id; 786 uint16_t i40e_vsi_num; 787 struct i40e_device *i40e_device; 788 i40e_func_rsrc_t i40e_resources; 789 uint16_t i40e_switch_rsrc_alloc; 790 uint16_t i40e_switch_rsrc_actual; 791 i40e_switch_rsrc_t *i40e_switch_rsrcs; 792 i40e_uaddr_t *i40e_uaddrs; 793 i40e_maddr_t *i40e_maddrs; 794 int i40e_mcast_promisc_count; 795 boolean_t i40e_promisc_on; 796 link_state_t i40e_link_state; 797 uint32_t i40e_link_speed; /* In Mbps */ 798 link_duplex_t i40e_link_duplex; 799 uint_t i40e_sdu; 800 uint_t i40e_frame_max; 801 802 /* 803 * Transmit and receive information, tunables, and MAC info. 804 */ 805 i40e_trqpair_t *i40e_trqpairs; 806 boolean_t i40e_mr_enable; 807 int i40e_num_trqpairs; 808 uint_t i40e_other_itr; 809 810 int i40e_num_rx_groups; 811 int i40e_num_rx_descs; 812 mac_group_handle_t i40e_rx_group_handle; 813 uint32_t i40e_rx_ring_size; 814 uint32_t i40e_rx_buf_size; 815 boolean_t i40e_rx_hcksum_enable; 816 uint32_t i40e_rx_dma_min; 817 uint32_t i40e_rx_limit_per_intr; 818 uint_t i40e_rx_itr; 819 820 int i40e_num_tx_descs; 821 uint32_t i40e_tx_ring_size; 822 uint32_t i40e_tx_buf_size; 823 uint32_t i40e_tx_block_thresh; 824 boolean_t i40e_tx_hcksum_enable; 825 uint32_t i40e_tx_dma_min; 826 uint_t i40e_tx_itr; 827 828 /* 829 * Interrupt state 830 */ 831 uint_t i40e_intr_pri; 832 uint_t i40e_intr_force; 833 uint_t i40e_intr_type; 834 int i40e_intr_cap; 835 uint32_t i40e_intr_count; 836 uint32_t i40e_intr_count_max; 837 uint32_t i40e_intr_count_min; 838 size_t i40e_intr_size; 839 ddi_intr_handle_t *i40e_intr_handles; 840 ddi_cb_handle_t i40e_callback_handle; 841 842 /* 843 * DMA attributes. See i40e_transceiver.c for why we have copies of them 844 * in the i40e_t. 845 */ 846 ddi_dma_attr_t i40e_static_dma_attr; 847 ddi_dma_attr_t i40e_txbind_dma_attr; 848 ddi_device_acc_attr_t i40e_desc_acc_attr; 849 ddi_device_acc_attr_t i40e_buf_acc_attr; 850 851 /* 852 * The following two fields are used to protect and keep track of 853 * outstanding, loaned buffers to MAC. If we have these, we can't 854 * detach as we have active DMA memory outstanding. 855 */ 856 kmutex_t i40e_rx_pending_lock; 857 kcondvar_t i40e_rx_pending_cv; 858 uint32_t i40e_rx_pending; 859 860 /* 861 * PF statistics and VSI statistics. 862 */ 863 kmutex_t i40e_stat_lock; 864 kstat_t *i40e_pf_kstat; 865 kstat_t *i40e_vsi_kstat; 866 i40e_pf_stats_t i40e_pf_stat; 867 i40e_vsi_stats_t i40e_vsi_stat; 868 uint16_t i40e_vsi_stat_id; 869 870 /* 871 * Misc. stats and counters that should maybe one day be kstats. 872 */ 873 uint64_t i40e_s_link_status_errs; 874 uint32_t i40e_s_link_status_lasterr; 875 } i40e_t; 876 877 /* 878 * The i40e_device represents a PCI device which encapsulates multiple physical 879 * functions which are represented as an i40e_t. This is used to track the use 880 * of pooled resources throughout all of the various devices. 881 */ 882 typedef struct i40e_device { 883 list_node_t id_link; 884 dev_info_t *id_parent; 885 uint_t id_pci_bus; 886 uint_t id_pci_device; 887 uint_t id_nfuncs; /* Total number of functions */ 888 uint_t id_nreg; /* Total number present */ 889 list_t id_i40e_list; /* List of i40e_t's registered */ 890 i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */ 891 uint_t id_rsrcs_alloc; /* Total allocated resources */ 892 uint_t id_rsrcs_act; /* Actual number of resources */ 893 } i40e_device_t; 894 895 /* Values for the interrupt forcing on the NIC. */ 896 #define I40E_INTR_NONE 0 897 #define I40E_INTR_MSIX 1 898 #define I40E_INTR_MSI 2 899 #define I40E_INTR_LEGACY 3 900 901 /* Hint that we don't want to do any polling... */ 902 #define I40E_POLL_NULL -1 903 904 /* 905 * Logging functions. 906 */ 907 /*PRINTFLIKE2*/ 908 extern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 909 /*PRINTFLIKE2*/ 910 extern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 911 /*PRINTFLIKE2*/ 912 extern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 913 914 /* 915 * General link handling functions. 916 */ 917 extern void i40e_link_check(i40e_t *); 918 extern void i40e_update_mtu(i40e_t *); 919 920 /* 921 * FMA functions. 922 */ 923 extern int i40e_check_acc_handle(ddi_acc_handle_t); 924 extern int i40e_check_dma_handle(ddi_dma_handle_t); 925 extern void i40e_fm_ereport(i40e_t *, char *); 926 927 /* 928 * Interrupt handlers and interrupt handler setup. 929 */ 930 extern void i40e_intr_chip_init(i40e_t *); 931 extern void i40e_intr_chip_fini(i40e_t *); 932 extern uint_t i40e_intr_msix(void *, void *); 933 extern uint_t i40e_intr_msi(void *, void *); 934 extern uint_t i40e_intr_legacy(void *, void *); 935 extern void i40e_intr_io_enable_all(i40e_t *); 936 extern void i40e_intr_io_disable_all(i40e_t *); 937 extern void i40e_intr_io_clear_cause(i40e_t *); 938 extern void i40e_intr_rx_queue_disable(i40e_trqpair_t *); 939 extern void i40e_intr_rx_queue_enable(i40e_trqpair_t *); 940 extern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t); 941 942 /* 943 * Receive-side functions 944 */ 945 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int); 946 extern mblk_t *i40e_ring_rx_poll(void *, int); 947 extern void i40e_rx_recycle(caddr_t); 948 949 /* 950 * Transmit-side functions 951 */ 952 mblk_t *i40e_ring_tx(void *, mblk_t *); 953 extern void i40e_tx_recycle_ring(i40e_trqpair_t *); 954 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *); 955 956 /* 957 * Statistics functions. 958 */ 959 extern boolean_t i40e_stats_init(i40e_t *); 960 extern void i40e_stats_fini(i40e_t *); 961 extern boolean_t i40e_stat_vsi_init(i40e_t *); 962 extern void i40e_stat_vsi_fini(i40e_t *); 963 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *); 964 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *); 965 extern int i40e_m_stat(void *, uint_t, uint64_t *); 966 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 967 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 968 969 /* 970 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code. 971 */ 972 extern boolean_t i40e_register_mac(i40e_t *); 973 extern boolean_t i40e_start(i40e_t *, boolean_t); 974 extern void i40e_stop(i40e_t *, boolean_t); 975 976 /* 977 * DMA & buffer functions and attributes 978 */ 979 extern void i40e_init_dma_attrs(i40e_t *, boolean_t); 980 extern boolean_t i40e_alloc_ring_mem(i40e_t *); 981 extern void i40e_free_ring_mem(i40e_t *, boolean_t); 982 983 #ifdef __cplusplus 984 } 985 #endif 986 987 #endif /* _I40E_SW_H */ 988