1 /****************************************************************************** 2 3 Copyright (c) 2013-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "virtchnl.h" 39 40 41 /** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48 static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 { 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 case I40E_DEV_ID_10G_BASE_T4: 65 case I40E_DEV_ID_20G_KR2: 66 case I40E_DEV_ID_20G_KR2_A: 67 case I40E_DEV_ID_25G_B: 68 case I40E_DEV_ID_25G_SFP28: 69 hw->mac.type = I40E_MAC_XL710; 70 break; 71 case I40E_DEV_ID_KX_X722: 72 case I40E_DEV_ID_QSFP_X722: 73 case I40E_DEV_ID_SFP_X722: 74 case I40E_DEV_ID_1G_BASE_T_X722: 75 case I40E_DEV_ID_10G_BASE_T_X722: 76 case I40E_DEV_ID_SFP_I_X722: 77 hw->mac.type = I40E_MAC_X722; 78 break; 79 default: 80 hw->mac.type = I40E_MAC_GENERIC; 81 break; 82 } 83 } else { 84 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 85 } 86 87 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 88 hw->mac.type, status); 89 return status; 90 } 91 92 /** 93 * i40e_aq_str - convert AQ err code to a string 94 * @hw: pointer to the HW structure 95 * @aq_err: the AQ error code to convert 96 **/ 97 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 98 { 99 switch (aq_err) { 100 case I40E_AQ_RC_OK: 101 return "OK"; 102 case I40E_AQ_RC_EPERM: 103 return "I40E_AQ_RC_EPERM"; 104 case I40E_AQ_RC_ENOENT: 105 return "I40E_AQ_RC_ENOENT"; 106 case I40E_AQ_RC_ESRCH: 107 return "I40E_AQ_RC_ESRCH"; 108 case I40E_AQ_RC_EINTR: 109 return "I40E_AQ_RC_EINTR"; 110 case I40E_AQ_RC_EIO: 111 return "I40E_AQ_RC_EIO"; 112 case I40E_AQ_RC_ENXIO: 113 return "I40E_AQ_RC_ENXIO"; 114 case I40E_AQ_RC_E2BIG: 115 return "I40E_AQ_RC_E2BIG"; 116 case I40E_AQ_RC_EAGAIN: 117 return "I40E_AQ_RC_EAGAIN"; 118 case I40E_AQ_RC_ENOMEM: 119 return "I40E_AQ_RC_ENOMEM"; 120 case I40E_AQ_RC_EACCES: 121 return "I40E_AQ_RC_EACCES"; 122 case I40E_AQ_RC_EFAULT: 123 return "I40E_AQ_RC_EFAULT"; 124 case I40E_AQ_RC_EBUSY: 125 return "I40E_AQ_RC_EBUSY"; 126 case I40E_AQ_RC_EEXIST: 127 return "I40E_AQ_RC_EEXIST"; 128 case I40E_AQ_RC_EINVAL: 129 return "I40E_AQ_RC_EINVAL"; 130 case I40E_AQ_RC_ENOTTY: 131 return "I40E_AQ_RC_ENOTTY"; 132 case I40E_AQ_RC_ENOSPC: 133 return "I40E_AQ_RC_ENOSPC"; 134 case I40E_AQ_RC_ENOSYS: 135 return "I40E_AQ_RC_ENOSYS"; 136 case I40E_AQ_RC_ERANGE: 137 return "I40E_AQ_RC_ERANGE"; 138 case I40E_AQ_RC_EFLUSHED: 139 return "I40E_AQ_RC_EFLUSHED"; 140 case I40E_AQ_RC_BAD_ADDR: 141 return "I40E_AQ_RC_BAD_ADDR"; 142 case I40E_AQ_RC_EMODE: 143 return "I40E_AQ_RC_EMODE"; 144 case I40E_AQ_RC_EFBIG: 145 return "I40E_AQ_RC_EFBIG"; 146 } 147 148 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 149 return hw->err_str; 150 } 151 152 /** 153 * i40e_stat_str - convert status err code to a string 154 * @hw: pointer to the HW structure 155 * @stat_err: the status error code to convert 156 **/ 157 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 158 { 159 switch (stat_err) { 160 case I40E_SUCCESS: 161 return "OK"; 162 case I40E_ERR_NVM: 163 return "I40E_ERR_NVM"; 164 case I40E_ERR_NVM_CHECKSUM: 165 return "I40E_ERR_NVM_CHECKSUM"; 166 case I40E_ERR_PHY: 167 return "I40E_ERR_PHY"; 168 case I40E_ERR_CONFIG: 169 return "I40E_ERR_CONFIG"; 170 case I40E_ERR_PARAM: 171 return "I40E_ERR_PARAM"; 172 case I40E_ERR_MAC_TYPE: 173 return "I40E_ERR_MAC_TYPE"; 174 case I40E_ERR_UNKNOWN_PHY: 175 return "I40E_ERR_UNKNOWN_PHY"; 176 case I40E_ERR_LINK_SETUP: 177 return "I40E_ERR_LINK_SETUP"; 178 case I40E_ERR_ADAPTER_STOPPED: 179 return "I40E_ERR_ADAPTER_STOPPED"; 180 case I40E_ERR_INVALID_MAC_ADDR: 181 return "I40E_ERR_INVALID_MAC_ADDR"; 182 case I40E_ERR_DEVICE_NOT_SUPPORTED: 183 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 184 case I40E_ERR_MASTER_REQUESTS_PENDING: 185 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 186 case I40E_ERR_INVALID_LINK_SETTINGS: 187 return "I40E_ERR_INVALID_LINK_SETTINGS"; 188 case I40E_ERR_AUTONEG_NOT_COMPLETE: 189 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 190 case I40E_ERR_RESET_FAILED: 191 return "I40E_ERR_RESET_FAILED"; 192 case I40E_ERR_SWFW_SYNC: 193 return "I40E_ERR_SWFW_SYNC"; 194 case I40E_ERR_NO_AVAILABLE_VSI: 195 return "I40E_ERR_NO_AVAILABLE_VSI"; 196 case I40E_ERR_NO_MEMORY: 197 return "I40E_ERR_NO_MEMORY"; 198 case I40E_ERR_BAD_PTR: 199 return "I40E_ERR_BAD_PTR"; 200 case I40E_ERR_RING_FULL: 201 return "I40E_ERR_RING_FULL"; 202 case I40E_ERR_INVALID_PD_ID: 203 return "I40E_ERR_INVALID_PD_ID"; 204 case I40E_ERR_INVALID_QP_ID: 205 return "I40E_ERR_INVALID_QP_ID"; 206 case I40E_ERR_INVALID_CQ_ID: 207 return "I40E_ERR_INVALID_CQ_ID"; 208 case I40E_ERR_INVALID_CEQ_ID: 209 return "I40E_ERR_INVALID_CEQ_ID"; 210 case I40E_ERR_INVALID_AEQ_ID: 211 return "I40E_ERR_INVALID_AEQ_ID"; 212 case I40E_ERR_INVALID_SIZE: 213 return "I40E_ERR_INVALID_SIZE"; 214 case I40E_ERR_INVALID_ARP_INDEX: 215 return "I40E_ERR_INVALID_ARP_INDEX"; 216 case I40E_ERR_INVALID_FPM_FUNC_ID: 217 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 218 case I40E_ERR_QP_INVALID_MSG_SIZE: 219 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 220 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 221 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 222 case I40E_ERR_INVALID_FRAG_COUNT: 223 return "I40E_ERR_INVALID_FRAG_COUNT"; 224 case I40E_ERR_QUEUE_EMPTY: 225 return "I40E_ERR_QUEUE_EMPTY"; 226 case I40E_ERR_INVALID_ALIGNMENT: 227 return "I40E_ERR_INVALID_ALIGNMENT"; 228 case I40E_ERR_FLUSHED_QUEUE: 229 return "I40E_ERR_FLUSHED_QUEUE"; 230 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 231 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 232 case I40E_ERR_INVALID_IMM_DATA_SIZE: 233 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 234 case I40E_ERR_TIMEOUT: 235 return "I40E_ERR_TIMEOUT"; 236 case I40E_ERR_OPCODE_MISMATCH: 237 return "I40E_ERR_OPCODE_MISMATCH"; 238 case I40E_ERR_CQP_COMPL_ERROR: 239 return "I40E_ERR_CQP_COMPL_ERROR"; 240 case I40E_ERR_INVALID_VF_ID: 241 return "I40E_ERR_INVALID_VF_ID"; 242 case I40E_ERR_INVALID_HMCFN_ID: 243 return "I40E_ERR_INVALID_HMCFN_ID"; 244 case I40E_ERR_BACKING_PAGE_ERROR: 245 return "I40E_ERR_BACKING_PAGE_ERROR"; 246 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 247 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 248 case I40E_ERR_INVALID_PBLE_INDEX: 249 return "I40E_ERR_INVALID_PBLE_INDEX"; 250 case I40E_ERR_INVALID_SD_INDEX: 251 return "I40E_ERR_INVALID_SD_INDEX"; 252 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 253 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 254 case I40E_ERR_INVALID_SD_TYPE: 255 return "I40E_ERR_INVALID_SD_TYPE"; 256 case I40E_ERR_MEMCPY_FAILED: 257 return "I40E_ERR_MEMCPY_FAILED"; 258 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 259 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 260 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 261 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 262 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 263 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 264 case I40E_ERR_SRQ_ENABLED: 265 return "I40E_ERR_SRQ_ENABLED"; 266 case I40E_ERR_ADMIN_QUEUE_ERROR: 267 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 268 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 269 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 270 case I40E_ERR_BUF_TOO_SHORT: 271 return "I40E_ERR_BUF_TOO_SHORT"; 272 case I40E_ERR_ADMIN_QUEUE_FULL: 273 return "I40E_ERR_ADMIN_QUEUE_FULL"; 274 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 275 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 276 case I40E_ERR_BAD_IWARP_CQE: 277 return "I40E_ERR_BAD_IWARP_CQE"; 278 case I40E_ERR_NVM_BLANK_MODE: 279 return "I40E_ERR_NVM_BLANK_MODE"; 280 case I40E_ERR_NOT_IMPLEMENTED: 281 return "I40E_ERR_NOT_IMPLEMENTED"; 282 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 283 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 284 case I40E_ERR_DIAG_TEST_FAILED: 285 return "I40E_ERR_DIAG_TEST_FAILED"; 286 case I40E_ERR_NOT_READY: 287 return "I40E_ERR_NOT_READY"; 288 case I40E_NOT_SUPPORTED: 289 return "I40E_NOT_SUPPORTED"; 290 case I40E_ERR_FIRMWARE_API_VERSION: 291 return "I40E_ERR_FIRMWARE_API_VERSION"; 292 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 293 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 294 } 295 296 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 297 return hw->err_str; 298 } 299 300 /** 301 * i40e_debug_aq 302 * @hw: debug mask related to admin queue 303 * @mask: debug mask 304 * @desc: pointer to admin queue descriptor 305 * @buffer: pointer to command buffer 306 * @buf_len: max length of buffer 307 * 308 * Dumps debug log about adminq command with descriptor contents. 309 **/ 310 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 311 void *buffer, u16 buf_len) 312 { 313 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 314 u8 *buf = (u8 *)buffer; 315 u16 len; 316 u16 i = 0; 317 318 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 319 return; 320 321 len = LE16_TO_CPU(aq_desc->datalen); 322 323 i40e_debug(hw, mask, 324 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 325 LE16_TO_CPU(aq_desc->opcode), 326 LE16_TO_CPU(aq_desc->flags), 327 LE16_TO_CPU(aq_desc->datalen), 328 LE16_TO_CPU(aq_desc->retval)); 329 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 330 LE32_TO_CPU(aq_desc->cookie_high), 331 LE32_TO_CPU(aq_desc->cookie_low)); 332 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 333 LE32_TO_CPU(aq_desc->params.internal.param0), 334 LE32_TO_CPU(aq_desc->params.internal.param1)); 335 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 336 LE32_TO_CPU(aq_desc->params.external.addr_high), 337 LE32_TO_CPU(aq_desc->params.external.addr_low)); 338 339 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 340 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 341 if (buf_len < len) 342 len = buf_len; 343 /* write the full 16-byte chunks */ 344 for (i = 0; i < (len - 16); i += 16) 345 i40e_debug(hw, mask, 346 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 347 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 348 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 349 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 350 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 351 /* the most we could have left is 16 bytes, pad with zeros */ 352 if (i < len) { 353 char d_buf[16]; 354 int j, i_sav; 355 356 i_sav = i; 357 memset(d_buf, 0, sizeof(d_buf)); 358 for (j = 0; i < len; j++, i++) 359 d_buf[j] = buf[i]; 360 i40e_debug(hw, mask, 361 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 362 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 363 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 364 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 365 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 366 } 367 } 368 } 369 370 /** 371 * i40e_check_asq_alive 372 * @hw: pointer to the hw struct 373 * 374 * Returns TRUE if Queue is enabled else FALSE. 375 **/ 376 bool i40e_check_asq_alive(struct i40e_hw *hw) 377 { 378 if (hw->aq.asq.len) 379 return !!(rd32(hw, hw->aq.asq.len) & 380 I40E_PF_ATQLEN_ATQENABLE_MASK); 381 return FALSE; 382 } 383 384 /** 385 * i40e_aq_queue_shutdown 386 * @hw: pointer to the hw struct 387 * @unloading: is the driver unloading itself 388 * 389 * Tell the Firmware that we're shutting down the AdminQ and whether 390 * or not the driver is unloading as well. 391 **/ 392 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 393 bool unloading) 394 { 395 struct i40e_aq_desc desc; 396 struct i40e_aqc_queue_shutdown *cmd = 397 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 398 enum i40e_status_code status; 399 400 i40e_fill_default_direct_cmd_desc(&desc, 401 i40e_aqc_opc_queue_shutdown); 402 403 if (unloading) 404 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 405 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 406 407 return status; 408 } 409 410 /** 411 * i40e_aq_get_set_rss_lut 412 * @hw: pointer to the hardware structure 413 * @vsi_id: vsi fw index 414 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 415 * @lut: pointer to the lut buffer provided by the caller 416 * @lut_size: size of the lut buffer 417 * @set: set TRUE to set the table, FALSE to get the table 418 * 419 * Internal function to get or set RSS look up table 420 **/ 421 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 422 u16 vsi_id, bool pf_lut, 423 u8 *lut, u16 lut_size, 424 bool set) 425 { 426 enum i40e_status_code status; 427 struct i40e_aq_desc desc; 428 struct i40e_aqc_get_set_rss_lut *cmd_resp = 429 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 430 431 if (set) 432 i40e_fill_default_direct_cmd_desc(&desc, 433 i40e_aqc_opc_set_rss_lut); 434 else 435 i40e_fill_default_direct_cmd_desc(&desc, 436 i40e_aqc_opc_get_rss_lut); 437 438 /* Indirect command */ 439 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 440 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 441 442 cmd_resp->vsi_id = 443 CPU_TO_LE16((u16)((vsi_id << 444 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 445 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 446 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 447 448 if (pf_lut) 449 cmd_resp->flags |= CPU_TO_LE16((u16) 450 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 451 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 452 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 453 else 454 cmd_resp->flags |= CPU_TO_LE16((u16) 455 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 456 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 457 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 458 459 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 460 461 return status; 462 } 463 464 /** 465 * i40e_aq_get_rss_lut 466 * @hw: pointer to the hardware structure 467 * @vsi_id: vsi fw index 468 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 469 * @lut: pointer to the lut buffer provided by the caller 470 * @lut_size: size of the lut buffer 471 * 472 * get the RSS lookup table, PF or VSI type 473 **/ 474 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 475 bool pf_lut, u8 *lut, u16 lut_size) 476 { 477 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 478 FALSE); 479 } 480 481 /** 482 * i40e_aq_set_rss_lut 483 * @hw: pointer to the hardware structure 484 * @vsi_id: vsi fw index 485 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 486 * @lut: pointer to the lut buffer provided by the caller 487 * @lut_size: size of the lut buffer 488 * 489 * set the RSS lookup table, PF or VSI type 490 **/ 491 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 492 bool pf_lut, u8 *lut, u16 lut_size) 493 { 494 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE); 495 } 496 497 /** 498 * i40e_aq_get_set_rss_key 499 * @hw: pointer to the hw struct 500 * @vsi_id: vsi fw index 501 * @key: pointer to key info struct 502 * @set: set TRUE to set the key, FALSE to get the key 503 * 504 * get the RSS key per VSI 505 **/ 506 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 507 u16 vsi_id, 508 struct i40e_aqc_get_set_rss_key_data *key, 509 bool set) 510 { 511 enum i40e_status_code status; 512 struct i40e_aq_desc desc; 513 struct i40e_aqc_get_set_rss_key *cmd_resp = 514 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 515 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 516 517 if (set) 518 i40e_fill_default_direct_cmd_desc(&desc, 519 i40e_aqc_opc_set_rss_key); 520 else 521 i40e_fill_default_direct_cmd_desc(&desc, 522 i40e_aqc_opc_get_rss_key); 523 524 /* Indirect command */ 525 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 526 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 527 528 cmd_resp->vsi_id = 529 CPU_TO_LE16((u16)((vsi_id << 530 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 531 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 532 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 533 534 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 535 536 return status; 537 } 538 539 /** 540 * i40e_aq_get_rss_key 541 * @hw: pointer to the hw struct 542 * @vsi_id: vsi fw index 543 * @key: pointer to key info struct 544 * 545 **/ 546 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 547 u16 vsi_id, 548 struct i40e_aqc_get_set_rss_key_data *key) 549 { 550 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE); 551 } 552 553 /** 554 * i40e_aq_set_rss_key 555 * @hw: pointer to the hw struct 556 * @vsi_id: vsi fw index 557 * @key: pointer to key info struct 558 * 559 * set the RSS key per VSI 560 **/ 561 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 562 u16 vsi_id, 563 struct i40e_aqc_get_set_rss_key_data *key) 564 { 565 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE); 566 } 567 568 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 569 * hardware to a bit-field that can be used by SW to more easily determine the 570 * packet type. 571 * 572 * Macros are used to shorten the table lines and make this table human 573 * readable. 574 * 575 * We store the PTYPE in the top byte of the bit field - this is just so that 576 * we can check that the table doesn't have a row missing, as the index into 577 * the table should be the PTYPE. 578 * 579 * Typical work flow: 580 * 581 * IF NOT i40e_ptype_lookup[ptype].known 582 * THEN 583 * Packet is unknown 584 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 585 * Use the rest of the fields to look at the tunnels, inner protocols, etc 586 * ELSE 587 * Use the enum i40e_rx_l2_ptype to decode the packet type 588 * ENDIF 589 */ 590 591 /* macro to make the table lines short */ 592 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 593 { PTYPE, \ 594 1, \ 595 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 596 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 597 I40E_RX_PTYPE_##OUTER_FRAG, \ 598 I40E_RX_PTYPE_TUNNEL_##T, \ 599 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 600 I40E_RX_PTYPE_##TEF, \ 601 I40E_RX_PTYPE_INNER_PROT_##I, \ 602 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 603 604 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 605 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 606 607 /* shorter macros makes the table fit but are terse */ 608 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 609 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 610 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 611 612 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 613 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 614 /* L2 Packet types */ 615 I40E_PTT_UNUSED_ENTRY(0), 616 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 617 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 618 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 619 I40E_PTT_UNUSED_ENTRY(4), 620 I40E_PTT_UNUSED_ENTRY(5), 621 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 622 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 623 I40E_PTT_UNUSED_ENTRY(8), 624 I40E_PTT_UNUSED_ENTRY(9), 625 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 626 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 627 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 628 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 629 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 630 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 631 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 632 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 633 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 634 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 635 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 636 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 637 638 /* Non Tunneled IPv4 */ 639 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 640 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 641 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 642 I40E_PTT_UNUSED_ENTRY(25), 643 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 644 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 645 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 646 647 /* IPv4 --> IPv4 */ 648 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 649 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 650 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 651 I40E_PTT_UNUSED_ENTRY(32), 652 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 653 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 654 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 655 656 /* IPv4 --> IPv6 */ 657 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 658 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 659 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 660 I40E_PTT_UNUSED_ENTRY(39), 661 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 662 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 663 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 664 665 /* IPv4 --> GRE/NAT */ 666 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 667 668 /* IPv4 --> GRE/NAT --> IPv4 */ 669 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 670 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 671 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 672 I40E_PTT_UNUSED_ENTRY(47), 673 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 674 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 675 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 676 677 /* IPv4 --> GRE/NAT --> IPv6 */ 678 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 679 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 680 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 681 I40E_PTT_UNUSED_ENTRY(54), 682 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 683 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 684 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 685 686 /* IPv4 --> GRE/NAT --> MAC */ 687 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 688 689 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 690 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 691 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 692 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 693 I40E_PTT_UNUSED_ENTRY(62), 694 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 695 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 696 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 697 698 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 699 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 700 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 701 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 702 I40E_PTT_UNUSED_ENTRY(69), 703 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 704 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 705 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 706 707 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 708 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 709 710 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 711 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 712 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 713 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 714 I40E_PTT_UNUSED_ENTRY(77), 715 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 716 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 717 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 718 719 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 720 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 721 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 722 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 723 I40E_PTT_UNUSED_ENTRY(84), 724 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 725 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 726 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 727 728 /* Non Tunneled IPv6 */ 729 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 730 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 731 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 732 I40E_PTT_UNUSED_ENTRY(91), 733 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 734 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 735 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 736 737 /* IPv6 --> IPv4 */ 738 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 739 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 740 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 741 I40E_PTT_UNUSED_ENTRY(98), 742 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 743 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 744 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 745 746 /* IPv6 --> IPv6 */ 747 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 748 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 749 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 750 I40E_PTT_UNUSED_ENTRY(105), 751 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 752 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 753 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 754 755 /* IPv6 --> GRE/NAT */ 756 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 757 758 /* IPv6 --> GRE/NAT -> IPv4 */ 759 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 760 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 761 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 762 I40E_PTT_UNUSED_ENTRY(113), 763 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 764 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 765 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 766 767 /* IPv6 --> GRE/NAT -> IPv6 */ 768 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 769 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 770 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 771 I40E_PTT_UNUSED_ENTRY(120), 772 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 773 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 774 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 775 776 /* IPv6 --> GRE/NAT -> MAC */ 777 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 778 779 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 780 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 781 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 782 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 783 I40E_PTT_UNUSED_ENTRY(128), 784 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 785 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 786 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 787 788 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 789 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 790 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 791 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 792 I40E_PTT_UNUSED_ENTRY(135), 793 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 794 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 795 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 796 797 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 798 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 799 800 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 801 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 802 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 803 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 804 I40E_PTT_UNUSED_ENTRY(143), 805 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 806 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 807 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 808 809 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 810 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 811 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 812 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 813 I40E_PTT_UNUSED_ENTRY(150), 814 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 815 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 816 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 817 818 /* unused entries */ 819 I40E_PTT_UNUSED_ENTRY(154), 820 I40E_PTT_UNUSED_ENTRY(155), 821 I40E_PTT_UNUSED_ENTRY(156), 822 I40E_PTT_UNUSED_ENTRY(157), 823 I40E_PTT_UNUSED_ENTRY(158), 824 I40E_PTT_UNUSED_ENTRY(159), 825 826 I40E_PTT_UNUSED_ENTRY(160), 827 I40E_PTT_UNUSED_ENTRY(161), 828 I40E_PTT_UNUSED_ENTRY(162), 829 I40E_PTT_UNUSED_ENTRY(163), 830 I40E_PTT_UNUSED_ENTRY(164), 831 I40E_PTT_UNUSED_ENTRY(165), 832 I40E_PTT_UNUSED_ENTRY(166), 833 I40E_PTT_UNUSED_ENTRY(167), 834 I40E_PTT_UNUSED_ENTRY(168), 835 I40E_PTT_UNUSED_ENTRY(169), 836 837 I40E_PTT_UNUSED_ENTRY(170), 838 I40E_PTT_UNUSED_ENTRY(171), 839 I40E_PTT_UNUSED_ENTRY(172), 840 I40E_PTT_UNUSED_ENTRY(173), 841 I40E_PTT_UNUSED_ENTRY(174), 842 I40E_PTT_UNUSED_ENTRY(175), 843 I40E_PTT_UNUSED_ENTRY(176), 844 I40E_PTT_UNUSED_ENTRY(177), 845 I40E_PTT_UNUSED_ENTRY(178), 846 I40E_PTT_UNUSED_ENTRY(179), 847 848 I40E_PTT_UNUSED_ENTRY(180), 849 I40E_PTT_UNUSED_ENTRY(181), 850 I40E_PTT_UNUSED_ENTRY(182), 851 I40E_PTT_UNUSED_ENTRY(183), 852 I40E_PTT_UNUSED_ENTRY(184), 853 I40E_PTT_UNUSED_ENTRY(185), 854 I40E_PTT_UNUSED_ENTRY(186), 855 I40E_PTT_UNUSED_ENTRY(187), 856 I40E_PTT_UNUSED_ENTRY(188), 857 I40E_PTT_UNUSED_ENTRY(189), 858 859 I40E_PTT_UNUSED_ENTRY(190), 860 I40E_PTT_UNUSED_ENTRY(191), 861 I40E_PTT_UNUSED_ENTRY(192), 862 I40E_PTT_UNUSED_ENTRY(193), 863 I40E_PTT_UNUSED_ENTRY(194), 864 I40E_PTT_UNUSED_ENTRY(195), 865 I40E_PTT_UNUSED_ENTRY(196), 866 I40E_PTT_UNUSED_ENTRY(197), 867 I40E_PTT_UNUSED_ENTRY(198), 868 I40E_PTT_UNUSED_ENTRY(199), 869 870 I40E_PTT_UNUSED_ENTRY(200), 871 I40E_PTT_UNUSED_ENTRY(201), 872 I40E_PTT_UNUSED_ENTRY(202), 873 I40E_PTT_UNUSED_ENTRY(203), 874 I40E_PTT_UNUSED_ENTRY(204), 875 I40E_PTT_UNUSED_ENTRY(205), 876 I40E_PTT_UNUSED_ENTRY(206), 877 I40E_PTT_UNUSED_ENTRY(207), 878 I40E_PTT_UNUSED_ENTRY(208), 879 I40E_PTT_UNUSED_ENTRY(209), 880 881 I40E_PTT_UNUSED_ENTRY(210), 882 I40E_PTT_UNUSED_ENTRY(211), 883 I40E_PTT_UNUSED_ENTRY(212), 884 I40E_PTT_UNUSED_ENTRY(213), 885 I40E_PTT_UNUSED_ENTRY(214), 886 I40E_PTT_UNUSED_ENTRY(215), 887 I40E_PTT_UNUSED_ENTRY(216), 888 I40E_PTT_UNUSED_ENTRY(217), 889 I40E_PTT_UNUSED_ENTRY(218), 890 I40E_PTT_UNUSED_ENTRY(219), 891 892 I40E_PTT_UNUSED_ENTRY(220), 893 I40E_PTT_UNUSED_ENTRY(221), 894 I40E_PTT_UNUSED_ENTRY(222), 895 I40E_PTT_UNUSED_ENTRY(223), 896 I40E_PTT_UNUSED_ENTRY(224), 897 I40E_PTT_UNUSED_ENTRY(225), 898 I40E_PTT_UNUSED_ENTRY(226), 899 I40E_PTT_UNUSED_ENTRY(227), 900 I40E_PTT_UNUSED_ENTRY(228), 901 I40E_PTT_UNUSED_ENTRY(229), 902 903 I40E_PTT_UNUSED_ENTRY(230), 904 I40E_PTT_UNUSED_ENTRY(231), 905 I40E_PTT_UNUSED_ENTRY(232), 906 I40E_PTT_UNUSED_ENTRY(233), 907 I40E_PTT_UNUSED_ENTRY(234), 908 I40E_PTT_UNUSED_ENTRY(235), 909 I40E_PTT_UNUSED_ENTRY(236), 910 I40E_PTT_UNUSED_ENTRY(237), 911 I40E_PTT_UNUSED_ENTRY(238), 912 I40E_PTT_UNUSED_ENTRY(239), 913 914 I40E_PTT_UNUSED_ENTRY(240), 915 I40E_PTT_UNUSED_ENTRY(241), 916 I40E_PTT_UNUSED_ENTRY(242), 917 I40E_PTT_UNUSED_ENTRY(243), 918 I40E_PTT_UNUSED_ENTRY(244), 919 I40E_PTT_UNUSED_ENTRY(245), 920 I40E_PTT_UNUSED_ENTRY(246), 921 I40E_PTT_UNUSED_ENTRY(247), 922 I40E_PTT_UNUSED_ENTRY(248), 923 I40E_PTT_UNUSED_ENTRY(249), 924 925 I40E_PTT_UNUSED_ENTRY(250), 926 I40E_PTT_UNUSED_ENTRY(251), 927 I40E_PTT_UNUSED_ENTRY(252), 928 I40E_PTT_UNUSED_ENTRY(253), 929 I40E_PTT_UNUSED_ENTRY(254), 930 I40E_PTT_UNUSED_ENTRY(255) 931 }; 932 933 934 /** 935 * i40e_validate_mac_addr - Validate unicast MAC address 936 * @mac_addr: pointer to MAC address 937 * 938 * Tests a MAC address to ensure it is a valid Individual Address 939 **/ 940 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 941 { 942 enum i40e_status_code status = I40E_SUCCESS; 943 944 DEBUGFUNC("i40e_validate_mac_addr"); 945 946 /* Broadcast addresses ARE multicast addresses 947 * Make sure it is not a multicast address 948 * Reject the zero address 949 */ 950 if (I40E_IS_MULTICAST(mac_addr) || 951 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 952 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 953 status = I40E_ERR_INVALID_MAC_ADDR; 954 955 return status; 956 } 957 958 /** 959 * i40e_init_shared_code - Initialize the shared code 960 * @hw: pointer to hardware structure 961 * 962 * This assigns the MAC type and PHY code and inits the NVM. 963 * Does not touch the hardware. This function must be called prior to any 964 * other function in the shared code. The i40e_hw structure should be 965 * memset to 0 prior to calling this function. The following fields in 966 * hw structure should be filled in prior to calling this function: 967 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 968 * subsystem_vendor_id, and revision_id 969 **/ 970 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 971 { 972 enum i40e_status_code status = I40E_SUCCESS; 973 u32 port, ari, func_rid; 974 975 DEBUGFUNC("i40e_init_shared_code"); 976 977 i40e_set_mac_type(hw); 978 979 switch (hw->mac.type) { 980 case I40E_MAC_XL710: 981 case I40E_MAC_X722: 982 break; 983 default: 984 return I40E_ERR_DEVICE_NOT_SUPPORTED; 985 } 986 987 hw->phy.get_link_info = TRUE; 988 989 /* Determine port number and PF number*/ 990 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 991 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 992 hw->port = (u8)port; 993 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 994 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 995 func_rid = rd32(hw, I40E_PF_FUNC_RID); 996 if (ari) 997 hw->pf_id = (u8)(func_rid & 0xff); 998 else 999 hw->pf_id = (u8)(func_rid & 0x7); 1000 1001 if (hw->mac.type == I40E_MAC_X722) 1002 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 1003 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 1004 1005 status = i40e_init_nvm(hw); 1006 return status; 1007 } 1008 1009 /** 1010 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1011 * @hw: pointer to the hw struct 1012 * @flags: a return indicator of what addresses were added to the addr store 1013 * @addrs: the requestor's mac addr store 1014 * @cmd_details: pointer to command details structure or NULL 1015 **/ 1016 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1017 u16 *flags, 1018 struct i40e_aqc_mac_address_read_data *addrs, 1019 struct i40e_asq_cmd_details *cmd_details) 1020 { 1021 struct i40e_aq_desc desc; 1022 struct i40e_aqc_mac_address_read *cmd_data = 1023 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1024 enum i40e_status_code status; 1025 1026 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1027 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1028 1029 status = i40e_asq_send_command(hw, &desc, addrs, 1030 sizeof(*addrs), cmd_details); 1031 *flags = LE16_TO_CPU(cmd_data->command_flags); 1032 1033 return status; 1034 } 1035 1036 /** 1037 * i40e_aq_mac_address_write - Change the MAC addresses 1038 * @hw: pointer to the hw struct 1039 * @flags: indicates which MAC to be written 1040 * @mac_addr: address to write 1041 * @cmd_details: pointer to command details structure or NULL 1042 **/ 1043 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1044 u16 flags, u8 *mac_addr, 1045 struct i40e_asq_cmd_details *cmd_details) 1046 { 1047 struct i40e_aq_desc desc; 1048 struct i40e_aqc_mac_address_write *cmd_data = 1049 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1050 enum i40e_status_code status; 1051 1052 i40e_fill_default_direct_cmd_desc(&desc, 1053 i40e_aqc_opc_mac_address_write); 1054 cmd_data->command_flags = CPU_TO_LE16(flags); 1055 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1056 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1057 ((u32)mac_addr[3] << 16) | 1058 ((u32)mac_addr[4] << 8) | 1059 mac_addr[5]); 1060 1061 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1062 1063 return status; 1064 } 1065 1066 /** 1067 * i40e_get_mac_addr - get MAC address 1068 * @hw: pointer to the HW structure 1069 * @mac_addr: pointer to MAC address 1070 * 1071 * Reads the adapter's MAC address from register 1072 **/ 1073 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1074 { 1075 struct i40e_aqc_mac_address_read_data addrs; 1076 enum i40e_status_code status; 1077 u16 flags = 0; 1078 1079 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1080 1081 if (flags & I40E_AQC_LAN_ADDR_VALID) 1082 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1083 I40E_NONDMA_TO_NONDMA); 1084 1085 return status; 1086 } 1087 1088 /** 1089 * i40e_get_port_mac_addr - get Port MAC address 1090 * @hw: pointer to the HW structure 1091 * @mac_addr: pointer to Port MAC address 1092 * 1093 * Reads the adapter's Port MAC address 1094 **/ 1095 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1096 { 1097 struct i40e_aqc_mac_address_read_data addrs; 1098 enum i40e_status_code status; 1099 u16 flags = 0; 1100 1101 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1102 if (status) 1103 return status; 1104 1105 if (flags & I40E_AQC_PORT_ADDR_VALID) 1106 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1107 I40E_NONDMA_TO_NONDMA); 1108 else 1109 status = I40E_ERR_INVALID_MAC_ADDR; 1110 1111 return status; 1112 } 1113 1114 /** 1115 * i40e_pre_tx_queue_cfg - pre tx queue configure 1116 * @hw: pointer to the HW structure 1117 * @queue: target pf queue index 1118 * @enable: state change request 1119 * 1120 * Handles hw requirement to indicate intention to enable 1121 * or disable target queue. 1122 **/ 1123 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1124 { 1125 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1126 u32 reg_block = 0; 1127 u32 reg_val; 1128 1129 if (abs_queue_idx >= 128) { 1130 reg_block = abs_queue_idx / 128; 1131 abs_queue_idx %= 128; 1132 } 1133 1134 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1135 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1136 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1137 1138 if (enable) 1139 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1140 else 1141 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1142 1143 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1144 } 1145 1146 /** 1147 * i40e_read_pba_string - Reads part number string from EEPROM 1148 * @hw: pointer to hardware structure 1149 * @pba_num: stores the part number string from the EEPROM 1150 * @pba_num_size: part number string buffer length 1151 * 1152 * Reads the part number string from the EEPROM. 1153 **/ 1154 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1155 u32 pba_num_size) 1156 { 1157 enum i40e_status_code status = I40E_SUCCESS; 1158 u16 pba_word = 0; 1159 u16 pba_size = 0; 1160 u16 pba_ptr = 0; 1161 u16 i = 0; 1162 1163 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1164 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1165 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1166 return status; 1167 } 1168 1169 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1170 if (status != I40E_SUCCESS) { 1171 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1172 return status; 1173 } 1174 1175 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1176 if (status != I40E_SUCCESS) { 1177 DEBUGOUT("Failed to read PBA Block size.\n"); 1178 return status; 1179 } 1180 1181 /* Subtract one to get PBA word count (PBA Size word is included in 1182 * total size) 1183 */ 1184 pba_size--; 1185 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1186 DEBUGOUT("Buffer to small for PBA data.\n"); 1187 return I40E_ERR_PARAM; 1188 } 1189 1190 for (i = 0; i < pba_size; i++) { 1191 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1192 if (status != I40E_SUCCESS) { 1193 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1194 return status; 1195 } 1196 1197 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1198 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1199 } 1200 pba_num[(pba_size * 2)] = '\0'; 1201 1202 return status; 1203 } 1204 1205 /** 1206 * i40e_get_media_type - Gets media type 1207 * @hw: pointer to the hardware structure 1208 **/ 1209 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1210 { 1211 enum i40e_media_type media; 1212 1213 switch (hw->phy.link_info.phy_type) { 1214 case I40E_PHY_TYPE_10GBASE_SR: 1215 case I40E_PHY_TYPE_10GBASE_LR: 1216 case I40E_PHY_TYPE_1000BASE_SX: 1217 case I40E_PHY_TYPE_1000BASE_LX: 1218 case I40E_PHY_TYPE_40GBASE_SR4: 1219 case I40E_PHY_TYPE_40GBASE_LR4: 1220 case I40E_PHY_TYPE_25GBASE_LR: 1221 case I40E_PHY_TYPE_25GBASE_SR: 1222 media = I40E_MEDIA_TYPE_FIBER; 1223 break; 1224 case I40E_PHY_TYPE_100BASE_TX: 1225 case I40E_PHY_TYPE_1000BASE_T: 1226 case I40E_PHY_TYPE_10GBASE_T: 1227 media = I40E_MEDIA_TYPE_BASET; 1228 break; 1229 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1230 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1231 case I40E_PHY_TYPE_10GBASE_CR1: 1232 case I40E_PHY_TYPE_40GBASE_CR4: 1233 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1234 case I40E_PHY_TYPE_40GBASE_AOC: 1235 case I40E_PHY_TYPE_10GBASE_AOC: 1236 case I40E_PHY_TYPE_25GBASE_CR: 1237 case I40E_PHY_TYPE_25GBASE_AOC: 1238 case I40E_PHY_TYPE_25GBASE_ACC: 1239 media = I40E_MEDIA_TYPE_DA; 1240 break; 1241 case I40E_PHY_TYPE_1000BASE_KX: 1242 case I40E_PHY_TYPE_10GBASE_KX4: 1243 case I40E_PHY_TYPE_10GBASE_KR: 1244 case I40E_PHY_TYPE_40GBASE_KR4: 1245 case I40E_PHY_TYPE_20GBASE_KR2: 1246 case I40E_PHY_TYPE_25GBASE_KR: 1247 media = I40E_MEDIA_TYPE_BACKPLANE; 1248 break; 1249 case I40E_PHY_TYPE_SGMII: 1250 case I40E_PHY_TYPE_XAUI: 1251 case I40E_PHY_TYPE_XFI: 1252 case I40E_PHY_TYPE_XLAUI: 1253 case I40E_PHY_TYPE_XLPPI: 1254 default: 1255 media = I40E_MEDIA_TYPE_UNKNOWN; 1256 break; 1257 } 1258 1259 return media; 1260 } 1261 1262 #define I40E_PF_RESET_WAIT_COUNT 200 1263 /** 1264 * i40e_pf_reset - Reset the PF 1265 * @hw: pointer to the hardware structure 1266 * 1267 * Assuming someone else has triggered a global reset, 1268 * assure the global reset is complete and then reset the PF 1269 **/ 1270 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1271 { 1272 u32 cnt = 0; 1273 u32 cnt1 = 0; 1274 u32 reg = 0; 1275 u32 grst_del; 1276 1277 /* Poll for Global Reset steady state in case of recent GRST. 1278 * The grst delay value is in 100ms units, and we'll wait a 1279 * couple counts longer to be sure we don't just miss the end. 1280 */ 1281 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1282 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1283 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1284 1285 grst_del = grst_del * 20; 1286 1287 for (cnt = 0; cnt < grst_del; cnt++) { 1288 reg = rd32(hw, I40E_GLGEN_RSTAT); 1289 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1290 break; 1291 i40e_msec_delay(100); 1292 } 1293 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1294 DEBUGOUT("Global reset polling failed to complete.\n"); 1295 return I40E_ERR_RESET_FAILED; 1296 } 1297 1298 /* Now Wait for the FW to be ready */ 1299 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1300 reg = rd32(hw, I40E_GLNVM_ULD); 1301 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1302 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1303 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1304 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1305 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1306 break; 1307 } 1308 i40e_msec_delay(10); 1309 } 1310 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1311 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1312 DEBUGOUT("wait for FW Reset complete timedout\n"); 1313 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1314 return I40E_ERR_RESET_FAILED; 1315 } 1316 1317 /* If there was a Global Reset in progress when we got here, 1318 * we don't need to do the PF Reset 1319 */ 1320 if (!cnt) { 1321 u32 reg2 = 0; 1322 1323 reg = rd32(hw, I40E_PFGEN_CTRL); 1324 wr32(hw, I40E_PFGEN_CTRL, 1325 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1326 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1327 reg = rd32(hw, I40E_PFGEN_CTRL); 1328 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1329 break; 1330 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1331 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1332 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n"); 1333 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2); 1334 return I40E_ERR_NOT_READY; 1335 } 1336 i40e_msec_delay(1); 1337 } 1338 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1339 DEBUGOUT("PF reset polling failed to complete.\n"); 1340 return I40E_ERR_RESET_FAILED; 1341 } 1342 } 1343 1344 i40e_clear_pxe_mode(hw); 1345 1346 1347 return I40E_SUCCESS; 1348 } 1349 1350 /** 1351 * i40e_clear_hw - clear out any left over hw state 1352 * @hw: pointer to the hw struct 1353 * 1354 * Clear queues and interrupts, typically called at init time, 1355 * but after the capabilities have been found so we know how many 1356 * queues and msix vectors have been allocated. 1357 **/ 1358 void i40e_clear_hw(struct i40e_hw *hw) 1359 { 1360 u32 num_queues, base_queue; 1361 u32 num_pf_int; 1362 u32 num_vf_int; 1363 u32 num_vfs; 1364 u32 i, j; 1365 u32 val; 1366 u32 eol = 0x7ff; 1367 1368 /* get number of interrupts, queues, and vfs */ 1369 val = rd32(hw, I40E_GLPCI_CNF2); 1370 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1371 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1372 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1373 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1374 1375 val = rd32(hw, I40E_PFLAN_QALLOC); 1376 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1377 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1378 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1379 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1380 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1381 num_queues = (j - base_queue) + 1; 1382 else 1383 num_queues = 0; 1384 1385 val = rd32(hw, I40E_PF_VT_PFALLOC); 1386 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1387 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1388 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1389 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1390 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1391 num_vfs = (j - i) + 1; 1392 else 1393 num_vfs = 0; 1394 1395 /* stop all the interrupts */ 1396 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1397 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1398 for (i = 0; i < num_pf_int - 2; i++) 1399 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1400 1401 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1402 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1403 wr32(hw, I40E_PFINT_LNKLST0, val); 1404 for (i = 0; i < num_pf_int - 2; i++) 1405 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1406 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1407 for (i = 0; i < num_vfs; i++) 1408 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1409 for (i = 0; i < num_vf_int - 2; i++) 1410 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1411 1412 /* warn the HW of the coming Tx disables */ 1413 for (i = 0; i < num_queues; i++) { 1414 u32 abs_queue_idx = base_queue + i; 1415 u32 reg_block = 0; 1416 1417 if (abs_queue_idx >= 128) { 1418 reg_block = abs_queue_idx / 128; 1419 abs_queue_idx %= 128; 1420 } 1421 1422 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1423 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1424 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1425 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1426 1427 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1428 } 1429 i40e_usec_delay(400); 1430 1431 /* stop all the queues */ 1432 for (i = 0; i < num_queues; i++) { 1433 wr32(hw, I40E_QINT_TQCTL(i), 0); 1434 wr32(hw, I40E_QTX_ENA(i), 0); 1435 wr32(hw, I40E_QINT_RQCTL(i), 0); 1436 wr32(hw, I40E_QRX_ENA(i), 0); 1437 } 1438 1439 /* short wait for all queue disables to settle */ 1440 i40e_usec_delay(50); 1441 } 1442 1443 /** 1444 * i40e_clear_pxe_mode - clear pxe operations mode 1445 * @hw: pointer to the hw struct 1446 * 1447 * Make sure all PXE mode settings are cleared, including things 1448 * like descriptor fetch/write-back mode. 1449 **/ 1450 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1451 { 1452 if (i40e_check_asq_alive(hw)) 1453 i40e_aq_clear_pxe_mode(hw, NULL); 1454 } 1455 1456 /** 1457 * i40e_led_is_mine - helper to find matching led 1458 * @hw: pointer to the hw struct 1459 * @idx: index into GPIO registers 1460 * 1461 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1462 */ 1463 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1464 { 1465 u32 gpio_val = 0; 1466 u32 port; 1467 1468 if (!hw->func_caps.led[idx]) 1469 return 0; 1470 1471 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1472 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1473 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1474 1475 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1476 * if it is not our port then ignore 1477 */ 1478 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1479 (port != hw->port)) 1480 return 0; 1481 1482 return gpio_val; 1483 } 1484 1485 #define I40E_COMBINED_ACTIVITY 0xA 1486 #define I40E_FILTER_ACTIVITY 0xE 1487 #define I40E_LINK_ACTIVITY 0xC 1488 #define I40E_MAC_ACTIVITY 0xD 1489 #define I40E_LED0 22 1490 1491 /** 1492 * i40e_led_get - return current on/off mode 1493 * @hw: pointer to the hw struct 1494 * 1495 * The value returned is the 'mode' field as defined in the 1496 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1497 * values are variations of possible behaviors relating to 1498 * blink, link, and wire. 1499 **/ 1500 u32 i40e_led_get(struct i40e_hw *hw) 1501 { 1502 u32 current_mode = 0; 1503 u32 mode = 0; 1504 int i; 1505 1506 /* as per the documentation GPIO 22-29 are the LED 1507 * GPIO pins named LED0..LED7 1508 */ 1509 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1510 u32 gpio_val = i40e_led_is_mine(hw, i); 1511 1512 if (!gpio_val) 1513 continue; 1514 1515 /* ignore gpio LED src mode entries related to the activity 1516 * LEDs 1517 */ 1518 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1519 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1520 switch (current_mode) { 1521 case I40E_COMBINED_ACTIVITY: 1522 case I40E_FILTER_ACTIVITY: 1523 case I40E_MAC_ACTIVITY: 1524 case I40E_LINK_ACTIVITY: 1525 continue; 1526 default: 1527 break; 1528 } 1529 1530 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1531 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1532 break; 1533 } 1534 1535 return mode; 1536 } 1537 1538 /** 1539 * i40e_led_set - set new on/off mode 1540 * @hw: pointer to the hw struct 1541 * @mode: 0=off, 0xf=on (else see manual for mode details) 1542 * @blink: TRUE if the LED should blink when on, FALSE if steady 1543 * 1544 * if this function is used to turn on the blink it should 1545 * be used to disable the blink when restoring the original state. 1546 **/ 1547 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1548 { 1549 u32 current_mode = 0; 1550 int i; 1551 1552 if (mode & 0xfffffff0) 1553 DEBUGOUT1("invalid mode passed in %X\n", mode); 1554 1555 /* as per the documentation GPIO 22-29 are the LED 1556 * GPIO pins named LED0..LED7 1557 */ 1558 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1559 u32 gpio_val = i40e_led_is_mine(hw, i); 1560 1561 if (!gpio_val) 1562 continue; 1563 1564 /* ignore gpio LED src mode entries related to the activity 1565 * LEDs 1566 */ 1567 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1568 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1569 switch (current_mode) { 1570 case I40E_COMBINED_ACTIVITY: 1571 case I40E_FILTER_ACTIVITY: 1572 case I40E_MAC_ACTIVITY: 1573 case I40E_LINK_ACTIVITY: 1574 continue; 1575 default: 1576 break; 1577 } 1578 1579 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1580 /* this & is a bit of paranoia, but serves as a range check */ 1581 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1582 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1583 1584 if (blink) 1585 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1586 else 1587 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1588 1589 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1590 break; 1591 } 1592 } 1593 1594 /* Admin command wrappers */ 1595 1596 /** 1597 * i40e_aq_get_phy_capabilities 1598 * @hw: pointer to the hw struct 1599 * @abilities: structure for PHY capabilities to be filled 1600 * @qualified_modules: report Qualified Modules 1601 * @report_init: report init capabilities (active are default) 1602 * @cmd_details: pointer to command details structure or NULL 1603 * 1604 * Returns the various PHY abilities supported on the Port. 1605 **/ 1606 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1607 bool qualified_modules, bool report_init, 1608 struct i40e_aq_get_phy_abilities_resp *abilities, 1609 struct i40e_asq_cmd_details *cmd_details) 1610 { 1611 struct i40e_aq_desc desc; 1612 enum i40e_status_code status; 1613 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1614 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1615 1616 if (!abilities) 1617 return I40E_ERR_PARAM; 1618 1619 do { 1620 i40e_fill_default_direct_cmd_desc(&desc, 1621 i40e_aqc_opc_get_phy_abilities); 1622 1623 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1624 if (abilities_size > I40E_AQ_LARGE_BUF) 1625 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1626 1627 if (qualified_modules) 1628 desc.params.external.param0 |= 1629 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1630 1631 if (report_init) 1632 desc.params.external.param0 |= 1633 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1634 1635 status = i40e_asq_send_command(hw, &desc, abilities, 1636 abilities_size, cmd_details); 1637 1638 if (status != I40E_SUCCESS) 1639 break; 1640 1641 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { 1642 status = I40E_ERR_UNKNOWN_PHY; 1643 break; 1644 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { 1645 i40e_msec_delay(1); 1646 total_delay++; 1647 status = I40E_ERR_TIMEOUT; 1648 } 1649 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && 1650 (total_delay < max_delay)); 1651 1652 if (status != I40E_SUCCESS) 1653 return status; 1654 1655 if (report_init) { 1656 if (hw->mac.type == I40E_MAC_XL710 && 1657 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1658 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1659 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 1660 } else { 1661 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1662 hw->phy.phy_types |= 1663 ((u64)abilities->phy_type_ext << 32); 1664 } 1665 } 1666 1667 return status; 1668 } 1669 1670 /** 1671 * i40e_aq_set_phy_config 1672 * @hw: pointer to the hw struct 1673 * @config: structure with PHY configuration to be set 1674 * @cmd_details: pointer to command details structure or NULL 1675 * 1676 * Set the various PHY configuration parameters 1677 * supported on the Port.One or more of the Set PHY config parameters may be 1678 * ignored in an MFP mode as the PF may not have the privilege to set some 1679 * of the PHY Config parameters. This status will be indicated by the 1680 * command response. 1681 **/ 1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1683 struct i40e_aq_set_phy_config *config, 1684 struct i40e_asq_cmd_details *cmd_details) 1685 { 1686 struct i40e_aq_desc desc; 1687 struct i40e_aq_set_phy_config *cmd = 1688 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1689 enum i40e_status_code status; 1690 1691 if (!config) 1692 return I40E_ERR_PARAM; 1693 1694 i40e_fill_default_direct_cmd_desc(&desc, 1695 i40e_aqc_opc_set_phy_config); 1696 1697 *cmd = *config; 1698 1699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1700 1701 return status; 1702 } 1703 1704 /** 1705 * i40e_set_fc 1706 * @hw: pointer to the hw struct 1707 * @aq_failures: buffer to return AdminQ failure information 1708 * @atomic_restart: whether to enable atomic link restart 1709 * 1710 * Set the requested flow control mode using set_phy_config. 1711 **/ 1712 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1713 bool atomic_restart) 1714 { 1715 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1716 struct i40e_aq_get_phy_abilities_resp abilities; 1717 struct i40e_aq_set_phy_config config; 1718 enum i40e_status_code status; 1719 u8 pause_mask = 0x0; 1720 1721 *aq_failures = 0x0; 1722 1723 switch (fc_mode) { 1724 case I40E_FC_FULL: 1725 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1726 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1727 break; 1728 case I40E_FC_RX_PAUSE: 1729 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1730 break; 1731 case I40E_FC_TX_PAUSE: 1732 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1733 break; 1734 default: 1735 break; 1736 } 1737 1738 /* Get the current phy config */ 1739 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1740 NULL); 1741 if (status) { 1742 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1743 return status; 1744 } 1745 1746 memset(&config, 0, sizeof(config)); 1747 /* clear the old pause settings */ 1748 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1749 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1750 /* set the new abilities */ 1751 config.abilities |= pause_mask; 1752 /* If the abilities have changed, then set the new config */ 1753 if (config.abilities != abilities.abilities) { 1754 /* Auto restart link so settings take effect */ 1755 if (atomic_restart) 1756 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1757 /* Copy over all the old settings */ 1758 config.phy_type = abilities.phy_type; 1759 config.phy_type_ext = abilities.phy_type_ext; 1760 config.link_speed = abilities.link_speed; 1761 config.eee_capability = abilities.eee_capability; 1762 config.eeer = abilities.eeer_val; 1763 config.low_power_ctrl = abilities.d3_lpan; 1764 status = i40e_aq_set_phy_config(hw, &config, NULL); 1765 1766 if (status) 1767 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1768 } 1769 /* Update the link info */ 1770 status = i40e_update_link_info(hw); 1771 if (status) { 1772 /* Wait a little bit (on 40G cards it sometimes takes a really 1773 * long time for link to come back from the atomic reset) 1774 * and try once more 1775 */ 1776 i40e_msec_delay(1000); 1777 status = i40e_update_link_info(hw); 1778 } 1779 if (status) 1780 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1781 1782 return status; 1783 } 1784 1785 /** 1786 * i40e_aq_set_mac_config 1787 * @hw: pointer to the hw struct 1788 * @max_frame_size: Maximum Frame Size to be supported by the port 1789 * @crc_en: Tell HW to append a CRC to outgoing frames 1790 * @pacing: Pacing configurations 1791 * @cmd_details: pointer to command details structure or NULL 1792 * 1793 * Configure MAC settings for frame size, jumbo frame support and the 1794 * addition of a CRC by the hardware. 1795 **/ 1796 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1797 u16 max_frame_size, 1798 bool crc_en, u16 pacing, 1799 struct i40e_asq_cmd_details *cmd_details) 1800 { 1801 struct i40e_aq_desc desc; 1802 struct i40e_aq_set_mac_config *cmd = 1803 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1804 enum i40e_status_code status; 1805 1806 if (max_frame_size == 0) 1807 return I40E_ERR_PARAM; 1808 1809 i40e_fill_default_direct_cmd_desc(&desc, 1810 i40e_aqc_opc_set_mac_config); 1811 1812 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1813 cmd->params = ((u8)pacing & 0x0F) << 3; 1814 if (crc_en) 1815 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1816 1817 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1818 1819 return status; 1820 } 1821 1822 /** 1823 * i40e_aq_clear_pxe_mode 1824 * @hw: pointer to the hw struct 1825 * @cmd_details: pointer to command details structure or NULL 1826 * 1827 * Tell the firmware that the driver is taking over from PXE 1828 **/ 1829 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1830 struct i40e_asq_cmd_details *cmd_details) 1831 { 1832 enum i40e_status_code status; 1833 struct i40e_aq_desc desc; 1834 struct i40e_aqc_clear_pxe *cmd = 1835 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1836 1837 i40e_fill_default_direct_cmd_desc(&desc, 1838 i40e_aqc_opc_clear_pxe_mode); 1839 1840 cmd->rx_cnt = 0x2; 1841 1842 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1843 1844 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1845 1846 return status; 1847 } 1848 1849 /** 1850 * i40e_aq_set_link_restart_an 1851 * @hw: pointer to the hw struct 1852 * @enable_link: if TRUE: enable link, if FALSE: disable link 1853 * @cmd_details: pointer to command details structure or NULL 1854 * 1855 * Sets up the link and restarts the Auto-Negotiation over the link. 1856 **/ 1857 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1858 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1859 { 1860 struct i40e_aq_desc desc; 1861 struct i40e_aqc_set_link_restart_an *cmd = 1862 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1863 enum i40e_status_code status; 1864 1865 i40e_fill_default_direct_cmd_desc(&desc, 1866 i40e_aqc_opc_set_link_restart_an); 1867 1868 cmd->command = I40E_AQ_PHY_RESTART_AN; 1869 if (enable_link) 1870 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1871 else 1872 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1873 1874 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1875 1876 return status; 1877 } 1878 1879 /** 1880 * i40e_aq_get_link_info 1881 * @hw: pointer to the hw struct 1882 * @enable_lse: enable/disable LinkStatusEvent reporting 1883 * @link: pointer to link status structure - optional 1884 * @cmd_details: pointer to command details structure or NULL 1885 * 1886 * Returns the link status of the adapter. 1887 **/ 1888 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1889 bool enable_lse, struct i40e_link_status *link, 1890 struct i40e_asq_cmd_details *cmd_details) 1891 { 1892 struct i40e_aq_desc desc; 1893 struct i40e_aqc_get_link_status *resp = 1894 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1895 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1896 enum i40e_status_code status; 1897 bool tx_pause, rx_pause; 1898 u16 command_flags; 1899 1900 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1901 1902 if (enable_lse) 1903 command_flags = I40E_AQ_LSE_ENABLE; 1904 else 1905 command_flags = I40E_AQ_LSE_DISABLE; 1906 resp->command_flags = CPU_TO_LE16(command_flags); 1907 1908 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1909 1910 if (status != I40E_SUCCESS) 1911 goto aq_get_link_info_exit; 1912 1913 /* save off old link status information */ 1914 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1915 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1916 1917 /* update link status */ 1918 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1919 hw->phy.media_type = i40e_get_media_type(hw); 1920 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1921 hw_link_info->link_info = resp->link_info; 1922 hw_link_info->an_info = resp->an_info; 1923 hw_link_info->ext_info = resp->ext_info; 1924 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1925 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1926 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1927 1928 /* update fc info */ 1929 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1930 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1931 if (tx_pause & rx_pause) 1932 hw->fc.current_mode = I40E_FC_FULL; 1933 else if (tx_pause) 1934 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1935 else if (rx_pause) 1936 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1937 else 1938 hw->fc.current_mode = I40E_FC_NONE; 1939 1940 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1941 hw_link_info->crc_enable = TRUE; 1942 else 1943 hw_link_info->crc_enable = FALSE; 1944 1945 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 1946 hw_link_info->lse_enable = TRUE; 1947 else 1948 hw_link_info->lse_enable = FALSE; 1949 1950 if ((hw->mac.type == I40E_MAC_XL710) && 1951 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1952 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1953 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1954 1955 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1956 hw->aq.api_min_ver >= 7) { 1957 __le32 tmp; 1958 1959 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), 1960 I40E_NONDMA_TO_NONDMA); 1961 hw->phy.phy_types = LE32_TO_CPU(tmp); 1962 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1963 } 1964 1965 /* save link status information */ 1966 if (link) 1967 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1968 I40E_NONDMA_TO_NONDMA); 1969 1970 /* flag cleared so helper functions don't call AQ again */ 1971 hw->phy.get_link_info = FALSE; 1972 1973 aq_get_link_info_exit: 1974 return status; 1975 } 1976 1977 /** 1978 * i40e_aq_set_phy_int_mask 1979 * @hw: pointer to the hw struct 1980 * @mask: interrupt mask to be set 1981 * @cmd_details: pointer to command details structure or NULL 1982 * 1983 * Set link interrupt mask. 1984 **/ 1985 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1986 u16 mask, 1987 struct i40e_asq_cmd_details *cmd_details) 1988 { 1989 struct i40e_aq_desc desc; 1990 struct i40e_aqc_set_phy_int_mask *cmd = 1991 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1992 enum i40e_status_code status; 1993 1994 i40e_fill_default_direct_cmd_desc(&desc, 1995 i40e_aqc_opc_set_phy_int_mask); 1996 1997 cmd->event_mask = CPU_TO_LE16(mask); 1998 1999 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2000 2001 return status; 2002 } 2003 2004 /** 2005 * i40e_aq_get_local_advt_reg 2006 * @hw: pointer to the hw struct 2007 * @advt_reg: local AN advertisement register value 2008 * @cmd_details: pointer to command details structure or NULL 2009 * 2010 * Get the Local AN advertisement register value. 2011 **/ 2012 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 2013 u64 *advt_reg, 2014 struct i40e_asq_cmd_details *cmd_details) 2015 { 2016 struct i40e_aq_desc desc; 2017 struct i40e_aqc_an_advt_reg *resp = 2018 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2019 enum i40e_status_code status; 2020 2021 i40e_fill_default_direct_cmd_desc(&desc, 2022 i40e_aqc_opc_get_local_advt_reg); 2023 2024 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2025 2026 if (status != I40E_SUCCESS) 2027 goto aq_get_local_advt_reg_exit; 2028 2029 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2030 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2031 2032 aq_get_local_advt_reg_exit: 2033 return status; 2034 } 2035 2036 /** 2037 * i40e_aq_set_local_advt_reg 2038 * @hw: pointer to the hw struct 2039 * @advt_reg: local AN advertisement register value 2040 * @cmd_details: pointer to command details structure or NULL 2041 * 2042 * Get the Local AN advertisement register value. 2043 **/ 2044 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2045 u64 advt_reg, 2046 struct i40e_asq_cmd_details *cmd_details) 2047 { 2048 struct i40e_aq_desc desc; 2049 struct i40e_aqc_an_advt_reg *cmd = 2050 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2051 enum i40e_status_code status; 2052 2053 i40e_fill_default_direct_cmd_desc(&desc, 2054 i40e_aqc_opc_get_local_advt_reg); 2055 2056 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2057 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2058 2059 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2060 2061 return status; 2062 } 2063 2064 /** 2065 * i40e_aq_get_partner_advt 2066 * @hw: pointer to the hw struct 2067 * @advt_reg: AN partner advertisement register value 2068 * @cmd_details: pointer to command details structure or NULL 2069 * 2070 * Get the link partner AN advertisement register value. 2071 **/ 2072 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2073 u64 *advt_reg, 2074 struct i40e_asq_cmd_details *cmd_details) 2075 { 2076 struct i40e_aq_desc desc; 2077 struct i40e_aqc_an_advt_reg *resp = 2078 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2079 enum i40e_status_code status; 2080 2081 i40e_fill_default_direct_cmd_desc(&desc, 2082 i40e_aqc_opc_get_partner_advt); 2083 2084 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2085 2086 if (status != I40E_SUCCESS) 2087 goto aq_get_partner_advt_exit; 2088 2089 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2090 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2091 2092 aq_get_partner_advt_exit: 2093 return status; 2094 } 2095 2096 /** 2097 * i40e_aq_set_lb_modes 2098 * @hw: pointer to the hw struct 2099 * @lb_modes: loopback mode to be set 2100 * @cmd_details: pointer to command details structure or NULL 2101 * 2102 * Sets loopback modes. 2103 **/ 2104 enum i40e_status_code 2105 i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed, 2106 struct i40e_asq_cmd_details *cmd_details) 2107 { 2108 struct i40e_aq_desc desc; 2109 struct i40e_aqc_set_lb_mode *cmd = 2110 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2111 enum i40e_status_code status; 2112 2113 i40e_fill_default_direct_cmd_desc(&desc, 2114 i40e_aqc_opc_set_lb_modes); 2115 2116 cmd->lb_level = lb_level; 2117 cmd->lb_type = lb_type; 2118 cmd->speed = speed; 2119 if (speed) 2120 cmd->force_speed = 1; 2121 2122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2123 2124 return status; 2125 } 2126 2127 /** 2128 * i40e_aq_set_phy_debug 2129 * @hw: pointer to the hw struct 2130 * @cmd_flags: debug command flags 2131 * @cmd_details: pointer to command details structure or NULL 2132 * 2133 * Reset the external PHY. 2134 **/ 2135 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2136 struct i40e_asq_cmd_details *cmd_details) 2137 { 2138 struct i40e_aq_desc desc; 2139 struct i40e_aqc_set_phy_debug *cmd = 2140 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2141 enum i40e_status_code status; 2142 2143 i40e_fill_default_direct_cmd_desc(&desc, 2144 i40e_aqc_opc_set_phy_debug); 2145 2146 cmd->command_flags = cmd_flags; 2147 2148 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2149 2150 return status; 2151 } 2152 2153 /** 2154 * i40e_aq_add_vsi 2155 * @hw: pointer to the hw struct 2156 * @vsi_ctx: pointer to a vsi context struct 2157 * @cmd_details: pointer to command details structure or NULL 2158 * 2159 * Add a VSI context to the hardware. 2160 **/ 2161 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2162 struct i40e_vsi_context *vsi_ctx, 2163 struct i40e_asq_cmd_details *cmd_details) 2164 { 2165 struct i40e_aq_desc desc; 2166 struct i40e_aqc_add_get_update_vsi *cmd = 2167 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2168 struct i40e_aqc_add_get_update_vsi_completion *resp = 2169 (struct i40e_aqc_add_get_update_vsi_completion *) 2170 &desc.params.raw; 2171 enum i40e_status_code status; 2172 2173 i40e_fill_default_direct_cmd_desc(&desc, 2174 i40e_aqc_opc_add_vsi); 2175 2176 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2177 cmd->connection_type = vsi_ctx->connection_type; 2178 cmd->vf_id = vsi_ctx->vf_num; 2179 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2180 2181 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2182 2183 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2184 sizeof(vsi_ctx->info), cmd_details); 2185 2186 if (status != I40E_SUCCESS) 2187 goto aq_add_vsi_exit; 2188 2189 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2190 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2191 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2192 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2193 2194 aq_add_vsi_exit: 2195 return status; 2196 } 2197 2198 /** 2199 * i40e_aq_set_default_vsi 2200 * @hw: pointer to the hw struct 2201 * @seid: vsi number 2202 * @cmd_details: pointer to command details structure or NULL 2203 **/ 2204 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2205 u16 seid, 2206 struct i40e_asq_cmd_details *cmd_details) 2207 { 2208 struct i40e_aq_desc desc; 2209 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2210 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2211 &desc.params.raw; 2212 enum i40e_status_code status; 2213 2214 i40e_fill_default_direct_cmd_desc(&desc, 2215 i40e_aqc_opc_set_vsi_promiscuous_modes); 2216 2217 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2218 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2219 cmd->seid = CPU_TO_LE16(seid); 2220 2221 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2222 2223 return status; 2224 } 2225 2226 /** 2227 * i40e_aq_clear_default_vsi 2228 * @hw: pointer to the hw struct 2229 * @seid: vsi number 2230 * @cmd_details: pointer to command details structure or NULL 2231 **/ 2232 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2233 u16 seid, 2234 struct i40e_asq_cmd_details *cmd_details) 2235 { 2236 struct i40e_aq_desc desc; 2237 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2238 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2239 &desc.params.raw; 2240 enum i40e_status_code status; 2241 2242 i40e_fill_default_direct_cmd_desc(&desc, 2243 i40e_aqc_opc_set_vsi_promiscuous_modes); 2244 2245 cmd->promiscuous_flags = CPU_TO_LE16(0); 2246 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2247 cmd->seid = CPU_TO_LE16(seid); 2248 2249 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2250 2251 return status; 2252 } 2253 2254 /** 2255 * i40e_aq_set_vsi_unicast_promiscuous 2256 * @hw: pointer to the hw struct 2257 * @seid: vsi number 2258 * @set: set unicast promiscuous enable/disable 2259 * @cmd_details: pointer to command details structure or NULL 2260 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2261 **/ 2262 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2263 u16 seid, bool set, 2264 struct i40e_asq_cmd_details *cmd_details, 2265 bool rx_only_promisc) 2266 { 2267 struct i40e_aq_desc desc; 2268 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2269 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2270 enum i40e_status_code status; 2271 u16 flags = 0; 2272 2273 i40e_fill_default_direct_cmd_desc(&desc, 2274 i40e_aqc_opc_set_vsi_promiscuous_modes); 2275 2276 if (set) { 2277 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2278 if (rx_only_promisc && 2279 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2280 (hw->aq.api_maj_ver > 1))) 2281 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2282 } 2283 2284 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2285 2286 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2287 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2288 (hw->aq.api_maj_ver > 1)) 2289 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2290 2291 cmd->seid = CPU_TO_LE16(seid); 2292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2293 2294 return status; 2295 } 2296 2297 /** 2298 * i40e_aq_set_vsi_multicast_promiscuous 2299 * @hw: pointer to the hw struct 2300 * @seid: vsi number 2301 * @set: set multicast promiscuous enable/disable 2302 * @cmd_details: pointer to command details structure or NULL 2303 **/ 2304 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2305 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2306 { 2307 struct i40e_aq_desc desc; 2308 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2309 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2310 enum i40e_status_code status; 2311 u16 flags = 0; 2312 2313 i40e_fill_default_direct_cmd_desc(&desc, 2314 i40e_aqc_opc_set_vsi_promiscuous_modes); 2315 2316 if (set) 2317 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2318 2319 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2320 2321 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2322 2323 cmd->seid = CPU_TO_LE16(seid); 2324 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2325 2326 return status; 2327 } 2328 2329 /** 2330 * i40e_aq_set_vsi_mc_promisc_on_vlan 2331 * @hw: pointer to the hw struct 2332 * @seid: vsi number 2333 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2334 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2335 * @cmd_details: pointer to command details structure or NULL 2336 **/ 2337 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2338 u16 seid, bool enable, u16 vid, 2339 struct i40e_asq_cmd_details *cmd_details) 2340 { 2341 struct i40e_aq_desc desc; 2342 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2343 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2344 enum i40e_status_code status; 2345 u16 flags = 0; 2346 2347 i40e_fill_default_direct_cmd_desc(&desc, 2348 i40e_aqc_opc_set_vsi_promiscuous_modes); 2349 2350 if (enable) 2351 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2352 2353 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2354 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2355 cmd->seid = CPU_TO_LE16(seid); 2356 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2357 2358 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2359 2360 return status; 2361 } 2362 2363 /** 2364 * i40e_aq_set_vsi_uc_promisc_on_vlan 2365 * @hw: pointer to the hw struct 2366 * @seid: vsi number 2367 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2368 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2369 * @cmd_details: pointer to command details structure or NULL 2370 **/ 2371 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2372 u16 seid, bool enable, u16 vid, 2373 struct i40e_asq_cmd_details *cmd_details) 2374 { 2375 struct i40e_aq_desc desc; 2376 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2377 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2378 enum i40e_status_code status; 2379 u16 flags = 0; 2380 2381 i40e_fill_default_direct_cmd_desc(&desc, 2382 i40e_aqc_opc_set_vsi_promiscuous_modes); 2383 2384 if (enable) 2385 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2386 2387 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2388 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2389 cmd->seid = CPU_TO_LE16(seid); 2390 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2391 2392 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2393 2394 return status; 2395 } 2396 2397 /** 2398 * i40e_aq_set_vsi_bc_promisc_on_vlan 2399 * @hw: pointer to the hw struct 2400 * @seid: vsi number 2401 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2402 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2403 * @cmd_details: pointer to command details structure or NULL 2404 **/ 2405 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2406 u16 seid, bool enable, u16 vid, 2407 struct i40e_asq_cmd_details *cmd_details) 2408 { 2409 struct i40e_aq_desc desc; 2410 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2411 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2412 enum i40e_status_code status; 2413 u16 flags = 0; 2414 2415 i40e_fill_default_direct_cmd_desc(&desc, 2416 i40e_aqc_opc_set_vsi_promiscuous_modes); 2417 2418 if (enable) 2419 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2420 2421 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2422 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2423 cmd->seid = CPU_TO_LE16(seid); 2424 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2425 2426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2427 2428 return status; 2429 } 2430 2431 /** 2432 * i40e_aq_set_vsi_broadcast 2433 * @hw: pointer to the hw struct 2434 * @seid: vsi number 2435 * @set_filter: TRUE to set filter, FALSE to clear filter 2436 * @cmd_details: pointer to command details structure or NULL 2437 * 2438 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2439 **/ 2440 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2441 u16 seid, bool set_filter, 2442 struct i40e_asq_cmd_details *cmd_details) 2443 { 2444 struct i40e_aq_desc desc; 2445 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2446 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2447 enum i40e_status_code status; 2448 2449 i40e_fill_default_direct_cmd_desc(&desc, 2450 i40e_aqc_opc_set_vsi_promiscuous_modes); 2451 2452 if (set_filter) 2453 cmd->promiscuous_flags 2454 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2455 else 2456 cmd->promiscuous_flags 2457 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2458 2459 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2460 cmd->seid = CPU_TO_LE16(seid); 2461 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2462 2463 return status; 2464 } 2465 2466 /** 2467 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2468 * @hw: pointer to the hw struct 2469 * @seid: vsi number 2470 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2471 * @cmd_details: pointer to command details structure or NULL 2472 **/ 2473 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2474 u16 seid, bool enable, 2475 struct i40e_asq_cmd_details *cmd_details) 2476 { 2477 struct i40e_aq_desc desc; 2478 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2479 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2480 enum i40e_status_code status; 2481 u16 flags = 0; 2482 2483 i40e_fill_default_direct_cmd_desc(&desc, 2484 i40e_aqc_opc_set_vsi_promiscuous_modes); 2485 if (enable) 2486 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2487 2488 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2489 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2490 cmd->seid = CPU_TO_LE16(seid); 2491 2492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2493 2494 return status; 2495 } 2496 2497 /** 2498 * i40e_get_vsi_params - get VSI configuration info 2499 * @hw: pointer to the hw struct 2500 * @vsi_ctx: pointer to a vsi context struct 2501 * @cmd_details: pointer to command details structure or NULL 2502 **/ 2503 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2504 struct i40e_vsi_context *vsi_ctx, 2505 struct i40e_asq_cmd_details *cmd_details) 2506 { 2507 struct i40e_aq_desc desc; 2508 struct i40e_aqc_add_get_update_vsi *cmd = 2509 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2510 struct i40e_aqc_add_get_update_vsi_completion *resp = 2511 (struct i40e_aqc_add_get_update_vsi_completion *) 2512 &desc.params.raw; 2513 enum i40e_status_code status; 2514 2515 i40e_fill_default_direct_cmd_desc(&desc, 2516 i40e_aqc_opc_get_vsi_parameters); 2517 2518 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2519 2520 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2521 2522 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2523 sizeof(vsi_ctx->info), NULL); 2524 2525 if (status != I40E_SUCCESS) 2526 goto aq_get_vsi_params_exit; 2527 2528 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2529 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2530 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2531 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2532 2533 aq_get_vsi_params_exit: 2534 return status; 2535 } 2536 2537 /** 2538 * i40e_aq_update_vsi_params 2539 * @hw: pointer to the hw struct 2540 * @vsi_ctx: pointer to a vsi context struct 2541 * @cmd_details: pointer to command details structure or NULL 2542 * 2543 * Update a VSI context. 2544 **/ 2545 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2546 struct i40e_vsi_context *vsi_ctx, 2547 struct i40e_asq_cmd_details *cmd_details) 2548 { 2549 struct i40e_aq_desc desc; 2550 struct i40e_aqc_add_get_update_vsi *cmd = 2551 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2552 struct i40e_aqc_add_get_update_vsi_completion *resp = 2553 (struct i40e_aqc_add_get_update_vsi_completion *) 2554 &desc.params.raw; 2555 enum i40e_status_code status; 2556 2557 i40e_fill_default_direct_cmd_desc(&desc, 2558 i40e_aqc_opc_update_vsi_parameters); 2559 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2560 2561 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2562 2563 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2564 sizeof(vsi_ctx->info), cmd_details); 2565 2566 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2567 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2568 2569 return status; 2570 } 2571 2572 /** 2573 * i40e_aq_get_switch_config 2574 * @hw: pointer to the hardware structure 2575 * @buf: pointer to the result buffer 2576 * @buf_size: length of input buffer 2577 * @start_seid: seid to start for the report, 0 == beginning 2578 * @cmd_details: pointer to command details structure or NULL 2579 * 2580 * Fill the buf with switch configuration returned from AdminQ command 2581 **/ 2582 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2583 struct i40e_aqc_get_switch_config_resp *buf, 2584 u16 buf_size, u16 *start_seid, 2585 struct i40e_asq_cmd_details *cmd_details) 2586 { 2587 struct i40e_aq_desc desc; 2588 struct i40e_aqc_switch_seid *scfg = 2589 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2590 enum i40e_status_code status; 2591 2592 i40e_fill_default_direct_cmd_desc(&desc, 2593 i40e_aqc_opc_get_switch_config); 2594 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2595 if (buf_size > I40E_AQ_LARGE_BUF) 2596 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2597 scfg->seid = CPU_TO_LE16(*start_seid); 2598 2599 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2600 *start_seid = LE16_TO_CPU(scfg->seid); 2601 2602 return status; 2603 } 2604 2605 /** 2606 * i40e_aq_set_switch_config 2607 * @hw: pointer to the hardware structure 2608 * @flags: bit flag values to set 2609 * @mode: cloud filter mode 2610 * @valid_flags: which bit flags to set 2611 * @cmd_details: pointer to command details structure or NULL 2612 * 2613 * Set switch configuration bits 2614 **/ 2615 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2616 u16 flags, u16 valid_flags, u8 mode, 2617 struct i40e_asq_cmd_details *cmd_details) 2618 { 2619 struct i40e_aq_desc desc; 2620 struct i40e_aqc_set_switch_config *scfg = 2621 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2622 enum i40e_status_code status; 2623 2624 i40e_fill_default_direct_cmd_desc(&desc, 2625 i40e_aqc_opc_set_switch_config); 2626 scfg->flags = CPU_TO_LE16(flags); 2627 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2628 scfg->mode = mode; 2629 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2630 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag); 2631 scfg->first_tag = CPU_TO_LE16(hw->first_tag); 2632 scfg->second_tag = CPU_TO_LE16(hw->second_tag); 2633 } 2634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2635 2636 return status; 2637 } 2638 2639 /** 2640 * i40e_aq_get_firmware_version 2641 * @hw: pointer to the hw struct 2642 * @fw_major_version: firmware major version 2643 * @fw_minor_version: firmware minor version 2644 * @fw_build: firmware build number 2645 * @api_major_version: major queue version 2646 * @api_minor_version: minor queue version 2647 * @cmd_details: pointer to command details structure or NULL 2648 * 2649 * Get the firmware version from the admin queue commands 2650 **/ 2651 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2652 u16 *fw_major_version, u16 *fw_minor_version, 2653 u32 *fw_build, 2654 u16 *api_major_version, u16 *api_minor_version, 2655 struct i40e_asq_cmd_details *cmd_details) 2656 { 2657 struct i40e_aq_desc desc; 2658 struct i40e_aqc_get_version *resp = 2659 (struct i40e_aqc_get_version *)&desc.params.raw; 2660 enum i40e_status_code status; 2661 2662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2663 2664 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2665 2666 if (status == I40E_SUCCESS) { 2667 if (fw_major_version != NULL) 2668 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2669 if (fw_minor_version != NULL) 2670 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2671 if (fw_build != NULL) 2672 *fw_build = LE32_TO_CPU(resp->fw_build); 2673 if (api_major_version != NULL) 2674 *api_major_version = LE16_TO_CPU(resp->api_major); 2675 if (api_minor_version != NULL) 2676 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2677 2678 /* A workaround to fix the API version in SW */ 2679 if (api_major_version && api_minor_version && 2680 fw_major_version && fw_minor_version && 2681 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2682 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2683 (*fw_major_version > 4))) 2684 *api_minor_version = 2; 2685 } 2686 2687 return status; 2688 } 2689 2690 /** 2691 * i40e_aq_send_driver_version 2692 * @hw: pointer to the hw struct 2693 * @dv: driver's major, minor version 2694 * @cmd_details: pointer to command details structure or NULL 2695 * 2696 * Send the driver version to the firmware 2697 **/ 2698 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2699 struct i40e_driver_version *dv, 2700 struct i40e_asq_cmd_details *cmd_details) 2701 { 2702 struct i40e_aq_desc desc; 2703 struct i40e_aqc_driver_version *cmd = 2704 (struct i40e_aqc_driver_version *)&desc.params.raw; 2705 enum i40e_status_code status; 2706 u16 len; 2707 2708 if (dv == NULL) 2709 return I40E_ERR_PARAM; 2710 2711 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2712 2713 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2714 cmd->driver_major_ver = dv->major_version; 2715 cmd->driver_minor_ver = dv->minor_version; 2716 cmd->driver_build_ver = dv->build_version; 2717 cmd->driver_subbuild_ver = dv->subbuild_version; 2718 2719 len = 0; 2720 while (len < sizeof(dv->driver_string) && 2721 (dv->driver_string[len] < 0x80) && 2722 dv->driver_string[len]) 2723 len++; 2724 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2725 len, cmd_details); 2726 2727 return status; 2728 } 2729 2730 /** 2731 * i40e_get_link_status - get status of the HW network link 2732 * @hw: pointer to the hw struct 2733 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2734 * 2735 * Variable link_up TRUE if link is up, FALSE if link is down. 2736 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2737 * 2738 * Side effect: LinkStatusEvent reporting becomes enabled 2739 **/ 2740 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2741 { 2742 enum i40e_status_code status = I40E_SUCCESS; 2743 2744 if (hw->phy.get_link_info) { 2745 status = i40e_update_link_info(hw); 2746 2747 if (status != I40E_SUCCESS) 2748 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2749 status); 2750 } 2751 2752 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2753 2754 return status; 2755 } 2756 2757 /** 2758 * i40e_updatelink_status - update status of the HW network link 2759 * @hw: pointer to the hw struct 2760 **/ 2761 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2762 { 2763 struct i40e_aq_get_phy_abilities_resp abilities; 2764 enum i40e_status_code status = I40E_SUCCESS; 2765 2766 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2767 if (status) 2768 return status; 2769 2770 /* extra checking needed to ensure link info to user is timely */ 2771 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2772 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2773 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2774 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 2775 &abilities, NULL); 2776 if (status) 2777 return status; 2778 2779 hw->phy.link_info.req_fec_info = 2780 abilities.fec_cfg_curr_mod_ext_info & 2781 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2782 2783 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2784 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2785 } 2786 return status; 2787 } 2788 2789 2790 /** 2791 * i40e_get_link_speed 2792 * @hw: pointer to the hw struct 2793 * 2794 * Returns the link speed of the adapter. 2795 **/ 2796 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2797 { 2798 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2799 enum i40e_status_code status = I40E_SUCCESS; 2800 2801 if (hw->phy.get_link_info) { 2802 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2803 2804 if (status != I40E_SUCCESS) 2805 goto i40e_link_speed_exit; 2806 } 2807 2808 speed = hw->phy.link_info.link_speed; 2809 2810 i40e_link_speed_exit: 2811 return speed; 2812 } 2813 2814 /** 2815 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2816 * @hw: pointer to the hw struct 2817 * @uplink_seid: the MAC or other gizmo SEID 2818 * @downlink_seid: the VSI SEID 2819 * @enabled_tc: bitmap of TCs to be enabled 2820 * @default_port: TRUE for default port VSI, FALSE for control port 2821 * @veb_seid: pointer to where to put the resulting VEB SEID 2822 * @enable_stats: TRUE to turn on VEB stats 2823 * @cmd_details: pointer to command details structure or NULL 2824 * 2825 * This asks the FW to add a VEB between the uplink and downlink 2826 * elements. If the uplink SEID is 0, this will be a floating VEB. 2827 **/ 2828 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2829 u16 downlink_seid, u8 enabled_tc, 2830 bool default_port, u16 *veb_seid, 2831 bool enable_stats, 2832 struct i40e_asq_cmd_details *cmd_details) 2833 { 2834 struct i40e_aq_desc desc; 2835 struct i40e_aqc_add_veb *cmd = 2836 (struct i40e_aqc_add_veb *)&desc.params.raw; 2837 struct i40e_aqc_add_veb_completion *resp = 2838 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2839 enum i40e_status_code status; 2840 u16 veb_flags = 0; 2841 2842 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2843 if (!!uplink_seid != !!downlink_seid) 2844 return I40E_ERR_PARAM; 2845 2846 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2847 2848 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2849 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2850 cmd->enable_tcs = enabled_tc; 2851 if (!uplink_seid) 2852 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2853 if (default_port) 2854 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2855 else 2856 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2857 2858 /* reverse logic here: set the bitflag to disable the stats */ 2859 if (!enable_stats) 2860 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2861 2862 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2863 2864 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2865 2866 if (!status && veb_seid) 2867 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2868 2869 return status; 2870 } 2871 2872 /** 2873 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2874 * @hw: pointer to the hw struct 2875 * @veb_seid: the SEID of the VEB to query 2876 * @switch_id: the uplink switch id 2877 * @floating: set to TRUE if the VEB is floating 2878 * @statistic_index: index of the stats counter block for this VEB 2879 * @vebs_used: number of VEB's used by function 2880 * @vebs_free: total VEB's not reserved by any function 2881 * @cmd_details: pointer to command details structure or NULL 2882 * 2883 * This retrieves the parameters for a particular VEB, specified by 2884 * uplink_seid, and returns them to the caller. 2885 **/ 2886 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2887 u16 veb_seid, u16 *switch_id, 2888 bool *floating, u16 *statistic_index, 2889 u16 *vebs_used, u16 *vebs_free, 2890 struct i40e_asq_cmd_details *cmd_details) 2891 { 2892 struct i40e_aq_desc desc; 2893 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2894 (struct i40e_aqc_get_veb_parameters_completion *) 2895 &desc.params.raw; 2896 enum i40e_status_code status; 2897 2898 if (veb_seid == 0) 2899 return I40E_ERR_PARAM; 2900 2901 i40e_fill_default_direct_cmd_desc(&desc, 2902 i40e_aqc_opc_get_veb_parameters); 2903 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2904 2905 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2906 if (status) 2907 goto get_veb_exit; 2908 2909 if (switch_id) 2910 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2911 if (statistic_index) 2912 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2913 if (vebs_used) 2914 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2915 if (vebs_free) 2916 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2917 if (floating) { 2918 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2919 2920 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2921 *floating = TRUE; 2922 else 2923 *floating = FALSE; 2924 } 2925 2926 get_veb_exit: 2927 return status; 2928 } 2929 2930 /** 2931 * i40e_aq_add_macvlan 2932 * @hw: pointer to the hw struct 2933 * @seid: VSI for the mac address 2934 * @mv_list: list of macvlans to be added 2935 * @count: length of the list 2936 * @cmd_details: pointer to command details structure or NULL 2937 * 2938 * Add MAC/VLAN addresses to the HW filtering 2939 **/ 2940 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2941 struct i40e_aqc_add_macvlan_element_data *mv_list, 2942 u16 count, struct i40e_asq_cmd_details *cmd_details) 2943 { 2944 struct i40e_aq_desc desc; 2945 struct i40e_aqc_macvlan *cmd = 2946 (struct i40e_aqc_macvlan *)&desc.params.raw; 2947 enum i40e_status_code status; 2948 u16 buf_size; 2949 int i; 2950 2951 if (count == 0 || !mv_list || !hw) 2952 return I40E_ERR_PARAM; 2953 2954 buf_size = count * sizeof(*mv_list); 2955 2956 /* prep the rest of the request */ 2957 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2958 cmd->num_addresses = CPU_TO_LE16(count); 2959 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2960 cmd->seid[1] = 0; 2961 cmd->seid[2] = 0; 2962 2963 for (i = 0; i < count; i++) 2964 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 2965 mv_list[i].flags |= 2966 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2967 2968 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2969 if (buf_size > I40E_AQ_LARGE_BUF) 2970 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2971 2972 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2973 cmd_details); 2974 2975 return status; 2976 } 2977 2978 /** 2979 * i40e_aq_remove_macvlan 2980 * @hw: pointer to the hw struct 2981 * @seid: VSI for the mac address 2982 * @mv_list: list of macvlans to be removed 2983 * @count: length of the list 2984 * @cmd_details: pointer to command details structure or NULL 2985 * 2986 * Remove MAC/VLAN addresses from the HW filtering 2987 **/ 2988 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2989 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2990 u16 count, struct i40e_asq_cmd_details *cmd_details) 2991 { 2992 struct i40e_aq_desc desc; 2993 struct i40e_aqc_macvlan *cmd = 2994 (struct i40e_aqc_macvlan *)&desc.params.raw; 2995 enum i40e_status_code status; 2996 u16 buf_size; 2997 2998 if (count == 0 || !mv_list || !hw) 2999 return I40E_ERR_PARAM; 3000 3001 buf_size = count * sizeof(*mv_list); 3002 3003 /* prep the rest of the request */ 3004 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 3005 cmd->num_addresses = CPU_TO_LE16(count); 3006 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3007 cmd->seid[1] = 0; 3008 cmd->seid[2] = 0; 3009 3010 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3011 if (buf_size > I40E_AQ_LARGE_BUF) 3012 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3013 3014 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3015 cmd_details); 3016 3017 return status; 3018 } 3019 3020 /** 3021 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 3022 * @hw: pointer to the hw struct 3023 * @opcode: AQ opcode for add or delete mirror rule 3024 * @sw_seid: Switch SEID (to which rule refers) 3025 * @rule_type: Rule Type (ingress/egress/VLAN) 3026 * @id: Destination VSI SEID or Rule ID 3027 * @count: length of the list 3028 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3029 * @cmd_details: pointer to command details structure or NULL 3030 * @rule_id: Rule ID returned from FW 3031 * @rules_used: Number of rules used in internal switch 3032 * @rules_free: Number of rules free in internal switch 3033 * 3034 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 3035 * VEBs/VEPA elements only 3036 **/ 3037 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 3038 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 3039 u16 count, __le16 *mr_list, 3040 struct i40e_asq_cmd_details *cmd_details, 3041 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3042 { 3043 struct i40e_aq_desc desc; 3044 struct i40e_aqc_add_delete_mirror_rule *cmd = 3045 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 3046 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 3047 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 3048 enum i40e_status_code status; 3049 u16 buf_size; 3050 3051 buf_size = count * sizeof(*mr_list); 3052 3053 /* prep the rest of the request */ 3054 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3055 cmd->seid = CPU_TO_LE16(sw_seid); 3056 cmd->rule_type = CPU_TO_LE16(rule_type & 3057 I40E_AQC_MIRROR_RULE_TYPE_MASK); 3058 cmd->num_entries = CPU_TO_LE16(count); 3059 /* Dest VSI for add, rule_id for delete */ 3060 cmd->destination = CPU_TO_LE16(id); 3061 if (mr_list) { 3062 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3063 I40E_AQ_FLAG_RD)); 3064 if (buf_size > I40E_AQ_LARGE_BUF) 3065 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3066 } 3067 3068 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3069 cmd_details); 3070 if (status == I40E_SUCCESS || 3071 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3072 if (rule_id) 3073 *rule_id = LE16_TO_CPU(resp->rule_id); 3074 if (rules_used) 3075 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3076 if (rules_free) 3077 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3078 } 3079 return status; 3080 } 3081 3082 /** 3083 * i40e_aq_add_mirrorrule - add a mirror rule 3084 * @hw: pointer to the hw struct 3085 * @sw_seid: Switch SEID (to which rule refers) 3086 * @rule_type: Rule Type (ingress/egress/VLAN) 3087 * @dest_vsi: SEID of VSI to which packets will be mirrored 3088 * @count: length of the list 3089 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3090 * @cmd_details: pointer to command details structure or NULL 3091 * @rule_id: Rule ID returned from FW 3092 * @rules_used: Number of rules used in internal switch 3093 * @rules_free: Number of rules free in internal switch 3094 * 3095 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3096 **/ 3097 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3098 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3099 struct i40e_asq_cmd_details *cmd_details, 3100 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3101 { 3102 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3103 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3104 if (count == 0 || !mr_list) 3105 return I40E_ERR_PARAM; 3106 } 3107 3108 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3109 rule_type, dest_vsi, count, mr_list, 3110 cmd_details, rule_id, rules_used, rules_free); 3111 } 3112 3113 /** 3114 * i40e_aq_delete_mirrorrule - delete a mirror rule 3115 * @hw: pointer to the hw struct 3116 * @sw_seid: Switch SEID (to which rule refers) 3117 * @rule_type: Rule Type (ingress/egress/VLAN) 3118 * @count: length of the list 3119 * @rule_id: Rule ID that is returned in the receive desc as part of 3120 * add_mirrorrule. 3121 * @mr_list: list of mirrored VLAN IDs to be removed 3122 * @cmd_details: pointer to command details structure or NULL 3123 * @rules_used: Number of rules used in internal switch 3124 * @rules_free: Number of rules free in internal switch 3125 * 3126 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3127 **/ 3128 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3129 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3130 struct i40e_asq_cmd_details *cmd_details, 3131 u16 *rules_used, u16 *rules_free) 3132 { 3133 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3134 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3135 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3136 * mirroring. For other rule_type, count and rule_type should 3137 * not matter. 3138 */ 3139 if (count == 0 || !mr_list) 3140 return I40E_ERR_PARAM; 3141 } 3142 3143 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3144 rule_type, rule_id, count, mr_list, 3145 cmd_details, NULL, rules_used, rules_free); 3146 } 3147 3148 /** 3149 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3150 * @hw: pointer to the hw struct 3151 * @seid: VSI for the vlan filters 3152 * @v_list: list of vlan filters to be added 3153 * @count: length of the list 3154 * @cmd_details: pointer to command details structure or NULL 3155 **/ 3156 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3157 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3158 u8 count, struct i40e_asq_cmd_details *cmd_details) 3159 { 3160 struct i40e_aq_desc desc; 3161 struct i40e_aqc_macvlan *cmd = 3162 (struct i40e_aqc_macvlan *)&desc.params.raw; 3163 enum i40e_status_code status; 3164 u16 buf_size; 3165 3166 if (count == 0 || !v_list || !hw) 3167 return I40E_ERR_PARAM; 3168 3169 buf_size = count * sizeof(*v_list); 3170 3171 /* prep the rest of the request */ 3172 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3173 cmd->num_addresses = CPU_TO_LE16(count); 3174 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3175 cmd->seid[1] = 0; 3176 cmd->seid[2] = 0; 3177 3178 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3179 if (buf_size > I40E_AQ_LARGE_BUF) 3180 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3181 3182 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3183 cmd_details); 3184 3185 return status; 3186 } 3187 3188 /** 3189 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3190 * @hw: pointer to the hw struct 3191 * @seid: VSI for the vlan filters 3192 * @v_list: list of macvlans to be removed 3193 * @count: length of the list 3194 * @cmd_details: pointer to command details structure or NULL 3195 **/ 3196 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3197 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3198 u8 count, struct i40e_asq_cmd_details *cmd_details) 3199 { 3200 struct i40e_aq_desc desc; 3201 struct i40e_aqc_macvlan *cmd = 3202 (struct i40e_aqc_macvlan *)&desc.params.raw; 3203 enum i40e_status_code status; 3204 u16 buf_size; 3205 3206 if (count == 0 || !v_list || !hw) 3207 return I40E_ERR_PARAM; 3208 3209 buf_size = count * sizeof(*v_list); 3210 3211 /* prep the rest of the request */ 3212 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3213 cmd->num_addresses = CPU_TO_LE16(count); 3214 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3215 cmd->seid[1] = 0; 3216 cmd->seid[2] = 0; 3217 3218 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3219 if (buf_size > I40E_AQ_LARGE_BUF) 3220 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3221 3222 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3223 cmd_details); 3224 3225 return status; 3226 } 3227 3228 /** 3229 * i40e_aq_send_msg_to_vf 3230 * @hw: pointer to the hardware structure 3231 * @vfid: vf id to send msg 3232 * @v_opcode: opcodes for VF-PF communication 3233 * @v_retval: return error code 3234 * @msg: pointer to the msg buffer 3235 * @msglen: msg length 3236 * @cmd_details: pointer to command details 3237 * 3238 * send msg to vf 3239 **/ 3240 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3241 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3242 struct i40e_asq_cmd_details *cmd_details) 3243 { 3244 struct i40e_aq_desc desc; 3245 struct i40e_aqc_pf_vf_message *cmd = 3246 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3247 enum i40e_status_code status; 3248 3249 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3250 cmd->id = CPU_TO_LE32(vfid); 3251 desc.cookie_high = CPU_TO_LE32(v_opcode); 3252 desc.cookie_low = CPU_TO_LE32(v_retval); 3253 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3254 if (msglen) { 3255 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3256 I40E_AQ_FLAG_RD)); 3257 if (msglen > I40E_AQ_LARGE_BUF) 3258 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3259 desc.datalen = CPU_TO_LE16(msglen); 3260 } 3261 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3262 3263 return status; 3264 } 3265 3266 /** 3267 * i40e_aq_debug_read_register 3268 * @hw: pointer to the hw struct 3269 * @reg_addr: register address 3270 * @reg_val: register value 3271 * @cmd_details: pointer to command details structure or NULL 3272 * 3273 * Read the register using the admin queue commands 3274 **/ 3275 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3276 u32 reg_addr, u64 *reg_val, 3277 struct i40e_asq_cmd_details *cmd_details) 3278 { 3279 struct i40e_aq_desc desc; 3280 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3281 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3282 enum i40e_status_code status; 3283 3284 if (reg_val == NULL) 3285 return I40E_ERR_PARAM; 3286 3287 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3288 3289 cmd_resp->address = CPU_TO_LE32(reg_addr); 3290 3291 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3292 3293 if (status == I40E_SUCCESS) { 3294 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3295 (u64)LE32_TO_CPU(cmd_resp->value_low); 3296 } 3297 3298 return status; 3299 } 3300 3301 /** 3302 * i40e_aq_debug_write_register 3303 * @hw: pointer to the hw struct 3304 * @reg_addr: register address 3305 * @reg_val: register value 3306 * @cmd_details: pointer to command details structure or NULL 3307 * 3308 * Write to a register using the admin queue commands 3309 **/ 3310 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3311 u32 reg_addr, u64 reg_val, 3312 struct i40e_asq_cmd_details *cmd_details) 3313 { 3314 struct i40e_aq_desc desc; 3315 struct i40e_aqc_debug_reg_read_write *cmd = 3316 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3317 enum i40e_status_code status; 3318 3319 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3320 3321 cmd->address = CPU_TO_LE32(reg_addr); 3322 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3323 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3324 3325 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3326 3327 return status; 3328 } 3329 3330 /** 3331 * i40e_aq_request_resource 3332 * @hw: pointer to the hw struct 3333 * @resource: resource id 3334 * @access: access type 3335 * @sdp_number: resource number 3336 * @timeout: the maximum time in ms that the driver may hold the resource 3337 * @cmd_details: pointer to command details structure or NULL 3338 * 3339 * requests common resource using the admin queue commands 3340 **/ 3341 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3342 enum i40e_aq_resources_ids resource, 3343 enum i40e_aq_resource_access_type access, 3344 u8 sdp_number, u64 *timeout, 3345 struct i40e_asq_cmd_details *cmd_details) 3346 { 3347 struct i40e_aq_desc desc; 3348 struct i40e_aqc_request_resource *cmd_resp = 3349 (struct i40e_aqc_request_resource *)&desc.params.raw; 3350 enum i40e_status_code status; 3351 3352 DEBUGFUNC("i40e_aq_request_resource"); 3353 3354 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3355 3356 cmd_resp->resource_id = CPU_TO_LE16(resource); 3357 cmd_resp->access_type = CPU_TO_LE16(access); 3358 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3359 3360 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3361 /* The completion specifies the maximum time in ms that the driver 3362 * may hold the resource in the Timeout field. 3363 * If the resource is held by someone else, the command completes with 3364 * busy return value and the timeout field indicates the maximum time 3365 * the current owner of the resource has to free it. 3366 */ 3367 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3368 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3369 3370 return status; 3371 } 3372 3373 /** 3374 * i40e_aq_release_resource 3375 * @hw: pointer to the hw struct 3376 * @resource: resource id 3377 * @sdp_number: resource number 3378 * @cmd_details: pointer to command details structure or NULL 3379 * 3380 * release common resource using the admin queue commands 3381 **/ 3382 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3383 enum i40e_aq_resources_ids resource, 3384 u8 sdp_number, 3385 struct i40e_asq_cmd_details *cmd_details) 3386 { 3387 struct i40e_aq_desc desc; 3388 struct i40e_aqc_request_resource *cmd = 3389 (struct i40e_aqc_request_resource *)&desc.params.raw; 3390 enum i40e_status_code status; 3391 3392 DEBUGFUNC("i40e_aq_release_resource"); 3393 3394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3395 3396 cmd->resource_id = CPU_TO_LE16(resource); 3397 cmd->resource_number = CPU_TO_LE32(sdp_number); 3398 3399 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3400 3401 return status; 3402 } 3403 3404 /** 3405 * i40e_aq_read_nvm 3406 * @hw: pointer to the hw struct 3407 * @module_pointer: module pointer location in words from the NVM beginning 3408 * @offset: byte offset from the module beginning 3409 * @length: length of the section to be read (in bytes from the offset) 3410 * @data: command buffer (size [bytes] = length) 3411 * @last_command: tells if this is the last command in a series 3412 * @cmd_details: pointer to command details structure or NULL 3413 * 3414 * Read the NVM using the admin queue commands 3415 **/ 3416 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3417 u32 offset, u16 length, void *data, 3418 bool last_command, 3419 struct i40e_asq_cmd_details *cmd_details) 3420 { 3421 struct i40e_aq_desc desc; 3422 struct i40e_aqc_nvm_update *cmd = 3423 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3424 enum i40e_status_code status; 3425 3426 DEBUGFUNC("i40e_aq_read_nvm"); 3427 3428 /* In offset the highest byte must be zeroed. */ 3429 if (offset & 0xFF000000) { 3430 status = I40E_ERR_PARAM; 3431 goto i40e_aq_read_nvm_exit; 3432 } 3433 3434 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3435 3436 /* If this is the last command in a series, set the proper flag. */ 3437 if (last_command) 3438 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3439 cmd->module_pointer = module_pointer; 3440 cmd->offset = CPU_TO_LE32(offset); 3441 cmd->length = CPU_TO_LE16(length); 3442 3443 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3444 if (length > I40E_AQ_LARGE_BUF) 3445 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3446 3447 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3448 3449 i40e_aq_read_nvm_exit: 3450 return status; 3451 } 3452 3453 /** 3454 * i40e_aq_read_nvm_config - read an nvm config block 3455 * @hw: pointer to the hw struct 3456 * @cmd_flags: NVM access admin command bits 3457 * @field_id: field or feature id 3458 * @data: buffer for result 3459 * @buf_size: buffer size 3460 * @element_count: pointer to count of elements read by FW 3461 * @cmd_details: pointer to command details structure or NULL 3462 **/ 3463 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3464 u8 cmd_flags, u32 field_id, void *data, 3465 u16 buf_size, u16 *element_count, 3466 struct i40e_asq_cmd_details *cmd_details) 3467 { 3468 struct i40e_aq_desc desc; 3469 struct i40e_aqc_nvm_config_read *cmd = 3470 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3471 enum i40e_status_code status; 3472 3473 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3474 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3475 if (buf_size > I40E_AQ_LARGE_BUF) 3476 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3477 3478 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3479 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3480 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3481 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3482 else 3483 cmd->element_id_msw = 0; 3484 3485 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3486 3487 if (!status && element_count) 3488 *element_count = LE16_TO_CPU(cmd->element_count); 3489 3490 return status; 3491 } 3492 3493 /** 3494 * i40e_aq_write_nvm_config - write an nvm config block 3495 * @hw: pointer to the hw struct 3496 * @cmd_flags: NVM access admin command bits 3497 * @data: buffer for result 3498 * @buf_size: buffer size 3499 * @element_count: count of elements to be written 3500 * @cmd_details: pointer to command details structure or NULL 3501 **/ 3502 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3503 u8 cmd_flags, void *data, u16 buf_size, 3504 u16 element_count, 3505 struct i40e_asq_cmd_details *cmd_details) 3506 { 3507 struct i40e_aq_desc desc; 3508 struct i40e_aqc_nvm_config_write *cmd = 3509 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3510 enum i40e_status_code status; 3511 3512 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3513 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3514 if (buf_size > I40E_AQ_LARGE_BUF) 3515 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3516 3517 cmd->element_count = CPU_TO_LE16(element_count); 3518 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3519 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3520 3521 return status; 3522 } 3523 3524 /** 3525 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3526 * @hw: pointer to the hw struct 3527 * @buff: buffer for result 3528 * @buff_size: buffer size 3529 * @cmd_details: pointer to command details structure or NULL 3530 **/ 3531 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3532 void *buff, u16 buff_size, 3533 struct i40e_asq_cmd_details *cmd_details) 3534 { 3535 struct i40e_aq_desc desc; 3536 enum i40e_status_code status; 3537 3538 3539 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3540 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3541 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3542 status = I40E_ERR_NOT_IMPLEMENTED; 3543 3544 return status; 3545 } 3546 3547 /** 3548 * i40e_aq_erase_nvm 3549 * @hw: pointer to the hw struct 3550 * @module_pointer: module pointer location in words from the NVM beginning 3551 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3552 * @length: length of the section to be erased (expressed in 4 KB) 3553 * @last_command: tells if this is the last command in a series 3554 * @cmd_details: pointer to command details structure or NULL 3555 * 3556 * Erase the NVM sector using the admin queue commands 3557 **/ 3558 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3559 u32 offset, u16 length, bool last_command, 3560 struct i40e_asq_cmd_details *cmd_details) 3561 { 3562 struct i40e_aq_desc desc; 3563 struct i40e_aqc_nvm_update *cmd = 3564 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3565 enum i40e_status_code status; 3566 3567 DEBUGFUNC("i40e_aq_erase_nvm"); 3568 3569 /* In offset the highest byte must be zeroed. */ 3570 if (offset & 0xFF000000) { 3571 status = I40E_ERR_PARAM; 3572 goto i40e_aq_erase_nvm_exit; 3573 } 3574 3575 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3576 3577 /* If this is the last command in a series, set the proper flag. */ 3578 if (last_command) 3579 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3580 cmd->module_pointer = module_pointer; 3581 cmd->offset = CPU_TO_LE32(offset); 3582 cmd->length = CPU_TO_LE16(length); 3583 3584 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3585 3586 i40e_aq_erase_nvm_exit: 3587 return status; 3588 } 3589 3590 /** 3591 * i40e_parse_discover_capabilities 3592 * @hw: pointer to the hw struct 3593 * @buff: pointer to a buffer containing device/function capability records 3594 * @cap_count: number of capability records in the list 3595 * @list_type_opc: type of capabilities list to parse 3596 * 3597 * Parse the device/function capabilities list. 3598 **/ 3599 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3600 u32 cap_count, 3601 enum i40e_admin_queue_opc list_type_opc) 3602 { 3603 struct i40e_aqc_list_capabilities_element_resp *cap; 3604 u32 valid_functions, num_functions; 3605 u32 number, logical_id, phys_id; 3606 struct i40e_hw_capabilities *p; 3607 enum i40e_status_code status; 3608 u16 id, ocp_cfg_word0; 3609 u8 major_rev; 3610 u32 i = 0; 3611 3612 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3613 3614 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3615 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3616 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3617 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3618 else 3619 return; 3620 3621 for (i = 0; i < cap_count; i++, cap++) { 3622 id = LE16_TO_CPU(cap->id); 3623 number = LE32_TO_CPU(cap->number); 3624 logical_id = LE32_TO_CPU(cap->logical_id); 3625 phys_id = LE32_TO_CPU(cap->phys_id); 3626 major_rev = cap->major_rev; 3627 3628 switch (id) { 3629 case I40E_AQ_CAP_ID_SWITCH_MODE: 3630 p->switch_mode = number; 3631 i40e_debug(hw, I40E_DEBUG_INIT, 3632 "HW Capability: Switch mode = %d\n", 3633 p->switch_mode); 3634 break; 3635 case I40E_AQ_CAP_ID_MNG_MODE: 3636 p->management_mode = number; 3637 if (major_rev > 1) { 3638 p->mng_protocols_over_mctp = logical_id; 3639 i40e_debug(hw, I40E_DEBUG_INIT, 3640 "HW Capability: Protocols over MCTP = %d\n", 3641 p->mng_protocols_over_mctp); 3642 } else { 3643 p->mng_protocols_over_mctp = 0; 3644 } 3645 i40e_debug(hw, I40E_DEBUG_INIT, 3646 "HW Capability: Management Mode = %d\n", 3647 p->management_mode); 3648 break; 3649 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3650 p->npar_enable = number; 3651 i40e_debug(hw, I40E_DEBUG_INIT, 3652 "HW Capability: NPAR enable = %d\n", 3653 p->npar_enable); 3654 break; 3655 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3656 p->os2bmc = number; 3657 i40e_debug(hw, I40E_DEBUG_INIT, 3658 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3659 break; 3660 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3661 p->valid_functions = number; 3662 i40e_debug(hw, I40E_DEBUG_INIT, 3663 "HW Capability: Valid Functions = %d\n", 3664 p->valid_functions); 3665 break; 3666 case I40E_AQ_CAP_ID_SRIOV: 3667 if (number == 1) 3668 p->sr_iov_1_1 = TRUE; 3669 i40e_debug(hw, I40E_DEBUG_INIT, 3670 "HW Capability: SR-IOV = %d\n", 3671 p->sr_iov_1_1); 3672 break; 3673 case I40E_AQ_CAP_ID_VF: 3674 p->num_vfs = number; 3675 p->vf_base_id = logical_id; 3676 i40e_debug(hw, I40E_DEBUG_INIT, 3677 "HW Capability: VF count = %d\n", 3678 p->num_vfs); 3679 i40e_debug(hw, I40E_DEBUG_INIT, 3680 "HW Capability: VF base_id = %d\n", 3681 p->vf_base_id); 3682 break; 3683 case I40E_AQ_CAP_ID_VMDQ: 3684 if (number == 1) 3685 p->vmdq = TRUE; 3686 i40e_debug(hw, I40E_DEBUG_INIT, 3687 "HW Capability: VMDQ = %d\n", p->vmdq); 3688 break; 3689 case I40E_AQ_CAP_ID_8021QBG: 3690 if (number == 1) 3691 p->evb_802_1_qbg = TRUE; 3692 i40e_debug(hw, I40E_DEBUG_INIT, 3693 "HW Capability: 802.1Qbg = %d\n", number); 3694 break; 3695 case I40E_AQ_CAP_ID_8021QBR: 3696 if (number == 1) 3697 p->evb_802_1_qbh = TRUE; 3698 i40e_debug(hw, I40E_DEBUG_INIT, 3699 "HW Capability: 802.1Qbh = %d\n", number); 3700 break; 3701 case I40E_AQ_CAP_ID_VSI: 3702 p->num_vsis = number; 3703 i40e_debug(hw, I40E_DEBUG_INIT, 3704 "HW Capability: VSI count = %d\n", 3705 p->num_vsis); 3706 break; 3707 case I40E_AQ_CAP_ID_DCB: 3708 if (number == 1) { 3709 p->dcb = TRUE; 3710 p->enabled_tcmap = logical_id; 3711 p->maxtc = phys_id; 3712 } 3713 i40e_debug(hw, I40E_DEBUG_INIT, 3714 "HW Capability: DCB = %d\n", p->dcb); 3715 i40e_debug(hw, I40E_DEBUG_INIT, 3716 "HW Capability: TC Mapping = %d\n", 3717 logical_id); 3718 i40e_debug(hw, I40E_DEBUG_INIT, 3719 "HW Capability: TC Max = %d\n", p->maxtc); 3720 break; 3721 case I40E_AQ_CAP_ID_FCOE: 3722 if (number == 1) 3723 p->fcoe = TRUE; 3724 i40e_debug(hw, I40E_DEBUG_INIT, 3725 "HW Capability: FCOE = %d\n", p->fcoe); 3726 break; 3727 case I40E_AQ_CAP_ID_ISCSI: 3728 if (number == 1) 3729 p->iscsi = TRUE; 3730 i40e_debug(hw, I40E_DEBUG_INIT, 3731 "HW Capability: iSCSI = %d\n", p->iscsi); 3732 break; 3733 case I40E_AQ_CAP_ID_RSS: 3734 p->rss = TRUE; 3735 p->rss_table_size = number; 3736 p->rss_table_entry_width = logical_id; 3737 i40e_debug(hw, I40E_DEBUG_INIT, 3738 "HW Capability: RSS = %d\n", p->rss); 3739 i40e_debug(hw, I40E_DEBUG_INIT, 3740 "HW Capability: RSS table size = %d\n", 3741 p->rss_table_size); 3742 i40e_debug(hw, I40E_DEBUG_INIT, 3743 "HW Capability: RSS table width = %d\n", 3744 p->rss_table_entry_width); 3745 break; 3746 case I40E_AQ_CAP_ID_RXQ: 3747 p->num_rx_qp = number; 3748 p->base_queue = phys_id; 3749 i40e_debug(hw, I40E_DEBUG_INIT, 3750 "HW Capability: Rx QP = %d\n", number); 3751 i40e_debug(hw, I40E_DEBUG_INIT, 3752 "HW Capability: base_queue = %d\n", 3753 p->base_queue); 3754 break; 3755 case I40E_AQ_CAP_ID_TXQ: 3756 p->num_tx_qp = number; 3757 p->base_queue = phys_id; 3758 i40e_debug(hw, I40E_DEBUG_INIT, 3759 "HW Capability: Tx QP = %d\n", number); 3760 i40e_debug(hw, I40E_DEBUG_INIT, 3761 "HW Capability: base_queue = %d\n", 3762 p->base_queue); 3763 break; 3764 case I40E_AQ_CAP_ID_MSIX: 3765 p->num_msix_vectors = number; 3766 i40e_debug(hw, I40E_DEBUG_INIT, 3767 "HW Capability: MSIX vector count = %d\n", 3768 p->num_msix_vectors); 3769 break; 3770 case I40E_AQ_CAP_ID_VF_MSIX: 3771 p->num_msix_vectors_vf = number; 3772 i40e_debug(hw, I40E_DEBUG_INIT, 3773 "HW Capability: MSIX VF vector count = %d\n", 3774 p->num_msix_vectors_vf); 3775 break; 3776 case I40E_AQ_CAP_ID_FLEX10: 3777 if (major_rev == 1) { 3778 if (number == 1) { 3779 p->flex10_enable = TRUE; 3780 p->flex10_capable = TRUE; 3781 } 3782 } else { 3783 /* Capability revision >= 2 */ 3784 if (number & 1) 3785 p->flex10_enable = TRUE; 3786 if (number & 2) 3787 p->flex10_capable = TRUE; 3788 } 3789 p->flex10_mode = logical_id; 3790 p->flex10_status = phys_id; 3791 i40e_debug(hw, I40E_DEBUG_INIT, 3792 "HW Capability: Flex10 mode = %d\n", 3793 p->flex10_mode); 3794 i40e_debug(hw, I40E_DEBUG_INIT, 3795 "HW Capability: Flex10 status = %d\n", 3796 p->flex10_status); 3797 break; 3798 case I40E_AQ_CAP_ID_CEM: 3799 if (number == 1) 3800 p->mgmt_cem = TRUE; 3801 i40e_debug(hw, I40E_DEBUG_INIT, 3802 "HW Capability: CEM = %d\n", p->mgmt_cem); 3803 break; 3804 case I40E_AQ_CAP_ID_IWARP: 3805 if (number == 1) 3806 p->iwarp = TRUE; 3807 i40e_debug(hw, I40E_DEBUG_INIT, 3808 "HW Capability: iWARP = %d\n", p->iwarp); 3809 break; 3810 case I40E_AQ_CAP_ID_LED: 3811 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3812 p->led[phys_id] = TRUE; 3813 i40e_debug(hw, I40E_DEBUG_INIT, 3814 "HW Capability: LED - PIN %d\n", phys_id); 3815 break; 3816 case I40E_AQ_CAP_ID_SDP: 3817 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3818 p->sdp[phys_id] = TRUE; 3819 i40e_debug(hw, I40E_DEBUG_INIT, 3820 "HW Capability: SDP - PIN %d\n", phys_id); 3821 break; 3822 case I40E_AQ_CAP_ID_MDIO: 3823 if (number == 1) { 3824 p->mdio_port_num = phys_id; 3825 p->mdio_port_mode = logical_id; 3826 } 3827 i40e_debug(hw, I40E_DEBUG_INIT, 3828 "HW Capability: MDIO port number = %d\n", 3829 p->mdio_port_num); 3830 i40e_debug(hw, I40E_DEBUG_INIT, 3831 "HW Capability: MDIO port mode = %d\n", 3832 p->mdio_port_mode); 3833 break; 3834 case I40E_AQ_CAP_ID_1588: 3835 if (number == 1) 3836 p->ieee_1588 = TRUE; 3837 i40e_debug(hw, I40E_DEBUG_INIT, 3838 "HW Capability: IEEE 1588 = %d\n", 3839 p->ieee_1588); 3840 break; 3841 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3842 p->fd = TRUE; 3843 p->fd_filters_guaranteed = number; 3844 p->fd_filters_best_effort = logical_id; 3845 i40e_debug(hw, I40E_DEBUG_INIT, 3846 "HW Capability: Flow Director = 1\n"); 3847 i40e_debug(hw, I40E_DEBUG_INIT, 3848 "HW Capability: Guaranteed FD filters = %d\n", 3849 p->fd_filters_guaranteed); 3850 break; 3851 case I40E_AQ_CAP_ID_WSR_PROT: 3852 p->wr_csr_prot = (u64)number; 3853 p->wr_csr_prot |= (u64)logical_id << 32; 3854 i40e_debug(hw, I40E_DEBUG_INIT, 3855 "HW Capability: wr_csr_prot = 0x%llX\n\n", 3856 (p->wr_csr_prot & 0xffff)); 3857 break; 3858 case I40E_AQ_CAP_ID_NVM_MGMT: 3859 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3860 p->sec_rev_disabled = TRUE; 3861 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3862 p->update_disabled = TRUE; 3863 break; 3864 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 3865 hw->num_wol_proxy_filters = (u16)number; 3866 hw->wol_proxy_vsi_seid = (u16)logical_id; 3867 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 3868 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 3869 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 3870 else 3871 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 3872 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 3873 i40e_debug(hw, I40E_DEBUG_INIT, 3874 "HW Capability: WOL proxy filters = %d\n", 3875 hw->num_wol_proxy_filters); 3876 break; 3877 default: 3878 break; 3879 } 3880 } 3881 3882 if (p->fcoe) 3883 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3884 3885 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3886 p->fcoe = FALSE; 3887 3888 valid_functions = p->valid_functions; 3889 num_functions = 0; 3890 while (valid_functions) { 3891 if (valid_functions & 1) 3892 num_functions++; 3893 valid_functions >>= 1; 3894 } 3895 3896 /* count the enabled ports (aka the "not disabled" ports) */ 3897 hw->num_ports = 0; 3898 for (i = 0; i < 4; i++) { 3899 u32 port_cfg_reg = I40E_PRTGEN_STATUS + (4 * i); 3900 u64 port_cfg = 0; 3901 3902 /* use AQ read to get the physical register offset instead 3903 * of the port relative offset 3904 */ 3905 status = i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3906 if ((status == I40E_SUCCESS) && 3907 (port_cfg & I40E_PRTGEN_STATUS_PORT_VALID_MASK)) 3908 hw->num_ports++; 3909 } 3910 3911 /* OCP cards case: if a mezz is removed the ethernet port is at 3912 * disabled state in PRTGEN_CNF register. Additional NVM read is 3913 * needed in order to check if we are dealing with OCP card. 3914 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 3915 * physical ports results in wrong partition id calculation and thus 3916 * not supporting WoL. 3917 * 3918 * Porting note: the above comment is no longer directly relevant: we 3919 * read PRTGEN_STATUS instead now, as PRTGEN_CNF was not reliable for 3920 * these parts. In addition, the claim about having 4 PFs is not 3921 * correct. For example, an X557-T2 is a dual port mezz card. Forcing 3922 * ports to four here will cause ->num_partitions to be zero. 3923 * 3924 * On the presumption that the hard-coded value is meaningful in some 3925 * cases, though, we'll take the minimal approach of ensuring that we 3926 * never have more ports than functions. 3927 */ 3928 if (hw->mac.type == I40E_MAC_X722) { 3929 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) { 3930 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 3931 2 * I40E_SR_OCP_CFG_WORD0, 3932 sizeof(ocp_cfg_word0), 3933 &ocp_cfg_word0, TRUE, NULL); 3934 #ifdef __sun__ 3935 if (status == I40E_SUCCESS && 3936 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) { 3937 hw->num_ports = 4; 3938 if (hw->num_ports > num_functions) { 3939 hw->num_ports = num_functions; 3940 DEBUGOUT1("clamped 4 OCP ports to %d\n", 3941 (int)hw->num_ports); 3942 } 3943 } 3944 #else 3945 if (status == I40E_SUCCESS && 3946 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 3947 hw->num_ports = 4; 3948 #endif 3949 i40e_release_nvm(hw); 3950 } 3951 } 3952 3953 /* partition id is 1-based, and functions are evenly spread 3954 * across the ports as partitions 3955 */ 3956 if (hw->num_ports != 0) { 3957 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3958 hw->num_partitions = num_functions / hw->num_ports; 3959 } 3960 3961 VERIFY(hw->num_partitions > 0); 3962 3963 /* additional HW specific goodies that might 3964 * someday be HW version specific 3965 */ 3966 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3967 } 3968 3969 /** 3970 * i40e_aq_discover_capabilities 3971 * @hw: pointer to the hw struct 3972 * @buff: a virtual buffer to hold the capabilities 3973 * @buff_size: Size of the virtual buffer 3974 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3975 * @list_type_opc: capabilities type to discover - pass in the command opcode 3976 * @cmd_details: pointer to command details structure or NULL 3977 * 3978 * Get the device capabilities descriptions from the firmware 3979 **/ 3980 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 3981 void *buff, u16 buff_size, u16 *data_size, 3982 enum i40e_admin_queue_opc list_type_opc, 3983 struct i40e_asq_cmd_details *cmd_details) 3984 { 3985 struct i40e_aqc_list_capabilites *cmd; 3986 struct i40e_aq_desc desc; 3987 enum i40e_status_code status = I40E_SUCCESS; 3988 3989 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3990 3991 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3992 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3993 status = I40E_ERR_PARAM; 3994 goto exit; 3995 } 3996 3997 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3998 3999 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4000 if (buff_size > I40E_AQ_LARGE_BUF) 4001 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4002 4003 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4004 *data_size = LE16_TO_CPU(desc.datalen); 4005 4006 if (status) 4007 goto exit; 4008 4009 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 4010 list_type_opc); 4011 4012 exit: 4013 return status; 4014 } 4015 4016 /** 4017 * i40e_aq_update_nvm 4018 * @hw: pointer to the hw struct 4019 * @module_pointer: module pointer location in words from the NVM beginning 4020 * @offset: byte offset from the module beginning 4021 * @length: length of the section to be written (in bytes from the offset) 4022 * @data: command buffer (size [bytes] = length) 4023 * @last_command: tells if this is the last command in a series 4024 * @preservation_flags: Preservation mode flags 4025 * @cmd_details: pointer to command details structure or NULL 4026 * 4027 * Update the NVM using the admin queue commands 4028 **/ 4029 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 4030 u32 offset, u16 length, void *data, 4031 bool last_command, u8 preservation_flags, 4032 struct i40e_asq_cmd_details *cmd_details) 4033 { 4034 struct i40e_aq_desc desc; 4035 struct i40e_aqc_nvm_update *cmd = 4036 (struct i40e_aqc_nvm_update *)&desc.params.raw; 4037 enum i40e_status_code status; 4038 4039 DEBUGFUNC("i40e_aq_update_nvm"); 4040 4041 /* In offset the highest byte must be zeroed. */ 4042 if (offset & 0xFF000000) { 4043 status = I40E_ERR_PARAM; 4044 goto i40e_aq_update_nvm_exit; 4045 } 4046 4047 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4048 4049 /* If this is the last command in a series, set the proper flag. */ 4050 if (last_command) 4051 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 4052 if (hw->mac.type == I40E_MAC_X722) { 4053 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 4054 cmd->command_flags |= 4055 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 4056 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4057 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 4058 cmd->command_flags |= 4059 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 4060 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4061 } 4062 cmd->module_pointer = module_pointer; 4063 cmd->offset = CPU_TO_LE32(offset); 4064 cmd->length = CPU_TO_LE16(length); 4065 4066 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4067 if (length > I40E_AQ_LARGE_BUF) 4068 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4069 4070 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 4071 4072 i40e_aq_update_nvm_exit: 4073 return status; 4074 } 4075 4076 /** 4077 * i40e_aq_nvm_progress 4078 * @hw: pointer to the hw struct 4079 * @progress: pointer to progress returned from AQ 4080 * @cmd_details: pointer to command details structure or NULL 4081 * 4082 * Gets progress of flash rearrangement process 4083 **/ 4084 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress, 4085 struct i40e_asq_cmd_details *cmd_details) 4086 { 4087 enum i40e_status_code status; 4088 struct i40e_aq_desc desc; 4089 4090 DEBUGFUNC("i40e_aq_nvm_progress"); 4091 4092 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress); 4093 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4094 *progress = desc.params.raw[0]; 4095 return status; 4096 } 4097 4098 /** 4099 * i40e_aq_get_lldp_mib 4100 * @hw: pointer to the hw struct 4101 * @bridge_type: type of bridge requested 4102 * @mib_type: Local, Remote or both Local and Remote MIBs 4103 * @buff: pointer to a user supplied buffer to store the MIB block 4104 * @buff_size: size of the buffer (in bytes) 4105 * @local_len : length of the returned Local LLDP MIB 4106 * @remote_len: length of the returned Remote LLDP MIB 4107 * @cmd_details: pointer to command details structure or NULL 4108 * 4109 * Requests the complete LLDP MIB (entire packet). 4110 **/ 4111 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 4112 u8 mib_type, void *buff, u16 buff_size, 4113 u16 *local_len, u16 *remote_len, 4114 struct i40e_asq_cmd_details *cmd_details) 4115 { 4116 struct i40e_aq_desc desc; 4117 struct i40e_aqc_lldp_get_mib *cmd = 4118 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4119 struct i40e_aqc_lldp_get_mib *resp = 4120 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4121 enum i40e_status_code status; 4122 4123 if (buff_size == 0 || !buff) 4124 return I40E_ERR_PARAM; 4125 4126 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 4127 /* Indirect Command */ 4128 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4129 4130 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 4131 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4132 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4133 4134 desc.datalen = CPU_TO_LE16(buff_size); 4135 4136 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4137 if (buff_size > I40E_AQ_LARGE_BUF) 4138 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4139 4140 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4141 if (!status) { 4142 if (local_len != NULL) 4143 *local_len = LE16_TO_CPU(resp->local_len); 4144 if (remote_len != NULL) 4145 *remote_len = LE16_TO_CPU(resp->remote_len); 4146 } 4147 4148 return status; 4149 } 4150 4151 /** 4152 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4153 * @hw: pointer to the hw struct 4154 * @mib_type: Local, Remote or both Local and Remote MIBs 4155 * @buff: pointer to a user supplied buffer to store the MIB block 4156 * @buff_size: size of the buffer (in bytes) 4157 * @cmd_details: pointer to command details structure or NULL 4158 * 4159 * Set the LLDP MIB. 4160 **/ 4161 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4162 u8 mib_type, void *buff, u16 buff_size, 4163 struct i40e_asq_cmd_details *cmd_details) 4164 { 4165 struct i40e_aq_desc desc; 4166 struct i40e_aqc_lldp_set_local_mib *cmd = 4167 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4168 enum i40e_status_code status; 4169 4170 if (buff_size == 0 || !buff) 4171 return I40E_ERR_PARAM; 4172 4173 i40e_fill_default_direct_cmd_desc(&desc, 4174 i40e_aqc_opc_lldp_set_local_mib); 4175 /* Indirect Command */ 4176 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4177 if (buff_size > I40E_AQ_LARGE_BUF) 4178 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4179 desc.datalen = CPU_TO_LE16(buff_size); 4180 4181 cmd->type = mib_type; 4182 cmd->length = CPU_TO_LE16(buff_size); 4183 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((uintptr_t)buff)); 4184 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)buff)); 4185 4186 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4187 return status; 4188 } 4189 4190 /** 4191 * i40e_aq_cfg_lldp_mib_change_event 4192 * @hw: pointer to the hw struct 4193 * @enable_update: Enable or Disable event posting 4194 * @cmd_details: pointer to command details structure or NULL 4195 * 4196 * Enable or Disable posting of an event on ARQ when LLDP MIB 4197 * associated with the interface changes 4198 **/ 4199 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4200 bool enable_update, 4201 struct i40e_asq_cmd_details *cmd_details) 4202 { 4203 struct i40e_aq_desc desc; 4204 struct i40e_aqc_lldp_update_mib *cmd = 4205 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4206 enum i40e_status_code status; 4207 4208 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4209 4210 if (!enable_update) 4211 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4212 4213 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4214 4215 return status; 4216 } 4217 4218 /** 4219 * i40e_aq_add_lldp_tlv 4220 * @hw: pointer to the hw struct 4221 * @bridge_type: type of bridge 4222 * @buff: buffer with TLV to add 4223 * @buff_size: length of the buffer 4224 * @tlv_len: length of the TLV to be added 4225 * @mib_len: length of the LLDP MIB returned in response 4226 * @cmd_details: pointer to command details structure or NULL 4227 * 4228 * Add the specified TLV to LLDP Local MIB for the given bridge type, 4229 * it is responsibility of the caller to make sure that the TLV is not 4230 * already present in the LLDPDU. 4231 * In return firmware will write the complete LLDP MIB with the newly 4232 * added TLV in the response buffer. 4233 **/ 4234 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 4235 void *buff, u16 buff_size, u16 tlv_len, 4236 u16 *mib_len, 4237 struct i40e_asq_cmd_details *cmd_details) 4238 { 4239 struct i40e_aq_desc desc; 4240 struct i40e_aqc_lldp_add_tlv *cmd = 4241 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4242 enum i40e_status_code status; 4243 4244 if (buff_size == 0 || !buff || tlv_len == 0) 4245 return I40E_ERR_PARAM; 4246 4247 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 4248 4249 /* Indirect Command */ 4250 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4251 if (buff_size > I40E_AQ_LARGE_BUF) 4252 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4253 desc.datalen = CPU_TO_LE16(buff_size); 4254 4255 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4256 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4257 cmd->len = CPU_TO_LE16(tlv_len); 4258 4259 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4260 if (!status) { 4261 if (mib_len != NULL) 4262 *mib_len = LE16_TO_CPU(desc.datalen); 4263 } 4264 4265 return status; 4266 } 4267 4268 /** 4269 * i40e_aq_update_lldp_tlv 4270 * @hw: pointer to the hw struct 4271 * @bridge_type: type of bridge 4272 * @buff: buffer with TLV to update 4273 * @buff_size: size of the buffer holding original and updated TLVs 4274 * @old_len: Length of the Original TLV 4275 * @new_len: Length of the Updated TLV 4276 * @offset: offset of the updated TLV in the buff 4277 * @mib_len: length of the returned LLDP MIB 4278 * @cmd_details: pointer to command details structure or NULL 4279 * 4280 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 4281 * Firmware will place the complete LLDP MIB in response buffer with the 4282 * updated TLV. 4283 **/ 4284 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 4285 u8 bridge_type, void *buff, u16 buff_size, 4286 u16 old_len, u16 new_len, u16 offset, 4287 u16 *mib_len, 4288 struct i40e_asq_cmd_details *cmd_details) 4289 { 4290 struct i40e_aq_desc desc; 4291 struct i40e_aqc_lldp_update_tlv *cmd = 4292 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 4293 enum i40e_status_code status; 4294 4295 if (buff_size == 0 || !buff || offset == 0 || 4296 old_len == 0 || new_len == 0) 4297 return I40E_ERR_PARAM; 4298 4299 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 4300 4301 /* Indirect Command */ 4302 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4303 if (buff_size > I40E_AQ_LARGE_BUF) 4304 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4305 desc.datalen = CPU_TO_LE16(buff_size); 4306 4307 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4308 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4309 cmd->old_len = CPU_TO_LE16(old_len); 4310 cmd->new_offset = CPU_TO_LE16(offset); 4311 cmd->new_len = CPU_TO_LE16(new_len); 4312 4313 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4314 if (!status) { 4315 if (mib_len != NULL) 4316 *mib_len = LE16_TO_CPU(desc.datalen); 4317 } 4318 4319 return status; 4320 } 4321 4322 /** 4323 * i40e_aq_delete_lldp_tlv 4324 * @hw: pointer to the hw struct 4325 * @bridge_type: type of bridge 4326 * @buff: pointer to a user supplied buffer that has the TLV 4327 * @buff_size: length of the buffer 4328 * @tlv_len: length of the TLV to be deleted 4329 * @mib_len: length of the returned LLDP MIB 4330 * @cmd_details: pointer to command details structure or NULL 4331 * 4332 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 4333 * The firmware places the entire LLDP MIB in the response buffer. 4334 **/ 4335 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 4336 u8 bridge_type, void *buff, u16 buff_size, 4337 u16 tlv_len, u16 *mib_len, 4338 struct i40e_asq_cmd_details *cmd_details) 4339 { 4340 struct i40e_aq_desc desc; 4341 struct i40e_aqc_lldp_add_tlv *cmd = 4342 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4343 enum i40e_status_code status; 4344 4345 if (buff_size == 0 || !buff) 4346 return I40E_ERR_PARAM; 4347 4348 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 4349 4350 /* Indirect Command */ 4351 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4352 if (buff_size > I40E_AQ_LARGE_BUF) 4353 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4354 desc.datalen = CPU_TO_LE16(buff_size); 4355 cmd->len = CPU_TO_LE16(tlv_len); 4356 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4357 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4358 4359 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4360 if (!status) { 4361 if (mib_len != NULL) 4362 *mib_len = LE16_TO_CPU(desc.datalen); 4363 } 4364 4365 return status; 4366 } 4367 4368 /** 4369 * i40e_aq_stop_lldp 4370 * @hw: pointer to the hw struct 4371 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4372 * @cmd_details: pointer to command details structure or NULL 4373 * 4374 * Stop or Shutdown the embedded LLDP Agent 4375 **/ 4376 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4377 struct i40e_asq_cmd_details *cmd_details) 4378 { 4379 struct i40e_aq_desc desc; 4380 struct i40e_aqc_lldp_stop *cmd = 4381 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4382 enum i40e_status_code status; 4383 4384 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4385 4386 if (shutdown_agent) 4387 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4388 4389 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4390 4391 return status; 4392 } 4393 4394 /** 4395 * i40e_aq_start_lldp 4396 * @hw: pointer to the hw struct 4397 * @cmd_details: pointer to command details structure or NULL 4398 * 4399 * Start the embedded LLDP Agent on all ports. 4400 **/ 4401 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4402 struct i40e_asq_cmd_details *cmd_details) 4403 { 4404 struct i40e_aq_desc desc; 4405 struct i40e_aqc_lldp_start *cmd = 4406 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4407 enum i40e_status_code status; 4408 4409 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4410 4411 cmd->command = I40E_AQ_LLDP_AGENT_START; 4412 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4413 4414 return status; 4415 } 4416 4417 /** 4418 * i40e_aq_set_dcb_parameters 4419 * @hw: pointer to the hw struct 4420 * @cmd_details: pointer to command details structure or NULL 4421 * @dcb_enable: True if DCB configuration needs to be applied 4422 * 4423 **/ 4424 enum i40e_status_code 4425 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 4426 struct i40e_asq_cmd_details *cmd_details) 4427 { 4428 struct i40e_aq_desc desc; 4429 struct i40e_aqc_set_dcb_parameters *cmd = 4430 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 4431 enum i40e_status_code status; 4432 4433 if ((hw->mac.type != I40E_MAC_XL710) || 4434 ((hw->aq.api_maj_ver < 1) || 4435 ((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 6)))) 4436 return I40E_ERR_DEVICE_NOT_SUPPORTED; 4437 4438 i40e_fill_default_direct_cmd_desc(&desc, 4439 i40e_aqc_opc_set_dcb_parameters); 4440 4441 if (dcb_enable) { 4442 cmd->valid_flags = I40E_DCB_VALID; 4443 cmd->command = I40E_AQ_DCB_SET_AGENT; 4444 } 4445 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4446 4447 return status; 4448 } 4449 4450 /** 4451 * i40e_aq_get_cee_dcb_config 4452 * @hw: pointer to the hw struct 4453 * @buff: response buffer that stores CEE operational configuration 4454 * @buff_size: size of the buffer passed 4455 * @cmd_details: pointer to command details structure or NULL 4456 * 4457 * Get CEE DCBX mode operational configuration from firmware 4458 **/ 4459 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4460 void *buff, u16 buff_size, 4461 struct i40e_asq_cmd_details *cmd_details) 4462 { 4463 struct i40e_aq_desc desc; 4464 enum i40e_status_code status; 4465 4466 if (buff_size == 0 || !buff) 4467 return I40E_ERR_PARAM; 4468 4469 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4470 4471 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4472 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4473 cmd_details); 4474 4475 return status; 4476 } 4477 4478 /** 4479 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4480 * @hw: pointer to the hw struct 4481 * @start_agent: True if DCBx Agent needs to be Started 4482 * False if DCBx Agent needs to be Stopped 4483 * @cmd_details: pointer to command details structure or NULL 4484 * 4485 * Start/Stop the embedded dcbx Agent 4486 **/ 4487 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4488 bool start_agent, 4489 struct i40e_asq_cmd_details *cmd_details) 4490 { 4491 struct i40e_aq_desc desc; 4492 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4493 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4494 &desc.params.raw; 4495 enum i40e_status_code status; 4496 4497 i40e_fill_default_direct_cmd_desc(&desc, 4498 i40e_aqc_opc_lldp_stop_start_spec_agent); 4499 4500 if (start_agent) 4501 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4502 4503 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4504 4505 return status; 4506 } 4507 4508 /** 4509 * i40e_aq_add_udp_tunnel 4510 * @hw: pointer to the hw struct 4511 * @udp_port: the UDP port to add 4512 * @header_len: length of the tunneling header length in DWords 4513 * @protocol_index: protocol index type 4514 * @filter_index: pointer to filter index 4515 * @cmd_details: pointer to command details structure or NULL 4516 **/ 4517 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4518 u16 udp_port, u8 protocol_index, 4519 u8 *filter_index, 4520 struct i40e_asq_cmd_details *cmd_details) 4521 { 4522 struct i40e_aq_desc desc; 4523 struct i40e_aqc_add_udp_tunnel *cmd = 4524 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4525 struct i40e_aqc_del_udp_tunnel_completion *resp = 4526 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4527 enum i40e_status_code status; 4528 4529 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4530 4531 cmd->udp_port = CPU_TO_LE16(udp_port); 4532 cmd->protocol_type = protocol_index; 4533 4534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4535 4536 if (!status && filter_index) 4537 *filter_index = resp->index; 4538 4539 return status; 4540 } 4541 4542 /** 4543 * i40e_aq_del_udp_tunnel 4544 * @hw: pointer to the hw struct 4545 * @index: filter index 4546 * @cmd_details: pointer to command details structure or NULL 4547 **/ 4548 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4549 struct i40e_asq_cmd_details *cmd_details) 4550 { 4551 struct i40e_aq_desc desc; 4552 struct i40e_aqc_remove_udp_tunnel *cmd = 4553 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4554 enum i40e_status_code status; 4555 4556 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4557 4558 cmd->index = index; 4559 4560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4561 4562 return status; 4563 } 4564 4565 /** 4566 * i40e_aq_get_switch_resource_alloc (0x0204) 4567 * @hw: pointer to the hw struct 4568 * @num_entries: pointer to u8 to store the number of resource entries returned 4569 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4570 * to store the resource information for all resource types. Each 4571 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4572 * @count: size, in bytes, of the buffer provided 4573 * @cmd_details: pointer to command details structure or NULL 4574 * 4575 * Query the resources allocated to a function. 4576 **/ 4577 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4578 u8 *num_entries, 4579 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4580 u16 count, 4581 struct i40e_asq_cmd_details *cmd_details) 4582 { 4583 struct i40e_aq_desc desc; 4584 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4585 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4586 enum i40e_status_code status; 4587 u16 length = count * sizeof(*buf); 4588 4589 i40e_fill_default_direct_cmd_desc(&desc, 4590 i40e_aqc_opc_get_switch_resource_alloc); 4591 4592 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4593 if (length > I40E_AQ_LARGE_BUF) 4594 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4595 4596 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4597 4598 if (!status && num_entries) 4599 *num_entries = cmd_resp->num_entries; 4600 4601 return status; 4602 } 4603 4604 /** 4605 * i40e_aq_delete_element - Delete switch element 4606 * @hw: pointer to the hw struct 4607 * @seid: the SEID to delete from the switch 4608 * @cmd_details: pointer to command details structure or NULL 4609 * 4610 * This deletes a switch element from the switch. 4611 **/ 4612 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4613 struct i40e_asq_cmd_details *cmd_details) 4614 { 4615 struct i40e_aq_desc desc; 4616 struct i40e_aqc_switch_seid *cmd = 4617 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4618 enum i40e_status_code status; 4619 4620 if (seid == 0) 4621 return I40E_ERR_PARAM; 4622 4623 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4624 4625 cmd->seid = CPU_TO_LE16(seid); 4626 4627 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4628 4629 return status; 4630 } 4631 4632 /** 4633 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4634 * @hw: pointer to the hw struct 4635 * @flags: component flags 4636 * @mac_seid: uplink seid (MAC SEID) 4637 * @vsi_seid: connected vsi seid 4638 * @ret_seid: seid of create pv component 4639 * 4640 * This instantiates an i40e port virtualizer with specified flags. 4641 * Depending on specified flags the port virtualizer can act as a 4642 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4643 */ 4644 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4645 u16 mac_seid, u16 vsi_seid, 4646 u16 *ret_seid) 4647 { 4648 struct i40e_aq_desc desc; 4649 struct i40e_aqc_add_update_pv *cmd = 4650 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4651 struct i40e_aqc_add_update_pv_completion *resp = 4652 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4653 enum i40e_status_code status; 4654 4655 if (vsi_seid == 0) 4656 return I40E_ERR_PARAM; 4657 4658 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4659 cmd->command_flags = CPU_TO_LE16(flags); 4660 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4661 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4662 4663 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4664 if (!status && ret_seid) 4665 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4666 4667 return status; 4668 } 4669 4670 /** 4671 * i40e_aq_add_tag - Add an S/E-tag 4672 * @hw: pointer to the hw struct 4673 * @direct_to_queue: should s-tag direct flow to a specific queue 4674 * @vsi_seid: VSI SEID to use this tag 4675 * @tag: value of the tag 4676 * @queue_num: queue number, only valid is direct_to_queue is TRUE 4677 * @tags_used: return value, number of tags in use by this PF 4678 * @tags_free: return value, number of unallocated tags 4679 * @cmd_details: pointer to command details structure or NULL 4680 * 4681 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4682 * the number of tags allocated by the PF, and the number of unallocated 4683 * tags available. 4684 **/ 4685 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4686 u16 vsi_seid, u16 tag, u16 queue_num, 4687 u16 *tags_used, u16 *tags_free, 4688 struct i40e_asq_cmd_details *cmd_details) 4689 { 4690 struct i40e_aq_desc desc; 4691 struct i40e_aqc_add_tag *cmd = 4692 (struct i40e_aqc_add_tag *)&desc.params.raw; 4693 struct i40e_aqc_add_remove_tag_completion *resp = 4694 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4695 enum i40e_status_code status; 4696 4697 if (vsi_seid == 0) 4698 return I40E_ERR_PARAM; 4699 4700 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4701 4702 cmd->seid = CPU_TO_LE16(vsi_seid); 4703 cmd->tag = CPU_TO_LE16(tag); 4704 if (direct_to_queue) { 4705 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4706 cmd->queue_number = CPU_TO_LE16(queue_num); 4707 } 4708 4709 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4710 4711 if (!status) { 4712 if (tags_used != NULL) 4713 *tags_used = LE16_TO_CPU(resp->tags_used); 4714 if (tags_free != NULL) 4715 *tags_free = LE16_TO_CPU(resp->tags_free); 4716 } 4717 4718 return status; 4719 } 4720 4721 /** 4722 * i40e_aq_remove_tag - Remove an S- or E-tag 4723 * @hw: pointer to the hw struct 4724 * @vsi_seid: VSI SEID this tag is associated with 4725 * @tag: value of the S-tag to delete 4726 * @tags_used: return value, number of tags in use by this PF 4727 * @tags_free: return value, number of unallocated tags 4728 * @cmd_details: pointer to command details structure or NULL 4729 * 4730 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4731 * the number of tags allocated by the PF, and the number of unallocated 4732 * tags available. 4733 **/ 4734 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4735 u16 tag, u16 *tags_used, u16 *tags_free, 4736 struct i40e_asq_cmd_details *cmd_details) 4737 { 4738 struct i40e_aq_desc desc; 4739 struct i40e_aqc_remove_tag *cmd = 4740 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4741 struct i40e_aqc_add_remove_tag_completion *resp = 4742 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4743 enum i40e_status_code status; 4744 4745 if (vsi_seid == 0) 4746 return I40E_ERR_PARAM; 4747 4748 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4749 4750 cmd->seid = CPU_TO_LE16(vsi_seid); 4751 cmd->tag = CPU_TO_LE16(tag); 4752 4753 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4754 4755 if (!status) { 4756 if (tags_used != NULL) 4757 *tags_used = LE16_TO_CPU(resp->tags_used); 4758 if (tags_free != NULL) 4759 *tags_free = LE16_TO_CPU(resp->tags_free); 4760 } 4761 4762 return status; 4763 } 4764 4765 /** 4766 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4767 * @hw: pointer to the hw struct 4768 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4769 * @etag: value of E-tag to add 4770 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4771 * @buf: address of indirect buffer 4772 * @tags_used: return value, number of E-tags in use by this port 4773 * @tags_free: return value, number of unallocated M-tags 4774 * @cmd_details: pointer to command details structure or NULL 4775 * 4776 * This associates a multicast E-tag to a port virtualizer. It will return 4777 * the number of tags allocated by the PF, and the number of unallocated 4778 * tags available. 4779 * 4780 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4781 * num_tags_in_buf long. 4782 **/ 4783 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4784 u16 etag, u8 num_tags_in_buf, void *buf, 4785 u16 *tags_used, u16 *tags_free, 4786 struct i40e_asq_cmd_details *cmd_details) 4787 { 4788 struct i40e_aq_desc desc; 4789 struct i40e_aqc_add_remove_mcast_etag *cmd = 4790 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4791 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4792 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4793 enum i40e_status_code status; 4794 u16 length = sizeof(u16) * num_tags_in_buf; 4795 4796 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4797 return I40E_ERR_PARAM; 4798 4799 i40e_fill_default_direct_cmd_desc(&desc, 4800 i40e_aqc_opc_add_multicast_etag); 4801 4802 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4803 cmd->etag = CPU_TO_LE16(etag); 4804 cmd->num_unicast_etags = num_tags_in_buf; 4805 4806 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4807 if (length > I40E_AQ_LARGE_BUF) 4808 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4809 4810 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4811 4812 if (!status) { 4813 if (tags_used != NULL) 4814 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4815 if (tags_free != NULL) 4816 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4817 } 4818 4819 return status; 4820 } 4821 4822 /** 4823 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4824 * @hw: pointer to the hw struct 4825 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4826 * @etag: value of the E-tag to remove 4827 * @tags_used: return value, number of tags in use by this port 4828 * @tags_free: return value, number of unallocated tags 4829 * @cmd_details: pointer to command details structure or NULL 4830 * 4831 * This deletes an E-tag from the port virtualizer. It will return 4832 * the number of tags allocated by the port, and the number of unallocated 4833 * tags available. 4834 **/ 4835 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4836 u16 etag, u16 *tags_used, u16 *tags_free, 4837 struct i40e_asq_cmd_details *cmd_details) 4838 { 4839 struct i40e_aq_desc desc; 4840 struct i40e_aqc_add_remove_mcast_etag *cmd = 4841 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4842 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4843 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4844 enum i40e_status_code status; 4845 4846 4847 if (pv_seid == 0) 4848 return I40E_ERR_PARAM; 4849 4850 i40e_fill_default_direct_cmd_desc(&desc, 4851 i40e_aqc_opc_remove_multicast_etag); 4852 4853 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4854 cmd->etag = CPU_TO_LE16(etag); 4855 4856 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4857 4858 if (!status) { 4859 if (tags_used != NULL) 4860 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4861 if (tags_free != NULL) 4862 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4863 } 4864 4865 return status; 4866 } 4867 4868 /** 4869 * i40e_aq_update_tag - Update an S/E-tag 4870 * @hw: pointer to the hw struct 4871 * @vsi_seid: VSI SEID using this S-tag 4872 * @old_tag: old tag value 4873 * @new_tag: new tag value 4874 * @tags_used: return value, number of tags in use by this PF 4875 * @tags_free: return value, number of unallocated tags 4876 * @cmd_details: pointer to command details structure or NULL 4877 * 4878 * This updates the value of the tag currently attached to this VSI 4879 * in the switch complex. It will return the number of tags allocated 4880 * by the PF, and the number of unallocated tags available. 4881 **/ 4882 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4883 u16 old_tag, u16 new_tag, u16 *tags_used, 4884 u16 *tags_free, 4885 struct i40e_asq_cmd_details *cmd_details) 4886 { 4887 struct i40e_aq_desc desc; 4888 struct i40e_aqc_update_tag *cmd = 4889 (struct i40e_aqc_update_tag *)&desc.params.raw; 4890 struct i40e_aqc_update_tag_completion *resp = 4891 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4892 enum i40e_status_code status; 4893 4894 if (vsi_seid == 0) 4895 return I40E_ERR_PARAM; 4896 4897 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4898 4899 cmd->seid = CPU_TO_LE16(vsi_seid); 4900 cmd->old_tag = CPU_TO_LE16(old_tag); 4901 cmd->new_tag = CPU_TO_LE16(new_tag); 4902 4903 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4904 4905 if (!status) { 4906 if (tags_used != NULL) 4907 *tags_used = LE16_TO_CPU(resp->tags_used); 4908 if (tags_free != NULL) 4909 *tags_free = LE16_TO_CPU(resp->tags_free); 4910 } 4911 4912 return status; 4913 } 4914 4915 /** 4916 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4917 * @hw: pointer to the hw struct 4918 * @tcmap: TC map for request/release any ignore PFC condition 4919 * @request: request or release ignore PFC condition 4920 * @tcmap_ret: return TCs for which PFC is currently ignored 4921 * @cmd_details: pointer to command details structure or NULL 4922 * 4923 * This sends out request/release to ignore PFC condition for a TC. 4924 * It will return the TCs for which PFC is currently ignored. 4925 **/ 4926 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4927 bool request, u8 *tcmap_ret, 4928 struct i40e_asq_cmd_details *cmd_details) 4929 { 4930 struct i40e_aq_desc desc; 4931 struct i40e_aqc_pfc_ignore *cmd_resp = 4932 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4933 enum i40e_status_code status; 4934 4935 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4936 4937 if (request) 4938 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4939 4940 cmd_resp->tc_bitmap = tcmap; 4941 4942 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4943 4944 if (!status) { 4945 if (tcmap_ret != NULL) 4946 *tcmap_ret = cmd_resp->tc_bitmap; 4947 } 4948 4949 return status; 4950 } 4951 4952 /** 4953 * i40e_aq_dcb_updated - DCB Updated Command 4954 * @hw: pointer to the hw struct 4955 * @cmd_details: pointer to command details structure or NULL 4956 * 4957 * When LLDP is handled in PF this command is used by the PF 4958 * to notify EMP that a DCB setting is modified. 4959 * When LLDP is handled in EMP this command is used by the PF 4960 * to notify EMP whenever one of the following parameters get 4961 * modified: 4962 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4963 * - PCIRTT in PRTDCB_GENC.PCIRTT 4964 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4965 * EMP will return when the shared RPB settings have been 4966 * recomputed and modified. The retval field in the descriptor 4967 * will be set to 0 when RPB is modified. 4968 **/ 4969 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 4970 struct i40e_asq_cmd_details *cmd_details) 4971 { 4972 struct i40e_aq_desc desc; 4973 enum i40e_status_code status; 4974 4975 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 4976 4977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4978 4979 return status; 4980 } 4981 4982 /** 4983 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 4984 * @hw: pointer to the hw struct 4985 * @seid: defines the SEID of the switch for which the stats are requested 4986 * @vlan_id: the VLAN ID for which the statistics are requested 4987 * @stat_index: index of the statistics counters block assigned to this VLAN 4988 * @cmd_details: pointer to command details structure or NULL 4989 * 4990 * XL710 supports 128 smonVlanStats counters.This command is used to 4991 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 4992 * switch. 4993 **/ 4994 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 4995 u16 vlan_id, u16 *stat_index, 4996 struct i40e_asq_cmd_details *cmd_details) 4997 { 4998 struct i40e_aq_desc desc; 4999 struct i40e_aqc_add_remove_statistics *cmd_resp = 5000 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5001 enum i40e_status_code status; 5002 5003 if ((seid == 0) || (stat_index == NULL)) 5004 return I40E_ERR_PARAM; 5005 5006 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 5007 5008 cmd_resp->seid = CPU_TO_LE16(seid); 5009 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 5010 5011 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5012 5013 if (!status && stat_index) 5014 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 5015 5016 return status; 5017 } 5018 5019 /** 5020 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 5021 * @hw: pointer to the hw struct 5022 * @seid: defines the SEID of the switch for which the stats are requested 5023 * @vlan_id: the VLAN ID for which the statistics are requested 5024 * @stat_index: index of the statistics counters block assigned to this VLAN 5025 * @cmd_details: pointer to command details structure or NULL 5026 * 5027 * XL710 supports 128 smonVlanStats counters.This command is used to 5028 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 5029 * switch. 5030 **/ 5031 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 5032 u16 vlan_id, u16 stat_index, 5033 struct i40e_asq_cmd_details *cmd_details) 5034 { 5035 struct i40e_aq_desc desc; 5036 struct i40e_aqc_add_remove_statistics *cmd = 5037 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5038 enum i40e_status_code status; 5039 5040 if (seid == 0) 5041 return I40E_ERR_PARAM; 5042 5043 i40e_fill_default_direct_cmd_desc(&desc, 5044 i40e_aqc_opc_remove_statistics); 5045 5046 cmd->seid = CPU_TO_LE16(seid); 5047 cmd->vlan = CPU_TO_LE16(vlan_id); 5048 cmd->stat_index = CPU_TO_LE16(stat_index); 5049 5050 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5051 5052 return status; 5053 } 5054 5055 /** 5056 * i40e_aq_set_port_parameters - set physical port parameters. 5057 * @hw: pointer to the hw struct 5058 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 5059 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 5060 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 5061 * @double_vlan: if set double VLAN is enabled 5062 * @cmd_details: pointer to command details structure or NULL 5063 **/ 5064 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 5065 u16 bad_frame_vsi, bool save_bad_pac, 5066 bool pad_short_pac, bool double_vlan, 5067 struct i40e_asq_cmd_details *cmd_details) 5068 { 5069 struct i40e_aqc_set_port_parameters *cmd; 5070 enum i40e_status_code status; 5071 struct i40e_aq_desc desc; 5072 u16 command_flags = 0; 5073 5074 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 5075 5076 i40e_fill_default_direct_cmd_desc(&desc, 5077 i40e_aqc_opc_set_port_parameters); 5078 5079 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 5080 if (save_bad_pac) 5081 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 5082 if (pad_short_pac) 5083 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 5084 if (double_vlan) 5085 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 5086 cmd->command_flags = CPU_TO_LE16(command_flags); 5087 5088 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5089 5090 return status; 5091 } 5092 5093 /** 5094 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 5095 * @hw: pointer to the hw struct 5096 * @seid: seid for the physical port/switching component/vsi 5097 * @buff: Indirect buffer to hold data parameters and response 5098 * @buff_size: Indirect buffer size 5099 * @opcode: Tx scheduler AQ command opcode 5100 * @cmd_details: pointer to command details structure or NULL 5101 * 5102 * Generic command handler for Tx scheduler AQ commands 5103 **/ 5104 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 5105 void *buff, u16 buff_size, 5106 enum i40e_admin_queue_opc opcode, 5107 struct i40e_asq_cmd_details *cmd_details) 5108 { 5109 struct i40e_aq_desc desc; 5110 struct i40e_aqc_tx_sched_ind *cmd = 5111 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 5112 enum i40e_status_code status; 5113 bool cmd_param_flag = FALSE; 5114 5115 switch (opcode) { 5116 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 5117 case i40e_aqc_opc_configure_vsi_tc_bw: 5118 case i40e_aqc_opc_enable_switching_comp_ets: 5119 case i40e_aqc_opc_modify_switching_comp_ets: 5120 case i40e_aqc_opc_disable_switching_comp_ets: 5121 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 5122 case i40e_aqc_opc_configure_switching_comp_bw_config: 5123 cmd_param_flag = TRUE; 5124 break; 5125 case i40e_aqc_opc_query_vsi_bw_config: 5126 case i40e_aqc_opc_query_vsi_ets_sla_config: 5127 case i40e_aqc_opc_query_switching_comp_ets_config: 5128 case i40e_aqc_opc_query_port_ets_config: 5129 case i40e_aqc_opc_query_switching_comp_bw_config: 5130 cmd_param_flag = FALSE; 5131 break; 5132 default: 5133 return I40E_ERR_PARAM; 5134 } 5135 5136 i40e_fill_default_direct_cmd_desc(&desc, opcode); 5137 5138 /* Indirect command */ 5139 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5140 if (cmd_param_flag) 5141 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5142 if (buff_size > I40E_AQ_LARGE_BUF) 5143 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5144 5145 desc.datalen = CPU_TO_LE16(buff_size); 5146 5147 cmd->vsi_seid = CPU_TO_LE16(seid); 5148 5149 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5150 5151 return status; 5152 } 5153 5154 /** 5155 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 5156 * @hw: pointer to the hw struct 5157 * @seid: VSI seid 5158 * @credit: BW limit credits (0 = disabled) 5159 * @max_credit: Max BW limit credits 5160 * @cmd_details: pointer to command details structure or NULL 5161 **/ 5162 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 5163 u16 seid, u16 credit, u8 max_credit, 5164 struct i40e_asq_cmd_details *cmd_details) 5165 { 5166 struct i40e_aq_desc desc; 5167 struct i40e_aqc_configure_vsi_bw_limit *cmd = 5168 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 5169 enum i40e_status_code status; 5170 5171 i40e_fill_default_direct_cmd_desc(&desc, 5172 i40e_aqc_opc_configure_vsi_bw_limit); 5173 5174 cmd->vsi_seid = CPU_TO_LE16(seid); 5175 cmd->credit = CPU_TO_LE16(credit); 5176 cmd->max_credit = max_credit; 5177 5178 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5179 5180 return status; 5181 } 5182 5183 /** 5184 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5185 * @hw: pointer to the hw struct 5186 * @seid: switching component seid 5187 * @credit: BW limit credits (0 = disabled) 5188 * @max_bw: Max BW limit credits 5189 * @cmd_details: pointer to command details structure or NULL 5190 **/ 5191 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5192 u16 seid, u16 credit, u8 max_bw, 5193 struct i40e_asq_cmd_details *cmd_details) 5194 { 5195 struct i40e_aq_desc desc; 5196 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5197 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5198 enum i40e_status_code status; 5199 5200 i40e_fill_default_direct_cmd_desc(&desc, 5201 i40e_aqc_opc_configure_switching_comp_bw_limit); 5202 5203 cmd->seid = CPU_TO_LE16(seid); 5204 cmd->credit = CPU_TO_LE16(credit); 5205 cmd->max_bw = max_bw; 5206 5207 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5208 5209 return status; 5210 } 5211 5212 /** 5213 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5214 * @hw: pointer to the hw struct 5215 * @seid: VSI seid 5216 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5217 * @cmd_details: pointer to command details structure or NULL 5218 **/ 5219 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5220 u16 seid, 5221 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5222 struct i40e_asq_cmd_details *cmd_details) 5223 { 5224 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5225 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5226 cmd_details); 5227 } 5228 5229 /** 5230 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5231 * @hw: pointer to the hw struct 5232 * @seid: VSI seid 5233 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5234 * @cmd_details: pointer to command details structure or NULL 5235 **/ 5236 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5237 u16 seid, 5238 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5239 struct i40e_asq_cmd_details *cmd_details) 5240 { 5241 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5242 i40e_aqc_opc_configure_vsi_tc_bw, 5243 cmd_details); 5244 } 5245 5246 /** 5247 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5248 * @hw: pointer to the hw struct 5249 * @seid: seid of the switching component 5250 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5251 * @cmd_details: pointer to command details structure or NULL 5252 **/ 5253 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5254 struct i40e_hw *hw, u16 seid, 5255 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5256 struct i40e_asq_cmd_details *cmd_details) 5257 { 5258 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5259 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5260 cmd_details); 5261 } 5262 5263 /** 5264 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5265 * @hw: pointer to the hw struct 5266 * @seid: seid of the VSI 5267 * @bw_data: Buffer to hold VSI BW configuration 5268 * @cmd_details: pointer to command details structure or NULL 5269 **/ 5270 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5271 u16 seid, 5272 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5273 struct i40e_asq_cmd_details *cmd_details) 5274 { 5275 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5276 i40e_aqc_opc_query_vsi_bw_config, 5277 cmd_details); 5278 } 5279 5280 /** 5281 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5282 * @hw: pointer to the hw struct 5283 * @seid: seid of the VSI 5284 * @bw_data: Buffer to hold VSI BW configuration per TC 5285 * @cmd_details: pointer to command details structure or NULL 5286 **/ 5287 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5288 u16 seid, 5289 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5290 struct i40e_asq_cmd_details *cmd_details) 5291 { 5292 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5293 i40e_aqc_opc_query_vsi_ets_sla_config, 5294 cmd_details); 5295 } 5296 5297 /** 5298 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5299 * @hw: pointer to the hw struct 5300 * @seid: seid of the switching component 5301 * @bw_data: Buffer to hold switching component's per TC BW config 5302 * @cmd_details: pointer to command details structure or NULL 5303 **/ 5304 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5305 u16 seid, 5306 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5307 struct i40e_asq_cmd_details *cmd_details) 5308 { 5309 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5310 i40e_aqc_opc_query_switching_comp_ets_config, 5311 cmd_details); 5312 } 5313 5314 /** 5315 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5316 * @hw: pointer to the hw struct 5317 * @seid: seid of the VSI or switching component connected to Physical Port 5318 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5319 * @cmd_details: pointer to command details structure or NULL 5320 **/ 5321 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5322 u16 seid, 5323 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5324 struct i40e_asq_cmd_details *cmd_details) 5325 { 5326 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5327 i40e_aqc_opc_query_port_ets_config, 5328 cmd_details); 5329 } 5330 5331 /** 5332 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5333 * @hw: pointer to the hw struct 5334 * @seid: seid of the switching component 5335 * @bw_data: Buffer to hold switching component's BW configuration 5336 * @cmd_details: pointer to command details structure or NULL 5337 **/ 5338 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5339 u16 seid, 5340 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5341 struct i40e_asq_cmd_details *cmd_details) 5342 { 5343 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5344 i40e_aqc_opc_query_switching_comp_bw_config, 5345 cmd_details); 5346 } 5347 5348 /** 5349 * i40e_validate_filter_settings 5350 * @hw: pointer to the hardware structure 5351 * @settings: Filter control settings 5352 * 5353 * Check and validate the filter control settings passed. 5354 * The function checks for the valid filter/context sizes being 5355 * passed for FCoE and PE. 5356 * 5357 * Returns I40E_SUCCESS if the values passed are valid and within 5358 * range else returns an error. 5359 **/ 5360 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5361 struct i40e_filter_control_settings *settings) 5362 { 5363 u32 fcoe_cntx_size, fcoe_filt_size; 5364 u32 pe_cntx_size, pe_filt_size; 5365 u32 fcoe_fmax; 5366 5367 u32 val; 5368 5369 /* Validate FCoE settings passed */ 5370 switch (settings->fcoe_filt_num) { 5371 case I40E_HASH_FILTER_SIZE_1K: 5372 case I40E_HASH_FILTER_SIZE_2K: 5373 case I40E_HASH_FILTER_SIZE_4K: 5374 case I40E_HASH_FILTER_SIZE_8K: 5375 case I40E_HASH_FILTER_SIZE_16K: 5376 case I40E_HASH_FILTER_SIZE_32K: 5377 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5378 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5379 break; 5380 default: 5381 return I40E_ERR_PARAM; 5382 } 5383 5384 switch (settings->fcoe_cntx_num) { 5385 case I40E_DMA_CNTX_SIZE_512: 5386 case I40E_DMA_CNTX_SIZE_1K: 5387 case I40E_DMA_CNTX_SIZE_2K: 5388 case I40E_DMA_CNTX_SIZE_4K: 5389 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5390 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5391 break; 5392 default: 5393 return I40E_ERR_PARAM; 5394 } 5395 5396 /* Validate PE settings passed */ 5397 switch (settings->pe_filt_num) { 5398 case I40E_HASH_FILTER_SIZE_1K: 5399 case I40E_HASH_FILTER_SIZE_2K: 5400 case I40E_HASH_FILTER_SIZE_4K: 5401 case I40E_HASH_FILTER_SIZE_8K: 5402 case I40E_HASH_FILTER_SIZE_16K: 5403 case I40E_HASH_FILTER_SIZE_32K: 5404 case I40E_HASH_FILTER_SIZE_64K: 5405 case I40E_HASH_FILTER_SIZE_128K: 5406 case I40E_HASH_FILTER_SIZE_256K: 5407 case I40E_HASH_FILTER_SIZE_512K: 5408 case I40E_HASH_FILTER_SIZE_1M: 5409 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5410 pe_filt_size <<= (u32)settings->pe_filt_num; 5411 break; 5412 default: 5413 return I40E_ERR_PARAM; 5414 } 5415 5416 switch (settings->pe_cntx_num) { 5417 case I40E_DMA_CNTX_SIZE_512: 5418 case I40E_DMA_CNTX_SIZE_1K: 5419 case I40E_DMA_CNTX_SIZE_2K: 5420 case I40E_DMA_CNTX_SIZE_4K: 5421 case I40E_DMA_CNTX_SIZE_8K: 5422 case I40E_DMA_CNTX_SIZE_16K: 5423 case I40E_DMA_CNTX_SIZE_32K: 5424 case I40E_DMA_CNTX_SIZE_64K: 5425 case I40E_DMA_CNTX_SIZE_128K: 5426 case I40E_DMA_CNTX_SIZE_256K: 5427 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5428 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5429 break; 5430 default: 5431 return I40E_ERR_PARAM; 5432 } 5433 5434 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5435 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5436 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5437 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5438 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5439 return I40E_ERR_INVALID_SIZE; 5440 5441 return I40E_SUCCESS; 5442 } 5443 5444 /** 5445 * i40e_set_filter_control 5446 * @hw: pointer to the hardware structure 5447 * @settings: Filter control settings 5448 * 5449 * Set the Queue Filters for PE/FCoE and enable filters required 5450 * for a single PF. It is expected that these settings are programmed 5451 * at the driver initialization time. 5452 **/ 5453 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5454 struct i40e_filter_control_settings *settings) 5455 { 5456 enum i40e_status_code ret = I40E_SUCCESS; 5457 u32 hash_lut_size = 0; 5458 u32 val; 5459 5460 if (!settings) 5461 return I40E_ERR_PARAM; 5462 5463 /* Validate the input settings */ 5464 ret = i40e_validate_filter_settings(hw, settings); 5465 if (ret) 5466 return ret; 5467 5468 /* Read the PF Queue Filter control register */ 5469 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5470 5471 /* Program required PE hash buckets for the PF */ 5472 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5473 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5474 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5475 /* Program required PE contexts for the PF */ 5476 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5477 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5478 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5479 5480 /* Program required FCoE hash buckets for the PF */ 5481 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5482 val |= ((u32)settings->fcoe_filt_num << 5483 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5484 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5485 /* Program required FCoE DDP contexts for the PF */ 5486 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5487 val |= ((u32)settings->fcoe_cntx_num << 5488 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5489 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5490 5491 /* Program Hash LUT size for the PF */ 5492 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5493 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5494 hash_lut_size = 1; 5495 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5496 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5497 5498 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5499 if (settings->enable_fdir) 5500 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5501 if (settings->enable_ethtype) 5502 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5503 if (settings->enable_macvlan) 5504 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5505 5506 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5507 5508 return I40E_SUCCESS; 5509 } 5510 5511 /** 5512 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5513 * @hw: pointer to the hw struct 5514 * @mac_addr: MAC address to use in the filter 5515 * @ethtype: Ethertype to use in the filter 5516 * @flags: Flags that needs to be applied to the filter 5517 * @vsi_seid: seid of the control VSI 5518 * @queue: VSI queue number to send the packet to 5519 * @is_add: Add control packet filter if True else remove 5520 * @stats: Structure to hold information on control filter counts 5521 * @cmd_details: pointer to command details structure or NULL 5522 * 5523 * This command will Add or Remove control packet filter for a control VSI. 5524 * In return it will update the total number of perfect filter count in 5525 * the stats member. 5526 **/ 5527 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5528 u8 *mac_addr, u16 ethtype, u16 flags, 5529 u16 vsi_seid, u16 queue, bool is_add, 5530 struct i40e_control_filter_stats *stats, 5531 struct i40e_asq_cmd_details *cmd_details) 5532 { 5533 struct i40e_aq_desc desc; 5534 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5535 (struct i40e_aqc_add_remove_control_packet_filter *) 5536 &desc.params.raw; 5537 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5538 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5539 &desc.params.raw; 5540 enum i40e_status_code status; 5541 5542 if (vsi_seid == 0) 5543 return I40E_ERR_PARAM; 5544 5545 if (is_add) { 5546 i40e_fill_default_direct_cmd_desc(&desc, 5547 i40e_aqc_opc_add_control_packet_filter); 5548 cmd->queue = CPU_TO_LE16(queue); 5549 } else { 5550 i40e_fill_default_direct_cmd_desc(&desc, 5551 i40e_aqc_opc_remove_control_packet_filter); 5552 } 5553 5554 if (mac_addr) 5555 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN, 5556 I40E_NONDMA_TO_NONDMA); 5557 5558 cmd->etype = CPU_TO_LE16(ethtype); 5559 cmd->flags = CPU_TO_LE16(flags); 5560 cmd->seid = CPU_TO_LE16(vsi_seid); 5561 5562 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5563 5564 if (!status && stats) { 5565 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5566 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5567 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5568 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5569 } 5570 5571 return status; 5572 } 5573 5574 /** 5575 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5576 * @hw: pointer to the hw struct 5577 * @seid: VSI seid to add ethertype filter from 5578 **/ 5579 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5580 u16 seid) 5581 { 5582 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5583 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5584 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5585 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5586 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5587 enum i40e_status_code status; 5588 5589 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5590 seid, 0, TRUE, NULL, 5591 NULL); 5592 if (status) 5593 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5594 } 5595 5596 /** 5597 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5598 * @filters: list of cloud filters 5599 * @filter_count: length of list 5600 * 5601 * There's an issue in the device where the Geneve VNI layout needs 5602 * to be shifted 1 byte over from the VxLAN VNI 5603 **/ 5604 static void i40e_fix_up_geneve_vni( 5605 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5606 u8 filter_count) 5607 { 5608 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters; 5609 int i; 5610 5611 for (i = 0; i < filter_count; i++) { 5612 u16 tnl_type; 5613 u32 ti; 5614 5615 tnl_type = (LE16_TO_CPU(f[i].flags) & 5616 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5617 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5618 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5619 ti = LE32_TO_CPU(f[i].tenant_id); 5620 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5621 } 5622 } 5623 } 5624 5625 /** 5626 * i40e_aq_add_cloud_filters 5627 * @hw: pointer to the hardware structure 5628 * @seid: VSI seid to add cloud filters from 5629 * @filters: Buffer which contains the filters to be added 5630 * @filter_count: number of filters contained in the buffer 5631 * 5632 * Set the cloud filters for a given VSI. The contents of the 5633 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5634 * in by the caller of the function. 5635 * 5636 **/ 5637 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5638 u16 seid, 5639 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5640 u8 filter_count) 5641 { 5642 struct i40e_aq_desc desc; 5643 struct i40e_aqc_add_remove_cloud_filters *cmd = 5644 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5645 enum i40e_status_code status; 5646 u16 buff_len; 5647 5648 i40e_fill_default_direct_cmd_desc(&desc, 5649 i40e_aqc_opc_add_cloud_filters); 5650 5651 buff_len = filter_count * sizeof(*filters); 5652 desc.datalen = CPU_TO_LE16(buff_len); 5653 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5654 cmd->num_filters = filter_count; 5655 cmd->seid = CPU_TO_LE16(seid); 5656 5657 i40e_fix_up_geneve_vni(filters, filter_count); 5658 5659 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5660 5661 return status; 5662 } 5663 5664 /** 5665 * i40e_aq_remove_cloud_filters 5666 * @hw: pointer to the hardware structure 5667 * @seid: VSI seid to remove cloud filters from 5668 * @filters: Buffer which contains the filters to be removed 5669 * @filter_count: number of filters contained in the buffer 5670 * 5671 * Remove the cloud filters for a given VSI. The contents of the 5672 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5673 * in by the caller of the function. 5674 * 5675 **/ 5676 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 5677 u16 seid, 5678 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5679 u8 filter_count) 5680 { 5681 struct i40e_aq_desc desc; 5682 struct i40e_aqc_add_remove_cloud_filters *cmd = 5683 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5684 enum i40e_status_code status; 5685 u16 buff_len; 5686 5687 i40e_fill_default_direct_cmd_desc(&desc, 5688 i40e_aqc_opc_remove_cloud_filters); 5689 5690 buff_len = filter_count * sizeof(*filters); 5691 desc.datalen = CPU_TO_LE16(buff_len); 5692 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5693 cmd->num_filters = filter_count; 5694 cmd->seid = CPU_TO_LE16(seid); 5695 5696 i40e_fix_up_geneve_vni(filters, filter_count); 5697 5698 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5699 5700 return status; 5701 } 5702 5703 /** 5704 * i40e_aq_alternate_write 5705 * @hw: pointer to the hardware structure 5706 * @reg_addr0: address of first dword to be read 5707 * @reg_val0: value to be written under 'reg_addr0' 5708 * @reg_addr1: address of second dword to be read 5709 * @reg_val1: value to be written under 'reg_addr1' 5710 * 5711 * Write one or two dwords to alternate structure. Fields are indicated 5712 * by 'reg_addr0' and 'reg_addr1' register numbers. 5713 * 5714 **/ 5715 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 5716 u32 reg_addr0, u32 reg_val0, 5717 u32 reg_addr1, u32 reg_val1) 5718 { 5719 struct i40e_aq_desc desc; 5720 struct i40e_aqc_alternate_write *cmd_resp = 5721 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5722 enum i40e_status_code status; 5723 5724 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 5725 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5726 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5727 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5728 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5729 5730 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5731 5732 return status; 5733 } 5734 5735 /** 5736 * i40e_aq_alternate_write_indirect 5737 * @hw: pointer to the hardware structure 5738 * @addr: address of a first register to be modified 5739 * @dw_count: number of alternate structure fields to write 5740 * @buffer: pointer to the command buffer 5741 * 5742 * Write 'dw_count' dwords from 'buffer' to alternate structure 5743 * starting at 'addr'. 5744 * 5745 **/ 5746 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5747 u32 addr, u32 dw_count, void *buffer) 5748 { 5749 struct i40e_aq_desc desc; 5750 struct i40e_aqc_alternate_ind_write *cmd_resp = 5751 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5752 enum i40e_status_code status; 5753 5754 if (buffer == NULL) 5755 return I40E_ERR_PARAM; 5756 5757 /* Indirect command */ 5758 i40e_fill_default_direct_cmd_desc(&desc, 5759 i40e_aqc_opc_alternate_write_indirect); 5760 5761 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5762 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5763 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5764 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5765 5766 cmd_resp->address = CPU_TO_LE32(addr); 5767 cmd_resp->length = CPU_TO_LE32(dw_count); 5768 5769 status = i40e_asq_send_command(hw, &desc, buffer, 5770 I40E_LO_DWORD(4*dw_count), NULL); 5771 5772 return status; 5773 } 5774 5775 /** 5776 * i40e_aq_alternate_read 5777 * @hw: pointer to the hardware structure 5778 * @reg_addr0: address of first dword to be read 5779 * @reg_val0: pointer for data read from 'reg_addr0' 5780 * @reg_addr1: address of second dword to be read 5781 * @reg_val1: pointer for data read from 'reg_addr1' 5782 * 5783 * Read one or two dwords from alternate structure. Fields are indicated 5784 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5785 * is not passed then only register at 'reg_addr0' is read. 5786 * 5787 **/ 5788 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5789 u32 reg_addr0, u32 *reg_val0, 5790 u32 reg_addr1, u32 *reg_val1) 5791 { 5792 struct i40e_aq_desc desc; 5793 struct i40e_aqc_alternate_write *cmd_resp = 5794 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5795 enum i40e_status_code status; 5796 5797 if (reg_val0 == NULL) 5798 return I40E_ERR_PARAM; 5799 5800 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5801 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5802 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5803 5804 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5805 5806 if (status == I40E_SUCCESS) { 5807 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5808 5809 if (reg_val1 != NULL) 5810 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5811 } 5812 5813 return status; 5814 } 5815 5816 /** 5817 * i40e_aq_alternate_read_indirect 5818 * @hw: pointer to the hardware structure 5819 * @addr: address of the alternate structure field 5820 * @dw_count: number of alternate structure fields to read 5821 * @buffer: pointer to the command buffer 5822 * 5823 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5824 * place them in 'buffer'. The buffer should be allocated by caller. 5825 * 5826 **/ 5827 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5828 u32 addr, u32 dw_count, void *buffer) 5829 { 5830 struct i40e_aq_desc desc; 5831 struct i40e_aqc_alternate_ind_write *cmd_resp = 5832 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5833 enum i40e_status_code status; 5834 5835 if (buffer == NULL) 5836 return I40E_ERR_PARAM; 5837 5838 /* Indirect command */ 5839 i40e_fill_default_direct_cmd_desc(&desc, 5840 i40e_aqc_opc_alternate_read_indirect); 5841 5842 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5843 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5844 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5845 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5846 5847 cmd_resp->address = CPU_TO_LE32(addr); 5848 cmd_resp->length = CPU_TO_LE32(dw_count); 5849 5850 status = i40e_asq_send_command(hw, &desc, buffer, 5851 I40E_LO_DWORD(4*dw_count), NULL); 5852 5853 return status; 5854 } 5855 5856 /** 5857 * i40e_aq_alternate_clear 5858 * @hw: pointer to the HW structure. 5859 * 5860 * Clear the alternate structures of the port from which the function 5861 * is called. 5862 * 5863 **/ 5864 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 5865 { 5866 struct i40e_aq_desc desc; 5867 enum i40e_status_code status; 5868 5869 i40e_fill_default_direct_cmd_desc(&desc, 5870 i40e_aqc_opc_alternate_clear_port); 5871 5872 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5873 5874 return status; 5875 } 5876 5877 /** 5878 * i40e_aq_alternate_write_done 5879 * @hw: pointer to the HW structure. 5880 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 5881 * @reset_needed: indicates the SW should trigger GLOBAL reset 5882 * 5883 * Indicates to the FW that alternate structures have been changed. 5884 * 5885 **/ 5886 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 5887 u8 bios_mode, bool *reset_needed) 5888 { 5889 struct i40e_aq_desc desc; 5890 struct i40e_aqc_alternate_write_done *cmd = 5891 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5892 enum i40e_status_code status; 5893 5894 if (reset_needed == NULL) 5895 return I40E_ERR_PARAM; 5896 5897 i40e_fill_default_direct_cmd_desc(&desc, 5898 i40e_aqc_opc_alternate_write_done); 5899 5900 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 5901 5902 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5903 if (!status && reset_needed) 5904 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 5905 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 5906 5907 return status; 5908 } 5909 5910 /** 5911 * i40e_aq_set_oem_mode 5912 * @hw: pointer to the HW structure. 5913 * @oem_mode: the OEM mode to be used 5914 * 5915 * Sets the device to a specific operating mode. Currently the only supported 5916 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 5917 * 5918 **/ 5919 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 5920 u8 oem_mode) 5921 { 5922 struct i40e_aq_desc desc; 5923 struct i40e_aqc_alternate_write_done *cmd = 5924 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5925 enum i40e_status_code status; 5926 5927 i40e_fill_default_direct_cmd_desc(&desc, 5928 i40e_aqc_opc_alternate_set_mode); 5929 5930 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 5931 5932 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5933 5934 return status; 5935 } 5936 5937 /** 5938 * i40e_aq_resume_port_tx 5939 * @hw: pointer to the hardware structure 5940 * @cmd_details: pointer to command details structure or NULL 5941 * 5942 * Resume port's Tx traffic 5943 **/ 5944 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 5945 struct i40e_asq_cmd_details *cmd_details) 5946 { 5947 struct i40e_aq_desc desc; 5948 enum i40e_status_code status; 5949 5950 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 5951 5952 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5953 5954 return status; 5955 } 5956 5957 /** 5958 * i40e_set_pci_config_data - store PCI bus info 5959 * @hw: pointer to hardware structure 5960 * @link_status: the link status word from PCI config space 5961 * 5962 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 5963 **/ 5964 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 5965 { 5966 hw->bus.type = i40e_bus_type_pci_express; 5967 5968 switch (link_status & I40E_PCI_LINK_WIDTH) { 5969 case I40E_PCI_LINK_WIDTH_1: 5970 hw->bus.width = i40e_bus_width_pcie_x1; 5971 break; 5972 case I40E_PCI_LINK_WIDTH_2: 5973 hw->bus.width = i40e_bus_width_pcie_x2; 5974 break; 5975 case I40E_PCI_LINK_WIDTH_4: 5976 hw->bus.width = i40e_bus_width_pcie_x4; 5977 break; 5978 case I40E_PCI_LINK_WIDTH_8: 5979 hw->bus.width = i40e_bus_width_pcie_x8; 5980 break; 5981 default: 5982 hw->bus.width = i40e_bus_width_unknown; 5983 break; 5984 } 5985 5986 switch (link_status & I40E_PCI_LINK_SPEED) { 5987 case I40E_PCI_LINK_SPEED_2500: 5988 hw->bus.speed = i40e_bus_speed_2500; 5989 break; 5990 case I40E_PCI_LINK_SPEED_5000: 5991 hw->bus.speed = i40e_bus_speed_5000; 5992 break; 5993 case I40E_PCI_LINK_SPEED_8000: 5994 hw->bus.speed = i40e_bus_speed_8000; 5995 break; 5996 default: 5997 hw->bus.speed = i40e_bus_speed_unknown; 5998 break; 5999 } 6000 } 6001 6002 /** 6003 * i40e_aq_debug_dump 6004 * @hw: pointer to the hardware structure 6005 * @cluster_id: specific cluster to dump 6006 * @table_id: table id within cluster 6007 * @start_index: index of line in the block to read 6008 * @buff_size: dump buffer size 6009 * @buff: dump buffer 6010 * @ret_buff_size: actual buffer size returned 6011 * @ret_next_table: next block to read 6012 * @ret_next_index: next index to read 6013 * @cmd_details: pointer to command details structure or NULL 6014 * 6015 * Dump internal FW/HW data for debug purposes. 6016 * 6017 **/ 6018 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 6019 u8 table_id, u32 start_index, u16 buff_size, 6020 void *buff, u16 *ret_buff_size, 6021 u8 *ret_next_table, u32 *ret_next_index, 6022 struct i40e_asq_cmd_details *cmd_details) 6023 { 6024 struct i40e_aq_desc desc; 6025 struct i40e_aqc_debug_dump_internals *cmd = 6026 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6027 struct i40e_aqc_debug_dump_internals *resp = 6028 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6029 enum i40e_status_code status; 6030 6031 if (buff_size == 0 || !buff) 6032 return I40E_ERR_PARAM; 6033 6034 i40e_fill_default_direct_cmd_desc(&desc, 6035 i40e_aqc_opc_debug_dump_internals); 6036 /* Indirect Command */ 6037 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6038 if (buff_size > I40E_AQ_LARGE_BUF) 6039 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6040 6041 cmd->cluster_id = cluster_id; 6042 cmd->table_id = table_id; 6043 cmd->idx = CPU_TO_LE32(start_index); 6044 6045 desc.datalen = CPU_TO_LE16(buff_size); 6046 6047 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 6048 if (!status) { 6049 if (ret_buff_size != NULL) 6050 *ret_buff_size = LE16_TO_CPU(desc.datalen); 6051 if (ret_next_table != NULL) 6052 *ret_next_table = resp->table_id; 6053 if (ret_next_index != NULL) 6054 *ret_next_index = LE32_TO_CPU(resp->idx); 6055 } 6056 6057 return status; 6058 } 6059 6060 /** 6061 * i40e_read_bw_from_alt_ram 6062 * @hw: pointer to the hardware structure 6063 * @max_bw: pointer for max_bw read 6064 * @min_bw: pointer for min_bw read 6065 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 6066 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 6067 * 6068 * Read bw from the alternate ram for the given pf 6069 **/ 6070 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 6071 u32 *max_bw, u32 *min_bw, 6072 bool *min_valid, bool *max_valid) 6073 { 6074 enum i40e_status_code status; 6075 u32 max_bw_addr, min_bw_addr; 6076 6077 /* Calculate the address of the min/max bw registers */ 6078 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6079 I40E_ALT_STRUCT_MAX_BW_OFFSET + 6080 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6081 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6082 I40E_ALT_STRUCT_MIN_BW_OFFSET + 6083 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6084 6085 /* Read the bandwidths from alt ram */ 6086 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 6087 min_bw_addr, min_bw); 6088 6089 if (*min_bw & I40E_ALT_BW_VALID_MASK) 6090 *min_valid = TRUE; 6091 else 6092 *min_valid = FALSE; 6093 6094 if (*max_bw & I40E_ALT_BW_VALID_MASK) 6095 *max_valid = TRUE; 6096 else 6097 *max_valid = FALSE; 6098 6099 return status; 6100 } 6101 6102 /** 6103 * i40e_aq_configure_partition_bw 6104 * @hw: pointer to the hardware structure 6105 * @bw_data: Buffer holding valid pfs and bw limits 6106 * @cmd_details: pointer to command details 6107 * 6108 * Configure partitions guaranteed/max bw 6109 **/ 6110 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 6111 struct i40e_aqc_configure_partition_bw_data *bw_data, 6112 struct i40e_asq_cmd_details *cmd_details) 6113 { 6114 enum i40e_status_code status; 6115 struct i40e_aq_desc desc; 6116 u16 bwd_size = sizeof(*bw_data); 6117 6118 i40e_fill_default_direct_cmd_desc(&desc, 6119 i40e_aqc_opc_configure_partition_bw); 6120 6121 /* Indirect command */ 6122 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6123 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6124 6125 desc.datalen = CPU_TO_LE16(bwd_size); 6126 6127 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 6128 6129 return status; 6130 } 6131 6132 /** 6133 * i40e_read_phy_register_clause22 6134 * @hw: pointer to the HW structure 6135 * @reg: register address in the page 6136 * @phy_addr: PHY address on MDIO interface 6137 * @value: PHY register value 6138 * 6139 * Reads specified PHY register value 6140 **/ 6141 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 6142 u16 reg, u8 phy_addr, u16 *value) 6143 { 6144 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6145 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6146 u32 command = 0; 6147 u16 retry = 1000; 6148 6149 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6150 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6151 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 6152 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6153 (I40E_GLGEN_MSCA_MDICMD_MASK); 6154 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6155 do { 6156 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6157 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6158 status = I40E_SUCCESS; 6159 break; 6160 } 6161 i40e_usec_delay(10); 6162 retry--; 6163 } while (retry); 6164 6165 if (status) { 6166 i40e_debug(hw, I40E_DEBUG_PHY, 6167 "PHY: Can't write command to external PHY.\n"); 6168 } else { 6169 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6170 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6171 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6172 } 6173 6174 return status; 6175 } 6176 6177 /** 6178 * i40e_write_phy_register_clause22 6179 * @hw: pointer to the HW structure 6180 * @reg: register address in the page 6181 * @phy_addr: PHY address on MDIO interface 6182 * @value: PHY register value 6183 * 6184 * Writes specified PHY register value 6185 **/ 6186 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6187 u16 reg, u8 phy_addr, u16 value) 6188 { 6189 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6190 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6191 u32 command = 0; 6192 u16 retry = 1000; 6193 6194 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6195 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6196 6197 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6198 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6199 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6200 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6201 (I40E_GLGEN_MSCA_MDICMD_MASK); 6202 6203 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6204 do { 6205 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6206 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6207 status = I40E_SUCCESS; 6208 break; 6209 } 6210 i40e_usec_delay(10); 6211 retry--; 6212 } while (retry); 6213 6214 return status; 6215 } 6216 6217 /** 6218 * i40e_read_phy_register_clause45 6219 * @hw: pointer to the HW structure 6220 * @page: registers page number 6221 * @reg: register address in the page 6222 * @phy_addr: PHY address on MDIO interface 6223 * @value: PHY register value 6224 * 6225 * Reads specified PHY register value 6226 **/ 6227 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6228 u8 page, u16 reg, u8 phy_addr, u16 *value) 6229 { 6230 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6231 u32 command = 0; 6232 u16 retry = 1000; 6233 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6234 6235 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6236 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6237 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6238 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6239 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6240 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6241 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6242 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6243 do { 6244 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6245 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6246 status = I40E_SUCCESS; 6247 break; 6248 } 6249 i40e_usec_delay(10); 6250 retry--; 6251 } while (retry); 6252 6253 if (status) { 6254 i40e_debug(hw, I40E_DEBUG_PHY, 6255 "PHY: Can't write command to external PHY.\n"); 6256 goto phy_read_end; 6257 } 6258 6259 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6260 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6261 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6262 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6263 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6264 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6265 status = I40E_ERR_TIMEOUT; 6266 retry = 1000; 6267 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6268 do { 6269 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6270 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6271 status = I40E_SUCCESS; 6272 break; 6273 } 6274 i40e_usec_delay(10); 6275 retry--; 6276 } while (retry); 6277 6278 if (!status) { 6279 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6280 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6281 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6282 } else { 6283 i40e_debug(hw, I40E_DEBUG_PHY, 6284 "PHY: Can't read register value from external PHY.\n"); 6285 } 6286 6287 phy_read_end: 6288 return status; 6289 } 6290 6291 /** 6292 * i40e_write_phy_register_clause45 6293 * @hw: pointer to the HW structure 6294 * @page: registers page number 6295 * @reg: register address in the page 6296 * @phy_addr: PHY address on MDIO interface 6297 * @value: PHY register value 6298 * 6299 * Writes value to specified PHY register 6300 **/ 6301 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6302 u8 page, u16 reg, u8 phy_addr, u16 value) 6303 { 6304 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6305 u32 command = 0; 6306 u16 retry = 1000; 6307 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6308 6309 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6310 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6311 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6312 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6313 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6314 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6315 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6316 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6317 do { 6318 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6319 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6320 status = I40E_SUCCESS; 6321 break; 6322 } 6323 i40e_usec_delay(10); 6324 retry--; 6325 } while (retry); 6326 if (status) { 6327 i40e_debug(hw, I40E_DEBUG_PHY, 6328 "PHY: Can't write command to external PHY.\n"); 6329 goto phy_write_end; 6330 } 6331 6332 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6333 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6334 6335 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6336 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6337 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6338 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6339 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6340 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6341 status = I40E_ERR_TIMEOUT; 6342 retry = 1000; 6343 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6344 do { 6345 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6346 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6347 status = I40E_SUCCESS; 6348 break; 6349 } 6350 i40e_usec_delay(10); 6351 retry--; 6352 } while (retry); 6353 6354 phy_write_end: 6355 return status; 6356 } 6357 6358 /** 6359 * i40e_write_phy_register 6360 * @hw: pointer to the HW structure 6361 * @page: registers page number 6362 * @reg: register address in the page 6363 * @phy_addr: PHY address on MDIO interface 6364 * @value: PHY register value 6365 * 6366 * Writes value to specified PHY register 6367 **/ 6368 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6369 u8 page, u16 reg, u8 phy_addr, u16 value) 6370 { 6371 enum i40e_status_code status; 6372 6373 switch (hw->device_id) { 6374 case I40E_DEV_ID_1G_BASE_T_X722: 6375 status = i40e_write_phy_register_clause22(hw, 6376 reg, phy_addr, value); 6377 break; 6378 case I40E_DEV_ID_10G_BASE_T: 6379 case I40E_DEV_ID_10G_BASE_T4: 6380 case I40E_DEV_ID_10G_BASE_T_X722: 6381 case I40E_DEV_ID_25G_B: 6382 case I40E_DEV_ID_25G_SFP28: 6383 status = i40e_write_phy_register_clause45(hw, 6384 page, reg, phy_addr, value); 6385 break; 6386 default: 6387 status = I40E_ERR_UNKNOWN_PHY; 6388 break; 6389 } 6390 6391 return status; 6392 } 6393 6394 /** 6395 * i40e_read_phy_register 6396 * @hw: pointer to the HW structure 6397 * @page: registers page number 6398 * @reg: register address in the page 6399 * @phy_addr: PHY address on MDIO interface 6400 * @value: PHY register value 6401 * 6402 * Reads specified PHY register value 6403 **/ 6404 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6405 u8 page, u16 reg, u8 phy_addr, u16 *value) 6406 { 6407 enum i40e_status_code status; 6408 6409 switch (hw->device_id) { 6410 case I40E_DEV_ID_1G_BASE_T_X722: 6411 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6412 value); 6413 break; 6414 case I40E_DEV_ID_10G_BASE_T: 6415 case I40E_DEV_ID_10G_BASE_T4: 6416 case I40E_DEV_ID_10G_BASE_T_X722: 6417 case I40E_DEV_ID_25G_B: 6418 case I40E_DEV_ID_25G_SFP28: 6419 status = i40e_read_phy_register_clause45(hw, page, reg, 6420 phy_addr, value); 6421 break; 6422 default: 6423 status = I40E_ERR_UNKNOWN_PHY; 6424 break; 6425 } 6426 6427 return status; 6428 } 6429 6430 /** 6431 * i40e_get_phy_address 6432 * @hw: pointer to the HW structure 6433 * @dev_num: PHY port num that address we want 6434 * 6435 * Gets PHY address for current port 6436 **/ 6437 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6438 { 6439 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6440 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6441 6442 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6443 } 6444 6445 /** 6446 * i40e_blink_phy_led 6447 * @hw: pointer to the HW structure 6448 * @time: time how long led will blinks in secs 6449 * @interval: gap between LED on and off in msecs 6450 * 6451 * Blinks PHY link LED 6452 **/ 6453 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6454 u32 time, u32 interval) 6455 { 6456 enum i40e_status_code status = I40E_SUCCESS; 6457 u32 i; 6458 u16 led_ctl = 0; 6459 u16 gpio_led_port; 6460 u16 led_reg; 6461 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6462 u8 phy_addr = 0; 6463 u8 port_num; 6464 6465 i = rd32(hw, I40E_PFGEN_PORTNUM); 6466 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6467 phy_addr = i40e_get_phy_address(hw, port_num); 6468 6469 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6470 led_addr++) { 6471 status = i40e_read_phy_register_clause45(hw, 6472 I40E_PHY_COM_REG_PAGE, 6473 led_addr, phy_addr, 6474 &led_reg); 6475 if (status) 6476 goto phy_blinking_end; 6477 led_ctl = led_reg; 6478 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6479 led_reg = 0; 6480 status = i40e_write_phy_register_clause45(hw, 6481 I40E_PHY_COM_REG_PAGE, 6482 led_addr, phy_addr, 6483 led_reg); 6484 if (status) 6485 goto phy_blinking_end; 6486 break; 6487 } 6488 } 6489 6490 if (time > 0 && interval > 0) { 6491 for (i = 0; i < time * 1000; i += interval) { 6492 status = i40e_read_phy_register_clause45(hw, 6493 I40E_PHY_COM_REG_PAGE, 6494 led_addr, phy_addr, &led_reg); 6495 if (status) 6496 goto restore_config; 6497 if (led_reg & I40E_PHY_LED_MANUAL_ON) 6498 led_reg = 0; 6499 else 6500 led_reg = I40E_PHY_LED_MANUAL_ON; 6501 status = i40e_write_phy_register_clause45(hw, 6502 I40E_PHY_COM_REG_PAGE, 6503 led_addr, phy_addr, led_reg); 6504 if (status) 6505 goto restore_config; 6506 i40e_msec_delay(interval); 6507 } 6508 } 6509 6510 restore_config: 6511 status = i40e_write_phy_register_clause45(hw, 6512 I40E_PHY_COM_REG_PAGE, 6513 led_addr, phy_addr, led_ctl); 6514 6515 phy_blinking_end: 6516 return status; 6517 } 6518 6519 /** 6520 * i40e_led_get_reg - read LED register 6521 * @hw: pointer to the HW structure 6522 * @led_addr: LED register address 6523 * @reg_val: read register value 6524 **/ 6525 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 6526 u32 *reg_val) 6527 { 6528 enum i40e_status_code status; 6529 u8 phy_addr = 0; 6530 6531 *reg_val = 0; 6532 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6533 status = i40e_aq_get_phy_register(hw, 6534 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6535 I40E_PHY_COM_REG_PAGE, 6536 I40E_PHY_LED_PROV_REG_1, 6537 reg_val, NULL); 6538 } else { 6539 phy_addr = i40e_get_phy_address(hw, hw->port); 6540 status = i40e_read_phy_register_clause45(hw, 6541 I40E_PHY_COM_REG_PAGE, 6542 led_addr, phy_addr, 6543 (u16 *)reg_val); 6544 } 6545 return status; 6546 } 6547 6548 /** 6549 * i40e_led_set_reg - write LED register 6550 * @hw: pointer to the HW structure 6551 * @led_addr: LED register address 6552 * @reg_val: register value to write 6553 **/ 6554 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 6555 u32 reg_val) 6556 { 6557 enum i40e_status_code status; 6558 u8 phy_addr = 0; 6559 6560 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6561 status = i40e_aq_set_phy_register(hw, 6562 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6563 I40E_PHY_COM_REG_PAGE, 6564 I40E_PHY_LED_PROV_REG_1, 6565 reg_val, NULL); 6566 } else { 6567 phy_addr = i40e_get_phy_address(hw, hw->port); 6568 status = i40e_write_phy_register_clause45(hw, 6569 I40E_PHY_COM_REG_PAGE, 6570 led_addr, phy_addr, 6571 (u16)reg_val); 6572 } 6573 6574 return status; 6575 } 6576 6577 /** 6578 * i40e_led_get_phy - return current on/off mode 6579 * @hw: pointer to the hw struct 6580 * @led_addr: address of led register to use 6581 * @val: original value of register to use 6582 * 6583 **/ 6584 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 6585 u16 *val) 6586 { 6587 enum i40e_status_code status = I40E_SUCCESS; 6588 u16 gpio_led_port; 6589 u32 reg_val_aq; 6590 u16 temp_addr; 6591 u8 phy_addr = 0; 6592 u16 reg_val; 6593 6594 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6595 status = i40e_aq_get_phy_register(hw, 6596 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6597 I40E_PHY_COM_REG_PAGE, 6598 I40E_PHY_LED_PROV_REG_1, 6599 ®_val_aq, NULL); 6600 if (status == I40E_SUCCESS) 6601 *val = (u16)reg_val_aq; 6602 return status; 6603 } 6604 temp_addr = I40E_PHY_LED_PROV_REG_1; 6605 phy_addr = i40e_get_phy_address(hw, hw->port); 6606 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6607 temp_addr++) { 6608 status = i40e_read_phy_register_clause45(hw, 6609 I40E_PHY_COM_REG_PAGE, 6610 temp_addr, phy_addr, 6611 ®_val); 6612 if (status) 6613 return status; 6614 *val = reg_val; 6615 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 6616 *led_addr = temp_addr; 6617 break; 6618 } 6619 } 6620 return status; 6621 } 6622 6623 /** 6624 * i40e_led_set_phy 6625 * @hw: pointer to the HW structure 6626 * @on: TRUE or FALSE 6627 * @led_addr: address of led register to use 6628 * @mode: original val plus bit for set or ignore 6629 * 6630 * Set led's on or off when controlled by the PHY 6631 * 6632 **/ 6633 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 6634 u16 led_addr, u32 mode) 6635 { 6636 enum i40e_status_code status = I40E_SUCCESS; 6637 u32 led_ctl = 0; 6638 u32 led_reg = 0; 6639 6640 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6641 if (status) 6642 return status; 6643 led_ctl = led_reg; 6644 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6645 led_reg = 0; 6646 status = i40e_led_set_reg(hw, led_addr, led_reg); 6647 if (status) 6648 return status; 6649 } 6650 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6651 if (status) 6652 goto restore_config; 6653 if (on) 6654 led_reg = I40E_PHY_LED_MANUAL_ON; 6655 else 6656 led_reg = 0; 6657 status = i40e_led_set_reg(hw, led_addr, led_reg); 6658 if (status) 6659 goto restore_config; 6660 if (mode & I40E_PHY_LED_MODE_ORIG) { 6661 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 6662 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6663 } 6664 return status; 6665 6666 restore_config: 6667 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6668 return status; 6669 } 6670 6671 /** 6672 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 6673 * @hw: pointer to the hw struct 6674 * @reg_addr: register address 6675 * @reg_val: ptr to register value 6676 * @cmd_details: pointer to command details structure or NULL 6677 * 6678 * Use the firmware to read the Rx control register, 6679 * especially useful if the Rx unit is under heavy pressure 6680 **/ 6681 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 6682 u32 reg_addr, u32 *reg_val, 6683 struct i40e_asq_cmd_details *cmd_details) 6684 { 6685 struct i40e_aq_desc desc; 6686 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 6687 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6688 enum i40e_status_code status; 6689 6690 if (reg_val == NULL) 6691 return I40E_ERR_PARAM; 6692 6693 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 6694 6695 cmd_resp->address = CPU_TO_LE32(reg_addr); 6696 6697 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6698 6699 if (status == I40E_SUCCESS) 6700 *reg_val = LE32_TO_CPU(cmd_resp->value); 6701 6702 return status; 6703 } 6704 6705 /** 6706 * i40e_read_rx_ctl - read from an Rx control register 6707 * @hw: pointer to the hw struct 6708 * @reg_addr: register address 6709 **/ 6710 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 6711 { 6712 enum i40e_status_code status = I40E_SUCCESS; 6713 bool use_register; 6714 int retry = 5; 6715 u32 val = 0; 6716 6717 use_register = (((hw->aq.api_maj_ver == 1) && 6718 (hw->aq.api_min_ver < 5)) || 6719 (hw->mac.type == I40E_MAC_X722)); 6720 if (!use_register) { 6721 do_retry: 6722 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 6723 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6724 i40e_msec_delay(1); 6725 retry--; 6726 goto do_retry; 6727 } 6728 } 6729 6730 /* if the AQ access failed, try the old-fashioned way */ 6731 if (status || use_register) 6732 val = rd32(hw, reg_addr); 6733 6734 return val; 6735 } 6736 6737 /** 6738 * i40e_aq_rx_ctl_write_register 6739 * @hw: pointer to the hw struct 6740 * @reg_addr: register address 6741 * @reg_val: register value 6742 * @cmd_details: pointer to command details structure or NULL 6743 * 6744 * Use the firmware to write to an Rx control register, 6745 * especially useful if the Rx unit is under heavy pressure 6746 **/ 6747 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 6748 u32 reg_addr, u32 reg_val, 6749 struct i40e_asq_cmd_details *cmd_details) 6750 { 6751 struct i40e_aq_desc desc; 6752 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 6753 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6754 enum i40e_status_code status; 6755 6756 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 6757 6758 cmd->address = CPU_TO_LE32(reg_addr); 6759 cmd->value = CPU_TO_LE32(reg_val); 6760 6761 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6762 6763 return status; 6764 } 6765 6766 /** 6767 * i40e_write_rx_ctl - write to an Rx control register 6768 * @hw: pointer to the hw struct 6769 * @reg_addr: register address 6770 * @reg_val: register value 6771 **/ 6772 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 6773 { 6774 enum i40e_status_code status = I40E_SUCCESS; 6775 bool use_register; 6776 int retry = 5; 6777 6778 use_register = (((hw->aq.api_maj_ver == 1) && 6779 (hw->aq.api_min_ver < 5)) || 6780 (hw->mac.type == I40E_MAC_X722)); 6781 if (!use_register) { 6782 do_retry: 6783 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 6784 reg_val, NULL); 6785 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6786 i40e_msec_delay(1); 6787 retry--; 6788 goto do_retry; 6789 } 6790 } 6791 6792 /* if the AQ access failed, try the old-fashioned way */ 6793 if (status || use_register) 6794 wr32(hw, reg_addr, reg_val); 6795 } 6796 6797 6798 /** 6799 * i40e_aq_set_phy_register 6800 * @hw: pointer to the hw struct 6801 * @phy_select: select which phy should be accessed 6802 * @dev_addr: PHY device address 6803 * @reg_addr: PHY register address 6804 * @reg_val: new register value 6805 * @cmd_details: pointer to command details structure or NULL 6806 * 6807 * Write the external PHY register. 6808 **/ 6809 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw, 6810 u8 phy_select, u8 dev_addr, 6811 u32 reg_addr, u32 reg_val, 6812 struct i40e_asq_cmd_details *cmd_details) 6813 { 6814 struct i40e_aq_desc desc; 6815 struct i40e_aqc_phy_register_access *cmd = 6816 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6817 enum i40e_status_code status; 6818 6819 i40e_fill_default_direct_cmd_desc(&desc, 6820 i40e_aqc_opc_set_phy_register); 6821 6822 cmd->phy_interface = phy_select; 6823 cmd->dev_addres = dev_addr; 6824 cmd->reg_address = reg_addr; 6825 cmd->reg_value = reg_val; 6826 6827 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6828 6829 return status; 6830 } 6831 6832 /** 6833 * i40e_aq_get_phy_register 6834 * @hw: pointer to the hw struct 6835 * @phy_select: select which phy should be accessed 6836 * @dev_addr: PHY device address 6837 * @reg_addr: PHY register address 6838 * @reg_val: read register value 6839 * @cmd_details: pointer to command details structure or NULL 6840 * 6841 * Read the external PHY register. 6842 **/ 6843 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw, 6844 u8 phy_select, u8 dev_addr, 6845 u32 reg_addr, u32 *reg_val, 6846 struct i40e_asq_cmd_details *cmd_details) 6847 { 6848 struct i40e_aq_desc desc; 6849 struct i40e_aqc_phy_register_access *cmd = 6850 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6851 enum i40e_status_code status; 6852 6853 i40e_fill_default_direct_cmd_desc(&desc, 6854 i40e_aqc_opc_get_phy_register); 6855 6856 cmd->phy_interface = phy_select; 6857 cmd->dev_addres = dev_addr; 6858 cmd->reg_address = reg_addr; 6859 6860 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6861 if (!status) 6862 *reg_val = cmd->reg_value; 6863 6864 return status; 6865 } 6866 6867 /** 6868 * i40e_aq_set_arp_proxy_config 6869 * @hw: pointer to the HW structure 6870 * @proxy_config: pointer to proxy config command table struct 6871 * @cmd_details: pointer to command details 6872 * 6873 * Set ARP offload parameters from pre-populated 6874 * i40e_aqc_arp_proxy_data struct 6875 **/ 6876 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 6877 struct i40e_aqc_arp_proxy_data *proxy_config, 6878 struct i40e_asq_cmd_details *cmd_details) 6879 { 6880 struct i40e_aq_desc desc; 6881 enum i40e_status_code status; 6882 6883 if (!proxy_config) 6884 return I40E_ERR_PARAM; 6885 6886 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 6887 6888 desc.params.external.addr_high = 6889 CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)proxy_config)); 6890 desc.params.external.addr_low = 6891 CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)proxy_config)); 6892 6893 status = i40e_asq_send_command(hw, &desc, proxy_config, 6894 sizeof(struct i40e_aqc_arp_proxy_data), 6895 cmd_details); 6896 6897 return status; 6898 } 6899 6900 /** 6901 * i40e_aq_opc_set_ns_proxy_table_entry 6902 * @hw: pointer to the HW structure 6903 * @ns_proxy_table_entry: pointer to NS table entry command struct 6904 * @cmd_details: pointer to command details 6905 * 6906 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 6907 * from pre-populated i40e_aqc_ns_proxy_data struct 6908 **/ 6909 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 6910 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 6911 struct i40e_asq_cmd_details *cmd_details) 6912 { 6913 struct i40e_aq_desc desc; 6914 enum i40e_status_code status; 6915 6916 if (!ns_proxy_table_entry) 6917 return I40E_ERR_PARAM; 6918 6919 i40e_fill_default_direct_cmd_desc(&desc, 6920 i40e_aqc_opc_set_ns_proxy_table_entry); 6921 6922 desc.params.external.addr_high = 6923 CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)ns_proxy_table_entry)); 6924 desc.params.external.addr_low = 6925 CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)ns_proxy_table_entry)); 6926 6927 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 6928 sizeof(struct i40e_aqc_ns_proxy_data), 6929 cmd_details); 6930 6931 return status; 6932 } 6933 6934 /** 6935 * i40e_aq_set_clear_wol_filter 6936 * @hw: pointer to the hw struct 6937 * @filter_index: index of filter to modify (0-7) 6938 * @filter: buffer containing filter to be set 6939 * @set_filter: TRUE to set filter, FALSE to clear filter 6940 * @no_wol_tco: if TRUE, pass through packets cannot cause wake-up 6941 * if FALSE, pass through packets may cause wake-up 6942 * @filter_valid: TRUE if filter action is valid 6943 * @no_wol_tco_valid: TRUE if no WoL in TCO traffic action valid 6944 * @cmd_details: pointer to command details structure or NULL 6945 * 6946 * Set or clear WoL filter for port attached to the PF 6947 **/ 6948 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 6949 u8 filter_index, 6950 struct i40e_aqc_set_wol_filter_data *filter, 6951 bool set_filter, bool no_wol_tco, 6952 bool filter_valid, bool no_wol_tco_valid, 6953 struct i40e_asq_cmd_details *cmd_details) 6954 { 6955 struct i40e_aq_desc desc; 6956 struct i40e_aqc_set_wol_filter *cmd = 6957 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 6958 enum i40e_status_code status; 6959 u16 cmd_flags = 0; 6960 u16 valid_flags = 0; 6961 u16 buff_len = 0; 6962 6963 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 6964 6965 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 6966 return I40E_ERR_PARAM; 6967 cmd->filter_index = CPU_TO_LE16(filter_index); 6968 6969 if (set_filter) { 6970 if (!filter) 6971 return I40E_ERR_PARAM; 6972 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 6973 buff_len = sizeof(*filter); 6974 } 6975 if (no_wol_tco) 6976 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 6977 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 6978 6979 if (filter_valid) 6980 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 6981 if (no_wol_tco_valid) 6982 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 6983 cmd->valid_flags = CPU_TO_LE16(valid_flags); 6984 6985 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)filter)); 6986 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)filter)); 6987 6988 status = i40e_asq_send_command(hw, &desc, filter, 6989 buff_len, cmd_details); 6990 6991 return status; 6992 } 6993 6994 /** 6995 * i40e_aq_get_wake_event_reason 6996 * @hw: pointer to the hw struct 6997 * @wake_reason: return value, index of matching filter 6998 * @cmd_details: pointer to command details structure or NULL 6999 * 7000 * Get information for the reason of a Wake Up event 7001 **/ 7002 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 7003 u16 *wake_reason, 7004 struct i40e_asq_cmd_details *cmd_details) 7005 { 7006 struct i40e_aq_desc desc; 7007 struct i40e_aqc_get_wake_reason_completion *resp = 7008 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 7009 enum i40e_status_code status; 7010 7011 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 7012 7013 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7014 7015 if (status == I40E_SUCCESS) 7016 *wake_reason = LE16_TO_CPU(resp->wake_reason); 7017 7018 return status; 7019 } 7020 7021