1 /****************************************************************************** 2 3 Copyright (c) 2013-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "virtchnl.h" 39 40 41 /** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48 static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 { 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 case I40E_DEV_ID_10G_BASE_T4: 65 case I40E_DEV_ID_20G_KR2: 66 case I40E_DEV_ID_20G_KR2_A: 67 case I40E_DEV_ID_25G_B: 68 case I40E_DEV_ID_25G_SFP28: 69 hw->mac.type = I40E_MAC_XL710; 70 break; 71 case I40E_DEV_ID_KX_X722: 72 case I40E_DEV_ID_QSFP_X722: 73 case I40E_DEV_ID_SFP_X722: 74 case I40E_DEV_ID_1G_BASE_T_X722: 75 case I40E_DEV_ID_10G_BASE_T_X722: 76 case I40E_DEV_ID_SFP_I_X722: 77 hw->mac.type = I40E_MAC_X722; 78 break; 79 default: 80 hw->mac.type = I40E_MAC_GENERIC; 81 break; 82 } 83 } else { 84 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 85 } 86 87 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 88 hw->mac.type, status); 89 return status; 90 } 91 92 /** 93 * i40e_aq_str - convert AQ err code to a string 94 * @hw: pointer to the HW structure 95 * @aq_err: the AQ error code to convert 96 **/ 97 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 98 { 99 switch (aq_err) { 100 case I40E_AQ_RC_OK: 101 return "OK"; 102 case I40E_AQ_RC_EPERM: 103 return "I40E_AQ_RC_EPERM"; 104 case I40E_AQ_RC_ENOENT: 105 return "I40E_AQ_RC_ENOENT"; 106 case I40E_AQ_RC_ESRCH: 107 return "I40E_AQ_RC_ESRCH"; 108 case I40E_AQ_RC_EINTR: 109 return "I40E_AQ_RC_EINTR"; 110 case I40E_AQ_RC_EIO: 111 return "I40E_AQ_RC_EIO"; 112 case I40E_AQ_RC_ENXIO: 113 return "I40E_AQ_RC_ENXIO"; 114 case I40E_AQ_RC_E2BIG: 115 return "I40E_AQ_RC_E2BIG"; 116 case I40E_AQ_RC_EAGAIN: 117 return "I40E_AQ_RC_EAGAIN"; 118 case I40E_AQ_RC_ENOMEM: 119 return "I40E_AQ_RC_ENOMEM"; 120 case I40E_AQ_RC_EACCES: 121 return "I40E_AQ_RC_EACCES"; 122 case I40E_AQ_RC_EFAULT: 123 return "I40E_AQ_RC_EFAULT"; 124 case I40E_AQ_RC_EBUSY: 125 return "I40E_AQ_RC_EBUSY"; 126 case I40E_AQ_RC_EEXIST: 127 return "I40E_AQ_RC_EEXIST"; 128 case I40E_AQ_RC_EINVAL: 129 return "I40E_AQ_RC_EINVAL"; 130 case I40E_AQ_RC_ENOTTY: 131 return "I40E_AQ_RC_ENOTTY"; 132 case I40E_AQ_RC_ENOSPC: 133 return "I40E_AQ_RC_ENOSPC"; 134 case I40E_AQ_RC_ENOSYS: 135 return "I40E_AQ_RC_ENOSYS"; 136 case I40E_AQ_RC_ERANGE: 137 return "I40E_AQ_RC_ERANGE"; 138 case I40E_AQ_RC_EFLUSHED: 139 return "I40E_AQ_RC_EFLUSHED"; 140 case I40E_AQ_RC_BAD_ADDR: 141 return "I40E_AQ_RC_BAD_ADDR"; 142 case I40E_AQ_RC_EMODE: 143 return "I40E_AQ_RC_EMODE"; 144 case I40E_AQ_RC_EFBIG: 145 return "I40E_AQ_RC_EFBIG"; 146 } 147 148 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 149 return hw->err_str; 150 } 151 152 /** 153 * i40e_stat_str - convert status err code to a string 154 * @hw: pointer to the HW structure 155 * @stat_err: the status error code to convert 156 **/ 157 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 158 { 159 switch (stat_err) { 160 case I40E_SUCCESS: 161 return "OK"; 162 case I40E_ERR_NVM: 163 return "I40E_ERR_NVM"; 164 case I40E_ERR_NVM_CHECKSUM: 165 return "I40E_ERR_NVM_CHECKSUM"; 166 case I40E_ERR_PHY: 167 return "I40E_ERR_PHY"; 168 case I40E_ERR_CONFIG: 169 return "I40E_ERR_CONFIG"; 170 case I40E_ERR_PARAM: 171 return "I40E_ERR_PARAM"; 172 case I40E_ERR_MAC_TYPE: 173 return "I40E_ERR_MAC_TYPE"; 174 case I40E_ERR_UNKNOWN_PHY: 175 return "I40E_ERR_UNKNOWN_PHY"; 176 case I40E_ERR_LINK_SETUP: 177 return "I40E_ERR_LINK_SETUP"; 178 case I40E_ERR_ADAPTER_STOPPED: 179 return "I40E_ERR_ADAPTER_STOPPED"; 180 case I40E_ERR_INVALID_MAC_ADDR: 181 return "I40E_ERR_INVALID_MAC_ADDR"; 182 case I40E_ERR_DEVICE_NOT_SUPPORTED: 183 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 184 case I40E_ERR_MASTER_REQUESTS_PENDING: 185 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 186 case I40E_ERR_INVALID_LINK_SETTINGS: 187 return "I40E_ERR_INVALID_LINK_SETTINGS"; 188 case I40E_ERR_AUTONEG_NOT_COMPLETE: 189 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 190 case I40E_ERR_RESET_FAILED: 191 return "I40E_ERR_RESET_FAILED"; 192 case I40E_ERR_SWFW_SYNC: 193 return "I40E_ERR_SWFW_SYNC"; 194 case I40E_ERR_NO_AVAILABLE_VSI: 195 return "I40E_ERR_NO_AVAILABLE_VSI"; 196 case I40E_ERR_NO_MEMORY: 197 return "I40E_ERR_NO_MEMORY"; 198 case I40E_ERR_BAD_PTR: 199 return "I40E_ERR_BAD_PTR"; 200 case I40E_ERR_RING_FULL: 201 return "I40E_ERR_RING_FULL"; 202 case I40E_ERR_INVALID_PD_ID: 203 return "I40E_ERR_INVALID_PD_ID"; 204 case I40E_ERR_INVALID_QP_ID: 205 return "I40E_ERR_INVALID_QP_ID"; 206 case I40E_ERR_INVALID_CQ_ID: 207 return "I40E_ERR_INVALID_CQ_ID"; 208 case I40E_ERR_INVALID_CEQ_ID: 209 return "I40E_ERR_INVALID_CEQ_ID"; 210 case I40E_ERR_INVALID_AEQ_ID: 211 return "I40E_ERR_INVALID_AEQ_ID"; 212 case I40E_ERR_INVALID_SIZE: 213 return "I40E_ERR_INVALID_SIZE"; 214 case I40E_ERR_INVALID_ARP_INDEX: 215 return "I40E_ERR_INVALID_ARP_INDEX"; 216 case I40E_ERR_INVALID_FPM_FUNC_ID: 217 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 218 case I40E_ERR_QP_INVALID_MSG_SIZE: 219 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 220 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 221 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 222 case I40E_ERR_INVALID_FRAG_COUNT: 223 return "I40E_ERR_INVALID_FRAG_COUNT"; 224 case I40E_ERR_QUEUE_EMPTY: 225 return "I40E_ERR_QUEUE_EMPTY"; 226 case I40E_ERR_INVALID_ALIGNMENT: 227 return "I40E_ERR_INVALID_ALIGNMENT"; 228 case I40E_ERR_FLUSHED_QUEUE: 229 return "I40E_ERR_FLUSHED_QUEUE"; 230 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 231 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 232 case I40E_ERR_INVALID_IMM_DATA_SIZE: 233 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 234 case I40E_ERR_TIMEOUT: 235 return "I40E_ERR_TIMEOUT"; 236 case I40E_ERR_OPCODE_MISMATCH: 237 return "I40E_ERR_OPCODE_MISMATCH"; 238 case I40E_ERR_CQP_COMPL_ERROR: 239 return "I40E_ERR_CQP_COMPL_ERROR"; 240 case I40E_ERR_INVALID_VF_ID: 241 return "I40E_ERR_INVALID_VF_ID"; 242 case I40E_ERR_INVALID_HMCFN_ID: 243 return "I40E_ERR_INVALID_HMCFN_ID"; 244 case I40E_ERR_BACKING_PAGE_ERROR: 245 return "I40E_ERR_BACKING_PAGE_ERROR"; 246 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 247 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 248 case I40E_ERR_INVALID_PBLE_INDEX: 249 return "I40E_ERR_INVALID_PBLE_INDEX"; 250 case I40E_ERR_INVALID_SD_INDEX: 251 return "I40E_ERR_INVALID_SD_INDEX"; 252 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 253 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 254 case I40E_ERR_INVALID_SD_TYPE: 255 return "I40E_ERR_INVALID_SD_TYPE"; 256 case I40E_ERR_MEMCPY_FAILED: 257 return "I40E_ERR_MEMCPY_FAILED"; 258 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 259 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 260 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 261 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 262 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 263 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 264 case I40E_ERR_SRQ_ENABLED: 265 return "I40E_ERR_SRQ_ENABLED"; 266 case I40E_ERR_ADMIN_QUEUE_ERROR: 267 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 268 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 269 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 270 case I40E_ERR_BUF_TOO_SHORT: 271 return "I40E_ERR_BUF_TOO_SHORT"; 272 case I40E_ERR_ADMIN_QUEUE_FULL: 273 return "I40E_ERR_ADMIN_QUEUE_FULL"; 274 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 275 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 276 case I40E_ERR_BAD_IWARP_CQE: 277 return "I40E_ERR_BAD_IWARP_CQE"; 278 case I40E_ERR_NVM_BLANK_MODE: 279 return "I40E_ERR_NVM_BLANK_MODE"; 280 case I40E_ERR_NOT_IMPLEMENTED: 281 return "I40E_ERR_NOT_IMPLEMENTED"; 282 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 283 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 284 case I40E_ERR_DIAG_TEST_FAILED: 285 return "I40E_ERR_DIAG_TEST_FAILED"; 286 case I40E_ERR_NOT_READY: 287 return "I40E_ERR_NOT_READY"; 288 case I40E_NOT_SUPPORTED: 289 return "I40E_NOT_SUPPORTED"; 290 case I40E_ERR_FIRMWARE_API_VERSION: 291 return "I40E_ERR_FIRMWARE_API_VERSION"; 292 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 293 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 294 } 295 296 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 297 return hw->err_str; 298 } 299 300 /** 301 * i40e_debug_aq 302 * @hw: debug mask related to admin queue 303 * @mask: debug mask 304 * @desc: pointer to admin queue descriptor 305 * @buffer: pointer to command buffer 306 * @buf_len: max length of buffer 307 * 308 * Dumps debug log about adminq command with descriptor contents. 309 **/ 310 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 311 void *buffer, u16 buf_len) 312 { 313 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 314 u8 *buf = (u8 *)buffer; 315 u16 len; 316 u16 i = 0; 317 318 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 319 return; 320 321 len = LE16_TO_CPU(aq_desc->datalen); 322 323 i40e_debug(hw, mask, 324 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 325 LE16_TO_CPU(aq_desc->opcode), 326 LE16_TO_CPU(aq_desc->flags), 327 LE16_TO_CPU(aq_desc->datalen), 328 LE16_TO_CPU(aq_desc->retval)); 329 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 330 LE32_TO_CPU(aq_desc->cookie_high), 331 LE32_TO_CPU(aq_desc->cookie_low)); 332 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 333 LE32_TO_CPU(aq_desc->params.internal.param0), 334 LE32_TO_CPU(aq_desc->params.internal.param1)); 335 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 336 LE32_TO_CPU(aq_desc->params.external.addr_high), 337 LE32_TO_CPU(aq_desc->params.external.addr_low)); 338 339 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 340 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 341 if (buf_len < len) 342 len = buf_len; 343 /* write the full 16-byte chunks */ 344 for (i = 0; i < (len - 16); i += 16) 345 i40e_debug(hw, mask, 346 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 347 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 348 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 349 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 350 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 351 /* the most we could have left is 16 bytes, pad with zeros */ 352 if (i < len) { 353 char d_buf[16]; 354 int j, i_sav; 355 356 i_sav = i; 357 memset(d_buf, 0, sizeof(d_buf)); 358 for (j = 0; i < len; j++, i++) 359 d_buf[j] = buf[i]; 360 i40e_debug(hw, mask, 361 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 362 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 363 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 364 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 365 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 366 } 367 } 368 } 369 370 /** 371 * i40e_check_asq_alive 372 * @hw: pointer to the hw struct 373 * 374 * Returns TRUE if Queue is enabled else FALSE. 375 **/ 376 bool i40e_check_asq_alive(struct i40e_hw *hw) 377 { 378 if (hw->aq.asq.len) 379 return !!(rd32(hw, hw->aq.asq.len) & 380 I40E_PF_ATQLEN_ATQENABLE_MASK); 381 return FALSE; 382 } 383 384 /** 385 * i40e_aq_queue_shutdown 386 * @hw: pointer to the hw struct 387 * @unloading: is the driver unloading itself 388 * 389 * Tell the Firmware that we're shutting down the AdminQ and whether 390 * or not the driver is unloading as well. 391 **/ 392 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 393 bool unloading) 394 { 395 struct i40e_aq_desc desc; 396 struct i40e_aqc_queue_shutdown *cmd = 397 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 398 enum i40e_status_code status; 399 400 i40e_fill_default_direct_cmd_desc(&desc, 401 i40e_aqc_opc_queue_shutdown); 402 403 if (unloading) 404 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 405 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 406 407 return status; 408 } 409 410 /** 411 * i40e_aq_get_set_rss_lut 412 * @hw: pointer to the hardware structure 413 * @vsi_id: vsi fw index 414 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 415 * @lut: pointer to the lut buffer provided by the caller 416 * @lut_size: size of the lut buffer 417 * @set: set TRUE to set the table, FALSE to get the table 418 * 419 * Internal function to get or set RSS look up table 420 **/ 421 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 422 u16 vsi_id, bool pf_lut, 423 u8 *lut, u16 lut_size, 424 bool set) 425 { 426 enum i40e_status_code status; 427 struct i40e_aq_desc desc; 428 struct i40e_aqc_get_set_rss_lut *cmd_resp = 429 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 430 431 if (set) 432 i40e_fill_default_direct_cmd_desc(&desc, 433 i40e_aqc_opc_set_rss_lut); 434 else 435 i40e_fill_default_direct_cmd_desc(&desc, 436 i40e_aqc_opc_get_rss_lut); 437 438 /* Indirect command */ 439 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 440 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 441 442 cmd_resp->vsi_id = 443 CPU_TO_LE16((u16)((vsi_id << 444 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 445 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 446 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 447 448 if (pf_lut) 449 cmd_resp->flags |= CPU_TO_LE16((u16) 450 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 451 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 452 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 453 else 454 cmd_resp->flags |= CPU_TO_LE16((u16) 455 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 456 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 457 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 458 459 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 460 461 return status; 462 } 463 464 /** 465 * i40e_aq_get_rss_lut 466 * @hw: pointer to the hardware structure 467 * @vsi_id: vsi fw index 468 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 469 * @lut: pointer to the lut buffer provided by the caller 470 * @lut_size: size of the lut buffer 471 * 472 * get the RSS lookup table, PF or VSI type 473 **/ 474 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 475 bool pf_lut, u8 *lut, u16 lut_size) 476 { 477 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 478 FALSE); 479 } 480 481 /** 482 * i40e_aq_set_rss_lut 483 * @hw: pointer to the hardware structure 484 * @vsi_id: vsi fw index 485 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 486 * @lut: pointer to the lut buffer provided by the caller 487 * @lut_size: size of the lut buffer 488 * 489 * set the RSS lookup table, PF or VSI type 490 **/ 491 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 492 bool pf_lut, u8 *lut, u16 lut_size) 493 { 494 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE); 495 } 496 497 /** 498 * i40e_aq_get_set_rss_key 499 * @hw: pointer to the hw struct 500 * @vsi_id: vsi fw index 501 * @key: pointer to key info struct 502 * @set: set TRUE to set the key, FALSE to get the key 503 * 504 * get the RSS key per VSI 505 **/ 506 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 507 u16 vsi_id, 508 struct i40e_aqc_get_set_rss_key_data *key, 509 bool set) 510 { 511 enum i40e_status_code status; 512 struct i40e_aq_desc desc; 513 struct i40e_aqc_get_set_rss_key *cmd_resp = 514 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 515 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 516 517 if (set) 518 i40e_fill_default_direct_cmd_desc(&desc, 519 i40e_aqc_opc_set_rss_key); 520 else 521 i40e_fill_default_direct_cmd_desc(&desc, 522 i40e_aqc_opc_get_rss_key); 523 524 /* Indirect command */ 525 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 526 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 527 528 cmd_resp->vsi_id = 529 CPU_TO_LE16((u16)((vsi_id << 530 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 531 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 532 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 533 534 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 535 536 return status; 537 } 538 539 /** 540 * i40e_aq_get_rss_key 541 * @hw: pointer to the hw struct 542 * @vsi_id: vsi fw index 543 * @key: pointer to key info struct 544 * 545 **/ 546 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 547 u16 vsi_id, 548 struct i40e_aqc_get_set_rss_key_data *key) 549 { 550 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE); 551 } 552 553 /** 554 * i40e_aq_set_rss_key 555 * @hw: pointer to the hw struct 556 * @vsi_id: vsi fw index 557 * @key: pointer to key info struct 558 * 559 * set the RSS key per VSI 560 **/ 561 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 562 u16 vsi_id, 563 struct i40e_aqc_get_set_rss_key_data *key) 564 { 565 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE); 566 } 567 568 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 569 * hardware to a bit-field that can be used by SW to more easily determine the 570 * packet type. 571 * 572 * Macros are used to shorten the table lines and make this table human 573 * readable. 574 * 575 * We store the PTYPE in the top byte of the bit field - this is just so that 576 * we can check that the table doesn't have a row missing, as the index into 577 * the table should be the PTYPE. 578 * 579 * Typical work flow: 580 * 581 * IF NOT i40e_ptype_lookup[ptype].known 582 * THEN 583 * Packet is unknown 584 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 585 * Use the rest of the fields to look at the tunnels, inner protocols, etc 586 * ELSE 587 * Use the enum i40e_rx_l2_ptype to decode the packet type 588 * ENDIF 589 */ 590 591 /* macro to make the table lines short */ 592 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 593 { PTYPE, \ 594 1, \ 595 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 596 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 597 I40E_RX_PTYPE_##OUTER_FRAG, \ 598 I40E_RX_PTYPE_TUNNEL_##T, \ 599 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 600 I40E_RX_PTYPE_##TEF, \ 601 I40E_RX_PTYPE_INNER_PROT_##I, \ 602 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 603 604 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 605 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 606 607 /* shorter macros makes the table fit but are terse */ 608 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 609 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 610 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 611 612 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 613 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 614 /* L2 Packet types */ 615 I40E_PTT_UNUSED_ENTRY(0), 616 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 617 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 618 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 619 I40E_PTT_UNUSED_ENTRY(4), 620 I40E_PTT_UNUSED_ENTRY(5), 621 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 622 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 623 I40E_PTT_UNUSED_ENTRY(8), 624 I40E_PTT_UNUSED_ENTRY(9), 625 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 626 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 627 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 628 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 629 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 630 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 631 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 632 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 633 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 634 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 635 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 636 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 637 638 /* Non Tunneled IPv4 */ 639 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 640 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 641 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 642 I40E_PTT_UNUSED_ENTRY(25), 643 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 644 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 645 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 646 647 /* IPv4 --> IPv4 */ 648 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 649 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 650 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 651 I40E_PTT_UNUSED_ENTRY(32), 652 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 653 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 654 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 655 656 /* IPv4 --> IPv6 */ 657 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 658 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 659 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 660 I40E_PTT_UNUSED_ENTRY(39), 661 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 662 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 663 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 664 665 /* IPv4 --> GRE/NAT */ 666 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 667 668 /* IPv4 --> GRE/NAT --> IPv4 */ 669 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 670 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 671 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 672 I40E_PTT_UNUSED_ENTRY(47), 673 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 674 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 675 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 676 677 /* IPv4 --> GRE/NAT --> IPv6 */ 678 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 679 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 680 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 681 I40E_PTT_UNUSED_ENTRY(54), 682 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 683 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 684 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 685 686 /* IPv4 --> GRE/NAT --> MAC */ 687 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 688 689 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 690 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 691 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 692 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 693 I40E_PTT_UNUSED_ENTRY(62), 694 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 695 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 696 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 697 698 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 699 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 700 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 701 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 702 I40E_PTT_UNUSED_ENTRY(69), 703 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 704 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 705 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 706 707 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 708 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 709 710 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 711 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 712 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 713 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 714 I40E_PTT_UNUSED_ENTRY(77), 715 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 716 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 717 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 718 719 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 720 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 721 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 722 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 723 I40E_PTT_UNUSED_ENTRY(84), 724 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 725 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 726 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 727 728 /* Non Tunneled IPv6 */ 729 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 730 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 731 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 732 I40E_PTT_UNUSED_ENTRY(91), 733 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 734 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 735 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 736 737 /* IPv6 --> IPv4 */ 738 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 739 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 740 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 741 I40E_PTT_UNUSED_ENTRY(98), 742 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 743 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 744 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 745 746 /* IPv6 --> IPv6 */ 747 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 748 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 749 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 750 I40E_PTT_UNUSED_ENTRY(105), 751 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 752 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 753 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 754 755 /* IPv6 --> GRE/NAT */ 756 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 757 758 /* IPv6 --> GRE/NAT -> IPv4 */ 759 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 760 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 761 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 762 I40E_PTT_UNUSED_ENTRY(113), 763 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 764 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 765 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 766 767 /* IPv6 --> GRE/NAT -> IPv6 */ 768 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 769 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 770 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 771 I40E_PTT_UNUSED_ENTRY(120), 772 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 773 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 774 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 775 776 /* IPv6 --> GRE/NAT -> MAC */ 777 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 778 779 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 780 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 781 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 782 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 783 I40E_PTT_UNUSED_ENTRY(128), 784 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 785 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 786 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 787 788 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 789 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 790 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 791 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 792 I40E_PTT_UNUSED_ENTRY(135), 793 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 794 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 795 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 796 797 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 798 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 799 800 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 801 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 802 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 803 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 804 I40E_PTT_UNUSED_ENTRY(143), 805 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 806 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 807 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 808 809 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 810 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 811 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 812 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 813 I40E_PTT_UNUSED_ENTRY(150), 814 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 815 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 816 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 817 818 /* unused entries */ 819 I40E_PTT_UNUSED_ENTRY(154), 820 I40E_PTT_UNUSED_ENTRY(155), 821 I40E_PTT_UNUSED_ENTRY(156), 822 I40E_PTT_UNUSED_ENTRY(157), 823 I40E_PTT_UNUSED_ENTRY(158), 824 I40E_PTT_UNUSED_ENTRY(159), 825 826 I40E_PTT_UNUSED_ENTRY(160), 827 I40E_PTT_UNUSED_ENTRY(161), 828 I40E_PTT_UNUSED_ENTRY(162), 829 I40E_PTT_UNUSED_ENTRY(163), 830 I40E_PTT_UNUSED_ENTRY(164), 831 I40E_PTT_UNUSED_ENTRY(165), 832 I40E_PTT_UNUSED_ENTRY(166), 833 I40E_PTT_UNUSED_ENTRY(167), 834 I40E_PTT_UNUSED_ENTRY(168), 835 I40E_PTT_UNUSED_ENTRY(169), 836 837 I40E_PTT_UNUSED_ENTRY(170), 838 I40E_PTT_UNUSED_ENTRY(171), 839 I40E_PTT_UNUSED_ENTRY(172), 840 I40E_PTT_UNUSED_ENTRY(173), 841 I40E_PTT_UNUSED_ENTRY(174), 842 I40E_PTT_UNUSED_ENTRY(175), 843 I40E_PTT_UNUSED_ENTRY(176), 844 I40E_PTT_UNUSED_ENTRY(177), 845 I40E_PTT_UNUSED_ENTRY(178), 846 I40E_PTT_UNUSED_ENTRY(179), 847 848 I40E_PTT_UNUSED_ENTRY(180), 849 I40E_PTT_UNUSED_ENTRY(181), 850 I40E_PTT_UNUSED_ENTRY(182), 851 I40E_PTT_UNUSED_ENTRY(183), 852 I40E_PTT_UNUSED_ENTRY(184), 853 I40E_PTT_UNUSED_ENTRY(185), 854 I40E_PTT_UNUSED_ENTRY(186), 855 I40E_PTT_UNUSED_ENTRY(187), 856 I40E_PTT_UNUSED_ENTRY(188), 857 I40E_PTT_UNUSED_ENTRY(189), 858 859 I40E_PTT_UNUSED_ENTRY(190), 860 I40E_PTT_UNUSED_ENTRY(191), 861 I40E_PTT_UNUSED_ENTRY(192), 862 I40E_PTT_UNUSED_ENTRY(193), 863 I40E_PTT_UNUSED_ENTRY(194), 864 I40E_PTT_UNUSED_ENTRY(195), 865 I40E_PTT_UNUSED_ENTRY(196), 866 I40E_PTT_UNUSED_ENTRY(197), 867 I40E_PTT_UNUSED_ENTRY(198), 868 I40E_PTT_UNUSED_ENTRY(199), 869 870 I40E_PTT_UNUSED_ENTRY(200), 871 I40E_PTT_UNUSED_ENTRY(201), 872 I40E_PTT_UNUSED_ENTRY(202), 873 I40E_PTT_UNUSED_ENTRY(203), 874 I40E_PTT_UNUSED_ENTRY(204), 875 I40E_PTT_UNUSED_ENTRY(205), 876 I40E_PTT_UNUSED_ENTRY(206), 877 I40E_PTT_UNUSED_ENTRY(207), 878 I40E_PTT_UNUSED_ENTRY(208), 879 I40E_PTT_UNUSED_ENTRY(209), 880 881 I40E_PTT_UNUSED_ENTRY(210), 882 I40E_PTT_UNUSED_ENTRY(211), 883 I40E_PTT_UNUSED_ENTRY(212), 884 I40E_PTT_UNUSED_ENTRY(213), 885 I40E_PTT_UNUSED_ENTRY(214), 886 I40E_PTT_UNUSED_ENTRY(215), 887 I40E_PTT_UNUSED_ENTRY(216), 888 I40E_PTT_UNUSED_ENTRY(217), 889 I40E_PTT_UNUSED_ENTRY(218), 890 I40E_PTT_UNUSED_ENTRY(219), 891 892 I40E_PTT_UNUSED_ENTRY(220), 893 I40E_PTT_UNUSED_ENTRY(221), 894 I40E_PTT_UNUSED_ENTRY(222), 895 I40E_PTT_UNUSED_ENTRY(223), 896 I40E_PTT_UNUSED_ENTRY(224), 897 I40E_PTT_UNUSED_ENTRY(225), 898 I40E_PTT_UNUSED_ENTRY(226), 899 I40E_PTT_UNUSED_ENTRY(227), 900 I40E_PTT_UNUSED_ENTRY(228), 901 I40E_PTT_UNUSED_ENTRY(229), 902 903 I40E_PTT_UNUSED_ENTRY(230), 904 I40E_PTT_UNUSED_ENTRY(231), 905 I40E_PTT_UNUSED_ENTRY(232), 906 I40E_PTT_UNUSED_ENTRY(233), 907 I40E_PTT_UNUSED_ENTRY(234), 908 I40E_PTT_UNUSED_ENTRY(235), 909 I40E_PTT_UNUSED_ENTRY(236), 910 I40E_PTT_UNUSED_ENTRY(237), 911 I40E_PTT_UNUSED_ENTRY(238), 912 I40E_PTT_UNUSED_ENTRY(239), 913 914 I40E_PTT_UNUSED_ENTRY(240), 915 I40E_PTT_UNUSED_ENTRY(241), 916 I40E_PTT_UNUSED_ENTRY(242), 917 I40E_PTT_UNUSED_ENTRY(243), 918 I40E_PTT_UNUSED_ENTRY(244), 919 I40E_PTT_UNUSED_ENTRY(245), 920 I40E_PTT_UNUSED_ENTRY(246), 921 I40E_PTT_UNUSED_ENTRY(247), 922 I40E_PTT_UNUSED_ENTRY(248), 923 I40E_PTT_UNUSED_ENTRY(249), 924 925 I40E_PTT_UNUSED_ENTRY(250), 926 I40E_PTT_UNUSED_ENTRY(251), 927 I40E_PTT_UNUSED_ENTRY(252), 928 I40E_PTT_UNUSED_ENTRY(253), 929 I40E_PTT_UNUSED_ENTRY(254), 930 I40E_PTT_UNUSED_ENTRY(255) 931 }; 932 933 934 /** 935 * i40e_validate_mac_addr - Validate unicast MAC address 936 * @mac_addr: pointer to MAC address 937 * 938 * Tests a MAC address to ensure it is a valid Individual Address 939 **/ 940 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 941 { 942 enum i40e_status_code status = I40E_SUCCESS; 943 944 DEBUGFUNC("i40e_validate_mac_addr"); 945 946 /* Broadcast addresses ARE multicast addresses 947 * Make sure it is not a multicast address 948 * Reject the zero address 949 */ 950 if (I40E_IS_MULTICAST(mac_addr) || 951 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 952 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 953 status = I40E_ERR_INVALID_MAC_ADDR; 954 955 return status; 956 } 957 958 /** 959 * i40e_init_shared_code - Initialize the shared code 960 * @hw: pointer to hardware structure 961 * 962 * This assigns the MAC type and PHY code and inits the NVM. 963 * Does not touch the hardware. This function must be called prior to any 964 * other function in the shared code. The i40e_hw structure should be 965 * memset to 0 prior to calling this function. The following fields in 966 * hw structure should be filled in prior to calling this function: 967 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 968 * subsystem_vendor_id, and revision_id 969 **/ 970 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 971 { 972 enum i40e_status_code status = I40E_SUCCESS; 973 u32 port, ari, func_rid; 974 975 DEBUGFUNC("i40e_init_shared_code"); 976 977 i40e_set_mac_type(hw); 978 979 switch (hw->mac.type) { 980 case I40E_MAC_XL710: 981 case I40E_MAC_X722: 982 break; 983 default: 984 return I40E_ERR_DEVICE_NOT_SUPPORTED; 985 } 986 987 hw->phy.get_link_info = TRUE; 988 989 /* Determine port number and PF number*/ 990 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 991 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 992 hw->port = (u8)port; 993 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 994 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 995 func_rid = rd32(hw, I40E_PF_FUNC_RID); 996 if (ari) 997 hw->pf_id = (u8)(func_rid & 0xff); 998 else 999 hw->pf_id = (u8)(func_rid & 0x7); 1000 1001 if (hw->mac.type == I40E_MAC_X722) 1002 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 1003 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 1004 1005 status = i40e_init_nvm(hw); 1006 return status; 1007 } 1008 1009 /** 1010 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1011 * @hw: pointer to the hw struct 1012 * @flags: a return indicator of what addresses were added to the addr store 1013 * @addrs: the requestor's mac addr store 1014 * @cmd_details: pointer to command details structure or NULL 1015 **/ 1016 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1017 u16 *flags, 1018 struct i40e_aqc_mac_address_read_data *addrs, 1019 struct i40e_asq_cmd_details *cmd_details) 1020 { 1021 struct i40e_aq_desc desc; 1022 struct i40e_aqc_mac_address_read *cmd_data = 1023 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1024 enum i40e_status_code status; 1025 1026 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1027 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1028 1029 status = i40e_asq_send_command(hw, &desc, addrs, 1030 sizeof(*addrs), cmd_details); 1031 *flags = LE16_TO_CPU(cmd_data->command_flags); 1032 1033 return status; 1034 } 1035 1036 /** 1037 * i40e_aq_mac_address_write - Change the MAC addresses 1038 * @hw: pointer to the hw struct 1039 * @flags: indicates which MAC to be written 1040 * @mac_addr: address to write 1041 * @cmd_details: pointer to command details structure or NULL 1042 **/ 1043 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1044 u16 flags, u8 *mac_addr, 1045 struct i40e_asq_cmd_details *cmd_details) 1046 { 1047 struct i40e_aq_desc desc; 1048 struct i40e_aqc_mac_address_write *cmd_data = 1049 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1050 enum i40e_status_code status; 1051 1052 i40e_fill_default_direct_cmd_desc(&desc, 1053 i40e_aqc_opc_mac_address_write); 1054 cmd_data->command_flags = CPU_TO_LE16(flags); 1055 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1056 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1057 ((u32)mac_addr[3] << 16) | 1058 ((u32)mac_addr[4] << 8) | 1059 mac_addr[5]); 1060 1061 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1062 1063 return status; 1064 } 1065 1066 /** 1067 * i40e_get_mac_addr - get MAC address 1068 * @hw: pointer to the HW structure 1069 * @mac_addr: pointer to MAC address 1070 * 1071 * Reads the adapter's MAC address from register 1072 **/ 1073 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1074 { 1075 struct i40e_aqc_mac_address_read_data addrs; 1076 enum i40e_status_code status; 1077 u16 flags = 0; 1078 1079 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1080 1081 if (flags & I40E_AQC_LAN_ADDR_VALID) 1082 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1083 I40E_NONDMA_TO_NONDMA); 1084 1085 return status; 1086 } 1087 1088 /** 1089 * i40e_get_port_mac_addr - get Port MAC address 1090 * @hw: pointer to the HW structure 1091 * @mac_addr: pointer to Port MAC address 1092 * 1093 * Reads the adapter's Port MAC address 1094 **/ 1095 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1096 { 1097 struct i40e_aqc_mac_address_read_data addrs; 1098 enum i40e_status_code status; 1099 u16 flags = 0; 1100 1101 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1102 if (status) 1103 return status; 1104 1105 if (flags & I40E_AQC_PORT_ADDR_VALID) 1106 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1107 I40E_NONDMA_TO_NONDMA); 1108 else 1109 status = I40E_ERR_INVALID_MAC_ADDR; 1110 1111 return status; 1112 } 1113 1114 /** 1115 * i40e_pre_tx_queue_cfg - pre tx queue configure 1116 * @hw: pointer to the HW structure 1117 * @queue: target pf queue index 1118 * @enable: state change request 1119 * 1120 * Handles hw requirement to indicate intention to enable 1121 * or disable target queue. 1122 **/ 1123 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1124 { 1125 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1126 u32 reg_block = 0; 1127 u32 reg_val; 1128 1129 if (abs_queue_idx >= 128) { 1130 reg_block = abs_queue_idx / 128; 1131 abs_queue_idx %= 128; 1132 } 1133 1134 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1135 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1136 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1137 1138 if (enable) 1139 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1140 else 1141 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1142 1143 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1144 } 1145 1146 /** 1147 * i40e_read_pba_string - Reads part number string from EEPROM 1148 * @hw: pointer to hardware structure 1149 * @pba_num: stores the part number string from the EEPROM 1150 * @pba_num_size: part number string buffer length 1151 * 1152 * Reads the part number string from the EEPROM. 1153 **/ 1154 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1155 u32 pba_num_size) 1156 { 1157 enum i40e_status_code status = I40E_SUCCESS; 1158 u16 pba_word = 0; 1159 u16 pba_size = 0; 1160 u16 pba_ptr = 0; 1161 u16 i = 0; 1162 1163 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1164 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1165 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1166 return status; 1167 } 1168 1169 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1170 if (status != I40E_SUCCESS) { 1171 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1172 return status; 1173 } 1174 1175 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1176 if (status != I40E_SUCCESS) { 1177 DEBUGOUT("Failed to read PBA Block size.\n"); 1178 return status; 1179 } 1180 1181 /* Subtract one to get PBA word count (PBA Size word is included in 1182 * total size) 1183 */ 1184 pba_size--; 1185 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1186 DEBUGOUT("Buffer to small for PBA data.\n"); 1187 return I40E_ERR_PARAM; 1188 } 1189 1190 for (i = 0; i < pba_size; i++) { 1191 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1192 if (status != I40E_SUCCESS) { 1193 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1194 return status; 1195 } 1196 1197 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1198 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1199 } 1200 pba_num[(pba_size * 2)] = '\0'; 1201 1202 return status; 1203 } 1204 1205 /** 1206 * i40e_get_media_type - Gets media type 1207 * @hw: pointer to the hardware structure 1208 **/ 1209 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1210 { 1211 enum i40e_media_type media; 1212 1213 switch (hw->phy.link_info.phy_type) { 1214 case I40E_PHY_TYPE_10GBASE_SR: 1215 case I40E_PHY_TYPE_10GBASE_LR: 1216 case I40E_PHY_TYPE_1000BASE_SX: 1217 case I40E_PHY_TYPE_1000BASE_LX: 1218 case I40E_PHY_TYPE_40GBASE_SR4: 1219 case I40E_PHY_TYPE_40GBASE_LR4: 1220 case I40E_PHY_TYPE_25GBASE_LR: 1221 case I40E_PHY_TYPE_25GBASE_SR: 1222 media = I40E_MEDIA_TYPE_FIBER; 1223 break; 1224 case I40E_PHY_TYPE_100BASE_TX: 1225 case I40E_PHY_TYPE_1000BASE_T: 1226 case I40E_PHY_TYPE_10GBASE_T: 1227 media = I40E_MEDIA_TYPE_BASET; 1228 break; 1229 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1230 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1231 case I40E_PHY_TYPE_10GBASE_CR1: 1232 case I40E_PHY_TYPE_40GBASE_CR4: 1233 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1234 case I40E_PHY_TYPE_40GBASE_AOC: 1235 case I40E_PHY_TYPE_10GBASE_AOC: 1236 case I40E_PHY_TYPE_25GBASE_CR: 1237 case I40E_PHY_TYPE_25GBASE_AOC: 1238 case I40E_PHY_TYPE_25GBASE_ACC: 1239 media = I40E_MEDIA_TYPE_DA; 1240 break; 1241 case I40E_PHY_TYPE_1000BASE_KX: 1242 case I40E_PHY_TYPE_10GBASE_KX4: 1243 case I40E_PHY_TYPE_10GBASE_KR: 1244 case I40E_PHY_TYPE_40GBASE_KR4: 1245 case I40E_PHY_TYPE_20GBASE_KR2: 1246 case I40E_PHY_TYPE_25GBASE_KR: 1247 media = I40E_MEDIA_TYPE_BACKPLANE; 1248 break; 1249 case I40E_PHY_TYPE_SGMII: 1250 case I40E_PHY_TYPE_XAUI: 1251 case I40E_PHY_TYPE_XFI: 1252 case I40E_PHY_TYPE_XLAUI: 1253 case I40E_PHY_TYPE_XLPPI: 1254 default: 1255 media = I40E_MEDIA_TYPE_UNKNOWN; 1256 break; 1257 } 1258 1259 return media; 1260 } 1261 1262 #define I40E_PF_RESET_WAIT_COUNT 200 1263 /** 1264 * i40e_pf_reset - Reset the PF 1265 * @hw: pointer to the hardware structure 1266 * 1267 * Assuming someone else has triggered a global reset, 1268 * assure the global reset is complete and then reset the PF 1269 **/ 1270 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1271 { 1272 u32 cnt = 0; 1273 u32 cnt1 = 0; 1274 u32 reg = 0; 1275 u32 grst_del; 1276 1277 /* Poll for Global Reset steady state in case of recent GRST. 1278 * The grst delay value is in 100ms units, and we'll wait a 1279 * couple counts longer to be sure we don't just miss the end. 1280 */ 1281 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1282 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1283 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1284 1285 grst_del = grst_del * 20; 1286 1287 for (cnt = 0; cnt < grst_del; cnt++) { 1288 reg = rd32(hw, I40E_GLGEN_RSTAT); 1289 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1290 break; 1291 i40e_msec_delay(100); 1292 } 1293 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1294 DEBUGOUT("Global reset polling failed to complete.\n"); 1295 return I40E_ERR_RESET_FAILED; 1296 } 1297 1298 /* Now Wait for the FW to be ready */ 1299 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1300 reg = rd32(hw, I40E_GLNVM_ULD); 1301 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1302 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1303 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1304 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1305 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1306 break; 1307 } 1308 i40e_msec_delay(10); 1309 } 1310 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1311 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1312 DEBUGOUT("wait for FW Reset complete timedout\n"); 1313 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1314 return I40E_ERR_RESET_FAILED; 1315 } 1316 1317 /* If there was a Global Reset in progress when we got here, 1318 * we don't need to do the PF Reset 1319 */ 1320 if (!cnt) { 1321 u32 reg2 = 0; 1322 1323 reg = rd32(hw, I40E_PFGEN_CTRL); 1324 wr32(hw, I40E_PFGEN_CTRL, 1325 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1326 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1327 reg = rd32(hw, I40E_PFGEN_CTRL); 1328 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1329 break; 1330 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1331 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1332 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n"); 1333 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2); 1334 return I40E_ERR_NOT_READY; 1335 } 1336 i40e_msec_delay(1); 1337 } 1338 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1339 DEBUGOUT("PF reset polling failed to complete.\n"); 1340 return I40E_ERR_RESET_FAILED; 1341 } 1342 } 1343 1344 i40e_clear_pxe_mode(hw); 1345 1346 1347 return I40E_SUCCESS; 1348 } 1349 1350 /** 1351 * i40e_clear_hw - clear out any left over hw state 1352 * @hw: pointer to the hw struct 1353 * 1354 * Clear queues and interrupts, typically called at init time, 1355 * but after the capabilities have been found so we know how many 1356 * queues and msix vectors have been allocated. 1357 **/ 1358 void i40e_clear_hw(struct i40e_hw *hw) 1359 { 1360 u32 num_queues, base_queue; 1361 u32 num_pf_int; 1362 u32 num_vf_int; 1363 u32 num_vfs; 1364 u32 i, j; 1365 u32 val; 1366 u32 eol = 0x7ff; 1367 1368 /* get number of interrupts, queues, and vfs */ 1369 val = rd32(hw, I40E_GLPCI_CNF2); 1370 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1371 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1372 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1373 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1374 1375 val = rd32(hw, I40E_PFLAN_QALLOC); 1376 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1377 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1378 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1379 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1380 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1381 num_queues = (j - base_queue) + 1; 1382 else 1383 num_queues = 0; 1384 1385 val = rd32(hw, I40E_PF_VT_PFALLOC); 1386 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1387 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1388 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1389 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1390 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1391 num_vfs = (j - i) + 1; 1392 else 1393 num_vfs = 0; 1394 1395 /* stop all the interrupts */ 1396 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1397 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1398 for (i = 0; i < num_pf_int - 2; i++) 1399 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1400 1401 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1402 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1403 wr32(hw, I40E_PFINT_LNKLST0, val); 1404 for (i = 0; i < num_pf_int - 2; i++) 1405 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1406 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1407 for (i = 0; i < num_vfs; i++) 1408 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1409 for (i = 0; i < num_vf_int - 2; i++) 1410 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1411 1412 /* warn the HW of the coming Tx disables */ 1413 for (i = 0; i < num_queues; i++) { 1414 u32 abs_queue_idx = base_queue + i; 1415 u32 reg_block = 0; 1416 1417 if (abs_queue_idx >= 128) { 1418 reg_block = abs_queue_idx / 128; 1419 abs_queue_idx %= 128; 1420 } 1421 1422 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1423 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1424 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1425 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1426 1427 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1428 } 1429 i40e_usec_delay(400); 1430 1431 /* stop all the queues */ 1432 for (i = 0; i < num_queues; i++) { 1433 wr32(hw, I40E_QINT_TQCTL(i), 0); 1434 wr32(hw, I40E_QTX_ENA(i), 0); 1435 wr32(hw, I40E_QINT_RQCTL(i), 0); 1436 wr32(hw, I40E_QRX_ENA(i), 0); 1437 } 1438 1439 /* short wait for all queue disables to settle */ 1440 i40e_usec_delay(50); 1441 } 1442 1443 /** 1444 * i40e_clear_pxe_mode - clear pxe operations mode 1445 * @hw: pointer to the hw struct 1446 * 1447 * Make sure all PXE mode settings are cleared, including things 1448 * like descriptor fetch/write-back mode. 1449 **/ 1450 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1451 { 1452 if (i40e_check_asq_alive(hw)) 1453 i40e_aq_clear_pxe_mode(hw, NULL); 1454 } 1455 1456 /** 1457 * i40e_led_is_mine - helper to find matching led 1458 * @hw: pointer to the hw struct 1459 * @idx: index into GPIO registers 1460 * 1461 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1462 */ 1463 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1464 { 1465 u32 gpio_val = 0; 1466 u32 port; 1467 1468 if (!hw->func_caps.led[idx]) 1469 return 0; 1470 1471 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1472 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1473 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1474 1475 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1476 * if it is not our port then ignore 1477 */ 1478 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1479 (port != hw->port)) 1480 return 0; 1481 1482 return gpio_val; 1483 } 1484 1485 #define I40E_COMBINED_ACTIVITY 0xA 1486 #define I40E_FILTER_ACTIVITY 0xE 1487 #define I40E_LINK_ACTIVITY 0xC 1488 #define I40E_MAC_ACTIVITY 0xD 1489 #define I40E_LED0 22 1490 1491 /** 1492 * i40e_led_get - return current on/off mode 1493 * @hw: pointer to the hw struct 1494 * 1495 * The value returned is the 'mode' field as defined in the 1496 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1497 * values are variations of possible behaviors relating to 1498 * blink, link, and wire. 1499 **/ 1500 u32 i40e_led_get(struct i40e_hw *hw) 1501 { 1502 u32 current_mode = 0; 1503 u32 mode = 0; 1504 int i; 1505 1506 /* as per the documentation GPIO 22-29 are the LED 1507 * GPIO pins named LED0..LED7 1508 */ 1509 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1510 u32 gpio_val = i40e_led_is_mine(hw, i); 1511 1512 if (!gpio_val) 1513 continue; 1514 1515 /* ignore gpio LED src mode entries related to the activity 1516 * LEDs 1517 */ 1518 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1519 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1520 switch (current_mode) { 1521 case I40E_COMBINED_ACTIVITY: 1522 case I40E_FILTER_ACTIVITY: 1523 case I40E_MAC_ACTIVITY: 1524 case I40E_LINK_ACTIVITY: 1525 continue; 1526 default: 1527 break; 1528 } 1529 1530 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1531 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1532 break; 1533 } 1534 1535 return mode; 1536 } 1537 1538 /** 1539 * i40e_led_set - set new on/off mode 1540 * @hw: pointer to the hw struct 1541 * @mode: 0=off, 0xf=on (else see manual for mode details) 1542 * @blink: TRUE if the LED should blink when on, FALSE if steady 1543 * 1544 * if this function is used to turn on the blink it should 1545 * be used to disable the blink when restoring the original state. 1546 **/ 1547 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1548 { 1549 u32 current_mode = 0; 1550 int i; 1551 1552 if (mode & 0xfffffff0) 1553 DEBUGOUT1("invalid mode passed in %X\n", mode); 1554 1555 /* as per the documentation GPIO 22-29 are the LED 1556 * GPIO pins named LED0..LED7 1557 */ 1558 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1559 u32 gpio_val = i40e_led_is_mine(hw, i); 1560 1561 if (!gpio_val) 1562 continue; 1563 1564 /* ignore gpio LED src mode entries related to the activity 1565 * LEDs 1566 */ 1567 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1568 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1569 switch (current_mode) { 1570 case I40E_COMBINED_ACTIVITY: 1571 case I40E_FILTER_ACTIVITY: 1572 case I40E_MAC_ACTIVITY: 1573 case I40E_LINK_ACTIVITY: 1574 continue; 1575 default: 1576 break; 1577 } 1578 1579 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1580 /* this & is a bit of paranoia, but serves as a range check */ 1581 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1582 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1583 1584 if (blink) 1585 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1586 else 1587 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1588 1589 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1590 break; 1591 } 1592 } 1593 1594 /* Admin command wrappers */ 1595 1596 /** 1597 * i40e_aq_get_phy_capabilities 1598 * @hw: pointer to the hw struct 1599 * @abilities: structure for PHY capabilities to be filled 1600 * @qualified_modules: report Qualified Modules 1601 * @report_init: report init capabilities (active are default) 1602 * @cmd_details: pointer to command details structure or NULL 1603 * 1604 * Returns the various PHY abilities supported on the Port. 1605 **/ 1606 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1607 bool qualified_modules, bool report_init, 1608 struct i40e_aq_get_phy_abilities_resp *abilities, 1609 struct i40e_asq_cmd_details *cmd_details) 1610 { 1611 struct i40e_aq_desc desc; 1612 enum i40e_status_code status; 1613 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1614 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1615 1616 if (!abilities) 1617 return I40E_ERR_PARAM; 1618 1619 do { 1620 i40e_fill_default_direct_cmd_desc(&desc, 1621 i40e_aqc_opc_get_phy_abilities); 1622 1623 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1624 if (abilities_size > I40E_AQ_LARGE_BUF) 1625 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1626 1627 if (qualified_modules) 1628 desc.params.external.param0 |= 1629 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1630 1631 if (report_init) 1632 desc.params.external.param0 |= 1633 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1634 1635 status = i40e_asq_send_command(hw, &desc, abilities, 1636 abilities_size, cmd_details); 1637 1638 if (status != I40E_SUCCESS) 1639 break; 1640 1641 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { 1642 status = I40E_ERR_UNKNOWN_PHY; 1643 break; 1644 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { 1645 i40e_msec_delay(1); 1646 total_delay++; 1647 status = I40E_ERR_TIMEOUT; 1648 } 1649 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && 1650 (total_delay < max_delay)); 1651 1652 if (status != I40E_SUCCESS) 1653 return status; 1654 1655 if (report_init) { 1656 if (hw->mac.type == I40E_MAC_XL710 && 1657 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1658 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1659 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 1660 } else { 1661 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1662 hw->phy.phy_types |= 1663 ((u64)abilities->phy_type_ext << 32); 1664 } 1665 } 1666 1667 return status; 1668 } 1669 1670 /** 1671 * i40e_aq_set_phy_config 1672 * @hw: pointer to the hw struct 1673 * @config: structure with PHY configuration to be set 1674 * @cmd_details: pointer to command details structure or NULL 1675 * 1676 * Set the various PHY configuration parameters 1677 * supported on the Port.One or more of the Set PHY config parameters may be 1678 * ignored in an MFP mode as the PF may not have the privilege to set some 1679 * of the PHY Config parameters. This status will be indicated by the 1680 * command response. 1681 **/ 1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1683 struct i40e_aq_set_phy_config *config, 1684 struct i40e_asq_cmd_details *cmd_details) 1685 { 1686 struct i40e_aq_desc desc; 1687 struct i40e_aq_set_phy_config *cmd = 1688 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1689 enum i40e_status_code status; 1690 1691 if (!config) 1692 return I40E_ERR_PARAM; 1693 1694 i40e_fill_default_direct_cmd_desc(&desc, 1695 i40e_aqc_opc_set_phy_config); 1696 1697 *cmd = *config; 1698 1699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1700 1701 return status; 1702 } 1703 1704 /** 1705 * i40e_set_fc 1706 * @hw: pointer to the hw struct 1707 * @aq_failures: buffer to return AdminQ failure information 1708 * @atomic_restart: whether to enable atomic link restart 1709 * 1710 * Set the requested flow control mode using set_phy_config. 1711 **/ 1712 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1713 bool atomic_restart) 1714 { 1715 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1716 struct i40e_aq_get_phy_abilities_resp abilities; 1717 struct i40e_aq_set_phy_config config; 1718 enum i40e_status_code status; 1719 u8 pause_mask = 0x0; 1720 1721 *aq_failures = 0x0; 1722 1723 switch (fc_mode) { 1724 case I40E_FC_FULL: 1725 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1726 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1727 break; 1728 case I40E_FC_RX_PAUSE: 1729 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1730 break; 1731 case I40E_FC_TX_PAUSE: 1732 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1733 break; 1734 default: 1735 break; 1736 } 1737 1738 /* Get the current phy config */ 1739 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1740 NULL); 1741 if (status) { 1742 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1743 return status; 1744 } 1745 1746 memset(&config, 0, sizeof(config)); 1747 /* clear the old pause settings */ 1748 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1749 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1750 /* set the new abilities */ 1751 config.abilities |= pause_mask; 1752 /* If the abilities have changed, then set the new config */ 1753 if (config.abilities != abilities.abilities) { 1754 /* Auto restart link so settings take effect */ 1755 if (atomic_restart) 1756 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1757 /* Copy over all the old settings */ 1758 config.phy_type = abilities.phy_type; 1759 config.phy_type_ext = abilities.phy_type_ext; 1760 config.link_speed = abilities.link_speed; 1761 config.eee_capability = abilities.eee_capability; 1762 config.eeer = abilities.eeer_val; 1763 config.low_power_ctrl = abilities.d3_lpan; 1764 config.fec_config = abilities.fec_cfg_curr_mod_ext_info & 1765 I40E_AQ_PHY_FEC_CONFIG_MASK; 1766 status = i40e_aq_set_phy_config(hw, &config, NULL); 1767 1768 if (status) 1769 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1770 } 1771 /* Update the link info */ 1772 status = i40e_update_link_info(hw); 1773 if (status) { 1774 /* Wait a little bit (on 40G cards it sometimes takes a really 1775 * long time for link to come back from the atomic reset) 1776 * and try once more 1777 */ 1778 i40e_msec_delay(1000); 1779 status = i40e_update_link_info(hw); 1780 } 1781 if (status) 1782 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1783 1784 return status; 1785 } 1786 1787 /** 1788 * i40e_aq_set_mac_config 1789 * @hw: pointer to the hw struct 1790 * @max_frame_size: Maximum Frame Size to be supported by the port 1791 * @crc_en: Tell HW to append a CRC to outgoing frames 1792 * @pacing: Pacing configurations 1793 * @cmd_details: pointer to command details structure or NULL 1794 * 1795 * Configure MAC settings for frame size, jumbo frame support and the 1796 * addition of a CRC by the hardware. 1797 **/ 1798 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1799 u16 max_frame_size, 1800 bool crc_en, u16 pacing, 1801 struct i40e_asq_cmd_details *cmd_details) 1802 { 1803 struct i40e_aq_desc desc; 1804 struct i40e_aq_set_mac_config *cmd = 1805 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1806 enum i40e_status_code status; 1807 1808 if (max_frame_size == 0) 1809 return I40E_ERR_PARAM; 1810 1811 i40e_fill_default_direct_cmd_desc(&desc, 1812 i40e_aqc_opc_set_mac_config); 1813 1814 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1815 cmd->params = ((u8)pacing & 0x0F) << 3; 1816 if (crc_en) 1817 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1818 1819 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1820 1821 return status; 1822 } 1823 1824 /** 1825 * i40e_aq_clear_pxe_mode 1826 * @hw: pointer to the hw struct 1827 * @cmd_details: pointer to command details structure or NULL 1828 * 1829 * Tell the firmware that the driver is taking over from PXE 1830 **/ 1831 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1832 struct i40e_asq_cmd_details *cmd_details) 1833 { 1834 enum i40e_status_code status; 1835 struct i40e_aq_desc desc; 1836 struct i40e_aqc_clear_pxe *cmd = 1837 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1838 1839 i40e_fill_default_direct_cmd_desc(&desc, 1840 i40e_aqc_opc_clear_pxe_mode); 1841 1842 cmd->rx_cnt = 0x2; 1843 1844 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1845 1846 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1847 1848 return status; 1849 } 1850 1851 /** 1852 * i40e_aq_set_link_restart_an 1853 * @hw: pointer to the hw struct 1854 * @enable_link: if TRUE: enable link, if FALSE: disable link 1855 * @cmd_details: pointer to command details structure or NULL 1856 * 1857 * Sets up the link and restarts the Auto-Negotiation over the link. 1858 **/ 1859 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1860 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1861 { 1862 struct i40e_aq_desc desc; 1863 struct i40e_aqc_set_link_restart_an *cmd = 1864 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1865 enum i40e_status_code status; 1866 1867 i40e_fill_default_direct_cmd_desc(&desc, 1868 i40e_aqc_opc_set_link_restart_an); 1869 1870 cmd->command = I40E_AQ_PHY_RESTART_AN; 1871 if (enable_link) 1872 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1873 else 1874 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1875 1876 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1877 1878 return status; 1879 } 1880 1881 /** 1882 * i40e_aq_get_link_info 1883 * @hw: pointer to the hw struct 1884 * @enable_lse: enable/disable LinkStatusEvent reporting 1885 * @link: pointer to link status structure - optional 1886 * @cmd_details: pointer to command details structure or NULL 1887 * 1888 * Returns the link status of the adapter. 1889 **/ 1890 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1891 bool enable_lse, struct i40e_link_status *link, 1892 struct i40e_asq_cmd_details *cmd_details) 1893 { 1894 struct i40e_aq_desc desc; 1895 struct i40e_aqc_get_link_status *resp = 1896 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1897 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1898 enum i40e_status_code status; 1899 bool tx_pause, rx_pause; 1900 u16 command_flags; 1901 1902 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1903 1904 if (enable_lse) 1905 command_flags = I40E_AQ_LSE_ENABLE; 1906 else 1907 command_flags = I40E_AQ_LSE_DISABLE; 1908 resp->command_flags = CPU_TO_LE16(command_flags); 1909 1910 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1911 1912 if (status != I40E_SUCCESS) 1913 goto aq_get_link_info_exit; 1914 1915 /* save off old link status information */ 1916 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1917 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1918 1919 /* update link status */ 1920 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1921 hw->phy.media_type = i40e_get_media_type(hw); 1922 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1923 hw_link_info->link_info = resp->link_info; 1924 hw_link_info->an_info = resp->an_info; 1925 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | 1926 I40E_AQ_CONFIG_FEC_RS_ENA); 1927 hw_link_info->ext_info = resp->ext_info; 1928 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1929 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1930 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1931 1932 /* update fc info */ 1933 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1934 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1935 if (tx_pause & rx_pause) 1936 hw->fc.current_mode = I40E_FC_FULL; 1937 else if (tx_pause) 1938 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1939 else if (rx_pause) 1940 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1941 else 1942 hw->fc.current_mode = I40E_FC_NONE; 1943 1944 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1945 hw_link_info->crc_enable = TRUE; 1946 else 1947 hw_link_info->crc_enable = FALSE; 1948 1949 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 1950 hw_link_info->lse_enable = TRUE; 1951 else 1952 hw_link_info->lse_enable = FALSE; 1953 1954 if ((hw->mac.type == I40E_MAC_XL710) && 1955 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1956 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1957 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1958 1959 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1960 hw->aq.api_min_ver >= 7) { 1961 __le32 tmp; 1962 1963 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), 1964 I40E_NONDMA_TO_NONDMA); 1965 hw->phy.phy_types = LE32_TO_CPU(tmp); 1966 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1967 } 1968 1969 /* save link status information */ 1970 if (link) 1971 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1972 I40E_NONDMA_TO_NONDMA); 1973 1974 /* flag cleared so helper functions don't call AQ again */ 1975 hw->phy.get_link_info = FALSE; 1976 1977 aq_get_link_info_exit: 1978 return status; 1979 } 1980 1981 /** 1982 * i40e_aq_set_phy_int_mask 1983 * @hw: pointer to the hw struct 1984 * @mask: interrupt mask to be set 1985 * @cmd_details: pointer to command details structure or NULL 1986 * 1987 * Set link interrupt mask. 1988 **/ 1989 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1990 u16 mask, 1991 struct i40e_asq_cmd_details *cmd_details) 1992 { 1993 struct i40e_aq_desc desc; 1994 struct i40e_aqc_set_phy_int_mask *cmd = 1995 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1996 enum i40e_status_code status; 1997 1998 i40e_fill_default_direct_cmd_desc(&desc, 1999 i40e_aqc_opc_set_phy_int_mask); 2000 2001 cmd->event_mask = CPU_TO_LE16(mask); 2002 2003 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2004 2005 return status; 2006 } 2007 2008 /** 2009 * i40e_aq_get_local_advt_reg 2010 * @hw: pointer to the hw struct 2011 * @advt_reg: local AN advertisement register value 2012 * @cmd_details: pointer to command details structure or NULL 2013 * 2014 * Get the Local AN advertisement register value. 2015 **/ 2016 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 2017 u64 *advt_reg, 2018 struct i40e_asq_cmd_details *cmd_details) 2019 { 2020 struct i40e_aq_desc desc; 2021 struct i40e_aqc_an_advt_reg *resp = 2022 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2023 enum i40e_status_code status; 2024 2025 i40e_fill_default_direct_cmd_desc(&desc, 2026 i40e_aqc_opc_get_local_advt_reg); 2027 2028 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2029 2030 if (status != I40E_SUCCESS) 2031 goto aq_get_local_advt_reg_exit; 2032 2033 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2034 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2035 2036 aq_get_local_advt_reg_exit: 2037 return status; 2038 } 2039 2040 /** 2041 * i40e_aq_set_local_advt_reg 2042 * @hw: pointer to the hw struct 2043 * @advt_reg: local AN advertisement register value 2044 * @cmd_details: pointer to command details structure or NULL 2045 * 2046 * Get the Local AN advertisement register value. 2047 **/ 2048 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2049 u64 advt_reg, 2050 struct i40e_asq_cmd_details *cmd_details) 2051 { 2052 struct i40e_aq_desc desc; 2053 struct i40e_aqc_an_advt_reg *cmd = 2054 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2055 enum i40e_status_code status; 2056 2057 i40e_fill_default_direct_cmd_desc(&desc, 2058 i40e_aqc_opc_get_local_advt_reg); 2059 2060 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2061 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2062 2063 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2064 2065 return status; 2066 } 2067 2068 /** 2069 * i40e_aq_get_partner_advt 2070 * @hw: pointer to the hw struct 2071 * @advt_reg: AN partner advertisement register value 2072 * @cmd_details: pointer to command details structure or NULL 2073 * 2074 * Get the link partner AN advertisement register value. 2075 **/ 2076 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2077 u64 *advt_reg, 2078 struct i40e_asq_cmd_details *cmd_details) 2079 { 2080 struct i40e_aq_desc desc; 2081 struct i40e_aqc_an_advt_reg *resp = 2082 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2083 enum i40e_status_code status; 2084 2085 i40e_fill_default_direct_cmd_desc(&desc, 2086 i40e_aqc_opc_get_partner_advt); 2087 2088 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2089 2090 if (status != I40E_SUCCESS) 2091 goto aq_get_partner_advt_exit; 2092 2093 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2094 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2095 2096 aq_get_partner_advt_exit: 2097 return status; 2098 } 2099 2100 /** 2101 * i40e_aq_set_lb_modes 2102 * @hw: pointer to the hw struct 2103 * @lb_modes: loopback mode to be set 2104 * @cmd_details: pointer to command details structure or NULL 2105 * 2106 * Sets loopback modes. 2107 **/ 2108 enum i40e_status_code 2109 i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed, 2110 struct i40e_asq_cmd_details *cmd_details) 2111 { 2112 struct i40e_aq_desc desc; 2113 struct i40e_aqc_set_lb_mode *cmd = 2114 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2115 enum i40e_status_code status; 2116 2117 i40e_fill_default_direct_cmd_desc(&desc, 2118 i40e_aqc_opc_set_lb_modes); 2119 2120 cmd->lb_level = lb_level; 2121 cmd->lb_type = lb_type; 2122 cmd->speed = speed; 2123 if (speed) 2124 cmd->force_speed = 1; 2125 2126 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2127 2128 return status; 2129 } 2130 2131 /** 2132 * i40e_aq_set_phy_debug 2133 * @hw: pointer to the hw struct 2134 * @cmd_flags: debug command flags 2135 * @cmd_details: pointer to command details structure or NULL 2136 * 2137 * Reset the external PHY. 2138 **/ 2139 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2140 struct i40e_asq_cmd_details *cmd_details) 2141 { 2142 struct i40e_aq_desc desc; 2143 struct i40e_aqc_set_phy_debug *cmd = 2144 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2145 enum i40e_status_code status; 2146 2147 i40e_fill_default_direct_cmd_desc(&desc, 2148 i40e_aqc_opc_set_phy_debug); 2149 2150 cmd->command_flags = cmd_flags; 2151 2152 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2153 2154 return status; 2155 } 2156 2157 /** 2158 * i40e_aq_add_vsi 2159 * @hw: pointer to the hw struct 2160 * @vsi_ctx: pointer to a vsi context struct 2161 * @cmd_details: pointer to command details structure or NULL 2162 * 2163 * Add a VSI context to the hardware. 2164 **/ 2165 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2166 struct i40e_vsi_context *vsi_ctx, 2167 struct i40e_asq_cmd_details *cmd_details) 2168 { 2169 struct i40e_aq_desc desc; 2170 struct i40e_aqc_add_get_update_vsi *cmd = 2171 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2172 struct i40e_aqc_add_get_update_vsi_completion *resp = 2173 (struct i40e_aqc_add_get_update_vsi_completion *) 2174 &desc.params.raw; 2175 enum i40e_status_code status; 2176 2177 i40e_fill_default_direct_cmd_desc(&desc, 2178 i40e_aqc_opc_add_vsi); 2179 2180 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2181 cmd->connection_type = vsi_ctx->connection_type; 2182 cmd->vf_id = vsi_ctx->vf_num; 2183 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2184 2185 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2186 2187 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2188 sizeof(vsi_ctx->info), cmd_details); 2189 2190 if (status != I40E_SUCCESS) 2191 goto aq_add_vsi_exit; 2192 2193 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2194 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2195 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2196 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2197 2198 aq_add_vsi_exit: 2199 return status; 2200 } 2201 2202 /** 2203 * i40e_aq_set_default_vsi 2204 * @hw: pointer to the hw struct 2205 * @seid: vsi number 2206 * @cmd_details: pointer to command details structure or NULL 2207 **/ 2208 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2209 u16 seid, 2210 struct i40e_asq_cmd_details *cmd_details) 2211 { 2212 struct i40e_aq_desc desc; 2213 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2214 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2215 &desc.params.raw; 2216 enum i40e_status_code status; 2217 2218 i40e_fill_default_direct_cmd_desc(&desc, 2219 i40e_aqc_opc_set_vsi_promiscuous_modes); 2220 2221 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2222 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2223 cmd->seid = CPU_TO_LE16(seid); 2224 2225 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2226 2227 return status; 2228 } 2229 2230 /** 2231 * i40e_aq_clear_default_vsi 2232 * @hw: pointer to the hw struct 2233 * @seid: vsi number 2234 * @cmd_details: pointer to command details structure or NULL 2235 **/ 2236 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2237 u16 seid, 2238 struct i40e_asq_cmd_details *cmd_details) 2239 { 2240 struct i40e_aq_desc desc; 2241 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2242 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2243 &desc.params.raw; 2244 enum i40e_status_code status; 2245 2246 i40e_fill_default_direct_cmd_desc(&desc, 2247 i40e_aqc_opc_set_vsi_promiscuous_modes); 2248 2249 cmd->promiscuous_flags = CPU_TO_LE16(0); 2250 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2251 cmd->seid = CPU_TO_LE16(seid); 2252 2253 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2254 2255 return status; 2256 } 2257 2258 /** 2259 * i40e_aq_set_vsi_unicast_promiscuous 2260 * @hw: pointer to the hw struct 2261 * @seid: vsi number 2262 * @set: set unicast promiscuous enable/disable 2263 * @cmd_details: pointer to command details structure or NULL 2264 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2265 **/ 2266 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2267 u16 seid, bool set, 2268 struct i40e_asq_cmd_details *cmd_details, 2269 bool rx_only_promisc) 2270 { 2271 struct i40e_aq_desc desc; 2272 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2273 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2274 enum i40e_status_code status; 2275 u16 flags = 0; 2276 2277 i40e_fill_default_direct_cmd_desc(&desc, 2278 i40e_aqc_opc_set_vsi_promiscuous_modes); 2279 2280 if (set) { 2281 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2282 if (rx_only_promisc && 2283 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2284 (hw->aq.api_maj_ver > 1))) 2285 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2286 } 2287 2288 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2289 2290 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2291 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2292 (hw->aq.api_maj_ver > 1)) 2293 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2294 2295 cmd->seid = CPU_TO_LE16(seid); 2296 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2297 2298 return status; 2299 } 2300 2301 /** 2302 * i40e_aq_set_vsi_multicast_promiscuous 2303 * @hw: pointer to the hw struct 2304 * @seid: vsi number 2305 * @set: set multicast promiscuous enable/disable 2306 * @cmd_details: pointer to command details structure or NULL 2307 **/ 2308 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2309 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2310 { 2311 struct i40e_aq_desc desc; 2312 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2313 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2314 enum i40e_status_code status; 2315 u16 flags = 0; 2316 2317 i40e_fill_default_direct_cmd_desc(&desc, 2318 i40e_aqc_opc_set_vsi_promiscuous_modes); 2319 2320 if (set) 2321 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2322 2323 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2324 2325 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2326 2327 cmd->seid = CPU_TO_LE16(seid); 2328 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2329 2330 return status; 2331 } 2332 2333 /** 2334 * i40e_aq_set_vsi_mc_promisc_on_vlan 2335 * @hw: pointer to the hw struct 2336 * @seid: vsi number 2337 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2338 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2339 * @cmd_details: pointer to command details structure or NULL 2340 **/ 2341 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2342 u16 seid, bool enable, u16 vid, 2343 struct i40e_asq_cmd_details *cmd_details) 2344 { 2345 struct i40e_aq_desc desc; 2346 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2347 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2348 enum i40e_status_code status; 2349 u16 flags = 0; 2350 2351 i40e_fill_default_direct_cmd_desc(&desc, 2352 i40e_aqc_opc_set_vsi_promiscuous_modes); 2353 2354 if (enable) 2355 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2356 2357 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2358 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2359 cmd->seid = CPU_TO_LE16(seid); 2360 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2361 2362 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2363 2364 return status; 2365 } 2366 2367 /** 2368 * i40e_aq_set_vsi_uc_promisc_on_vlan 2369 * @hw: pointer to the hw struct 2370 * @seid: vsi number 2371 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2372 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2373 * @cmd_details: pointer to command details structure or NULL 2374 **/ 2375 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2376 u16 seid, bool enable, u16 vid, 2377 struct i40e_asq_cmd_details *cmd_details) 2378 { 2379 struct i40e_aq_desc desc; 2380 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2381 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2382 enum i40e_status_code status; 2383 u16 flags = 0; 2384 2385 i40e_fill_default_direct_cmd_desc(&desc, 2386 i40e_aqc_opc_set_vsi_promiscuous_modes); 2387 2388 if (enable) 2389 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2390 2391 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2392 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2393 cmd->seid = CPU_TO_LE16(seid); 2394 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2395 2396 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2397 2398 return status; 2399 } 2400 2401 /** 2402 * i40e_aq_set_vsi_bc_promisc_on_vlan 2403 * @hw: pointer to the hw struct 2404 * @seid: vsi number 2405 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2406 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2407 * @cmd_details: pointer to command details structure or NULL 2408 **/ 2409 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2410 u16 seid, bool enable, u16 vid, 2411 struct i40e_asq_cmd_details *cmd_details) 2412 { 2413 struct i40e_aq_desc desc; 2414 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2415 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2416 enum i40e_status_code status; 2417 u16 flags = 0; 2418 2419 i40e_fill_default_direct_cmd_desc(&desc, 2420 i40e_aqc_opc_set_vsi_promiscuous_modes); 2421 2422 if (enable) 2423 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2424 2425 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2426 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2427 cmd->seid = CPU_TO_LE16(seid); 2428 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2429 2430 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2431 2432 return status; 2433 } 2434 2435 /** 2436 * i40e_aq_set_vsi_broadcast 2437 * @hw: pointer to the hw struct 2438 * @seid: vsi number 2439 * @set_filter: TRUE to set filter, FALSE to clear filter 2440 * @cmd_details: pointer to command details structure or NULL 2441 * 2442 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2443 **/ 2444 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2445 u16 seid, bool set_filter, 2446 struct i40e_asq_cmd_details *cmd_details) 2447 { 2448 struct i40e_aq_desc desc; 2449 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2450 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2451 enum i40e_status_code status; 2452 2453 i40e_fill_default_direct_cmd_desc(&desc, 2454 i40e_aqc_opc_set_vsi_promiscuous_modes); 2455 2456 if (set_filter) 2457 cmd->promiscuous_flags 2458 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2459 else 2460 cmd->promiscuous_flags 2461 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2462 2463 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2464 cmd->seid = CPU_TO_LE16(seid); 2465 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2466 2467 return status; 2468 } 2469 2470 /** 2471 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2472 * @hw: pointer to the hw struct 2473 * @seid: vsi number 2474 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2475 * @cmd_details: pointer to command details structure or NULL 2476 **/ 2477 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2478 u16 seid, bool enable, 2479 struct i40e_asq_cmd_details *cmd_details) 2480 { 2481 struct i40e_aq_desc desc; 2482 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2483 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2484 enum i40e_status_code status; 2485 u16 flags = 0; 2486 2487 i40e_fill_default_direct_cmd_desc(&desc, 2488 i40e_aqc_opc_set_vsi_promiscuous_modes); 2489 if (enable) 2490 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2491 2492 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2493 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2494 cmd->seid = CPU_TO_LE16(seid); 2495 2496 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2497 2498 return status; 2499 } 2500 2501 /** 2502 * i40e_get_vsi_params - get VSI configuration info 2503 * @hw: pointer to the hw struct 2504 * @vsi_ctx: pointer to a vsi context struct 2505 * @cmd_details: pointer to command details structure or NULL 2506 **/ 2507 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2508 struct i40e_vsi_context *vsi_ctx, 2509 struct i40e_asq_cmd_details *cmd_details) 2510 { 2511 struct i40e_aq_desc desc; 2512 struct i40e_aqc_add_get_update_vsi *cmd = 2513 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2514 struct i40e_aqc_add_get_update_vsi_completion *resp = 2515 (struct i40e_aqc_add_get_update_vsi_completion *) 2516 &desc.params.raw; 2517 enum i40e_status_code status; 2518 2519 i40e_fill_default_direct_cmd_desc(&desc, 2520 i40e_aqc_opc_get_vsi_parameters); 2521 2522 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2523 2524 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2525 2526 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2527 sizeof(vsi_ctx->info), NULL); 2528 2529 if (status != I40E_SUCCESS) 2530 goto aq_get_vsi_params_exit; 2531 2532 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2533 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2534 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2535 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2536 2537 aq_get_vsi_params_exit: 2538 return status; 2539 } 2540 2541 /** 2542 * i40e_aq_update_vsi_params 2543 * @hw: pointer to the hw struct 2544 * @vsi_ctx: pointer to a vsi context struct 2545 * @cmd_details: pointer to command details structure or NULL 2546 * 2547 * Update a VSI context. 2548 **/ 2549 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2550 struct i40e_vsi_context *vsi_ctx, 2551 struct i40e_asq_cmd_details *cmd_details) 2552 { 2553 struct i40e_aq_desc desc; 2554 struct i40e_aqc_add_get_update_vsi *cmd = 2555 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2556 struct i40e_aqc_add_get_update_vsi_completion *resp = 2557 (struct i40e_aqc_add_get_update_vsi_completion *) 2558 &desc.params.raw; 2559 enum i40e_status_code status; 2560 2561 i40e_fill_default_direct_cmd_desc(&desc, 2562 i40e_aqc_opc_update_vsi_parameters); 2563 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2564 2565 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2566 2567 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2568 sizeof(vsi_ctx->info), cmd_details); 2569 2570 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2571 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2572 2573 return status; 2574 } 2575 2576 /** 2577 * i40e_aq_get_switch_config 2578 * @hw: pointer to the hardware structure 2579 * @buf: pointer to the result buffer 2580 * @buf_size: length of input buffer 2581 * @start_seid: seid to start for the report, 0 == beginning 2582 * @cmd_details: pointer to command details structure or NULL 2583 * 2584 * Fill the buf with switch configuration returned from AdminQ command 2585 **/ 2586 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2587 struct i40e_aqc_get_switch_config_resp *buf, 2588 u16 buf_size, u16 *start_seid, 2589 struct i40e_asq_cmd_details *cmd_details) 2590 { 2591 struct i40e_aq_desc desc; 2592 struct i40e_aqc_switch_seid *scfg = 2593 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2594 enum i40e_status_code status; 2595 2596 i40e_fill_default_direct_cmd_desc(&desc, 2597 i40e_aqc_opc_get_switch_config); 2598 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2599 if (buf_size > I40E_AQ_LARGE_BUF) 2600 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2601 scfg->seid = CPU_TO_LE16(*start_seid); 2602 2603 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2604 *start_seid = LE16_TO_CPU(scfg->seid); 2605 2606 return status; 2607 } 2608 2609 /** 2610 * i40e_aq_set_switch_config 2611 * @hw: pointer to the hardware structure 2612 * @flags: bit flag values to set 2613 * @mode: cloud filter mode 2614 * @valid_flags: which bit flags to set 2615 * @cmd_details: pointer to command details structure or NULL 2616 * 2617 * Set switch configuration bits 2618 **/ 2619 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2620 u16 flags, u16 valid_flags, u8 mode, 2621 struct i40e_asq_cmd_details *cmd_details) 2622 { 2623 struct i40e_aq_desc desc; 2624 struct i40e_aqc_set_switch_config *scfg = 2625 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2626 enum i40e_status_code status; 2627 2628 i40e_fill_default_direct_cmd_desc(&desc, 2629 i40e_aqc_opc_set_switch_config); 2630 scfg->flags = CPU_TO_LE16(flags); 2631 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2632 scfg->mode = mode; 2633 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2634 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag); 2635 scfg->first_tag = CPU_TO_LE16(hw->first_tag); 2636 scfg->second_tag = CPU_TO_LE16(hw->second_tag); 2637 } 2638 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2639 2640 return status; 2641 } 2642 2643 /** 2644 * i40e_aq_get_firmware_version 2645 * @hw: pointer to the hw struct 2646 * @fw_major_version: firmware major version 2647 * @fw_minor_version: firmware minor version 2648 * @fw_build: firmware build number 2649 * @api_major_version: major queue version 2650 * @api_minor_version: minor queue version 2651 * @cmd_details: pointer to command details structure or NULL 2652 * 2653 * Get the firmware version from the admin queue commands 2654 **/ 2655 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2656 u16 *fw_major_version, u16 *fw_minor_version, 2657 u32 *fw_build, 2658 u16 *api_major_version, u16 *api_minor_version, 2659 struct i40e_asq_cmd_details *cmd_details) 2660 { 2661 struct i40e_aq_desc desc; 2662 struct i40e_aqc_get_version *resp = 2663 (struct i40e_aqc_get_version *)&desc.params.raw; 2664 enum i40e_status_code status; 2665 2666 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2667 2668 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2669 2670 if (status == I40E_SUCCESS) { 2671 if (fw_major_version != NULL) 2672 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2673 if (fw_minor_version != NULL) 2674 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2675 if (fw_build != NULL) 2676 *fw_build = LE32_TO_CPU(resp->fw_build); 2677 if (api_major_version != NULL) 2678 *api_major_version = LE16_TO_CPU(resp->api_major); 2679 if (api_minor_version != NULL) 2680 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2681 2682 /* A workaround to fix the API version in SW */ 2683 if (api_major_version && api_minor_version && 2684 fw_major_version && fw_minor_version && 2685 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2686 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2687 (*fw_major_version > 4))) 2688 *api_minor_version = 2; 2689 } 2690 2691 return status; 2692 } 2693 2694 /** 2695 * i40e_aq_send_driver_version 2696 * @hw: pointer to the hw struct 2697 * @dv: driver's major, minor version 2698 * @cmd_details: pointer to command details structure or NULL 2699 * 2700 * Send the driver version to the firmware 2701 **/ 2702 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2703 struct i40e_driver_version *dv, 2704 struct i40e_asq_cmd_details *cmd_details) 2705 { 2706 struct i40e_aq_desc desc; 2707 struct i40e_aqc_driver_version *cmd = 2708 (struct i40e_aqc_driver_version *)&desc.params.raw; 2709 enum i40e_status_code status; 2710 u16 len; 2711 2712 if (dv == NULL) 2713 return I40E_ERR_PARAM; 2714 2715 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2716 2717 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2718 cmd->driver_major_ver = dv->major_version; 2719 cmd->driver_minor_ver = dv->minor_version; 2720 cmd->driver_build_ver = dv->build_version; 2721 cmd->driver_subbuild_ver = dv->subbuild_version; 2722 2723 len = 0; 2724 while (len < sizeof(dv->driver_string) && 2725 (dv->driver_string[len] < 0x80) && 2726 dv->driver_string[len]) 2727 len++; 2728 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2729 len, cmd_details); 2730 2731 return status; 2732 } 2733 2734 /** 2735 * i40e_get_link_status - get status of the HW network link 2736 * @hw: pointer to the hw struct 2737 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2738 * 2739 * Variable link_up TRUE if link is up, FALSE if link is down. 2740 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2741 * 2742 * Side effect: LinkStatusEvent reporting becomes enabled 2743 **/ 2744 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2745 { 2746 enum i40e_status_code status = I40E_SUCCESS; 2747 2748 if (hw->phy.get_link_info) { 2749 status = i40e_update_link_info(hw); 2750 2751 if (status != I40E_SUCCESS) 2752 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2753 status); 2754 } 2755 2756 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2757 2758 return status; 2759 } 2760 2761 /** 2762 * i40e_updatelink_status - update status of the HW network link 2763 * @hw: pointer to the hw struct 2764 **/ 2765 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2766 { 2767 struct i40e_aq_get_phy_abilities_resp abilities; 2768 enum i40e_status_code status = I40E_SUCCESS; 2769 2770 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2771 if (status) 2772 return status; 2773 2774 /* extra checking needed to ensure link info to user is timely */ 2775 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2776 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2777 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2778 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 2779 &abilities, NULL); 2780 if (status) 2781 return status; 2782 2783 hw->phy.link_info.req_fec_info = 2784 abilities.fec_cfg_curr_mod_ext_info & 2785 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2786 2787 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2788 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2789 } 2790 return status; 2791 } 2792 2793 2794 /** 2795 * i40e_get_link_speed 2796 * @hw: pointer to the hw struct 2797 * 2798 * Returns the link speed of the adapter. 2799 **/ 2800 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2801 { 2802 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2803 enum i40e_status_code status = I40E_SUCCESS; 2804 2805 if (hw->phy.get_link_info) { 2806 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2807 2808 if (status != I40E_SUCCESS) 2809 goto i40e_link_speed_exit; 2810 } 2811 2812 speed = hw->phy.link_info.link_speed; 2813 2814 i40e_link_speed_exit: 2815 return speed; 2816 } 2817 2818 /** 2819 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2820 * @hw: pointer to the hw struct 2821 * @uplink_seid: the MAC or other gizmo SEID 2822 * @downlink_seid: the VSI SEID 2823 * @enabled_tc: bitmap of TCs to be enabled 2824 * @default_port: TRUE for default port VSI, FALSE for control port 2825 * @veb_seid: pointer to where to put the resulting VEB SEID 2826 * @enable_stats: TRUE to turn on VEB stats 2827 * @cmd_details: pointer to command details structure or NULL 2828 * 2829 * This asks the FW to add a VEB between the uplink and downlink 2830 * elements. If the uplink SEID is 0, this will be a floating VEB. 2831 **/ 2832 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2833 u16 downlink_seid, u8 enabled_tc, 2834 bool default_port, u16 *veb_seid, 2835 bool enable_stats, 2836 struct i40e_asq_cmd_details *cmd_details) 2837 { 2838 struct i40e_aq_desc desc; 2839 struct i40e_aqc_add_veb *cmd = 2840 (struct i40e_aqc_add_veb *)&desc.params.raw; 2841 struct i40e_aqc_add_veb_completion *resp = 2842 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2843 enum i40e_status_code status; 2844 u16 veb_flags = 0; 2845 2846 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2847 if (!!uplink_seid != !!downlink_seid) 2848 return I40E_ERR_PARAM; 2849 2850 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2851 2852 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2853 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2854 cmd->enable_tcs = enabled_tc; 2855 if (!uplink_seid) 2856 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2857 if (default_port) 2858 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2859 else 2860 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2861 2862 /* reverse logic here: set the bitflag to disable the stats */ 2863 if (!enable_stats) 2864 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2865 2866 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2867 2868 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2869 2870 if (!status && veb_seid) 2871 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2872 2873 return status; 2874 } 2875 2876 /** 2877 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2878 * @hw: pointer to the hw struct 2879 * @veb_seid: the SEID of the VEB to query 2880 * @switch_id: the uplink switch id 2881 * @floating: set to TRUE if the VEB is floating 2882 * @statistic_index: index of the stats counter block for this VEB 2883 * @vebs_used: number of VEB's used by function 2884 * @vebs_free: total VEB's not reserved by any function 2885 * @cmd_details: pointer to command details structure or NULL 2886 * 2887 * This retrieves the parameters for a particular VEB, specified by 2888 * uplink_seid, and returns them to the caller. 2889 **/ 2890 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2891 u16 veb_seid, u16 *switch_id, 2892 bool *floating, u16 *statistic_index, 2893 u16 *vebs_used, u16 *vebs_free, 2894 struct i40e_asq_cmd_details *cmd_details) 2895 { 2896 struct i40e_aq_desc desc; 2897 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2898 (struct i40e_aqc_get_veb_parameters_completion *) 2899 &desc.params.raw; 2900 enum i40e_status_code status; 2901 2902 if (veb_seid == 0) 2903 return I40E_ERR_PARAM; 2904 2905 i40e_fill_default_direct_cmd_desc(&desc, 2906 i40e_aqc_opc_get_veb_parameters); 2907 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2908 2909 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2910 if (status) 2911 goto get_veb_exit; 2912 2913 if (switch_id) 2914 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2915 if (statistic_index) 2916 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2917 if (vebs_used) 2918 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2919 if (vebs_free) 2920 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2921 if (floating) { 2922 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2923 2924 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2925 *floating = TRUE; 2926 else 2927 *floating = FALSE; 2928 } 2929 2930 get_veb_exit: 2931 return status; 2932 } 2933 2934 /** 2935 * i40e_aq_add_macvlan 2936 * @hw: pointer to the hw struct 2937 * @seid: VSI for the mac address 2938 * @mv_list: list of macvlans to be added 2939 * @count: length of the list 2940 * @cmd_details: pointer to command details structure or NULL 2941 * 2942 * Add MAC/VLAN addresses to the HW filtering 2943 **/ 2944 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2945 struct i40e_aqc_add_macvlan_element_data *mv_list, 2946 u16 count, struct i40e_asq_cmd_details *cmd_details) 2947 { 2948 struct i40e_aq_desc desc; 2949 struct i40e_aqc_macvlan *cmd = 2950 (struct i40e_aqc_macvlan *)&desc.params.raw; 2951 enum i40e_status_code status; 2952 u16 buf_size; 2953 int i; 2954 2955 if (count == 0 || !mv_list || !hw) 2956 return I40E_ERR_PARAM; 2957 2958 buf_size = count * sizeof(*mv_list); 2959 2960 /* prep the rest of the request */ 2961 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2962 cmd->num_addresses = CPU_TO_LE16(count); 2963 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2964 cmd->seid[1] = 0; 2965 cmd->seid[2] = 0; 2966 2967 for (i = 0; i < count; i++) 2968 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 2969 mv_list[i].flags |= 2970 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2971 2972 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2973 if (buf_size > I40E_AQ_LARGE_BUF) 2974 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2975 2976 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2977 cmd_details); 2978 2979 return status; 2980 } 2981 2982 /** 2983 * i40e_aq_remove_macvlan 2984 * @hw: pointer to the hw struct 2985 * @seid: VSI for the mac address 2986 * @mv_list: list of macvlans to be removed 2987 * @count: length of the list 2988 * @cmd_details: pointer to command details structure or NULL 2989 * 2990 * Remove MAC/VLAN addresses from the HW filtering 2991 **/ 2992 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2993 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2994 u16 count, struct i40e_asq_cmd_details *cmd_details) 2995 { 2996 struct i40e_aq_desc desc; 2997 struct i40e_aqc_macvlan *cmd = 2998 (struct i40e_aqc_macvlan *)&desc.params.raw; 2999 enum i40e_status_code status; 3000 u16 buf_size; 3001 3002 if (count == 0 || !mv_list || !hw) 3003 return I40E_ERR_PARAM; 3004 3005 buf_size = count * sizeof(*mv_list); 3006 3007 /* prep the rest of the request */ 3008 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 3009 cmd->num_addresses = CPU_TO_LE16(count); 3010 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3011 cmd->seid[1] = 0; 3012 cmd->seid[2] = 0; 3013 3014 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3015 if (buf_size > I40E_AQ_LARGE_BUF) 3016 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3017 3018 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3019 cmd_details); 3020 3021 return status; 3022 } 3023 3024 /** 3025 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 3026 * @hw: pointer to the hw struct 3027 * @opcode: AQ opcode for add or delete mirror rule 3028 * @sw_seid: Switch SEID (to which rule refers) 3029 * @rule_type: Rule Type (ingress/egress/VLAN) 3030 * @id: Destination VSI SEID or Rule ID 3031 * @count: length of the list 3032 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3033 * @cmd_details: pointer to command details structure or NULL 3034 * @rule_id: Rule ID returned from FW 3035 * @rules_used: Number of rules used in internal switch 3036 * @rules_free: Number of rules free in internal switch 3037 * 3038 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 3039 * VEBs/VEPA elements only 3040 **/ 3041 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 3042 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 3043 u16 count, __le16 *mr_list, 3044 struct i40e_asq_cmd_details *cmd_details, 3045 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3046 { 3047 struct i40e_aq_desc desc; 3048 struct i40e_aqc_add_delete_mirror_rule *cmd = 3049 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 3050 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 3051 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 3052 enum i40e_status_code status; 3053 u16 buf_size; 3054 3055 buf_size = count * sizeof(*mr_list); 3056 3057 /* prep the rest of the request */ 3058 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3059 cmd->seid = CPU_TO_LE16(sw_seid); 3060 cmd->rule_type = CPU_TO_LE16(rule_type & 3061 I40E_AQC_MIRROR_RULE_TYPE_MASK); 3062 cmd->num_entries = CPU_TO_LE16(count); 3063 /* Dest VSI for add, rule_id for delete */ 3064 cmd->destination = CPU_TO_LE16(id); 3065 if (mr_list) { 3066 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3067 I40E_AQ_FLAG_RD)); 3068 if (buf_size > I40E_AQ_LARGE_BUF) 3069 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3070 } 3071 3072 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3073 cmd_details); 3074 if (status == I40E_SUCCESS || 3075 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3076 if (rule_id) 3077 *rule_id = LE16_TO_CPU(resp->rule_id); 3078 if (rules_used) 3079 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3080 if (rules_free) 3081 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3082 } 3083 return status; 3084 } 3085 3086 /** 3087 * i40e_aq_add_mirrorrule - add a mirror rule 3088 * @hw: pointer to the hw struct 3089 * @sw_seid: Switch SEID (to which rule refers) 3090 * @rule_type: Rule Type (ingress/egress/VLAN) 3091 * @dest_vsi: SEID of VSI to which packets will be mirrored 3092 * @count: length of the list 3093 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3094 * @cmd_details: pointer to command details structure or NULL 3095 * @rule_id: Rule ID returned from FW 3096 * @rules_used: Number of rules used in internal switch 3097 * @rules_free: Number of rules free in internal switch 3098 * 3099 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3100 **/ 3101 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3102 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3103 struct i40e_asq_cmd_details *cmd_details, 3104 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3105 { 3106 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3107 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3108 if (count == 0 || !mr_list) 3109 return I40E_ERR_PARAM; 3110 } 3111 3112 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3113 rule_type, dest_vsi, count, mr_list, 3114 cmd_details, rule_id, rules_used, rules_free); 3115 } 3116 3117 /** 3118 * i40e_aq_delete_mirrorrule - delete a mirror rule 3119 * @hw: pointer to the hw struct 3120 * @sw_seid: Switch SEID (to which rule refers) 3121 * @rule_type: Rule Type (ingress/egress/VLAN) 3122 * @count: length of the list 3123 * @rule_id: Rule ID that is returned in the receive desc as part of 3124 * add_mirrorrule. 3125 * @mr_list: list of mirrored VLAN IDs to be removed 3126 * @cmd_details: pointer to command details structure or NULL 3127 * @rules_used: Number of rules used in internal switch 3128 * @rules_free: Number of rules free in internal switch 3129 * 3130 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3131 **/ 3132 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3133 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3134 struct i40e_asq_cmd_details *cmd_details, 3135 u16 *rules_used, u16 *rules_free) 3136 { 3137 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3138 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3139 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3140 * mirroring. For other rule_type, count and rule_type should 3141 * not matter. 3142 */ 3143 if (count == 0 || !mr_list) 3144 return I40E_ERR_PARAM; 3145 } 3146 3147 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3148 rule_type, rule_id, count, mr_list, 3149 cmd_details, NULL, rules_used, rules_free); 3150 } 3151 3152 /** 3153 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3154 * @hw: pointer to the hw struct 3155 * @seid: VSI for the vlan filters 3156 * @v_list: list of vlan filters to be added 3157 * @count: length of the list 3158 * @cmd_details: pointer to command details structure or NULL 3159 **/ 3160 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3161 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3162 u8 count, struct i40e_asq_cmd_details *cmd_details) 3163 { 3164 struct i40e_aq_desc desc; 3165 struct i40e_aqc_macvlan *cmd = 3166 (struct i40e_aqc_macvlan *)&desc.params.raw; 3167 enum i40e_status_code status; 3168 u16 buf_size; 3169 3170 if (count == 0 || !v_list || !hw) 3171 return I40E_ERR_PARAM; 3172 3173 buf_size = count * sizeof(*v_list); 3174 3175 /* prep the rest of the request */ 3176 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3177 cmd->num_addresses = CPU_TO_LE16(count); 3178 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3179 cmd->seid[1] = 0; 3180 cmd->seid[2] = 0; 3181 3182 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3183 if (buf_size > I40E_AQ_LARGE_BUF) 3184 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3185 3186 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3187 cmd_details); 3188 3189 return status; 3190 } 3191 3192 /** 3193 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3194 * @hw: pointer to the hw struct 3195 * @seid: VSI for the vlan filters 3196 * @v_list: list of macvlans to be removed 3197 * @count: length of the list 3198 * @cmd_details: pointer to command details structure or NULL 3199 **/ 3200 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3201 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3202 u8 count, struct i40e_asq_cmd_details *cmd_details) 3203 { 3204 struct i40e_aq_desc desc; 3205 struct i40e_aqc_macvlan *cmd = 3206 (struct i40e_aqc_macvlan *)&desc.params.raw; 3207 enum i40e_status_code status; 3208 u16 buf_size; 3209 3210 if (count == 0 || !v_list || !hw) 3211 return I40E_ERR_PARAM; 3212 3213 buf_size = count * sizeof(*v_list); 3214 3215 /* prep the rest of the request */ 3216 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3217 cmd->num_addresses = CPU_TO_LE16(count); 3218 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3219 cmd->seid[1] = 0; 3220 cmd->seid[2] = 0; 3221 3222 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3223 if (buf_size > I40E_AQ_LARGE_BUF) 3224 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3225 3226 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3227 cmd_details); 3228 3229 return status; 3230 } 3231 3232 /** 3233 * i40e_aq_send_msg_to_vf 3234 * @hw: pointer to the hardware structure 3235 * @vfid: vf id to send msg 3236 * @v_opcode: opcodes for VF-PF communication 3237 * @v_retval: return error code 3238 * @msg: pointer to the msg buffer 3239 * @msglen: msg length 3240 * @cmd_details: pointer to command details 3241 * 3242 * send msg to vf 3243 **/ 3244 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3245 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3246 struct i40e_asq_cmd_details *cmd_details) 3247 { 3248 struct i40e_aq_desc desc; 3249 struct i40e_aqc_pf_vf_message *cmd = 3250 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3251 enum i40e_status_code status; 3252 3253 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3254 cmd->id = CPU_TO_LE32(vfid); 3255 desc.cookie_high = CPU_TO_LE32(v_opcode); 3256 desc.cookie_low = CPU_TO_LE32(v_retval); 3257 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3258 if (msglen) { 3259 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3260 I40E_AQ_FLAG_RD)); 3261 if (msglen > I40E_AQ_LARGE_BUF) 3262 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3263 desc.datalen = CPU_TO_LE16(msglen); 3264 } 3265 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3266 3267 return status; 3268 } 3269 3270 /** 3271 * i40e_aq_debug_read_register 3272 * @hw: pointer to the hw struct 3273 * @reg_addr: register address 3274 * @reg_val: register value 3275 * @cmd_details: pointer to command details structure or NULL 3276 * 3277 * Read the register using the admin queue commands 3278 **/ 3279 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3280 u32 reg_addr, u64 *reg_val, 3281 struct i40e_asq_cmd_details *cmd_details) 3282 { 3283 struct i40e_aq_desc desc; 3284 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3285 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3286 enum i40e_status_code status; 3287 3288 if (reg_val == NULL) 3289 return I40E_ERR_PARAM; 3290 3291 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3292 3293 cmd_resp->address = CPU_TO_LE32(reg_addr); 3294 3295 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3296 3297 if (status == I40E_SUCCESS) { 3298 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3299 (u64)LE32_TO_CPU(cmd_resp->value_low); 3300 } 3301 3302 return status; 3303 } 3304 3305 /** 3306 * i40e_aq_debug_write_register 3307 * @hw: pointer to the hw struct 3308 * @reg_addr: register address 3309 * @reg_val: register value 3310 * @cmd_details: pointer to command details structure or NULL 3311 * 3312 * Write to a register using the admin queue commands 3313 **/ 3314 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3315 u32 reg_addr, u64 reg_val, 3316 struct i40e_asq_cmd_details *cmd_details) 3317 { 3318 struct i40e_aq_desc desc; 3319 struct i40e_aqc_debug_reg_read_write *cmd = 3320 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3321 enum i40e_status_code status; 3322 3323 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3324 3325 cmd->address = CPU_TO_LE32(reg_addr); 3326 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3327 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3328 3329 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3330 3331 return status; 3332 } 3333 3334 /** 3335 * i40e_aq_request_resource 3336 * @hw: pointer to the hw struct 3337 * @resource: resource id 3338 * @access: access type 3339 * @sdp_number: resource number 3340 * @timeout: the maximum time in ms that the driver may hold the resource 3341 * @cmd_details: pointer to command details structure or NULL 3342 * 3343 * requests common resource using the admin queue commands 3344 **/ 3345 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3346 enum i40e_aq_resources_ids resource, 3347 enum i40e_aq_resource_access_type access, 3348 u8 sdp_number, u64 *timeout, 3349 struct i40e_asq_cmd_details *cmd_details) 3350 { 3351 struct i40e_aq_desc desc; 3352 struct i40e_aqc_request_resource *cmd_resp = 3353 (struct i40e_aqc_request_resource *)&desc.params.raw; 3354 enum i40e_status_code status; 3355 3356 DEBUGFUNC("i40e_aq_request_resource"); 3357 3358 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3359 3360 cmd_resp->resource_id = CPU_TO_LE16(resource); 3361 cmd_resp->access_type = CPU_TO_LE16(access); 3362 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3363 3364 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3365 /* The completion specifies the maximum time in ms that the driver 3366 * may hold the resource in the Timeout field. 3367 * If the resource is held by someone else, the command completes with 3368 * busy return value and the timeout field indicates the maximum time 3369 * the current owner of the resource has to free it. 3370 */ 3371 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3372 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3373 3374 return status; 3375 } 3376 3377 /** 3378 * i40e_aq_release_resource 3379 * @hw: pointer to the hw struct 3380 * @resource: resource id 3381 * @sdp_number: resource number 3382 * @cmd_details: pointer to command details structure or NULL 3383 * 3384 * release common resource using the admin queue commands 3385 **/ 3386 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3387 enum i40e_aq_resources_ids resource, 3388 u8 sdp_number, 3389 struct i40e_asq_cmd_details *cmd_details) 3390 { 3391 struct i40e_aq_desc desc; 3392 struct i40e_aqc_request_resource *cmd = 3393 (struct i40e_aqc_request_resource *)&desc.params.raw; 3394 enum i40e_status_code status; 3395 3396 DEBUGFUNC("i40e_aq_release_resource"); 3397 3398 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3399 3400 cmd->resource_id = CPU_TO_LE16(resource); 3401 cmd->resource_number = CPU_TO_LE32(sdp_number); 3402 3403 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3404 3405 return status; 3406 } 3407 3408 /** 3409 * i40e_aq_read_nvm 3410 * @hw: pointer to the hw struct 3411 * @module_pointer: module pointer location in words from the NVM beginning 3412 * @offset: byte offset from the module beginning 3413 * @length: length of the section to be read (in bytes from the offset) 3414 * @data: command buffer (size [bytes] = length) 3415 * @last_command: tells if this is the last command in a series 3416 * @cmd_details: pointer to command details structure or NULL 3417 * 3418 * Read the NVM using the admin queue commands 3419 **/ 3420 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3421 u32 offset, u16 length, void *data, 3422 bool last_command, 3423 struct i40e_asq_cmd_details *cmd_details) 3424 { 3425 struct i40e_aq_desc desc; 3426 struct i40e_aqc_nvm_update *cmd = 3427 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3428 enum i40e_status_code status; 3429 3430 DEBUGFUNC("i40e_aq_read_nvm"); 3431 3432 /* In offset the highest byte must be zeroed. */ 3433 if (offset & 0xFF000000) { 3434 status = I40E_ERR_PARAM; 3435 goto i40e_aq_read_nvm_exit; 3436 } 3437 3438 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3439 3440 /* If this is the last command in a series, set the proper flag. */ 3441 if (last_command) 3442 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3443 cmd->module_pointer = module_pointer; 3444 cmd->offset = CPU_TO_LE32(offset); 3445 cmd->length = CPU_TO_LE16(length); 3446 3447 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3448 if (length > I40E_AQ_LARGE_BUF) 3449 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3450 3451 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3452 3453 i40e_aq_read_nvm_exit: 3454 return status; 3455 } 3456 3457 /** 3458 * i40e_aq_read_nvm_config - read an nvm config block 3459 * @hw: pointer to the hw struct 3460 * @cmd_flags: NVM access admin command bits 3461 * @field_id: field or feature id 3462 * @data: buffer for result 3463 * @buf_size: buffer size 3464 * @element_count: pointer to count of elements read by FW 3465 * @cmd_details: pointer to command details structure or NULL 3466 **/ 3467 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3468 u8 cmd_flags, u32 field_id, void *data, 3469 u16 buf_size, u16 *element_count, 3470 struct i40e_asq_cmd_details *cmd_details) 3471 { 3472 struct i40e_aq_desc desc; 3473 struct i40e_aqc_nvm_config_read *cmd = 3474 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3475 enum i40e_status_code status; 3476 3477 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3478 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3479 if (buf_size > I40E_AQ_LARGE_BUF) 3480 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3481 3482 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3483 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3484 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3485 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3486 else 3487 cmd->element_id_msw = 0; 3488 3489 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3490 3491 if (!status && element_count) 3492 *element_count = LE16_TO_CPU(cmd->element_count); 3493 3494 return status; 3495 } 3496 3497 /** 3498 * i40e_aq_write_nvm_config - write an nvm config block 3499 * @hw: pointer to the hw struct 3500 * @cmd_flags: NVM access admin command bits 3501 * @data: buffer for result 3502 * @buf_size: buffer size 3503 * @element_count: count of elements to be written 3504 * @cmd_details: pointer to command details structure or NULL 3505 **/ 3506 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3507 u8 cmd_flags, void *data, u16 buf_size, 3508 u16 element_count, 3509 struct i40e_asq_cmd_details *cmd_details) 3510 { 3511 struct i40e_aq_desc desc; 3512 struct i40e_aqc_nvm_config_write *cmd = 3513 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3514 enum i40e_status_code status; 3515 3516 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3517 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3518 if (buf_size > I40E_AQ_LARGE_BUF) 3519 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3520 3521 cmd->element_count = CPU_TO_LE16(element_count); 3522 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3523 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3524 3525 return status; 3526 } 3527 3528 /** 3529 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3530 * @hw: pointer to the hw struct 3531 * @buff: buffer for result 3532 * @buff_size: buffer size 3533 * @cmd_details: pointer to command details structure or NULL 3534 **/ 3535 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3536 void *buff, u16 buff_size, 3537 struct i40e_asq_cmd_details *cmd_details) 3538 { 3539 struct i40e_aq_desc desc; 3540 enum i40e_status_code status; 3541 3542 3543 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3544 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3545 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3546 status = I40E_ERR_NOT_IMPLEMENTED; 3547 3548 return status; 3549 } 3550 3551 /** 3552 * i40e_aq_erase_nvm 3553 * @hw: pointer to the hw struct 3554 * @module_pointer: module pointer location in words from the NVM beginning 3555 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3556 * @length: length of the section to be erased (expressed in 4 KB) 3557 * @last_command: tells if this is the last command in a series 3558 * @cmd_details: pointer to command details structure or NULL 3559 * 3560 * Erase the NVM sector using the admin queue commands 3561 **/ 3562 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3563 u32 offset, u16 length, bool last_command, 3564 struct i40e_asq_cmd_details *cmd_details) 3565 { 3566 struct i40e_aq_desc desc; 3567 struct i40e_aqc_nvm_update *cmd = 3568 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3569 enum i40e_status_code status; 3570 3571 DEBUGFUNC("i40e_aq_erase_nvm"); 3572 3573 /* In offset the highest byte must be zeroed. */ 3574 if (offset & 0xFF000000) { 3575 status = I40E_ERR_PARAM; 3576 goto i40e_aq_erase_nvm_exit; 3577 } 3578 3579 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3580 3581 /* If this is the last command in a series, set the proper flag. */ 3582 if (last_command) 3583 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3584 cmd->module_pointer = module_pointer; 3585 cmd->offset = CPU_TO_LE32(offset); 3586 cmd->length = CPU_TO_LE16(length); 3587 3588 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3589 3590 i40e_aq_erase_nvm_exit: 3591 return status; 3592 } 3593 3594 /** 3595 * i40e_parse_discover_capabilities 3596 * @hw: pointer to the hw struct 3597 * @buff: pointer to a buffer containing device/function capability records 3598 * @cap_count: number of capability records in the list 3599 * @list_type_opc: type of capabilities list to parse 3600 * 3601 * Parse the device/function capabilities list. 3602 **/ 3603 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3604 u32 cap_count, 3605 enum i40e_admin_queue_opc list_type_opc) 3606 { 3607 struct i40e_aqc_list_capabilities_element_resp *cap; 3608 u32 valid_functions, num_functions; 3609 u32 number, logical_id, phys_id; 3610 struct i40e_hw_capabilities *p; 3611 enum i40e_status_code status; 3612 u16 id, ocp_cfg_word0; 3613 u8 major_rev; 3614 u32 i = 0; 3615 3616 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3617 3618 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3619 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3620 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3621 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3622 else 3623 return; 3624 3625 for (i = 0; i < cap_count; i++, cap++) { 3626 id = LE16_TO_CPU(cap->id); 3627 number = LE32_TO_CPU(cap->number); 3628 logical_id = LE32_TO_CPU(cap->logical_id); 3629 phys_id = LE32_TO_CPU(cap->phys_id); 3630 major_rev = cap->major_rev; 3631 3632 switch (id) { 3633 case I40E_AQ_CAP_ID_SWITCH_MODE: 3634 p->switch_mode = number; 3635 i40e_debug(hw, I40E_DEBUG_INIT, 3636 "HW Capability: Switch mode = %d\n", 3637 p->switch_mode); 3638 break; 3639 case I40E_AQ_CAP_ID_MNG_MODE: 3640 p->management_mode = number; 3641 if (major_rev > 1) { 3642 p->mng_protocols_over_mctp = logical_id; 3643 i40e_debug(hw, I40E_DEBUG_INIT, 3644 "HW Capability: Protocols over MCTP = %d\n", 3645 p->mng_protocols_over_mctp); 3646 } else { 3647 p->mng_protocols_over_mctp = 0; 3648 } 3649 i40e_debug(hw, I40E_DEBUG_INIT, 3650 "HW Capability: Management Mode = %d\n", 3651 p->management_mode); 3652 break; 3653 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3654 p->npar_enable = number; 3655 i40e_debug(hw, I40E_DEBUG_INIT, 3656 "HW Capability: NPAR enable = %d\n", 3657 p->npar_enable); 3658 break; 3659 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3660 p->os2bmc = number; 3661 i40e_debug(hw, I40E_DEBUG_INIT, 3662 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3663 break; 3664 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3665 p->valid_functions = number; 3666 i40e_debug(hw, I40E_DEBUG_INIT, 3667 "HW Capability: Valid Functions = %d\n", 3668 p->valid_functions); 3669 break; 3670 case I40E_AQ_CAP_ID_SRIOV: 3671 if (number == 1) 3672 p->sr_iov_1_1 = TRUE; 3673 i40e_debug(hw, I40E_DEBUG_INIT, 3674 "HW Capability: SR-IOV = %d\n", 3675 p->sr_iov_1_1); 3676 break; 3677 case I40E_AQ_CAP_ID_VF: 3678 p->num_vfs = number; 3679 p->vf_base_id = logical_id; 3680 i40e_debug(hw, I40E_DEBUG_INIT, 3681 "HW Capability: VF count = %d\n", 3682 p->num_vfs); 3683 i40e_debug(hw, I40E_DEBUG_INIT, 3684 "HW Capability: VF base_id = %d\n", 3685 p->vf_base_id); 3686 break; 3687 case I40E_AQ_CAP_ID_VMDQ: 3688 if (number == 1) 3689 p->vmdq = TRUE; 3690 i40e_debug(hw, I40E_DEBUG_INIT, 3691 "HW Capability: VMDQ = %d\n", p->vmdq); 3692 break; 3693 case I40E_AQ_CAP_ID_8021QBG: 3694 if (number == 1) 3695 p->evb_802_1_qbg = TRUE; 3696 i40e_debug(hw, I40E_DEBUG_INIT, 3697 "HW Capability: 802.1Qbg = %d\n", number); 3698 break; 3699 case I40E_AQ_CAP_ID_8021QBR: 3700 if (number == 1) 3701 p->evb_802_1_qbh = TRUE; 3702 i40e_debug(hw, I40E_DEBUG_INIT, 3703 "HW Capability: 802.1Qbh = %d\n", number); 3704 break; 3705 case I40E_AQ_CAP_ID_VSI: 3706 p->num_vsis = number; 3707 i40e_debug(hw, I40E_DEBUG_INIT, 3708 "HW Capability: VSI count = %d\n", 3709 p->num_vsis); 3710 break; 3711 case I40E_AQ_CAP_ID_DCB: 3712 if (number == 1) { 3713 p->dcb = TRUE; 3714 p->enabled_tcmap = logical_id; 3715 p->maxtc = phys_id; 3716 } 3717 i40e_debug(hw, I40E_DEBUG_INIT, 3718 "HW Capability: DCB = %d\n", p->dcb); 3719 i40e_debug(hw, I40E_DEBUG_INIT, 3720 "HW Capability: TC Mapping = %d\n", 3721 logical_id); 3722 i40e_debug(hw, I40E_DEBUG_INIT, 3723 "HW Capability: TC Max = %d\n", p->maxtc); 3724 break; 3725 case I40E_AQ_CAP_ID_FCOE: 3726 if (number == 1) 3727 p->fcoe = TRUE; 3728 i40e_debug(hw, I40E_DEBUG_INIT, 3729 "HW Capability: FCOE = %d\n", p->fcoe); 3730 break; 3731 case I40E_AQ_CAP_ID_ISCSI: 3732 if (number == 1) 3733 p->iscsi = TRUE; 3734 i40e_debug(hw, I40E_DEBUG_INIT, 3735 "HW Capability: iSCSI = %d\n", p->iscsi); 3736 break; 3737 case I40E_AQ_CAP_ID_RSS: 3738 p->rss = TRUE; 3739 p->rss_table_size = number; 3740 p->rss_table_entry_width = logical_id; 3741 i40e_debug(hw, I40E_DEBUG_INIT, 3742 "HW Capability: RSS = %d\n", p->rss); 3743 i40e_debug(hw, I40E_DEBUG_INIT, 3744 "HW Capability: RSS table size = %d\n", 3745 p->rss_table_size); 3746 i40e_debug(hw, I40E_DEBUG_INIT, 3747 "HW Capability: RSS table width = %d\n", 3748 p->rss_table_entry_width); 3749 break; 3750 case I40E_AQ_CAP_ID_RXQ: 3751 p->num_rx_qp = number; 3752 p->base_queue = phys_id; 3753 i40e_debug(hw, I40E_DEBUG_INIT, 3754 "HW Capability: Rx QP = %d\n", number); 3755 i40e_debug(hw, I40E_DEBUG_INIT, 3756 "HW Capability: base_queue = %d\n", 3757 p->base_queue); 3758 break; 3759 case I40E_AQ_CAP_ID_TXQ: 3760 p->num_tx_qp = number; 3761 p->base_queue = phys_id; 3762 i40e_debug(hw, I40E_DEBUG_INIT, 3763 "HW Capability: Tx QP = %d\n", number); 3764 i40e_debug(hw, I40E_DEBUG_INIT, 3765 "HW Capability: base_queue = %d\n", 3766 p->base_queue); 3767 break; 3768 case I40E_AQ_CAP_ID_MSIX: 3769 p->num_msix_vectors = number; 3770 i40e_debug(hw, I40E_DEBUG_INIT, 3771 "HW Capability: MSIX vector count = %d\n", 3772 p->num_msix_vectors); 3773 break; 3774 case I40E_AQ_CAP_ID_VF_MSIX: 3775 p->num_msix_vectors_vf = number; 3776 i40e_debug(hw, I40E_DEBUG_INIT, 3777 "HW Capability: MSIX VF vector count = %d\n", 3778 p->num_msix_vectors_vf); 3779 break; 3780 case I40E_AQ_CAP_ID_FLEX10: 3781 if (major_rev == 1) { 3782 if (number == 1) { 3783 p->flex10_enable = TRUE; 3784 p->flex10_capable = TRUE; 3785 } 3786 } else { 3787 /* Capability revision >= 2 */ 3788 if (number & 1) 3789 p->flex10_enable = TRUE; 3790 if (number & 2) 3791 p->flex10_capable = TRUE; 3792 } 3793 p->flex10_mode = logical_id; 3794 p->flex10_status = phys_id; 3795 i40e_debug(hw, I40E_DEBUG_INIT, 3796 "HW Capability: Flex10 mode = %d\n", 3797 p->flex10_mode); 3798 i40e_debug(hw, I40E_DEBUG_INIT, 3799 "HW Capability: Flex10 status = %d\n", 3800 p->flex10_status); 3801 break; 3802 case I40E_AQ_CAP_ID_CEM: 3803 if (number == 1) 3804 p->mgmt_cem = TRUE; 3805 i40e_debug(hw, I40E_DEBUG_INIT, 3806 "HW Capability: CEM = %d\n", p->mgmt_cem); 3807 break; 3808 case I40E_AQ_CAP_ID_IWARP: 3809 if (number == 1) 3810 p->iwarp = TRUE; 3811 i40e_debug(hw, I40E_DEBUG_INIT, 3812 "HW Capability: iWARP = %d\n", p->iwarp); 3813 break; 3814 case I40E_AQ_CAP_ID_LED: 3815 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3816 p->led[phys_id] = TRUE; 3817 i40e_debug(hw, I40E_DEBUG_INIT, 3818 "HW Capability: LED - PIN %d\n", phys_id); 3819 break; 3820 case I40E_AQ_CAP_ID_SDP: 3821 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3822 p->sdp[phys_id] = TRUE; 3823 i40e_debug(hw, I40E_DEBUG_INIT, 3824 "HW Capability: SDP - PIN %d\n", phys_id); 3825 break; 3826 case I40E_AQ_CAP_ID_MDIO: 3827 if (number == 1) { 3828 p->mdio_port_num = phys_id; 3829 p->mdio_port_mode = logical_id; 3830 } 3831 i40e_debug(hw, I40E_DEBUG_INIT, 3832 "HW Capability: MDIO port number = %d\n", 3833 p->mdio_port_num); 3834 i40e_debug(hw, I40E_DEBUG_INIT, 3835 "HW Capability: MDIO port mode = %d\n", 3836 p->mdio_port_mode); 3837 break; 3838 case I40E_AQ_CAP_ID_1588: 3839 if (number == 1) 3840 p->ieee_1588 = TRUE; 3841 i40e_debug(hw, I40E_DEBUG_INIT, 3842 "HW Capability: IEEE 1588 = %d\n", 3843 p->ieee_1588); 3844 break; 3845 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3846 p->fd = TRUE; 3847 p->fd_filters_guaranteed = number; 3848 p->fd_filters_best_effort = logical_id; 3849 i40e_debug(hw, I40E_DEBUG_INIT, 3850 "HW Capability: Flow Director = 1\n"); 3851 i40e_debug(hw, I40E_DEBUG_INIT, 3852 "HW Capability: Guaranteed FD filters = %d\n", 3853 p->fd_filters_guaranteed); 3854 break; 3855 case I40E_AQ_CAP_ID_WSR_PROT: 3856 p->wr_csr_prot = (u64)number; 3857 p->wr_csr_prot |= (u64)logical_id << 32; 3858 i40e_debug(hw, I40E_DEBUG_INIT, 3859 "HW Capability: wr_csr_prot = 0x%llX\n\n", 3860 (p->wr_csr_prot & 0xffff)); 3861 break; 3862 case I40E_AQ_CAP_ID_NVM_MGMT: 3863 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3864 p->sec_rev_disabled = TRUE; 3865 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3866 p->update_disabled = TRUE; 3867 break; 3868 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 3869 hw->num_wol_proxy_filters = (u16)number; 3870 hw->wol_proxy_vsi_seid = (u16)logical_id; 3871 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 3872 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 3873 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 3874 else 3875 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 3876 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 3877 i40e_debug(hw, I40E_DEBUG_INIT, 3878 "HW Capability: WOL proxy filters = %d\n", 3879 hw->num_wol_proxy_filters); 3880 break; 3881 default: 3882 break; 3883 } 3884 } 3885 3886 if (p->fcoe) 3887 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3888 3889 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3890 p->fcoe = FALSE; 3891 3892 valid_functions = p->valid_functions; 3893 num_functions = 0; 3894 while (valid_functions) { 3895 if (valid_functions & 1) 3896 num_functions++; 3897 valid_functions >>= 1; 3898 } 3899 3900 /* count the enabled ports (aka the "not disabled" ports) */ 3901 hw->num_ports = 0; 3902 for (i = 0; i < 4; i++) { 3903 u32 port_cfg_reg = I40E_PRTGEN_STATUS + (4 * i); 3904 u64 port_cfg = 0; 3905 3906 /* use AQ read to get the physical register offset instead 3907 * of the port relative offset 3908 */ 3909 status = i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3910 if ((status == I40E_SUCCESS) && 3911 (port_cfg & I40E_PRTGEN_STATUS_PORT_VALID_MASK)) 3912 hw->num_ports++; 3913 } 3914 3915 /* OCP cards case: if a mezz is removed the ethernet port is at 3916 * disabled state in PRTGEN_CNF register. Additional NVM read is 3917 * needed in order to check if we are dealing with OCP card. 3918 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 3919 * physical ports results in wrong partition id calculation and thus 3920 * not supporting WoL. 3921 * 3922 * Porting note: the above comment is no longer directly relevant: we 3923 * read PRTGEN_STATUS instead now, as PRTGEN_CNF was not reliable for 3924 * these parts. In addition, the claim about having 4 PFs is not 3925 * correct. For example, an X557-T2 is a dual port mezz card. Forcing 3926 * ports to four here will cause ->num_partitions to be zero. 3927 * 3928 * On the presumption that the hard-coded value is meaningful in some 3929 * cases, though, we'll take the minimal approach of ensuring that we 3930 * never have more ports than functions. 3931 */ 3932 if (hw->mac.type == I40E_MAC_X722) { 3933 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) { 3934 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 3935 2 * I40E_SR_OCP_CFG_WORD0, 3936 sizeof(ocp_cfg_word0), 3937 &ocp_cfg_word0, TRUE, NULL); 3938 #ifdef __sun__ 3939 if (status == I40E_SUCCESS && 3940 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) { 3941 hw->num_ports = 4; 3942 if (hw->num_ports > num_functions) { 3943 hw->num_ports = num_functions; 3944 DEBUGOUT1("clamped 4 OCP ports to %d\n", 3945 (int)hw->num_ports); 3946 } 3947 } 3948 #else 3949 if (status == I40E_SUCCESS && 3950 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 3951 hw->num_ports = 4; 3952 #endif 3953 i40e_release_nvm(hw); 3954 } 3955 } 3956 3957 /* partition id is 1-based, and functions are evenly spread 3958 * across the ports as partitions 3959 */ 3960 if (hw->num_ports != 0) { 3961 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3962 hw->num_partitions = num_functions / hw->num_ports; 3963 } 3964 3965 VERIFY(hw->num_partitions > 0); 3966 3967 /* additional HW specific goodies that might 3968 * someday be HW version specific 3969 */ 3970 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3971 } 3972 3973 /** 3974 * i40e_aq_discover_capabilities 3975 * @hw: pointer to the hw struct 3976 * @buff: a virtual buffer to hold the capabilities 3977 * @buff_size: Size of the virtual buffer 3978 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3979 * @list_type_opc: capabilities type to discover - pass in the command opcode 3980 * @cmd_details: pointer to command details structure or NULL 3981 * 3982 * Get the device capabilities descriptions from the firmware 3983 **/ 3984 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 3985 void *buff, u16 buff_size, u16 *data_size, 3986 enum i40e_admin_queue_opc list_type_opc, 3987 struct i40e_asq_cmd_details *cmd_details) 3988 { 3989 struct i40e_aqc_list_capabilites *cmd; 3990 struct i40e_aq_desc desc; 3991 enum i40e_status_code status = I40E_SUCCESS; 3992 3993 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3994 3995 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3996 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3997 status = I40E_ERR_PARAM; 3998 goto exit; 3999 } 4000 4001 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 4002 4003 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4004 if (buff_size > I40E_AQ_LARGE_BUF) 4005 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4006 4007 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4008 *data_size = LE16_TO_CPU(desc.datalen); 4009 4010 if (status) 4011 goto exit; 4012 4013 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 4014 list_type_opc); 4015 4016 exit: 4017 return status; 4018 } 4019 4020 /** 4021 * i40e_aq_update_nvm 4022 * @hw: pointer to the hw struct 4023 * @module_pointer: module pointer location in words from the NVM beginning 4024 * @offset: byte offset from the module beginning 4025 * @length: length of the section to be written (in bytes from the offset) 4026 * @data: command buffer (size [bytes] = length) 4027 * @last_command: tells if this is the last command in a series 4028 * @preservation_flags: Preservation mode flags 4029 * @cmd_details: pointer to command details structure or NULL 4030 * 4031 * Update the NVM using the admin queue commands 4032 **/ 4033 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 4034 u32 offset, u16 length, void *data, 4035 bool last_command, u8 preservation_flags, 4036 struct i40e_asq_cmd_details *cmd_details) 4037 { 4038 struct i40e_aq_desc desc; 4039 struct i40e_aqc_nvm_update *cmd = 4040 (struct i40e_aqc_nvm_update *)&desc.params.raw; 4041 enum i40e_status_code status; 4042 4043 DEBUGFUNC("i40e_aq_update_nvm"); 4044 4045 /* In offset the highest byte must be zeroed. */ 4046 if (offset & 0xFF000000) { 4047 status = I40E_ERR_PARAM; 4048 goto i40e_aq_update_nvm_exit; 4049 } 4050 4051 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4052 4053 /* If this is the last command in a series, set the proper flag. */ 4054 if (last_command) 4055 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 4056 if (hw->mac.type == I40E_MAC_X722) { 4057 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 4058 cmd->command_flags |= 4059 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 4060 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4061 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 4062 cmd->command_flags |= 4063 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 4064 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4065 } 4066 cmd->module_pointer = module_pointer; 4067 cmd->offset = CPU_TO_LE32(offset); 4068 cmd->length = CPU_TO_LE16(length); 4069 4070 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4071 if (length > I40E_AQ_LARGE_BUF) 4072 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4073 4074 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 4075 4076 i40e_aq_update_nvm_exit: 4077 return status; 4078 } 4079 4080 /** 4081 * i40e_aq_nvm_progress 4082 * @hw: pointer to the hw struct 4083 * @progress: pointer to progress returned from AQ 4084 * @cmd_details: pointer to command details structure or NULL 4085 * 4086 * Gets progress of flash rearrangement process 4087 **/ 4088 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress, 4089 struct i40e_asq_cmd_details *cmd_details) 4090 { 4091 enum i40e_status_code status; 4092 struct i40e_aq_desc desc; 4093 4094 DEBUGFUNC("i40e_aq_nvm_progress"); 4095 4096 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress); 4097 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4098 *progress = desc.params.raw[0]; 4099 return status; 4100 } 4101 4102 /** 4103 * i40e_aq_get_lldp_mib 4104 * @hw: pointer to the hw struct 4105 * @bridge_type: type of bridge requested 4106 * @mib_type: Local, Remote or both Local and Remote MIBs 4107 * @buff: pointer to a user supplied buffer to store the MIB block 4108 * @buff_size: size of the buffer (in bytes) 4109 * @local_len : length of the returned Local LLDP MIB 4110 * @remote_len: length of the returned Remote LLDP MIB 4111 * @cmd_details: pointer to command details structure or NULL 4112 * 4113 * Requests the complete LLDP MIB (entire packet). 4114 **/ 4115 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 4116 u8 mib_type, void *buff, u16 buff_size, 4117 u16 *local_len, u16 *remote_len, 4118 struct i40e_asq_cmd_details *cmd_details) 4119 { 4120 struct i40e_aq_desc desc; 4121 struct i40e_aqc_lldp_get_mib *cmd = 4122 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4123 struct i40e_aqc_lldp_get_mib *resp = 4124 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4125 enum i40e_status_code status; 4126 4127 if (buff_size == 0 || !buff) 4128 return I40E_ERR_PARAM; 4129 4130 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 4131 /* Indirect Command */ 4132 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4133 4134 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 4135 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4136 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4137 4138 desc.datalen = CPU_TO_LE16(buff_size); 4139 4140 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4141 if (buff_size > I40E_AQ_LARGE_BUF) 4142 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4143 4144 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4145 if (!status) { 4146 if (local_len != NULL) 4147 *local_len = LE16_TO_CPU(resp->local_len); 4148 if (remote_len != NULL) 4149 *remote_len = LE16_TO_CPU(resp->remote_len); 4150 } 4151 4152 return status; 4153 } 4154 4155 /** 4156 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4157 * @hw: pointer to the hw struct 4158 * @mib_type: Local, Remote or both Local and Remote MIBs 4159 * @buff: pointer to a user supplied buffer to store the MIB block 4160 * @buff_size: size of the buffer (in bytes) 4161 * @cmd_details: pointer to command details structure or NULL 4162 * 4163 * Set the LLDP MIB. 4164 **/ 4165 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4166 u8 mib_type, void *buff, u16 buff_size, 4167 struct i40e_asq_cmd_details *cmd_details) 4168 { 4169 struct i40e_aq_desc desc; 4170 struct i40e_aqc_lldp_set_local_mib *cmd = 4171 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4172 enum i40e_status_code status; 4173 4174 if (buff_size == 0 || !buff) 4175 return I40E_ERR_PARAM; 4176 4177 i40e_fill_default_direct_cmd_desc(&desc, 4178 i40e_aqc_opc_lldp_set_local_mib); 4179 /* Indirect Command */ 4180 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4181 if (buff_size > I40E_AQ_LARGE_BUF) 4182 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4183 desc.datalen = CPU_TO_LE16(buff_size); 4184 4185 cmd->type = mib_type; 4186 cmd->length = CPU_TO_LE16(buff_size); 4187 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((uintptr_t)buff)); 4188 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)buff)); 4189 4190 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4191 return status; 4192 } 4193 4194 /** 4195 * i40e_aq_cfg_lldp_mib_change_event 4196 * @hw: pointer to the hw struct 4197 * @enable_update: Enable or Disable event posting 4198 * @cmd_details: pointer to command details structure or NULL 4199 * 4200 * Enable or Disable posting of an event on ARQ when LLDP MIB 4201 * associated with the interface changes 4202 **/ 4203 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4204 bool enable_update, 4205 struct i40e_asq_cmd_details *cmd_details) 4206 { 4207 struct i40e_aq_desc desc; 4208 struct i40e_aqc_lldp_update_mib *cmd = 4209 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4210 enum i40e_status_code status; 4211 4212 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4213 4214 if (!enable_update) 4215 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4216 4217 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4218 4219 return status; 4220 } 4221 4222 /** 4223 * i40e_aq_add_lldp_tlv 4224 * @hw: pointer to the hw struct 4225 * @bridge_type: type of bridge 4226 * @buff: buffer with TLV to add 4227 * @buff_size: length of the buffer 4228 * @tlv_len: length of the TLV to be added 4229 * @mib_len: length of the LLDP MIB returned in response 4230 * @cmd_details: pointer to command details structure or NULL 4231 * 4232 * Add the specified TLV to LLDP Local MIB for the given bridge type, 4233 * it is responsibility of the caller to make sure that the TLV is not 4234 * already present in the LLDPDU. 4235 * In return firmware will write the complete LLDP MIB with the newly 4236 * added TLV in the response buffer. 4237 **/ 4238 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 4239 void *buff, u16 buff_size, u16 tlv_len, 4240 u16 *mib_len, 4241 struct i40e_asq_cmd_details *cmd_details) 4242 { 4243 struct i40e_aq_desc desc; 4244 struct i40e_aqc_lldp_add_tlv *cmd = 4245 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4246 enum i40e_status_code status; 4247 4248 if (buff_size == 0 || !buff || tlv_len == 0) 4249 return I40E_ERR_PARAM; 4250 4251 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 4252 4253 /* Indirect Command */ 4254 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4255 if (buff_size > I40E_AQ_LARGE_BUF) 4256 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4257 desc.datalen = CPU_TO_LE16(buff_size); 4258 4259 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4260 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4261 cmd->len = CPU_TO_LE16(tlv_len); 4262 4263 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4264 if (!status) { 4265 if (mib_len != NULL) 4266 *mib_len = LE16_TO_CPU(desc.datalen); 4267 } 4268 4269 return status; 4270 } 4271 4272 /** 4273 * i40e_aq_update_lldp_tlv 4274 * @hw: pointer to the hw struct 4275 * @bridge_type: type of bridge 4276 * @buff: buffer with TLV to update 4277 * @buff_size: size of the buffer holding original and updated TLVs 4278 * @old_len: Length of the Original TLV 4279 * @new_len: Length of the Updated TLV 4280 * @offset: offset of the updated TLV in the buff 4281 * @mib_len: length of the returned LLDP MIB 4282 * @cmd_details: pointer to command details structure or NULL 4283 * 4284 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 4285 * Firmware will place the complete LLDP MIB in response buffer with the 4286 * updated TLV. 4287 **/ 4288 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 4289 u8 bridge_type, void *buff, u16 buff_size, 4290 u16 old_len, u16 new_len, u16 offset, 4291 u16 *mib_len, 4292 struct i40e_asq_cmd_details *cmd_details) 4293 { 4294 struct i40e_aq_desc desc; 4295 struct i40e_aqc_lldp_update_tlv *cmd = 4296 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 4297 enum i40e_status_code status; 4298 4299 if (buff_size == 0 || !buff || offset == 0 || 4300 old_len == 0 || new_len == 0) 4301 return I40E_ERR_PARAM; 4302 4303 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 4304 4305 /* Indirect Command */ 4306 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4307 if (buff_size > I40E_AQ_LARGE_BUF) 4308 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4309 desc.datalen = CPU_TO_LE16(buff_size); 4310 4311 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4312 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4313 cmd->old_len = CPU_TO_LE16(old_len); 4314 cmd->new_offset = CPU_TO_LE16(offset); 4315 cmd->new_len = CPU_TO_LE16(new_len); 4316 4317 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4318 if (!status) { 4319 if (mib_len != NULL) 4320 *mib_len = LE16_TO_CPU(desc.datalen); 4321 } 4322 4323 return status; 4324 } 4325 4326 /** 4327 * i40e_aq_delete_lldp_tlv 4328 * @hw: pointer to the hw struct 4329 * @bridge_type: type of bridge 4330 * @buff: pointer to a user supplied buffer that has the TLV 4331 * @buff_size: length of the buffer 4332 * @tlv_len: length of the TLV to be deleted 4333 * @mib_len: length of the returned LLDP MIB 4334 * @cmd_details: pointer to command details structure or NULL 4335 * 4336 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 4337 * The firmware places the entire LLDP MIB in the response buffer. 4338 **/ 4339 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 4340 u8 bridge_type, void *buff, u16 buff_size, 4341 u16 tlv_len, u16 *mib_len, 4342 struct i40e_asq_cmd_details *cmd_details) 4343 { 4344 struct i40e_aq_desc desc; 4345 struct i40e_aqc_lldp_add_tlv *cmd = 4346 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4347 enum i40e_status_code status; 4348 4349 if (buff_size == 0 || !buff) 4350 return I40E_ERR_PARAM; 4351 4352 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 4353 4354 /* Indirect Command */ 4355 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4356 if (buff_size > I40E_AQ_LARGE_BUF) 4357 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4358 desc.datalen = CPU_TO_LE16(buff_size); 4359 cmd->len = CPU_TO_LE16(tlv_len); 4360 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4361 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4362 4363 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4364 if (!status) { 4365 if (mib_len != NULL) 4366 *mib_len = LE16_TO_CPU(desc.datalen); 4367 } 4368 4369 return status; 4370 } 4371 4372 /** 4373 * i40e_aq_stop_lldp 4374 * @hw: pointer to the hw struct 4375 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4376 * @cmd_details: pointer to command details structure or NULL 4377 * 4378 * Stop or Shutdown the embedded LLDP Agent 4379 **/ 4380 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4381 struct i40e_asq_cmd_details *cmd_details) 4382 { 4383 struct i40e_aq_desc desc; 4384 struct i40e_aqc_lldp_stop *cmd = 4385 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4386 enum i40e_status_code status; 4387 4388 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4389 4390 if (shutdown_agent) 4391 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4392 4393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4394 4395 return status; 4396 } 4397 4398 /** 4399 * i40e_aq_start_lldp 4400 * @hw: pointer to the hw struct 4401 * @cmd_details: pointer to command details structure or NULL 4402 * 4403 * Start the embedded LLDP Agent on all ports. 4404 **/ 4405 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4406 struct i40e_asq_cmd_details *cmd_details) 4407 { 4408 struct i40e_aq_desc desc; 4409 struct i40e_aqc_lldp_start *cmd = 4410 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4411 enum i40e_status_code status; 4412 4413 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4414 4415 cmd->command = I40E_AQ_LLDP_AGENT_START; 4416 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4417 4418 return status; 4419 } 4420 4421 /** 4422 * i40e_aq_set_dcb_parameters 4423 * @hw: pointer to the hw struct 4424 * @cmd_details: pointer to command details structure or NULL 4425 * @dcb_enable: True if DCB configuration needs to be applied 4426 * 4427 **/ 4428 enum i40e_status_code 4429 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 4430 struct i40e_asq_cmd_details *cmd_details) 4431 { 4432 struct i40e_aq_desc desc; 4433 struct i40e_aqc_set_dcb_parameters *cmd = 4434 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 4435 enum i40e_status_code status; 4436 4437 if ((hw->mac.type != I40E_MAC_XL710) || 4438 ((hw->aq.api_maj_ver < 1) || 4439 ((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 6)))) 4440 return I40E_ERR_DEVICE_NOT_SUPPORTED; 4441 4442 i40e_fill_default_direct_cmd_desc(&desc, 4443 i40e_aqc_opc_set_dcb_parameters); 4444 4445 if (dcb_enable) { 4446 cmd->valid_flags = I40E_DCB_VALID; 4447 cmd->command = I40E_AQ_DCB_SET_AGENT; 4448 } 4449 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4450 4451 return status; 4452 } 4453 4454 /** 4455 * i40e_aq_get_cee_dcb_config 4456 * @hw: pointer to the hw struct 4457 * @buff: response buffer that stores CEE operational configuration 4458 * @buff_size: size of the buffer passed 4459 * @cmd_details: pointer to command details structure or NULL 4460 * 4461 * Get CEE DCBX mode operational configuration from firmware 4462 **/ 4463 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4464 void *buff, u16 buff_size, 4465 struct i40e_asq_cmd_details *cmd_details) 4466 { 4467 struct i40e_aq_desc desc; 4468 enum i40e_status_code status; 4469 4470 if (buff_size == 0 || !buff) 4471 return I40E_ERR_PARAM; 4472 4473 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4474 4475 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4476 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4477 cmd_details); 4478 4479 return status; 4480 } 4481 4482 /** 4483 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4484 * @hw: pointer to the hw struct 4485 * @start_agent: True if DCBx Agent needs to be Started 4486 * False if DCBx Agent needs to be Stopped 4487 * @cmd_details: pointer to command details structure or NULL 4488 * 4489 * Start/Stop the embedded dcbx Agent 4490 **/ 4491 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4492 bool start_agent, 4493 struct i40e_asq_cmd_details *cmd_details) 4494 { 4495 struct i40e_aq_desc desc; 4496 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4497 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4498 &desc.params.raw; 4499 enum i40e_status_code status; 4500 4501 i40e_fill_default_direct_cmd_desc(&desc, 4502 i40e_aqc_opc_lldp_stop_start_spec_agent); 4503 4504 if (start_agent) 4505 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4506 4507 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4508 4509 return status; 4510 } 4511 4512 /** 4513 * i40e_aq_add_udp_tunnel 4514 * @hw: pointer to the hw struct 4515 * @udp_port: the UDP port to add 4516 * @header_len: length of the tunneling header length in DWords 4517 * @protocol_index: protocol index type 4518 * @filter_index: pointer to filter index 4519 * @cmd_details: pointer to command details structure or NULL 4520 **/ 4521 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4522 u16 udp_port, u8 protocol_index, 4523 u8 *filter_index, 4524 struct i40e_asq_cmd_details *cmd_details) 4525 { 4526 struct i40e_aq_desc desc; 4527 struct i40e_aqc_add_udp_tunnel *cmd = 4528 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4529 struct i40e_aqc_del_udp_tunnel_completion *resp = 4530 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4531 enum i40e_status_code status; 4532 4533 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4534 4535 cmd->udp_port = CPU_TO_LE16(udp_port); 4536 cmd->protocol_type = protocol_index; 4537 4538 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4539 4540 if (!status && filter_index) 4541 *filter_index = resp->index; 4542 4543 return status; 4544 } 4545 4546 /** 4547 * i40e_aq_del_udp_tunnel 4548 * @hw: pointer to the hw struct 4549 * @index: filter index 4550 * @cmd_details: pointer to command details structure or NULL 4551 **/ 4552 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4553 struct i40e_asq_cmd_details *cmd_details) 4554 { 4555 struct i40e_aq_desc desc; 4556 struct i40e_aqc_remove_udp_tunnel *cmd = 4557 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4558 enum i40e_status_code status; 4559 4560 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4561 4562 cmd->index = index; 4563 4564 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4565 4566 return status; 4567 } 4568 4569 /** 4570 * i40e_aq_get_switch_resource_alloc (0x0204) 4571 * @hw: pointer to the hw struct 4572 * @num_entries: pointer to u8 to store the number of resource entries returned 4573 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4574 * to store the resource information for all resource types. Each 4575 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4576 * @count: size, in bytes, of the buffer provided 4577 * @cmd_details: pointer to command details structure or NULL 4578 * 4579 * Query the resources allocated to a function. 4580 **/ 4581 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4582 u8 *num_entries, 4583 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4584 u16 count, 4585 struct i40e_asq_cmd_details *cmd_details) 4586 { 4587 struct i40e_aq_desc desc; 4588 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4589 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4590 enum i40e_status_code status; 4591 u16 length = count * sizeof(*buf); 4592 4593 i40e_fill_default_direct_cmd_desc(&desc, 4594 i40e_aqc_opc_get_switch_resource_alloc); 4595 4596 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4597 if (length > I40E_AQ_LARGE_BUF) 4598 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4599 4600 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4601 4602 if (!status && num_entries) 4603 *num_entries = cmd_resp->num_entries; 4604 4605 return status; 4606 } 4607 4608 /** 4609 * i40e_aq_delete_element - Delete switch element 4610 * @hw: pointer to the hw struct 4611 * @seid: the SEID to delete from the switch 4612 * @cmd_details: pointer to command details structure or NULL 4613 * 4614 * This deletes a switch element from the switch. 4615 **/ 4616 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4617 struct i40e_asq_cmd_details *cmd_details) 4618 { 4619 struct i40e_aq_desc desc; 4620 struct i40e_aqc_switch_seid *cmd = 4621 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4622 enum i40e_status_code status; 4623 4624 if (seid == 0) 4625 return I40E_ERR_PARAM; 4626 4627 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4628 4629 cmd->seid = CPU_TO_LE16(seid); 4630 4631 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4632 4633 return status; 4634 } 4635 4636 /** 4637 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4638 * @hw: pointer to the hw struct 4639 * @flags: component flags 4640 * @mac_seid: uplink seid (MAC SEID) 4641 * @vsi_seid: connected vsi seid 4642 * @ret_seid: seid of create pv component 4643 * 4644 * This instantiates an i40e port virtualizer with specified flags. 4645 * Depending on specified flags the port virtualizer can act as a 4646 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4647 */ 4648 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4649 u16 mac_seid, u16 vsi_seid, 4650 u16 *ret_seid) 4651 { 4652 struct i40e_aq_desc desc; 4653 struct i40e_aqc_add_update_pv *cmd = 4654 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4655 struct i40e_aqc_add_update_pv_completion *resp = 4656 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4657 enum i40e_status_code status; 4658 4659 if (vsi_seid == 0) 4660 return I40E_ERR_PARAM; 4661 4662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4663 cmd->command_flags = CPU_TO_LE16(flags); 4664 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4665 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4666 4667 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4668 if (!status && ret_seid) 4669 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4670 4671 return status; 4672 } 4673 4674 /** 4675 * i40e_aq_add_tag - Add an S/E-tag 4676 * @hw: pointer to the hw struct 4677 * @direct_to_queue: should s-tag direct flow to a specific queue 4678 * @vsi_seid: VSI SEID to use this tag 4679 * @tag: value of the tag 4680 * @queue_num: queue number, only valid is direct_to_queue is TRUE 4681 * @tags_used: return value, number of tags in use by this PF 4682 * @tags_free: return value, number of unallocated tags 4683 * @cmd_details: pointer to command details structure or NULL 4684 * 4685 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4686 * the number of tags allocated by the PF, and the number of unallocated 4687 * tags available. 4688 **/ 4689 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4690 u16 vsi_seid, u16 tag, u16 queue_num, 4691 u16 *tags_used, u16 *tags_free, 4692 struct i40e_asq_cmd_details *cmd_details) 4693 { 4694 struct i40e_aq_desc desc; 4695 struct i40e_aqc_add_tag *cmd = 4696 (struct i40e_aqc_add_tag *)&desc.params.raw; 4697 struct i40e_aqc_add_remove_tag_completion *resp = 4698 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4699 enum i40e_status_code status; 4700 4701 if (vsi_seid == 0) 4702 return I40E_ERR_PARAM; 4703 4704 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4705 4706 cmd->seid = CPU_TO_LE16(vsi_seid); 4707 cmd->tag = CPU_TO_LE16(tag); 4708 if (direct_to_queue) { 4709 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4710 cmd->queue_number = CPU_TO_LE16(queue_num); 4711 } 4712 4713 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4714 4715 if (!status) { 4716 if (tags_used != NULL) 4717 *tags_used = LE16_TO_CPU(resp->tags_used); 4718 if (tags_free != NULL) 4719 *tags_free = LE16_TO_CPU(resp->tags_free); 4720 } 4721 4722 return status; 4723 } 4724 4725 /** 4726 * i40e_aq_remove_tag - Remove an S- or E-tag 4727 * @hw: pointer to the hw struct 4728 * @vsi_seid: VSI SEID this tag is associated with 4729 * @tag: value of the S-tag to delete 4730 * @tags_used: return value, number of tags in use by this PF 4731 * @tags_free: return value, number of unallocated tags 4732 * @cmd_details: pointer to command details structure or NULL 4733 * 4734 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4735 * the number of tags allocated by the PF, and the number of unallocated 4736 * tags available. 4737 **/ 4738 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4739 u16 tag, u16 *tags_used, u16 *tags_free, 4740 struct i40e_asq_cmd_details *cmd_details) 4741 { 4742 struct i40e_aq_desc desc; 4743 struct i40e_aqc_remove_tag *cmd = 4744 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4745 struct i40e_aqc_add_remove_tag_completion *resp = 4746 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4747 enum i40e_status_code status; 4748 4749 if (vsi_seid == 0) 4750 return I40E_ERR_PARAM; 4751 4752 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4753 4754 cmd->seid = CPU_TO_LE16(vsi_seid); 4755 cmd->tag = CPU_TO_LE16(tag); 4756 4757 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4758 4759 if (!status) { 4760 if (tags_used != NULL) 4761 *tags_used = LE16_TO_CPU(resp->tags_used); 4762 if (tags_free != NULL) 4763 *tags_free = LE16_TO_CPU(resp->tags_free); 4764 } 4765 4766 return status; 4767 } 4768 4769 /** 4770 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4771 * @hw: pointer to the hw struct 4772 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4773 * @etag: value of E-tag to add 4774 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4775 * @buf: address of indirect buffer 4776 * @tags_used: return value, number of E-tags in use by this port 4777 * @tags_free: return value, number of unallocated M-tags 4778 * @cmd_details: pointer to command details structure or NULL 4779 * 4780 * This associates a multicast E-tag to a port virtualizer. It will return 4781 * the number of tags allocated by the PF, and the number of unallocated 4782 * tags available. 4783 * 4784 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4785 * num_tags_in_buf long. 4786 **/ 4787 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4788 u16 etag, u8 num_tags_in_buf, void *buf, 4789 u16 *tags_used, u16 *tags_free, 4790 struct i40e_asq_cmd_details *cmd_details) 4791 { 4792 struct i40e_aq_desc desc; 4793 struct i40e_aqc_add_remove_mcast_etag *cmd = 4794 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4795 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4796 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4797 enum i40e_status_code status; 4798 u16 length = sizeof(u16) * num_tags_in_buf; 4799 4800 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4801 return I40E_ERR_PARAM; 4802 4803 i40e_fill_default_direct_cmd_desc(&desc, 4804 i40e_aqc_opc_add_multicast_etag); 4805 4806 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4807 cmd->etag = CPU_TO_LE16(etag); 4808 cmd->num_unicast_etags = num_tags_in_buf; 4809 4810 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4811 if (length > I40E_AQ_LARGE_BUF) 4812 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4813 4814 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4815 4816 if (!status) { 4817 if (tags_used != NULL) 4818 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4819 if (tags_free != NULL) 4820 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4821 } 4822 4823 return status; 4824 } 4825 4826 /** 4827 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4828 * @hw: pointer to the hw struct 4829 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4830 * @etag: value of the E-tag to remove 4831 * @tags_used: return value, number of tags in use by this port 4832 * @tags_free: return value, number of unallocated tags 4833 * @cmd_details: pointer to command details structure or NULL 4834 * 4835 * This deletes an E-tag from the port virtualizer. It will return 4836 * the number of tags allocated by the port, and the number of unallocated 4837 * tags available. 4838 **/ 4839 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4840 u16 etag, u16 *tags_used, u16 *tags_free, 4841 struct i40e_asq_cmd_details *cmd_details) 4842 { 4843 struct i40e_aq_desc desc; 4844 struct i40e_aqc_add_remove_mcast_etag *cmd = 4845 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4846 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4847 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4848 enum i40e_status_code status; 4849 4850 4851 if (pv_seid == 0) 4852 return I40E_ERR_PARAM; 4853 4854 i40e_fill_default_direct_cmd_desc(&desc, 4855 i40e_aqc_opc_remove_multicast_etag); 4856 4857 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4858 cmd->etag = CPU_TO_LE16(etag); 4859 4860 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4861 4862 if (!status) { 4863 if (tags_used != NULL) 4864 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4865 if (tags_free != NULL) 4866 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4867 } 4868 4869 return status; 4870 } 4871 4872 /** 4873 * i40e_aq_update_tag - Update an S/E-tag 4874 * @hw: pointer to the hw struct 4875 * @vsi_seid: VSI SEID using this S-tag 4876 * @old_tag: old tag value 4877 * @new_tag: new tag value 4878 * @tags_used: return value, number of tags in use by this PF 4879 * @tags_free: return value, number of unallocated tags 4880 * @cmd_details: pointer to command details structure or NULL 4881 * 4882 * This updates the value of the tag currently attached to this VSI 4883 * in the switch complex. It will return the number of tags allocated 4884 * by the PF, and the number of unallocated tags available. 4885 **/ 4886 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4887 u16 old_tag, u16 new_tag, u16 *tags_used, 4888 u16 *tags_free, 4889 struct i40e_asq_cmd_details *cmd_details) 4890 { 4891 struct i40e_aq_desc desc; 4892 struct i40e_aqc_update_tag *cmd = 4893 (struct i40e_aqc_update_tag *)&desc.params.raw; 4894 struct i40e_aqc_update_tag_completion *resp = 4895 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4896 enum i40e_status_code status; 4897 4898 if (vsi_seid == 0) 4899 return I40E_ERR_PARAM; 4900 4901 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4902 4903 cmd->seid = CPU_TO_LE16(vsi_seid); 4904 cmd->old_tag = CPU_TO_LE16(old_tag); 4905 cmd->new_tag = CPU_TO_LE16(new_tag); 4906 4907 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4908 4909 if (!status) { 4910 if (tags_used != NULL) 4911 *tags_used = LE16_TO_CPU(resp->tags_used); 4912 if (tags_free != NULL) 4913 *tags_free = LE16_TO_CPU(resp->tags_free); 4914 } 4915 4916 return status; 4917 } 4918 4919 /** 4920 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4921 * @hw: pointer to the hw struct 4922 * @tcmap: TC map for request/release any ignore PFC condition 4923 * @request: request or release ignore PFC condition 4924 * @tcmap_ret: return TCs for which PFC is currently ignored 4925 * @cmd_details: pointer to command details structure or NULL 4926 * 4927 * This sends out request/release to ignore PFC condition for a TC. 4928 * It will return the TCs for which PFC is currently ignored. 4929 **/ 4930 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4931 bool request, u8 *tcmap_ret, 4932 struct i40e_asq_cmd_details *cmd_details) 4933 { 4934 struct i40e_aq_desc desc; 4935 struct i40e_aqc_pfc_ignore *cmd_resp = 4936 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4937 enum i40e_status_code status; 4938 4939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4940 4941 if (request) 4942 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4943 4944 cmd_resp->tc_bitmap = tcmap; 4945 4946 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4947 4948 if (!status) { 4949 if (tcmap_ret != NULL) 4950 *tcmap_ret = cmd_resp->tc_bitmap; 4951 } 4952 4953 return status; 4954 } 4955 4956 /** 4957 * i40e_aq_dcb_updated - DCB Updated Command 4958 * @hw: pointer to the hw struct 4959 * @cmd_details: pointer to command details structure or NULL 4960 * 4961 * When LLDP is handled in PF this command is used by the PF 4962 * to notify EMP that a DCB setting is modified. 4963 * When LLDP is handled in EMP this command is used by the PF 4964 * to notify EMP whenever one of the following parameters get 4965 * modified: 4966 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4967 * - PCIRTT in PRTDCB_GENC.PCIRTT 4968 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4969 * EMP will return when the shared RPB settings have been 4970 * recomputed and modified. The retval field in the descriptor 4971 * will be set to 0 when RPB is modified. 4972 **/ 4973 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 4974 struct i40e_asq_cmd_details *cmd_details) 4975 { 4976 struct i40e_aq_desc desc; 4977 enum i40e_status_code status; 4978 4979 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 4980 4981 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4982 4983 return status; 4984 } 4985 4986 /** 4987 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 4988 * @hw: pointer to the hw struct 4989 * @seid: defines the SEID of the switch for which the stats are requested 4990 * @vlan_id: the VLAN ID for which the statistics are requested 4991 * @stat_index: index of the statistics counters block assigned to this VLAN 4992 * @cmd_details: pointer to command details structure or NULL 4993 * 4994 * XL710 supports 128 smonVlanStats counters.This command is used to 4995 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 4996 * switch. 4997 **/ 4998 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 4999 u16 vlan_id, u16 *stat_index, 5000 struct i40e_asq_cmd_details *cmd_details) 5001 { 5002 struct i40e_aq_desc desc; 5003 struct i40e_aqc_add_remove_statistics *cmd_resp = 5004 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5005 enum i40e_status_code status; 5006 5007 if ((seid == 0) || (stat_index == NULL)) 5008 return I40E_ERR_PARAM; 5009 5010 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 5011 5012 cmd_resp->seid = CPU_TO_LE16(seid); 5013 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 5014 5015 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5016 5017 if (!status && stat_index) 5018 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 5019 5020 return status; 5021 } 5022 5023 /** 5024 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 5025 * @hw: pointer to the hw struct 5026 * @seid: defines the SEID of the switch for which the stats are requested 5027 * @vlan_id: the VLAN ID for which the statistics are requested 5028 * @stat_index: index of the statistics counters block assigned to this VLAN 5029 * @cmd_details: pointer to command details structure or NULL 5030 * 5031 * XL710 supports 128 smonVlanStats counters.This command is used to 5032 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 5033 * switch. 5034 **/ 5035 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 5036 u16 vlan_id, u16 stat_index, 5037 struct i40e_asq_cmd_details *cmd_details) 5038 { 5039 struct i40e_aq_desc desc; 5040 struct i40e_aqc_add_remove_statistics *cmd = 5041 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5042 enum i40e_status_code status; 5043 5044 if (seid == 0) 5045 return I40E_ERR_PARAM; 5046 5047 i40e_fill_default_direct_cmd_desc(&desc, 5048 i40e_aqc_opc_remove_statistics); 5049 5050 cmd->seid = CPU_TO_LE16(seid); 5051 cmd->vlan = CPU_TO_LE16(vlan_id); 5052 cmd->stat_index = CPU_TO_LE16(stat_index); 5053 5054 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5055 5056 return status; 5057 } 5058 5059 /** 5060 * i40e_aq_set_port_parameters - set physical port parameters. 5061 * @hw: pointer to the hw struct 5062 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 5063 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 5064 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 5065 * @double_vlan: if set double VLAN is enabled 5066 * @cmd_details: pointer to command details structure or NULL 5067 **/ 5068 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 5069 u16 bad_frame_vsi, bool save_bad_pac, 5070 bool pad_short_pac, bool double_vlan, 5071 struct i40e_asq_cmd_details *cmd_details) 5072 { 5073 struct i40e_aqc_set_port_parameters *cmd; 5074 enum i40e_status_code status; 5075 struct i40e_aq_desc desc; 5076 u16 command_flags = 0; 5077 5078 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 5079 5080 i40e_fill_default_direct_cmd_desc(&desc, 5081 i40e_aqc_opc_set_port_parameters); 5082 5083 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 5084 if (save_bad_pac) 5085 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 5086 if (pad_short_pac) 5087 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 5088 if (double_vlan) 5089 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 5090 cmd->command_flags = CPU_TO_LE16(command_flags); 5091 5092 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5093 5094 return status; 5095 } 5096 5097 /** 5098 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 5099 * @hw: pointer to the hw struct 5100 * @seid: seid for the physical port/switching component/vsi 5101 * @buff: Indirect buffer to hold data parameters and response 5102 * @buff_size: Indirect buffer size 5103 * @opcode: Tx scheduler AQ command opcode 5104 * @cmd_details: pointer to command details structure or NULL 5105 * 5106 * Generic command handler for Tx scheduler AQ commands 5107 **/ 5108 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 5109 void *buff, u16 buff_size, 5110 enum i40e_admin_queue_opc opcode, 5111 struct i40e_asq_cmd_details *cmd_details) 5112 { 5113 struct i40e_aq_desc desc; 5114 struct i40e_aqc_tx_sched_ind *cmd = 5115 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 5116 enum i40e_status_code status; 5117 bool cmd_param_flag = FALSE; 5118 5119 switch (opcode) { 5120 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 5121 case i40e_aqc_opc_configure_vsi_tc_bw: 5122 case i40e_aqc_opc_enable_switching_comp_ets: 5123 case i40e_aqc_opc_modify_switching_comp_ets: 5124 case i40e_aqc_opc_disable_switching_comp_ets: 5125 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 5126 case i40e_aqc_opc_configure_switching_comp_bw_config: 5127 cmd_param_flag = TRUE; 5128 break; 5129 case i40e_aqc_opc_query_vsi_bw_config: 5130 case i40e_aqc_opc_query_vsi_ets_sla_config: 5131 case i40e_aqc_opc_query_switching_comp_ets_config: 5132 case i40e_aqc_opc_query_port_ets_config: 5133 case i40e_aqc_opc_query_switching_comp_bw_config: 5134 cmd_param_flag = FALSE; 5135 break; 5136 default: 5137 return I40E_ERR_PARAM; 5138 } 5139 5140 i40e_fill_default_direct_cmd_desc(&desc, opcode); 5141 5142 /* Indirect command */ 5143 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5144 if (cmd_param_flag) 5145 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5146 if (buff_size > I40E_AQ_LARGE_BUF) 5147 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5148 5149 desc.datalen = CPU_TO_LE16(buff_size); 5150 5151 cmd->vsi_seid = CPU_TO_LE16(seid); 5152 5153 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5154 5155 return status; 5156 } 5157 5158 /** 5159 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 5160 * @hw: pointer to the hw struct 5161 * @seid: VSI seid 5162 * @credit: BW limit credits (0 = disabled) 5163 * @max_credit: Max BW limit credits 5164 * @cmd_details: pointer to command details structure or NULL 5165 **/ 5166 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 5167 u16 seid, u16 credit, u8 max_credit, 5168 struct i40e_asq_cmd_details *cmd_details) 5169 { 5170 struct i40e_aq_desc desc; 5171 struct i40e_aqc_configure_vsi_bw_limit *cmd = 5172 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 5173 enum i40e_status_code status; 5174 5175 i40e_fill_default_direct_cmd_desc(&desc, 5176 i40e_aqc_opc_configure_vsi_bw_limit); 5177 5178 cmd->vsi_seid = CPU_TO_LE16(seid); 5179 cmd->credit = CPU_TO_LE16(credit); 5180 cmd->max_credit = max_credit; 5181 5182 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5183 5184 return status; 5185 } 5186 5187 /** 5188 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5189 * @hw: pointer to the hw struct 5190 * @seid: switching component seid 5191 * @credit: BW limit credits (0 = disabled) 5192 * @max_bw: Max BW limit credits 5193 * @cmd_details: pointer to command details structure or NULL 5194 **/ 5195 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5196 u16 seid, u16 credit, u8 max_bw, 5197 struct i40e_asq_cmd_details *cmd_details) 5198 { 5199 struct i40e_aq_desc desc; 5200 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5201 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5202 enum i40e_status_code status; 5203 5204 i40e_fill_default_direct_cmd_desc(&desc, 5205 i40e_aqc_opc_configure_switching_comp_bw_limit); 5206 5207 cmd->seid = CPU_TO_LE16(seid); 5208 cmd->credit = CPU_TO_LE16(credit); 5209 cmd->max_bw = max_bw; 5210 5211 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5212 5213 return status; 5214 } 5215 5216 /** 5217 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5218 * @hw: pointer to the hw struct 5219 * @seid: VSI seid 5220 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5221 * @cmd_details: pointer to command details structure or NULL 5222 **/ 5223 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5224 u16 seid, 5225 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5226 struct i40e_asq_cmd_details *cmd_details) 5227 { 5228 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5229 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5230 cmd_details); 5231 } 5232 5233 /** 5234 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5235 * @hw: pointer to the hw struct 5236 * @seid: VSI seid 5237 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5238 * @cmd_details: pointer to command details structure or NULL 5239 **/ 5240 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5241 u16 seid, 5242 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5243 struct i40e_asq_cmd_details *cmd_details) 5244 { 5245 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5246 i40e_aqc_opc_configure_vsi_tc_bw, 5247 cmd_details); 5248 } 5249 5250 /** 5251 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5252 * @hw: pointer to the hw struct 5253 * @seid: seid of the switching component 5254 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5255 * @cmd_details: pointer to command details structure or NULL 5256 **/ 5257 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5258 struct i40e_hw *hw, u16 seid, 5259 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5260 struct i40e_asq_cmd_details *cmd_details) 5261 { 5262 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5263 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5264 cmd_details); 5265 } 5266 5267 /** 5268 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5269 * @hw: pointer to the hw struct 5270 * @seid: seid of the VSI 5271 * @bw_data: Buffer to hold VSI BW configuration 5272 * @cmd_details: pointer to command details structure or NULL 5273 **/ 5274 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5275 u16 seid, 5276 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5277 struct i40e_asq_cmd_details *cmd_details) 5278 { 5279 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5280 i40e_aqc_opc_query_vsi_bw_config, 5281 cmd_details); 5282 } 5283 5284 /** 5285 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5286 * @hw: pointer to the hw struct 5287 * @seid: seid of the VSI 5288 * @bw_data: Buffer to hold VSI BW configuration per TC 5289 * @cmd_details: pointer to command details structure or NULL 5290 **/ 5291 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5292 u16 seid, 5293 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5294 struct i40e_asq_cmd_details *cmd_details) 5295 { 5296 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5297 i40e_aqc_opc_query_vsi_ets_sla_config, 5298 cmd_details); 5299 } 5300 5301 /** 5302 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5303 * @hw: pointer to the hw struct 5304 * @seid: seid of the switching component 5305 * @bw_data: Buffer to hold switching component's per TC BW config 5306 * @cmd_details: pointer to command details structure or NULL 5307 **/ 5308 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5309 u16 seid, 5310 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5311 struct i40e_asq_cmd_details *cmd_details) 5312 { 5313 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5314 i40e_aqc_opc_query_switching_comp_ets_config, 5315 cmd_details); 5316 } 5317 5318 /** 5319 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5320 * @hw: pointer to the hw struct 5321 * @seid: seid of the VSI or switching component connected to Physical Port 5322 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5323 * @cmd_details: pointer to command details structure or NULL 5324 **/ 5325 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5326 u16 seid, 5327 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5328 struct i40e_asq_cmd_details *cmd_details) 5329 { 5330 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5331 i40e_aqc_opc_query_port_ets_config, 5332 cmd_details); 5333 } 5334 5335 /** 5336 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5337 * @hw: pointer to the hw struct 5338 * @seid: seid of the switching component 5339 * @bw_data: Buffer to hold switching component's BW configuration 5340 * @cmd_details: pointer to command details structure or NULL 5341 **/ 5342 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5343 u16 seid, 5344 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5345 struct i40e_asq_cmd_details *cmd_details) 5346 { 5347 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5348 i40e_aqc_opc_query_switching_comp_bw_config, 5349 cmd_details); 5350 } 5351 5352 /** 5353 * i40e_validate_filter_settings 5354 * @hw: pointer to the hardware structure 5355 * @settings: Filter control settings 5356 * 5357 * Check and validate the filter control settings passed. 5358 * The function checks for the valid filter/context sizes being 5359 * passed for FCoE and PE. 5360 * 5361 * Returns I40E_SUCCESS if the values passed are valid and within 5362 * range else returns an error. 5363 **/ 5364 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5365 struct i40e_filter_control_settings *settings) 5366 { 5367 u32 fcoe_cntx_size, fcoe_filt_size; 5368 u32 pe_cntx_size, pe_filt_size; 5369 u32 fcoe_fmax; 5370 5371 u32 val; 5372 5373 /* Validate FCoE settings passed */ 5374 switch (settings->fcoe_filt_num) { 5375 case I40E_HASH_FILTER_SIZE_1K: 5376 case I40E_HASH_FILTER_SIZE_2K: 5377 case I40E_HASH_FILTER_SIZE_4K: 5378 case I40E_HASH_FILTER_SIZE_8K: 5379 case I40E_HASH_FILTER_SIZE_16K: 5380 case I40E_HASH_FILTER_SIZE_32K: 5381 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5382 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5383 break; 5384 default: 5385 return I40E_ERR_PARAM; 5386 } 5387 5388 switch (settings->fcoe_cntx_num) { 5389 case I40E_DMA_CNTX_SIZE_512: 5390 case I40E_DMA_CNTX_SIZE_1K: 5391 case I40E_DMA_CNTX_SIZE_2K: 5392 case I40E_DMA_CNTX_SIZE_4K: 5393 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5394 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5395 break; 5396 default: 5397 return I40E_ERR_PARAM; 5398 } 5399 5400 /* Validate PE settings passed */ 5401 switch (settings->pe_filt_num) { 5402 case I40E_HASH_FILTER_SIZE_1K: 5403 case I40E_HASH_FILTER_SIZE_2K: 5404 case I40E_HASH_FILTER_SIZE_4K: 5405 case I40E_HASH_FILTER_SIZE_8K: 5406 case I40E_HASH_FILTER_SIZE_16K: 5407 case I40E_HASH_FILTER_SIZE_32K: 5408 case I40E_HASH_FILTER_SIZE_64K: 5409 case I40E_HASH_FILTER_SIZE_128K: 5410 case I40E_HASH_FILTER_SIZE_256K: 5411 case I40E_HASH_FILTER_SIZE_512K: 5412 case I40E_HASH_FILTER_SIZE_1M: 5413 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5414 pe_filt_size <<= (u32)settings->pe_filt_num; 5415 break; 5416 default: 5417 return I40E_ERR_PARAM; 5418 } 5419 5420 switch (settings->pe_cntx_num) { 5421 case I40E_DMA_CNTX_SIZE_512: 5422 case I40E_DMA_CNTX_SIZE_1K: 5423 case I40E_DMA_CNTX_SIZE_2K: 5424 case I40E_DMA_CNTX_SIZE_4K: 5425 case I40E_DMA_CNTX_SIZE_8K: 5426 case I40E_DMA_CNTX_SIZE_16K: 5427 case I40E_DMA_CNTX_SIZE_32K: 5428 case I40E_DMA_CNTX_SIZE_64K: 5429 case I40E_DMA_CNTX_SIZE_128K: 5430 case I40E_DMA_CNTX_SIZE_256K: 5431 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5432 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5433 break; 5434 default: 5435 return I40E_ERR_PARAM; 5436 } 5437 5438 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5439 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5440 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5441 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5442 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5443 return I40E_ERR_INVALID_SIZE; 5444 5445 return I40E_SUCCESS; 5446 } 5447 5448 /** 5449 * i40e_set_filter_control 5450 * @hw: pointer to the hardware structure 5451 * @settings: Filter control settings 5452 * 5453 * Set the Queue Filters for PE/FCoE and enable filters required 5454 * for a single PF. It is expected that these settings are programmed 5455 * at the driver initialization time. 5456 **/ 5457 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5458 struct i40e_filter_control_settings *settings) 5459 { 5460 enum i40e_status_code ret = I40E_SUCCESS; 5461 u32 hash_lut_size = 0; 5462 u32 val; 5463 5464 if (!settings) 5465 return I40E_ERR_PARAM; 5466 5467 /* Validate the input settings */ 5468 ret = i40e_validate_filter_settings(hw, settings); 5469 if (ret) 5470 return ret; 5471 5472 /* Read the PF Queue Filter control register */ 5473 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5474 5475 /* Program required PE hash buckets for the PF */ 5476 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5477 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5478 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5479 /* Program required PE contexts for the PF */ 5480 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5481 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5482 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5483 5484 /* Program required FCoE hash buckets for the PF */ 5485 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5486 val |= ((u32)settings->fcoe_filt_num << 5487 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5488 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5489 /* Program required FCoE DDP contexts for the PF */ 5490 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5491 val |= ((u32)settings->fcoe_cntx_num << 5492 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5493 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5494 5495 /* Program Hash LUT size for the PF */ 5496 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5497 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5498 hash_lut_size = 1; 5499 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5500 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5501 5502 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5503 if (settings->enable_fdir) 5504 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5505 if (settings->enable_ethtype) 5506 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5507 if (settings->enable_macvlan) 5508 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5509 5510 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5511 5512 return I40E_SUCCESS; 5513 } 5514 5515 /** 5516 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5517 * @hw: pointer to the hw struct 5518 * @mac_addr: MAC address to use in the filter 5519 * @ethtype: Ethertype to use in the filter 5520 * @flags: Flags that needs to be applied to the filter 5521 * @vsi_seid: seid of the control VSI 5522 * @queue: VSI queue number to send the packet to 5523 * @is_add: Add control packet filter if True else remove 5524 * @stats: Structure to hold information on control filter counts 5525 * @cmd_details: pointer to command details structure or NULL 5526 * 5527 * This command will Add or Remove control packet filter for a control VSI. 5528 * In return it will update the total number of perfect filter count in 5529 * the stats member. 5530 **/ 5531 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5532 u8 *mac_addr, u16 ethtype, u16 flags, 5533 u16 vsi_seid, u16 queue, bool is_add, 5534 struct i40e_control_filter_stats *stats, 5535 struct i40e_asq_cmd_details *cmd_details) 5536 { 5537 struct i40e_aq_desc desc; 5538 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5539 (struct i40e_aqc_add_remove_control_packet_filter *) 5540 &desc.params.raw; 5541 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5542 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5543 &desc.params.raw; 5544 enum i40e_status_code status; 5545 5546 if (vsi_seid == 0) 5547 return I40E_ERR_PARAM; 5548 5549 if (is_add) { 5550 i40e_fill_default_direct_cmd_desc(&desc, 5551 i40e_aqc_opc_add_control_packet_filter); 5552 cmd->queue = CPU_TO_LE16(queue); 5553 } else { 5554 i40e_fill_default_direct_cmd_desc(&desc, 5555 i40e_aqc_opc_remove_control_packet_filter); 5556 } 5557 5558 if (mac_addr) 5559 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN, 5560 I40E_NONDMA_TO_NONDMA); 5561 5562 cmd->etype = CPU_TO_LE16(ethtype); 5563 cmd->flags = CPU_TO_LE16(flags); 5564 cmd->seid = CPU_TO_LE16(vsi_seid); 5565 5566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5567 5568 if (!status && stats) { 5569 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5570 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5571 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5572 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5573 } 5574 5575 return status; 5576 } 5577 5578 /** 5579 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5580 * @hw: pointer to the hw struct 5581 * @seid: VSI seid to add ethertype filter from 5582 **/ 5583 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5584 u16 seid) 5585 { 5586 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5587 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5588 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5589 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5590 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5591 enum i40e_status_code status; 5592 5593 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5594 seid, 0, TRUE, NULL, 5595 NULL); 5596 if (status) 5597 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5598 } 5599 5600 /** 5601 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5602 * @filters: list of cloud filters 5603 * @filter_count: length of list 5604 * 5605 * There's an issue in the device where the Geneve VNI layout needs 5606 * to be shifted 1 byte over from the VxLAN VNI 5607 **/ 5608 static void i40e_fix_up_geneve_vni( 5609 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5610 u8 filter_count) 5611 { 5612 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters; 5613 int i; 5614 5615 for (i = 0; i < filter_count; i++) { 5616 u16 tnl_type; 5617 u32 ti; 5618 5619 tnl_type = (LE16_TO_CPU(f[i].flags) & 5620 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5621 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5622 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5623 ti = LE32_TO_CPU(f[i].tenant_id); 5624 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5625 } 5626 } 5627 } 5628 5629 /** 5630 * i40e_aq_add_cloud_filters 5631 * @hw: pointer to the hardware structure 5632 * @seid: VSI seid to add cloud filters from 5633 * @filters: Buffer which contains the filters to be added 5634 * @filter_count: number of filters contained in the buffer 5635 * 5636 * Set the cloud filters for a given VSI. The contents of the 5637 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5638 * in by the caller of the function. 5639 * 5640 **/ 5641 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5642 u16 seid, 5643 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5644 u8 filter_count) 5645 { 5646 struct i40e_aq_desc desc; 5647 struct i40e_aqc_add_remove_cloud_filters *cmd = 5648 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5649 enum i40e_status_code status; 5650 u16 buff_len; 5651 5652 i40e_fill_default_direct_cmd_desc(&desc, 5653 i40e_aqc_opc_add_cloud_filters); 5654 5655 buff_len = filter_count * sizeof(*filters); 5656 desc.datalen = CPU_TO_LE16(buff_len); 5657 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5658 cmd->num_filters = filter_count; 5659 cmd->seid = CPU_TO_LE16(seid); 5660 5661 i40e_fix_up_geneve_vni(filters, filter_count); 5662 5663 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5664 5665 return status; 5666 } 5667 5668 /** 5669 * i40e_aq_remove_cloud_filters 5670 * @hw: pointer to the hardware structure 5671 * @seid: VSI seid to remove cloud filters from 5672 * @filters: Buffer which contains the filters to be removed 5673 * @filter_count: number of filters contained in the buffer 5674 * 5675 * Remove the cloud filters for a given VSI. The contents of the 5676 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5677 * in by the caller of the function. 5678 * 5679 **/ 5680 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 5681 u16 seid, 5682 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5683 u8 filter_count) 5684 { 5685 struct i40e_aq_desc desc; 5686 struct i40e_aqc_add_remove_cloud_filters *cmd = 5687 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5688 enum i40e_status_code status; 5689 u16 buff_len; 5690 5691 i40e_fill_default_direct_cmd_desc(&desc, 5692 i40e_aqc_opc_remove_cloud_filters); 5693 5694 buff_len = filter_count * sizeof(*filters); 5695 desc.datalen = CPU_TO_LE16(buff_len); 5696 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5697 cmd->num_filters = filter_count; 5698 cmd->seid = CPU_TO_LE16(seid); 5699 5700 i40e_fix_up_geneve_vni(filters, filter_count); 5701 5702 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5703 5704 return status; 5705 } 5706 5707 /** 5708 * i40e_aq_alternate_write 5709 * @hw: pointer to the hardware structure 5710 * @reg_addr0: address of first dword to be read 5711 * @reg_val0: value to be written under 'reg_addr0' 5712 * @reg_addr1: address of second dword to be read 5713 * @reg_val1: value to be written under 'reg_addr1' 5714 * 5715 * Write one or two dwords to alternate structure. Fields are indicated 5716 * by 'reg_addr0' and 'reg_addr1' register numbers. 5717 * 5718 **/ 5719 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 5720 u32 reg_addr0, u32 reg_val0, 5721 u32 reg_addr1, u32 reg_val1) 5722 { 5723 struct i40e_aq_desc desc; 5724 struct i40e_aqc_alternate_write *cmd_resp = 5725 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5726 enum i40e_status_code status; 5727 5728 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 5729 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5730 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5731 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5732 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5733 5734 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5735 5736 return status; 5737 } 5738 5739 /** 5740 * i40e_aq_alternate_write_indirect 5741 * @hw: pointer to the hardware structure 5742 * @addr: address of a first register to be modified 5743 * @dw_count: number of alternate structure fields to write 5744 * @buffer: pointer to the command buffer 5745 * 5746 * Write 'dw_count' dwords from 'buffer' to alternate structure 5747 * starting at 'addr'. 5748 * 5749 **/ 5750 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5751 u32 addr, u32 dw_count, void *buffer) 5752 { 5753 struct i40e_aq_desc desc; 5754 struct i40e_aqc_alternate_ind_write *cmd_resp = 5755 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5756 enum i40e_status_code status; 5757 5758 if (buffer == NULL) 5759 return I40E_ERR_PARAM; 5760 5761 /* Indirect command */ 5762 i40e_fill_default_direct_cmd_desc(&desc, 5763 i40e_aqc_opc_alternate_write_indirect); 5764 5765 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5766 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5767 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5768 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5769 5770 cmd_resp->address = CPU_TO_LE32(addr); 5771 cmd_resp->length = CPU_TO_LE32(dw_count); 5772 5773 status = i40e_asq_send_command(hw, &desc, buffer, 5774 I40E_LO_DWORD(4*dw_count), NULL); 5775 5776 return status; 5777 } 5778 5779 /** 5780 * i40e_aq_alternate_read 5781 * @hw: pointer to the hardware structure 5782 * @reg_addr0: address of first dword to be read 5783 * @reg_val0: pointer for data read from 'reg_addr0' 5784 * @reg_addr1: address of second dword to be read 5785 * @reg_val1: pointer for data read from 'reg_addr1' 5786 * 5787 * Read one or two dwords from alternate structure. Fields are indicated 5788 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5789 * is not passed then only register at 'reg_addr0' is read. 5790 * 5791 **/ 5792 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5793 u32 reg_addr0, u32 *reg_val0, 5794 u32 reg_addr1, u32 *reg_val1) 5795 { 5796 struct i40e_aq_desc desc; 5797 struct i40e_aqc_alternate_write *cmd_resp = 5798 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5799 enum i40e_status_code status; 5800 5801 if (reg_val0 == NULL) 5802 return I40E_ERR_PARAM; 5803 5804 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5805 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5806 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5807 5808 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5809 5810 if (status == I40E_SUCCESS) { 5811 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5812 5813 if (reg_val1 != NULL) 5814 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5815 } 5816 5817 return status; 5818 } 5819 5820 /** 5821 * i40e_aq_alternate_read_indirect 5822 * @hw: pointer to the hardware structure 5823 * @addr: address of the alternate structure field 5824 * @dw_count: number of alternate structure fields to read 5825 * @buffer: pointer to the command buffer 5826 * 5827 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5828 * place them in 'buffer'. The buffer should be allocated by caller. 5829 * 5830 **/ 5831 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5832 u32 addr, u32 dw_count, void *buffer) 5833 { 5834 struct i40e_aq_desc desc; 5835 struct i40e_aqc_alternate_ind_write *cmd_resp = 5836 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5837 enum i40e_status_code status; 5838 5839 if (buffer == NULL) 5840 return I40E_ERR_PARAM; 5841 5842 /* Indirect command */ 5843 i40e_fill_default_direct_cmd_desc(&desc, 5844 i40e_aqc_opc_alternate_read_indirect); 5845 5846 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5847 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5848 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5849 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5850 5851 cmd_resp->address = CPU_TO_LE32(addr); 5852 cmd_resp->length = CPU_TO_LE32(dw_count); 5853 5854 status = i40e_asq_send_command(hw, &desc, buffer, 5855 I40E_LO_DWORD(4*dw_count), NULL); 5856 5857 return status; 5858 } 5859 5860 /** 5861 * i40e_aq_alternate_clear 5862 * @hw: pointer to the HW structure. 5863 * 5864 * Clear the alternate structures of the port from which the function 5865 * is called. 5866 * 5867 **/ 5868 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 5869 { 5870 struct i40e_aq_desc desc; 5871 enum i40e_status_code status; 5872 5873 i40e_fill_default_direct_cmd_desc(&desc, 5874 i40e_aqc_opc_alternate_clear_port); 5875 5876 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5877 5878 return status; 5879 } 5880 5881 /** 5882 * i40e_aq_alternate_write_done 5883 * @hw: pointer to the HW structure. 5884 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 5885 * @reset_needed: indicates the SW should trigger GLOBAL reset 5886 * 5887 * Indicates to the FW that alternate structures have been changed. 5888 * 5889 **/ 5890 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 5891 u8 bios_mode, bool *reset_needed) 5892 { 5893 struct i40e_aq_desc desc; 5894 struct i40e_aqc_alternate_write_done *cmd = 5895 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5896 enum i40e_status_code status; 5897 5898 if (reset_needed == NULL) 5899 return I40E_ERR_PARAM; 5900 5901 i40e_fill_default_direct_cmd_desc(&desc, 5902 i40e_aqc_opc_alternate_write_done); 5903 5904 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 5905 5906 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5907 if (!status && reset_needed) 5908 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 5909 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 5910 5911 return status; 5912 } 5913 5914 /** 5915 * i40e_aq_set_oem_mode 5916 * @hw: pointer to the HW structure. 5917 * @oem_mode: the OEM mode to be used 5918 * 5919 * Sets the device to a specific operating mode. Currently the only supported 5920 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 5921 * 5922 **/ 5923 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 5924 u8 oem_mode) 5925 { 5926 struct i40e_aq_desc desc; 5927 struct i40e_aqc_alternate_write_done *cmd = 5928 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5929 enum i40e_status_code status; 5930 5931 i40e_fill_default_direct_cmd_desc(&desc, 5932 i40e_aqc_opc_alternate_set_mode); 5933 5934 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 5935 5936 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5937 5938 return status; 5939 } 5940 5941 /** 5942 * i40e_aq_resume_port_tx 5943 * @hw: pointer to the hardware structure 5944 * @cmd_details: pointer to command details structure or NULL 5945 * 5946 * Resume port's Tx traffic 5947 **/ 5948 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 5949 struct i40e_asq_cmd_details *cmd_details) 5950 { 5951 struct i40e_aq_desc desc; 5952 enum i40e_status_code status; 5953 5954 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 5955 5956 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5957 5958 return status; 5959 } 5960 5961 /** 5962 * i40e_set_pci_config_data - store PCI bus info 5963 * @hw: pointer to hardware structure 5964 * @link_status: the link status word from PCI config space 5965 * 5966 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 5967 **/ 5968 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 5969 { 5970 hw->bus.type = i40e_bus_type_pci_express; 5971 5972 switch (link_status & I40E_PCI_LINK_WIDTH) { 5973 case I40E_PCI_LINK_WIDTH_1: 5974 hw->bus.width = i40e_bus_width_pcie_x1; 5975 break; 5976 case I40E_PCI_LINK_WIDTH_2: 5977 hw->bus.width = i40e_bus_width_pcie_x2; 5978 break; 5979 case I40E_PCI_LINK_WIDTH_4: 5980 hw->bus.width = i40e_bus_width_pcie_x4; 5981 break; 5982 case I40E_PCI_LINK_WIDTH_8: 5983 hw->bus.width = i40e_bus_width_pcie_x8; 5984 break; 5985 default: 5986 hw->bus.width = i40e_bus_width_unknown; 5987 break; 5988 } 5989 5990 switch (link_status & I40E_PCI_LINK_SPEED) { 5991 case I40E_PCI_LINK_SPEED_2500: 5992 hw->bus.speed = i40e_bus_speed_2500; 5993 break; 5994 case I40E_PCI_LINK_SPEED_5000: 5995 hw->bus.speed = i40e_bus_speed_5000; 5996 break; 5997 case I40E_PCI_LINK_SPEED_8000: 5998 hw->bus.speed = i40e_bus_speed_8000; 5999 break; 6000 default: 6001 hw->bus.speed = i40e_bus_speed_unknown; 6002 break; 6003 } 6004 } 6005 6006 /** 6007 * i40e_aq_debug_dump 6008 * @hw: pointer to the hardware structure 6009 * @cluster_id: specific cluster to dump 6010 * @table_id: table id within cluster 6011 * @start_index: index of line in the block to read 6012 * @buff_size: dump buffer size 6013 * @buff: dump buffer 6014 * @ret_buff_size: actual buffer size returned 6015 * @ret_next_table: next block to read 6016 * @ret_next_index: next index to read 6017 * @cmd_details: pointer to command details structure or NULL 6018 * 6019 * Dump internal FW/HW data for debug purposes. 6020 * 6021 **/ 6022 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 6023 u8 table_id, u32 start_index, u16 buff_size, 6024 void *buff, u16 *ret_buff_size, 6025 u8 *ret_next_table, u32 *ret_next_index, 6026 struct i40e_asq_cmd_details *cmd_details) 6027 { 6028 struct i40e_aq_desc desc; 6029 struct i40e_aqc_debug_dump_internals *cmd = 6030 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6031 struct i40e_aqc_debug_dump_internals *resp = 6032 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6033 enum i40e_status_code status; 6034 6035 if (buff_size == 0 || !buff) 6036 return I40E_ERR_PARAM; 6037 6038 i40e_fill_default_direct_cmd_desc(&desc, 6039 i40e_aqc_opc_debug_dump_internals); 6040 /* Indirect Command */ 6041 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6042 if (buff_size > I40E_AQ_LARGE_BUF) 6043 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6044 6045 cmd->cluster_id = cluster_id; 6046 cmd->table_id = table_id; 6047 cmd->idx = CPU_TO_LE32(start_index); 6048 6049 desc.datalen = CPU_TO_LE16(buff_size); 6050 6051 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 6052 if (!status) { 6053 if (ret_buff_size != NULL) 6054 *ret_buff_size = LE16_TO_CPU(desc.datalen); 6055 if (ret_next_table != NULL) 6056 *ret_next_table = resp->table_id; 6057 if (ret_next_index != NULL) 6058 *ret_next_index = LE32_TO_CPU(resp->idx); 6059 } 6060 6061 return status; 6062 } 6063 6064 /** 6065 * i40e_read_bw_from_alt_ram 6066 * @hw: pointer to the hardware structure 6067 * @max_bw: pointer for max_bw read 6068 * @min_bw: pointer for min_bw read 6069 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 6070 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 6071 * 6072 * Read bw from the alternate ram for the given pf 6073 **/ 6074 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 6075 u32 *max_bw, u32 *min_bw, 6076 bool *min_valid, bool *max_valid) 6077 { 6078 enum i40e_status_code status; 6079 u32 max_bw_addr, min_bw_addr; 6080 6081 /* Calculate the address of the min/max bw registers */ 6082 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6083 I40E_ALT_STRUCT_MAX_BW_OFFSET + 6084 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6085 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6086 I40E_ALT_STRUCT_MIN_BW_OFFSET + 6087 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6088 6089 /* Read the bandwidths from alt ram */ 6090 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 6091 min_bw_addr, min_bw); 6092 6093 if (*min_bw & I40E_ALT_BW_VALID_MASK) 6094 *min_valid = TRUE; 6095 else 6096 *min_valid = FALSE; 6097 6098 if (*max_bw & I40E_ALT_BW_VALID_MASK) 6099 *max_valid = TRUE; 6100 else 6101 *max_valid = FALSE; 6102 6103 return status; 6104 } 6105 6106 /** 6107 * i40e_aq_configure_partition_bw 6108 * @hw: pointer to the hardware structure 6109 * @bw_data: Buffer holding valid pfs and bw limits 6110 * @cmd_details: pointer to command details 6111 * 6112 * Configure partitions guaranteed/max bw 6113 **/ 6114 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 6115 struct i40e_aqc_configure_partition_bw_data *bw_data, 6116 struct i40e_asq_cmd_details *cmd_details) 6117 { 6118 enum i40e_status_code status; 6119 struct i40e_aq_desc desc; 6120 u16 bwd_size = sizeof(*bw_data); 6121 6122 i40e_fill_default_direct_cmd_desc(&desc, 6123 i40e_aqc_opc_configure_partition_bw); 6124 6125 /* Indirect command */ 6126 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6127 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6128 6129 desc.datalen = CPU_TO_LE16(bwd_size); 6130 6131 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 6132 6133 return status; 6134 } 6135 6136 /** 6137 * i40e_read_phy_register_clause22 6138 * @hw: pointer to the HW structure 6139 * @reg: register address in the page 6140 * @phy_addr: PHY address on MDIO interface 6141 * @value: PHY register value 6142 * 6143 * Reads specified PHY register value 6144 **/ 6145 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 6146 u16 reg, u8 phy_addr, u16 *value) 6147 { 6148 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6149 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6150 u32 command = 0; 6151 u16 retry = 1000; 6152 6153 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6154 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6155 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 6156 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6157 (I40E_GLGEN_MSCA_MDICMD_MASK); 6158 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6159 do { 6160 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6161 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6162 status = I40E_SUCCESS; 6163 break; 6164 } 6165 i40e_usec_delay(10); 6166 retry--; 6167 } while (retry); 6168 6169 if (status) { 6170 i40e_debug(hw, I40E_DEBUG_PHY, 6171 "PHY: Can't write command to external PHY.\n"); 6172 } else { 6173 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6174 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6175 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6176 } 6177 6178 return status; 6179 } 6180 6181 /** 6182 * i40e_write_phy_register_clause22 6183 * @hw: pointer to the HW structure 6184 * @reg: register address in the page 6185 * @phy_addr: PHY address on MDIO interface 6186 * @value: PHY register value 6187 * 6188 * Writes specified PHY register value 6189 **/ 6190 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6191 u16 reg, u8 phy_addr, u16 value) 6192 { 6193 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6194 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6195 u32 command = 0; 6196 u16 retry = 1000; 6197 6198 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6199 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6200 6201 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6202 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6203 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6204 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6205 (I40E_GLGEN_MSCA_MDICMD_MASK); 6206 6207 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6208 do { 6209 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6210 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6211 status = I40E_SUCCESS; 6212 break; 6213 } 6214 i40e_usec_delay(10); 6215 retry--; 6216 } while (retry); 6217 6218 return status; 6219 } 6220 6221 /** 6222 * i40e_read_phy_register_clause45 6223 * @hw: pointer to the HW structure 6224 * @page: registers page number 6225 * @reg: register address in the page 6226 * @phy_addr: PHY address on MDIO interface 6227 * @value: PHY register value 6228 * 6229 * Reads specified PHY register value 6230 **/ 6231 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6232 u8 page, u16 reg, u8 phy_addr, u16 *value) 6233 { 6234 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6235 u32 command = 0; 6236 u16 retry = 1000; 6237 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6238 6239 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6240 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6241 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6242 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6243 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6244 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6245 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6246 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6247 do { 6248 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6249 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6250 status = I40E_SUCCESS; 6251 break; 6252 } 6253 i40e_usec_delay(10); 6254 retry--; 6255 } while (retry); 6256 6257 if (status) { 6258 i40e_debug(hw, I40E_DEBUG_PHY, 6259 "PHY: Can't write command to external PHY.\n"); 6260 goto phy_read_end; 6261 } 6262 6263 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6264 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6265 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6266 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6267 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6268 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6269 status = I40E_ERR_TIMEOUT; 6270 retry = 1000; 6271 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6272 do { 6273 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6274 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6275 status = I40E_SUCCESS; 6276 break; 6277 } 6278 i40e_usec_delay(10); 6279 retry--; 6280 } while (retry); 6281 6282 if (!status) { 6283 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6284 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6285 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6286 } else { 6287 i40e_debug(hw, I40E_DEBUG_PHY, 6288 "PHY: Can't read register value from external PHY.\n"); 6289 } 6290 6291 phy_read_end: 6292 return status; 6293 } 6294 6295 /** 6296 * i40e_write_phy_register_clause45 6297 * @hw: pointer to the HW structure 6298 * @page: registers page number 6299 * @reg: register address in the page 6300 * @phy_addr: PHY address on MDIO interface 6301 * @value: PHY register value 6302 * 6303 * Writes value to specified PHY register 6304 **/ 6305 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6306 u8 page, u16 reg, u8 phy_addr, u16 value) 6307 { 6308 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6309 u32 command = 0; 6310 u16 retry = 1000; 6311 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6312 6313 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6314 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6315 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6316 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6317 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6318 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6319 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6320 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6321 do { 6322 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6323 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6324 status = I40E_SUCCESS; 6325 break; 6326 } 6327 i40e_usec_delay(10); 6328 retry--; 6329 } while (retry); 6330 if (status) { 6331 i40e_debug(hw, I40E_DEBUG_PHY, 6332 "PHY: Can't write command to external PHY.\n"); 6333 goto phy_write_end; 6334 } 6335 6336 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6337 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6338 6339 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6340 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6341 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6342 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6343 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6344 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6345 status = I40E_ERR_TIMEOUT; 6346 retry = 1000; 6347 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6348 do { 6349 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6350 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6351 status = I40E_SUCCESS; 6352 break; 6353 } 6354 i40e_usec_delay(10); 6355 retry--; 6356 } while (retry); 6357 6358 phy_write_end: 6359 return status; 6360 } 6361 6362 /** 6363 * i40e_write_phy_register 6364 * @hw: pointer to the HW structure 6365 * @page: registers page number 6366 * @reg: register address in the page 6367 * @phy_addr: PHY address on MDIO interface 6368 * @value: PHY register value 6369 * 6370 * Writes value to specified PHY register 6371 **/ 6372 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6373 u8 page, u16 reg, u8 phy_addr, u16 value) 6374 { 6375 enum i40e_status_code status; 6376 6377 switch (hw->device_id) { 6378 case I40E_DEV_ID_1G_BASE_T_X722: 6379 status = i40e_write_phy_register_clause22(hw, 6380 reg, phy_addr, value); 6381 break; 6382 case I40E_DEV_ID_10G_BASE_T: 6383 case I40E_DEV_ID_10G_BASE_T4: 6384 case I40E_DEV_ID_10G_BASE_T_X722: 6385 case I40E_DEV_ID_25G_B: 6386 case I40E_DEV_ID_25G_SFP28: 6387 status = i40e_write_phy_register_clause45(hw, 6388 page, reg, phy_addr, value); 6389 break; 6390 default: 6391 status = I40E_ERR_UNKNOWN_PHY; 6392 break; 6393 } 6394 6395 return status; 6396 } 6397 6398 /** 6399 * i40e_read_phy_register 6400 * @hw: pointer to the HW structure 6401 * @page: registers page number 6402 * @reg: register address in the page 6403 * @phy_addr: PHY address on MDIO interface 6404 * @value: PHY register value 6405 * 6406 * Reads specified PHY register value 6407 **/ 6408 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6409 u8 page, u16 reg, u8 phy_addr, u16 *value) 6410 { 6411 enum i40e_status_code status; 6412 6413 switch (hw->device_id) { 6414 case I40E_DEV_ID_1G_BASE_T_X722: 6415 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6416 value); 6417 break; 6418 case I40E_DEV_ID_10G_BASE_T: 6419 case I40E_DEV_ID_10G_BASE_T4: 6420 case I40E_DEV_ID_10G_BASE_T_X722: 6421 case I40E_DEV_ID_25G_B: 6422 case I40E_DEV_ID_25G_SFP28: 6423 status = i40e_read_phy_register_clause45(hw, page, reg, 6424 phy_addr, value); 6425 break; 6426 default: 6427 status = I40E_ERR_UNKNOWN_PHY; 6428 break; 6429 } 6430 6431 return status; 6432 } 6433 6434 /** 6435 * i40e_get_phy_address 6436 * @hw: pointer to the HW structure 6437 * @dev_num: PHY port num that address we want 6438 * 6439 * Gets PHY address for current port 6440 **/ 6441 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6442 { 6443 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6444 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6445 6446 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6447 } 6448 6449 /** 6450 * i40e_blink_phy_led 6451 * @hw: pointer to the HW structure 6452 * @time: time how long led will blinks in secs 6453 * @interval: gap between LED on and off in msecs 6454 * 6455 * Blinks PHY link LED 6456 **/ 6457 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6458 u32 time, u32 interval) 6459 { 6460 enum i40e_status_code status = I40E_SUCCESS; 6461 u32 i; 6462 u16 led_ctl = 0; 6463 u16 gpio_led_port; 6464 u16 led_reg; 6465 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6466 u8 phy_addr = 0; 6467 u8 port_num; 6468 6469 i = rd32(hw, I40E_PFGEN_PORTNUM); 6470 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6471 phy_addr = i40e_get_phy_address(hw, port_num); 6472 6473 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6474 led_addr++) { 6475 status = i40e_read_phy_register_clause45(hw, 6476 I40E_PHY_COM_REG_PAGE, 6477 led_addr, phy_addr, 6478 &led_reg); 6479 if (status) 6480 goto phy_blinking_end; 6481 led_ctl = led_reg; 6482 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6483 led_reg = 0; 6484 status = i40e_write_phy_register_clause45(hw, 6485 I40E_PHY_COM_REG_PAGE, 6486 led_addr, phy_addr, 6487 led_reg); 6488 if (status) 6489 goto phy_blinking_end; 6490 break; 6491 } 6492 } 6493 6494 if (time > 0 && interval > 0) { 6495 for (i = 0; i < time * 1000; i += interval) { 6496 status = i40e_read_phy_register_clause45(hw, 6497 I40E_PHY_COM_REG_PAGE, 6498 led_addr, phy_addr, &led_reg); 6499 if (status) 6500 goto restore_config; 6501 if (led_reg & I40E_PHY_LED_MANUAL_ON) 6502 led_reg = 0; 6503 else 6504 led_reg = I40E_PHY_LED_MANUAL_ON; 6505 status = i40e_write_phy_register_clause45(hw, 6506 I40E_PHY_COM_REG_PAGE, 6507 led_addr, phy_addr, led_reg); 6508 if (status) 6509 goto restore_config; 6510 i40e_msec_delay(interval); 6511 } 6512 } 6513 6514 restore_config: 6515 status = i40e_write_phy_register_clause45(hw, 6516 I40E_PHY_COM_REG_PAGE, 6517 led_addr, phy_addr, led_ctl); 6518 6519 phy_blinking_end: 6520 return status; 6521 } 6522 6523 /** 6524 * i40e_led_get_reg - read LED register 6525 * @hw: pointer to the HW structure 6526 * @led_addr: LED register address 6527 * @reg_val: read register value 6528 **/ 6529 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 6530 u32 *reg_val) 6531 { 6532 enum i40e_status_code status; 6533 u8 phy_addr = 0; 6534 6535 *reg_val = 0; 6536 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6537 status = i40e_aq_get_phy_register(hw, 6538 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6539 I40E_PHY_COM_REG_PAGE, 6540 I40E_PHY_LED_PROV_REG_1, 6541 reg_val, NULL); 6542 } else { 6543 phy_addr = i40e_get_phy_address(hw, hw->port); 6544 status = i40e_read_phy_register_clause45(hw, 6545 I40E_PHY_COM_REG_PAGE, 6546 led_addr, phy_addr, 6547 (u16 *)reg_val); 6548 } 6549 return status; 6550 } 6551 6552 /** 6553 * i40e_led_set_reg - write LED register 6554 * @hw: pointer to the HW structure 6555 * @led_addr: LED register address 6556 * @reg_val: register value to write 6557 **/ 6558 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 6559 u32 reg_val) 6560 { 6561 enum i40e_status_code status; 6562 u8 phy_addr = 0; 6563 6564 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6565 status = i40e_aq_set_phy_register(hw, 6566 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6567 I40E_PHY_COM_REG_PAGE, 6568 I40E_PHY_LED_PROV_REG_1, 6569 reg_val, NULL); 6570 } else { 6571 phy_addr = i40e_get_phy_address(hw, hw->port); 6572 status = i40e_write_phy_register_clause45(hw, 6573 I40E_PHY_COM_REG_PAGE, 6574 led_addr, phy_addr, 6575 (u16)reg_val); 6576 } 6577 6578 return status; 6579 } 6580 6581 /** 6582 * i40e_led_get_phy - return current on/off mode 6583 * @hw: pointer to the hw struct 6584 * @led_addr: address of led register to use 6585 * @val: original value of register to use 6586 * 6587 **/ 6588 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 6589 u16 *val) 6590 { 6591 enum i40e_status_code status = I40E_SUCCESS; 6592 u16 gpio_led_port; 6593 u32 reg_val_aq; 6594 u16 temp_addr; 6595 u8 phy_addr = 0; 6596 u16 reg_val; 6597 6598 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6599 status = i40e_aq_get_phy_register(hw, 6600 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6601 I40E_PHY_COM_REG_PAGE, 6602 I40E_PHY_LED_PROV_REG_1, 6603 ®_val_aq, NULL); 6604 if (status == I40E_SUCCESS) 6605 *val = (u16)reg_val_aq; 6606 return status; 6607 } 6608 temp_addr = I40E_PHY_LED_PROV_REG_1; 6609 phy_addr = i40e_get_phy_address(hw, hw->port); 6610 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6611 temp_addr++) { 6612 status = i40e_read_phy_register_clause45(hw, 6613 I40E_PHY_COM_REG_PAGE, 6614 temp_addr, phy_addr, 6615 ®_val); 6616 if (status) 6617 return status; 6618 *val = reg_val; 6619 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 6620 *led_addr = temp_addr; 6621 break; 6622 } 6623 } 6624 return status; 6625 } 6626 6627 /** 6628 * i40e_led_set_phy 6629 * @hw: pointer to the HW structure 6630 * @on: TRUE or FALSE 6631 * @led_addr: address of led register to use 6632 * @mode: original val plus bit for set or ignore 6633 * 6634 * Set led's on or off when controlled by the PHY 6635 * 6636 **/ 6637 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 6638 u16 led_addr, u32 mode) 6639 { 6640 enum i40e_status_code status = I40E_SUCCESS; 6641 u32 led_ctl = 0; 6642 u32 led_reg = 0; 6643 6644 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6645 if (status) 6646 return status; 6647 led_ctl = led_reg; 6648 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6649 led_reg = 0; 6650 status = i40e_led_set_reg(hw, led_addr, led_reg); 6651 if (status) 6652 return status; 6653 } 6654 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6655 if (status) 6656 goto restore_config; 6657 if (on) 6658 led_reg = I40E_PHY_LED_MANUAL_ON; 6659 else 6660 led_reg = 0; 6661 status = i40e_led_set_reg(hw, led_addr, led_reg); 6662 if (status) 6663 goto restore_config; 6664 if (mode & I40E_PHY_LED_MODE_ORIG) { 6665 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 6666 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6667 } 6668 return status; 6669 6670 restore_config: 6671 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6672 return status; 6673 } 6674 6675 /** 6676 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 6677 * @hw: pointer to the hw struct 6678 * @reg_addr: register address 6679 * @reg_val: ptr to register value 6680 * @cmd_details: pointer to command details structure or NULL 6681 * 6682 * Use the firmware to read the Rx control register, 6683 * especially useful if the Rx unit is under heavy pressure 6684 **/ 6685 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 6686 u32 reg_addr, u32 *reg_val, 6687 struct i40e_asq_cmd_details *cmd_details) 6688 { 6689 struct i40e_aq_desc desc; 6690 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 6691 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6692 enum i40e_status_code status; 6693 6694 if (reg_val == NULL) 6695 return I40E_ERR_PARAM; 6696 6697 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 6698 6699 cmd_resp->address = CPU_TO_LE32(reg_addr); 6700 6701 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6702 6703 if (status == I40E_SUCCESS) 6704 *reg_val = LE32_TO_CPU(cmd_resp->value); 6705 6706 return status; 6707 } 6708 6709 /** 6710 * i40e_read_rx_ctl - read from an Rx control register 6711 * @hw: pointer to the hw struct 6712 * @reg_addr: register address 6713 **/ 6714 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 6715 { 6716 enum i40e_status_code status = I40E_SUCCESS; 6717 bool use_register; 6718 int retry = 5; 6719 u32 val = 0; 6720 6721 use_register = (((hw->aq.api_maj_ver == 1) && 6722 (hw->aq.api_min_ver < 5)) || 6723 (hw->mac.type == I40E_MAC_X722)); 6724 if (!use_register) { 6725 do_retry: 6726 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 6727 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6728 i40e_msec_delay(1); 6729 retry--; 6730 goto do_retry; 6731 } 6732 } 6733 6734 /* if the AQ access failed, try the old-fashioned way */ 6735 if (status || use_register) 6736 val = rd32(hw, reg_addr); 6737 6738 return val; 6739 } 6740 6741 /** 6742 * i40e_aq_rx_ctl_write_register 6743 * @hw: pointer to the hw struct 6744 * @reg_addr: register address 6745 * @reg_val: register value 6746 * @cmd_details: pointer to command details structure or NULL 6747 * 6748 * Use the firmware to write to an Rx control register, 6749 * especially useful if the Rx unit is under heavy pressure 6750 **/ 6751 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 6752 u32 reg_addr, u32 reg_val, 6753 struct i40e_asq_cmd_details *cmd_details) 6754 { 6755 struct i40e_aq_desc desc; 6756 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 6757 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6758 enum i40e_status_code status; 6759 6760 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 6761 6762 cmd->address = CPU_TO_LE32(reg_addr); 6763 cmd->value = CPU_TO_LE32(reg_val); 6764 6765 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6766 6767 return status; 6768 } 6769 6770 /** 6771 * i40e_write_rx_ctl - write to an Rx control register 6772 * @hw: pointer to the hw struct 6773 * @reg_addr: register address 6774 * @reg_val: register value 6775 **/ 6776 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 6777 { 6778 enum i40e_status_code status = I40E_SUCCESS; 6779 bool use_register; 6780 int retry = 5; 6781 6782 use_register = (((hw->aq.api_maj_ver == 1) && 6783 (hw->aq.api_min_ver < 5)) || 6784 (hw->mac.type == I40E_MAC_X722)); 6785 if (!use_register) { 6786 do_retry: 6787 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 6788 reg_val, NULL); 6789 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6790 i40e_msec_delay(1); 6791 retry--; 6792 goto do_retry; 6793 } 6794 } 6795 6796 /* if the AQ access failed, try the old-fashioned way */ 6797 if (status || use_register) 6798 wr32(hw, reg_addr, reg_val); 6799 } 6800 6801 6802 /** 6803 * i40e_aq_set_phy_register 6804 * @hw: pointer to the hw struct 6805 * @phy_select: select which phy should be accessed 6806 * @dev_addr: PHY device address 6807 * @reg_addr: PHY register address 6808 * @reg_val: new register value 6809 * @cmd_details: pointer to command details structure or NULL 6810 * 6811 * Write the external PHY register. 6812 **/ 6813 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw, 6814 u8 phy_select, u8 dev_addr, 6815 u32 reg_addr, u32 reg_val, 6816 struct i40e_asq_cmd_details *cmd_details) 6817 { 6818 struct i40e_aq_desc desc; 6819 struct i40e_aqc_phy_register_access *cmd = 6820 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6821 enum i40e_status_code status; 6822 6823 i40e_fill_default_direct_cmd_desc(&desc, 6824 i40e_aqc_opc_set_phy_register); 6825 6826 cmd->phy_interface = phy_select; 6827 cmd->dev_addres = dev_addr; 6828 cmd->reg_address = reg_addr; 6829 cmd->reg_value = reg_val; 6830 6831 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6832 6833 return status; 6834 } 6835 6836 /** 6837 * i40e_aq_get_phy_register 6838 * @hw: pointer to the hw struct 6839 * @phy_select: select which phy should be accessed 6840 * @dev_addr: PHY device address 6841 * @reg_addr: PHY register address 6842 * @reg_val: read register value 6843 * @cmd_details: pointer to command details structure or NULL 6844 * 6845 * Read the external PHY register. 6846 **/ 6847 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw, 6848 u8 phy_select, u8 dev_addr, 6849 u32 reg_addr, u32 *reg_val, 6850 struct i40e_asq_cmd_details *cmd_details) 6851 { 6852 struct i40e_aq_desc desc; 6853 struct i40e_aqc_phy_register_access *cmd = 6854 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6855 enum i40e_status_code status; 6856 6857 i40e_fill_default_direct_cmd_desc(&desc, 6858 i40e_aqc_opc_get_phy_register); 6859 6860 cmd->phy_interface = phy_select; 6861 cmd->dev_addres = dev_addr; 6862 cmd->reg_address = reg_addr; 6863 6864 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6865 if (!status) 6866 *reg_val = cmd->reg_value; 6867 6868 return status; 6869 } 6870 6871 /** 6872 * i40e_aq_set_arp_proxy_config 6873 * @hw: pointer to the HW structure 6874 * @proxy_config: pointer to proxy config command table struct 6875 * @cmd_details: pointer to command details 6876 * 6877 * Set ARP offload parameters from pre-populated 6878 * i40e_aqc_arp_proxy_data struct 6879 **/ 6880 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 6881 struct i40e_aqc_arp_proxy_data *proxy_config, 6882 struct i40e_asq_cmd_details *cmd_details) 6883 { 6884 struct i40e_aq_desc desc; 6885 enum i40e_status_code status; 6886 6887 if (!proxy_config) 6888 return I40E_ERR_PARAM; 6889 6890 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 6891 6892 desc.params.external.addr_high = 6893 CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)proxy_config)); 6894 desc.params.external.addr_low = 6895 CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)proxy_config)); 6896 6897 status = i40e_asq_send_command(hw, &desc, proxy_config, 6898 sizeof(struct i40e_aqc_arp_proxy_data), 6899 cmd_details); 6900 6901 return status; 6902 } 6903 6904 /** 6905 * i40e_aq_opc_set_ns_proxy_table_entry 6906 * @hw: pointer to the HW structure 6907 * @ns_proxy_table_entry: pointer to NS table entry command struct 6908 * @cmd_details: pointer to command details 6909 * 6910 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 6911 * from pre-populated i40e_aqc_ns_proxy_data struct 6912 **/ 6913 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 6914 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 6915 struct i40e_asq_cmd_details *cmd_details) 6916 { 6917 struct i40e_aq_desc desc; 6918 enum i40e_status_code status; 6919 6920 if (!ns_proxy_table_entry) 6921 return I40E_ERR_PARAM; 6922 6923 i40e_fill_default_direct_cmd_desc(&desc, 6924 i40e_aqc_opc_set_ns_proxy_table_entry); 6925 6926 desc.params.external.addr_high = 6927 CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)ns_proxy_table_entry)); 6928 desc.params.external.addr_low = 6929 CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)ns_proxy_table_entry)); 6930 6931 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 6932 sizeof(struct i40e_aqc_ns_proxy_data), 6933 cmd_details); 6934 6935 return status; 6936 } 6937 6938 /** 6939 * i40e_aq_set_clear_wol_filter 6940 * @hw: pointer to the hw struct 6941 * @filter_index: index of filter to modify (0-7) 6942 * @filter: buffer containing filter to be set 6943 * @set_filter: TRUE to set filter, FALSE to clear filter 6944 * @no_wol_tco: if TRUE, pass through packets cannot cause wake-up 6945 * if FALSE, pass through packets may cause wake-up 6946 * @filter_valid: TRUE if filter action is valid 6947 * @no_wol_tco_valid: TRUE if no WoL in TCO traffic action valid 6948 * @cmd_details: pointer to command details structure or NULL 6949 * 6950 * Set or clear WoL filter for port attached to the PF 6951 **/ 6952 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 6953 u8 filter_index, 6954 struct i40e_aqc_set_wol_filter_data *filter, 6955 bool set_filter, bool no_wol_tco, 6956 bool filter_valid, bool no_wol_tco_valid, 6957 struct i40e_asq_cmd_details *cmd_details) 6958 { 6959 struct i40e_aq_desc desc; 6960 struct i40e_aqc_set_wol_filter *cmd = 6961 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 6962 enum i40e_status_code status; 6963 u16 cmd_flags = 0; 6964 u16 valid_flags = 0; 6965 u16 buff_len = 0; 6966 6967 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 6968 6969 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 6970 return I40E_ERR_PARAM; 6971 cmd->filter_index = CPU_TO_LE16(filter_index); 6972 6973 if (set_filter) { 6974 if (!filter) 6975 return I40E_ERR_PARAM; 6976 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 6977 buff_len = sizeof(*filter); 6978 } 6979 if (no_wol_tco) 6980 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 6981 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 6982 6983 if (filter_valid) 6984 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 6985 if (no_wol_tco_valid) 6986 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 6987 cmd->valid_flags = CPU_TO_LE16(valid_flags); 6988 6989 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)filter)); 6990 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)filter)); 6991 6992 status = i40e_asq_send_command(hw, &desc, filter, 6993 buff_len, cmd_details); 6994 6995 return status; 6996 } 6997 6998 /** 6999 * i40e_aq_get_wake_event_reason 7000 * @hw: pointer to the hw struct 7001 * @wake_reason: return value, index of matching filter 7002 * @cmd_details: pointer to command details structure or NULL 7003 * 7004 * Get information for the reason of a Wake Up event 7005 **/ 7006 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 7007 u16 *wake_reason, 7008 struct i40e_asq_cmd_details *cmd_details) 7009 { 7010 struct i40e_aq_desc desc; 7011 struct i40e_aqc_get_wake_reason_completion *resp = 7012 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 7013 enum i40e_status_code status; 7014 7015 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 7016 7017 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 7018 7019 if (status == I40E_SUCCESS) 7020 *wake_reason = LE16_TO_CPU(resp->wake_reason); 7021 7022 return status; 7023 } 7024 7025