1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_HXGE_HXGE_TXDMA_HW_H 28 #define _SYS_HXGE_HXGE_TXDMA_HW_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <hxge_defs.h> 37 #include <hxge_tdc_hw.h> 38 39 /* 40 * Transmit Packet Descriptor Structure 41 * See Hydra PRM (Chapter 8, Section 8.1.1) 42 */ 43 typedef union _tx_desc_t { 44 uint64_t value; 45 struct { 46 #if defined(_BIG_ENDIAN) 47 uint32_t sop:1; 48 uint32_t mark:1; 49 uint32_t num_ptr:4; 50 uint32_t rsvd:1; 51 uint32_t tr_len:13; 52 uint32_t sad:12; 53 uint32_t sad_l:32; 54 #else 55 uint32_t sad_l:32; 56 uint32_t sad:12; 57 uint32_t tr_len:13; 58 uint32_t rsvd:1; 59 uint32_t num_ptr:4; 60 uint32_t mark:1; 61 uint32_t sop:1; 62 #endif 63 } bits; 64 } tx_desc_t, *p_tx_desc_t; 65 66 /* 67 * TDC Ring Configuration 68 */ 69 #define TDC_TDR_CFG_STADDR_SHIFT 6 /* bits 18:6 */ 70 #define TDC_TDR_CFG_STADDR_MASK 0x000000000007FFC0ULL 71 #define TDC_TDR_CFG_ADDR_MASK 0x00000FFFFFFFFFC0ULL 72 #define TDC_TDR_CFG_STADDR_BASE_SHIFT 19 /* bits 43:19 */ 73 #define TDC_TDR_CFG_STADDR_BASE_MASK 0x00000FFFFFF80000ULL 74 #define TDC_TDR_CFG_LEN_SHIFT 53 /* bits 63:53 */ 75 #define TDC_TDR_CFG_LEN_MASK 0xFFE0000000000000ULL 76 #define TDC_TDR_RST_SHIFT 46 77 #define TDC_TDR_RST_MASK 0x0000400000000000ULL 78 79 /* 80 * Transmit Event Mask 81 */ 82 #define TDC_INT_MASK_MK_MASK 0x0000000000008000ULL 83 84 /* 85 * Trasnmit Mailbox High 86 */ 87 #define TDC_MBH_SHIFT 0 /* bit 11:0 */ 88 #define TDC_MBH_ADDR_SHIFT 32 /* bit 43:32 */ 89 #define TDC_MBH_MASK 0x0000000000000FFFULL 90 91 /* 92 * Trasnmit Mailbox Low 93 */ 94 #define TDC_MBL_SHIFT 6 /* bit 31:6 */ 95 #define TDC_MBL_MASK 0x00000000FFFFFFC0ULL 96 97 #define TXDMA_MAILBOX_BYTE_LENGTH 64 98 #define TXDMA_MAILBOX_UNUSED 24 99 100 typedef struct _txdma_mailbox_t { 101 tdc_stat_t tx_cs; /* 8 bytes */ 102 tdc_tdr_pre_head_t tx_dma_pre_st; /* 8 bytes */ 103 tdc_tdr_head_t tx_ring_hdl; /* 8 bytes */ 104 tdc_tdr_kick_t tx_ring_kick; /* 8 bytes */ 105 uint32_t tx_rng_err_logh; /* 4 bytes */ 106 uint32_t tx_rng_err_logl; /* 4 bytes */ 107 uint8_t resv[TXDMA_MAILBOX_UNUSED]; 108 } txdma_mailbox_t, *p_txdma_mailbox_t; 109 110 /* 111 * Internal Transmit Packet Format (16 bytes) 112 */ 113 #define TX_PKT_HEADER_SIZE 16 114 #define TX_MAX_GATHER_POINTERS 15 115 #define TX_GATHER_POINTERS_THRESHOLD 8 116 /* 117 * There is bugs in the hardware 118 * and max sfter len is changed from 4096 to 4076. 119 * 120 * Jumbo from 9500 to 9216 121 */ 122 #define TX_MAX_TRANSFER_LENGTH 4076 123 #define TX_JUMBO_MTU 9216 124 125 #define TX_PKT_HEADER_PAD_SHIFT 0 /* bit 2:0 */ 126 #define TX_PKT_HEADER_PAD_MASK 0x0000000000000007ULL 127 #define TX_PKT_HEADER_TOT_XFER_LEN_SHIFT 16 /* bit 16:29 */ 128 #define TX_PKT_HEADER_TOT_XFER_LEN_MASK 0x000000000000FFF8ULL 129 #define TX_PKT_HEADER_L4STUFF_SHIFT 32 /* bit 37:32 */ 130 #define TX_PKT_HEADER_L4STUFF_MASK 0x0000003F00000000ULL 131 #define TX_PKT_HEADER_L4START_SHIFT 40 /* bit 45:40 */ 132 #define TX_PKT_HEADER_L4START_MASK 0x00003F0000000000ULL 133 #define TX_PKT_HEADER_L3START_SHIFT 48 /* bit 45:40 */ 134 #define TX_PKT_HEADER_IHL_SHIFT 52 /* bit 52 */ 135 #define TX_PKT_HEADER_VLAN__SHIFT 56 /* bit 56 */ 136 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SHIFT 57 /* bit 57 */ 137 #define TX_PKT_HEADER_LLC_SHIFT 57 /* bit 57 */ 138 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SET 0x0200000000000000ULL 139 #define TX_PKT_HEADER_TCP_UDP_CRC32C_MASK 0x0200000000000000ULL 140 #define TX_PKT_HEADER_L4_PROTO_OP_SHIFT 2 /* bit 59:58 */ 141 #define TX_PKT_HEADER_L4_PROTO_OP_MASK 0x0C00000000000000ULL 142 #define TX_PKT_HEADER_V4_HDR_CS_SHIFT 60 /* bit 60 */ 143 #define TX_PKT_HEADER_V4_HDR_CS_SET 0x1000000000000000ULL 144 #define TX_PKT_HEADER_V4_HDR_CS_MASK 0x1000000000000000ULL 145 #define TX_PKT_HEADER_IP_VER_SHIFT 61 /* bit 61 */ 146 #define TX_PKT_HEADER_IP_VER_MASK 0x2000000000000000ULL 147 #define TX_PKT_HEADER_PKT_TYPE_SHIFT 62 /* bit 62 */ 148 #define TX_PKT_HEADER_PKT_TYPE_MASK 0x4000000000000000ULL 149 150 /* L4 Prototol Operations */ 151 #define TX_PKT_L4_PROTO_OP_NOP 0x00 152 #define TX_PKT_L4_PROTO_OP_FULL_L4_CSUM 0x01 153 #define TX_PKT_L4_PROTO_OP_L4_PAYLOAD_CSUM 0x02 154 #define TX_PKT_L4_PROTO_OP_SCTP_CRC32 0x04 155 156 /* Transmit Packet Types */ 157 #define TX_PKT_PKT_TYPE_NOP 0x00 158 #define TX_PKT_PKT_TYPE_TCP 0x01 159 #define TX_PKT_PKT_TYPE_UDP 0x02 160 #define TX_PKT_PKT_TYPE_SCTP 0x03 161 162 typedef union _tx_pkt_header_t { 163 uint64_t value; 164 struct { 165 #if defined(_BIG_ENDIAN) 166 uint32_t cksum_en_pkt_type:2; 167 uint32_t ip_ver:1; 168 uint32_t rsrvd:4; 169 uint32_t vlan:1; 170 uint32_t ihl:4; 171 uint32_t l3start:4; 172 uint32_t rsvrvd1:2; 173 uint32_t l4start:6; 174 uint32_t rsvrvd2:2; 175 uint32_t l4stuff:6; 176 uint32_t rsvrvd3:2; 177 uint32_t tot_xfer_len:14; 178 uint32_t rsrrvd4:13; 179 uint32_t pad:3; 180 #else 181 uint32_t pad:3; 182 uint32_t rsrrvd4:13; 183 uint32_t tot_xfer_len:14; 184 uint32_t rsvrvd3:2; 185 uint32_t l4stuff:6; 186 uint32_t rsvrvd2:2; 187 uint32_t l4start:6; 188 uint32_t rsvrvd1:2; 189 uint32_t l3start:4; 190 uint32_t ihl:4; 191 uint32_t vlan:1; 192 uint32_t rsrvd:4; 193 uint32_t ip_ver:1; 194 uint32_t cksum_en_pkt_type:2; 195 #endif 196 } bits; 197 } tx_pkt_header_t, *p_tx_pkt_header_t; 198 199 typedef struct _tx_pkt_hdr_all_t { 200 tx_pkt_header_t pkthdr; 201 uint64_t reserved; 202 } tx_pkt_hdr_all_t, *p_tx_pkt_hdr_all_t; 203 204 205 #ifdef __cplusplus 206 } 207 #endif 208 209 #endif /* _SYS_HXGE_HXGE_TXDMA_HW_H */ 210