1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HXGE_TDC_HW_H 27 #define _HXGE_TDC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define TDC_BASE_ADDR 0X00400000 36 37 #define TDC_PAGE_HANDLE (TDC_BASE_ADDR + 0x8) 38 #define TDC_TDR_CFG (TDC_BASE_ADDR + 0x20) 39 #define TDC_TDR_HEAD (TDC_BASE_ADDR + 0x28) 40 #define TDC_TDR_PRE_HEAD (TDC_BASE_ADDR + 0x30) 41 #define TDC_TDR_KICK (TDC_BASE_ADDR + 0x38) 42 #define TDC_INT_MASK (TDC_BASE_ADDR + 0x40) 43 #define TDC_STAT (TDC_BASE_ADDR + 0x48) 44 #define TDC_MBH (TDC_BASE_ADDR + 0x50) 45 #define TDC_MBL (TDC_BASE_ADDR + 0x58) 46 #define TDC_BYTE_CNT (TDC_BASE_ADDR + 0x80) 47 #define TDC_TDR_QLEN (TDC_BASE_ADDR + 0x88) 48 #define TDC_RTAB_PTR (TDC_BASE_ADDR + 0x90) 49 #define TDC_DROP_CNT (TDC_BASE_ADDR + 0x98) 50 #define TDC_LAST_PKT_RBUF_PTRS (TDC_BASE_ADDR + 0xA8) 51 #define TDC_PREF_CMD (TDC_BASE_ADDR + 0x100) 52 #define TDC_PREF_DATA (TDC_BASE_ADDR + 0x108) 53 #define TDC_PREF_PAR_DATA (TDC_BASE_ADDR + 0x110) 54 #define TDC_REORD_BUF_CMD (TDC_BASE_ADDR + 0x120) 55 #define TDC_REORD_BUF_DATA (TDC_BASE_ADDR + 0x128) 56 #define TDC_REORD_BUF_ECC_DATA (TDC_BASE_ADDR + 0x130) 57 #define TDC_REORD_TBL_CMD (TDC_BASE_ADDR + 0x140) 58 #define TDC_REORD_TBL_DATA_LO (TDC_BASE_ADDR + 0x148) 59 #define TDC_REORD_TBL_DATA_HI (TDC_BASE_ADDR + 0x150) 60 #define TDC_PREF_PAR_LOG (TDC_BASE_ADDR + 0x200) 61 #define TDC_REORD_BUF_ECC_LOG (TDC_BASE_ADDR + 0x208) 62 #define TDC_REORD_TBL_PAR_LOG (TDC_BASE_ADDR + 0x210) 63 #define TDC_FIFO_ERR_MASK (TDC_BASE_ADDR + 0x220) 64 #define TDC_FIFO_ERR_STAT (TDC_BASE_ADDR + 0x228) 65 #define TDC_FIFO_ERR_INT_DBG (TDC_BASE_ADDR + 0x230) 66 #define TDC_STAT_INT_DBG (TDC_BASE_ADDR + 0x240) 67 #define TDC_PKT_REQ_TID_TAG (TDC_BASE_ADDR + 0x250) 68 #define TDC_SOP_PREF_DESC_LOG (TDC_BASE_ADDR + 0x260) 69 #define TDC_PREF_DESC_LOG (TDC_BASE_ADDR + 0x268) 70 #define TDC_PEU_TXN_LOG (TDC_BASE_ADDR + 0x270) 71 #define TDC_DBG_TRAINING_VEC (TDC_BASE_ADDR + 0x300) 72 #define TDC_DBG_GRP_SEL (TDC_BASE_ADDR + 0x308) 73 74 75 /* 76 * Register: TdcPageHandle 77 * Logical Page Handle 78 * Description: Upper 20 bits [63:44] to use for all accesses over 79 * the PCI-E bus. Fields in this register are part of the dma 80 * configuration and cannot be changed once the dma is enabled. 81 * Fields: 82 * Page handle, bits [63:44] of all PCI-E transactions for this 83 * channel. 84 */ 85 typedef union { 86 uint64_t value; 87 struct { 88 #if defined(_BIG_ENDIAN) 89 uint64_t rsrvd:44; 90 uint64_t page_handle:20; 91 #else 92 uint64_t page_handle:20; 93 uint64_t rsrvd:44; 94 #endif 95 } bits; 96 } tdc_page_handle_t; 97 98 99 /* 100 * Register: TdcTdrCfg 101 * Transmit Ring Configuration 102 * Description: Configuration parameters for transmit DMA block. 103 * Software configures the location of the transmit ring in host 104 * memory, as well as its maximum size. Fields in this register are 105 * part of the dma configuration and cannot be changed once the dma 106 * is enabled. 107 * HW does not check for all configuration errors across different 108 * fields. 109 * The usage of enable, reset, and qst is as follows. Software 110 * should use the following sequence to reset a DMA channel. First, 111 * set DMA.enable to 0, wait for DMA.qst=1 and then, set DMA.reset to 112 * 1. After DMA.reset is cleared by hardware and the DMA.qst is set 113 * to 1, software may then start configuring the DMA channel. The 114 * DMA.enable can be set or cleared while the DMA is in operation. 115 * The state machines of the DMA may not have returned to its initial 116 * states yet after the DMA.enable bit is cleared. This condition is 117 * indicated by the value of the DMA.qst. An example of DMA.enable 118 * being cleared during operation is when a fatal error occurs. 119 * Fields: 120 * Bits [15:5] of the maximum number of entries in the Transmit 121 * Queue ring buffer. Bits [4:0] are always 0. Maximum number of 122 * entries is (2^16 - 32) and is limited by the staddr value. 123 * (len + staddr) should not exceed (2^16 - 32). 124 * Set to 1 to enable the Transmit DMA. On fatal errors, this bit 125 * will be cleared by hardware. This bit cannot be set if sw has 126 * not resolved any pending fatal error condition: i.e. any 127 * TdcStat ldf1 error bits remain set. 128 * Set to 1 to reset the DMA. Hardware will clear this bit after 129 * reset is completed. A reset will bring the sepecific DMA back 130 * to the power on state (including the DMA.en in this register). 131 * When set to 1, it indicates all state associated with the DMA 132 * are in its initial state following either dma reset or 133 * disable. Thus, once this is set to 1, sw could start to 134 * configure the DMA if needed. In an extreme case such as if a 135 * parity error on an EOP descriptor prevents recognition of the 136 * EOP, it is possible that the qst bit will not be set even 137 * though the dma engine has been disabled. 138 * Address bits [43:19] of the start address for the transmit 139 * ring buffer. The value in this field is dependent on len 140 * field. (len + staddr) should not exceed (2^16 - 32). 141 * Bits [18:6] of the start address for the transmit ring buffer. 142 * Bits [5:0] are assumed to be zero, or 64B aligned. 143 */ 144 typedef union { 145 uint64_t value; 146 struct { 147 #if defined(_BIG_ENDIAN) 148 uint64_t len:11; 149 uint64_t rsrvd:5; 150 uint64_t enable:1; 151 uint64_t reset:1; 152 uint64_t qst:1; 153 uint64_t rsrvd1:1; 154 uint64_t staddr_base:25; 155 uint64_t staddr:13; 156 uint64_t rsrvd2:6; 157 #else 158 uint64_t rsrvd2:6; 159 uint64_t staddr:13; 160 uint64_t staddr_base:25; 161 uint64_t rsrvd1:1; 162 uint64_t qst:1; 163 uint64_t reset:1; 164 uint64_t enable:1; 165 uint64_t rsrvd:5; 166 uint64_t len:11; 167 #endif 168 } bits; 169 } tdc_tdr_cfg_t; 170 171 172 /* 173 * Register: TdcTdrHead 174 * Transmit Ring Head 175 * Description: Read-only register software call poll to determine 176 * the current head of the transmit ring, from the tdcTxPkt block. 177 * Software uses this to know which Tdr entries have had their 178 * descriptors transmitted. These entries and their descriptors may 179 * then be reused by software. 180 * Fields: 181 * Hardware will toggle this bit every time the head is wrapped 182 * around the configured ring buffer. 183 * Entry in transmit ring which will be the next descriptor 184 * transmitted. Software should consider the Tdr full if head == 185 * TdcTdrKick::tail and wrap != TdcTdrKick::wrap. The ring is 186 * empty of head == TdcTdrKick::tail and wrap == 187 * TdcTdrKick::wrap. 188 */ 189 typedef union { 190 uint64_t value; 191 struct { 192 #if defined(_BIG_ENDIAN) 193 uint64_t rsrvd:47; 194 uint64_t wrap:1; 195 uint64_t head:16; 196 #else 197 uint64_t head:16; 198 uint64_t wrap:1; 199 uint64_t rsrvd:47; 200 #endif 201 } bits; 202 } tdc_tdr_head_t; 203 204 205 /* 206 * Register: TdcTdrPreHead 207 * Transmit Ring Prefetch Head 208 * Description: Read-only register software call poll to determine 209 * the current prefetch head of the transmit ring, from the tdcPktReq 210 * block. Transmit descriptors are prefetched into chip memory. 211 * Indicates next descriptor to be read from host memory. For debug 212 * use only. 213 * Fields: 214 * Hardware will toggle this bit every time the prefetch head is 215 * wrapped around the configured ring buffer. 216 * Entry in transmit ring which will be fetched next from host 217 * memory. 218 */ 219 typedef union { 220 uint64_t value; 221 struct { 222 #if defined(_BIG_ENDIAN) 223 uint64_t rsrvd:47; 224 uint64_t wrap:1; 225 uint64_t head:16; 226 #else 227 uint64_t head:16; 228 uint64_t wrap:1; 229 uint64_t rsrvd:47; 230 #endif 231 } bits; 232 } tdc_tdr_pre_head_t; 233 234 235 /* 236 * Register: TdcTdrKick 237 * Transmit Ring Kick 238 * Description: After posting transmit descriptors to the Transmit 239 * Ring, software updates the tail pointer to inform Hydra of the new 240 * descriptors. Software can only post descriptors through this 241 * register when the entire packet is in the ring. Otherwise, 242 * hardware dead-lock can occur. If an overflow kick occurs when the 243 * channel is disabled, tdcStat.txRngOflow (Transmit Ring Overflow) 244 * status is not set. 245 * Fields: 246 * Software needs to toggle this bit every time the tail is 247 * wrapped around the configured ring buffer. 248 * Entry where the next valid descriptor will be added (one entry 249 * past the last valid descriptor.) 250 */ 251 typedef union { 252 uint64_t value; 253 struct { 254 #if defined(_BIG_ENDIAN) 255 uint64_t rsrvd:47; 256 uint64_t wrap:1; 257 uint64_t tail:16; 258 #else 259 uint64_t tail:16; 260 uint64_t wrap:1; 261 uint64_t rsrvd:47; 262 #endif 263 } bits; 264 } tdc_tdr_kick_t; 265 266 267 /* 268 * Register: TdcIntMask 269 * Transmit Event Mask 270 * Description: The Tx DMA can generate a number of LDF events. The 271 * events can be enabled by software by setting the corresponding bit 272 * to 0. The default value of 1 means the event is masked and no LDF 273 * event is generated. 274 * Fields: 275 * Set to 0 to select the event to raise the LDF for packets 276 * marked. An LDF 0 event. 277 * Set to 0 to select the event to raise the LDF when poisoned 278 * completion or non-zero (unsuccessful) completion status 279 * received from PEU. An LDF 1 event. 280 * Set to 0 to select the event to raise the LDF when total bytes 281 * transmitted compared against pkt internal header bytes 282 * transmitted mismatch. An LDF 1 event. 283 * Set to 0 to select the event to raise the LDF when a runt 284 * packet is dropped (when VMAC does not allow runt packets to be 285 * padded). An LDF 1 event. 286 * Set to 0 to select the event to raise the LDF when the packet 287 * size exceeds hardware limit. An LDF 1 event. 288 * Set to 0 to select the event to raise the LDF to indicate 289 * Transmit Ring Overflow An LDF 1 event. 290 * Set to 0 to select the event to raise the LDF to indicate 291 * parity error on the tdr prefetch buffer occurred. An LDF 1 292 * event. 293 * Set to 0 to select the event to raise the LDF to indicate tdc 294 * received a response completion timeout from peu for tdr 295 * descriptor prefetch An LDF 1 event. 296 * Set to 0 to select the event to raise the LDF to indicate tdc 297 * received a response completion timeout from peu for packet 298 * data request An LDF 1 event. 299 * Set to 0 to select the event to raise the LDF to indicate tdc 300 * did not receive an SOP in the 1st descriptor as was expected 301 * or the numPtr in the 1st descriptor was set to 0. An LDF 1 302 * event. 303 * Set to 0 to select the event to raise the LDF to indicate tdc 304 * received an unexpected SOP descriptor error. An LDF 1 event. 305 */ 306 typedef union { 307 uint64_t value; 308 struct { 309 #if defined(_BIG_ENDIAN) 310 uint64_t rsrvd:48; 311 uint64_t marked:1; 312 uint64_t rsrvd1:5; 313 uint64_t peu_resp_err:1; 314 uint64_t pkt_size_hdr_err:1; 315 uint64_t runt_pkt_drop_err:1; 316 uint64_t pkt_size_err:1; 317 uint64_t tx_rng_oflow:1; 318 uint64_t pref_par_err:1; 319 uint64_t tdr_pref_cpl_to:1; 320 uint64_t pkt_cpl_to:1; 321 uint64_t invalid_sop:1; 322 uint64_t unexpected_sop:1; 323 #else 324 uint64_t unexpected_sop:1; 325 uint64_t invalid_sop:1; 326 uint64_t pkt_cpl_to:1; 327 uint64_t tdr_pref_cpl_to:1; 328 uint64_t pref_par_err:1; 329 uint64_t tx_rng_oflow:1; 330 uint64_t pkt_size_err:1; 331 uint64_t runt_pkt_drop_err:1; 332 uint64_t pkt_size_hdr_err:1; 333 uint64_t peu_resp_err:1; 334 uint64_t rsrvd1:5; 335 uint64_t marked:1; 336 uint64_t rsrvd:48; 337 #endif 338 } bits; 339 } tdc_int_mask_t; 340 341 342 /* 343 * Register: TdcStat 344 * Transmit Control and Status 345 * Description: Combined control and status register. When writing to 346 * this register, any bit that software wishes not to change should 347 * be written to 0. The TdcStat register may be read or written only 348 * when no mailbox updates are pending. Accordingly, the expected 349 * algorithm for software to use in tracking marked packets and 350 * mailbox updates is one of the following only: 1) enable 351 * interrupts, enable mb, send a single marked packet, wait for Ldf0, 352 * clear marked, repeat or 2) disable interrupts, never enable mb, 353 * send one or more marked packets, poll TdcStat for marked/mMarked 354 * state, clear marked/mMarked bits, repeat. If interrupts are 355 * enabled, upon receiving an Ldf1 interrupt for a given channel 356 * software must wait until a channel's Qst bit has asserted before 357 * reading TdcStat for corresponding error information and before 358 * writing to TdcStat to clear error state. 359 * Fields: 360 * A wrap-around counter to keep track of packets transmitted. 361 * Reset to zero when the DMA is reset 362 * The pktCnt corresponds to the last packet with the MARK bit 363 * set. Reset to zero when the DMA is reset. 364 * Set to 1 to cause HW to update the mailbox when the next 365 * packet with the marked bit set is transmitted. HW clears this 366 * bit to zero after the mailbox update has completed. Note that, 367 * correspondingly, the TdcStat data for the Tx mailbox write 368 * will reflect the state of mb prior to the mb bit's update for 369 * the marked packet being sent. Software should send only one 370 * marked packet per assertion of the mb bit. Multiple marked 371 * packets after setting the mb bit and before receiving the 372 * corresponding mailbox update is not supported. Precautionary 373 * note: Emphasize HW is responsible for clearing this bit. If 374 * software clears this bit, the behavior is undefined. 375 * Set to 1 when a packet with the mark bit set is transmitted. 376 * If mb is set at the time of the marked packet transmission, 377 * marked will not be set until the corresponding mailbox write 378 * has completed. Note that, correspondingly, the TdcStat data 379 * for the Tx mailbox write will reflect the state of marked 380 * prior to the marked bit's update for the marked packet being 381 * sent. Software may read the register to clear the bit. 382 * Alternatively, software may write a 1 to clear the MARKED bit 383 * (Write 0 has no effect). In the case of write 1, if mMarked 384 * bit is set, MARKED bit will NOT be cleared. This bit is used 385 * to generate LDF 0 consistent with settings in TdcIntMask. 386 * Overflow bit for MARKED register bit. Indicates that multiple 387 * marked packets have been transmitted since the last clear of 388 * the marked bit. If hardware is waiting to update MARKED until 389 * a mailbox write has completed, when another marked packet is 390 * transmitted, mMarked will also not be set until the mailbox 391 * write completes. Note that, correspondingly, the TdcStat data 392 * for the Tx mailbox write will reflect the state of mMarked 393 * prior to the mMarked bit's update for the marked packet being 394 * sent. Software reads to clear. A write 1 to MARKED bit will 395 * also clear the mMarked bit. A write 0 has no effect. 396 * Set to 1 to indicate poisoned completion or non-zero 397 * (unsuccessful) completion status received from PEU. Part of 398 * LDF 1. 399 * Set to 1 to indicate tdc descriptor error: total bytes 400 * transmitted compared against pkt internal header bytes 401 * transmitted mismatch. Fatal error. Part of LDF 1. 402 * Set to 1 when a runt packet is dropped (when VMAC does not 403 * allow runt packets to be padded. Fatal error. Part of LDF1. 404 * Set to 1 when the packet size exceeds hardware limit: the sum 405 * of gathers exceeds the maximum transmit length (specified in 406 * the Tx VMAC Configuration register txMaxFrameLength) or any 407 * descriptor attempts to transmit more than 4K. Writing a 1 408 * clears the value to 0. Writing a 0 has no effect. Part of LDF 409 * 1. Note that packet size for the purpose of this error is 410 * determined by the actual transfer size from the Tdc to the Tdp 411 * and not from the totXferSize field of the internal header. 412 * Set to 1 to indicate Transmit Ring Overflow: Tail > Ringlength 413 * or if the relative position of the shadow tail to the ring 414 * tail is not correct with respect to the wrap bit. Transmit 415 * Ring Overflow status is not set, if the dma is disabled. Fatal 416 * error. Part of LDF1. 417 * Set to 1 by HW to indicate parity error on the tdr prefetch 418 * buffer occurred. Writing a 1 clears the parity error log 419 * register Part of LDF 1. 420 * Set to 1 to indicate tdc received a response completion 421 * timeout from peu for tdr descriptor prefetch Fatal error. Part 422 * of LDF 1. 423 * Set to 1 to indicate tdc received a response completion 424 * timeout from peu for packet data request Fatal error. Part of 425 * LDF 1. 426 * Set to 1 to indicate tdc did not receive an SOP in the 1st 427 * descriptor as was expected or the numPtr in the 1st descriptor 428 * was set to 0. Fatal error. Part of LDF 1. 429 * Set to 1 to indicate tdc received an unexpected SOP descriptor 430 * error. Fatal error. Part of LDF 1. 431 */ 432 typedef union { 433 uint64_t value; 434 struct { 435 #if defined(_BIG_ENDIAN) 436 uint64_t rsrvd:4; 437 uint64_t pkt_cnt:12; 438 uint64_t rsrvd1:4; 439 uint64_t lastmark:12; 440 uint64_t rsrvd2:2; 441 uint64_t mb:1; 442 uint64_t rsrvd3:13; 443 uint64_t marked:1; 444 uint64_t m_marked:1; 445 uint64_t rsrvd4:4; 446 uint64_t peu_resp_err:1; 447 uint64_t pkt_size_hdr_err:1; 448 uint64_t runt_pkt_drop_err:1; 449 uint64_t pkt_size_err:1; 450 uint64_t tx_rng_oflow:1; 451 uint64_t pref_par_err:1; 452 uint64_t tdr_pref_cpl_to:1; 453 uint64_t pkt_cpl_to:1; 454 uint64_t invalid_sop:1; 455 uint64_t unexpected_sop:1; 456 #else 457 uint64_t unexpected_sop:1; 458 uint64_t invalid_sop:1; 459 uint64_t pkt_cpl_to:1; 460 uint64_t tdr_pref_cpl_to:1; 461 uint64_t pref_par_err:1; 462 uint64_t tx_rng_oflow:1; 463 uint64_t pkt_size_err:1; 464 uint64_t runt_pkt_drop_err:1; 465 uint64_t pkt_size_hdr_err:1; 466 uint64_t peu_resp_err:1; 467 uint64_t rsrvd4:4; 468 uint64_t m_marked:1; 469 uint64_t marked:1; 470 uint64_t rsrvd3:13; 471 uint64_t mb:1; 472 uint64_t rsrvd2:2; 473 uint64_t lastmark:12; 474 uint64_t rsrvd1:4; 475 uint64_t pkt_cnt:12; 476 uint64_t rsrvd:4; 477 #endif 478 } bits; 479 } tdc_stat_t; 480 481 482 /* 483 * Register: TdcMbh 484 * Tx DMA Mailbox High 485 * Description: Upper bits of Tx DMA mailbox address in host memory. 486 * Fields in this register are part of the dma configuration and 487 * cannot be changed once the dma is enabled. 488 * Fields: 489 * Bits [43:32] of the Mailbox address. 490 */ 491 typedef union { 492 uint64_t value; 493 struct { 494 #if defined(_BIG_ENDIAN) 495 uint64_t rsrvd:52; 496 uint64_t mbaddr:12; 497 #else 498 uint64_t mbaddr:12; 499 uint64_t rsrvd:52; 500 #endif 501 } bits; 502 } tdc_mbh_t; 503 504 505 /* 506 * Register: TdcMbl 507 * Tx DMA Mailbox Low 508 * Description: Lower bits of Tx DMA mailbox address in host memory. 509 * Fields in this register are part of the dma configuration and 510 * cannot be changed once the dma is enabled. 511 * Fields: 512 * Bits [31:6] of the Mailbox address. Bits [5:0] are assumed to 513 * be zero, or 64B aligned. 514 */ 515 typedef union { 516 uint64_t value; 517 struct { 518 #if defined(_BIG_ENDIAN) 519 uint64_t rsrvd:32; 520 uint64_t mbaddr:26; 521 uint64_t rsrvd1:6; 522 #else 523 uint64_t rsrvd1:6; 524 uint64_t mbaddr:26; 525 uint64_t rsrvd:32; 526 #endif 527 } bits; 528 } tdc_mbl_t; 529 530 531 /* 532 * Register: TdcByteCnt 533 * Tx DMA Byte Count 534 * Description: Counts the number of bytes transmitted to the tx 535 * datapath block. This count may increment in advance of 536 * corresponding updates to TdcStat for the bytes transmitted. 537 * Fields: 538 * Number of bytes transmitted from transmit ring. This counter 539 * will saturate. This register is cleared on read. 540 */ 541 typedef union { 542 uint64_t value; 543 struct { 544 #if defined(_BIG_ENDIAN) 545 uint64_t rsrvd:32; 546 uint64_t byte_count:32; 547 #else 548 uint64_t byte_count:32; 549 uint64_t rsrvd:32; 550 #endif 551 } bits; 552 } tdc_byte_cnt_t; 553 554 555 /* 556 * Register: TdcTdrQlen 557 * Tdr Queue Length 558 * Description: Number of descriptors in Tdr For debug only. Note: 559 * Not analogous to either rdc.rbrQlen or tdc.tdcKick - 560 * tdc.tdcTdrHead. Indicates depth of the two intermediate descriptor 561 * usage points rather than end-to-end descriptor availability. 562 * Fields: 563 * Current number of descriptors in Tdr, unprefetched 564 * Current number of descriptors in Tdr in prefetch buffer, i.e. 565 * those which have been prefetched but have not yet been 566 * allocated to the RTab. 567 */ 568 typedef union { 569 uint64_t value; 570 struct { 571 #if defined(_BIG_ENDIAN) 572 uint64_t rsrvd:32; 573 uint64_t tdr_qlen:16; 574 uint64_t tdr_pref_qlen:16; 575 #else 576 uint64_t tdr_pref_qlen:16; 577 uint64_t tdr_qlen:16; 578 uint64_t rsrvd:32; 579 #endif 580 } bits; 581 } tdc_tdr_qlen_t; 582 583 584 /* 585 * Register: TdcRtabPtr 586 * RTAB pointers 587 * Description: Status of the reorder table pointers Writing to this 588 * register is for debug purposes only and is enabled when vnmDbgOn 589 * is set to 1 590 * Fields: 591 * Current rtab head pointer, used in the txPkt block This 592 * register is used to dequeue entries in the reorder table when 593 * packets are sent out 594 * Current rtab head pointer, used in the pktResp block This 595 * register is used to scan entries in the reorder table when 596 * packet data response completions arrive 597 * Current rtab tail pointer, used in the pktReq block This 598 * register is used to allocate entries in the reorder table when 599 * packet data requests are made 600 */ 601 typedef union { 602 uint64_t value; 603 struct { 604 #if defined(_BIG_ENDIAN) 605 uint64_t rsrvd:24; 606 uint64_t pkt_rtab_head:8; 607 uint64_t rsrvd1:7; 608 uint64_t rtab_head:9; 609 uint64_t rsrvd2:7; 610 uint64_t rtab_tail:9; 611 #else 612 uint64_t rtab_tail:9; 613 uint64_t rsrvd2:7; 614 uint64_t rtab_head:9; 615 uint64_t rsrvd1:7; 616 uint64_t pkt_rtab_head:8; 617 uint64_t rsrvd:24; 618 #endif 619 } bits; 620 } tdc_rtab_ptr_t; 621 622 623 /* 624 * Register: TdcDropCnt 625 * Packet Drop Counter 626 * Description: Counts the number of runt, aborted and size 627 * mismatched packets dropped by the tx datapath block. 628 * Fields: 629 * Number of dropped due to pktSizeHdrErr. This counter will 630 * saturate. This counter is cleared on read. 631 * Number of dropped due to packet abort bit being set. Many 632 * different error events could be the source of packet abort 633 * drop. Descriptor-related error events include those errors 634 * encountered while in the middle of processing a packet 635 * request: 1. unexpectedSop; 2. non-SOP descriptor parity error 636 * (prefParErr); 3. ran out of non-SOP descriptors due to peu 637 * response errors (tdrPrefCplTo or peuRespErr) or the channel 638 * being disabled before the TDR request can be made. Packet 639 * response errors encountered while in the middle of processing 640 * a packet request also can trigger the packet abort: 4. packet 641 * response did not return due to peu response errors ( pktCplTo 642 * or peuRespErr); 5. Rtab parity error (reordTblParErr). This 643 * counter will saturate. This counter is cleared on read. Note 644 * that packet aborts are not counted until the packet is cleared 645 * from the RTab, which may be an arbitrary amount of time after 646 * the corresponding error is logged in TdcStat. In most cases, 647 * this will occur before the channel is quiesced following 648 * channel disable. In an extreme case such as if a parity error 649 * on an EOP descriptor prevents recognition of the EOP, it is 650 * possible that the quiescent bit itself will not be set 651 * although the packet drop counter will be incremented. 652 * Number of dropped due to runt packet size error. This counter 653 * will saturate. This counter is cleared on read. 654 */ 655 typedef union { 656 uint64_t value; 657 struct { 658 #if defined(_BIG_ENDIAN) 659 uint64_t rsrvd:40; 660 uint64_t hdr_size_error_count:8; 661 uint64_t abort_count:8; 662 uint64_t runt_count:8; 663 #else 664 uint64_t runt_count:8; 665 uint64_t abort_count:8; 666 uint64_t hdr_size_error_count:8; 667 uint64_t rsrvd:40; 668 #endif 669 } bits; 670 } tdc_drop_cnt_t; 671 672 673 /* 674 * Register: TdcLastPktRbufPtrs 675 * Last Packet RBUF Pointers 676 * Description: Logs the RBUF head and tail pointer of the last 677 * packet sent by the tx datapath block. 678 * Fields: 679 * Logs the RBUF tail pointer of the last packet sent 680 * Logs the RBUF head pointer of the last packet sent 681 */ 682 typedef union { 683 uint64_t value; 684 struct { 685 #if defined(_BIG_ENDIAN) 686 uint64_t rsrvd:36; 687 uint64_t rbuf_tail_ptr:12; 688 uint64_t rsrvd1:4; 689 uint64_t rbuf_head_ptr:12; 690 #else 691 uint64_t rbuf_head_ptr:12; 692 uint64_t rsrvd1:4; 693 uint64_t rbuf_tail_ptr:12; 694 uint64_t rsrvd:36; 695 #endif 696 } bits; 697 } tdc_last_pkt_rbuf_ptrs_t; 698 699 700 /* 701 * Register: TdcPrefCmd 702 * Tx DMA Prefetch Buffer Command 703 * Description: Allows debug access to the entire prefetch buffer. 704 * For writes, software writes the tdcPrefData and tdcPrefParData 705 * registers, before writing the tdcPrefCmd register. For reads, 706 * software writes the tdcPrefCmd register, then reads the 707 * tdcPrefData and tdcPrefParData registers. The valid field should 708 * be polled by software until it goes low, indicating the read or 709 * write has completed. Writing the tdcPrefCmd triggers the access. 710 * Fields: 711 * status of indirect access 0=busy 1=done 712 * Command type. 1 indicates a read command, 0 a write command. 713 * enable writing of parity bits 1=enabled, 0=disabled 714 * DMA channel of entry to read or write 715 * Entry in the prefetch buffer to read or write 716 */ 717 typedef union { 718 uint64_t value; 719 struct { 720 #if defined(_BIG_ENDIAN) 721 uint64_t rsrvd:32; 722 uint64_t status:1; 723 uint64_t cmd:1; 724 uint64_t par_en:1; 725 uint64_t rsrvd1:23; 726 uint64_t dmc:2; 727 uint64_t entry:4; 728 #else 729 uint64_t entry:4; 730 uint64_t dmc:2; 731 uint64_t rsrvd1:23; 732 uint64_t par_en:1; 733 uint64_t cmd:1; 734 uint64_t status:1; 735 uint64_t rsrvd:32; 736 #endif 737 } bits; 738 } tdc_pref_cmd_t; 739 740 741 /* 742 * Register: TdcPrefData 743 * Tx DMA Prefetch Buffer Data 744 * Description: See tdcPrefCmd register. 745 * Fields: 746 * For writes, data which is written into prefetch buffer. For 747 * reads, data read from the prefetch buffer. 748 */ 749 typedef union { 750 uint64_t value; 751 struct { 752 #if defined(_BIG_ENDIAN) 753 uint64_t data:64; 754 #else 755 uint64_t data:64; 756 #endif 757 } bits; 758 } tdc_pref_data_t; 759 760 761 /* 762 * Register: TdcPrefParData 763 * Tx DMA Prefetch Buffer Parity Data 764 * Description: See tdcPrefCmd register. 765 * Fields: 766 * For writes, parity data which is written into prefetch buffer. 767 * For reads, parity data read from the prefetch buffer. 768 */ 769 typedef union { 770 uint64_t value; 771 struct { 772 #if defined(_BIG_ENDIAN) 773 uint64_t rsrvd:56; 774 uint64_t par_data:8; 775 #else 776 uint64_t par_data:8; 777 uint64_t rsrvd:56; 778 #endif 779 } bits; 780 } tdc_pref_par_data_t; 781 782 783 /* 784 * Register: TdcReordBufCmd 785 * Tx DMA Reorder Buffer Command 786 * Description: Allows debug access to the entire Reorder buffer. For 787 * writes, software writes the tdcReordBufData and tdcReordBufEccData 788 * before writing the tdcReordBufCmd register. For reads, software 789 * writes the tdcReordBufCmd register, then reads the tdcReordBufData 790 * and tdcReordBufEccData registers. The valid field should be polled 791 * by software until it goes low, indicating the read or write has 792 * completed. Writing the tdcReordBufCmd triggers the access. 793 * Fields: 794 * status of indirect access 0=busy 1=done 795 * Command type. 1 indicates a read command, 0 a write command. 796 * enable writing of ecc bits 1=enabled, 0=disabled 797 * Entry in the reorder buffer to read or write 798 */ 799 typedef union { 800 uint64_t value; 801 struct { 802 #if defined(_BIG_ENDIAN) 803 uint64_t rsrvd:32; 804 uint64_t status:1; 805 uint64_t cmd:1; 806 uint64_t ecc_en:1; 807 uint64_t rsrvd1:17; 808 uint64_t entry:12; 809 #else 810 uint64_t entry:12; 811 uint64_t rsrvd1:17; 812 uint64_t ecc_en:1; 813 uint64_t cmd:1; 814 uint64_t status:1; 815 uint64_t rsrvd:32; 816 #endif 817 } bits; 818 } tdc_reord_buf_cmd_t; 819 820 821 /* 822 * Register: TdcReordBufData 823 * Tx DMA Reorder Buffer Data 824 * Description: See tdcReordBufCmd register. 825 * Fields: 826 * For writes, data which is written into reorder buffer. For 827 * reads, data read from the reorder buffer. 828 */ 829 typedef union { 830 uint64_t value; 831 struct { 832 #if defined(_BIG_ENDIAN) 833 uint64_t data:64; 834 #else 835 uint64_t data:64; 836 #endif 837 } bits; 838 } tdc_reord_buf_data_t; 839 840 841 /* 842 * Register: TdcReordBufEccData 843 * Tx DMA Reorder Buffer ECC Data 844 * Description: See tdcReordBufCmd register. 845 * Fields: 846 * For writes, ecc data which is written into reorder buffer. For 847 * reads, ecc data read from the reorder buffer. 848 */ 849 typedef union { 850 uint64_t value; 851 struct { 852 #if defined(_BIG_ENDIAN) 853 uint64_t rsrvd:56; 854 uint64_t ecc_data:8; 855 #else 856 uint64_t ecc_data:8; 857 uint64_t rsrvd:56; 858 #endif 859 } bits; 860 } tdc_reord_buf_ecc_data_t; 861 862 863 /* 864 * Register: TdcReordTblCmd 865 * Tx DMA Reorder Table Command 866 * Description: Allows debug access to the entire Reorder Table. For 867 * writes, software writes the tdcReordTblData and tdcReordTblParData 868 * before writing the tdcReordTblCmd register. For reads, software 869 * writes the tdcReordTblCmd register, then reads the tdcReordTblData 870 * and tdcReordTblParData registers. The valid field should be polled 871 * by software until it goes low, indicating the read or write has 872 * completed. Writing the tdcReordTblCmd triggers the access. 873 * Fields: 874 * status of indirect access 0=busy 1=done 875 * Command type. 1 indicates a read command, 0 a write command. 876 * enable writing of par bits 1=enabled, 0=disabled 877 * Address in the reorder table to read from or write to 878 */ 879 typedef union { 880 uint64_t value; 881 struct { 882 #if defined(_BIG_ENDIAN) 883 uint64_t rsrvd:32; 884 uint64_t status:1; 885 uint64_t cmd:1; 886 uint64_t par_en:1; 887 uint64_t rsrvd1:21; 888 uint64_t entry:8; 889 #else 890 uint64_t entry:8; 891 uint64_t rsrvd1:21; 892 uint64_t par_en:1; 893 uint64_t cmd:1; 894 uint64_t status:1; 895 uint64_t rsrvd:32; 896 #endif 897 } bits; 898 } tdc_reord_tbl_cmd_t; 899 900 901 /* 902 * Register: TdcReordTblDataLo 903 * Tx DMA Reorder Table Data Lo 904 * Description: See tdcReordTblCmd register. 905 * Fields: 906 * For writes, data which is written into reorder table. For 907 * reads, data read from the reorder table. 908 */ 909 typedef union { 910 uint64_t value; 911 struct { 912 #if defined(_BIG_ENDIAN) 913 uint64_t data:64; 914 #else 915 uint64_t data:64; 916 #endif 917 } bits; 918 } tdc_reord_tbl_data_lo_t; 919 920 921 /* 922 * Register: TdcReordTblDataHi 923 * Tx DMA Reorder Table Data Hi 924 * Description: See tdcReordTblCmd register. 925 * Fields: 926 * For writes, parity data which is written into reorder table. 927 * For reads, parity data read from the reorder table. 928 * For writes, data which is written into reorder table. For 929 * reads, data read from the reorder table. 930 */ 931 typedef union { 932 uint64_t value; 933 struct { 934 #if defined(_BIG_ENDIAN) 935 uint64_t rsrvd:47; 936 uint64_t par_data:9; 937 uint64_t hi_data:8; 938 #else 939 uint64_t hi_data:8; 940 uint64_t par_data:9; 941 uint64_t rsrvd:47; 942 #endif 943 } bits; 944 } tdc_reord_tbl_data_hi_t; 945 946 947 /* 948 * Register: TdcPrefParLog 949 * Tx DMA Prefetch Buffer Parity Log 950 * Description: TDC DMA Prefetch Buffer parity log register This 951 * register logs the first parity error encountered. Writing a 1 to 952 * TdcStat::prefParErr clears this register and re-arms for logging 953 * the next error 954 * Fields: 955 * Address of parity error read data 956 */ 957 typedef union { 958 uint64_t value; 959 struct { 960 #if defined(_BIG_ENDIAN) 961 uint64_t rsrvd:32; 962 uint64_t rsrvd1:26; 963 uint64_t address:6; 964 #else 965 uint64_t address:6; 966 uint64_t rsrvd1:26; 967 uint64_t rsrvd:32; 968 #endif 969 } bits; 970 } tdc_pref_par_log_t; 971 972 973 /* 974 * Register: TdcReordBufEccLog 975 * Tx Reorder Buffer ECC Log 976 * Description: TDC Reorder Buffer ECC log register This register 977 * logs the first ECC error encountered. Writing a 1 to 978 * tdcFifoErrStat::reordBufDedErr or tdcFifoErrStat::reordBufSecErr 979 * clears this register and re-arms for logging 980 * Fields: 981 * Address of ECC error 982 * Syndrome of ECC error 983 */ 984 typedef union { 985 uint64_t value; 986 struct { 987 #if defined(_BIG_ENDIAN) 988 uint64_t rsrvd:32; 989 uint64_t rsrvd1:4; 990 uint64_t address:12; 991 uint64_t rsrvd2:8; 992 uint64_t syndrome:8; 993 #else 994 uint64_t syndrome:8; 995 uint64_t rsrvd2:8; 996 uint64_t address:12; 997 uint64_t rsrvd1:4; 998 uint64_t rsrvd:32; 999 #endif 1000 } bits; 1001 } tdc_reord_buf_ecc_log_t; 1002 1003 1004 /* 1005 * Register: TdcReordTblParLog 1006 * Tx Reorder Table Parity Log 1007 * Description: TDC Reorder Table parity log register This register 1008 * logs the first parity error encountered. Writing a 1 to 1009 * tdcFifoErrStat::reordTblParErr clears this register and re-arms 1010 * for logging 1011 * Fields: 1012 * Address of parity error 1013 */ 1014 typedef union { 1015 uint64_t value; 1016 struct { 1017 #if defined(_BIG_ENDIAN) 1018 uint64_t rsrvd:32; 1019 uint64_t rsrvd1:24; 1020 uint64_t address:8; 1021 #else 1022 uint64_t address:8; 1023 uint64_t rsrvd1:24; 1024 uint64_t rsrvd:32; 1025 #endif 1026 } bits; 1027 } tdc_reord_tbl_par_log_t; 1028 1029 1030 /* 1031 * Register: TdcFifoErrMask 1032 * FIFO Error Mask 1033 * Description: FIFO Error Mask register. Mask status of Reorder 1034 * Buffer and Reorder Table Buffer Errors. 1035 * Fields: 1036 * Set to 0 to select the event to raise the LDF to indicate 1037 * reorder table ram received a parity error An Device Error 1 1038 * event. 1039 * Set to 0 to select the event to raise the LDF to indicate 1040 * reorder buffer ram received a ecc double bit error An Device 1041 * Error 1 event. 1042 * Set to 0 to select the event to raise the LDF to indicate 1043 * reorder buffer ram received a ecc single bit error An Device 1044 * Error 0 event. 1045 */ 1046 typedef union { 1047 uint64_t value; 1048 struct { 1049 #if defined(_BIG_ENDIAN) 1050 uint64_t rsrvd:61; 1051 uint64_t reord_tbl_par_err:1; 1052 uint64_t reord_buf_ded_err:1; 1053 uint64_t reord_buf_sec_err:1; 1054 #else 1055 uint64_t reord_buf_sec_err:1; 1056 uint64_t reord_buf_ded_err:1; 1057 uint64_t reord_tbl_par_err:1; 1058 uint64_t rsrvd:61; 1059 #endif 1060 } bits; 1061 } tdc_fifo_err_mask_t; 1062 1063 1064 /* 1065 * Register: TdcFifoErrStat 1066 * FIFO Error Status 1067 * Description: FIFO Error Status register. Log status of Reorder 1068 * Buffer and Reorder Table Buffer Errors. 1069 * Fields: 1070 * Set to 1 by HW to indicate reorder table ram received a parity 1071 * error Writing a 1 clears this bit and also clears the 1072 * TdcReordTblParLog register Fatal error. Part of Device Error 1073 * 1. 1074 * Set to 1 by HW to indicate reorder buffer ram received a 1075 * double bit ecc error Writing a 1 clears this bit and also 1076 * clears the tdcReordBufEccLog register Fatal error. Part of 1077 * Device Error 1. 1078 * Set to 1 by HW to indicate reorder buffer ram received a 1079 * single bit ecc error Writing a 1 clears this bit and also 1080 * clears the tdcReordBufEccLog register Non-Fatal error. Part of 1081 * Device Error 0. 1082 */ 1083 typedef union { 1084 uint64_t value; 1085 struct { 1086 #if defined(_BIG_ENDIAN) 1087 uint64_t rsrvd:61; 1088 uint64_t reord_tbl_par_err:1; 1089 uint64_t reord_buf_ded_err:1; 1090 uint64_t reord_buf_sec_err:1; 1091 #else 1092 uint64_t reord_buf_sec_err:1; 1093 uint64_t reord_buf_ded_err:1; 1094 uint64_t reord_tbl_par_err:1; 1095 uint64_t rsrvd:61; 1096 #endif 1097 } bits; 1098 } tdc_fifo_err_stat_t; 1099 1100 1101 /* 1102 * Register: TdcFifoErrIntDbg 1103 * FIFO Error Interrupt Debug 1104 * Description: FIFO Error Interrupt Debug register. Write this 1105 * regsiter to set bits in TdcFifoErrStat, allowing debug creation of 1106 * interrupts without needing to create the actual events. This 1107 * register holds no state. Reading this register gives the Tdc Fifo 1108 * Err Status data. Clear interrupt state by clearing TdcFifoErrStat. 1109 * For Debug only 1110 * Fields: 1111 * Set to 1 to select the event to raise the LDF to indicate 1112 * reorder table ram received a parity error An Device Error 1 1113 * event. 1114 * Set to 1 to select the event to raise the LDF to indicate 1115 * reorder buffer ram received a ecc double bit error An Device 1116 * Error 1 event. 1117 * Set to 1 to select the event to raise the LDF to indicate 1118 * reorder buffer ram received a ecc single bit error An Device 1119 * Error 0 event. 1120 */ 1121 typedef union { 1122 uint64_t value; 1123 struct { 1124 #if defined(_BIG_ENDIAN) 1125 uint64_t rsrvd:61; 1126 uint64_t reord_tbl_par_err:1; 1127 uint64_t reord_buf_ded_err:1; 1128 uint64_t reord_buf_sec_err:1; 1129 #else 1130 uint64_t reord_buf_sec_err:1; 1131 uint64_t reord_buf_ded_err:1; 1132 uint64_t reord_tbl_par_err:1; 1133 uint64_t rsrvd:61; 1134 #endif 1135 } bits; 1136 } tdc_fifo_err_int_dbg_t; 1137 1138 1139 /* 1140 * Register: TdcStatIntDbg 1141 * Transmit Status Interrupt Debug 1142 * Description: Write this regsiter to set bits in TdcStat, allowing 1143 * debug creation of interrupts without needing to create the actual 1144 * events. This register holds no state. Reading this register gives 1145 * the Transmit Control and Status data. Clear interrupt state by 1146 * clearing TdcStat. For Debug only 1147 * Fields: 1148 * Set to 1 to select the event to raise the LDF for packets 1149 * marked. An LDF 0 event. 1150 * Set to 1 to select the event to raise the LDF when poisoned 1151 * completion or non-zero (unsuccessful) completion status 1152 * received from PEU. An LDF 1 event. 1153 * Set to 1 to select the event to raise the LDF when total bytes 1154 * transmitted compared against pkt internal header bytes 1155 * transmitted mismatch. An LDF 1 event. 1156 * Set to 1 to select the event to raise the LDF when a runt 1157 * packet is dropped (when VMAC does not allow runt packets to be 1158 * padded). An LDF 1 event. 1159 * Set to 1 to select the event to raise the LDF when the packet 1160 * size exceeds hardware limit. An LDF 1 event. 1161 * Set to 1 to select the event to raise the LDF to indicate 1162 * Transmit Ring Overflow An LDF 1 event. 1163 * Set to 1 to select the event to raise the LDF to indicate 1164 * parity error on the tdr prefetch buffer occurred. An LDF 1 1165 * event. 1166 * Set to 1 to select the event to raise the LDF to indicate tdc 1167 * received a response completion timeout from peu for tdr 1168 * descriptor prefetch An LDF 1 event. 1169 * Set to 1 to select the event to raise the LDF to indicate tdc 1170 * received a response completion timeout from peu for packet 1171 * data request An LDF 1 event. 1172 * Set to 1 to select the event to raise the LDF to indicate tdc 1173 * did not receive an SOP in the 1st descriptor as was expected 1174 * or the numPtr in the 1st descriptor was set to 0. An LDF 1 1175 * event. 1176 * Set to 1 to select the event to raise the LDF to indicate tdc 1177 * received an unexpected SOP descriptor error. An LDF 1 event. 1178 */ 1179 typedef union { 1180 uint64_t value; 1181 struct { 1182 #if defined(_BIG_ENDIAN) 1183 uint64_t rsrvd:48; 1184 uint64_t marked:1; 1185 uint64_t rsrvd1:5; 1186 uint64_t peu_resp_err:1; 1187 uint64_t pkt_size_hdr_err:1; 1188 uint64_t runt_pkt_drop_err:1; 1189 uint64_t pkt_size_err:1; 1190 uint64_t tx_rng_oflow:1; 1191 uint64_t pref_par_err:1; 1192 uint64_t tdr_pref_cpl_to:1; 1193 uint64_t pkt_cpl_to:1; 1194 uint64_t invalid_sop:1; 1195 uint64_t unexpected_sop:1; 1196 #else 1197 uint64_t unexpected_sop:1; 1198 uint64_t invalid_sop:1; 1199 uint64_t pkt_cpl_to:1; 1200 uint64_t tdr_pref_cpl_to:1; 1201 uint64_t pref_par_err:1; 1202 uint64_t tx_rng_oflow:1; 1203 uint64_t pkt_size_err:1; 1204 uint64_t runt_pkt_drop_err:1; 1205 uint64_t pkt_size_hdr_err:1; 1206 uint64_t peu_resp_err:1; 1207 uint64_t rsrvd1:5; 1208 uint64_t marked:1; 1209 uint64_t rsrvd:48; 1210 #endif 1211 } bits; 1212 } tdc_stat_int_dbg_t; 1213 1214 1215 /* 1216 * Register: TdcPktReqTidTag 1217 * Packet Request TID Tag 1218 * Description: Packet Request TID Tag register Track the packet 1219 * request TID currently used 1220 * Fields: 1221 * When set to 1, it indicates the TID is currently being used 1222 */ 1223 typedef union { 1224 uint64_t value; 1225 struct { 1226 #if defined(_BIG_ENDIAN) 1227 uint64_t rsrvd:32; 1228 uint64_t pkt_req_tid_tag:24; 1229 uint64_t rsrvd1:8; 1230 #else 1231 uint64_t rsrvd1:8; 1232 uint64_t pkt_req_tid_tag:24; 1233 uint64_t rsrvd:32; 1234 #endif 1235 } bits; 1236 } tdc_pkt_req_tid_tag_t; 1237 1238 1239 /* 1240 * Register: TdcSopPrefDescLog 1241 * SOP Prefetch Descriptor Log 1242 * Description: SOP Descriptor Log register Logs the last SOP 1243 * prefetch descriptor processed by the packet request block. This 1244 * log could represent the current SOP prefetch descriptor if the 1245 * packet request block did not complete issuing the data requests 1246 * from this descriptor. Descriptors are logged to this register when 1247 * the packet request block is expecting an SOP descriptor, and it 1248 * receives it. 1249 * Fields: 1250 * Represents the last or current SOP descriptor being processed 1251 */ 1252 typedef union { 1253 uint64_t value; 1254 struct { 1255 #if defined(_BIG_ENDIAN) 1256 uint64_t sop_pref_desc_log:64; 1257 #else 1258 uint64_t sop_pref_desc_log:64; 1259 #endif 1260 } bits; 1261 } tdc_sop_pref_desc_log_t; 1262 1263 1264 /* 1265 * Register: TdcPrefDescLog 1266 * Prefetch Descriptor Log 1267 * Description: SOP Descriptor Log register Logs the last prefetch 1268 * descriptor processed by the packet request block. This log could 1269 * represent the current prefetch descriptor if the packet request 1270 * block did not complete issuing the data requests from this 1271 * descriptor. The contents in this register could differ from the 1272 * SOP Prefetch Descriptor Log register if a particular packet 1273 * requires usage of more than 1 descriptor. Descriptors are logged 1274 * to this register when the packet request block is expecting a 1275 * descriptor after the SOP descriptor. 1276 * Fields: 1277 * Represents the last or current descriptor being processed 1278 */ 1279 typedef union { 1280 uint64_t value; 1281 struct { 1282 #if defined(_BIG_ENDIAN) 1283 uint64_t pref_desc_log:64; 1284 #else 1285 uint64_t pref_desc_log:64; 1286 #endif 1287 } bits; 1288 } tdc_pref_desc_log_t; 1289 1290 1291 /* 1292 * Register: TdcPeuTxnLog 1293 * PEU Transaction Log 1294 * Description: PEU Transaction Log register. Counts the memory read 1295 * and write requests sent to peu block. For debug only. 1296 * Fields: 1297 * Counts the memory write transactions sent to peu block. This 1298 * counter saturates. This counter increments when vnmDbg is on 1299 * Counts the memory read transactions sent to peu block. This 1300 * counter saturates. This counter increments when vnmDbg is on 1301 */ 1302 typedef union { 1303 uint64_t value; 1304 struct { 1305 #if defined(_BIG_ENDIAN) 1306 uint64_t rsrvd:32; 1307 uint64_t rsrvd1:16; 1308 uint64_t peu_mem_wr_count:8; 1309 uint64_t peu_mem_rd_count:8; 1310 #else 1311 uint64_t peu_mem_rd_count:8; 1312 uint64_t peu_mem_wr_count:8; 1313 uint64_t rsrvd1:16; 1314 uint64_t rsrvd:32; 1315 #endif 1316 } bits; 1317 } tdc_peu_txn_log_t; 1318 1319 1320 /* 1321 * Register: TdcDbgTrainingVec 1322 * Debug Training Vector 1323 * Description: Debug Training Vector register. Debug Training Vector 1324 * for the coreClk domain. For the pcieClk domain, the dbgxMsb and 1325 * dbgyMsb values are flipped on the debug bus. 1326 * Fields: 1327 * Blade Number, the value read depends on the blade this block 1328 * resides 1329 * debug training vector the sub-group select value of 0 selects 1330 * this vector 1331 * Blade Number, the value read depends on the blade this block 1332 * resides 1333 * debug training vector the sub-group select value of 0 selects 1334 * this vector 1335 */ 1336 typedef union { 1337 uint64_t value; 1338 struct { 1339 #if defined(_BIG_ENDIAN) 1340 uint64_t rsrvd:32; 1341 uint64_t dbgx_msb:1; 1342 uint64_t dbgx_bld_num:3; 1343 uint64_t dbgx_training_vec:12; 1344 uint64_t dbgy_msb:1; 1345 uint64_t dbgy_bld_num:3; 1346 uint64_t dbgy_training_vec:12; 1347 #else 1348 uint64_t dbgy_training_vec:12; 1349 uint64_t dbgy_bld_num:3; 1350 uint64_t dbgy_msb:1; 1351 uint64_t dbgx_training_vec:12; 1352 uint64_t dbgx_bld_num:3; 1353 uint64_t dbgx_msb:1; 1354 uint64_t rsrvd:32; 1355 #endif 1356 } bits; 1357 } tdc_dbg_training_vec_t; 1358 1359 1360 /* 1361 * Register: TdcDbgGrpSel 1362 * Debug Group Select 1363 * Description: Debug Group Select register. Debug Group Select 1364 * register selects the group of signals brought out on the debug 1365 * port 1366 * Fields: 1367 * high 32b sub-group select 1368 * low 32b sub-group select 1369 */ 1370 typedef union { 1371 uint64_t value; 1372 struct { 1373 #if defined(_BIG_ENDIAN) 1374 uint64_t rsrvd:48; 1375 uint64_t rsrvd1:1; 1376 uint64_t dbg_h32_sub_sel:7; 1377 uint64_t rsrvd2:1; 1378 uint64_t dbg_l32_sub_sel:7; 1379 #else 1380 uint64_t dbg_l32_sub_sel:7; 1381 uint64_t rsrvd2:1; 1382 uint64_t dbg_h32_sub_sel:7; 1383 uint64_t rsrvd1:1; 1384 uint64_t rsrvd:48; 1385 #endif 1386 } bits; 1387 } tdc_dbg_grp_sel_t; 1388 1389 1390 #ifdef __cplusplus 1391 } 1392 #endif 1393 1394 #endif /* _HXGE_TDC_HW_H */ 1395