1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HXGE_TDC_HW_H 27 #define _HXGE_TDC_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define TDC_BASE_ADDR 0X00400000 34 35 #define TDC_PAGE_HANDLE (TDC_BASE_ADDR + 0x8) 36 #define TDC_TDR_CFG (TDC_BASE_ADDR + 0x20) 37 #define TDC_TDR_HEAD (TDC_BASE_ADDR + 0x28) 38 #define TDC_TDR_PRE_HEAD (TDC_BASE_ADDR + 0x30) 39 #define TDC_TDR_KICK (TDC_BASE_ADDR + 0x38) 40 #define TDC_INT_MASK (TDC_BASE_ADDR + 0x40) 41 #define TDC_STAT (TDC_BASE_ADDR + 0x48) 42 #define TDC_MBH (TDC_BASE_ADDR + 0x50) 43 #define TDC_MBL (TDC_BASE_ADDR + 0x58) 44 #define TDC_BYTE_CNT (TDC_BASE_ADDR + 0x80) 45 #define TDC_TDR_QLEN (TDC_BASE_ADDR + 0x88) 46 #define TDC_RTAB_PTR (TDC_BASE_ADDR + 0x90) 47 #define TDC_DROP_CNT (TDC_BASE_ADDR + 0x98) 48 #define TDC_LAST_PKT_RBUF_PTRS (TDC_BASE_ADDR + 0xA8) 49 #define TDC_PREF_CMD (TDC_BASE_ADDR + 0x100) 50 #define TDC_PREF_DATA (TDC_BASE_ADDR + 0x108) 51 #define TDC_PREF_PAR_DATA (TDC_BASE_ADDR + 0x110) 52 #define TDC_REORD_BUF_CMD (TDC_BASE_ADDR + 0x120) 53 #define TDC_REORD_BUF_DATA (TDC_BASE_ADDR + 0x128) 54 #define TDC_REORD_BUF_ECC_DATA (TDC_BASE_ADDR + 0x130) 55 #define TDC_REORD_TBL_CMD (TDC_BASE_ADDR + 0x140) 56 #define TDC_REORD_TBL_DATA_LO (TDC_BASE_ADDR + 0x148) 57 #define TDC_REORD_TBL_DATA_HI (TDC_BASE_ADDR + 0x150) 58 #define TDC_PREF_PAR_LOG (TDC_BASE_ADDR + 0x200) 59 #define TDC_REORD_BUF_ECC_LOG (TDC_BASE_ADDR + 0x208) 60 #define TDC_REORD_TBL_PAR_LOG (TDC_BASE_ADDR + 0x210) 61 #define TDC_FIFO_ERR_MASK (TDC_BASE_ADDR + 0x220) 62 #define TDC_FIFO_ERR_STAT (TDC_BASE_ADDR + 0x228) 63 #define TDC_FIFO_ERR_INT_DBG (TDC_BASE_ADDR + 0x230) 64 #define TDC_STAT_INT_DBG (TDC_BASE_ADDR + 0x240) 65 #define TDC_PKT_REQ_TID_TAG (TDC_BASE_ADDR + 0x250) 66 #define TDC_SOP_PREF_DESC_LOG (TDC_BASE_ADDR + 0x260) 67 #define TDC_PREF_DESC_LOG (TDC_BASE_ADDR + 0x268) 68 #define TDC_PEU_TXN_LOG (TDC_BASE_ADDR + 0x270) 69 #define TDC_DBG_TRAINING_VEC (TDC_BASE_ADDR + 0x300) 70 #define TDC_DBG_GRP_SEL (TDC_BASE_ADDR + 0x308) 71 72 73 /* 74 * Register: TdcPageHandle 75 * Logical Page Handle 76 * Description: Upper 20 bits [63:44] to use for all accesses over 77 * the PCI-E bus. Fields in this register are part of the dma 78 * configuration and cannot be changed once the dma is enabled. 79 * Fields: 80 * Page handle, bits [63:44] of all PCI-E transactions for this 81 * channel. 82 */ 83 typedef union { 84 uint64_t value; 85 struct { 86 #if defined(_BIG_ENDIAN) 87 uint32_t rsrvd:32; 88 uint32_t rsrvd_l:12; 89 uint32_t page_handle:20; 90 #else 91 uint32_t page_handle:20; 92 uint32_t rsrvd_l:12; 93 uint32_t rsrvd:32; 94 #endif 95 } bits; 96 } tdc_page_handle_t; 97 98 99 /* 100 * Register: TdcTdrCfg 101 * Transmit Ring Configuration 102 * Description: Configuration parameters for transmit DMA block. 103 * Software configures the location of the transmit ring in host 104 * memory, as well as its maximum size. Fields in this register are 105 * part of the dma configuration and cannot be changed once the dma 106 * is enabled. 107 * HW does not check for all configuration errors across different 108 * fields. 109 * The usage of enable, reset, and qst is as follows. Software 110 * should use the following sequence to reset a DMA channel. First, 111 * set DMA.enable to 0, wait for DMA.qst=1 and then, set DMA.reset to 112 * 1. After DMA.reset is cleared by hardware and the DMA.qst is set 113 * to 1, software may then start configuring the DMA channel. The 114 * DMA.enable can be set or cleared while the DMA is in operation. 115 * The state machines of the DMA may not have returned to its initial 116 * states yet after the DMA.enable bit is cleared. This condition is 117 * indicated by the value of the DMA.qst. An example of DMA.enable 118 * being cleared during operation is when a fatal error occurs. 119 * Fields: 120 * Bits [15:5] of the maximum number of entries in the Transmit 121 * Queue ring buffer. Bits [4:0] are always 0. Maximum number of 122 * entries is (2^16 - 32) and is limited by the staddr value. 123 * (len + staddr) should not exceed (2^16 - 32). 124 * Set to 1 to enable the Transmit DMA. On fatal errors, this bit 125 * will be cleared by hardware. This bit cannot be set if sw has 126 * not resolved any pending fatal error condition: i.e. any 127 * TdcStat ldf1 error bits remain set. 128 * Set to 1 to reset the DMA. Hardware will clear this bit after 129 * reset is completed. A reset will bring the sepecific DMA back 130 * to the power on state (including the DMA.en in this register). 131 * When set to 1, it indicates all state associated with the DMA 132 * are in its initial state following either dma reset or 133 * disable. Thus, once this is set to 1, sw could start to 134 * configure the DMA if needed. In an extreme case such as if a 135 * parity error on an EOP descriptor prevents recognition of the 136 * EOP, it is possible that the qst bit will not be set even 137 * though the dma engine has been disabled. 138 * Address bits [43:19] of the start address for the transmit 139 * ring buffer. The value in this field is dependent on len 140 * field. (len + staddr) should not exceed (2^16 - 32). 141 * Bits [18:6] of the start address for the transmit ring buffer. 142 * Bits [5:0] are assumed to be zero, or 64B aligned. 143 */ 144 typedef union { 145 uint64_t value; 146 struct { 147 #if defined(_BIG_ENDIAN) 148 uint32_t len:11; 149 uint32_t rsrvd:5; 150 uint32_t enable:1; 151 uint32_t reset:1; 152 uint32_t qst:1; 153 uint32_t rsrvd1:1; 154 uint32_t staddr_base:12; 155 uint32_t staddr_base_l:13; 156 uint32_t staddr:13; 157 uint32_t rsrvd2:6; 158 #else 159 uint32_t rsrvd2:6; 160 uint32_t staddr:13; 161 uint32_t staddr_base_l:13; 162 uint32_t staddr_base:12; 163 uint32_t rsrvd1:1; 164 uint32_t qst:1; 165 uint32_t reset:1; 166 uint32_t enable:1; 167 uint32_t rsrvd:5; 168 uint32_t len:11; 169 #endif 170 } bits; 171 } tdc_tdr_cfg_t; 172 173 174 /* 175 * Register: TdcTdrHead 176 * Transmit Ring Head 177 * Description: Read-only register software call poll to determine 178 * the current head of the transmit ring, from the tdcTxPkt block. 179 * Software uses this to know which Tdr entries have had their 180 * descriptors transmitted. These entries and their descriptors may 181 * then be reused by software. 182 * Fields: 183 * Hardware will toggle this bit every time the head is wrapped 184 * around the configured ring buffer. 185 * Entry in transmit ring which will be the next descriptor 186 * transmitted. Software should consider the Tdr full if head == 187 * TdcTdrKick::tail and wrap != TdcTdrKick::wrap. The ring is 188 * empty of head == TdcTdrKick::tail and wrap == 189 * TdcTdrKick::wrap. 190 */ 191 typedef union { 192 uint64_t value; 193 struct { 194 #if defined(_BIG_ENDIAN) 195 uint32_t rsrvd:32; 196 uint32_t rsrvd_l:15; 197 uint32_t wrap:1; 198 uint32_t head:16; 199 #else 200 uint32_t head:16; 201 uint32_t wrap:1; 202 uint32_t rsrvd_l:15; 203 uint32_t rsrvd:32; 204 #endif 205 } bits; 206 } tdc_tdr_head_t; 207 208 209 /* 210 * Register: TdcTdrPreHead 211 * Transmit Ring Prefetch Head 212 * Description: Read-only register software call poll to determine 213 * the current prefetch head of the transmit ring, from the tdcPktReq 214 * block. Transmit descriptors are prefetched into chip memory. 215 * Indicates next descriptor to be read from host memory. For debug 216 * use only. 217 * Fields: 218 * Hardware will toggle this bit every time the prefetch head is 219 * wrapped around the configured ring buffer. 220 * Entry in transmit ring which will be fetched next from host 221 * memory. 222 */ 223 typedef union { 224 uint64_t value; 225 struct { 226 #if defined(_BIG_ENDIAN) 227 uint32_t rsrvd:32; 228 uint32_t rsrvd_l:15; 229 uint32_t wrap:1; 230 uint32_t head:16; 231 #else 232 uint32_t head:16; 233 uint32_t wrap:1; 234 uint32_t rsrvd_l:15; 235 uint32_t rsrvd:32; 236 #endif 237 } bits; 238 } tdc_tdr_pre_head_t; 239 240 241 /* 242 * Register: TdcTdrKick 243 * Transmit Ring Kick 244 * Description: After posting transmit descriptors to the Transmit 245 * Ring, software updates the tail pointer to inform Hydra of the new 246 * descriptors. Software can only post descriptors through this 247 * register when the entire packet is in the ring. Otherwise, 248 * hardware dead-lock can occur. If an overflow kick occurs when the 249 * channel is disabled, tdcStat.txRngOflow (Transmit Ring Overflow) 250 * status is not set. 251 * Fields: 252 * Software needs to toggle this bit every time the tail is 253 * wrapped around the configured ring buffer. 254 * Entry where the next valid descriptor will be added (one entry 255 * past the last valid descriptor.) 256 */ 257 typedef union { 258 uint64_t value; 259 struct { 260 #if defined(_BIG_ENDIAN) 261 uint32_t rsrvd:32; 262 uint32_t rsrvd_l:15; 263 uint32_t wrap:1; 264 uint32_t tail:16; 265 #else 266 uint32_t tail:16; 267 uint32_t wrap:1; 268 uint32_t rsrvd_l:15; 269 uint32_t rsrvd:32; 270 #endif 271 } bits; 272 } tdc_tdr_kick_t; 273 274 275 /* 276 * Register: TdcIntMask 277 * Transmit Event Mask 278 * Description: The Tx DMA can generate a number of LDF events. The 279 * events can be enabled by software by setting the corresponding bit 280 * to 0. The default value of 1 means the event is masked and no LDF 281 * event is generated. 282 * Fields: 283 * Set to 0 to select the event to raise the LDF for packets 284 * marked. An LDF 0 event. 285 * Set to 0 to select the event to raise the LDF when poisoned 286 * completion or non-zero (unsuccessful) completion status 287 * received from PEU. An LDF 1 event. 288 * Set to 0 to select the event to raise the LDF when total bytes 289 * transmitted compared against pkt internal header bytes 290 * transmitted mismatch. An LDF 1 event. 291 * Set to 0 to select the event to raise the LDF when a runt 292 * packet is dropped (when VMAC does not allow runt packets to be 293 * padded). An LDF 1 event. 294 * Set to 0 to select the event to raise the LDF when the packet 295 * size exceeds hardware limit. An LDF 1 event. 296 * Set to 0 to select the event to raise the LDF to indicate 297 * Transmit Ring Overflow An LDF 1 event. 298 * Set to 0 to select the event to raise the LDF to indicate 299 * parity error on the tdr prefetch buffer occurred. An LDF 1 300 * event. 301 * Set to 0 to select the event to raise the LDF to indicate tdc 302 * received a response completion timeout from peu for tdr 303 * descriptor prefetch An LDF 1 event. 304 * Set to 0 to select the event to raise the LDF to indicate tdc 305 * received a response completion timeout from peu for packet 306 * data request An LDF 1 event. 307 * Set to 0 to select the event to raise the LDF to indicate tdc 308 * did not receive an SOP in the 1st descriptor as was expected 309 * or the numPtr in the 1st descriptor was set to 0. An LDF 1 310 * event. 311 * Set to 0 to select the event to raise the LDF to indicate tdc 312 * received an unexpected SOP descriptor error. An LDF 1 event. 313 */ 314 typedef union { 315 uint64_t value; 316 struct { 317 #if defined(_BIG_ENDIAN) 318 uint32_t rsrvd:32; 319 uint32_t rsrvd_l:16; 320 uint32_t marked:1; 321 uint32_t rsrvd1:5; 322 uint32_t peu_resp_err:1; 323 uint32_t pkt_size_hdr_err:1; 324 uint32_t runt_pkt_drop_err:1; 325 uint32_t pkt_size_err:1; 326 uint32_t tx_rng_oflow:1; 327 uint32_t pref_par_err:1; 328 uint32_t tdr_pref_cpl_to:1; 329 uint32_t pkt_cpl_to:1; 330 uint32_t invalid_sop:1; 331 uint32_t unexpected_sop:1; 332 #else 333 uint32_t unexpected_sop:1; 334 uint32_t invalid_sop:1; 335 uint32_t pkt_cpl_to:1; 336 uint32_t tdr_pref_cpl_to:1; 337 uint32_t pref_par_err:1; 338 uint32_t tx_rng_oflow:1; 339 uint32_t pkt_size_err:1; 340 uint32_t runt_pkt_drop_err:1; 341 uint32_t pkt_size_hdr_err:1; 342 uint32_t peu_resp_err:1; 343 uint32_t rsrvd1:5; 344 uint32_t marked:1; 345 uint32_t rsrvd_l:16; 346 uint32_t rsrvd:32; 347 #endif 348 } bits; 349 } tdc_int_mask_t; 350 351 352 /* 353 * Register: TdcStat 354 * Transmit Control and Status 355 * Description: Combined control and status register. When writing to 356 * this register, any bit that software wishes not to change should 357 * be written to 0. The TdcStat register may be read or written only 358 * when no mailbox updates are pending. Accordingly, the expected 359 * algorithm for software to use in tracking marked packets and 360 * mailbox updates is one of the following only: 1) enable 361 * interrupts, enable mb, send a single marked packet, wait for Ldf0, 362 * clear marked, repeat or 2) disable interrupts, never enable mb, 363 * send one or more marked packets, poll TdcStat for marked/mMarked 364 * state, clear marked/mMarked bits, repeat. If interrupts are 365 * enabled, upon receiving an Ldf1 interrupt for a given channel 366 * software must wait until a channel's Qst bit has asserted before 367 * reading TdcStat for corresponding error information and before 368 * writing to TdcStat to clear error state. 369 * Fields: 370 * A wrap-around counter to keep track of packets transmitted. 371 * Reset to zero when the DMA is reset 372 * The pktCnt corresponds to the last packet with the MARK bit 373 * set. Reset to zero when the DMA is reset. 374 * Set to 1 to cause HW to update the mailbox when the next 375 * packet with the marked bit set is transmitted. HW clears this 376 * bit to zero after the mailbox update has completed. Note that, 377 * correspondingly, the TdcStat data for the Tx mailbox write 378 * will reflect the state of mb prior to the mb bit's update for 379 * the marked packet being sent. Software should send only one 380 * marked packet per assertion of the mb bit. Multiple marked 381 * packets after setting the mb bit and before receiving the 382 * corresponding mailbox update is not supported. Precautionary 383 * note: Emphasize HW is responsible for clearing this bit. If 384 * software clears this bit, the behavior is undefined. 385 * Set to 1 when a packet with the mark bit set is transmitted. 386 * If mb is set at the time of the marked packet transmission, 387 * marked will not be set until the corresponding mailbox write 388 * has completed. Note that, correspondingly, the TdcStat data 389 * for the Tx mailbox write will reflect the state of marked 390 * prior to the marked bit's update for the marked packet being 391 * sent. Software may read the register to clear the bit. 392 * Alternatively, software may write a 1 to clear the MARKED bit 393 * (Write 0 has no effect). In the case of write 1, if mMarked 394 * bit is set, MARKED bit will NOT be cleared. This bit is used 395 * to generate LDF 0 consistent with settings in TdcIntMask. 396 * Overflow bit for MARKED register bit. Indicates that multiple 397 * marked packets have been transmitted since the last clear of 398 * the marked bit. If hardware is waiting to update MARKED until 399 * a mailbox write has completed, when another marked packet is 400 * transmitted, mMarked will also not be set until the mailbox 401 * write completes. Note that, correspondingly, the TdcStat data 402 * for the Tx mailbox write will reflect the state of mMarked 403 * prior to the mMarked bit's update for the marked packet being 404 * sent. Software reads to clear. A write 1 to MARKED bit will 405 * also clear the mMarked bit. A write 0 has no effect. 406 * Set to 1 to indicate poisoned completion or non-zero 407 * (unsuccessful) completion status received from PEU. Part of 408 * LDF 1. 409 * Set to 1 to indicate tdc descriptor error: total bytes 410 * transmitted compared against pkt internal header bytes 411 * transmitted mismatch. Fatal error. Part of LDF 1. 412 * Set to 1 when a runt packet is dropped (when VMAC does not 413 * allow runt packets to be padded. Fatal error. Part of LDF1. 414 * Set to 1 when the packet size exceeds hardware limit: the sum 415 * of gathers exceeds the maximum transmit length (specified in 416 * the Tx VMAC Configuration register txMaxFrameLength) or any 417 * descriptor attempts to transmit more than 4K. Writing a 1 418 * clears the value to 0. Writing a 0 has no effect. Part of LDF 419 * 1. Note that packet size for the purpose of this error is 420 * determined by the actual transfer size from the Tdc to the Tdp 421 * and not from the totXferSize field of the internal header. 422 * Set to 1 to indicate Transmit Ring Overflow: Tail > Ringlength 423 * or if the relative position of the shadow tail to the ring 424 * tail is not correct with respect to the wrap bit. Transmit 425 * Ring Overflow status is not set, if the dma is disabled. Fatal 426 * error. Part of LDF1. 427 * Set to 1 by HW to indicate parity error on the tdr prefetch 428 * buffer occurred. Writing a 1 clears the parity error log 429 * register Part of LDF 1. 430 * Set to 1 to indicate tdc received a response completion 431 * timeout from peu for tdr descriptor prefetch Fatal error. Part 432 * of LDF 1. 433 * Set to 1 to indicate tdc received a response completion 434 * timeout from peu for packet data request Fatal error. Part of 435 * LDF 1. 436 * Set to 1 to indicate tdc did not receive an SOP in the 1st 437 * descriptor as was expected or the numPtr in the 1st descriptor 438 * was set to 0. Fatal error. Part of LDF 1. 439 * Set to 1 to indicate tdc received an unexpected SOP descriptor 440 * error. Fatal error. Part of LDF 1. 441 */ 442 typedef union { 443 uint64_t value; 444 struct { 445 #if defined(_BIG_ENDIAN) 446 uint32_t rsrvd:4; 447 uint32_t pkt_cnt:12; 448 uint32_t rsrvd1:4; 449 uint32_t lastmark:12; 450 uint32_t rsrvd2:2; 451 uint32_t mb:1; 452 uint32_t rsrvd3:13; 453 uint32_t marked:1; 454 uint32_t m_marked:1; 455 uint32_t rsrvd4:4; 456 uint32_t peu_resp_err:1; 457 uint32_t pkt_size_hdr_err:1; 458 uint32_t runt_pkt_drop_err:1; 459 uint32_t pkt_size_err:1; 460 uint32_t tx_rng_oflow:1; 461 uint32_t pref_par_err:1; 462 uint32_t tdr_pref_cpl_to:1; 463 uint32_t pkt_cpl_to:1; 464 uint32_t invalid_sop:1; 465 uint32_t unexpected_sop:1; 466 #else 467 uint32_t unexpected_sop:1; 468 uint32_t invalid_sop:1; 469 uint32_t pkt_cpl_to:1; 470 uint32_t tdr_pref_cpl_to:1; 471 uint32_t pref_par_err:1; 472 uint32_t tx_rng_oflow:1; 473 uint32_t pkt_size_err:1; 474 uint32_t runt_pkt_drop_err:1; 475 uint32_t pkt_size_hdr_err:1; 476 uint32_t peu_resp_err:1; 477 uint32_t rsrvd4:4; 478 uint32_t m_marked:1; 479 uint32_t marked:1; 480 uint32_t rsrvd3:13; 481 uint32_t mb:1; 482 uint32_t rsrvd2:2; 483 uint32_t lastmark:12; 484 uint32_t rsrvd1:4; 485 uint32_t pkt_cnt:12; 486 uint32_t rsrvd:4; 487 #endif 488 } bits; 489 } tdc_stat_t; 490 491 492 /* 493 * Register: TdcMbh 494 * Tx DMA Mailbox High 495 * Description: Upper bits of Tx DMA mailbox address in host memory. 496 * Fields in this register are part of the dma configuration and 497 * cannot be changed once the dma is enabled. 498 * Fields: 499 * Bits [43:32] of the Mailbox address. 500 */ 501 typedef union { 502 uint64_t value; 503 struct { 504 #if defined(_BIG_ENDIAN) 505 uint32_t rsrvd:32; 506 uint32_t rsrvd_l:20; 507 uint32_t mbaddr:12; 508 #else 509 uint32_t mbaddr:12; 510 uint32_t rsrvd_l:20; 511 uint32_t rsrvd:32; 512 #endif 513 } bits; 514 } tdc_mbh_t; 515 516 517 /* 518 * Register: TdcMbl 519 * Tx DMA Mailbox Low 520 * Description: Lower bits of Tx DMA mailbox address in host memory. 521 * Fields in this register are part of the dma configuration and 522 * cannot be changed once the dma is enabled. 523 * Fields: 524 * Bits [31:6] of the Mailbox address. Bits [5:0] are assumed to 525 * be zero, or 64B aligned. 526 */ 527 typedef union { 528 uint64_t value; 529 struct { 530 #if defined(_BIG_ENDIAN) 531 uint32_t rsrvd:32; 532 uint32_t mbaddr:26; 533 uint32_t rsrvd1:6; 534 #else 535 uint32_t rsrvd1:6; 536 uint32_t mbaddr:26; 537 uint32_t rsrvd:32; 538 #endif 539 } bits; 540 } tdc_mbl_t; 541 542 543 /* 544 * Register: TdcByteCnt 545 * Tx DMA Byte Count 546 * Description: Counts the number of bytes transmitted to the tx 547 * datapath block. This count may increment in advance of 548 * corresponding updates to TdcStat for the bytes transmitted. 549 * Fields: 550 * Number of bytes transmitted from transmit ring. This counter 551 * will saturate. This register is cleared on read. 552 */ 553 typedef union { 554 uint64_t value; 555 struct { 556 #if defined(_BIG_ENDIAN) 557 uint32_t rsrvd:32; 558 uint32_t byte_count:32; 559 #else 560 uint32_t byte_count:32; 561 uint32_t rsrvd:32; 562 #endif 563 } bits; 564 } tdc_byte_cnt_t; 565 566 567 /* 568 * Register: TdcTdrQlen 569 * Tdr Queue Length 570 * Description: Number of descriptors in Tdr For debug only. Note: 571 * Not analogous to either rdc.rbrQlen or tdc.tdcKick - 572 * tdc.tdcTdrHead. Indicates depth of the two intermediate descriptor 573 * usage points rather than end-to-end descriptor availability. 574 * Fields: 575 * Current number of descriptors in Tdr, unprefetched 576 * Current number of descriptors in Tdr in prefetch buffer, i.e. 577 * those which have been prefetched but have not yet been 578 * allocated to the RTab. 579 */ 580 typedef union { 581 uint64_t value; 582 struct { 583 #if defined(_BIG_ENDIAN) 584 uint32_t rsrvd:32; 585 uint32_t tdr_qlen:16; 586 uint32_t tdr_pref_qlen:16; 587 #else 588 uint32_t tdr_pref_qlen:16; 589 uint32_t tdr_qlen:16; 590 uint32_t rsrvd:32; 591 #endif 592 } bits; 593 } tdc_tdr_qlen_t; 594 595 596 /* 597 * Register: TdcRtabPtr 598 * RTAB pointers 599 * Description: Status of the reorder table pointers Writing to this 600 * register is for debug purposes only and is enabled when vnmDbgOn 601 * is set to 1 602 * Fields: 603 * Current rtab head pointer, used in the txPkt block This 604 * register is used to dequeue entries in the reorder table when 605 * packets are sent out 606 * Current rtab head pointer, used in the pktResp block This 607 * register is used to scan entries in the reorder table when 608 * packet data response completions arrive 609 * Current rtab tail pointer, used in the pktReq block This 610 * register is used to allocate entries in the reorder table when 611 * packet data requests are made 612 */ 613 typedef union { 614 uint64_t value; 615 struct { 616 #if defined(_BIG_ENDIAN) 617 uint32_t rsrvd:24; 618 uint32_t pkt_rtab_head:8; 619 uint32_t rsrvd1:7; 620 uint32_t rtab_head:9; 621 uint32_t rsrvd2:7; 622 uint32_t rtab_tail:9; 623 #else 624 uint32_t rtab_tail:9; 625 uint32_t rsrvd2:7; 626 uint32_t rtab_head:9; 627 uint32_t rsrvd1:7; 628 uint32_t pkt_rtab_head:8; 629 uint32_t rsrvd:24; 630 #endif 631 } bits; 632 } tdc_rtab_ptr_t; 633 634 635 /* 636 * Register: TdcDropCnt 637 * Packet Drop Counter 638 * Description: Counts the number of runt, aborted and size 639 * mismatched packets dropped by the tx datapath block. 640 * Fields: 641 * Number of dropped due to pktSizeHdrErr. This counter will 642 * saturate. This counter is cleared on read. 643 * Number of dropped due to packet abort bit being set. Many 644 * different error events could be the source of packet abort 645 * drop. Descriptor-related error events include those errors 646 * encountered while in the middle of processing a packet 647 * request: 1. unexpectedSop; 2. non-SOP descriptor parity error 648 * (prefParErr); 3. ran out of non-SOP descriptors due to peu 649 * response errors (tdrPrefCplTo or peuRespErr) or the channel 650 * being disabled before the TDR request can be made. Packet 651 * response errors encountered while in the middle of processing 652 * a packet request also can trigger the packet abort: 4. packet 653 * response did not return due to peu response errors ( pktCplTo 654 * or peuRespErr); 5. Rtab parity error (reordTblParErr). This 655 * counter will saturate. This counter is cleared on read. Note 656 * that packet aborts are not counted until the packet is cleared 657 * from the RTab, which may be an arbitrary amount of time after 658 * the corresponding error is logged in TdcStat. In most cases, 659 * this will occur before the channel is quiesced following 660 * channel disable. In an extreme case such as if a parity error 661 * on an EOP descriptor prevents recognition of the EOP, it is 662 * possible that the quiescent bit itself will not be set 663 * although the packet drop counter will be incremented. 664 * Number of dropped due to runt packet size error. This counter 665 * will saturate. This counter is cleared on read. 666 */ 667 typedef union { 668 uint64_t value; 669 struct { 670 #if defined(_BIG_ENDIAN) 671 uint32_t rsrvd:32; 672 uint32_t rsrvd_l:8; 673 uint32_t hdr_size_error_count:8; 674 uint32_t abort_count:8; 675 uint32_t runt_count:8; 676 #else 677 uint32_t runt_count:8; 678 uint32_t abort_count:8; 679 uint32_t hdr_size_error_count:8; 680 uint32_t rsrvd_l:8; 681 uint32_t rsrvd:32; 682 #endif 683 } bits; 684 } tdc_drop_cnt_t; 685 686 687 /* 688 * Register: TdcLastPktRbufPtrs 689 * Last Packet RBUF Pointers 690 * Description: Logs the RBUF head and tail pointer of the last 691 * packet sent by the tx datapath block. 692 * Fields: 693 * Logs the RBUF tail pointer of the last packet sent 694 * Logs the RBUF head pointer of the last packet sent 695 */ 696 typedef union { 697 uint64_t value; 698 struct { 699 #if defined(_BIG_ENDIAN) 700 uint32_t rsrvd:32; 701 uint32_t rsrvd_l:4; 702 uint32_t rbuf_tail_ptr:12; 703 uint32_t rsrvd1:4; 704 uint32_t rbuf_head_ptr:12; 705 #else 706 uint32_t rbuf_head_ptr:12; 707 uint32_t rsrvd1:4; 708 uint32_t rbuf_tail_ptr:12; 709 uint32_t rsrvd_l:4; 710 uint32_t rsrvd:32; 711 #endif 712 } bits; 713 } tdc_last_pkt_rbuf_ptrs_t; 714 715 716 /* 717 * Register: TdcPrefCmd 718 * Tx DMA Prefetch Buffer Command 719 * Description: Allows debug access to the entire prefetch buffer. 720 * For writes, software writes the tdcPrefData and tdcPrefParData 721 * registers, before writing the tdcPrefCmd register. For reads, 722 * software writes the tdcPrefCmd register, then reads the 723 * tdcPrefData and tdcPrefParData registers. The valid field should 724 * be polled by software until it goes low, indicating the read or 725 * write has completed. Writing the tdcPrefCmd triggers the access. 726 * Fields: 727 * status of indirect access 0=busy 1=done 728 * Command type. 1 indicates a read command, 0 a write command. 729 * enable writing of parity bits 1=enabled, 0=disabled 730 * DMA channel of entry to read or write 731 * Entry in the prefetch buffer to read or write 732 */ 733 typedef union { 734 uint64_t value; 735 struct { 736 #if defined(_BIG_ENDIAN) 737 uint32_t rsrvd:32; 738 uint32_t status:1; 739 uint32_t cmd:1; 740 uint32_t par_en:1; 741 uint32_t rsrvd1:23; 742 uint32_t dmc:2; 743 uint32_t entry:4; 744 #else 745 uint32_t entry:4; 746 uint32_t dmc:2; 747 uint32_t rsrvd1:23; 748 uint32_t par_en:1; 749 uint32_t cmd:1; 750 uint32_t status:1; 751 uint32_t rsrvd:32; 752 #endif 753 } bits; 754 } tdc_pref_cmd_t; 755 756 757 /* 758 * Register: TdcPrefData 759 * Tx DMA Prefetch Buffer Data 760 * Description: See tdcPrefCmd register. 761 * Fields: 762 * For writes, data which is written into prefetch buffer. For 763 * reads, data read from the prefetch buffer. 764 */ 765 typedef union { 766 uint64_t value; 767 struct { 768 #if defined(_BIG_ENDIAN) 769 uint32_t data:32; 770 uint32_t data_l:32; 771 #else 772 uint32_t data_l:32; 773 uint32_t data:32; 774 #endif 775 } bits; 776 } tdc_pref_data_t; 777 778 779 /* 780 * Register: TdcPrefParData 781 * Tx DMA Prefetch Buffer Parity Data 782 * Description: See tdcPrefCmd register. 783 * Fields: 784 * For writes, parity data which is written into prefetch buffer. 785 * For reads, parity data read from the prefetch buffer. 786 */ 787 typedef union { 788 uint64_t value; 789 struct { 790 #if defined(_BIG_ENDIAN) 791 uint32_t rsrvd:32; 792 uint32_t rsrvd_l:24; 793 uint32_t par_data:8; 794 #else 795 uint32_t par_data:8; 796 uint32_t rsrvd_l:24; 797 uint32_t rsrvd:32; 798 #endif 799 } bits; 800 } tdc_pref_par_data_t; 801 802 803 /* 804 * Register: TdcReordBufCmd 805 * Tx DMA Reorder Buffer Command 806 * Description: Allows debug access to the entire Reorder buffer. For 807 * writes, software writes the tdcReordBufData and tdcReordBufEccData 808 * before writing the tdcReordBufCmd register. For reads, software 809 * writes the tdcReordBufCmd register, then reads the tdcReordBufData 810 * and tdcReordBufEccData registers. The valid field should be polled 811 * by software until it goes low, indicating the read or write has 812 * completed. Writing the tdcReordBufCmd triggers the access. 813 * Fields: 814 * status of indirect access 0=busy 1=done 815 * Command type. 1 indicates a read command, 0 a write command. 816 * enable writing of ecc bits 1=enabled, 0=disabled 817 * Entry in the reorder buffer to read or write 818 */ 819 typedef union { 820 uint64_t value; 821 struct { 822 #if defined(_BIG_ENDIAN) 823 uint32_t rsrvd:32; 824 uint32_t status:1; 825 uint32_t cmd:1; 826 uint32_t ecc_en:1; 827 uint32_t rsrvd1:17; 828 uint32_t entry:12; 829 #else 830 uint32_t entry:12; 831 uint32_t rsrvd1:17; 832 uint32_t ecc_en:1; 833 uint32_t cmd:1; 834 uint32_t status:1; 835 uint32_t rsrvd:32; 836 #endif 837 } bits; 838 } tdc_reord_buf_cmd_t; 839 840 841 /* 842 * Register: TdcReordBufData 843 * Tx DMA Reorder Buffer Data 844 * Description: See tdcReordBufCmd register. 845 * Fields: 846 * For writes, data which is written into reorder buffer. For 847 * reads, data read from the reorder buffer. 848 */ 849 typedef union { 850 uint64_t value; 851 struct { 852 #if defined(_BIG_ENDIAN) 853 uint32_t data:32; 854 uint32_t data_l:32; 855 #else 856 uint32_t data_l:32; 857 uint32_t data:32; 858 #endif 859 } bits; 860 } tdc_reord_buf_data_t; 861 862 863 /* 864 * Register: TdcReordBufEccData 865 * Tx DMA Reorder Buffer ECC Data 866 * Description: See tdcReordBufCmd register. 867 * Fields: 868 * For writes, ecc data which is written into reorder buffer. For 869 * reads, ecc data read from the reorder buffer. 870 */ 871 typedef union { 872 uint64_t value; 873 struct { 874 #if defined(_BIG_ENDIAN) 875 uint32_t rsrvd:32; 876 uint32_t rsrvd_l:24; 877 uint32_t ecc_data:8; 878 #else 879 uint32_t ecc_data:8; 880 uint32_t rsrvd_l:24; 881 uint32_t rsrvd:32; 882 #endif 883 } bits; 884 } tdc_reord_buf_ecc_data_t; 885 886 887 /* 888 * Register: TdcReordTblCmd 889 * Tx DMA Reorder Table Command 890 * Description: Allows debug access to the entire Reorder Table. For 891 * writes, software writes the tdcReordTblData and tdcReordTblParData 892 * before writing the tdcReordTblCmd register. For reads, software 893 * writes the tdcReordTblCmd register, then reads the tdcReordTblData 894 * and tdcReordTblParData registers. The valid field should be polled 895 * by software until it goes low, indicating the read or write has 896 * completed. Writing the tdcReordTblCmd triggers the access. 897 * Fields: 898 * status of indirect access 0=busy 1=done 899 * Command type. 1 indicates a read command, 0 a write command. 900 * enable writing of par bits 1=enabled, 0=disabled 901 * Address in the reorder table to read from or write to 902 */ 903 typedef union { 904 uint64_t value; 905 struct { 906 #if defined(_BIG_ENDIAN) 907 uint32_t rsrvd:32; 908 uint32_t status:1; 909 uint32_t cmd:1; 910 uint32_t par_en:1; 911 uint32_t rsrvd1:21; 912 uint32_t entry:8; 913 #else 914 uint32_t entry:8; 915 uint32_t rsrvd1:21; 916 uint32_t par_en:1; 917 uint32_t cmd:1; 918 uint32_t status:1; 919 uint32_t rsrvd:32; 920 #endif 921 } bits; 922 } tdc_reord_tbl_cmd_t; 923 924 925 /* 926 * Register: TdcReordTblDataLo 927 * Tx DMA Reorder Table Data Lo 928 * Description: See tdcReordTblCmd register. 929 * Fields: 930 * For writes, data which is written into reorder table. For 931 * reads, data read from the reorder table. 932 */ 933 typedef union { 934 uint64_t value; 935 struct { 936 #if defined(_BIG_ENDIAN) 937 uint32_t data:32; 938 uint32_t data_l:32; 939 #else 940 uint32_t data_l:32; 941 uint32_t data:32; 942 #endif 943 } bits; 944 } tdc_reord_tbl_data_lo_t; 945 946 947 /* 948 * Register: TdcReordTblDataHi 949 * Tx DMA Reorder Table Data Hi 950 * Description: See tdcReordTblCmd register. 951 * Fields: 952 * For writes, parity data which is written into reorder table. 953 * For reads, parity data read from the reorder table. 954 * For writes, data which is written into reorder table. For 955 * reads, data read from the reorder table. 956 */ 957 typedef union { 958 uint64_t value; 959 struct { 960 #if defined(_BIG_ENDIAN) 961 uint32_t rsrvd:32; 962 uint32_t rsrvd_l:15; 963 uint32_t par_data:9; 964 uint32_t hi_data:8; 965 #else 966 uint32_t hi_data:8; 967 uint32_t par_data:9; 968 uint32_t rsrvd_l:15; 969 uint32_t rsrvd:32; 970 #endif 971 } bits; 972 } tdc_reord_tbl_data_hi_t; 973 974 975 /* 976 * Register: TdcPrefParLog 977 * Tx DMA Prefetch Buffer Parity Log 978 * Description: TDC DMA Prefetch Buffer parity log register This 979 * register logs the first parity error encountered. Writing a 1 to 980 * TdcStat::prefParErr clears this register and re-arms for logging 981 * the next error 982 * Fields: 983 * Address of parity error read data 984 */ 985 typedef union { 986 uint64_t value; 987 struct { 988 #if defined(_BIG_ENDIAN) 989 uint32_t rsrvd:32; 990 uint32_t rsrvd1:26; 991 uint32_t address:6; 992 #else 993 uint32_t address:6; 994 uint32_t rsrvd1:26; 995 uint32_t rsrvd:32; 996 #endif 997 } bits; 998 } tdc_pref_par_log_t; 999 1000 1001 /* 1002 * Register: TdcReordBufEccLog 1003 * Tx Reorder Buffer ECC Log 1004 * Description: TDC Reorder Buffer ECC log register This register 1005 * logs the first ECC error encountered. Writing a 1 to 1006 * tdcFifoErrStat::reordBufDedErr or tdcFifoErrStat::reordBufSecErr 1007 * clears this register and re-arms for logging 1008 * Fields: 1009 * Address of ECC error 1010 * Syndrome of ECC error 1011 */ 1012 typedef union { 1013 uint64_t value; 1014 struct { 1015 #if defined(_BIG_ENDIAN) 1016 uint32_t rsrvd:32; 1017 uint32_t rsrvd1:4; 1018 uint32_t address:12; 1019 uint32_t rsrvd2:8; 1020 uint32_t syndrome:8; 1021 #else 1022 uint32_t syndrome:8; 1023 uint32_t rsrvd2:8; 1024 uint32_t address:12; 1025 uint32_t rsrvd1:4; 1026 uint32_t rsrvd:32; 1027 #endif 1028 } bits; 1029 } tdc_reord_buf_ecc_log_t; 1030 1031 1032 /* 1033 * Register: TdcReordTblParLog 1034 * Tx Reorder Table Parity Log 1035 * Description: TDC Reorder Table parity log register This register 1036 * logs the first parity error encountered. Writing a 1 to 1037 * tdcFifoErrStat::reordTblParErr clears this register and re-arms 1038 * for logging 1039 * Fields: 1040 * Address of parity error 1041 */ 1042 typedef union { 1043 uint64_t value; 1044 struct { 1045 #if defined(_BIG_ENDIAN) 1046 uint32_t rsrvd:32; 1047 uint32_t rsrvd1:24; 1048 uint32_t address:8; 1049 #else 1050 uint32_t address:8; 1051 uint32_t rsrvd1:24; 1052 uint32_t rsrvd:32; 1053 #endif 1054 } bits; 1055 } tdc_reord_tbl_par_log_t; 1056 1057 1058 /* 1059 * Register: TdcFifoErrMask 1060 * FIFO Error Mask 1061 * Description: FIFO Error Mask register. Mask status of Reorder 1062 * Buffer and Reorder Table Buffer Errors. 1063 * Fields: 1064 * Set to 0 to select the event to raise the LDF to indicate 1065 * reorder table ram received a parity error An Device Error 1 1066 * event. 1067 * Set to 0 to select the event to raise the LDF to indicate 1068 * reorder buffer ram received a ecc double bit error An Device 1069 * Error 1 event. 1070 * Set to 0 to select the event to raise the LDF to indicate 1071 * reorder buffer ram received a ecc single bit error An Device 1072 * Error 0 event. 1073 */ 1074 typedef union { 1075 uint64_t value; 1076 struct { 1077 #if defined(_BIG_ENDIAN) 1078 uint32_t rsrvd:32; 1079 uint32_t rsrvd_l:29; 1080 uint32_t reord_tbl_par_err:1; 1081 uint32_t reord_buf_ded_err:1; 1082 uint32_t reord_buf_sec_err:1; 1083 #else 1084 uint32_t reord_buf_sec_err:1; 1085 uint32_t reord_buf_ded_err:1; 1086 uint32_t reord_tbl_par_err:1; 1087 uint32_t rsrvd_l:29; 1088 uint32_t rsrvd:32; 1089 #endif 1090 } bits; 1091 } tdc_fifo_err_mask_t; 1092 1093 1094 /* 1095 * Register: TdcFifoErrStat 1096 * FIFO Error Status 1097 * Description: FIFO Error Status register. Log status of Reorder 1098 * Buffer and Reorder Table Buffer Errors. 1099 * Fields: 1100 * Set to 1 by HW to indicate reorder table ram received a parity 1101 * error Writing a 1 clears this bit and also clears the 1102 * TdcReordTblParLog register Fatal error. Part of Device Error 1103 * 1. 1104 * Set to 1 by HW to indicate reorder buffer ram received a 1105 * double bit ecc error Writing a 1 clears this bit and also 1106 * clears the tdcReordBufEccLog register Fatal error. Part of 1107 * Device Error 1. 1108 * Set to 1 by HW to indicate reorder buffer ram received a 1109 * single bit ecc error Writing a 1 clears this bit and also 1110 * clears the tdcReordBufEccLog register Non-Fatal error. Part of 1111 * Device Error 0. 1112 */ 1113 typedef union { 1114 uint64_t value; 1115 struct { 1116 #if defined(_BIG_ENDIAN) 1117 uint32_t rsrvd:32; 1118 uint32_t rsrvd_l:29; 1119 uint32_t reord_tbl_par_err:1; 1120 uint32_t reord_buf_ded_err:1; 1121 uint32_t reord_buf_sec_err:1; 1122 #else 1123 uint32_t reord_buf_sec_err:1; 1124 uint32_t reord_buf_ded_err:1; 1125 uint32_t reord_tbl_par_err:1; 1126 uint32_t rsrvd_l:29; 1127 uint32_t rsrvd:32; 1128 #endif 1129 } bits; 1130 } tdc_fifo_err_stat_t; 1131 1132 1133 /* 1134 * Register: TdcFifoErrIntDbg 1135 * FIFO Error Interrupt Debug 1136 * Description: FIFO Error Interrupt Debug register. Write this 1137 * regsiter to set bits in TdcFifoErrStat, allowing debug creation of 1138 * interrupts without needing to create the actual events. This 1139 * register holds no state. Reading this register gives the Tdc Fifo 1140 * Err Status data. Clear interrupt state by clearing TdcFifoErrStat. 1141 * For Debug only 1142 * Fields: 1143 * Set to 1 to select the event to raise the LDF to indicate 1144 * reorder table ram received a parity error An Device Error 1 1145 * event. 1146 * Set to 1 to select the event to raise the LDF to indicate 1147 * reorder buffer ram received a ecc double bit error An Device 1148 * Error 1 event. 1149 * Set to 1 to select the event to raise the LDF to indicate 1150 * reorder buffer ram received a ecc single bit error An Device 1151 * Error 0 event. 1152 */ 1153 typedef union { 1154 uint64_t value; 1155 struct { 1156 #if defined(_BIG_ENDIAN) 1157 uint32_t rsrvd:32; 1158 uint32_t rsrvd_l:29; 1159 uint32_t reord_tbl_par_err:1; 1160 uint32_t reord_buf_ded_err:1; 1161 uint32_t reord_buf_sec_err:1; 1162 #else 1163 uint32_t reord_buf_sec_err:1; 1164 uint32_t reord_buf_ded_err:1; 1165 uint32_t reord_tbl_par_err:1; 1166 uint32_t rsrvd_l:29; 1167 uint32_t rsrvd:32; 1168 #endif 1169 } bits; 1170 } tdc_fifo_err_int_dbg_t; 1171 1172 1173 /* 1174 * Register: TdcStatIntDbg 1175 * Transmit Status Interrupt Debug 1176 * Description: Write this regsiter to set bits in TdcStat, allowing 1177 * debug creation of interrupts without needing to create the actual 1178 * events. This register holds no state. Reading this register gives 1179 * the Transmit Control and Status data. Clear interrupt state by 1180 * clearing TdcStat. For Debug only 1181 * Fields: 1182 * Set to 1 to select the event to raise the LDF for packets 1183 * marked. An LDF 0 event. 1184 * Set to 1 to select the event to raise the LDF when poisoned 1185 * completion or non-zero (unsuccessful) completion status 1186 * received from PEU. An LDF 1 event. 1187 * Set to 1 to select the event to raise the LDF when total bytes 1188 * transmitted compared against pkt internal header bytes 1189 * transmitted mismatch. An LDF 1 event. 1190 * Set to 1 to select the event to raise the LDF when a runt 1191 * packet is dropped (when VMAC does not allow runt packets to be 1192 * padded). An LDF 1 event. 1193 * Set to 1 to select the event to raise the LDF when the packet 1194 * size exceeds hardware limit. An LDF 1 event. 1195 * Set to 1 to select the event to raise the LDF to indicate 1196 * Transmit Ring Overflow An LDF 1 event. 1197 * Set to 1 to select the event to raise the LDF to indicate 1198 * parity error on the tdr prefetch buffer occurred. An LDF 1 1199 * event. 1200 * Set to 1 to select the event to raise the LDF to indicate tdc 1201 * received a response completion timeout from peu for tdr 1202 * descriptor prefetch An LDF 1 event. 1203 * Set to 1 to select the event to raise the LDF to indicate tdc 1204 * received a response completion timeout from peu for packet 1205 * data request An LDF 1 event. 1206 * Set to 1 to select the event to raise the LDF to indicate tdc 1207 * did not receive an SOP in the 1st descriptor as was expected 1208 * or the numPtr in the 1st descriptor was set to 0. An LDF 1 1209 * event. 1210 * Set to 1 to select the event to raise the LDF to indicate tdc 1211 * received an unexpected SOP descriptor error. An LDF 1 event. 1212 */ 1213 typedef union { 1214 uint64_t value; 1215 struct { 1216 #if defined(_BIG_ENDIAN) 1217 uint32_t rsrvd:32; 1218 uint32_t rsrvd_l:16; 1219 uint32_t marked:1; 1220 uint32_t rsrvd1:5; 1221 uint32_t peu_resp_err:1; 1222 uint32_t pkt_size_hdr_err:1; 1223 uint32_t runt_pkt_drop_err:1; 1224 uint32_t pkt_size_err:1; 1225 uint32_t tx_rng_oflow:1; 1226 uint32_t pref_par_err:1; 1227 uint32_t tdr_pref_cpl_to:1; 1228 uint32_t pkt_cpl_to:1; 1229 uint32_t invalid_sop:1; 1230 uint32_t unexpected_sop:1; 1231 #else 1232 uint32_t unexpected_sop:1; 1233 uint32_t invalid_sop:1; 1234 uint32_t pkt_cpl_to:1; 1235 uint32_t tdr_pref_cpl_to:1; 1236 uint32_t pref_par_err:1; 1237 uint32_t tx_rng_oflow:1; 1238 uint32_t pkt_size_err:1; 1239 uint32_t runt_pkt_drop_err:1; 1240 uint32_t pkt_size_hdr_err:1; 1241 uint32_t peu_resp_err:1; 1242 uint32_t rsrvd1:5; 1243 uint32_t marked:1; 1244 uint32_t rsrvd_l:16; 1245 uint32_t rsrvd:32; 1246 #endif 1247 } bits; 1248 } tdc_stat_int_dbg_t; 1249 1250 1251 /* 1252 * Register: TdcPktReqTidTag 1253 * Packet Request TID Tag 1254 * Description: Packet Request TID Tag register Track the packet 1255 * request TID currently used 1256 * Fields: 1257 * When set to 1, it indicates the TID is currently being used 1258 */ 1259 typedef union { 1260 uint64_t value; 1261 struct { 1262 #if defined(_BIG_ENDIAN) 1263 uint32_t rsrvd:32; 1264 uint32_t pkt_req_tid_tag:24; 1265 uint32_t rsrvd1:8; 1266 #else 1267 uint32_t rsrvd1:8; 1268 uint32_t pkt_req_tid_tag:24; 1269 uint32_t rsrvd:32; 1270 #endif 1271 } bits; 1272 } tdc_pkt_req_tid_tag_t; 1273 1274 1275 /* 1276 * Register: TdcSopPrefDescLog 1277 * SOP Prefetch Descriptor Log 1278 * Description: SOP Descriptor Log register Logs the last SOP 1279 * prefetch descriptor processed by the packet request block. This 1280 * log could represent the current SOP prefetch descriptor if the 1281 * packet request block did not complete issuing the data requests 1282 * from this descriptor. Descriptors are logged to this register when 1283 * the packet request block is expecting an SOP descriptor, and it 1284 * receives it. 1285 * Fields: 1286 * Represents the last or current SOP descriptor being processed 1287 */ 1288 typedef union { 1289 uint64_t value; 1290 struct { 1291 #if defined(_BIG_ENDIAN) 1292 uint32_t sop_pref_desc_log:32; 1293 uint32_t sop_pref_desc_log_l:32; 1294 #else 1295 uint32_t sop_pref_desc_log_l:32; 1296 uint32_t sop_pref_desc_log:32; 1297 #endif 1298 } bits; 1299 } tdc_sop_pref_desc_log_t; 1300 1301 1302 /* 1303 * Register: TdcPrefDescLog 1304 * Prefetch Descriptor Log 1305 * Description: SOP Descriptor Log register Logs the last prefetch 1306 * descriptor processed by the packet request block. This log could 1307 * represent the current prefetch descriptor if the packet request 1308 * block did not complete issuing the data requests from this 1309 * descriptor. The contents in this register could differ from the 1310 * SOP Prefetch Descriptor Log register if a particular packet 1311 * requires usage of more than 1 descriptor. Descriptors are logged 1312 * to this register when the packet request block is expecting a 1313 * descriptor after the SOP descriptor. 1314 * Fields: 1315 * Represents the last or current descriptor being processed 1316 */ 1317 typedef union { 1318 uint64_t value; 1319 struct { 1320 #if defined(_BIG_ENDIAN) 1321 uint32_t pref_desc_log:32; 1322 uint32_t pref_desc_log_l:32; 1323 #else 1324 uint32_t pref_desc_log_l:32; 1325 uint32_t pref_desc_log:32; 1326 #endif 1327 } bits; 1328 } tdc_pref_desc_log_t; 1329 1330 1331 /* 1332 * Register: TdcPeuTxnLog 1333 * PEU Transaction Log 1334 * Description: PEU Transaction Log register. Counts the memory read 1335 * and write requests sent to peu block. For debug only. 1336 * Fields: 1337 * Counts the memory write transactions sent to peu block. This 1338 * counter saturates. This counter increments when vnmDbg is on 1339 * Counts the memory read transactions sent to peu block. This 1340 * counter saturates. This counter increments when vnmDbg is on 1341 */ 1342 typedef union { 1343 uint64_t value; 1344 struct { 1345 #if defined(_BIG_ENDIAN) 1346 uint32_t rsrvd:32; 1347 uint32_t rsrvd1:16; 1348 uint32_t peu_mem_wr_count:8; 1349 uint32_t peu_mem_rd_count:8; 1350 #else 1351 uint32_t peu_mem_rd_count:8; 1352 uint32_t peu_mem_wr_count:8; 1353 uint32_t rsrvd1:16; 1354 uint32_t rsrvd:32; 1355 #endif 1356 } bits; 1357 } tdc_peu_txn_log_t; 1358 1359 1360 /* 1361 * Register: TdcDbgTrainingVec 1362 * Debug Training Vector 1363 * Description: Debug Training Vector register. Debug Training Vector 1364 * for the coreClk domain. For the pcieClk domain, the dbgxMsb and 1365 * dbgyMsb values are flipped on the debug bus. 1366 * Fields: 1367 * Blade Number, the value read depends on the blade this block 1368 * resides 1369 * debug training vector the sub-group select value of 0 selects 1370 * this vector 1371 * Blade Number, the value read depends on the blade this block 1372 * resides 1373 * debug training vector the sub-group select value of 0 selects 1374 * this vector 1375 */ 1376 typedef union { 1377 uint64_t value; 1378 struct { 1379 #if defined(_BIG_ENDIAN) 1380 uint32_t rsrvd:32; 1381 uint32_t dbgx_msb:1; 1382 uint32_t dbgx_bld_num:3; 1383 uint32_t dbgx_training_vec:12; 1384 uint32_t dbgy_msb:1; 1385 uint32_t dbgy_bld_num:3; 1386 uint32_t dbgy_training_vec:12; 1387 #else 1388 uint32_t dbgy_training_vec:12; 1389 uint32_t dbgy_bld_num:3; 1390 uint32_t dbgy_msb:1; 1391 uint32_t dbgx_training_vec:12; 1392 uint32_t dbgx_bld_num:3; 1393 uint32_t dbgx_msb:1; 1394 uint32_t rsrvd:32; 1395 #endif 1396 } bits; 1397 } tdc_dbg_training_vec_t; 1398 1399 1400 /* 1401 * Register: TdcDbgGrpSel 1402 * Debug Group Select 1403 * Description: Debug Group Select register. Debug Group Select 1404 * register selects the group of signals brought out on the debug 1405 * port 1406 * Fields: 1407 * high 32b sub-group select 1408 * low 32b sub-group select 1409 */ 1410 typedef union { 1411 uint64_t value; 1412 struct { 1413 #if defined(_BIG_ENDIAN) 1414 uint32_t rsrvd:32; 1415 uint32_t rsrvd_l:16; 1416 uint32_t rsrvd1:1; 1417 uint32_t dbg_h32_sub_sel:7; 1418 uint32_t rsrvd2:1; 1419 uint32_t dbg_l32_sub_sel:7; 1420 #else 1421 uint32_t dbg_l32_sub_sel:7; 1422 uint32_t rsrvd2:1; 1423 uint32_t dbg_h32_sub_sel:7; 1424 uint32_t rsrvd1:1; 1425 uint32_t rsrvd_l:16; 1426 uint32_t rsrvd:32; 1427 #endif 1428 } bits; 1429 } tdc_dbg_grp_sel_t; 1430 1431 1432 #ifdef __cplusplus 1433 } 1434 #endif 1435 1436 #endif /* _HXGE_TDC_HW_H */ 1437