1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <hxge_impl.h> 28 29 extern uint32_t hxge_reclaim_pending; 30 extern uint32_t hxge_bcopy_thresh; 31 extern uint32_t hxge_dvma_thresh; 32 extern uint32_t hxge_dma_stream_thresh; 33 extern uint32_t hxge_tx_minfree; 34 extern uint32_t hxge_tx_intr_thres; 35 extern uint32_t hxge_tx_max_gathers; 36 extern uint32_t hxge_tx_tiny_pack; 37 extern uint32_t hxge_tx_use_bcopy; 38 39 static int hxge_start(p_hxge_t hxgep, p_tx_ring_t tx_ring_p, p_mblk_t mp); 40 41 void 42 hxge_tx_ring_task(void *arg) 43 { 44 p_tx_ring_t ring = (p_tx_ring_t)arg; 45 46 MUTEX_ENTER(&ring->lock); 47 (void) hxge_txdma_reclaim(ring->hxgep, ring, 0); 48 MUTEX_EXIT(&ring->lock); 49 50 mac_tx_ring_update(ring->hxgep->mach, ring->ring_handle); 51 } 52 53 static void 54 hxge_tx_ring_dispatch(p_tx_ring_t ring) 55 { 56 /* 57 * Kick the ring task to reclaim some buffers. 58 */ 59 (void) ddi_taskq_dispatch(ring->taskq, 60 hxge_tx_ring_task, (void *)ring, DDI_SLEEP); 61 } 62 63 mblk_t * 64 hxge_tx_ring_send(void *arg, mblk_t *mp) 65 { 66 p_hxge_ring_handle_t rhp = (p_hxge_ring_handle_t)arg; 67 p_hxge_t hxgep; 68 p_tx_ring_t tx_ring_p; 69 int status; 70 71 ASSERT(rhp != NULL); 72 ASSERT((rhp->index >= 0) && (rhp->index < HXGE_MAX_TDCS)); 73 74 hxgep = rhp->hxgep; 75 tx_ring_p = hxgep->tx_rings->rings[rhp->index]; 76 ASSERT(hxgep == tx_ring_p->hxgep); 77 78 status = hxge_start(hxgep, tx_ring_p, mp); 79 if (status != 0) { 80 hxge_tx_ring_dispatch(tx_ring_p); 81 return (mp); 82 } 83 84 return ((mblk_t *)NULL); 85 } 86 87 static int 88 hxge_start(p_hxge_t hxgep, p_tx_ring_t tx_ring_p, p_mblk_t mp) 89 { 90 int dma_status, status = 0; 91 p_tx_desc_t tx_desc_ring_vp; 92 hpi_handle_t hpi_desc_handle; 93 hxge_os_dma_handle_t tx_desc_dma_handle; 94 p_tx_desc_t tx_desc_p; 95 p_tx_msg_t tx_msg_ring; 96 p_tx_msg_t tx_msg_p; 97 tx_desc_t tx_desc, *tmp_desc_p; 98 tx_desc_t sop_tx_desc, *sop_tx_desc_p; 99 p_tx_pkt_header_t hdrp; 100 p_tx_pkt_hdr_all_t pkthdrp; 101 uint8_t npads = 0; 102 uint64_t dma_ioaddr; 103 uint32_t dma_flags; 104 int last_bidx; 105 uint8_t *b_rptr; 106 caddr_t kaddr; 107 uint32_t nmblks; 108 uint32_t ngathers; 109 uint32_t clen; 110 int len; 111 uint32_t pkt_len, pack_len, min_len; 112 uint32_t bcopy_thresh; 113 int i, cur_index, sop_index; 114 uint16_t tail_index; 115 boolean_t tail_wrap = B_FALSE; 116 hxge_dma_common_t desc_area; 117 hxge_os_dma_handle_t dma_handle; 118 ddi_dma_cookie_t dma_cookie; 119 hpi_handle_t hpi_handle; 120 p_mblk_t nmp; 121 p_mblk_t t_mp; 122 uint32_t ncookies; 123 boolean_t good_packet; 124 boolean_t mark_mode = B_FALSE; 125 p_hxge_stats_t statsp; 126 p_hxge_tx_ring_stats_t tdc_stats; 127 t_uscalar_t start_offset = 0; 128 t_uscalar_t stuff_offset = 0; 129 t_uscalar_t end_offset = 0; 130 t_uscalar_t value = 0; 131 t_uscalar_t cksum_flags = 0; 132 boolean_t cksum_on = B_FALSE; 133 uint32_t boff = 0; 134 uint64_t tot_xfer_len = 0, tmp_len = 0; 135 boolean_t header_set = B_FALSE; 136 tdc_tdr_kick_t kick; 137 uint32_t offset; 138 #ifdef HXGE_DEBUG 139 p_tx_desc_t tx_desc_ring_pp; 140 p_tx_desc_t tx_desc_pp; 141 tx_desc_t *save_desc_p; 142 int dump_len; 143 int sad_len; 144 uint64_t sad; 145 int xfer_len; 146 uint32_t msgsize; 147 #endif 148 149 HXGE_DEBUG_MSG((hxgep, TX_CTL, 150 "==> hxge_start: tx dma channel %d", tx_ring_p->tdc)); 151 HXGE_DEBUG_MSG((hxgep, TX_CTL, 152 "==> hxge_start: Starting tdc %d desc pending %d", 153 tx_ring_p->tdc, tx_ring_p->descs_pending)); 154 155 statsp = hxgep->statsp; 156 157 if (hxgep->statsp->port_stats.lb_mode == hxge_lb_normal) { 158 if (!statsp->mac_stats.link_up) { 159 freemsg(mp); 160 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start: " 161 "link not up or LB mode")); 162 goto hxge_start_fail1; 163 } 164 } 165 166 mac_hcksum_get(mp, &start_offset, &stuff_offset, &end_offset, &value, 167 &cksum_flags); 168 if (!HXGE_IS_VLAN_PACKET(mp->b_rptr)) { 169 start_offset += sizeof (ether_header_t); 170 stuff_offset += sizeof (ether_header_t); 171 } else { 172 start_offset += sizeof (struct ether_vlan_header); 173 stuff_offset += sizeof (struct ether_vlan_header); 174 } 175 176 if (cksum_flags & HCK_PARTIALCKSUM) { 177 HXGE_DEBUG_MSG((hxgep, TX_CTL, 178 "==> hxge_start: mp $%p len %d " 179 "cksum_flags 0x%x (partial checksum) ", 180 mp, MBLKL(mp), cksum_flags)); 181 cksum_on = B_TRUE; 182 } 183 184 MUTEX_ENTER(&tx_ring_p->lock); 185 ngathers = 0; 186 sop_index = tx_ring_p->wr_index; 187 #ifdef HXGE_DEBUG 188 if (tx_ring_p->descs_pending) { 189 HXGE_DEBUG_MSG((hxgep, TX_CTL, 190 "==> hxge_start: desc pending %d ", 191 tx_ring_p->descs_pending)); 192 } 193 194 dump_len = (int)(MBLKL(mp)); 195 dump_len = (dump_len > 128) ? 128: dump_len; 196 197 HXGE_DEBUG_MSG((hxgep, TX_CTL, 198 "==> hxge_start: tdc %d: dumping ...: b_rptr $%p " 199 "(Before header reserve: ORIGINAL LEN %d)", 200 tx_ring_p->tdc, mp->b_rptr, dump_len)); 201 202 HXGE_DEBUG_MSG((hxgep, TX_CTL, 203 "==> hxge_start: dump packets (IP ORIGINAL b_rptr $%p): %s", 204 mp->b_rptr, hxge_dump_packet((char *)mp->b_rptr, dump_len))); 205 #endif 206 207 tdc_stats = tx_ring_p->tdc_stats; 208 mark_mode = (tx_ring_p->descs_pending && 209 ((tx_ring_p->tx_ring_size - tx_ring_p->descs_pending) < 210 hxge_tx_minfree)); 211 212 HXGE_DEBUG_MSG((hxgep, TX_CTL, 213 "TX Descriptor ring is channel %d mark mode %d", 214 tx_ring_p->tdc, mark_mode)); 215 216 if (!hxge_txdma_reclaim(hxgep, tx_ring_p, hxge_tx_minfree)) { 217 HXGE_DEBUG_MSG((hxgep, TX_CTL, 218 "TX Descriptor ring is full: channel %d", tx_ring_p->tdc)); 219 HXGE_DEBUG_MSG((hxgep, TX_CTL, 220 "TX Descriptor ring is full: channel %d", tx_ring_p->tdc)); 221 (void) atomic_cas_32((uint32_t *)&tx_ring_p->queueing, 0, 1); 222 tdc_stats->tx_no_desc++; 223 MUTEX_EXIT(&tx_ring_p->lock); 224 status = 1; 225 goto hxge_start_fail1; 226 } 227 228 nmp = mp; 229 i = sop_index = tx_ring_p->wr_index; 230 nmblks = 0; 231 ngathers = 0; 232 pkt_len = 0; 233 pack_len = 0; 234 clen = 0; 235 last_bidx = -1; 236 good_packet = B_TRUE; 237 238 desc_area = tx_ring_p->tdc_desc; 239 hpi_handle = desc_area.hpi_handle; 240 hpi_desc_handle.regh = (hxge_os_acc_handle_t) 241 DMA_COMMON_ACC_HANDLE(desc_area); 242 hpi_desc_handle.hxgep = hxgep; 243 tx_desc_ring_vp = (p_tx_desc_t)DMA_COMMON_VPTR(desc_area); 244 #ifdef HXGE_DEBUG 245 tx_desc_ring_pp = (p_tx_desc_t)DMA_COMMON_IOADDR(desc_area); 246 #endif 247 tx_desc_dma_handle = (hxge_os_dma_handle_t)DMA_COMMON_HANDLE(desc_area); 248 tx_msg_ring = tx_ring_p->tx_msg_ring; 249 250 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start: wr_index %d i %d", 251 sop_index, i)); 252 253 #ifdef HXGE_DEBUG 254 msgsize = msgdsize(nmp); 255 HXGE_DEBUG_MSG((hxgep, TX_CTL, 256 "==> hxge_start(1): wr_index %d i %d msgdsize %d", 257 sop_index, i, msgsize)); 258 #endif 259 /* 260 * The first 16 bytes of the premapped buffer are reserved 261 * for header. No padding will be used. 262 */ 263 pkt_len = pack_len = boff = TX_PKT_HEADER_SIZE; 264 if (hxge_tx_use_bcopy) { 265 bcopy_thresh = (hxge_bcopy_thresh - TX_PKT_HEADER_SIZE); 266 } else { 267 bcopy_thresh = (TX_BCOPY_SIZE - TX_PKT_HEADER_SIZE); 268 } 269 while (nmp) { 270 good_packet = B_TRUE; 271 b_rptr = nmp->b_rptr; 272 len = MBLKL(nmp); 273 if (len <= 0) { 274 nmp = nmp->b_cont; 275 continue; 276 } 277 nmblks++; 278 279 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start(1): nmblks %d " 280 "len %d pkt_len %d pack_len %d", 281 nmblks, len, pkt_len, pack_len)); 282 /* 283 * Hardware limits the transfer length to 4K. 284 * If len is more than 4K, we need to break 285 * nmp into two chunks: Make first chunk smaller 286 * than 4K. The second chunk will be broken into 287 * less than 4K (if needed) during the next pass. 288 */ 289 if (len > (TX_MAX_TRANSFER_LENGTH - TX_PKT_HEADER_SIZE)) { 290 if ((t_mp = dupb(nmp)) != NULL) { 291 nmp->b_wptr = nmp->b_rptr + 292 (TX_MAX_TRANSFER_LENGTH - 293 TX_PKT_HEADER_SIZE); 294 t_mp->b_rptr = nmp->b_wptr; 295 t_mp->b_cont = nmp->b_cont; 296 nmp->b_cont = t_mp; 297 len = MBLKL(nmp); 298 } else { 299 good_packet = B_FALSE; 300 goto hxge_start_fail2; 301 } 302 } 303 tx_desc.value = 0; 304 tx_desc_p = &tx_desc_ring_vp[i]; 305 #ifdef HXGE_DEBUG 306 tx_desc_pp = &tx_desc_ring_pp[i]; 307 #endif 308 tx_msg_p = &tx_msg_ring[i]; 309 hpi_desc_handle.regp = (uint64_t)tx_desc_p; 310 if (!header_set && 311 ((!hxge_tx_use_bcopy && (len > TX_BCOPY_SIZE)) || 312 (len >= bcopy_thresh))) { 313 header_set = B_TRUE; 314 bcopy_thresh += TX_PKT_HEADER_SIZE; 315 boff = 0; 316 pack_len = 0; 317 kaddr = (caddr_t)DMA_COMMON_VPTR(tx_msg_p->buf_dma); 318 hdrp = (p_tx_pkt_header_t)kaddr; 319 clen = pkt_len; 320 dma_handle = tx_msg_p->buf_dma_handle; 321 dma_ioaddr = DMA_COMMON_IOADDR(tx_msg_p->buf_dma); 322 offset = tx_msg_p->offset_index * hxge_bcopy_thresh; 323 (void) ddi_dma_sync(dma_handle, 324 offset, hxge_bcopy_thresh, DDI_DMA_SYNC_FORDEV); 325 326 tx_msg_p->flags.dma_type = USE_BCOPY; 327 goto hxge_start_control_header_only; 328 } 329 330 pkt_len += len; 331 pack_len += len; 332 333 HXGE_DEBUG_MSG((hxgep, TX_CTL, 334 "==> hxge_start(3): desc entry %d DESC IOADDR $%p " 335 "desc_vp $%p tx_desc_p $%p desc_pp $%p tx_desc_pp $%p " 336 "len %d pkt_len %d pack_len %d", 337 i, 338 DMA_COMMON_IOADDR(desc_area), 339 tx_desc_ring_vp, tx_desc_p, 340 tx_desc_ring_pp, tx_desc_pp, 341 len, pkt_len, pack_len)); 342 343 if (len < bcopy_thresh) { 344 HXGE_DEBUG_MSG((hxgep, TX_CTL, 345 "==> hxge_start(4): USE BCOPY: ")); 346 if (hxge_tx_tiny_pack) { 347 uint32_t blst = TXDMA_DESC_NEXT_INDEX(i, -1, 348 tx_ring_p->tx_wrap_mask); 349 HXGE_DEBUG_MSG((hxgep, TX_CTL, 350 "==> hxge_start(5): pack")); 351 if ((pack_len <= bcopy_thresh) && 352 (last_bidx == blst)) { 353 HXGE_DEBUG_MSG((hxgep, TX_CTL, 354 "==> hxge_start: pack(6) " 355 "(pkt_len %d pack_len %d)", 356 pkt_len, pack_len)); 357 i = blst; 358 tx_desc_p = &tx_desc_ring_vp[i]; 359 #ifdef HXGE_DEBUG 360 tx_desc_pp = &tx_desc_ring_pp[i]; 361 #endif 362 tx_msg_p = &tx_msg_ring[i]; 363 boff = pack_len - len; 364 ngathers--; 365 } else if (pack_len > bcopy_thresh && 366 header_set) { 367 pack_len = len; 368 boff = 0; 369 bcopy_thresh = hxge_bcopy_thresh; 370 HXGE_DEBUG_MSG((hxgep, TX_CTL, 371 "==> hxge_start(7): > max NEW " 372 "bcopy thresh %d " 373 "pkt_len %d pack_len %d(next)", 374 bcopy_thresh, pkt_len, pack_len)); 375 } 376 last_bidx = i; 377 } 378 kaddr = (caddr_t)DMA_COMMON_VPTR(tx_msg_p->buf_dma); 379 if ((boff == TX_PKT_HEADER_SIZE) && (nmblks == 1)) { 380 hdrp = (p_tx_pkt_header_t)kaddr; 381 header_set = B_TRUE; 382 HXGE_DEBUG_MSG((hxgep, TX_CTL, 383 "==> hxge_start(7_x2): " 384 "pkt_len %d pack_len %d (new hdrp $%p)", 385 pkt_len, pack_len, hdrp)); 386 } 387 tx_msg_p->flags.dma_type = USE_BCOPY; 388 kaddr += boff; 389 HXGE_DEBUG_MSG((hxgep, TX_CTL, 390 "==> hxge_start(8): USE BCOPY: before bcopy " 391 "DESC IOADDR $%p entry %d bcopy packets %d " 392 "bcopy kaddr $%p bcopy ioaddr (SAD) $%p " 393 "bcopy clen %d bcopy boff %d", 394 DMA_COMMON_IOADDR(desc_area), i, 395 tdc_stats->tx_hdr_pkts, kaddr, dma_ioaddr, 396 clen, boff)); 397 HXGE_DEBUG_MSG((hxgep, TX_CTL, 398 "==> hxge_start: 1USE BCOPY: ")); 399 HXGE_DEBUG_MSG((hxgep, TX_CTL, 400 "==> hxge_start: 2USE BCOPY: ")); 401 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start: " 402 "last USE BCOPY: copy from b_rptr $%p " 403 "to KADDR $%p (len %d offset %d", 404 b_rptr, kaddr, len, boff)); 405 bcopy(b_rptr, kaddr, len); 406 #ifdef HXGE_DEBUG 407 dump_len = (len > 128) ? 128: len; 408 HXGE_DEBUG_MSG((hxgep, TX_CTL, 409 "==> hxge_start: dump packets " 410 "(After BCOPY len %d)" 411 "(b_rptr $%p): %s", len, nmp->b_rptr, 412 hxge_dump_packet((char *)nmp->b_rptr, 413 dump_len))); 414 #endif 415 dma_handle = tx_msg_p->buf_dma_handle; 416 dma_ioaddr = DMA_COMMON_IOADDR(tx_msg_p->buf_dma); 417 offset = tx_msg_p->offset_index * hxge_bcopy_thresh; 418 (void) ddi_dma_sync(dma_handle, 419 offset, hxge_bcopy_thresh, DDI_DMA_SYNC_FORDEV); 420 clen = len + boff; 421 tdc_stats->tx_hdr_pkts++; 422 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start(9): " 423 "USE BCOPY: DESC IOADDR $%p entry %d " 424 "bcopy packets %d bcopy kaddr $%p " 425 "bcopy ioaddr (SAD) $%p bcopy clen %d " 426 "bcopy boff %d", 427 DMA_COMMON_IOADDR(desc_area), i, 428 tdc_stats->tx_hdr_pkts, kaddr, dma_ioaddr, 429 clen, boff)); 430 } else { 431 HXGE_DEBUG_MSG((hxgep, TX_CTL, 432 "==> hxge_start(12): USE DVMA: len %d", len)); 433 tx_msg_p->flags.dma_type = USE_DMA; 434 dma_flags = DDI_DMA_WRITE; 435 if (len < hxge_dma_stream_thresh) { 436 dma_flags |= DDI_DMA_CONSISTENT; 437 } else { 438 dma_flags |= DDI_DMA_STREAMING; 439 } 440 441 dma_handle = tx_msg_p->dma_handle; 442 dma_status = ddi_dma_addr_bind_handle(dma_handle, NULL, 443 (caddr_t)b_rptr, len, dma_flags, 444 DDI_DMA_DONTWAIT, NULL, 445 &dma_cookie, &ncookies); 446 if (dma_status == DDI_DMA_MAPPED) { 447 dma_ioaddr = dma_cookie.dmac_laddress; 448 len = (int)dma_cookie.dmac_size; 449 clen = (uint32_t)dma_cookie.dmac_size; 450 HXGE_DEBUG_MSG((hxgep, TX_CTL, 451 "==> hxge_start(12_1): " 452 "USE DVMA: len %d clen %d ngathers %d", 453 len, clen, ngathers)); 454 hpi_desc_handle.regp = (uint64_t)tx_desc_p; 455 while (ncookies > 1) { 456 ngathers++; 457 /* 458 * this is the fix for multiple 459 * cookies, which are basically 460 * a descriptor entry, we don't set 461 * SOP bit as well as related fields 462 */ 463 464 (void) hpi_txdma_desc_gather_set( 465 hpi_desc_handle, &tx_desc, 466 (ngathers -1), mark_mode, 467 ngathers, dma_ioaddr, clen); 468 tx_msg_p->tx_msg_size = clen; 469 HXGE_DEBUG_MSG((hxgep, TX_CTL, 470 "==> hxge_start: DMA " 471 "ncookie %d ngathers %d " 472 "dma_ioaddr $%p len %d" 473 "desc $%p descp $%p (%d)", 474 ncookies, ngathers, 475 dma_ioaddr, clen, 476 *tx_desc_p, tx_desc_p, i)); 477 478 ddi_dma_nextcookie(dma_handle, 479 &dma_cookie); 480 dma_ioaddr = dma_cookie.dmac_laddress; 481 482 len = (int)dma_cookie.dmac_size; 483 clen = (uint32_t)dma_cookie.dmac_size; 484 HXGE_DEBUG_MSG((hxgep, TX_CTL, 485 "==> hxge_start(12_2): " 486 "USE DVMA: len %d clen %d ", 487 len, clen)); 488 489 i = TXDMA_DESC_NEXT_INDEX(i, 1, 490 tx_ring_p->tx_wrap_mask); 491 tx_desc_p = &tx_desc_ring_vp[i]; 492 493 hpi_desc_handle.regp = 494 (uint64_t)tx_desc_p; 495 tx_msg_p = &tx_msg_ring[i]; 496 tx_msg_p->flags.dma_type = USE_NONE; 497 tx_desc.value = 0; 498 ncookies--; 499 } 500 tdc_stats->tx_ddi_pkts++; 501 HXGE_DEBUG_MSG((hxgep, TX_CTL, 502 "==> hxge_start: DMA: ddi packets %d", 503 tdc_stats->tx_ddi_pkts)); 504 } else { 505 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 506 "dma mapping failed for %d " 507 "bytes addr $%p flags %x (%d)", 508 len, b_rptr, status, status)); 509 good_packet = B_FALSE; 510 tdc_stats->tx_dma_bind_fail++; 511 tx_msg_p->flags.dma_type = USE_NONE; 512 status = 1; 513 goto hxge_start_fail2; 514 } 515 } /* ddi dvma */ 516 517 nmp = nmp->b_cont; 518 hxge_start_control_header_only: 519 hpi_desc_handle.regp = (uint64_t)tx_desc_p; 520 ngathers++; 521 522 if (ngathers == 1) { 523 #ifdef HXGE_DEBUG 524 save_desc_p = &sop_tx_desc; 525 #endif 526 sop_tx_desc_p = &sop_tx_desc; 527 sop_tx_desc_p->value = 0; 528 sop_tx_desc_p->bits.tr_len = clen; 529 sop_tx_desc_p->bits.sad = dma_ioaddr >> 32; 530 sop_tx_desc_p->bits.sad_l = dma_ioaddr & 0xffffffff; 531 } else { 532 #ifdef HXGE_DEBUG 533 save_desc_p = &tx_desc; 534 #endif 535 tmp_desc_p = &tx_desc; 536 tmp_desc_p->value = 0; 537 tmp_desc_p->bits.tr_len = clen; 538 tmp_desc_p->bits.sad = dma_ioaddr >> 32; 539 tmp_desc_p->bits.sad_l = dma_ioaddr & 0xffffffff; 540 541 tx_desc_p->value = tmp_desc_p->value; 542 } 543 544 HXGE_DEBUG_MSG((hxgep, TX_CTL, 545 "==> hxge_start(13): Desc_entry %d ngathers %d " 546 "desc_vp $%p tx_desc_p $%p " 547 "len %d clen %d pkt_len %d pack_len %d nmblks %d " 548 "dma_ioaddr (SAD) $%p mark %d", 549 i, ngathers, tx_desc_ring_vp, tx_desc_p, 550 len, clen, pkt_len, pack_len, nmblks, 551 dma_ioaddr, mark_mode)); 552 553 #ifdef HXGE_DEBUG 554 hpi_desc_handle.hxgep = hxgep; 555 hpi_desc_handle.function.function = 0; 556 hpi_desc_handle.function.instance = hxgep->instance; 557 sad = save_desc_p->bits.sad; 558 sad = (sad << 32) | save_desc_p->bits.sad_l; 559 xfer_len = save_desc_p->bits.tr_len; 560 561 HXGE_DEBUG_MSG((hxgep, TX_CTL, "\n\t: value 0x%llx\n" 562 "\t\tsad $%p\ttr_len %d len %d\tnptrs %d\t" 563 "mark %d sop %d\n", 564 save_desc_p->value, sad, save_desc_p->bits.tr_len, 565 xfer_len, save_desc_p->bits.num_ptr, 566 save_desc_p->bits.mark, save_desc_p->bits.sop)); 567 568 hpi_txdma_dump_desc_one(hpi_desc_handle, NULL, i); 569 #endif 570 571 tx_msg_p->tx_msg_size = clen; 572 i = TXDMA_DESC_NEXT_INDEX(i, 1, tx_ring_p->tx_wrap_mask); 573 if (ngathers > hxge_tx_max_gathers) { 574 good_packet = B_FALSE; 575 mac_hcksum_get(mp, &start_offset, &stuff_offset, 576 &end_offset, &value, &cksum_flags); 577 578 HXGE_DEBUG_MSG((NULL, TX_CTL, 579 "==> hxge_start(14): pull msg - " 580 "len %d pkt_len %d ngathers %d", 581 len, pkt_len, ngathers)); 582 goto hxge_start_fail2; 583 } 584 } /* while (nmp) */ 585 586 tx_msg_p->tx_message = mp; 587 tx_desc_p = &tx_desc_ring_vp[sop_index]; 588 hpi_desc_handle.regp = (uint64_t)tx_desc_p; 589 590 pkthdrp = (p_tx_pkt_hdr_all_t)hdrp; 591 pkthdrp->reserved = 0; 592 hdrp->value = 0; 593 (void) hxge_fill_tx_hdr(mp, B_FALSE, cksum_on, 594 (pkt_len - TX_PKT_HEADER_SIZE), npads, pkthdrp); 595 596 /* 597 * Hardware header should not be counted as part of the frame 598 * when determining the frame size 599 */ 600 if ((pkt_len - TX_PKT_HEADER_SIZE) > (STD_FRAME_SIZE - ETHERFCSL)) { 601 tdc_stats->tx_jumbo_pkts++; 602 } 603 604 min_len = (hxgep->msg_min + TX_PKT_HEADER_SIZE + (npads * 2)); 605 if (pkt_len < min_len) { 606 /* Assume we use bcopy to premapped buffers */ 607 kaddr = (caddr_t)DMA_COMMON_VPTR(tx_msg_p->buf_dma); 608 HXGE_DEBUG_MSG((NULL, TX_CTL, 609 "==> hxge_start(14-1): < (msg_min + 16)" 610 "len %d pkt_len %d min_len %d bzero %d ngathers %d", 611 len, pkt_len, min_len, (min_len - pkt_len), ngathers)); 612 bzero((kaddr + pkt_len), (min_len - pkt_len)); 613 pkt_len = tx_msg_p->tx_msg_size = min_len; 614 615 sop_tx_desc_p->bits.tr_len = min_len; 616 617 HXGE_MEM_PIO_WRITE64(hpi_desc_handle, sop_tx_desc_p->value); 618 tx_desc_p->value = sop_tx_desc_p->value; 619 620 HXGE_DEBUG_MSG((NULL, TX_CTL, 621 "==> hxge_start(14-2): < msg_min - " 622 "len %d pkt_len %d min_len %d ngathers %d", 623 len, pkt_len, min_len, ngathers)); 624 } 625 626 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start: cksum_flags 0x%x ", 627 cksum_flags)); 628 if (cksum_flags & HCK_PARTIALCKSUM) { 629 HXGE_DEBUG_MSG((hxgep, TX_CTL, 630 "==> hxge_start: cksum_flags 0x%x (partial checksum) ", 631 cksum_flags)); 632 cksum_on = B_TRUE; 633 HXGE_DEBUG_MSG((hxgep, TX_CTL, 634 "==> hxge_start: from IP cksum_flags 0x%x " 635 "(partial checksum) " 636 "start_offset %d stuff_offset %d", 637 cksum_flags, start_offset, stuff_offset)); 638 tmp_len = (uint64_t)(start_offset >> 1); 639 hdrp->value |= (tmp_len << TX_PKT_HEADER_L4START_SHIFT); 640 tmp_len = (uint64_t)(stuff_offset >> 1); 641 hdrp->value |= (tmp_len << TX_PKT_HEADER_L4STUFF_SHIFT); 642 643 HXGE_DEBUG_MSG((hxgep, TX_CTL, 644 "==> hxge_start: from IP cksum_flags 0x%x " 645 "(partial checksum) " 646 "after SHIFT start_offset %d stuff_offset %d", 647 cksum_flags, start_offset, stuff_offset)); 648 } 649 650 /* 651 * pkt_len already includes 16 + paddings!! 652 * Update the control header length 653 */ 654 655 /* 656 * Note that Hydra is different from Neptune where 657 * tot_xfer_len = (pkt_len - TX_PKT_HEADER_SIZE); 658 */ 659 tot_xfer_len = pkt_len; 660 tmp_len = hdrp->value | 661 (tot_xfer_len << TX_PKT_HEADER_TOT_XFER_LEN_SHIFT); 662 663 HXGE_DEBUG_MSG((hxgep, TX_CTL, 664 "==> hxge_start(15_x1): setting SOP " 665 "tot_xfer_len 0x%llx (%d) pkt_len %d tmp_len " 666 "0x%llx hdrp->value 0x%llx", 667 tot_xfer_len, tot_xfer_len, pkt_len, tmp_len, hdrp->value)); 668 #if defined(_BIG_ENDIAN) 669 hdrp->value = ddi_swap64(tmp_len); 670 #else 671 hdrp->value = tmp_len; 672 #endif 673 HXGE_DEBUG_MSG((hxgep, 674 TX_CTL, "==> hxge_start(15_x2): setting SOP " 675 "after SWAP: tot_xfer_len 0x%llx pkt_len %d " 676 "tmp_len 0x%llx hdrp->value 0x%llx", 677 tot_xfer_len, pkt_len, tmp_len, hdrp->value)); 678 679 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start(15): setting SOP " 680 "wr_index %d tot_xfer_len (%d) pkt_len %d npads %d", 681 sop_index, tot_xfer_len, pkt_len, npads)); 682 683 sop_tx_desc_p->bits.sop = 1; 684 sop_tx_desc_p->bits.mark = mark_mode; 685 sop_tx_desc_p->bits.num_ptr = ngathers; 686 687 if (mark_mode) 688 tdc_stats->tx_marks++; 689 690 HXGE_MEM_PIO_WRITE64(hpi_desc_handle, sop_tx_desc_p->value); 691 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start(16): set SOP done")); 692 693 #ifdef HXGE_DEBUG 694 hpi_desc_handle.hxgep = hxgep; 695 hpi_desc_handle.function.function = 0; 696 hpi_desc_handle.function.instance = hxgep->instance; 697 698 HXGE_DEBUG_MSG((hxgep, TX_CTL, "\n\t: value 0x%llx\n" 699 "\t\tsad $%p\ttr_len %d len %d\tnptrs %d\tmark %d sop %d\n", 700 save_desc_p->value, sad, save_desc_p->bits.tr_len, 701 xfer_len, save_desc_p->bits.num_ptr, save_desc_p->bits.mark, 702 save_desc_p->bits.sop)); 703 (void) hpi_txdma_dump_desc_one(hpi_desc_handle, NULL, sop_index); 704 705 dump_len = (pkt_len > 128) ? 128: pkt_len; 706 HXGE_DEBUG_MSG((hxgep, TX_CTL, 707 "==> hxge_start: dump packets(17) (after sop set, len " 708 " (len/dump_len/pkt_len/tot_xfer_len) %d/%d/%d/%d):\n" 709 "ptr $%p: %s", len, dump_len, pkt_len, tot_xfer_len, 710 (char *)hdrp, hxge_dump_packet((char *)hdrp, dump_len))); 711 HXGE_DEBUG_MSG((hxgep, TX_CTL, 712 "==> hxge_start(18): TX desc sync: sop_index %d", sop_index)); 713 #endif 714 715 if ((ngathers == 1) || tx_ring_p->wr_index < i) { 716 (void) ddi_dma_sync(tx_desc_dma_handle, 717 sop_index * sizeof (tx_desc_t), 718 ngathers * sizeof (tx_desc_t), DDI_DMA_SYNC_FORDEV); 719 720 HXGE_DEBUG_MSG((hxgep, TX_CTL, "hxge_start(19): sync 1 " 721 "cs_off = 0x%02X cs_s_off = 0x%02X " 722 "pkt_len %d ngathers %d sop_index %d\n", 723 stuff_offset, start_offset, 724 pkt_len, ngathers, sop_index)); 725 } else { /* more than one descriptor and wrap around */ 726 uint32_t nsdescs = tx_ring_p->tx_ring_size - sop_index; 727 (void) ddi_dma_sync(tx_desc_dma_handle, 728 sop_index * sizeof (tx_desc_t), 729 nsdescs * sizeof (tx_desc_t), DDI_DMA_SYNC_FORDEV); 730 HXGE_DEBUG_MSG((hxgep, TX_CTL, "hxge_start(20): sync 1 " 731 "cs_off = 0x%02X cs_s_off = 0x%02X " 732 "pkt_len %d ngathers %d sop_index %d\n", 733 stuff_offset, start_offset, pkt_len, ngathers, sop_index)); 734 735 (void) ddi_dma_sync(tx_desc_dma_handle, 0, 736 (ngathers - nsdescs) * sizeof (tx_desc_t), 737 DDI_DMA_SYNC_FORDEV); 738 HXGE_DEBUG_MSG((hxgep, TX_CTL, "hxge_start(21): sync 2 " 739 "cs_off = 0x%02X cs_s_off = 0x%02X " 740 "pkt_len %d ngathers %d sop_index %d\n", 741 stuff_offset, start_offset, 742 pkt_len, ngathers, sop_index)); 743 } 744 745 tail_index = tx_ring_p->wr_index; 746 tail_wrap = tx_ring_p->wr_index_wrap; 747 748 tx_ring_p->wr_index = i; 749 if (tx_ring_p->wr_index <= tail_index) { 750 tx_ring_p->wr_index_wrap = ((tail_wrap == B_TRUE) ? 751 B_FALSE : B_TRUE); 752 } 753 754 tx_ring_p->descs_pending += ngathers; 755 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start: TX kick: " 756 "channel %d wr_index %d wrap %d ngathers %d desc_pend %d", 757 tx_ring_p->tdc, tx_ring_p->wr_index, tx_ring_p->wr_index_wrap, 758 ngathers, tx_ring_p->descs_pending)); 759 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start: TX KICKING: ")); 760 761 kick.value = 0; 762 kick.bits.wrap = tx_ring_p->wr_index_wrap; 763 kick.bits.tail = (uint16_t)tx_ring_p->wr_index; 764 765 /* Kick start the Transmit kick register */ 766 TXDMA_REG_WRITE64(HXGE_DEV_HPI_HANDLE(hxgep), 767 TDC_TDR_KICK, (uint8_t)tx_ring_p->tdc, kick.value); 768 tdc_stats->tx_starts++; 769 MUTEX_EXIT(&tx_ring_p->lock); 770 HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_start")); 771 return (status); 772 773 hxge_start_fail2: 774 if (good_packet == B_FALSE) { 775 cur_index = sop_index; 776 HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_start: clean up")); 777 for (i = 0; i < ngathers; i++) { 778 tx_desc_p = &tx_desc_ring_vp[cur_index]; 779 hpi_handle.regp = (uint64_t)tx_desc_p; 780 tx_msg_p = &tx_msg_ring[cur_index]; 781 (void) hpi_txdma_desc_set_zero(hpi_handle, 1); 782 if (tx_msg_p->flags.dma_type == USE_DVMA) { 783 HXGE_DEBUG_MSG((hxgep, TX_CTL, 784 "tx_desc_p = %X index = %d", 785 tx_desc_p, tx_ring_p->rd_index)); 786 (void) dvma_unload(tx_msg_p->dvma_handle, 787 0, -1); 788 tx_msg_p->dvma_handle = NULL; 789 if (tx_ring_p->dvma_wr_index == 790 tx_ring_p->dvma_wrap_mask) 791 tx_ring_p->dvma_wr_index = 0; 792 else 793 tx_ring_p->dvma_wr_index++; 794 tx_ring_p->dvma_pending--; 795 } else if (tx_msg_p->flags.dma_type == USE_DMA) { 796 if (ddi_dma_unbind_handle( 797 tx_msg_p->dma_handle)) { 798 cmn_err(CE_WARN, "hxge_start: " 799 "ddi_dma_unbind_handle failed"); 800 } 801 } 802 tx_msg_p->flags.dma_type = USE_NONE; 803 cur_index = TXDMA_DESC_NEXT_INDEX(cur_index, 1, 804 tx_ring_p->tx_wrap_mask); 805 806 } 807 } 808 809 MUTEX_EXIT(&tx_ring_p->lock); 810 811 hxge_start_fail1: 812 /* Add FMA to check the access handle hxge_hregh */ 813 HXGE_DEBUG_MSG((hxgep, TX_CTL, "<== hxge_start")); 814 return (status); 815 } 816