1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <hxge_impl.h> 27 #include <hxge_rxdma.h> 28 29 /* 30 * Number of blocks to accumulate before re-enabling DMA 31 * when we get RBR empty. 32 */ 33 #define HXGE_RBR_EMPTY_THRESHOLD 64 34 35 /* 36 * Globals: tunable parameters (/etc/system or adb) 37 * 38 */ 39 extern uint32_t hxge_rbr_size; 40 extern uint32_t hxge_rcr_size; 41 extern uint32_t hxge_rbr_spare_size; 42 extern uint32_t hxge_mblks_pending; 43 44 /* 45 * Tunable to reduce the amount of time spent in the 46 * ISR doing Rx Processing. 47 */ 48 extern uint32_t hxge_max_rx_pkts; 49 50 /* 51 * Tunables to manage the receive buffer blocks. 52 * 53 * hxge_rx_threshold_hi: copy all buffers. 54 * hxge_rx_bcopy_size_type: receive buffer block size type. 55 * hxge_rx_threshold_lo: copy only up to tunable block size type. 56 */ 57 extern hxge_rxbuf_threshold_t hxge_rx_threshold_hi; 58 extern hxge_rxbuf_type_t hxge_rx_buf_size_type; 59 extern hxge_rxbuf_threshold_t hxge_rx_threshold_lo; 60 61 /* 62 * Static local functions. 63 */ 64 static hxge_status_t hxge_map_rxdma(p_hxge_t hxgep); 65 static void hxge_unmap_rxdma(p_hxge_t hxgep); 66 static hxge_status_t hxge_rxdma_hw_start_common(p_hxge_t hxgep); 67 static hxge_status_t hxge_rxdma_hw_start(p_hxge_t hxgep); 68 static void hxge_rxdma_hw_stop(p_hxge_t hxgep); 69 static hxge_status_t hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 70 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 71 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 72 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 73 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 74 static void hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 75 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 76 static hxge_status_t hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, 77 uint16_t dma_channel, p_hxge_dma_common_t *dma_rbr_cntl_p, 78 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 79 p_rx_rbr_ring_t *rbr_p, p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 80 static void hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 81 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 82 static hxge_status_t hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, 83 uint16_t channel, p_hxge_dma_common_t *dma_buf_p, 84 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks); 85 static void hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 86 p_rx_rbr_ring_t rbr_p); 87 static hxge_status_t hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 88 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p, 89 int n_init_kick); 90 static hxge_status_t hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel); 91 static mblk_t *hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 92 p_rx_rcr_ring_t *rcr_p, rdc_stat_t cs); 93 static uint32_t hxge_scan_for_last_eop(p_rx_rcr_ring_t rcr_p, 94 p_rcr_entry_t rcr_desc_rd_head_p, uint32_t num_rcrs); 95 static void hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p, 96 p_rcr_entry_t rcr_desc_rd_head_p, boolean_t *multi_p, 97 mblk_t ** mp, mblk_t ** mp_cont, uint32_t *invalid_rcr_entry); 98 static hxge_status_t hxge_disable_rxdma_channel(p_hxge_t hxgep, 99 uint16_t channel); 100 static p_rx_msg_t hxge_allocb(size_t, uint32_t, p_hxge_dma_common_t); 101 static void hxge_freeb(p_rx_msg_t); 102 static void hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, 103 p_hxge_ldv_t ldvp, rdc_stat_t cs); 104 static hxge_status_t hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, 105 p_hxge_ldv_t ldvp, rdc_stat_t cs); 106 static hxge_status_t hxge_rxbuf_index_info_init(p_hxge_t hxgep, 107 p_rx_rbr_ring_t rx_dmap); 108 static hxge_status_t hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, 109 uint16_t channel); 110 static hxge_status_t hxge_rx_port_fatal_err_recover(p_hxge_t hxgep); 111 static void hxge_rbr_empty_restore(p_hxge_t hxgep, 112 p_rx_rbr_ring_t rx_rbr_p); 113 114 hxge_status_t 115 hxge_init_rxdma_channels(p_hxge_t hxgep) 116 { 117 hxge_status_t status = HXGE_OK; 118 block_reset_t reset_reg; 119 int i; 120 121 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_init_rxdma_channels")); 122 123 for (i = 0; i < HXGE_MAX_RDCS; i++) 124 hxgep->rdc_first_intr[i] = B_TRUE; 125 126 /* Reset RDC block from PEU to clear any previous state */ 127 reset_reg.value = 0; 128 reset_reg.bits.rdc_rst = 1; 129 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 130 HXGE_DELAY(1000); 131 132 status = hxge_map_rxdma(hxgep); 133 if (status != HXGE_OK) { 134 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 135 "<== hxge_init_rxdma: status 0x%x", status)); 136 return (status); 137 } 138 139 status = hxge_rxdma_hw_start_common(hxgep); 140 if (status != HXGE_OK) { 141 hxge_unmap_rxdma(hxgep); 142 } 143 144 status = hxge_rxdma_hw_start(hxgep); 145 if (status != HXGE_OK) { 146 hxge_unmap_rxdma(hxgep); 147 } 148 149 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 150 "<== hxge_init_rxdma_channels: status 0x%x", status)); 151 return (status); 152 } 153 154 void 155 hxge_uninit_rxdma_channels(p_hxge_t hxgep) 156 { 157 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_uninit_rxdma_channels")); 158 159 hxge_rxdma_hw_stop(hxgep); 160 hxge_unmap_rxdma(hxgep); 161 162 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_uinit_rxdma_channels")); 163 } 164 165 hxge_status_t 166 hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, uint16_t channel, 167 rdc_stat_t *cs_p) 168 { 169 hpi_handle_t handle; 170 hpi_status_t rs = HPI_SUCCESS; 171 hxge_status_t status = HXGE_OK; 172 173 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 174 "<== hxge_init_rxdma_channel_cntl_stat")); 175 176 handle = HXGE_DEV_HPI_HANDLE(hxgep); 177 rs = hpi_rxdma_control_status(handle, OP_SET, channel, cs_p); 178 179 if (rs != HPI_SUCCESS) { 180 status = HXGE_ERROR | rs; 181 } 182 return (status); 183 } 184 185 186 hxge_status_t 187 hxge_enable_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 188 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p, 189 int n_init_kick) 190 { 191 hpi_handle_t handle; 192 rdc_desc_cfg_t rdc_desc; 193 rdc_rcr_cfg_b_t *cfgb_p; 194 hpi_status_t rs = HPI_SUCCESS; 195 196 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel")); 197 handle = HXGE_DEV_HPI_HANDLE(hxgep); 198 199 /* 200 * Use configuration data composed at init time. Write to hardware the 201 * receive ring configurations. 202 */ 203 rdc_desc.mbox_enable = 1; 204 rdc_desc.mbox_addr = mbox_p->mbox_addr; 205 HXGE_DEBUG_MSG((hxgep, RX_CTL, 206 "==> hxge_enable_rxdma_channel: mboxp $%p($%p)", 207 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 208 209 rdc_desc.rbr_len = rbr_p->rbb_max; 210 rdc_desc.rbr_addr = rbr_p->rbr_addr; 211 212 switch (hxgep->rx_bksize_code) { 213 case RBR_BKSIZE_4K: 214 rdc_desc.page_size = SIZE_4KB; 215 break; 216 case RBR_BKSIZE_8K: 217 rdc_desc.page_size = SIZE_8KB; 218 break; 219 } 220 221 rdc_desc.size0 = rbr_p->hpi_pkt_buf_size0; 222 rdc_desc.valid0 = 1; 223 224 rdc_desc.size1 = rbr_p->hpi_pkt_buf_size1; 225 rdc_desc.valid1 = 1; 226 227 rdc_desc.size2 = rbr_p->hpi_pkt_buf_size2; 228 rdc_desc.valid2 = 1; 229 230 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 231 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 232 233 rdc_desc.rcr_len = rcr_p->comp_size; 234 rdc_desc.rcr_addr = rcr_p->rcr_addr; 235 236 cfgb_p = &(rcr_p->rcr_cfgb); 237 rdc_desc.rcr_threshold = cfgb_p->bits.pthres; 238 rdc_desc.rcr_timeout = cfgb_p->bits.timeout; 239 rdc_desc.rcr_timeout_enable = cfgb_p->bits.entout; 240 241 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 242 "rbr_len qlen %d pagesize code %d rcr_len %d", 243 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 244 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 245 "size 0 %d size 1 %d size 2 %d", 246 rbr_p->hpi_pkt_buf_size0, rbr_p->hpi_pkt_buf_size1, 247 rbr_p->hpi_pkt_buf_size2)); 248 249 rs = hpi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 250 if (rs != HPI_SUCCESS) { 251 return (HXGE_ERROR | rs); 252 } 253 254 /* 255 * Enable the timeout and threshold. 256 */ 257 rs = hpi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 258 rdc_desc.rcr_threshold); 259 if (rs != HPI_SUCCESS) { 260 return (HXGE_ERROR | rs); 261 } 262 263 rs = hpi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 264 rdc_desc.rcr_timeout); 265 if (rs != HPI_SUCCESS) { 266 return (HXGE_ERROR | rs); 267 } 268 269 /* Enable the DMA */ 270 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 271 if (rs != HPI_SUCCESS) { 272 return (HXGE_ERROR | rs); 273 } 274 275 /* Kick the DMA engine */ 276 hpi_rxdma_rdc_rbr_kick(handle, channel, n_init_kick); 277 278 /* Clear the rbr empty bit */ 279 (void) hpi_rxdma_channel_rbr_empty_clear(handle, channel); 280 281 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_enable_rxdma_channel")); 282 283 return (HXGE_OK); 284 } 285 286 static hxge_status_t 287 hxge_disable_rxdma_channel(p_hxge_t hxgep, uint16_t channel) 288 { 289 hpi_handle_t handle; 290 hpi_status_t rs = HPI_SUCCESS; 291 292 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_disable_rxdma_channel")); 293 294 handle = HXGE_DEV_HPI_HANDLE(hxgep); 295 296 /* disable the DMA */ 297 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 298 if (rs != HPI_SUCCESS) { 299 HXGE_DEBUG_MSG((hxgep, RX_CTL, 300 "<== hxge_disable_rxdma_channel:failed (0x%x)", rs)); 301 return (HXGE_ERROR | rs); 302 } 303 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_disable_rxdma_channel")); 304 return (HXGE_OK); 305 } 306 307 hxge_status_t 308 hxge_rxdma_channel_rcrflush(p_hxge_t hxgep, uint8_t channel) 309 { 310 hpi_handle_t handle; 311 hxge_status_t status = HXGE_OK; 312 313 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 314 "==> hxge_rxdma_channel_rcrflush")); 315 316 handle = HXGE_DEV_HPI_HANDLE(hxgep); 317 hpi_rxdma_rdc_rcr_flush(handle, channel); 318 319 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 320 "<== hxge_rxdma_channel_rcrflush")); 321 return (status); 322 323 } 324 325 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 326 327 #define TO_LEFT -1 328 #define TO_RIGHT 1 329 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 330 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 331 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 332 #define NO_HINT 0xffffffff 333 334 /*ARGSUSED*/ 335 hxge_status_t 336 hxge_rxbuf_pp_to_vp(p_hxge_t hxgep, p_rx_rbr_ring_t rbr_p, 337 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 338 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 339 { 340 int bufsize; 341 uint64_t pktbuf_pp; 342 uint64_t dvma_addr; 343 rxring_info_t *ring_info; 344 int base_side, end_side; 345 int r_index, l_index, anchor_index; 346 int found, search_done; 347 uint32_t offset, chunk_size, block_size, page_size_mask; 348 uint32_t chunk_index, block_index, total_index; 349 int max_iterations, iteration; 350 rxbuf_index_info_t *bufinfo; 351 352 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_rxbuf_pp_to_vp")); 353 354 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 355 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 356 pkt_buf_addr_pp, pktbufsz_type)); 357 358 #if defined(__i386) 359 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 360 #else 361 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 362 #endif 363 364 switch (pktbufsz_type) { 365 case 0: 366 bufsize = rbr_p->pkt_buf_size0; 367 break; 368 case 1: 369 bufsize = rbr_p->pkt_buf_size1; 370 break; 371 case 2: 372 bufsize = rbr_p->pkt_buf_size2; 373 break; 374 case RCR_SINGLE_BLOCK: 375 bufsize = 0; 376 anchor_index = 0; 377 break; 378 default: 379 return (HXGE_ERROR); 380 } 381 382 if (rbr_p->num_blocks == 1) { 383 anchor_index = 0; 384 ring_info = rbr_p->ring_info; 385 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 386 387 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 388 "==> hxge_rxbuf_pp_to_vp: (found, 1 block) " 389 "buf_pp $%p btype %d anchor_index %d bufinfo $%p", 390 pkt_buf_addr_pp, pktbufsz_type, anchor_index, bufinfo)); 391 392 goto found_index; 393 } 394 395 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 396 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d anchor_index %d", 397 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 398 399 ring_info = rbr_p->ring_info; 400 found = B_FALSE; 401 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 402 iteration = 0; 403 max_iterations = ring_info->max_iterations; 404 405 /* 406 * First check if this block have been seen recently. This is indicated 407 * by a hint which is initialized when the first buffer of the block is 408 * seen. The hint is reset when the last buffer of the block has been 409 * processed. As three block sizes are supported, three hints are kept. 410 * The idea behind the hints is that once the hardware uses a block 411 * for a buffer of that size, it will use it exclusively for that size 412 * and will use it until it is exhausted. It is assumed that there 413 * would a single block being used for the same buffer sizes at any 414 * given time. 415 */ 416 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 417 anchor_index = ring_info->hint[pktbufsz_type]; 418 dvma_addr = bufinfo[anchor_index].dvma_addr; 419 chunk_size = bufinfo[anchor_index].buf_size; 420 if ((pktbuf_pp >= dvma_addr) && 421 (pktbuf_pp < (dvma_addr + chunk_size))) { 422 found = B_TRUE; 423 /* 424 * check if this is the last buffer in the block If so, 425 * then reset the hint for the size; 426 */ 427 428 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 429 ring_info->hint[pktbufsz_type] = NO_HINT; 430 } 431 } 432 433 if (found == B_FALSE) { 434 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 435 "==> hxge_rxbuf_pp_to_vp: (!found)" 436 "buf_pp $%p btype %d anchor_index %d", 437 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 438 439 /* 440 * This is the first buffer of the block of this size. Need to 441 * search the whole information array. the search algorithm 442 * uses a binary tree search algorithm. It assumes that the 443 * information is already sorted with increasing order info[0] 444 * < info[1] < info[2] .... < info[n-1] where n is the size of 445 * the information array 446 */ 447 r_index = rbr_p->num_blocks - 1; 448 l_index = 0; 449 search_done = B_FALSE; 450 anchor_index = MID_INDEX(r_index, l_index); 451 while (search_done == B_FALSE) { 452 if ((r_index == l_index) || 453 (iteration >= max_iterations)) 454 search_done = B_TRUE; 455 456 end_side = TO_RIGHT; /* to the right */ 457 base_side = TO_LEFT; /* to the left */ 458 /* read the DVMA address information and sort it */ 459 dvma_addr = bufinfo[anchor_index].dvma_addr; 460 chunk_size = bufinfo[anchor_index].buf_size; 461 462 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 463 "==> hxge_rxbuf_pp_to_vp: (searching)" 464 "buf_pp $%p btype %d " 465 "anchor_index %d chunk_size %d dvmaaddr $%p", 466 pkt_buf_addr_pp, pktbufsz_type, anchor_index, 467 chunk_size, dvma_addr)); 468 469 if (pktbuf_pp >= dvma_addr) 470 base_side = TO_RIGHT; /* to the right */ 471 if (pktbuf_pp < (dvma_addr + chunk_size)) 472 end_side = TO_LEFT; /* to the left */ 473 474 switch (base_side + end_side) { 475 case IN_MIDDLE: 476 /* found */ 477 found = B_TRUE; 478 search_done = B_TRUE; 479 if ((pktbuf_pp + bufsize) < 480 (dvma_addr + chunk_size)) 481 ring_info->hint[pktbufsz_type] = 482 bufinfo[anchor_index].buf_index; 483 break; 484 case BOTH_RIGHT: 485 /* not found: go to the right */ 486 l_index = anchor_index + 1; 487 anchor_index = MID_INDEX(r_index, l_index); 488 break; 489 490 case BOTH_LEFT: 491 /* not found: go to the left */ 492 r_index = anchor_index - 1; 493 anchor_index = MID_INDEX(r_index, l_index); 494 break; 495 default: /* should not come here */ 496 return (HXGE_ERROR); 497 } 498 iteration++; 499 } 500 501 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 502 "==> hxge_rxbuf_pp_to_vp: (search done)" 503 "buf_pp $%p btype %d anchor_index %d", 504 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 505 } 506 507 if (found == B_FALSE) { 508 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 509 "==> hxge_rxbuf_pp_to_vp: (search failed)" 510 "buf_pp $%p btype %d anchor_index %d", 511 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 512 return (HXGE_ERROR); 513 } 514 515 found_index: 516 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 517 "==> hxge_rxbuf_pp_to_vp: (FOUND1)" 518 "buf_pp $%p btype %d bufsize %d anchor_index %d", 519 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index)); 520 521 /* index of the first block in this chunk */ 522 chunk_index = bufinfo[anchor_index].start_index; 523 dvma_addr = bufinfo[anchor_index].dvma_addr; 524 page_size_mask = ring_info->block_size_mask; 525 526 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 527 "==> hxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 528 "buf_pp $%p btype %d bufsize %d " 529 "anchor_index %d chunk_index %d dvma $%p", 530 pkt_buf_addr_pp, pktbufsz_type, bufsize, 531 anchor_index, chunk_index, dvma_addr)); 532 533 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 534 block_size = rbr_p->block_size; /* System block(page) size */ 535 536 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 537 "==> hxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 538 "buf_pp $%p btype %d bufsize %d " 539 "anchor_index %d chunk_index %d dvma $%p " 540 "offset %d block_size %d", 541 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index, 542 chunk_index, dvma_addr, offset, block_size)); 543 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> getting total index")); 544 545 block_index = (offset / block_size); /* index within chunk */ 546 total_index = chunk_index + block_index; 547 548 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 549 "==> hxge_rxbuf_pp_to_vp: " 550 "total_index %d dvma_addr $%p " 551 "offset %d block_size %d " 552 "block_index %d ", 553 total_index, dvma_addr, offset, block_size, block_index)); 554 555 #if defined(__i386) 556 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 557 (uint32_t)offset); 558 #else 559 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 560 offset); 561 #endif 562 563 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 564 "==> hxge_rxbuf_pp_to_vp: " 565 "total_index %d dvma_addr $%p " 566 "offset %d block_size %d " 567 "block_index %d " 568 "*pkt_buf_addr_p $%p", 569 total_index, dvma_addr, offset, block_size, 570 block_index, *pkt_buf_addr_p)); 571 572 *msg_index = total_index; 573 *bufoffset = (offset & page_size_mask); 574 575 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 576 "==> hxge_rxbuf_pp_to_vp: get msg index: " 577 "msg_index %d bufoffset_index %d", 578 *msg_index, *bufoffset)); 579 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "<== hxge_rxbuf_pp_to_vp")); 580 581 return (HXGE_OK); 582 } 583 584 585 /* 586 * used by quick sort (qsort) function 587 * to perform comparison 588 */ 589 static int 590 hxge_sort_compare(const void *p1, const void *p2) 591 { 592 593 rxbuf_index_info_t *a, *b; 594 595 a = (rxbuf_index_info_t *)p1; 596 b = (rxbuf_index_info_t *)p2; 597 598 if (a->dvma_addr > b->dvma_addr) 599 return (1); 600 if (a->dvma_addr < b->dvma_addr) 601 return (-1); 602 return (0); 603 } 604 605 /* 606 * Grabbed this sort implementation from common/syscall/avl.c 607 * 608 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 609 * v = Ptr to array/vector of objs 610 * n = # objs in the array 611 * s = size of each obj (must be multiples of a word size) 612 * f = ptr to function to compare two objs 613 * returns (-1 = less than, 0 = equal, 1 = greater than 614 */ 615 void 616 hxge_ksort(caddr_t v, int n, int s, int (*f) ()) 617 { 618 int g, i, j, ii; 619 unsigned int *p1, *p2; 620 unsigned int tmp; 621 622 /* No work to do */ 623 if (v == NULL || n <= 1) 624 return; 625 /* Sanity check on arguments */ 626 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 627 ASSERT(s > 0); 628 629 for (g = n / 2; g > 0; g /= 2) { 630 for (i = g; i < n; i++) { 631 for (j = i - g; j >= 0 && 632 (*f) (v + j * s, v + (j + g) * s) == 1; j -= g) { 633 p1 = (unsigned *)(v + j * s); 634 p2 = (unsigned *)(v + (j + g) * s); 635 for (ii = 0; ii < s / 4; ii++) { 636 tmp = *p1; 637 *p1++ = *p2; 638 *p2++ = tmp; 639 } 640 } 641 } 642 } 643 } 644 645 /* 646 * Initialize data structures required for rxdma 647 * buffer dvma->vmem address lookup 648 */ 649 /*ARGSUSED*/ 650 static hxge_status_t 651 hxge_rxbuf_index_info_init(p_hxge_t hxgep, p_rx_rbr_ring_t rbrp) 652 { 653 int index; 654 rxring_info_t *ring_info; 655 int max_iteration = 0, max_index = 0; 656 657 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_rxbuf_index_info_init")); 658 659 ring_info = rbrp->ring_info; 660 ring_info->hint[0] = NO_HINT; 661 ring_info->hint[1] = NO_HINT; 662 ring_info->hint[2] = NO_HINT; 663 max_index = rbrp->num_blocks; 664 665 /* read the DVMA address information and sort it */ 666 /* do init of the information array */ 667 668 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 669 " hxge_rxbuf_index_info_init Sort ptrs")); 670 671 /* sort the array */ 672 hxge_ksort((void *) ring_info->buffer, max_index, 673 sizeof (rxbuf_index_info_t), hxge_sort_compare); 674 675 for (index = 0; index < max_index; index++) { 676 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 677 " hxge_rxbuf_index_info_init: sorted chunk %d " 678 " ioaddr $%p kaddr $%p size %x", 679 index, ring_info->buffer[index].dvma_addr, 680 ring_info->buffer[index].kaddr, 681 ring_info->buffer[index].buf_size)); 682 } 683 684 max_iteration = 0; 685 while (max_index >= (1ULL << max_iteration)) 686 max_iteration++; 687 ring_info->max_iterations = max_iteration + 1; 688 689 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 690 " hxge_rxbuf_index_info_init Find max iter %d", 691 ring_info->max_iterations)); 692 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_rxbuf_index_info_init")); 693 694 return (HXGE_OK); 695 } 696 697 /*ARGSUSED*/ 698 void 699 hxge_dump_rcr_entry(p_hxge_t hxgep, p_rcr_entry_t entry_p) 700 { 701 #ifdef HXGE_DEBUG 702 703 uint32_t bptr; 704 uint64_t pp; 705 706 bptr = entry_p->bits.pkt_buf_addr; 707 708 HXGE_DEBUG_MSG((hxgep, RX_CTL, 709 "\trcr entry $%p " 710 "\trcr entry 0x%0llx " 711 "\trcr entry 0x%08x " 712 "\trcr entry 0x%08x " 713 "\tvalue 0x%0llx\n" 714 "\tmulti = %d\n" 715 "\tpkt_type = 0x%x\n" 716 "\terror = 0x%04x\n" 717 "\tl2_len = %d\n" 718 "\tpktbufsize = %d\n" 719 "\tpkt_buf_addr = $%p\n" 720 "\tpkt_buf_addr (<< 6) = $%p\n", 721 entry_p, 722 *(int64_t *)entry_p, 723 *(int32_t *)entry_p, 724 *(int32_t *)((char *)entry_p + 32), 725 entry_p->value, 726 entry_p->bits.multi, 727 entry_p->bits.pkt_type, 728 entry_p->bits.error, 729 entry_p->bits.l2_len, 730 entry_p->bits.pktbufsz, 731 bptr, 732 entry_p->bits.pkt_buf_addr_l)); 733 734 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 735 RCR_PKT_BUF_ADDR_SHIFT; 736 737 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 738 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 739 #endif 740 } 741 742 /*ARGSUSED*/ 743 void 744 hxge_rxdma_stop(p_hxge_t hxgep) 745 { 746 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop")); 747 748 (void) hxge_rx_vmac_disable(hxgep); 749 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP); 750 751 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop")); 752 } 753 754 void 755 hxge_rxdma_stop_reinit(p_hxge_t hxgep) 756 { 757 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_reinit")); 758 759 (void) hxge_rxdma_stop(hxgep); 760 (void) hxge_uninit_rxdma_channels(hxgep); 761 (void) hxge_init_rxdma_channels(hxgep); 762 763 (void) hxge_rx_vmac_enable(hxgep); 764 765 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_reinit")); 766 } 767 768 hxge_status_t 769 hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable) 770 { 771 int i, ndmas; 772 uint16_t channel; 773 p_rx_rbr_rings_t rx_rbr_rings; 774 p_rx_rbr_ring_t *rbr_rings; 775 hpi_handle_t handle; 776 hpi_status_t rs = HPI_SUCCESS; 777 hxge_status_t status = HXGE_OK; 778 779 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 780 "==> hxge_rxdma_hw_mode: mode %d", enable)); 781 782 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 783 HXGE_DEBUG_MSG((hxgep, RX_CTL, 784 "<== hxge_rxdma_mode: not initialized")); 785 return (HXGE_ERROR); 786 } 787 788 rx_rbr_rings = hxgep->rx_rbr_rings; 789 if (rx_rbr_rings == NULL) { 790 HXGE_DEBUG_MSG((hxgep, RX_CTL, 791 "<== hxge_rxdma_mode: NULL ring pointer")); 792 return (HXGE_ERROR); 793 } 794 795 if (rx_rbr_rings->rbr_rings == NULL) { 796 HXGE_DEBUG_MSG((hxgep, RX_CTL, 797 "<== hxge_rxdma_mode: NULL rbr rings pointer")); 798 return (HXGE_ERROR); 799 } 800 801 ndmas = rx_rbr_rings->ndmas; 802 if (!ndmas) { 803 HXGE_DEBUG_MSG((hxgep, RX_CTL, 804 "<== hxge_rxdma_mode: no channel")); 805 return (HXGE_ERROR); 806 } 807 808 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 809 "==> hxge_rxdma_mode (ndmas %d)", ndmas)); 810 811 rbr_rings = rx_rbr_rings->rbr_rings; 812 813 handle = HXGE_DEV_HPI_HANDLE(hxgep); 814 815 for (i = 0; i < ndmas; i++) { 816 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 817 continue; 818 } 819 channel = rbr_rings[i]->rdc; 820 if (enable) { 821 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 822 "==> hxge_rxdma_hw_mode: channel %d (enable)", 823 channel)); 824 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 825 } else { 826 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 827 "==> hxge_rxdma_hw_mode: channel %d (disable)", 828 channel)); 829 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 830 } 831 } 832 833 status = ((rs == HPI_SUCCESS) ? HXGE_OK : HXGE_ERROR | rs); 834 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 835 "<== hxge_rxdma_hw_mode: status 0x%x", status)); 836 837 return (status); 838 } 839 840 int 841 hxge_rxdma_get_ring_index(p_hxge_t hxgep, uint16_t channel) 842 { 843 int i, ndmas; 844 uint16_t rdc; 845 p_rx_rbr_rings_t rx_rbr_rings; 846 p_rx_rbr_ring_t *rbr_rings; 847 848 HXGE_DEBUG_MSG((hxgep, RX_CTL, 849 "==> hxge_rxdma_get_ring_index: channel %d", channel)); 850 851 rx_rbr_rings = hxgep->rx_rbr_rings; 852 if (rx_rbr_rings == NULL) { 853 HXGE_DEBUG_MSG((hxgep, RX_CTL, 854 "<== hxge_rxdma_get_ring_index: NULL ring pointer")); 855 return (-1); 856 } 857 858 ndmas = rx_rbr_rings->ndmas; 859 if (!ndmas) { 860 HXGE_DEBUG_MSG((hxgep, RX_CTL, 861 "<== hxge_rxdma_get_ring_index: no channel")); 862 return (-1); 863 } 864 865 HXGE_DEBUG_MSG((hxgep, RX_CTL, 866 "==> hxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 867 868 rbr_rings = rx_rbr_rings->rbr_rings; 869 for (i = 0; i < ndmas; i++) { 870 rdc = rbr_rings[i]->rdc; 871 if (channel == rdc) { 872 HXGE_DEBUG_MSG((hxgep, RX_CTL, 873 "==> hxge_rxdma_get_rbr_ring: " 874 "channel %d (index %d) " 875 "ring %d", channel, i, rbr_rings[i])); 876 877 return (i); 878 } 879 } 880 881 HXGE_DEBUG_MSG((hxgep, RX_CTL, 882 "<== hxge_rxdma_get_rbr_ring_index: not found")); 883 884 return (-1); 885 } 886 887 /* 888 * Static functions start here. 889 */ 890 static p_rx_msg_t 891 hxge_allocb(size_t size, uint32_t pri, p_hxge_dma_common_t dmabuf_p) 892 { 893 p_rx_msg_t hxge_mp = NULL; 894 p_hxge_dma_common_t dmamsg_p; 895 uchar_t *buffer; 896 897 hxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 898 if (hxge_mp == NULL) { 899 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 900 "Allocation of a rx msg failed.")); 901 goto hxge_allocb_exit; 902 } 903 904 hxge_mp->use_buf_pool = B_FALSE; 905 if (dmabuf_p) { 906 hxge_mp->use_buf_pool = B_TRUE; 907 908 dmamsg_p = (p_hxge_dma_common_t)&hxge_mp->buf_dma; 909 *dmamsg_p = *dmabuf_p; 910 dmamsg_p->nblocks = 1; 911 dmamsg_p->block_size = size; 912 dmamsg_p->alength = size; 913 buffer = (uchar_t *)dmabuf_p->kaddrp; 914 915 dmabuf_p->kaddrp = (void *)((char *)dmabuf_p->kaddrp + size); 916 dmabuf_p->ioaddr_pp = (void *) 917 ((char *)dmabuf_p->ioaddr_pp + size); 918 919 dmabuf_p->alength -= size; 920 dmabuf_p->offset += size; 921 dmabuf_p->dma_cookie.dmac_laddress += size; 922 dmabuf_p->dma_cookie.dmac_size -= size; 923 } else { 924 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 925 if (buffer == NULL) { 926 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 927 "Allocation of a receive page failed.")); 928 goto hxge_allocb_fail1; 929 } 930 } 931 932 hxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &hxge_mp->freeb); 933 if (hxge_mp->rx_mblk_p == NULL) { 934 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, "desballoc failed.")); 935 goto hxge_allocb_fail2; 936 } 937 hxge_mp->buffer = buffer; 938 hxge_mp->block_size = size; 939 hxge_mp->freeb.free_func = (void (*) ()) hxge_freeb; 940 hxge_mp->freeb.free_arg = (caddr_t)hxge_mp; 941 hxge_mp->ref_cnt = 1; 942 hxge_mp->free = B_TRUE; 943 hxge_mp->rx_use_bcopy = B_FALSE; 944 945 atomic_inc_32(&hxge_mblks_pending); 946 947 goto hxge_allocb_exit; 948 949 hxge_allocb_fail2: 950 if (!hxge_mp->use_buf_pool) { 951 KMEM_FREE(buffer, size); 952 } 953 hxge_allocb_fail1: 954 KMEM_FREE(hxge_mp, sizeof (rx_msg_t)); 955 hxge_mp = NULL; 956 957 hxge_allocb_exit: 958 return (hxge_mp); 959 } 960 961 p_mblk_t 962 hxge_dupb(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 963 { 964 p_mblk_t mp; 965 966 HXGE_DEBUG_MSG((NULL, MEM_CTL, "==> hxge_dupb")); 967 HXGE_DEBUG_MSG((NULL, MEM_CTL, "hxge_mp = $%p " 968 "offset = 0x%08X " "size = 0x%08X", hxge_mp, offset, size)); 969 970 mp = desballoc(&hxge_mp->buffer[offset], size, 0, &hxge_mp->freeb); 971 if (mp == NULL) { 972 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 973 goto hxge_dupb_exit; 974 } 975 976 atomic_inc_32(&hxge_mp->ref_cnt); 977 978 hxge_dupb_exit: 979 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 980 return (mp); 981 } 982 983 p_mblk_t 984 hxge_dupb_bcopy(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 985 { 986 p_mblk_t mp; 987 uchar_t *dp; 988 989 mp = allocb(size + HXGE_RXBUF_EXTRA, 0); 990 if (mp == NULL) { 991 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 992 goto hxge_dupb_bcopy_exit; 993 } 994 dp = mp->b_rptr = mp->b_rptr + HXGE_RXBUF_EXTRA; 995 bcopy((void *) &hxge_mp->buffer[offset], dp, size); 996 mp->b_wptr = dp + size; 997 998 hxge_dupb_bcopy_exit: 999 1000 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 1001 1002 return (mp); 1003 } 1004 1005 void hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, 1006 p_rx_msg_t rx_msg_p); 1007 1008 void 1009 hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1010 { 1011 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_post_page")); 1012 1013 /* Reuse this buffer */ 1014 rx_msg_p->free = B_FALSE; 1015 rx_msg_p->cur_usage_cnt = 0; 1016 rx_msg_p->max_usage_cnt = 0; 1017 rx_msg_p->pkt_buf_size = 0; 1018 1019 if (rx_rbr_p->rbr_use_bcopy) { 1020 rx_msg_p->rx_use_bcopy = B_FALSE; 1021 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1022 } 1023 atomic_dec_32(&rx_rbr_p->rbr_used); 1024 1025 /* 1026 * Get the rbr header pointer and its offset index. 1027 */ 1028 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1029 rx_rbr_p->rbr_wrap_mask); 1030 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1031 1032 /* 1033 * Accumulate some buffers in the ring before re-enabling the 1034 * DMA channel, if rbr empty was signaled. 1035 */ 1036 hpi_rxdma_rdc_rbr_kick(HXGE_DEV_HPI_HANDLE(hxgep), rx_rbr_p->rdc, 1); 1037 if (rx_rbr_p->rbr_is_empty && 1038 (rx_rbr_p->rbb_max - rx_rbr_p->rbr_used) >= 1039 HXGE_RBR_EMPTY_THRESHOLD) { 1040 hxge_rbr_empty_restore(hxgep, rx_rbr_p); 1041 } 1042 1043 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1044 "<== hxge_post_page (channel %d post_next_index %d)", 1045 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1046 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_post_page")); 1047 } 1048 1049 void 1050 hxge_freeb(p_rx_msg_t rx_msg_p) 1051 { 1052 size_t size; 1053 uchar_t *buffer = NULL; 1054 int ref_cnt; 1055 boolean_t free_state = B_FALSE; 1056 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1057 1058 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> hxge_freeb")); 1059 HXGE_DEBUG_MSG((NULL, MEM2_CTL, 1060 "hxge_freeb:rx_msg_p = $%p (block pending %d)", 1061 rx_msg_p, hxge_mblks_pending)); 1062 1063 if (ring == NULL) 1064 return; 1065 1066 /* 1067 * This is to prevent posting activities while we are recovering 1068 * from fatal errors. This should not be a performance drag since 1069 * ref_cnt != 0 most times. 1070 */ 1071 if (ring->rbr_state == RBR_POSTING) 1072 MUTEX_ENTER(&ring->post_lock); 1073 1074 /* 1075 * First we need to get the free state, then 1076 * atomic decrement the reference count to prevent 1077 * the race condition with the interrupt thread that 1078 * is processing a loaned up buffer block. 1079 */ 1080 free_state = rx_msg_p->free; 1081 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1082 if (!ref_cnt) { 1083 atomic_dec_32(&hxge_mblks_pending); 1084 1085 buffer = rx_msg_p->buffer; 1086 size = rx_msg_p->block_size; 1087 1088 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "hxge_freeb: " 1089 "will free: rx_msg_p = $%p (block pending %d)", 1090 rx_msg_p, hxge_mblks_pending)); 1091 1092 if (!rx_msg_p->use_buf_pool) { 1093 KMEM_FREE(buffer, size); 1094 } 1095 1096 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1097 /* 1098 * Decrement the receive buffer ring's reference 1099 * count, too. 1100 */ 1101 atomic_dec_32(&ring->rbr_ref_cnt); 1102 1103 /* 1104 * Free the receive buffer ring, iff 1105 * 1. all the receive buffers have been freed 1106 * 2. and we are in the proper state (that is, 1107 * we are not UNMAPPING). 1108 */ 1109 if (ring->rbr_ref_cnt == 0 && 1110 ring->rbr_state == RBR_UNMAPPED) { 1111 KMEM_FREE(ring, sizeof (*ring)); 1112 /* post_lock has been destroyed already */ 1113 return; 1114 } 1115 } 1116 1117 /* 1118 * Repost buffer. 1119 */ 1120 if (free_state && (ref_cnt == 1)) { 1121 HXGE_DEBUG_MSG((NULL, RX_CTL, 1122 "hxge_freeb: post page $%p:", rx_msg_p)); 1123 if (ring->rbr_state == RBR_POSTING) 1124 hxge_post_page(rx_msg_p->hxgep, ring, rx_msg_p); 1125 } 1126 1127 if (ring->rbr_state == RBR_POSTING) 1128 MUTEX_EXIT(&ring->post_lock); 1129 1130 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== hxge_freeb")); 1131 } 1132 1133 uint_t 1134 hxge_rx_intr(caddr_t arg1, caddr_t arg2) 1135 { 1136 p_hxge_ldv_t ldvp = (p_hxge_ldv_t)arg1; 1137 p_hxge_t hxgep = (p_hxge_t)arg2; 1138 p_hxge_ldg_t ldgp; 1139 uint8_t channel; 1140 hpi_handle_t handle; 1141 rdc_stat_t cs; 1142 uint_t serviced = DDI_INTR_UNCLAIMED; 1143 1144 if (ldvp == NULL) { 1145 HXGE_DEBUG_MSG((NULL, RX_INT_CTL, 1146 "<== hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1147 return (DDI_INTR_UNCLAIMED); 1148 } 1149 1150 if (arg2 == NULL || (void *) ldvp->hxgep != arg2) { 1151 hxgep = ldvp->hxgep; 1152 } 1153 1154 /* 1155 * If the interface is not started, just swallow the interrupt 1156 * for the logical device and don't rearm it. 1157 */ 1158 if (hxgep->hxge_mac_state != HXGE_MAC_STARTED) 1159 return (DDI_INTR_CLAIMED); 1160 1161 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1162 "==> hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1163 1164 /* 1165 * This interrupt handler is for a specific receive dma channel. 1166 */ 1167 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1168 1169 /* 1170 * Get the control and status for this channel. 1171 */ 1172 channel = ldvp->channel; 1173 ldgp = ldvp->ldgp; 1174 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value); 1175 cs.bits.ptrread = 0; 1176 cs.bits.pktread = 0; 1177 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1178 1179 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_intr:channel %d " 1180 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1181 channel, cs.value, cs.bits.rcr_to, cs.bits.rcr_thres)); 1182 1183 hxge_rx_pkts_vring(hxgep, ldvp->vdma_index, ldvp, cs); 1184 serviced = DDI_INTR_CLAIMED; 1185 1186 /* error events. */ 1187 if (cs.value & RDC_STAT_ERROR) { 1188 (void) hxge_rx_err_evnts(hxgep, ldvp->vdma_index, ldvp, cs); 1189 } 1190 1191 hxge_intr_exit: 1192 /* 1193 * Enable the mailbox update interrupt if we want to use mailbox. We 1194 * probably don't need to use mailbox as it only saves us one pio read. 1195 * Also write 1 to rcrthres and rcrto to clear these two edge triggered 1196 * bits. 1197 */ 1198 cs.value &= RDC_STAT_WR1C; 1199 cs.bits.mex = 1; 1200 cs.bits.ptrread = 0; 1201 cs.bits.pktread = 0; 1202 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1203 1204 /* 1205 * Rearm this logical group if this is a single device group. 1206 */ 1207 if (ldgp->nldvs == 1) { 1208 ld_intr_mgmt_t mgm; 1209 1210 mgm.value = 0; 1211 mgm.bits.arm = 1; 1212 mgm.bits.timer = ldgp->ldg_timer; 1213 HXGE_REG_WR32(handle, 1214 LD_INTR_MGMT + LDSV_OFFSET(ldgp->ldg), mgm.value); 1215 } 1216 1217 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1218 "<== hxge_rx_intr: serviced %d", serviced)); 1219 return (serviced); 1220 } 1221 1222 static void 1223 hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1224 rdc_stat_t cs) 1225 { 1226 p_mblk_t mp; 1227 p_rx_rcr_ring_t rcrp; 1228 1229 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts_vring")); 1230 if ((mp = hxge_rx_pkts(hxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1231 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1232 "<== hxge_rx_pkts_vring: no mp")); 1233 return; 1234 } 1235 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts_vring: $%p", mp)); 1236 1237 #ifdef HXGE_DEBUG 1238 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1239 "==> hxge_rx_pkts_vring:calling mac_rx (NEMO) " 1240 "LEN %d mp $%p mp->b_next $%p rcrp $%p", 1241 (mp->b_wptr - mp->b_rptr), mp, mp->b_next, rcrp)); 1242 1243 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1244 "==> hxge_rx_pkts_vring: dump packets " 1245 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1246 mp, mp->b_rptr, mp->b_wptr, 1247 hxge_dump_packet((char *)mp->b_rptr, 64))); 1248 1249 if (mp->b_cont) { 1250 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1251 "==> hxge_rx_pkts_vring: dump b_cont packets " 1252 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1253 mp->b_cont, mp->b_cont->b_rptr, mp->b_cont->b_wptr, 1254 hxge_dump_packet((char *)mp->b_cont->b_rptr, 1255 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1256 } 1257 if (mp->b_next) { 1258 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1259 "==> hxge_rx_pkts_vring: dump next packets " 1260 "(b_rptr $%p): %s", 1261 mp->b_next->b_rptr, 1262 hxge_dump_packet((char *)mp->b_next->b_rptr, 64))); 1263 } 1264 #endif 1265 1266 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1267 "==> hxge_rx_pkts_vring: send packet to stack")); 1268 mac_rx(hxgep->mach, NULL, mp); 1269 1270 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_pkts_vring")); 1271 } 1272 1273 /*ARGSUSED*/ 1274 mblk_t * 1275 hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1276 p_rx_rcr_ring_t *rcrp, rdc_stat_t cs) 1277 { 1278 hpi_handle_t handle; 1279 uint8_t channel; 1280 p_rx_rcr_rings_t rx_rcr_rings; 1281 p_rx_rcr_ring_t rcr_p; 1282 uint32_t comp_rd_index; 1283 p_rcr_entry_t rcr_desc_rd_head_p; 1284 p_rcr_entry_t rcr_desc_rd_head_pp; 1285 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1286 uint16_t qlen, nrcr_read, npkt_read; 1287 uint32_t qlen_hw, qlen_sw, num_rcrs; 1288 uint32_t invalid_rcr_entry; 1289 boolean_t multi; 1290 rdc_rcr_cfg_b_t rcr_cfg_b; 1291 uint64_t rcr_head_index, rcr_tail_index; 1292 uint64_t rcr_tail; 1293 rdc_rcr_tail_t rcr_tail_reg; 1294 p_hxge_rx_ring_stats_t rdc_stats; 1295 1296 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:vindex %d " 1297 "channel %d", vindex, ldvp->channel)); 1298 1299 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 1300 return (NULL); 1301 } 1302 1303 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1304 rx_rcr_rings = hxgep->rx_rcr_rings; 1305 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1306 channel = rcr_p->rdc; 1307 if (channel != ldvp->channel) { 1308 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:index %d " 1309 "channel %d, and rcr channel %d not matched.", 1310 vindex, ldvp->channel, channel)); 1311 return (NULL); 1312 } 1313 1314 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1315 "==> hxge_rx_pkts: START: rcr channel %d " 1316 "head_p $%p head_pp $%p index %d ", 1317 channel, rcr_p->rcr_desc_rd_head_p, 1318 rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1319 1320 (void) hpi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1321 RXDMA_REG_READ64(handle, RDC_RCR_TAIL, channel, &rcr_tail_reg.value); 1322 rcr_tail = rcr_tail_reg.bits.tail; 1323 1324 if (!qlen) { 1325 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1326 "<== hxge_rx_pkts:rcr channel %d qlen %d (no pkts)", 1327 channel, qlen)); 1328 return (NULL); 1329 } 1330 1331 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts:rcr channel %d " 1332 "qlen %d", channel, qlen)); 1333 1334 comp_rd_index = rcr_p->comp_rd_index; 1335 1336 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1337 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1338 nrcr_read = npkt_read = 0; 1339 1340 if (hxgep->rdc_first_intr[channel]) 1341 qlen_hw = qlen; 1342 else 1343 qlen_hw = qlen - 1; 1344 1345 head_mp = NULL; 1346 tail_mp = &head_mp; 1347 nmp = mp_cont = NULL; 1348 multi = B_FALSE; 1349 1350 rcr_head_index = rcr_p->rcr_desc_rd_head_p - rcr_p->rcr_desc_first_p; 1351 rcr_tail_index = rcr_tail - rcr_p->rcr_tail_begin; 1352 1353 if (rcr_tail_index >= rcr_head_index) { 1354 num_rcrs = rcr_tail_index - rcr_head_index; 1355 } else { 1356 /* rcr_tail has wrapped around */ 1357 num_rcrs = (rcr_p->comp_size - rcr_head_index) + rcr_tail_index; 1358 } 1359 1360 qlen_sw = hxge_scan_for_last_eop(rcr_p, rcr_desc_rd_head_p, num_rcrs); 1361 if (!qlen_sw) 1362 return (NULL); 1363 1364 if (qlen_hw > qlen_sw) { 1365 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1366 "Channel %d, rcr_qlen from reg %d and from rcr_tail %d\n", 1367 channel, qlen_hw, qlen_sw)); 1368 qlen_hw = qlen_sw; 1369 } 1370 1371 while (qlen_hw) { 1372 #ifdef HXGE_DEBUG 1373 hxge_dump_rcr_entry(hxgep, rcr_desc_rd_head_p); 1374 #endif 1375 /* 1376 * Process one completion ring entry. 1377 */ 1378 invalid_rcr_entry = 0; 1379 hxge_receive_packet(hxgep, 1380 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont, 1381 &invalid_rcr_entry); 1382 if (invalid_rcr_entry != 0) { 1383 rdc_stats = rcr_p->rdc_stats; 1384 rdc_stats->rcr_invalids++; 1385 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1386 "Channel %d could only read 0x%x packets, " 1387 "but 0x%x pending\n", channel, npkt_read, qlen_hw)); 1388 break; 1389 } 1390 1391 /* 1392 * message chaining modes (nemo msg chaining) 1393 */ 1394 if (nmp) { 1395 nmp->b_next = NULL; 1396 if (!multi && !mp_cont) { /* frame fits a partition */ 1397 *tail_mp = nmp; 1398 tail_mp = &nmp->b_next; 1399 nmp = NULL; 1400 } else if (multi && !mp_cont) { /* first segment */ 1401 *tail_mp = nmp; 1402 tail_mp = &nmp->b_cont; 1403 } else if (multi && mp_cont) { /* mid of multi segs */ 1404 *tail_mp = mp_cont; 1405 tail_mp = &mp_cont->b_cont; 1406 } else if (!multi && mp_cont) { /* last segment */ 1407 *tail_mp = mp_cont; 1408 tail_mp = &nmp->b_next; 1409 nmp = NULL; 1410 } 1411 } 1412 1413 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1414 "==> hxge_rx_pkts: loop: rcr channel %d " 1415 "before updating: multi %d " 1416 "nrcr_read %d " 1417 "npk read %d " 1418 "head_pp $%p index %d ", 1419 channel, multi, 1420 nrcr_read, npkt_read, rcr_desc_rd_head_pp, comp_rd_index)); 1421 1422 if (!multi) { 1423 qlen_hw--; 1424 npkt_read++; 1425 } 1426 1427 /* 1428 * Update the next read entry. 1429 */ 1430 comp_rd_index = NEXT_ENTRY(comp_rd_index, 1431 rcr_p->comp_wrap_mask); 1432 1433 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1434 rcr_p->rcr_desc_first_p, rcr_p->rcr_desc_last_p); 1435 1436 nrcr_read++; 1437 1438 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1439 "<== hxge_rx_pkts: (SAM, process one packet) " 1440 "nrcr_read %d", nrcr_read)); 1441 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1442 "==> hxge_rx_pkts: loop: rcr channel %d " 1443 "multi %d nrcr_read %d npk read %d head_pp $%p index %d ", 1444 channel, multi, nrcr_read, npkt_read, rcr_desc_rd_head_pp, 1445 comp_rd_index)); 1446 } 1447 1448 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 1449 rcr_p->comp_rd_index = comp_rd_index; 1450 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 1451 1452 if ((hxgep->intr_timeout != rcr_p->intr_timeout) || 1453 (hxgep->intr_threshold != rcr_p->intr_threshold)) { 1454 rcr_p->intr_timeout = hxgep->intr_timeout; 1455 rcr_p->intr_threshold = hxgep->intr_threshold; 1456 rcr_cfg_b.value = 0x0ULL; 1457 if (rcr_p->intr_timeout) 1458 rcr_cfg_b.bits.entout = 1; 1459 rcr_cfg_b.bits.timeout = rcr_p->intr_timeout; 1460 rcr_cfg_b.bits.pthres = rcr_p->intr_threshold; 1461 RXDMA_REG_WRITE64(handle, RDC_RCR_CFG_B, 1462 channel, rcr_cfg_b.value); 1463 } 1464 1465 if (hxgep->rdc_first_intr[channel] && (npkt_read > 0)) { 1466 hxgep->rdc_first_intr[channel] = B_FALSE; 1467 cs.bits.pktread = npkt_read - 1; 1468 } else 1469 cs.bits.pktread = npkt_read; 1470 cs.bits.ptrread = nrcr_read; 1471 cs.value &= 0xffffffffULL; 1472 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1473 1474 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1475 "==> hxge_rx_pkts: EXIT: rcr channel %d " 1476 "head_pp $%p index %016llx ", 1477 channel, rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1478 1479 /* 1480 * Update RCR buffer pointer read and number of packets read. 1481 */ 1482 *rcrp = rcr_p; 1483 1484 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "<== hxge_rx_pkts")); 1485 1486 return (head_mp); 1487 } 1488 1489 #define RCR_ENTRY_PATTERN 0x5a5a6b6b7c7c8d8dULL 1490 #define NO_PORT_BIT 0x20 1491 #define L4_CS_EQ_BIT 0x40 1492 1493 static uint32_t hxge_scan_for_last_eop(p_rx_rcr_ring_t rcr_p, 1494 p_rcr_entry_t rcr_desc_rd_head_p, uint32_t num_rcrs) 1495 { 1496 uint64_t rcr_entry; 1497 uint32_t rcrs = 0; 1498 uint32_t pkts = 0; 1499 1500 while (rcrs++ < num_rcrs) { 1501 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 1502 1503 if ((rcr_entry == 0x0) || (rcr_entry == RCR_ENTRY_PATTERN)) 1504 break; 1505 1506 if (!(rcr_entry & RCR_MULTI_MASK)) 1507 pkts++; 1508 1509 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1510 rcr_p->rcr_desc_first_p, rcr_p->rcr_desc_last_p); 1511 } 1512 1513 return (pkts); 1514 } 1515 1516 /*ARGSUSED*/ 1517 void 1518 hxge_receive_packet(p_hxge_t hxgep, 1519 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 1520 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont, 1521 uint32_t *invalid_rcr_entry) 1522 { 1523 p_mblk_t nmp = NULL; 1524 uint64_t multi; 1525 uint8_t channel; 1526 1527 boolean_t first_entry = B_TRUE; 1528 boolean_t is_tcp_udp = B_FALSE; 1529 boolean_t buffer_free = B_FALSE; 1530 boolean_t error_send_up = B_FALSE; 1531 uint8_t error_type; 1532 uint16_t l2_len; 1533 uint16_t skip_len; 1534 uint8_t pktbufsz_type; 1535 uint64_t rcr_entry; 1536 uint64_t *pkt_buf_addr_pp; 1537 uint64_t *pkt_buf_addr_p; 1538 uint32_t buf_offset; 1539 uint32_t bsize; 1540 uint32_t msg_index; 1541 p_rx_rbr_ring_t rx_rbr_p; 1542 p_rx_msg_t *rx_msg_ring_p; 1543 p_rx_msg_t rx_msg_p; 1544 1545 uint16_t sw_offset_bytes = 0, hdr_size = 0; 1546 hxge_status_t status = HXGE_OK; 1547 boolean_t is_valid = B_FALSE; 1548 p_hxge_rx_ring_stats_t rdc_stats; 1549 uint32_t bytes_read; 1550 uint8_t header0 = 0; 1551 uint8_t header1 = 0; 1552 uint64_t pkt_type; 1553 uint8_t no_port_bit = 0; 1554 uint8_t l4_cs_eq_bit = 0; 1555 1556 channel = rcr_p->rdc; 1557 1558 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_receive_packet")); 1559 1560 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 1561 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 1562 1563 /* Verify the content of the rcr_entry for a hardware bug workaround */ 1564 if ((rcr_entry == 0x0) || (rcr_entry == RCR_ENTRY_PATTERN)) { 1565 *invalid_rcr_entry = 1; 1566 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "hxge_receive_packet " 1567 "Channel %d invalid RCR entry 0x%llx found, returning\n", 1568 channel, (long long) rcr_entry)); 1569 return; 1570 } 1571 *((uint64_t *)rcr_desc_rd_head_p) = RCR_ENTRY_PATTERN; 1572 1573 multi = (rcr_entry & RCR_MULTI_MASK); 1574 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 1575 1576 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 1577 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 1578 1579 /* 1580 * Hardware does not strip the CRC due bug ID 11451 where 1581 * the hardware mis handles minimum size packets. 1582 */ 1583 l2_len -= ETHERFCSL; 1584 1585 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 1586 RCR_PKTBUFSZ_SHIFT); 1587 #if defined(__i386) 1588 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 1589 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 1590 #else 1591 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 1592 RCR_PKT_BUF_ADDR_SHIFT); 1593 #endif 1594 1595 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1596 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1597 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1598 "error_type 0x%x pktbufsz_type %d ", 1599 rcr_desc_rd_head_p, rcr_entry, pkt_buf_addr_pp, l2_len, 1600 multi, error_type, pktbufsz_type)); 1601 1602 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1603 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1604 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1605 "error_type 0x%x ", rcr_desc_rd_head_p, 1606 rcr_entry, pkt_buf_addr_pp, l2_len, multi, error_type)); 1607 1608 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1609 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1610 "full pkt_buf_addr_pp $%p l2_len %d", 1611 rcr_entry, pkt_buf_addr_pp, l2_len)); 1612 1613 /* get the stats ptr */ 1614 rdc_stats = rcr_p->rdc_stats; 1615 1616 if (!l2_len) { 1617 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1618 "<== hxge_receive_packet: failed: l2 length is 0.")); 1619 return; 1620 } 1621 1622 /* shift 6 bits to get the full io address */ 1623 #if defined(__i386) 1624 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 1625 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1626 #else 1627 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 1628 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1629 #endif 1630 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1631 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1632 "full pkt_buf_addr_pp $%p l2_len %d", 1633 rcr_entry, pkt_buf_addr_pp, l2_len)); 1634 1635 rx_rbr_p = rcr_p->rx_rbr_p; 1636 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 1637 1638 if (first_entry) { 1639 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 1640 RXDMA_HDR_SIZE_DEFAULT); 1641 1642 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1643 "==> hxge_receive_packet: first entry 0x%016llx " 1644 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 1645 rcr_entry, pkt_buf_addr_pp, l2_len, hdr_size)); 1646 } 1647 1648 MUTEX_ENTER(&rcr_p->lock); 1649 MUTEX_ENTER(&rx_rbr_p->lock); 1650 1651 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1652 "==> (rbr 1) hxge_receive_packet: entry 0x%0llx " 1653 "full pkt_buf_addr_pp $%p l2_len %d", 1654 rcr_entry, pkt_buf_addr_pp, l2_len)); 1655 1656 /* 1657 * Packet buffer address in the completion entry points to the starting 1658 * buffer address (offset 0). Use the starting buffer address to locate 1659 * the corresponding kernel address. 1660 */ 1661 status = hxge_rxbuf_pp_to_vp(hxgep, rx_rbr_p, 1662 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 1663 &buf_offset, &msg_index); 1664 1665 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1666 "==> (rbr 2) hxge_receive_packet: entry 0x%0llx " 1667 "full pkt_buf_addr_pp $%p l2_len %d", 1668 rcr_entry, pkt_buf_addr_pp, l2_len)); 1669 1670 if (status != HXGE_OK) { 1671 MUTEX_EXIT(&rx_rbr_p->lock); 1672 MUTEX_EXIT(&rcr_p->lock); 1673 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1674 "<== hxge_receive_packet: found vaddr failed %d", status)); 1675 return; 1676 } 1677 1678 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1679 "==> (rbr 3) hxge_receive_packet: entry 0x%0llx " 1680 "full pkt_buf_addr_pp $%p l2_len %d", 1681 rcr_entry, pkt_buf_addr_pp, l2_len)); 1682 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1683 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1684 "full pkt_buf_addr_pp $%p l2_len %d", 1685 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1686 1687 if (msg_index >= rx_rbr_p->tnblocks) { 1688 MUTEX_EXIT(&rx_rbr_p->lock); 1689 MUTEX_EXIT(&rcr_p->lock); 1690 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1691 "==> hxge_receive_packet: FATAL msg_index (%d) " 1692 "should be smaller than tnblocks (%d)\n", 1693 msg_index, rx_rbr_p->tnblocks)); 1694 return; 1695 } 1696 1697 rx_msg_p = rx_msg_ring_p[msg_index]; 1698 1699 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1700 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1701 "full pkt_buf_addr_pp $%p l2_len %d", 1702 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1703 1704 switch (pktbufsz_type) { 1705 case RCR_PKTBUFSZ_0: 1706 bsize = rx_rbr_p->pkt_buf_size0_bytes; 1707 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1708 "==> hxge_receive_packet: 0 buf %d", bsize)); 1709 break; 1710 case RCR_PKTBUFSZ_1: 1711 bsize = rx_rbr_p->pkt_buf_size1_bytes; 1712 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1713 "==> hxge_receive_packet: 1 buf %d", bsize)); 1714 break; 1715 case RCR_PKTBUFSZ_2: 1716 bsize = rx_rbr_p->pkt_buf_size2_bytes; 1717 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1718 "==> hxge_receive_packet: 2 buf %d", bsize)); 1719 break; 1720 case RCR_SINGLE_BLOCK: 1721 bsize = rx_msg_p->block_size; 1722 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1723 "==> hxge_receive_packet: single %d", bsize)); 1724 1725 break; 1726 default: 1727 MUTEX_EXIT(&rx_rbr_p->lock); 1728 MUTEX_EXIT(&rcr_p->lock); 1729 return; 1730 } 1731 1732 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 1733 (buf_offset + sw_offset_bytes), (hdr_size + l2_len), 1734 DDI_DMA_SYNC_FORCPU); 1735 1736 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1737 "==> hxge_receive_packet: after first dump:usage count")); 1738 1739 if (rx_msg_p->cur_usage_cnt == 0) { 1740 atomic_inc_32(&rx_rbr_p->rbr_used); 1741 if (rx_rbr_p->rbr_use_bcopy) { 1742 atomic_inc_32(&rx_rbr_p->rbr_consumed); 1743 if (rx_rbr_p->rbr_consumed < 1744 rx_rbr_p->rbr_threshold_hi) { 1745 if (rx_rbr_p->rbr_threshold_lo == 0 || 1746 ((rx_rbr_p->rbr_consumed >= 1747 rx_rbr_p->rbr_threshold_lo) && 1748 (rx_rbr_p->rbr_bufsize_type >= 1749 pktbufsz_type))) { 1750 rx_msg_p->rx_use_bcopy = B_TRUE; 1751 } 1752 } else { 1753 rx_msg_p->rx_use_bcopy = B_TRUE; 1754 } 1755 } 1756 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1757 "==> hxge_receive_packet: buf %d (new block) ", bsize)); 1758 1759 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 1760 rx_msg_p->pkt_buf_size = bsize; 1761 rx_msg_p->cur_usage_cnt = 1; 1762 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 1763 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1764 "==> hxge_receive_packet: buf %d (single block) ", 1765 bsize)); 1766 /* 1767 * Buffer can be reused once the free function is 1768 * called. 1769 */ 1770 rx_msg_p->max_usage_cnt = 1; 1771 buffer_free = B_TRUE; 1772 } else { 1773 rx_msg_p->max_usage_cnt = rx_msg_p->block_size / bsize; 1774 if (rx_msg_p->max_usage_cnt == 1) { 1775 buffer_free = B_TRUE; 1776 } 1777 } 1778 } else { 1779 rx_msg_p->cur_usage_cnt++; 1780 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 1781 buffer_free = B_TRUE; 1782 } 1783 } 1784 1785 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1786 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 1787 msg_index, l2_len, 1788 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 1789 1790 if (error_type) { 1791 rdc_stats->ierrors++; 1792 /* Update error stats */ 1793 rdc_stats->errlog.compl_err_type = error_type; 1794 HXGE_FM_REPORT_ERROR(hxgep, NULL, HXGE_FM_EREPORT_RDMC_RCR_ERR); 1795 1796 if (error_type & RCR_CTRL_FIFO_DED) { 1797 rdc_stats->ctrl_fifo_ecc_err++; 1798 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1799 " hxge_receive_packet: " 1800 " channel %d RCR ctrl_fifo_ded error", channel)); 1801 } else if (error_type & RCR_DATA_FIFO_DED) { 1802 rdc_stats->data_fifo_ecc_err++; 1803 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1804 " hxge_receive_packet: channel %d" 1805 " RCR data_fifo_ded error", channel)); 1806 } 1807 1808 /* 1809 * Update and repost buffer block if max usage count is 1810 * reached. 1811 */ 1812 if (error_send_up == B_FALSE) { 1813 atomic_inc_32(&rx_msg_p->ref_cnt); 1814 if (buffer_free == B_TRUE) { 1815 rx_msg_p->free = B_TRUE; 1816 } 1817 1818 MUTEX_EXIT(&rx_rbr_p->lock); 1819 MUTEX_EXIT(&rcr_p->lock); 1820 hxge_freeb(rx_msg_p); 1821 return; 1822 } 1823 } 1824 1825 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1826 "==> hxge_receive_packet: DMA sync second ")); 1827 1828 bytes_read = rcr_p->rcvd_pkt_bytes; 1829 skip_len = sw_offset_bytes + hdr_size; 1830 1831 if (first_entry) { 1832 header0 = rx_msg_p->buffer[buf_offset]; 1833 no_port_bit = header0 & NO_PORT_BIT; 1834 1835 header1 = rx_msg_p->buffer[buf_offset + 1]; 1836 l4_cs_eq_bit = header1 & L4_CS_EQ_BIT; 1837 } 1838 1839 if (!rx_msg_p->rx_use_bcopy) { 1840 /* 1841 * For loaned up buffers, the driver reference count 1842 * will be incremented first and then the free state. 1843 */ 1844 if ((nmp = hxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 1845 if (first_entry) { 1846 nmp->b_rptr = &nmp->b_rptr[skip_len]; 1847 if (l2_len < bsize - skip_len) { 1848 nmp->b_wptr = &nmp->b_rptr[l2_len]; 1849 } else { 1850 nmp->b_wptr = &nmp->b_rptr[bsize 1851 - skip_len]; 1852 } 1853 } else { 1854 if (l2_len - bytes_read < bsize) { 1855 nmp->b_wptr = 1856 &nmp->b_rptr[l2_len - bytes_read]; 1857 } else { 1858 nmp->b_wptr = &nmp->b_rptr[bsize]; 1859 } 1860 } 1861 } 1862 } else { 1863 if (first_entry) { 1864 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 1865 l2_len < bsize - skip_len ? 1866 l2_len : bsize - skip_len); 1867 } else { 1868 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset, 1869 l2_len - bytes_read < bsize ? 1870 l2_len - bytes_read : bsize); 1871 } 1872 } 1873 1874 if (nmp != NULL) { 1875 if (first_entry) 1876 bytes_read = nmp->b_wptr - nmp->b_rptr; 1877 else 1878 bytes_read += nmp->b_wptr - nmp->b_rptr; 1879 1880 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1881 "==> hxge_receive_packet after dupb: " 1882 "rbr consumed %d " 1883 "pktbufsz_type %d " 1884 "nmp $%p rptr $%p wptr $%p " 1885 "buf_offset %d bzise %d l2_len %d skip_len %d", 1886 rx_rbr_p->rbr_consumed, 1887 pktbufsz_type, 1888 nmp, nmp->b_rptr, nmp->b_wptr, 1889 buf_offset, bsize, l2_len, skip_len)); 1890 } else { 1891 cmn_err(CE_WARN, "!hxge_receive_packet: update stats (error)"); 1892 1893 atomic_inc_32(&rx_msg_p->ref_cnt); 1894 if (buffer_free == B_TRUE) { 1895 rx_msg_p->free = B_TRUE; 1896 } 1897 1898 MUTEX_EXIT(&rx_rbr_p->lock); 1899 MUTEX_EXIT(&rcr_p->lock); 1900 hxge_freeb(rx_msg_p); 1901 return; 1902 } 1903 1904 if (buffer_free == B_TRUE) { 1905 rx_msg_p->free = B_TRUE; 1906 } 1907 1908 /* 1909 * ERROR, FRAG and PKT_TYPE are only reported in the first entry. If a 1910 * packet is not fragmented and no error bit is set, then L4 checksum 1911 * is OK. 1912 */ 1913 is_valid = (nmp != NULL); 1914 if (first_entry) { 1915 rdc_stats->ipackets++; /* count only 1st seg for jumbo */ 1916 if (l2_len > (STD_FRAME_SIZE - ETHERFCSL)) 1917 rdc_stats->jumbo_pkts++; 1918 rdc_stats->ibytes += skip_len + l2_len < bsize ? 1919 l2_len : bsize; 1920 } else { 1921 /* 1922 * Add the current portion of the packet to the kstats. 1923 * The current portion of the packet is calculated by using 1924 * length of the packet and the previously received portion. 1925 */ 1926 rdc_stats->ibytes += l2_len - rcr_p->rcvd_pkt_bytes < bsize ? 1927 l2_len - rcr_p->rcvd_pkt_bytes : bsize; 1928 } 1929 1930 rcr_p->rcvd_pkt_bytes = bytes_read; 1931 1932 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 1933 atomic_inc_32(&rx_msg_p->ref_cnt); 1934 MUTEX_EXIT(&rx_rbr_p->lock); 1935 MUTEX_EXIT(&rcr_p->lock); 1936 hxge_freeb(rx_msg_p); 1937 } else { 1938 MUTEX_EXIT(&rx_rbr_p->lock); 1939 MUTEX_EXIT(&rcr_p->lock); 1940 } 1941 1942 if (is_valid) { 1943 nmp->b_cont = NULL; 1944 if (first_entry) { 1945 *mp = nmp; 1946 *mp_cont = NULL; 1947 } else { 1948 *mp_cont = nmp; 1949 } 1950 } 1951 1952 /* 1953 * Update stats and hardware checksuming. 1954 */ 1955 if (is_valid && !multi) { 1956 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 1957 pkt_type == RCR_PKT_IS_UDP) ? B_TRUE : B_FALSE); 1958 1959 if (!no_port_bit && l4_cs_eq_bit && is_tcp_udp && !error_type) { 1960 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 1961 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 1962 1963 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1964 "==> hxge_receive_packet: Full tcp/udp cksum " 1965 "is_valid 0x%x multi %d error %d", 1966 is_valid, multi, error_type)); 1967 } 1968 } 1969 1970 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1971 "==> hxge_receive_packet: *mp 0x%016llx", *mp)); 1972 1973 *multi_p = (multi == RCR_MULTI_MASK); 1974 1975 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_receive_packet: " 1976 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 1977 *multi_p, nmp, *mp, *mp_cont)); 1978 } 1979 1980 static void 1981 hxge_rx_rbr_empty_recover(p_hxge_t hxgep, uint8_t channel) 1982 { 1983 hpi_handle_t handle; 1984 p_rx_rcr_ring_t rcrp; 1985 p_rx_rbr_ring_t rbrp; 1986 1987 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel]; 1988 rbrp = rcrp->rx_rbr_p; 1989 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1990 1991 /* 1992 * Wait for the channel to be quiet 1993 */ 1994 (void) hpi_rxdma_cfg_rdc_wait_for_qst(handle, channel); 1995 1996 /* 1997 * Post page will accumulate some buffers before re-enabling 1998 * the DMA channel. 1999 */ 2000 2001 MUTEX_ENTER(&rbrp->post_lock); 2002 if ((rbrp->rbb_max - rbrp->rbr_used) >= HXGE_RBR_EMPTY_THRESHOLD) { 2003 hxge_rbr_empty_restore(hxgep, rbrp); 2004 } else { 2005 rbrp->rbr_is_empty = B_TRUE; 2006 } 2007 MUTEX_EXIT(&rbrp->post_lock); 2008 } 2009 2010 /*ARGSUSED*/ 2011 static hxge_status_t 2012 hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, p_hxge_ldv_t ldvp, 2013 rdc_stat_t cs) 2014 { 2015 p_hxge_rx_ring_stats_t rdc_stats; 2016 hpi_handle_t handle; 2017 boolean_t rxchan_fatal = B_FALSE; 2018 uint8_t channel; 2019 hxge_status_t status = HXGE_OK; 2020 uint64_t cs_val; 2021 2022 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_rx_err_evnts")); 2023 2024 handle = HXGE_DEV_HPI_HANDLE(hxgep); 2025 channel = ldvp->channel; 2026 2027 /* Clear the interrupts */ 2028 cs.bits.pktread = 0; 2029 cs.bits.ptrread = 0; 2030 cs_val = cs.value & RDC_STAT_WR1C; 2031 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs_val); 2032 2033 rdc_stats = &hxgep->statsp->rdc_stats[ldvp->vdma_index]; 2034 2035 if (cs.bits.rbr_cpl_to) { 2036 rdc_stats->rbr_tmout++; 2037 HXGE_FM_REPORT_ERROR(hxgep, channel, 2038 HXGE_FM_EREPORT_RDMC_RBR_CPL_TO); 2039 rxchan_fatal = B_TRUE; 2040 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2041 "==> hxge_rx_err_evnts(channel %d): " 2042 "fatal error: rx_rbr_timeout", channel)); 2043 } 2044 2045 if ((cs.bits.rcr_shadow_par_err) || (cs.bits.rbr_prefetch_par_err)) { 2046 (void) hpi_rxdma_ring_perr_stat_get(handle, 2047 &rdc_stats->errlog.pre_par, &rdc_stats->errlog.sha_par); 2048 } 2049 2050 if (cs.bits.rcr_shadow_par_err) { 2051 rdc_stats->rcr_sha_par++; 2052 HXGE_FM_REPORT_ERROR(hxgep, channel, 2053 HXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2054 rxchan_fatal = B_TRUE; 2055 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2056 "==> hxge_rx_err_evnts(channel %d): " 2057 "fatal error: rcr_shadow_par_err", channel)); 2058 } 2059 2060 if (cs.bits.rbr_prefetch_par_err) { 2061 rdc_stats->rbr_pre_par++; 2062 HXGE_FM_REPORT_ERROR(hxgep, channel, 2063 HXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2064 rxchan_fatal = B_TRUE; 2065 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2066 "==> hxge_rx_err_evnts(channel %d): " 2067 "fatal error: rbr_prefetch_par_err", channel)); 2068 } 2069 2070 if (cs.bits.rbr_pre_empty) { 2071 rdc_stats->rbr_pre_empty++; 2072 HXGE_FM_REPORT_ERROR(hxgep, channel, 2073 HXGE_FM_EREPORT_RDMC_RBR_PRE_EMPTY); 2074 rxchan_fatal = B_TRUE; 2075 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2076 "==> hxge_rx_err_evnts(channel %d): " 2077 "fatal error: rbr_pre_empty", channel)); 2078 } 2079 2080 if (cs.bits.peu_resp_err) { 2081 rdc_stats->peu_resp_err++; 2082 HXGE_FM_REPORT_ERROR(hxgep, channel, 2083 HXGE_FM_EREPORT_RDMC_PEU_RESP_ERR); 2084 rxchan_fatal = B_TRUE; 2085 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2086 "==> hxge_rx_err_evnts(channel %d): " 2087 "fatal error: peu_resp_err", channel)); 2088 } 2089 2090 if (cs.bits.rcr_thres) { 2091 rdc_stats->rcr_thres++; 2092 } 2093 2094 if (cs.bits.rcr_to) { 2095 rdc_stats->rcr_to++; 2096 } 2097 2098 if (cs.bits.rcr_shadow_full) { 2099 rdc_stats->rcr_shadow_full++; 2100 HXGE_FM_REPORT_ERROR(hxgep, channel, 2101 HXGE_FM_EREPORT_RDMC_RCR_SHA_FULL); 2102 rxchan_fatal = B_TRUE; 2103 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2104 "==> hxge_rx_err_evnts(channel %d): " 2105 "fatal error: rcr_shadow_full", channel)); 2106 } 2107 2108 if (cs.bits.rcr_full) { 2109 rdc_stats->rcrfull++; 2110 HXGE_FM_REPORT_ERROR(hxgep, channel, 2111 HXGE_FM_EREPORT_RDMC_RCRFULL); 2112 rxchan_fatal = B_TRUE; 2113 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2114 "==> hxge_rx_err_evnts(channel %d): " 2115 "fatal error: rcrfull error", channel)); 2116 } 2117 2118 if (cs.bits.rbr_empty) { 2119 rdc_stats->rbr_empty++; 2120 hxge_rx_rbr_empty_recover(hxgep, channel); 2121 } 2122 2123 if (cs.bits.rbr_full) { 2124 rdc_stats->rbrfull++; 2125 HXGE_FM_REPORT_ERROR(hxgep, channel, 2126 HXGE_FM_EREPORT_RDMC_RBRFULL); 2127 rxchan_fatal = B_TRUE; 2128 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2129 "==> hxge_rx_err_evnts(channel %d): " 2130 "fatal error: rbr_full error", channel)); 2131 } 2132 2133 if (rxchan_fatal) { 2134 p_rx_rcr_ring_t rcrp; 2135 p_rx_rbr_ring_t rbrp; 2136 2137 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel]; 2138 rbrp = rcrp->rx_rbr_p; 2139 2140 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2141 " hxge_rx_err_evnts: fatal error on Channel #%d\n", 2142 channel)); 2143 MUTEX_ENTER(&rbrp->post_lock); 2144 /* This function needs to be inside the post_lock */ 2145 status = hxge_rxdma_fatal_err_recover(hxgep, channel); 2146 MUTEX_EXIT(&rbrp->post_lock); 2147 if (status == HXGE_OK) { 2148 FM_SERVICE_RESTORED(hxgep); 2149 } 2150 } 2151 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_rx_err_evnts")); 2152 2153 return (status); 2154 } 2155 2156 static hxge_status_t 2157 hxge_map_rxdma(p_hxge_t hxgep) 2158 { 2159 int i, ndmas; 2160 uint16_t channel; 2161 p_rx_rbr_rings_t rx_rbr_rings; 2162 p_rx_rbr_ring_t *rbr_rings; 2163 p_rx_rcr_rings_t rx_rcr_rings; 2164 p_rx_rcr_ring_t *rcr_rings; 2165 p_rx_mbox_areas_t rx_mbox_areas_p; 2166 p_rx_mbox_t *rx_mbox_p; 2167 p_hxge_dma_pool_t dma_buf_poolp; 2168 p_hxge_dma_common_t *dma_buf_p; 2169 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2170 p_hxge_dma_common_t *dma_rbr_cntl_p; 2171 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2172 p_hxge_dma_common_t *dma_rcr_cntl_p; 2173 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2174 p_hxge_dma_common_t *dma_mbox_cntl_p; 2175 uint32_t *num_chunks; 2176 hxge_status_t status = HXGE_OK; 2177 2178 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_map_rxdma")); 2179 2180 dma_buf_poolp = hxgep->rx_buf_pool_p; 2181 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2182 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2183 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2184 2185 if (!dma_buf_poolp->buf_allocated || 2186 !dma_rbr_cntl_poolp->buf_allocated || 2187 !dma_rcr_cntl_poolp->buf_allocated || 2188 !dma_mbox_cntl_poolp->buf_allocated) { 2189 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2190 "<== hxge_map_rxdma: buf not allocated")); 2191 return (HXGE_ERROR); 2192 } 2193 2194 ndmas = dma_buf_poolp->ndmas; 2195 if (!ndmas) { 2196 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2197 "<== hxge_map_rxdma: no dma allocated")); 2198 return (HXGE_ERROR); 2199 } 2200 2201 num_chunks = dma_buf_poolp->num_chunks; 2202 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2203 dma_rbr_cntl_p = dma_rbr_cntl_poolp->dma_buf_pool_p; 2204 dma_rcr_cntl_p = dma_rcr_cntl_poolp->dma_buf_pool_p; 2205 dma_mbox_cntl_p = dma_mbox_cntl_poolp->dma_buf_pool_p; 2206 2207 rx_rbr_rings = (p_rx_rbr_rings_t) 2208 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2209 rbr_rings = (p_rx_rbr_ring_t *)KMEM_ZALLOC( 2210 sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2211 2212 rx_rcr_rings = (p_rx_rcr_rings_t) 2213 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2214 rcr_rings = (p_rx_rcr_ring_t *)KMEM_ZALLOC( 2215 sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2216 2217 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2218 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2219 rx_mbox_p = (p_rx_mbox_t *)KMEM_ZALLOC( 2220 sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2221 2222 /* 2223 * Timeout should be set based on the system clock divider. 2224 * The following timeout value of 1 assumes that the 2225 * granularity (1000) is 3 microseconds running at 300MHz. 2226 */ 2227 2228 hxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2229 hxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2230 2231 /* 2232 * Map descriptors from the buffer polls for each dam channel. 2233 */ 2234 for (i = 0; i < ndmas; i++) { 2235 /* 2236 * Set up and prepare buffer blocks, descriptors and mailbox. 2237 */ 2238 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2239 status = hxge_map_rxdma_channel(hxgep, channel, 2240 (p_hxge_dma_common_t *)&dma_buf_p[i], 2241 (p_rx_rbr_ring_t *)&rbr_rings[i], 2242 num_chunks[i], 2243 (p_hxge_dma_common_t *)&dma_rbr_cntl_p[i], 2244 (p_hxge_dma_common_t *)&dma_rcr_cntl_p[i], 2245 (p_hxge_dma_common_t *)&dma_mbox_cntl_p[i], 2246 (p_rx_rcr_ring_t *)&rcr_rings[i], 2247 (p_rx_mbox_t *)&rx_mbox_p[i]); 2248 if (status != HXGE_OK) { 2249 goto hxge_map_rxdma_fail1; 2250 } 2251 rbr_rings[i]->index = (uint16_t)i; 2252 rcr_rings[i]->index = (uint16_t)i; 2253 rcr_rings[i]->rdc_stats = &hxgep->statsp->rdc_stats[i]; 2254 } 2255 2256 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2257 rx_rbr_rings->rbr_rings = rbr_rings; 2258 hxgep->rx_rbr_rings = rx_rbr_rings; 2259 rx_rcr_rings->rcr_rings = rcr_rings; 2260 hxgep->rx_rcr_rings = rx_rcr_rings; 2261 2262 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2263 hxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2264 2265 goto hxge_map_rxdma_exit; 2266 2267 hxge_map_rxdma_fail1: 2268 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2269 "==> hxge_map_rxdma: unmap rbr,rcr (status 0x%x channel %d i %d)", 2270 status, channel, i)); 2271 i--; 2272 for (; i >= 0; i--) { 2273 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2274 hxge_unmap_rxdma_channel(hxgep, channel, 2275 rbr_rings[i], rcr_rings[i], rx_mbox_p[i]); 2276 } 2277 2278 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2279 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2280 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2281 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2282 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2283 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2284 2285 hxge_map_rxdma_exit: 2286 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2287 "<== hxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 2288 2289 return (status); 2290 } 2291 2292 static void 2293 hxge_unmap_rxdma(p_hxge_t hxgep) 2294 { 2295 int i, ndmas; 2296 uint16_t channel; 2297 p_rx_rbr_rings_t rx_rbr_rings; 2298 p_rx_rbr_ring_t *rbr_rings; 2299 p_rx_rcr_rings_t rx_rcr_rings; 2300 p_rx_rcr_ring_t *rcr_rings; 2301 p_rx_mbox_areas_t rx_mbox_areas_p; 2302 p_rx_mbox_t *rx_mbox_p; 2303 p_hxge_dma_pool_t dma_buf_poolp; 2304 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2305 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2306 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2307 p_hxge_dma_common_t *dma_buf_p; 2308 2309 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_unmap_rxdma")); 2310 2311 dma_buf_poolp = hxgep->rx_buf_pool_p; 2312 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2313 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2314 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2315 2316 if (!dma_buf_poolp->buf_allocated || 2317 !dma_rbr_cntl_poolp->buf_allocated || 2318 !dma_rcr_cntl_poolp->buf_allocated || 2319 !dma_mbox_cntl_poolp->buf_allocated) { 2320 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2321 "<== hxge_unmap_rxdma: NULL buf pointers")); 2322 return; 2323 } 2324 2325 rx_rbr_rings = hxgep->rx_rbr_rings; 2326 rx_rcr_rings = hxgep->rx_rcr_rings; 2327 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2328 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2329 "<== hxge_unmap_rxdma: NULL pointers")); 2330 return; 2331 } 2332 2333 ndmas = rx_rbr_rings->ndmas; 2334 if (!ndmas) { 2335 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2336 "<== hxge_unmap_rxdma: no channel")); 2337 return; 2338 } 2339 2340 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2341 "==> hxge_unmap_rxdma (ndmas %d)", ndmas)); 2342 2343 rbr_rings = rx_rbr_rings->rbr_rings; 2344 rcr_rings = rx_rcr_rings->rcr_rings; 2345 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 2346 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 2347 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2348 2349 for (i = 0; i < ndmas; i++) { 2350 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2351 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2352 "==> hxge_unmap_rxdma (ndmas %d) channel %d", 2353 ndmas, channel)); 2354 (void) hxge_unmap_rxdma_channel(hxgep, channel, 2355 (p_rx_rbr_ring_t)rbr_rings[i], 2356 (p_rx_rcr_ring_t)rcr_rings[i], 2357 (p_rx_mbox_t)rx_mbox_p[i]); 2358 } 2359 2360 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2361 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2362 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2363 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2364 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2365 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2366 2367 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma")); 2368 } 2369 2370 hxge_status_t 2371 hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2372 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 2373 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 2374 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 2375 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2376 { 2377 int status = HXGE_OK; 2378 2379 /* 2380 * Set up and prepare buffer blocks, descriptors and mailbox. 2381 */ 2382 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2383 "==> hxge_map_rxdma_channel (channel %d)", channel)); 2384 2385 /* 2386 * Receive buffer blocks 2387 */ 2388 status = hxge_map_rxdma_channel_buf_ring(hxgep, channel, 2389 dma_buf_p, rbr_p, num_chunks); 2390 if (status != HXGE_OK) { 2391 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2392 "==> hxge_map_rxdma_channel (channel %d): " 2393 "map buffer failed 0x%x", channel, status)); 2394 goto hxge_map_rxdma_channel_exit; 2395 } 2396 2397 /* 2398 * Receive block ring, completion ring and mailbox. 2399 */ 2400 status = hxge_map_rxdma_channel_cfg_ring(hxgep, channel, 2401 dma_rbr_cntl_p, dma_rcr_cntl_p, dma_mbox_cntl_p, 2402 rbr_p, rcr_p, rx_mbox_p); 2403 if (status != HXGE_OK) { 2404 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2405 "==> hxge_map_rxdma_channel (channel %d): " 2406 "map config failed 0x%x", channel, status)); 2407 goto hxge_map_rxdma_channel_fail2; 2408 } 2409 goto hxge_map_rxdma_channel_exit; 2410 2411 hxge_map_rxdma_channel_fail3: 2412 /* Free rbr, rcr */ 2413 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2414 "==> hxge_map_rxdma_channel: free rbr/rcr (status 0x%x channel %d)", 2415 status, channel)); 2416 hxge_unmap_rxdma_channel_cfg_ring(hxgep, *rcr_p, *rx_mbox_p); 2417 2418 hxge_map_rxdma_channel_fail2: 2419 /* Free buffer blocks */ 2420 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2421 "==> hxge_map_rxdma_channel: free rx buffers" 2422 "(hxgep 0x%x status 0x%x channel %d)", 2423 hxgep, status, channel)); 2424 hxge_unmap_rxdma_channel_buf_ring(hxgep, *rbr_p); 2425 2426 status = HXGE_ERROR; 2427 2428 hxge_map_rxdma_channel_exit: 2429 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2430 "<== hxge_map_rxdma_channel: (hxgep 0x%x status 0x%x channel %d)", 2431 hxgep, status, channel)); 2432 2433 return (status); 2434 } 2435 2436 /*ARGSUSED*/ 2437 static void 2438 hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2439 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2440 { 2441 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2442 "==> hxge_unmap_rxdma_channel (channel %d)", channel)); 2443 2444 /* 2445 * unmap receive block ring, completion ring and mailbox. 2446 */ 2447 (void) hxge_unmap_rxdma_channel_cfg_ring(hxgep, rcr_p, rx_mbox_p); 2448 2449 /* unmap buffer blocks */ 2450 (void) hxge_unmap_rxdma_channel_buf_ring(hxgep, rbr_p); 2451 2452 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma_channel")); 2453 } 2454 2455 /*ARGSUSED*/ 2456 static hxge_status_t 2457 hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, uint16_t dma_channel, 2458 p_hxge_dma_common_t *dma_rbr_cntl_p, p_hxge_dma_common_t *dma_rcr_cntl_p, 2459 p_hxge_dma_common_t *dma_mbox_cntl_p, p_rx_rbr_ring_t *rbr_p, 2460 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2461 { 2462 p_rx_rbr_ring_t rbrp; 2463 p_rx_rcr_ring_t rcrp; 2464 p_rx_mbox_t mboxp; 2465 p_hxge_dma_common_t cntl_dmap; 2466 p_hxge_dma_common_t dmap; 2467 p_rx_msg_t *rx_msg_ring; 2468 p_rx_msg_t rx_msg_p; 2469 rdc_rbr_cfg_a_t *rcfga_p; 2470 rdc_rbr_cfg_b_t *rcfgb_p; 2471 rdc_rcr_cfg_a_t *cfga_p; 2472 rdc_rcr_cfg_b_t *cfgb_p; 2473 rdc_rx_cfg1_t *cfig1_p; 2474 rdc_rx_cfg2_t *cfig2_p; 2475 rdc_rbr_kick_t *kick_p; 2476 uint32_t dmaaddrp; 2477 uint32_t *rbr_vaddrp; 2478 uint32_t bkaddr; 2479 hxge_status_t status = HXGE_OK; 2480 int i; 2481 uint32_t hxge_port_rcr_size; 2482 2483 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2484 "==> hxge_map_rxdma_channel_cfg_ring")); 2485 2486 cntl_dmap = *dma_rbr_cntl_p; 2487 2488 /* 2489 * Map in the receive block ring 2490 */ 2491 rbrp = *rbr_p; 2492 dmap = (p_hxge_dma_common_t)&rbrp->rbr_desc; 2493 hxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 2494 2495 /* 2496 * Zero out buffer block ring descriptors. 2497 */ 2498 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2499 2500 rcfga_p = &(rbrp->rbr_cfga); 2501 rcfgb_p = &(rbrp->rbr_cfgb); 2502 kick_p = &(rbrp->rbr_kick); 2503 rcfga_p->value = 0; 2504 rcfgb_p->value = 0; 2505 kick_p->value = 0; 2506 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 2507 rcfga_p->value = (rbrp->rbr_addr & 2508 (RBR_CFIG_A_STDADDR_MASK | RBR_CFIG_A_STDADDR_BASE_MASK)); 2509 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 2510 2511 /* XXXX: how to choose packet buffer sizes */ 2512 rcfgb_p->bits.bufsz0 = rbrp->pkt_buf_size0; 2513 rcfgb_p->bits.vld0 = 1; 2514 rcfgb_p->bits.bufsz1 = rbrp->pkt_buf_size1; 2515 rcfgb_p->bits.vld1 = 1; 2516 rcfgb_p->bits.bufsz2 = rbrp->pkt_buf_size2; 2517 rcfgb_p->bits.vld2 = 1; 2518 rcfgb_p->bits.bksize = hxgep->rx_bksize_code; 2519 2520 /* 2521 * For each buffer block, enter receive block address to the ring. 2522 */ 2523 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 2524 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 2525 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2526 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2527 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 2528 2529 rx_msg_ring = rbrp->rx_msg_ring; 2530 for (i = 0; i < rbrp->tnblocks; i++) { 2531 rx_msg_p = rx_msg_ring[i]; 2532 rx_msg_p->hxgep = hxgep; 2533 rx_msg_p->rx_rbr_p = rbrp; 2534 bkaddr = (uint32_t) 2535 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2536 RBR_BKADDR_SHIFT)); 2537 rx_msg_p->free = B_FALSE; 2538 rx_msg_p->max_usage_cnt = 0xbaddcafe; 2539 2540 *rbr_vaddrp++ = bkaddr; 2541 } 2542 2543 kick_p->bits.bkadd = rbrp->rbb_max; 2544 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 2545 2546 rbrp->rbr_rd_index = 0; 2547 2548 rbrp->rbr_consumed = 0; 2549 rbrp->rbr_used = 0; 2550 rbrp->rbr_use_bcopy = B_TRUE; 2551 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 2552 2553 /* 2554 * Do bcopy on packets greater than bcopy size once the lo threshold is 2555 * reached. This lo threshold should be less than the hi threshold. 2556 * 2557 * Do bcopy on every packet once the hi threshold is reached. 2558 */ 2559 if (hxge_rx_threshold_lo >= hxge_rx_threshold_hi) { 2560 /* default it to use hi */ 2561 hxge_rx_threshold_lo = hxge_rx_threshold_hi; 2562 } 2563 if (hxge_rx_buf_size_type > HXGE_RBR_TYPE2) { 2564 hxge_rx_buf_size_type = HXGE_RBR_TYPE2; 2565 } 2566 rbrp->rbr_bufsize_type = hxge_rx_buf_size_type; 2567 2568 switch (hxge_rx_threshold_hi) { 2569 default: 2570 case HXGE_RX_COPY_NONE: 2571 /* Do not do bcopy at all */ 2572 rbrp->rbr_use_bcopy = B_FALSE; 2573 rbrp->rbr_threshold_hi = rbrp->rbb_max; 2574 break; 2575 2576 case HXGE_RX_COPY_1: 2577 case HXGE_RX_COPY_2: 2578 case HXGE_RX_COPY_3: 2579 case HXGE_RX_COPY_4: 2580 case HXGE_RX_COPY_5: 2581 case HXGE_RX_COPY_6: 2582 case HXGE_RX_COPY_7: 2583 rbrp->rbr_threshold_hi = 2584 rbrp->rbb_max * (hxge_rx_threshold_hi) / 2585 HXGE_RX_BCOPY_SCALE; 2586 break; 2587 2588 case HXGE_RX_COPY_ALL: 2589 rbrp->rbr_threshold_hi = 0; 2590 break; 2591 } 2592 2593 switch (hxge_rx_threshold_lo) { 2594 default: 2595 case HXGE_RX_COPY_NONE: 2596 /* Do not do bcopy at all */ 2597 if (rbrp->rbr_use_bcopy) { 2598 rbrp->rbr_use_bcopy = B_FALSE; 2599 } 2600 rbrp->rbr_threshold_lo = rbrp->rbb_max; 2601 break; 2602 2603 case HXGE_RX_COPY_1: 2604 case HXGE_RX_COPY_2: 2605 case HXGE_RX_COPY_3: 2606 case HXGE_RX_COPY_4: 2607 case HXGE_RX_COPY_5: 2608 case HXGE_RX_COPY_6: 2609 case HXGE_RX_COPY_7: 2610 rbrp->rbr_threshold_lo = 2611 rbrp->rbb_max * (hxge_rx_threshold_lo) / 2612 HXGE_RX_BCOPY_SCALE; 2613 break; 2614 2615 case HXGE_RX_COPY_ALL: 2616 rbrp->rbr_threshold_lo = 0; 2617 break; 2618 } 2619 2620 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2621 "hxge_map_rxdma_channel_cfg_ring: channel %d rbb_max %d " 2622 "rbrp->rbr_bufsize_type %d rbb_threshold_hi %d " 2623 "rbb_threshold_lo %d", 2624 dma_channel, rbrp->rbb_max, rbrp->rbr_bufsize_type, 2625 rbrp->rbr_threshold_hi, rbrp->rbr_threshold_lo)); 2626 2627 /* Map in the receive completion ring */ 2628 rcrp = (p_rx_rcr_ring_t)KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 2629 rcrp->rdc = dma_channel; 2630 rcrp->hxgep = hxgep; 2631 2632 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 2633 rcrp->comp_size = hxge_port_rcr_size; 2634 rcrp->comp_wrap_mask = hxge_port_rcr_size - 1; 2635 2636 rcrp->max_receive_pkts = hxge_max_rx_pkts; 2637 2638 cntl_dmap = *dma_rcr_cntl_p; 2639 2640 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 2641 hxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 2642 sizeof (rcr_entry_t)); 2643 rcrp->comp_rd_index = 0; 2644 rcrp->comp_wt_index = 0; 2645 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 2646 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 2647 #if defined(__i386) 2648 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2649 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2650 #else 2651 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2652 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2653 #endif 2654 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 2655 (hxge_port_rcr_size - 1); 2656 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 2657 (hxge_port_rcr_size - 1); 2658 2659 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 2660 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 2661 2662 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2663 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2664 "rbr_vaddrp $%p rcr_desc_rd_head_p $%p " 2665 "rcr_desc_rd_head_pp $%p rcr_desc_rd_last_p $%p " 2666 "rcr_desc_rd_last_pp $%p ", 2667 dma_channel, rbr_vaddrp, rcrp->rcr_desc_rd_head_p, 2668 rcrp->rcr_desc_rd_head_pp, rcrp->rcr_desc_last_p, 2669 rcrp->rcr_desc_last_pp)); 2670 2671 /* 2672 * Zero out buffer block ring descriptors. 2673 */ 2674 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2675 rcrp->intr_timeout = hxgep->intr_timeout; 2676 rcrp->intr_threshold = hxgep->intr_threshold; 2677 rcrp->full_hdr_flag = B_FALSE; 2678 rcrp->sw_priv_hdr_len = 0; 2679 2680 cfga_p = &(rcrp->rcr_cfga); 2681 cfgb_p = &(rcrp->rcr_cfgb); 2682 cfga_p->value = 0; 2683 cfgb_p->value = 0; 2684 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 2685 2686 cfga_p->value = (rcrp->rcr_addr & 2687 (RCRCFIG_A_STADDR_MASK | RCRCFIG_A_STADDR_BASE_MASK)); 2688 2689 cfga_p->value |= ((uint64_t)rcrp->comp_size << RCRCFIG_A_LEN_SHIF); 2690 2691 /* 2692 * Timeout should be set based on the system clock divider. The 2693 * following timeout value of 1 assumes that the granularity (1000) is 2694 * 3 microseconds running at 300MHz. 2695 */ 2696 cfgb_p->bits.pthres = rcrp->intr_threshold; 2697 cfgb_p->bits.timeout = rcrp->intr_timeout; 2698 cfgb_p->bits.entout = 1; 2699 2700 /* Map in the mailbox */ 2701 cntl_dmap = *dma_mbox_cntl_p; 2702 mboxp = (p_rx_mbox_t)KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 2703 dmap = (p_hxge_dma_common_t)&mboxp->rx_mbox; 2704 hxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 2705 cfig1_p = (rdc_rx_cfg1_t *)&mboxp->rx_cfg1; 2706 cfig2_p = (rdc_rx_cfg2_t *)&mboxp->rx_cfg2; 2707 cfig1_p->value = cfig2_p->value = 0; 2708 2709 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 2710 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2711 "==> hxge_map_rxdma_channel_cfg_ring: " 2712 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 2713 dma_channel, cfig1_p->value, cfig2_p->value, 2714 mboxp->mbox_addr)); 2715 2716 dmaaddrp = (uint32_t)((dmap->dma_cookie.dmac_laddress >> 32) & 0xfff); 2717 cfig1_p->bits.mbaddr_h = dmaaddrp; 2718 2719 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 2720 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 2721 RXDMA_CFIG2_MBADDR_L_MASK); 2722 2723 cfig2_p->bits.mbaddr_l = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 2724 2725 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2726 "==> hxge_map_rxdma_channel_cfg_ring: channel %d damaddrp $%p " 2727 "cfg1 0x%016llx cfig2 0x%016llx", 2728 dma_channel, dmaaddrp, cfig1_p->value, cfig2_p->value)); 2729 2730 cfig2_p->bits.full_hdr = rcrp->full_hdr_flag; 2731 cfig2_p->bits.offset = rcrp->sw_priv_hdr_len; 2732 2733 rbrp->rx_rcr_p = rcrp; 2734 rcrp->rx_rbr_p = rbrp; 2735 *rcr_p = rcrp; 2736 *rx_mbox_p = mboxp; 2737 2738 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2739 "<== hxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 2740 return (status); 2741 } 2742 2743 /*ARGSUSED*/ 2744 static void 2745 hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 2746 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2747 { 2748 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2749 "==> hxge_unmap_rxdma_channel_cfg_ring: channel %d", rcr_p->rdc)); 2750 2751 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 2752 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 2753 2754 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2755 "<== hxge_unmap_rxdma_channel_cfg_ring")); 2756 } 2757 2758 static hxge_status_t 2759 hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel, 2760 p_hxge_dma_common_t *dma_buf_p, 2761 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 2762 { 2763 p_rx_rbr_ring_t rbrp; 2764 p_hxge_dma_common_t dma_bufp, tmp_bufp; 2765 p_rx_msg_t *rx_msg_ring; 2766 p_rx_msg_t rx_msg_p; 2767 p_mblk_t mblk_p; 2768 2769 rxring_info_t *ring_info; 2770 hxge_status_t status = HXGE_OK; 2771 int i, j, index; 2772 uint32_t size, bsize, nblocks, nmsgs; 2773 2774 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2775 "==> hxge_map_rxdma_channel_buf_ring: channel %d", channel)); 2776 2777 dma_bufp = tmp_bufp = *dma_buf_p; 2778 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2779 " hxge_map_rxdma_channel_buf_ring: channel %d to map %d " 2780 "chunks bufp 0x%016llx", channel, num_chunks, dma_bufp)); 2781 2782 nmsgs = 0; 2783 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 2784 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2785 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2786 "bufp 0x%016llx nblocks %d nmsgs %d", 2787 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 2788 nmsgs += tmp_bufp->nblocks; 2789 } 2790 if (!nmsgs) { 2791 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2792 "<== hxge_map_rxdma_channel_buf_ring: channel %d " 2793 "no msg blocks", channel)); 2794 status = HXGE_ERROR; 2795 goto hxge_map_rxdma_channel_buf_ring_exit; 2796 } 2797 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (rx_rbr_ring_t), KM_SLEEP); 2798 2799 size = nmsgs * sizeof (p_rx_msg_t); 2800 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 2801 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 2802 KM_SLEEP); 2803 2804 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 2805 (void *) hxgep->interrupt_cookie); 2806 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 2807 (void *) hxgep->interrupt_cookie); 2808 2809 rbrp->rdc = channel; 2810 rbrp->num_blocks = num_chunks; 2811 rbrp->tnblocks = nmsgs; 2812 rbrp->rbb_max = nmsgs; 2813 rbrp->rbr_max_size = nmsgs; 2814 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 2815 2816 /* 2817 * Buffer sizes suggested by NIU architect. 256, 512 and 2K. 2818 */ 2819 2820 switch (hxgep->rx_bksize_code) { 2821 case RBR_BKSIZE_4K: 2822 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 2823 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 2824 rbrp->hpi_pkt_buf_size0 = SIZE_256B; 2825 break; 2826 case RBR_BKSIZE_8K: 2827 /* Use 512 to avoid possible rcr_full condition */ 2828 rbrp->pkt_buf_size0 = RBR_BUFSZ0_512B; 2829 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_512_BYTES; 2830 rbrp->hpi_pkt_buf_size0 = SIZE_512B; 2831 break; 2832 } 2833 2834 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 2835 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 2836 rbrp->hpi_pkt_buf_size1 = SIZE_1KB; 2837 2838 rbrp->block_size = hxgep->rx_default_block_size; 2839 2840 if (!hxgep->param_arr[param_accept_jumbo].value) { 2841 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 2842 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 2843 rbrp->hpi_pkt_buf_size2 = SIZE_2KB; 2844 } else { 2845 rbrp->hpi_pkt_buf_size2 = SIZE_4KB; 2846 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 2847 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 2848 } 2849 2850 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2851 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2852 "actual rbr max %d rbb_max %d nmsgs %d " 2853 "rbrp->block_size %d default_block_size %d " 2854 "(config hxge_rbr_size %d hxge_rbr_spare_size %d)", 2855 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 2856 rbrp->block_size, hxgep->rx_default_block_size, 2857 hxge_rbr_size, hxge_rbr_spare_size)); 2858 2859 /* 2860 * Map in buffers from the buffer pool. 2861 * Note that num_blocks is the num_chunks. For Sparc, there is likely 2862 * only one chunk. For x86, there will be many chunks. 2863 * Loop over chunks. 2864 */ 2865 index = 0; 2866 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 2867 bsize = dma_bufp->block_size; 2868 nblocks = dma_bufp->nblocks; 2869 #if defined(__i386) 2870 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 2871 #else 2872 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 2873 #endif 2874 ring_info->buffer[i].buf_index = i; 2875 ring_info->buffer[i].buf_size = dma_bufp->alength; 2876 ring_info->buffer[i].start_index = index; 2877 #if defined(__i386) 2878 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 2879 #else 2880 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 2881 #endif 2882 2883 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2884 " hxge_map_rxdma_channel_buf_ring: map channel %d " 2885 "chunk %d nblocks %d chunk_size %x block_size 0x%x " 2886 "dma_bufp $%p dvma_addr $%p", channel, i, 2887 dma_bufp->nblocks, 2888 ring_info->buffer[i].buf_size, bsize, dma_bufp, 2889 ring_info->buffer[i].dvma_addr)); 2890 2891 /* loop over blocks within a chunk */ 2892 for (j = 0; j < nblocks; j++) { 2893 if ((rx_msg_p = hxge_allocb(bsize, BPRI_LO, 2894 dma_bufp)) == NULL) { 2895 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2896 "allocb failed (index %d i %d j %d)", 2897 index, i, j)); 2898 goto hxge_map_rxdma_channel_buf_ring_fail1; 2899 } 2900 rx_msg_ring[index] = rx_msg_p; 2901 rx_msg_p->block_index = index; 2902 rx_msg_p->shifted_addr = (uint32_t) 2903 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2904 RBR_BKADDR_SHIFT)); 2905 /* 2906 * Too much output 2907 * HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2908 * "index %d j %d rx_msg_p $%p mblk %p", 2909 * index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 2910 */ 2911 mblk_p = rx_msg_p->rx_mblk_p; 2912 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 2913 2914 rbrp->rbr_ref_cnt++; 2915 index++; 2916 rx_msg_p->buf_dma.dma_channel = channel; 2917 } 2918 } 2919 if (i < rbrp->num_blocks) { 2920 goto hxge_map_rxdma_channel_buf_ring_fail1; 2921 } 2922 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2923 "hxge_map_rxdma_channel_buf_ring: done buf init " 2924 "channel %d msg block entries %d", channel, index)); 2925 ring_info->block_size_mask = bsize - 1; 2926 rbrp->rx_msg_ring = rx_msg_ring; 2927 rbrp->dma_bufp = dma_buf_p; 2928 rbrp->ring_info = ring_info; 2929 2930 status = hxge_rxbuf_index_info_init(hxgep, rbrp); 2931 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, " hxge_map_rxdma_channel_buf_ring: " 2932 "channel %d done buf info init", channel)); 2933 2934 /* 2935 * Finally, permit hxge_freeb() to call hxge_post_page(). 2936 */ 2937 rbrp->rbr_state = RBR_POSTING; 2938 2939 *rbr_p = rbrp; 2940 2941 goto hxge_map_rxdma_channel_buf_ring_exit; 2942 2943 hxge_map_rxdma_channel_buf_ring_fail1: 2944 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2945 " hxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 2946 channel, status)); 2947 2948 index--; 2949 for (; index >= 0; index--) { 2950 rx_msg_p = rx_msg_ring[index]; 2951 if (rx_msg_p != NULL) { 2952 freeb(rx_msg_p->rx_mblk_p); 2953 rx_msg_ring[index] = NULL; 2954 } 2955 } 2956 2957 hxge_map_rxdma_channel_buf_ring_fail: 2958 MUTEX_DESTROY(&rbrp->post_lock); 2959 MUTEX_DESTROY(&rbrp->lock); 2960 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 2961 KMEM_FREE(rx_msg_ring, size); 2962 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 2963 2964 status = HXGE_ERROR; 2965 2966 hxge_map_rxdma_channel_buf_ring_exit: 2967 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2968 "<== hxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 2969 2970 return (status); 2971 } 2972 2973 /*ARGSUSED*/ 2974 static void 2975 hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 2976 p_rx_rbr_ring_t rbr_p) 2977 { 2978 p_rx_msg_t *rx_msg_ring; 2979 p_rx_msg_t rx_msg_p; 2980 rxring_info_t *ring_info; 2981 int i; 2982 uint32_t size; 2983 2984 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2985 "==> hxge_unmap_rxdma_channel_buf_ring")); 2986 if (rbr_p == NULL) { 2987 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2988 "<== hxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 2989 return; 2990 } 2991 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2992 "==> hxge_unmap_rxdma_channel_buf_ring: channel %d", rbr_p->rdc)); 2993 2994 rx_msg_ring = rbr_p->rx_msg_ring; 2995 ring_info = rbr_p->ring_info; 2996 2997 if (rx_msg_ring == NULL || ring_info == NULL) { 2998 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2999 "<== hxge_unmap_rxdma_channel_buf_ring: " 3000 "rx_msg_ring $%p ring_info $%p", rx_msg_p, ring_info)); 3001 return; 3002 } 3003 3004 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3005 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3006 " hxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3007 "tnblocks %d (max %d) size ptrs %d ", rbr_p->rdc, rbr_p->num_blocks, 3008 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3009 3010 for (i = 0; i < rbr_p->tnblocks; i++) { 3011 rx_msg_p = rx_msg_ring[i]; 3012 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3013 " hxge_unmap_rxdma_channel_buf_ring: " 3014 "rx_msg_p $%p", rx_msg_p)); 3015 if (rx_msg_p != NULL) { 3016 freeb(rx_msg_p->rx_mblk_p); 3017 rx_msg_ring[i] = NULL; 3018 } 3019 } 3020 3021 /* 3022 * We no longer may use the mutex <post_lock>. By setting 3023 * <rbr_state> to anything but POSTING, we prevent 3024 * hxge_post_page() from accessing a dead mutex. 3025 */ 3026 rbr_p->rbr_state = RBR_UNMAPPING; 3027 MUTEX_DESTROY(&rbr_p->post_lock); 3028 3029 MUTEX_DESTROY(&rbr_p->lock); 3030 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3031 KMEM_FREE(rx_msg_ring, size); 3032 3033 if (rbr_p->rbr_ref_cnt == 0) { 3034 /* This is the normal state of affairs. */ 3035 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 3036 } else { 3037 /* 3038 * Some of our buffers are still being used. 3039 * Therefore, tell hxge_freeb() this ring is 3040 * unmapped, so it may free <rbr_p> for us. 3041 */ 3042 rbr_p->rbr_state = RBR_UNMAPPED; 3043 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3044 "unmap_rxdma_buf_ring: %d %s outstanding.", 3045 rbr_p->rbr_ref_cnt, 3046 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 3047 } 3048 3049 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3050 "<== hxge_unmap_rxdma_channel_buf_ring")); 3051 } 3052 3053 static hxge_status_t 3054 hxge_rxdma_hw_start_common(p_hxge_t hxgep) 3055 { 3056 hxge_status_t status = HXGE_OK; 3057 3058 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 3059 3060 /* 3061 * Load the sharable parameters by writing to the function zero control 3062 * registers. These FZC registers should be initialized only once for 3063 * the entire chip. 3064 */ 3065 (void) hxge_init_fzc_rx_common(hxgep); 3066 3067 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 3068 3069 return (status); 3070 } 3071 3072 static hxge_status_t 3073 hxge_rxdma_hw_start(p_hxge_t hxgep) 3074 { 3075 int i, ndmas; 3076 uint16_t channel; 3077 p_rx_rbr_rings_t rx_rbr_rings; 3078 p_rx_rbr_ring_t *rbr_rings; 3079 p_rx_rcr_rings_t rx_rcr_rings; 3080 p_rx_rcr_ring_t *rcr_rings; 3081 p_rx_mbox_areas_t rx_mbox_areas_p; 3082 p_rx_mbox_t *rx_mbox_p; 3083 hxge_status_t status = HXGE_OK; 3084 3085 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start")); 3086 3087 rx_rbr_rings = hxgep->rx_rbr_rings; 3088 rx_rcr_rings = hxgep->rx_rcr_rings; 3089 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3090 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3091 "<== hxge_rxdma_hw_start: NULL ring pointers")); 3092 return (HXGE_ERROR); 3093 } 3094 3095 ndmas = rx_rbr_rings->ndmas; 3096 if (ndmas == 0) { 3097 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3098 "<== hxge_rxdma_hw_start: no dma channel allocated")); 3099 return (HXGE_ERROR); 3100 } 3101 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3102 "==> hxge_rxdma_hw_start (ndmas %d)", ndmas)); 3103 3104 /* 3105 * Scrub the RDC Rx DMA Prefetch Buffer Command. 3106 */ 3107 for (i = 0; i < 128; i++) { 3108 HXGE_REG_WR64(hxgep->hpi_handle, RDC_PREF_CMD, i); 3109 } 3110 3111 /* 3112 * Scrub Rx DMA Shadow Tail Command. 3113 */ 3114 for (i = 0; i < 64; i++) { 3115 HXGE_REG_WR64(hxgep->hpi_handle, RDC_SHADOW_CMD, i); 3116 } 3117 3118 /* 3119 * Scrub Rx DMA Control Fifo Command. 3120 */ 3121 for (i = 0; i < 512; i++) { 3122 HXGE_REG_WR64(hxgep->hpi_handle, RDC_CTRL_FIFO_CMD, i); 3123 } 3124 3125 /* 3126 * Scrub Rx DMA Data Fifo Command. 3127 */ 3128 for (i = 0; i < 1536; i++) { 3129 HXGE_REG_WR64(hxgep->hpi_handle, RDC_DATA_FIFO_CMD, i); 3130 } 3131 3132 /* 3133 * Reset the FIFO Error Stat. 3134 */ 3135 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_STAT, 0xFF); 3136 3137 /* Set the error mask to receive interrupts */ 3138 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3139 3140 rbr_rings = rx_rbr_rings->rbr_rings; 3141 rcr_rings = rx_rcr_rings->rcr_rings; 3142 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 3143 if (rx_mbox_areas_p) { 3144 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3145 } 3146 3147 for (i = 0; i < ndmas; i++) { 3148 channel = rbr_rings[i]->rdc; 3149 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3150 "==> hxge_rxdma_hw_start (ndmas %d) channel %d", 3151 ndmas, channel)); 3152 status = hxge_rxdma_start_channel(hxgep, channel, 3153 (p_rx_rbr_ring_t)rbr_rings[i], 3154 (p_rx_rcr_ring_t)rcr_rings[i], 3155 (p_rx_mbox_t)rx_mbox_p[i], rbr_rings[i]->rbb_max); 3156 if (status != HXGE_OK) { 3157 goto hxge_rxdma_hw_start_fail1; 3158 } 3159 } 3160 3161 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start: " 3162 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3163 rx_rbr_rings, rx_rcr_rings)); 3164 goto hxge_rxdma_hw_start_exit; 3165 3166 hxge_rxdma_hw_start_fail1: 3167 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3168 "==> hxge_rxdma_hw_start: disable " 3169 "(status 0x%x channel %d i %d)", status, channel, i)); 3170 for (; i >= 0; i--) { 3171 channel = rbr_rings[i]->rdc; 3172 (void) hxge_rxdma_stop_channel(hxgep, channel); 3173 } 3174 3175 hxge_rxdma_hw_start_exit: 3176 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3177 "==> hxge_rxdma_hw_start: (status 0x%x)", status)); 3178 return (status); 3179 } 3180 3181 static void 3182 hxge_rxdma_hw_stop(p_hxge_t hxgep) 3183 { 3184 int i, ndmas; 3185 uint16_t channel; 3186 p_rx_rbr_rings_t rx_rbr_rings; 3187 p_rx_rbr_ring_t *rbr_rings; 3188 p_rx_rcr_rings_t rx_rcr_rings; 3189 3190 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop")); 3191 3192 rx_rbr_rings = hxgep->rx_rbr_rings; 3193 rx_rcr_rings = hxgep->rx_rcr_rings; 3194 3195 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3196 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3197 "<== hxge_rxdma_hw_stop: NULL ring pointers")); 3198 return; 3199 } 3200 3201 ndmas = rx_rbr_rings->ndmas; 3202 if (!ndmas) { 3203 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3204 "<== hxge_rxdma_hw_stop: no dma channel allocated")); 3205 return; 3206 } 3207 3208 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3209 "==> hxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3210 3211 rbr_rings = rx_rbr_rings->rbr_rings; 3212 for (i = 0; i < ndmas; i++) { 3213 channel = rbr_rings[i]->rdc; 3214 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3215 "==> hxge_rxdma_hw_stop (ndmas %d) channel %d", 3216 ndmas, channel)); 3217 (void) hxge_rxdma_stop_channel(hxgep, channel); 3218 } 3219 3220 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop: " 3221 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3222 rx_rbr_rings, rx_rcr_rings)); 3223 3224 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_hw_stop")); 3225 } 3226 3227 static hxge_status_t 3228 hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 3229 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p, 3230 int n_init_kick) 3231 { 3232 hpi_handle_t handle; 3233 hpi_status_t rs = HPI_SUCCESS; 3234 rdc_stat_t cs; 3235 rdc_int_mask_t ent_mask; 3236 hxge_status_t status = HXGE_OK; 3237 3238 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel")); 3239 3240 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3241 3242 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "hxge_rxdma_start_channel: " 3243 "hpi handle addr $%p acc $%p", 3244 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3245 3246 /* Reset RXDMA channel */ 3247 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3248 if (rs != HPI_SUCCESS) { 3249 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3250 "==> hxge_rxdma_start_channel: " 3251 "reset rxdma failed (0x%08x channel %d)", 3252 status, channel)); 3253 return (HXGE_ERROR | rs); 3254 } 3255 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3256 "==> hxge_rxdma_start_channel: reset done: channel %d", channel)); 3257 3258 /* 3259 * Initialize the RXDMA channel specific FZC control configurations. 3260 * These FZC registers are pertaining to each RX channel (logical 3261 * pages). 3262 */ 3263 status = hxge_init_fzc_rxdma_channel(hxgep, 3264 channel, rbr_p, rcr_p, mbox_p); 3265 if (status != HXGE_OK) { 3266 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3267 "==> hxge_rxdma_start_channel: " 3268 "init fzc rxdma failed (0x%08x channel %d)", 3269 status, channel)); 3270 return (status); 3271 } 3272 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3273 "==> hxge_rxdma_start_channel: fzc done")); 3274 3275 /* 3276 * Zero out the shadow and prefetch ram. 3277 */ 3278 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3279 "==> hxge_rxdma_start_channel: ram done")); 3280 3281 /* Set up the interrupt event masks. */ 3282 ent_mask.value = 0; 3283 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3284 if (rs != HPI_SUCCESS) { 3285 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3286 "==> hxge_rxdma_start_channel: " 3287 "init rxdma event masks failed (0x%08x channel %d)", 3288 status, channel)); 3289 return (HXGE_ERROR | rs); 3290 } 3291 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3292 "event done: channel %d (mask 0x%016llx)", 3293 channel, ent_mask.value)); 3294 3295 /* 3296 * Load RXDMA descriptors, buffers, mailbox, initialise the receive DMA 3297 * channels and enable each DMA channel. 3298 */ 3299 status = hxge_enable_rxdma_channel(hxgep, 3300 channel, rbr_p, rcr_p, mbox_p, n_init_kick); 3301 if (status != HXGE_OK) { 3302 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3303 " hxge_rxdma_start_channel: " 3304 " init enable rxdma failed (0x%08x channel %d)", 3305 status, channel)); 3306 return (status); 3307 } 3308 3309 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3310 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3311 3312 /* 3313 * Initialize the receive DMA control and status register 3314 * Note that rdc_stat HAS to be set after RBR and RCR rings are set 3315 */ 3316 cs.value = 0; 3317 cs.bits.mex = 1; 3318 cs.bits.rcr_thres = 1; 3319 cs.bits.rcr_to = 1; 3320 cs.bits.rbr_empty = 1; 3321 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3322 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3323 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 3324 if (status != HXGE_OK) { 3325 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3326 "==> hxge_rxdma_start_channel: " 3327 "init rxdma control register failed (0x%08x channel %d", 3328 status, channel)); 3329 return (status); 3330 } 3331 3332 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3333 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3334 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3335 "==> hxge_rxdma_start_channel: enable done")); 3336 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_start_channel")); 3337 3338 return (HXGE_OK); 3339 } 3340 3341 static hxge_status_t 3342 hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel) 3343 { 3344 hpi_handle_t handle; 3345 hpi_status_t rs = HPI_SUCCESS; 3346 rdc_stat_t cs; 3347 rdc_int_mask_t ent_mask; 3348 hxge_status_t status = HXGE_OK; 3349 3350 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel")); 3351 3352 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3353 3354 HXGE_DEBUG_MSG((hxgep, RX_CTL, "hxge_rxdma_stop_channel: " 3355 "hpi handle addr $%p acc $%p", 3356 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3357 3358 /* Reset RXDMA channel */ 3359 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3360 if (rs != HPI_SUCCESS) { 3361 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3362 " hxge_rxdma_stop_channel: " 3363 " reset rxdma failed (0x%08x channel %d)", 3364 rs, channel)); 3365 return (HXGE_ERROR | rs); 3366 } 3367 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3368 "==> hxge_rxdma_stop_channel: reset done")); 3369 3370 /* Set up the interrupt event masks. */ 3371 ent_mask.value = RDC_INT_MASK_ALL; 3372 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3373 if (rs != HPI_SUCCESS) { 3374 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3375 "==> hxge_rxdma_stop_channel: " 3376 "set rxdma event masks failed (0x%08x channel %d)", 3377 rs, channel)); 3378 return (HXGE_ERROR | rs); 3379 } 3380 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3381 "==> hxge_rxdma_stop_channel: event done")); 3382 3383 /* Initialize the receive DMA control and status register */ 3384 cs.value = 0; 3385 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3386 3387 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel: control " 3388 " to default (all 0s) 0x%08x", cs.value)); 3389 3390 if (status != HXGE_OK) { 3391 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3392 " hxge_rxdma_stop_channel: init rxdma" 3393 " control register failed (0x%08x channel %d", 3394 status, channel)); 3395 return (status); 3396 } 3397 3398 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3399 "==> hxge_rxdma_stop_channel: control done")); 3400 3401 /* disable dma channel */ 3402 status = hxge_disable_rxdma_channel(hxgep, channel); 3403 3404 if (status != HXGE_OK) { 3405 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3406 " hxge_rxdma_stop_channel: " 3407 " init enable rxdma failed (0x%08x channel %d)", 3408 status, channel)); 3409 return (status); 3410 } 3411 3412 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3413 "==> hxge_rxdma_stop_channel: disable done")); 3414 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_channel")); 3415 3416 return (HXGE_OK); 3417 } 3418 3419 hxge_status_t 3420 hxge_rxdma_handle_sys_errors(p_hxge_t hxgep) 3421 { 3422 hpi_handle_t handle; 3423 p_hxge_rdc_sys_stats_t statsp; 3424 rdc_fifo_err_stat_t stat; 3425 hxge_status_t status = HXGE_OK; 3426 3427 handle = hxgep->hpi_handle; 3428 statsp = (p_hxge_rdc_sys_stats_t)&hxgep->statsp->rdc_sys_stats; 3429 3430 /* Clear the int_dbg register in case it is an injected err */ 3431 HXGE_REG_WR64(handle, RDC_FIFO_ERR_INT_DBG, 0x0); 3432 3433 /* Get the error status and clear the register */ 3434 HXGE_REG_RD64(handle, RDC_FIFO_ERR_STAT, &stat.value); 3435 HXGE_REG_WR64(handle, RDC_FIFO_ERR_STAT, stat.value); 3436 3437 if (stat.bits.rx_ctrl_fifo_sec) { 3438 statsp->ctrl_fifo_sec++; 3439 if (statsp->ctrl_fifo_sec == 1) 3440 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3441 "==> hxge_rxdma_handle_sys_errors: " 3442 "rx_ctrl_fifo_sec")); 3443 } 3444 3445 if (stat.bits.rx_ctrl_fifo_ded) { 3446 /* Global fatal error encountered */ 3447 statsp->ctrl_fifo_ded++; 3448 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3449 HXGE_FM_EREPORT_RDMC_CTRL_FIFO_DED); 3450 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3451 "==> hxge_rxdma_handle_sys_errors: " 3452 "fatal error: rx_ctrl_fifo_ded error")); 3453 } 3454 3455 if (stat.bits.rx_data_fifo_sec) { 3456 statsp->data_fifo_sec++; 3457 if (statsp->data_fifo_sec == 1) 3458 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3459 "==> hxge_rxdma_handle_sys_errors: " 3460 "rx_data_fifo_sec")); 3461 } 3462 3463 if (stat.bits.rx_data_fifo_ded) { 3464 /* Global fatal error encountered */ 3465 statsp->data_fifo_ded++; 3466 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3467 HXGE_FM_EREPORT_RDMC_DATA_FIFO_DED); 3468 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3469 "==> hxge_rxdma_handle_sys_errors: " 3470 "fatal error: rx_data_fifo_ded error")); 3471 } 3472 3473 if (stat.bits.rx_ctrl_fifo_ded || stat.bits.rx_data_fifo_ded) { 3474 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3475 " hxge_rxdma_handle_sys_errors: fatal error\n")); 3476 status = hxge_rx_port_fatal_err_recover(hxgep); 3477 if (status == HXGE_OK) { 3478 FM_SERVICE_RESTORED(hxgep); 3479 } 3480 } 3481 3482 return (HXGE_OK); 3483 } 3484 3485 static hxge_status_t 3486 hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel) 3487 { 3488 hpi_handle_t handle; 3489 hpi_status_t rs = HPI_SUCCESS; 3490 hxge_status_t status = HXGE_OK; 3491 p_rx_rbr_ring_t rbrp; 3492 p_rx_rcr_ring_t rcrp; 3493 p_rx_mbox_t mboxp; 3494 rdc_int_mask_t ent_mask; 3495 p_hxge_dma_common_t dmap; 3496 int ring_idx; 3497 p_rx_msg_t rx_msg_p; 3498 int i; 3499 uint32_t hxge_port_rcr_size; 3500 uint64_t tmp; 3501 int n_init_kick = 0; 3502 3503 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_fatal_err_recover")); 3504 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3505 "Recovering from RxDMAChannel#%d error...", channel)); 3506 3507 /* 3508 * Stop the dma channel waits for the stop done. If the stop done bit 3509 * is not set, then create an error. 3510 */ 3511 3512 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3513 3514 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Rx DMA stop...")); 3515 3516 ring_idx = hxge_rxdma_get_ring_index(hxgep, channel); 3517 rbrp = (p_rx_rbr_ring_t)hxgep->rx_rbr_rings->rbr_rings[ring_idx]; 3518 rcrp = (p_rx_rcr_ring_t)hxgep->rx_rcr_rings->rcr_rings[ring_idx]; 3519 3520 MUTEX_ENTER(&rcrp->lock); 3521 MUTEX_ENTER(&rbrp->lock); 3522 3523 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA channel...")); 3524 3525 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 3526 if (rs != HPI_SUCCESS) { 3527 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3528 "hxge_disable_rxdma_channel:failed")); 3529 goto fail; 3530 } 3531 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA interrupt...")); 3532 3533 /* Disable interrupt */ 3534 ent_mask.value = RDC_INT_MASK_ALL; 3535 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3536 if (rs != HPI_SUCCESS) { 3537 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3538 "Set rxdma event masks failed (channel %d)", channel)); 3539 } 3540 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel reset...")); 3541 3542 /* Reset RXDMA channel */ 3543 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3544 if (rs != HPI_SUCCESS) { 3545 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3546 "Reset rxdma failed (channel %d)", channel)); 3547 goto fail; 3548 } 3549 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 3550 mboxp = (p_rx_mbox_t)hxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 3551 3552 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3553 rbrp->rbr_rd_index = 0; 3554 3555 rcrp->comp_rd_index = 0; 3556 rcrp->comp_wt_index = 0; 3557 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3558 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3559 #if defined(__i386) 3560 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3561 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3562 #else 3563 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3564 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3565 #endif 3566 3567 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3568 (hxge_port_rcr_size - 1); 3569 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3570 (hxge_port_rcr_size - 1); 3571 3572 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 3573 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 3574 3575 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 3576 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3577 3578 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rbr entries = %d\n", 3579 rbrp->rbr_max_size)); 3580 3581 /* Count the number of buffers owned by the hardware at this moment */ 3582 for (i = 0; i < rbrp->rbr_max_size; i++) { 3583 rx_msg_p = rbrp->rx_msg_ring[i]; 3584 if (rx_msg_p->ref_cnt == 1) { 3585 n_init_kick++; 3586 } 3587 } 3588 3589 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel re-start...")); 3590 3591 /* 3592 * This is error recover! Some buffers are owned by the hardware and 3593 * the rest are owned by the apps. We should only kick in those 3594 * owned by the hardware initially. The apps will post theirs 3595 * eventually. 3596 */ 3597 status = hxge_rxdma_start_channel(hxgep, channel, rbrp, rcrp, mboxp, 3598 n_init_kick); 3599 if (status != HXGE_OK) { 3600 goto fail; 3601 } 3602 3603 /* 3604 * The DMA channel may disable itself automatically. 3605 * The following is a work-around. 3606 */ 3607 HXGE_REG_RD64(handle, RDC_RX_CFG1, &tmp); 3608 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 3609 if (rs != HPI_SUCCESS) { 3610 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3611 "hpi_rxdma_cfg_rdc_enable (channel %d)", channel)); 3612 } 3613 3614 MUTEX_EXIT(&rbrp->lock); 3615 MUTEX_EXIT(&rcrp->lock); 3616 3617 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3618 "Recovery Successful, RxDMAChannel#%d Restored", channel)); 3619 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_fatal_err_recover")); 3620 3621 return (HXGE_OK); 3622 3623 fail: 3624 MUTEX_EXIT(&rbrp->lock); 3625 MUTEX_EXIT(&rcrp->lock); 3626 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3627 3628 return (HXGE_ERROR | rs); 3629 } 3630 3631 static hxge_status_t 3632 hxge_rx_port_fatal_err_recover(p_hxge_t hxgep) 3633 { 3634 hxge_status_t status = HXGE_OK; 3635 p_hxge_dma_common_t *dma_buf_p; 3636 uint16_t channel; 3637 int ndmas; 3638 int i; 3639 block_reset_t reset_reg; 3640 p_rx_rcr_ring_t rcrp; 3641 p_rx_rbr_ring_t rbrp; 3642 3643 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_port_fatal_err_recover")); 3644 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovering from RDC error ...")); 3645 3646 /* Reset RDC block from PEU for this fatal error */ 3647 reset_reg.value = 0; 3648 reset_reg.bits.rdc_rst = 1; 3649 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 3650 3651 /* Disable RxMAC */ 3652 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxMAC...\n")); 3653 if (hxge_rx_vmac_disable(hxgep) != HXGE_OK) 3654 goto fail; 3655 3656 HXGE_DELAY(1000); 3657 3658 /* Restore any common settings after PEU reset */ 3659 if (hxge_rxdma_hw_start_common(hxgep) != HXGE_OK) 3660 goto fail; 3661 3662 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Stop all RxDMA channels...")); 3663 3664 ndmas = hxgep->rx_buf_pool_p->ndmas; 3665 dma_buf_p = hxgep->rx_buf_pool_p->dma_buf_pool_p; 3666 3667 for (i = 0; i < ndmas; i++) { 3668 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 3669 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel]; 3670 rbrp = rcrp->rx_rbr_p; 3671 3672 MUTEX_ENTER(&rbrp->post_lock); 3673 /* This function needs to be inside the post_lock */ 3674 if (hxge_rxdma_fatal_err_recover(hxgep, channel) != HXGE_OK) { 3675 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3676 "Could not recover channel %d", channel)); 3677 } 3678 MUTEX_EXIT(&rbrp->post_lock); 3679 } 3680 3681 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Reset RxMAC...")); 3682 3683 /* Reset RxMAC */ 3684 if (hxge_rx_vmac_reset(hxgep) != HXGE_OK) { 3685 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3686 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3687 goto fail; 3688 } 3689 3690 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-initialize RxMAC...")); 3691 3692 /* Re-Initialize RxMAC */ 3693 if ((status = hxge_rx_vmac_init(hxgep)) != HXGE_OK) { 3694 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3695 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3696 goto fail; 3697 } 3698 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-enable RxMAC...")); 3699 3700 /* Re-enable RxMAC */ 3701 if ((status = hxge_rx_vmac_enable(hxgep)) != HXGE_OK) { 3702 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3703 "hxge_rx_port_fatal_err_recover: Failed to enable RxMAC")); 3704 goto fail; 3705 } 3706 3707 /* Reset the error mask since PEU reset cleared it */ 3708 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3709 3710 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3711 "Recovery Successful, RxPort Restored")); 3712 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_port_fatal_err_recover")); 3713 3714 return (HXGE_OK); 3715 fail: 3716 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3717 return (status); 3718 } 3719 3720 static void 3721 hxge_rbr_empty_restore(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p) 3722 { 3723 hpi_status_t hpi_status; 3724 hxge_status_t status; 3725 int i; 3726 p_hxge_rx_ring_stats_t rdc_stats; 3727 3728 rdc_stats = &hxgep->statsp->rdc_stats[rx_rbr_p->rdc]; 3729 rdc_stats->rbr_empty_restore++; 3730 rx_rbr_p->rbr_is_empty = B_FALSE; 3731 3732 /* 3733 * Complete the processing for the RBR Empty by: 3734 * 0) kicking back HXGE_RBR_EMPTY_THRESHOLD 3735 * packets. 3736 * 1) Disable the RX vmac. 3737 * 2) Re-enable the affected DMA channel. 3738 * 3) Re-enable the RX vmac. 3739 */ 3740 3741 /* 3742 * Disable the RX VMAC, but setting the framelength 3743 * to 0, since there is a hardware bug when disabling 3744 * the vmac. 3745 */ 3746 MUTEX_ENTER(hxgep->genlock); 3747 (void) hpi_vmac_rx_set_framesize( 3748 HXGE_DEV_HPI_HANDLE(hxgep), (uint16_t)0); 3749 3750 hpi_status = hpi_rxdma_cfg_rdc_enable( 3751 HXGE_DEV_HPI_HANDLE(hxgep), rx_rbr_p->rdc); 3752 if (hpi_status != HPI_SUCCESS) { 3753 rdc_stats->rbr_empty_fail++; 3754 3755 /* Assume we are already inside the post_lock */ 3756 status = hxge_rxdma_fatal_err_recover(hxgep, rx_rbr_p->rdc); 3757 if (status != HXGE_OK) { 3758 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3759 "hxge(%d): channel(%d) is empty.", 3760 hxgep->instance, rx_rbr_p->rdc)); 3761 } 3762 } 3763 3764 for (i = 0; i < 1024; i++) { 3765 uint64_t value; 3766 RXDMA_REG_READ64(HXGE_DEV_HPI_HANDLE(hxgep), 3767 RDC_STAT, i & 3, &value); 3768 } 3769 3770 /* 3771 * Re-enable the RX VMAC. 3772 */ 3773 (void) hpi_vmac_rx_set_framesize(HXGE_DEV_HPI_HANDLE(hxgep), 3774 (uint16_t)hxgep->vmac.maxframesize); 3775 MUTEX_EXIT(hxgep->genlock); 3776 } 3777