1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HXGE_RDC_HW_H 27 #define _HXGE_RDC_HW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define RDC_BASE_ADDR 0X00300000 36 37 #define RDC_PAGE_HANDLE (RDC_BASE_ADDR + 0x8) 38 #define RDC_RX_CFG1 (RDC_BASE_ADDR + 0x20) 39 #define RDC_RX_CFG2 (RDC_BASE_ADDR + 0x28) 40 #define RDC_RBR_CFG_A (RDC_BASE_ADDR + 0x40) 41 #define RDC_RBR_CFG_B (RDC_BASE_ADDR + 0x48) 42 #define RDC_RBR_KICK (RDC_BASE_ADDR + 0x50) 43 #define RDC_RBR_QLEN (RDC_BASE_ADDR + 0x58) 44 #define RDC_RBR_HEAD (RDC_BASE_ADDR + 0x68) 45 #define RDC_RCR_CFG_A (RDC_BASE_ADDR + 0x80) 46 #define RDC_RCR_CFG_B (RDC_BASE_ADDR + 0x88) 47 #define RDC_RCR_QLEN (RDC_BASE_ADDR + 0x90) 48 #define RDC_RCR_TAIL (RDC_BASE_ADDR + 0xA0) 49 #define RDC_RCR_FLUSH (RDC_BASE_ADDR + 0xA8) 50 #define RDC_CLOCK_DIV (RDC_BASE_ADDR + 0xB0) 51 #define RDC_INT_MASK (RDC_BASE_ADDR + 0xB8) 52 #define RDC_STAT (RDC_BASE_ADDR + 0xC0) 53 #define RDC_PKT_COUNT (RDC_BASE_ADDR + 0xD0) 54 #define RDC_DROP_COUNT (RDC_BASE_ADDR + 0xD8) 55 #define RDC_BYTE_COUNT (RDC_BASE_ADDR + 0xE0) 56 #define RDC_PREF_CMD (RDC_BASE_ADDR + 0x100) 57 #define RDC_PREF_DATA (RDC_BASE_ADDR + 0x108) 58 #define RDC_SHADOW_CMD (RDC_BASE_ADDR + 0x110) 59 #define RDC_SHADOW_DATA (RDC_BASE_ADDR + 0x118) 60 #define RDC_SHADOW_PAR_DATA (RDC_BASE_ADDR + 0x120) 61 #define RDC_CTRL_FIFO_CMD (RDC_BASE_ADDR + 0x128) 62 #define RDC_CTRL_FIFO_DATA_LO (RDC_BASE_ADDR + 0x130) 63 #define RDC_CTRL_FIFO_DATA_HI (RDC_BASE_ADDR + 0x138) 64 #define RDC_CTRL_FIFO_DATA_ECC (RDC_BASE_ADDR + 0x140) 65 #define RDC_DATA_FIFO_CMD (RDC_BASE_ADDR + 0x148) 66 #define RDC_DATA_FIFO_DATA_LO (RDC_BASE_ADDR + 0x150) 67 #define RDC_DATA_FIFO_DATA_HI (RDC_BASE_ADDR + 0x158) 68 #define RDC_DATA_FIFO_DATA_ECC (RDC_BASE_ADDR + 0x160) 69 #define RDC_STAT_INT_DBG (RDC_BASE_ADDR + 0x200) 70 #define RDC_PREF_PAR_LOG (RDC_BASE_ADDR + 0x210) 71 #define RDC_SHADOW_PAR_LOG (RDC_BASE_ADDR + 0x218) 72 #define RDC_CTRL_FIFO_ECC_LOG (RDC_BASE_ADDR + 0x220) 73 #define RDC_DATA_FIFO_ECC_LOG (RDC_BASE_ADDR + 0x228) 74 #define RDC_FIFO_ERR_INT_MASK (RDC_BASE_ADDR + 0x230) 75 #define RDC_FIFO_ERR_STAT (RDC_BASE_ADDR + 0x238) 76 #define RDC_FIFO_ERR_INT_DBG (RDC_BASE_ADDR + 0x240) 77 #define RDC_PEU_TXN_LOG (RDC_BASE_ADDR + 0x250) 78 #define RDC_DBG_TRAINING_VEC (RDC_BASE_ADDR + 0x300) 79 #define RDC_DBG_GRP_SEL (RDC_BASE_ADDR + 0x308) 80 81 82 /* 83 * Register: RdcPageHandle 84 * Logical Page Handle 85 * Description: Logical page handle specifying upper bits of 64-bit 86 * PCIE addresses. Fields in this register are part of the dma 87 * configuration and cannot be changed once the dma is enabled. 88 * Fields: 89 * Bits [63:44] of a 64-bit address, used to concatenate to a 90 * 44-bit address when generating 64-bit addresses on the PCIE 91 * bus. 92 */ 93 typedef union { 94 uint64_t value; 95 struct { 96 #if defined(_BIG_ENDIAN) 97 uint64_t rsrvd:44; 98 uint64_t handle:20; 99 #else 100 uint64_t handle:20; 101 uint64_t rsrvd:44; 102 #endif 103 } bits; 104 } rdc_page_handle_t; 105 106 107 /* 108 * Register: RdcRxCfg1 109 * DMA Configuration 1 110 * Description: Configuration parameters for receive DMA block. 111 * Fields in this register are part of the dma configuration and 112 * cannot be changed once the dma is enabled. 113 * The usage of enable, reset, and qst is as follows. Software 114 * should use the following sequence to reset a DMA channel. First, 115 * set DMA.enable to 0, wait for DMA.qst=1 and then, set DMA.reset to 116 * 1. After DMA.reset is cleared by hardware and the DMA.qst is set 117 * to 1, software may then start configuring the DMA channel. The 118 * DMA.enable can be set or cleared while the DMA is in operation. 119 * The state machines of the DMA may not have returned to its initial 120 * states yet after the DMA.enable bit is cleared. This condition is 121 * indicated by the value of the DMA.qst. An example of DMA.enable 122 * being cleared during operation is when a fatal error occurs. 123 * Fields: 124 * Set to 1 to enable the Receive DMA. If set to 0, packets 125 * selecting this DMA will be discarded. On fatal errors, this 126 * bit will be cleared by hardware. This bit cannot be set if sw 127 * has not resolved any pending fatal error condition: i.e. any 128 * RdcStat ldf1 error bits remain set. 129 * Set to 1 to reset the DMA. Hardware will clear this bit after 130 * reset is completed. A reset will bring the sepecific DMA back 131 * to the power on state (including the DMA.en in this register). 132 * When set to 1, it indicates all state associated with the DMA 133 * are in its initial state following either dma reset or 134 * disable. Thus, once this is set to 1, sw could start to 135 * configure the DMA if needed. 136 * Bits [43:32] of the Mailbox address. 137 */ 138 typedef union { 139 uint64_t value; 140 struct { 141 #if defined(_BIG_ENDIAN) 142 uint64_t rsrvd:32; 143 uint64_t enable:1; 144 uint64_t reset:1; 145 uint64_t qst:1; 146 uint64_t rsrvd1:17; 147 uint64_t mbaddr_h:12; 148 #else 149 uint64_t mbaddr_h:12; 150 uint64_t rsrvd1:17; 151 uint64_t qst:1; 152 uint64_t reset:1; 153 uint64_t enable:1; 154 uint64_t rsrvd:32; 155 #endif 156 } bits; 157 } rdc_rx_cfg1_t; 158 159 160 /* 161 * Register: RdcRxCfg2 162 * DMA Configuration 2 163 * Description: Configuration parameters for receive DMA block. 164 * Fields in this register are part of the dma configuration and 165 * cannot be changed once the dma is enabled. 166 * Fields: 167 * Bits [31:6] of the Mailbox address. Bits [5:0] are assumed to 168 * be zero, or 64B aligned. 169 * Multiple of 64Bs, 0 means no offset, b01 means 64B, b10 means 170 * 128B. b11 is invalid, hardware behavior not specified. 171 * Set to 1 to select the entire header of 6B. 172 */ 173 typedef union { 174 uint64_t value; 175 struct { 176 #if defined(_BIG_ENDIAN) 177 uint64_t rsrvd:32; 178 uint64_t mbaddr_l:26; 179 uint64_t rsrvd1:3; 180 uint64_t offset:2; 181 uint64_t full_hdr:1; 182 #else 183 uint64_t full_hdr:1; 184 uint64_t offset:2; 185 uint64_t rsrvd1:3; 186 uint64_t mbaddr_l:26; 187 uint64_t rsrvd:32; 188 #endif 189 } bits; 190 } rdc_rx_cfg2_t; 191 192 193 /* 194 * Register: RdcRbrCfgA 195 * RBR Configuration A 196 * Description: The following registers are used to configure and 197 * manage the RBR. Note that the entire RBR must stay within the 198 * 'page' defined by staddrBase. The behavior of the hardware is 199 * undefined if the last entry is outside of the page (if bits 43:18 200 * of the address of the last entry are different from bits 43:18 of 201 * the base address). Hardware will support wrapping around at the 202 * end of the ring buffer defined by LEN. LEN must be a multiple of 203 * 64. Fields in this register are part of the dma configuration and 204 * cannot be changed once the dma is enabled. 205 * HW does not check for all configuration errors across different 206 * fields. 207 * 208 * Fields: 209 * Bits 15:6 of the maximum number of RBBs in the buffer ring. 210 * Bits 5:0 are hardcoded to zero. The maximum is (2^16 - 64) and 211 * is limited by the staddr value. (len + staddr) should not 212 * exceed (2^16 - 64). 213 * Bits [43:18] of the address for the RBR. This value remains 214 * fixed, and is used as the base address of the ring. All 215 * entries in the ring have this as their upper address bits. 216 * Bits [17:6] of the address of the RBR. staddrBase concatinated 217 * with staddr is the starting address of the RBR. (len + staddr) 218 * should not exceed (2^16 - 64). 219 */ 220 typedef union { 221 uint64_t value; 222 struct { 223 #if defined(_BIG_ENDIAN) 224 uint64_t len:10; 225 uint64_t len_lo:6; 226 uint64_t rsrvd:4; 227 uint64_t staddr_base:26; 228 uint64_t staddr:12; 229 uint64_t rsrvd1:6; 230 #else 231 uint64_t rsrvd1:6; 232 uint64_t staddr:12; 233 uint64_t staddr_base:26; 234 uint64_t rsrvd:4; 235 uint64_t len_lo:6; 236 uint64_t len:10; 237 #endif 238 } bits; 239 } rdc_rbr_cfg_a_t; 240 241 242 /* 243 * Register: RdcRbrCfgB 244 * RBR Configuration B 245 * Description: This register configures the block size, and the 246 * individual packet buffer sizes. The VLD bits of the three block 247 * sizes have to be set to 1 in normal operations. These bits may be 248 * turned off for debug purpose only. Fields in this register are 249 * part of the dma configuration and cannot be changed once the dma 250 * is enabled. 251 * Fields: 252 * Buffer Block Size. b0 - 4K; b1 - 8K. 253 * Set to 1 to indicate SIZE2 is valid, and enable hardware to 254 * allocate buffers of size 2. Always set to 1 in normal 255 * operation. 256 * Size 2 of packet buffer. b0 - 2K; b1 - 4K. 257 * Set to 1 to indicate SIZE1 is valid, and enable hardware to 258 * allocate buffers of size 1. Always set to 1 in normal 259 * operation. 260 * Size 1 of packet buffer. b0 - 1K; b1 - 2K. 261 * Set to 1 to indicate SIZE0 is valid, and enable hardware to 262 * allocate buffers of size 0. Always set to 1 in normal 263 * operation. 264 * Size 0 of packet buffer. b00 - 256; b01 - 512; b10 - 1K; b11 - 265 * reserved. 266 */ 267 typedef union { 268 uint64_t value; 269 struct { 270 #if defined(_BIG_ENDIAN) 271 uint64_t rsrvd:39; 272 uint64_t bksize:1; 273 uint64_t vld2:1; 274 uint64_t rsrvd1:6; 275 uint64_t bufsz2:1; 276 uint64_t vld1:1; 277 uint64_t rsrvd2:6; 278 uint64_t bufsz1:1; 279 uint64_t vld0:1; 280 uint64_t rsrvd3:5; 281 uint64_t bufsz0:2; 282 #else 283 uint64_t bufsz0:2; 284 uint64_t rsrvd3:5; 285 uint64_t vld0:1; 286 uint64_t bufsz1:1; 287 uint64_t rsrvd2:6; 288 uint64_t vld1:1; 289 uint64_t bufsz2:1; 290 uint64_t rsrvd1:6; 291 uint64_t vld2:1; 292 uint64_t bksize:1; 293 uint64_t rsrvd:39; 294 #endif 295 } bits; 296 } rdc_rbr_cfg_b_t; 297 298 299 /* 300 * Register: RdcRbrKick 301 * RBR Kick 302 * Description: Block buffer addresses are added to the ring buffer 303 * by software. When software writes to the Kick register, indicating 304 * the number of descriptors added, hardware will update the internal 305 * state of the corresponding buffer pool. 306 * HW does not check for all configuration errors across different 307 * fields. 308 * 309 * Fields: 310 * Number of Block Buffers added by software. Hardware effect 311 * will be triggered when the register is written to. 312 */ 313 typedef union { 314 uint64_t value; 315 struct { 316 #if defined(_BIG_ENDIAN) 317 uint64_t rsrvd:48; 318 uint64_t bkadd:16; 319 #else 320 uint64_t bkadd:16; 321 uint64_t rsrvd:48; 322 #endif 323 } bits; 324 } rdc_rbr_kick_t; 325 326 327 /* 328 * Register: RdcRbrQlen 329 * RBR Queue Length 330 * Description: The current number of entries in the RBR. 331 * Fields: 332 * Number of block addresses in the ring buffer. 333 */ 334 typedef union { 335 uint64_t value; 336 struct { 337 #if defined(_BIG_ENDIAN) 338 uint64_t rsrvd:48; 339 uint64_t qlen:16; 340 #else 341 uint64_t qlen:16; 342 uint64_t rsrvd:48; 343 #endif 344 } bits; 345 } rdc_rbr_qlen_t; 346 347 348 /* 349 * Register: RdcRbrHead 350 * RBR Head 351 * Description: Lower bits of the RBR head pointer. Software programs 352 * the upper bits, specified in rdcRbrConfigA.staddrBase. 353 * Fields: 354 * Bits [17:2] of the software posted address, 4B aligned. This 355 * pointer is updated by hardware after each block buffer is 356 * consumed. 357 */ 358 typedef union { 359 uint64_t value; 360 struct { 361 #if defined(_BIG_ENDIAN) 362 uint64_t rsrvd:46; 363 uint64_t head:16; 364 uint64_t rsrvd1:2; 365 #else 366 uint64_t rsrvd1:2; 367 uint64_t head:16; 368 uint64_t rsrvd:46; 369 #endif 370 } bits; 371 } rdc_rbr_head_t; 372 373 374 /* 375 * Register: RdcRcrCfgA 376 * RCR Configuration A 377 * Description: The RCR should be within the 'page' defined by the 378 * staddrBase, i.e. staddrBase concatenate with STADDR plus 8 x LEN 379 * should be within the last address of the 'page' defined by 380 * staddrBase. The length must be a multiple of 32. Fields in this 381 * register are part of the dma configuration and cannot be changed 382 * once the dma is enabled. 383 * HW does not check for all configuration errors across different 384 * fields. 385 * 386 * Fields: 387 * Bits 15:5 of the maximum number of 8B entries in RCR. Bits 4:0 388 * are hard-coded to zero. The maximum size is (2^16 - 32) and is 389 * limited by staddr value. (len + staddr) should not exceed 390 * (2^16 - 32). 391 * Bits [43:19] of the Start address for the RCR. 392 * Bits [18:6] of start address for the RCR. (len + staddr) 393 * should not exceed (2^16 - 32). 394 */ 395 typedef union { 396 uint64_t value; 397 struct { 398 #if defined(_BIG_ENDIAN) 399 uint64_t len:11; 400 uint64_t len_lo:5; 401 uint64_t rsrvd:4; 402 uint64_t staddr_base:25; 403 uint64_t staddr:13; 404 uint64_t rsrvd1:6; 405 #else 406 uint64_t rsrvd1:6; 407 uint64_t staddr:13; 408 uint64_t staddr_base:25; 409 uint64_t rsrvd:4; 410 uint64_t len_lo:5; 411 uint64_t len:11; 412 #endif 413 } bits; 414 } rdc_rcr_cfg_a_t; 415 416 417 /* 418 * Register: RdcRcrCfgB 419 * RCR Configuration B 420 * Description: RCR configuration settings. 421 * Fields: 422 * Packet Threshold; when the number of packets enqueued in RCR 423 * is strictly larger than PTHRES, the DMA MAY issue an interrupt 424 * if enabled. 425 * Enable timeout. If set to one, enable the timeout. A timeout 426 * will initiate an update of the software visible states. If 427 * interrupt is armed, in addition to the update, an interrupt to 428 * CPU will be generated, and the interrupt disarmed. 429 * Time out value. The system clock is divided down by the value 430 * programmed in the Receive DMA Clock Divider register. 431 */ 432 typedef union { 433 uint64_t value; 434 struct { 435 #if defined(_BIG_ENDIAN) 436 uint64_t rsrvd:32; 437 uint64_t pthres:16; 438 uint64_t entout:1; 439 uint64_t rsrvd1:9; 440 uint64_t timeout:6; 441 #else 442 uint64_t timeout:6; 443 uint64_t rsrvd1:9; 444 uint64_t entout:1; 445 uint64_t pthres:16; 446 uint64_t rsrvd:32; 447 #endif 448 } bits; 449 } rdc_rcr_cfg_b_t; 450 451 452 /* 453 * Register: RdcRcrQlen 454 * RCR Queue Length 455 * Description: The number of entries in the RCR. 456 * Fields: 457 * Number of packets queued. Initialize to zero after the RCR 458 * Configuration A register is written to. 459 */ 460 typedef union { 461 uint64_t value; 462 struct { 463 #if defined(_BIG_ENDIAN) 464 uint64_t rsrvd:48; 465 uint64_t qlen:16; 466 #else 467 uint64_t qlen:16; 468 uint64_t rsrvd:48; 469 #endif 470 } bits; 471 } rdc_rcr_qlen_t; 472 473 474 /* 475 * Register: RdcRcrTail 476 * RCR Tail 477 * Description: Lower bits of the RCR tail pointer. Software programs 478 * the upper bits, specified in rdcRcrConfigA.staddrBase. 479 * Fields: 480 * Address of the RCR Tail Pointer [18:3] (points to the next 481 * available location.) Initialized after the RCR Configuration A 482 * register is written to. 483 */ 484 typedef union { 485 uint64_t value; 486 struct { 487 #if defined(_BIG_ENDIAN) 488 uint64_t rsrvd:45; 489 uint64_t tail:16; 490 uint64_t rsrvd1:3; 491 #else 492 uint64_t rsrvd1:3; 493 uint64_t tail:16; 494 uint64_t rsrvd:45; 495 #endif 496 } bits; 497 } rdc_rcr_tail_t; 498 499 500 /* 501 * Register: RdcRcrFlush 502 * RCR Flush 503 * Description: This register will force an update to the RCR in 504 * system memory. 505 * Fields: 506 * Set to 1 to force the hardware to store the shadow tail block 507 * to DRAM if the hardware state (queue length and pointers) is 508 * different from the software visible state. Reset to 0 by 509 * hardware when done. 510 */ 511 typedef union { 512 uint64_t value; 513 struct { 514 #if defined(_BIG_ENDIAN) 515 uint64_t rsrvd:63; 516 uint64_t flush:1; 517 #else 518 uint64_t flush:1; 519 uint64_t rsrvd:63; 520 #endif 521 } bits; 522 } rdc_rcr_flush_t; 523 524 525 /* 526 * Register: RdcClockDiv 527 * Receive DMA Clock Divider 528 * Description: The granularity of the DMA timers is determined by 529 * the following counter. This is used to drive the DMA timeout 530 * counters. For a 250MHz system clock, a value of 25000 (decimal) 531 * will yield a granularity of 100 usec. 532 * Fields: 533 * System clock divider, determines the granularity of the DMA 534 * timeout count-down. The hardware count down is count+1. 535 */ 536 typedef union { 537 uint64_t value; 538 struct { 539 #if defined(_BIG_ENDIAN) 540 uint64_t rsrvd:48; 541 uint64_t count:16; 542 #else 543 uint64_t count:16; 544 uint64_t rsrvd:48; 545 #endif 546 } bits; 547 } rdc_clock_div_t; 548 549 550 /* 551 * Register: RdcIntMask 552 * RDC Interrupt Mask 553 * Description: RDC interrupt status register. RCRTHRES and RCRTO 554 * bits are used to keep track of normal DMA operations, while the 555 * remaining bits are primarily used to detect error conditions. 556 * Fields: 557 * Set to 0 to enable flagging when rdc receives a response 558 * completion timeout from peu. Part of LDF 1. 559 * Set to 1 to enable flagging when rdc receives a poisoned 560 * completion or non-zero (unsuccessful) completion status 561 * received from PEU. Part of LDF 1. 562 * Set to 0 to enable flagging when RCR threshold crossed. Part 563 * of LDF 0. 564 * Set to 0 to enable flagging when RCR timeout. Part of LDF 0. 565 * Set to 0 to enable flagging when read from rcr shadow ram 566 * generates a parity error Part of LDF 1. 567 * Set to 0 to enable flagging when read from rbr prefetch ram 568 * generates a parity error Part of LDF 1. 569 * Set to 0 to enable flagging when Receive Block Ring prefetch 570 * is empty (not enough buffer blocks available depending on 571 * incoming pkt size) when hardware tries to queue a packet. 572 * Incoming packets will be discarded. Non-fatal error. Part of 573 * LDF 1. 574 * Set to 0 to enable flagging when packet discard because of RCR 575 * shadow full. 576 * Set to 0 to enable flagging when Receive Completion Ring full 577 * when hardware tries to enqueue the completion status of a 578 * packet. Part of LDF 1. 579 * Set to 0 to enable flagging when RBR empty when hardware 580 * attempts to prefetch. Part of LDF 1. 581 * Set to 0 to enable flagging when Receive Block Ring full when 582 * software tries to post more blocks. Part of LDF 1. 583 */ 584 typedef union { 585 uint64_t value; 586 struct { 587 #if defined(_BIG_ENDIAN) 588 uint64_t rsrvd:10; 589 uint64_t rbr_cpl_to:1; 590 uint64_t peu_resp_err:1; 591 uint64_t rsrvd1:5; 592 uint64_t rcr_thres:1; 593 uint64_t rcr_to:1; 594 uint64_t rcr_shadow_par_err:1; 595 uint64_t rbr_prefetch_par_err:1; 596 uint64_t rsrvd2:2; 597 uint64_t rbr_pre_empty:1; 598 uint64_t rcr_shadow_full:1; 599 uint64_t rsrvd3:2; 600 uint64_t rcr_full:1; 601 uint64_t rbr_empty:1; 602 uint64_t rbr_full:1; 603 uint64_t rsrvd4:2; 604 uint64_t rsrvd5:32; 605 #else 606 uint64_t rsrvd5:32; 607 uint64_t rsrvd4:2; 608 uint64_t rbr_full:1; 609 uint64_t rbr_empty:1; 610 uint64_t rcr_full:1; 611 uint64_t rsrvd3:2; 612 uint64_t rcr_shadow_full:1; 613 uint64_t rbr_pre_empty:1; 614 uint64_t rsrvd2:2; 615 uint64_t rbr_prefetch_par_err:1; 616 uint64_t rcr_shadow_par_err:1; 617 uint64_t rcr_to:1; 618 uint64_t rcr_thres:1; 619 uint64_t rsrvd1:5; 620 uint64_t peu_resp_err:1; 621 uint64_t rbr_cpl_to:1; 622 uint64_t rsrvd:10; 623 #endif 624 } bits; 625 } rdc_int_mask_t; 626 627 628 /* 629 * Register: RdcStat 630 * RDC Control And Status 631 * Description: The DMA channels are controlled using this register. 632 * Fields: 633 * Set to 1 to indicate rdc received a response completion 634 * timeout from peu. Fatal error. Part of LDF 1. 635 * Set to 1 to indicate poisoned completion or non-zero 636 * (unsuccessful) completion status received from PEU. Part of 637 * LDF 1. 638 * Set to 1 to enable mailbox update. Hardware will reset to 0 639 * after one update. Software needs to set to 1 for each update. 640 * Write 0 has no effect. Note that once set by software, only 641 * hardware can reset the value. This bit is also used to keep 642 * track of the exclusivity between threshold triggered or 643 * timeout triggered interrupt. If this bit is not set, there 644 * will be no timer based interrupt, and threshold based 645 * interrupt will not issue a mailbox update. It is recommended 646 * that software should set this bit to one when arming the 647 * device for interrupt. 648 * Set to 1 to indicate RCR threshold crossed. This is a level 649 * event. Part of LDF 0. 650 * Set to 1 to indicate RCR time-outed if MEX bit is set and the 651 * queue length is non-zero when timeout occurs. When software 652 * writes 1 to this bit, RCRTO will be reset to 0. Part of LDF 0. 653 * Set to 1 to indicate read from rcr shadow ram generates a 654 * parity error Writing a 1 to this register also clears the 655 * rdcshadowParLog register Fatal error. Part of LDF 1. 656 * Set to 1 to indicate read from rbr prefetch ram generates 657 * parity error Writing a 1 to this register also clears the 658 * rdcPrefParLog register Fatal error. Part of LDF 1. 659 * Set to 1 to indicate Receive Block Ring prefetch is empty (not 660 * enough buffer blocks available depending on incoming pkt size) 661 * when hardware tries to queue a packet. Incoming packets will 662 * be discarded. Non-fatal error. Part of LDF 1. 663 * Set to 1 to indicate packet discard because of RCR shadow 664 * full. RCR Shadow full cannot be set to 1 in a normal 665 * operation. When set to 1, it indicates a fatal error. Part of 666 * LDF 1. 667 * Set to 1 to indicate Receive Completion Ring full when 668 * hardware tries to enqueue the completion status of a packet. 669 * Incoming packets will be discarded. No buffer consumed. Fatal 670 * error. Part of LDF 1. 671 * Set to 1 to indicate RBR empty when hardware attempts to 672 * prefetch. Part of LDF 1. 673 * Set to 1 to indicate Receive Buffer Ring full when software 674 * writes the kick register with a value greater than the length 675 * of the RBR length. Incoming packets will be discarded. Fatal 676 * error. Part of LDF 1. 677 * Number of buffer pointers read. Used to advance the RCR head 678 * pointer. 679 * Number of packets read; when written to, decrement the QLEN 680 * counter by PKTREAD. QLEN is lower bounded to zero. 681 */ 682 typedef union { 683 uint64_t value; 684 struct { 685 #if defined(_BIG_ENDIAN) 686 uint64_t rsrvd:10; 687 uint64_t rbr_cpl_to:1; 688 uint64_t peu_resp_err:1; 689 uint64_t rsrvd1:4; 690 uint64_t mex:1; 691 uint64_t rcr_thres:1; 692 uint64_t rcr_to:1; 693 uint64_t rcr_shadow_par_err:1; 694 uint64_t rbr_prefetch_par_err:1; 695 uint64_t rsrvd2:2; 696 uint64_t rbr_pre_empty:1; 697 uint64_t rcr_shadow_full:1; 698 uint64_t rsrvd3:2; 699 uint64_t rcr_full:1; 700 uint64_t rbr_empty:1; 701 uint64_t rbr_full:1; 702 uint64_t rsrvd4:2; 703 uint64_t ptrread:16; 704 uint64_t pktread:16; 705 #else 706 uint64_t pktread:16; 707 uint64_t ptrread:16; 708 uint64_t rsrvd4:2; 709 uint64_t rbr_full:1; 710 uint64_t rbr_empty:1; 711 uint64_t rcr_full:1; 712 uint64_t rsrvd3:2; 713 uint64_t rcr_shadow_full:1; 714 uint64_t rbr_pre_empty:1; 715 uint64_t rsrvd2:2; 716 uint64_t rbr_prefetch_par_err:1; 717 uint64_t rcr_shadow_par_err:1; 718 uint64_t rcr_to:1; 719 uint64_t rcr_thres:1; 720 uint64_t mex:1; 721 uint64_t rsrvd1:4; 722 uint64_t peu_resp_err:1; 723 uint64_t rbr_cpl_to:1; 724 uint64_t rsrvd:10; 725 #endif 726 } bits; 727 } rdc_stat_t; 728 729 730 /* 731 * Register: RdcPktCount 732 * Rx DMA Packet Counter 733 * Description: Counts the number of packets received from the Rx 734 * Virtual MAC for this DMA channel. 735 * Fields: 736 * Count of SYN packets received from RVM. This counter 737 * saturates. 738 * Count of packets received from RVM. This counter saturates. 739 */ 740 typedef union { 741 uint64_t value; 742 struct { 743 #if defined(_BIG_ENDIAN) 744 uint64_t syn_pkt_count:32; 745 uint64_t pkt_count:32; 746 #else 747 uint64_t pkt_count:32; 748 uint64_t syn_pkt_count:32; 749 #endif 750 } bits; 751 } rdc_pkt_count_t; 752 753 754 /* 755 * Register: RdcDropCount 756 * Rx DMA Dropped Packet Counters 757 * Description: Counts the number of packets dropped due to different 758 * types of errors. 759 * Fields: 760 * Count of packets dropped because they were longer than the 761 * maximum length. This counter saturates. 762 * Count of packets dropped because there was no block available 763 * in the RBR Prefetch Buffer. This counter saturates. 764 * Count of packets dropped because the RVM marked the packet as 765 * errored. This counter saturates. 766 * Count of packets dropped because there was a framing error 767 * from the RVM. This counter saturates. 768 * Count of packets dropped because the packet did not fit in the 769 * rx ram. This counter saturates. 770 */ 771 typedef union { 772 uint64_t value; 773 struct { 774 #if defined(_BIG_ENDIAN) 775 uint64_t rsrvd:16; 776 uint64_t too_long:8; 777 uint64_t no_rbr_avail:8; 778 uint64_t rvm_error:8; 779 uint64_t frame_error:8; 780 uint64_t rxram_error:8; 781 uint64_t rsrvd1:8; 782 #else 783 uint64_t rsrvd1:8; 784 uint64_t rxram_error:8; 785 uint64_t frame_error:8; 786 uint64_t rvm_error:8; 787 uint64_t no_rbr_avail:8; 788 uint64_t too_long:8; 789 uint64_t rsrvd:16; 790 #endif 791 } bits; 792 } rdc_drop_count_t; 793 794 795 /* 796 * Register: RdcByteCount 797 * Rx DMA Byte Counter 798 * Description: Counts the number of bytes transferred by dma for all 799 * channels. 800 * Fields: 801 * Count of bytes transferred by dma. This counter saturates. 802 */ 803 typedef union { 804 uint64_t value; 805 struct { 806 #if defined(_BIG_ENDIAN) 807 uint64_t rsrvd:32; 808 uint64_t count:32; 809 #else 810 uint64_t count:32; 811 uint64_t rsrvd:32; 812 #endif 813 } bits; 814 } rdc_byte_count_t; 815 816 817 /* 818 * Register: RdcPrefCmd 819 * Rx DMA Prefetch Buffer Command 820 * Description: Allows debug access to the entire prefetch buffer, 821 * along with the rdcPrefData register. Writing the rdcPrefCmd 822 * triggers the access. For writes, software writes the 32 bits of 823 * data to the rdcPrefData register before writing the write command 824 * to this register. For reads, software first writes the the read 825 * command to this register, then reads the 32-bit value from the 826 * rdcPrefData register. The status field should be polled by 827 * software until it goes low, indicating the read or write has 828 * completed. 829 * Fields: 830 * status of indirect access 0=busy 1=done 831 * Command type. 1 indicates a read command, 0 a write command. 832 * enable writing of parity bits 1=enabled, 0=disabled 833 * DMA channel of entry to read or write 834 * Entry in the prefetch buffer to read or write 835 */ 836 typedef union { 837 uint64_t value; 838 struct { 839 #if defined(_BIG_ENDIAN) 840 uint64_t rsrvd:32; 841 uint64_t status:1; 842 uint64_t cmd:1; 843 uint64_t par_en:1; 844 uint64_t rsrvd1:22; 845 uint64_t dmc:2; 846 uint64_t entry:5; 847 #else 848 uint64_t entry:5; 849 uint64_t dmc:2; 850 uint64_t rsrvd1:22; 851 uint64_t par_en:1; 852 uint64_t cmd:1; 853 uint64_t status:1; 854 uint64_t rsrvd:32; 855 #endif 856 } bits; 857 } rdc_pref_cmd_t; 858 859 860 /* 861 * Register: RdcPrefData 862 * Rx DMA Prefetch Buffer Data 863 * Description: See rdcPrefCmd register. 864 * Fields: 865 * For writes, parity bits is written into prefetch buffer. For 866 * reads, parity bits read from the prefetch buffer. 867 * For writes, data which is written into prefetch buffer. For 868 * reads, data read from the prefetch buffer. 869 */ 870 typedef union { 871 uint64_t value; 872 struct { 873 #if defined(_BIG_ENDIAN) 874 uint64_t rsrvd:28; 875 uint64_t par:4; 876 uint64_t data:32; 877 #else 878 uint64_t data:32; 879 uint64_t par:4; 880 uint64_t rsrvd:28; 881 #endif 882 } bits; 883 } rdc_pref_data_t; 884 885 886 /* 887 * Register: RdcShadowCmd 888 * Rx DMA Shadow Tail Command 889 * Description: Allows debug access to the entire shadow tail, along 890 * with the rdcShadowData register. Writing the rdcShadowCmd triggers 891 * the access. For writes, software writes the 64 bits of data to the 892 * rdcShadowData register before writing the write command to this 893 * register. For reads, software first writes the the read command to 894 * this register, then reads the 64-bit value from the rdcShadowData 895 * register. The valid field should be polled by software until it 896 * goes low, indicating the read or write has completed. 897 * Fields: 898 * status of indirect access 0=busy 1=done 899 * Command type. 1 indicates a read command, 0 a write command. 900 * enable writing of parity bits 1=enabled, 0=disabled 901 * DMA channel of entry to read or write 902 * Entry in the shadow tail to read or write 903 */ 904 typedef union { 905 uint64_t value; 906 struct { 907 #if defined(_BIG_ENDIAN) 908 uint64_t rsrvd:32; 909 uint64_t status:1; 910 uint64_t cmd:1; 911 uint64_t par_en:1; 912 uint64_t rsrvd1:23; 913 uint64_t dmc:2; 914 uint64_t entry:4; 915 #else 916 uint64_t entry:4; 917 uint64_t dmc:2; 918 uint64_t rsrvd1:23; 919 uint64_t par_en:1; 920 uint64_t cmd:1; 921 uint64_t status:1; 922 uint64_t rsrvd:32; 923 #endif 924 } bits; 925 } rdc_shadow_cmd_t; 926 927 928 /* 929 * Register: RdcShadowData 930 * Rx DMA Shadow Tail Data 931 * Description: See rdcShadowCmd register. 932 * Fields: 933 * For writes, data which is written into shadow tail. For reads, 934 * data read from the shadow tail. 935 */ 936 typedef union { 937 uint64_t value; 938 struct { 939 #if defined(_BIG_ENDIAN) 940 uint64_t data:64; 941 #else 942 uint64_t data:64; 943 #endif 944 } bits; 945 } rdc_shadow_data_t; 946 947 948 /* 949 * Register: RdcShadowParData 950 * Rx DMA Shadow Tail Parity Data 951 * Description: See rdcShadowCmd register. 952 * Fields: 953 * For writes, parity data is written into shadow tail. For 954 * reads, parity data read from the shadow tail. 955 */ 956 typedef union { 957 uint64_t value; 958 struct { 959 #if defined(_BIG_ENDIAN) 960 uint64_t rsrvd:32; 961 uint64_t rsrvd1:24; 962 uint64_t parity_data:8; 963 #else 964 uint64_t parity_data:8; 965 uint64_t rsrvd1:24; 966 uint64_t rsrvd:32; 967 #endif 968 } bits; 969 } rdc_shadow_par_data_t; 970 971 972 /* 973 * Register: RdcCtrlFifoCmd 974 * Rx DMA Control Fifo Command 975 * Description: Allows debug access to the entire Rx Ctl FIFO, along 976 * with the rdcCtrlFifoData register. Writing the rdcCtrlFifoCmd 977 * triggers the access. For writes, software writes the 128 bits of 978 * data to the rdcCtrlFifoData registers before writing the write 979 * command to this register. For reads, software first writes the the 980 * read command to this register, then reads the 128-bit value from 981 * the rdcCtrlFifoData registers. The valid field should be polled by 982 * software until it goes low, indicating the read or write has 983 * completed. 984 * Fields: 985 * status of indirect access 0=busy 1=done 986 * Command type. 1 indicates a read command, 0 a write command. 987 * enable writing of ECC bits 1=enabled, 0=disabled 988 * Entry in the rx control ram to read or write 989 */ 990 typedef union { 991 uint64_t value; 992 struct { 993 #if defined(_BIG_ENDIAN) 994 uint64_t rsrvd:32; 995 uint64_t status:1; 996 uint64_t cmd:1; 997 uint64_t ecc_en:1; 998 uint64_t rsrvd1:20; 999 uint64_t entry:9; 1000 #else 1001 uint64_t entry:9; 1002 uint64_t rsrvd1:20; 1003 uint64_t ecc_en:1; 1004 uint64_t cmd:1; 1005 uint64_t status:1; 1006 uint64_t rsrvd:32; 1007 #endif 1008 } bits; 1009 } rdc_ctrl_fifo_cmd_t; 1010 1011 1012 /* 1013 * Register: RdcCtrlFifoDataLo 1014 * Rx DMA Control Fifo Data Lo 1015 * Description: Lower 64 bits read or written to the Rx Ctl FIFO. See 1016 * rdcCtrlFifoCmd register. 1017 * Fields: 1018 * For writes, data which is written into rx control ram. For 1019 * reads, data read from the rx control ram. 1020 */ 1021 typedef union { 1022 uint64_t value; 1023 struct { 1024 #if defined(_BIG_ENDIAN) 1025 uint64_t data:64; 1026 #else 1027 uint64_t data:64; 1028 #endif 1029 } bits; 1030 } rdc_ctrl_fifo_data_lo_t; 1031 1032 1033 /* 1034 * Register: RdcCtrlFifoDataHi 1035 * Rx DMA Control Fifo Data Hi 1036 * Description: Upper 64 bits read or written to the Rx Ctl FIFO. See 1037 * rdcCtrlFifoCmd register. 1038 * Fields: 1039 * For writes, data which is written into rx control ram. For 1040 * reads, data read from the rx control ram. 1041 */ 1042 typedef union { 1043 uint64_t value; 1044 struct { 1045 #if defined(_BIG_ENDIAN) 1046 uint64_t data:64; 1047 #else 1048 uint64_t data:64; 1049 #endif 1050 } bits; 1051 } rdc_ctrl_fifo_data_hi_t; 1052 1053 1054 /* 1055 * Register: RdcCtrlFifoDataEcc 1056 * Rx DMA Control Fifo Data ECC 1057 * Description: 16 bits ECC data read or written to the Rx Ctl FIFO. 1058 * See rdcCtrlFifoCmd register. 1059 * Fields: 1060 * For writes, data which is written into rx control ram. For 1061 * reads, data read from the rx control ram. 1062 * For writes, data which is written into rx control ram. For 1063 * reads, data read from the rx control ram. 1064 */ 1065 typedef union { 1066 uint64_t value; 1067 struct { 1068 #if defined(_BIG_ENDIAN) 1069 uint64_t rsrvd:32; 1070 uint64_t rsrvd1:16; 1071 uint64_t ecc_data_hi:8; 1072 uint64_t ecc_data_lo:8; 1073 #else 1074 uint64_t ecc_data_lo:8; 1075 uint64_t ecc_data_hi:8; 1076 uint64_t rsrvd1:16; 1077 uint64_t rsrvd:32; 1078 #endif 1079 } bits; 1080 } rdc_ctrl_fifo_data_ecc_t; 1081 1082 1083 /* 1084 * Register: RdcDataFifoCmd 1085 * Rx DMA Data Fifo Command 1086 * Description: Allows debug access to the entire Rx Data FIFO, along 1087 * with the rdcDataFifoData register. Writing the rdcCtrlFifoCmd 1088 * triggers the access. For writes, software writes the 128 bits of 1089 * data to the rdcDataFifoData registers before writing the write 1090 * command to this register. For reads, software first writes the the 1091 * read command to this register, then reads the 128-bit value from 1092 * the rdcDataFifoData registers. The valid field should be polled by 1093 * software until it goes low, indicating the read or write has 1094 * completed. 1095 * Fields: 1096 * status of indirect access 0=busy 1=done 1097 * Command type. 1 indicates a read command, 0 a write command. 1098 * enable writing of ECC bits 1=enabled, 0=disabled 1099 * Entry in the rx data ram to read or write 1100 */ 1101 typedef union { 1102 uint64_t value; 1103 struct { 1104 #if defined(_BIG_ENDIAN) 1105 uint64_t rsrvd:32; 1106 uint64_t status:1; 1107 uint64_t cmd:1; 1108 uint64_t ecc_en:1; 1109 uint64_t rsrvd1:18; 1110 uint64_t entry:11; 1111 #else 1112 uint64_t entry:11; 1113 uint64_t rsrvd1:18; 1114 uint64_t ecc_en:1; 1115 uint64_t cmd:1; 1116 uint64_t status:1; 1117 uint64_t rsrvd:32; 1118 #endif 1119 } bits; 1120 } rdc_data_fifo_cmd_t; 1121 1122 1123 /* 1124 * Register: RdcDataFifoDataLo 1125 * Rx DMA Data Fifo Data Lo 1126 * Description: Lower 64 bits read or written to the Rx Data FIFO. 1127 * See rdcDataFifoCmd register. 1128 * Fields: 1129 * For writes, data which is written into rx data ram. For reads, 1130 * data read from the rx data ram. 1131 */ 1132 typedef union { 1133 uint64_t value; 1134 struct { 1135 #if defined(_BIG_ENDIAN) 1136 uint64_t data:64; 1137 #else 1138 uint64_t data:64; 1139 #endif 1140 } bits; 1141 } rdc_data_fifo_data_lo_t; 1142 1143 1144 /* 1145 * Register: RdcDataFifoDataHi 1146 * Rx DMA Data Fifo Data Hi 1147 * Description: Upper 64 bits read or written to the Rx Data FIFO. 1148 * See rdcDataFifoCmd register. 1149 * Fields: 1150 * For writes, data which is written into rx data ram. For reads, 1151 * data read from the rx data ram. 1152 */ 1153 typedef union { 1154 uint64_t value; 1155 struct { 1156 #if defined(_BIG_ENDIAN) 1157 uint64_t data:64; 1158 #else 1159 uint64_t data:64; 1160 #endif 1161 } bits; 1162 } rdc_data_fifo_data_hi_t; 1163 1164 1165 /* 1166 * Register: RdcDataFifoDataEcc 1167 * Rx DMA Data Fifo ECC Data 1168 * Description: 16 bits ECC data read or written to the Rx Data FIFO. 1169 * See rdcDataFifoCmd register. 1170 * Fields: 1171 * For writes, data which is written into rx data ram. For reads, 1172 * data read from the rx data ram. 1173 * For writes, data which is written into rx data ram. For reads, 1174 * data read from the rx data ram. 1175 */ 1176 typedef union { 1177 uint64_t value; 1178 struct { 1179 #if defined(_BIG_ENDIAN) 1180 uint64_t rsrvd:32; 1181 uint64_t rsrvd1:16; 1182 uint64_t ecc_data_hi:8; 1183 uint64_t ecc_data_lo:8; 1184 #else 1185 uint64_t ecc_data_lo:8; 1186 uint64_t ecc_data_hi:8; 1187 uint64_t rsrvd1:16; 1188 uint64_t rsrvd:32; 1189 #endif 1190 } bits; 1191 } rdc_data_fifo_data_ecc_t; 1192 1193 1194 /* 1195 * Register: RdcStatIntDbg 1196 * RDC Debug Control and Status Interrupt 1197 * Description: RDC debug control and status interrupt register. 1198 * Debug RDC control and status register bits to check if interrupt 1199 * is asserted used to detect error conditions. 1200 * Fields: 1201 * Set to 1 to enable interrupt Part of LDF 1. 1202 * Set to 1 to enable interrupt Part of LDF 1. 1203 * Set to 1 to enable interrupt Part of LDF 0. 1204 * Set to 1 to enable interrupt Part of LDF 0. 1205 * Set to 1 to enable interrupt Part of LDF 1. 1206 * Set to 1 to enable interrupt Part of LDF 1. 1207 * Set to 1 to enable interrupt Part of LDF 1. 1208 * Set to 1 to enable interrupt 1209 * Set to 1 to enable interrupt Part of LDF 1. 1210 * Set to 1 to enable interrupt Part of LDF 1. 1211 * Set to 1 to enable interrupt Part of LDF 1. 1212 */ 1213 typedef union { 1214 uint64_t value; 1215 struct { 1216 #if defined(_BIG_ENDIAN) 1217 uint64_t rsrvd:10; 1218 uint64_t rbr_cpl_to:1; 1219 uint64_t peu_resp_err:1; 1220 uint64_t rsrvd1:5; 1221 uint64_t rcr_thres:1; 1222 uint64_t rcr_to:1; 1223 uint64_t rcr_shadow_par_err:1; 1224 uint64_t rbr_prefetch_par_err:1; 1225 uint64_t rsrvd2:2; 1226 uint64_t rbr_pre_empty:1; 1227 uint64_t rcr_shadow_full:1; 1228 uint64_t rsrvd3:2; 1229 uint64_t rcr_full:1; 1230 uint64_t rbr_empty:1; 1231 uint64_t rbr_full:1; 1232 uint64_t rsrvd4:2; 1233 uint64_t rsrvd5:32; 1234 #else 1235 uint64_t rsrvd5:32; 1236 uint64_t rsrvd4:2; 1237 uint64_t rbr_full:1; 1238 uint64_t rbr_empty:1; 1239 uint64_t rcr_full:1; 1240 uint64_t rsrvd3:2; 1241 uint64_t rcr_shadow_full:1; 1242 uint64_t rbr_pre_empty:1; 1243 uint64_t rsrvd2:2; 1244 uint64_t rbr_prefetch_par_err:1; 1245 uint64_t rcr_shadow_par_err:1; 1246 uint64_t rcr_to:1; 1247 uint64_t rcr_thres:1; 1248 uint64_t rsrvd1:5; 1249 uint64_t peu_resp_err:1; 1250 uint64_t rbr_cpl_to:1; 1251 uint64_t rsrvd:10; 1252 #endif 1253 } bits; 1254 } rdc_stat_int_dbg_t; 1255 1256 1257 /* 1258 * Register: RdcPrefParLog 1259 * Rx DMA Prefetch Buffer Parity Log 1260 * Description: RDC DMA Prefetch Buffer parity log register This 1261 * register logs the first parity error that is encountered. Writing 1262 * a 1 to RdcStat::rbrPrefetchParErr clears this register 1263 * Fields: 1264 * Address of parity error 1265 */ 1266 typedef union { 1267 uint64_t value; 1268 struct { 1269 #if defined(_BIG_ENDIAN) 1270 uint64_t rsrvd:57; 1271 uint64_t address:7; 1272 #else 1273 uint64_t address:7; 1274 uint64_t rsrvd:57; 1275 #endif 1276 } bits; 1277 } rdc_pref_par_log_t; 1278 1279 1280 /* 1281 * Register: RdcShadowParLog 1282 * Rx DMA Shadow Tail Parity Log 1283 * Description: RDC DMA Shadow Tail parity log register This register 1284 * logs the first parity error that is encountered. Writing a 1 to 1285 * RdcStat::rcrShadowParErr clears this register 1286 * Fields: 1287 * Address of parity error 1288 */ 1289 typedef union { 1290 uint64_t value; 1291 struct { 1292 #if defined(_BIG_ENDIAN) 1293 uint64_t rsrvd:32; 1294 uint64_t rsrvd1:26; 1295 uint64_t address:6; 1296 #else 1297 uint64_t address:6; 1298 uint64_t rsrvd1:26; 1299 uint64_t rsrvd:32; 1300 #endif 1301 } bits; 1302 } rdc_shadow_par_log_t; 1303 1304 1305 /* 1306 * Register: RdcCtrlFifoEccLog 1307 * Rx DMA Control Fifo ECC Log 1308 * Description: RDC DMA Control FIFO ECC log register This register 1309 * logs the first ECC error that is encountered. A double-bit ecc 1310 * error over writes any single-bit ecc error previously logged 1311 * Fields: 1312 * Address of ECC error for upper 64 bits Writing a 1 to 1313 * RdcFifoErrStat::rxCtrlFifoDed[1] or 1314 * RdcFifoErrStat::rxCtrlFifoSec[1] clears this register 1315 * Address of ECC error for lower 64 bits Writing a 1 to 1316 * RdcFifoErrStat::rxCtrlFifoDed[0] or 1317 * RdcFifoErrStat::rxCtrlFifoSec[0] clears this register 1318 * ECC syndrome for upper 64 bits Writing a 1 to 1319 * RdcFifoErrStat::rxCtrlFifoDed[1] or 1320 * RdcFifoErrStat::rxCtrlFifoSec[1] clears this register 1321 * ECC syndrome for lower 64 bits Writing a 1 to 1322 * RdcFifoErrStat::rxCtrlFifoDed[0] or 1323 * RdcFifoErrStat::rxCtrlFifoSec[0] clears this register 1324 */ 1325 typedef union { 1326 uint64_t value; 1327 struct { 1328 #if defined(_BIG_ENDIAN) 1329 uint64_t rsrvd:7; 1330 uint64_t address_hi:9; 1331 uint64_t rsrvd1:7; 1332 uint64_t address_lo:9; 1333 uint64_t rsrvd2:8; 1334 uint64_t syndrome_hi:8; 1335 uint64_t rsrvd3:8; 1336 uint64_t syndrome_lo:8; 1337 #else 1338 uint64_t syndrome_lo:8; 1339 uint64_t rsrvd3:8; 1340 uint64_t syndrome_hi:8; 1341 uint64_t rsrvd2:8; 1342 uint64_t address_lo:9; 1343 uint64_t rsrvd1:7; 1344 uint64_t address_hi:9; 1345 uint64_t rsrvd:7; 1346 #endif 1347 } bits; 1348 } rdc_ctrl_fifo_ecc_log_t; 1349 1350 1351 /* 1352 * Register: RdcDataFifoEccLog 1353 * Rx DMA Data Fifo ECC Log 1354 * Description: RDC DMA data FIFO ECC log register This register logs 1355 * the first ECC error that is encountered. A double-bit ecc error 1356 * over writes any single-bit ecc error previously logged 1357 * Fields: 1358 * Address of ECC error for upper 64 bits Writing a 1 to 1359 * RdcFifoErrStat::rxDataFifoDed[1] or 1360 * RdcFifoErrStat::rxDataFifoSec[1] clears this register 1361 * Address of ECC error for lower 64 bits Writing a 1 to 1362 * RdcFifoErrStat::rxDataFifoDed[0] or 1363 * RdcFifoErrStat::rxDataFifoSec[0] clears this register 1364 * ECC syndrome for upper 64 bits Writing a 1 to 1365 * RdcFifoErrStat::rxDataFifoDed[1] or 1366 * RdcFifoErrStat::rxDataFifoSec[1] clears this register 1367 * ECC syndrome for lower 64 bits Writing a 1 to 1368 * RdcFifoErrStat::rxDataFifoDed[0] or 1369 * RdcFifoErrStat::rxDataFifoSec[0] clears this register 1370 */ 1371 typedef union { 1372 uint64_t value; 1373 struct { 1374 #if defined(_BIG_ENDIAN) 1375 uint64_t rsrvd:5; 1376 uint64_t address_hi:11; 1377 uint64_t rsrvd1:5; 1378 uint64_t address_lo:11; 1379 uint64_t rsrvd2:8; 1380 uint64_t syndrome_hi:8; 1381 uint64_t rsrvd3:8; 1382 uint64_t syndrome_lo:8; 1383 #else 1384 uint64_t syndrome_lo:8; 1385 uint64_t rsrvd3:8; 1386 uint64_t syndrome_hi:8; 1387 uint64_t rsrvd2:8; 1388 uint64_t address_lo:11; 1389 uint64_t rsrvd1:5; 1390 uint64_t address_hi:11; 1391 uint64_t rsrvd:5; 1392 #endif 1393 } bits; 1394 } rdc_data_fifo_ecc_log_t; 1395 1396 1397 /* 1398 * Register: RdcFifoErrIntMask 1399 * FIFO Error Interrupt Mask 1400 * Description: FIFO Error interrupt mask register. Control the 1401 * interrupt assertion of FIFO Errors. see FIFO Error Status register 1402 * for more description 1403 * Fields: 1404 * Set to 0 to enable flagging when rx ctrl ram logs ecc single 1405 * bit error Part of Device Error 0. 1406 * Set to 0 to enable flagging when rx ctrl ram logs ecc double 1407 * bit error Part of Device Error 1. 1408 * Set to 0 to enable flagging when rx data ram logs ecc single 1409 * bit error Part of Device Error 0. 1410 * Set to 0 to enable flagging when rx data ram logs ecc double 1411 * bit error Part of Device Error 1. 1412 */ 1413 typedef union { 1414 uint64_t value; 1415 struct { 1416 #if defined(_BIG_ENDIAN) 1417 uint64_t rsrvd:32; 1418 uint64_t rsrvd1:24; 1419 uint64_t rx_ctrl_fifo_sec:2; 1420 uint64_t rx_ctrl_fifo_ded:2; 1421 uint64_t rx_data_fifo_sec:2; 1422 uint64_t rx_data_fifo_ded:2; 1423 #else 1424 uint64_t rx_data_fifo_ded:2; 1425 uint64_t rx_data_fifo_sec:2; 1426 uint64_t rx_ctrl_fifo_ded:2; 1427 uint64_t rx_ctrl_fifo_sec:2; 1428 uint64_t rsrvd1:24; 1429 uint64_t rsrvd:32; 1430 #endif 1431 } bits; 1432 } rdc_fifo_err_int_mask_t; 1433 1434 1435 /* 1436 * Register: RdcFifoErrStat 1437 * FIFO Error Status 1438 * Description: FIFO Error Status register. Log status of FIFO 1439 * Errors. Rx Data buffer is physically two seperate memory, each of 1440 * the two error bits point to one of the memory. Each entry in the 1441 * rx ctrl point to 2 buffer locations and they are read seperatly. 1442 * The two error bits point to each half of the entry. 1443 * Fields: 1444 * Set to 1 by HW to indicate rx control ram received a ecc 1445 * single bit error Writing a 1 to either bit clears the 1446 * RdcCtrlFifoEccLog register Non-Fatal error. Part of Device 1447 * Error 0 1448 * Set to 1 by HW to indicate rx control ram received a ecc 1449 * double bit error Writing a 1 to either bit clears the 1450 * RdcCtrlFifoEccLog register Fatal error. Part of Device Error 1 1451 * Set to 1 by HW to indicate rx data ram received a ecc single 1452 * bit error Writing a 1 to either bit clears the 1453 * RdcDataFifoEccLog register Non-Fatal error. Part of Device 1454 * Error 0 1455 * Set to 1 by HW to indicate rx data ram received a ecc double 1456 * bit error Writing a 1 to either bit clears the 1457 * RdcDataFifoEccLog register Fatal error. Part of Device Error 1 1458 */ 1459 typedef union { 1460 uint64_t value; 1461 struct { 1462 #if defined(_BIG_ENDIAN) 1463 uint64_t rsrvd:56; 1464 uint64_t rx_ctrl_fifo_sec:2; 1465 uint64_t rx_ctrl_fifo_ded:2; 1466 uint64_t rx_data_fifo_sec:2; 1467 uint64_t rx_data_fifo_ded:2; 1468 #else 1469 uint64_t rx_data_fifo_ded:2; 1470 uint64_t rx_data_fifo_sec:2; 1471 uint64_t rx_ctrl_fifo_ded:2; 1472 uint64_t rx_ctrl_fifo_sec:2; 1473 uint64_t rsrvd:56; 1474 #endif 1475 } bits; 1476 } rdc_fifo_err_stat_t; 1477 1478 1479 /* 1480 * Register: RdcFifoErrIntDbg 1481 * FIFO Error Interrupt Debug 1482 * Description: FIFO Error interrupt Debug register. Debug Control 1483 * the interrupt assertion of FIFO Errors. 1484 * Fields: 1485 * Set to 1 to enable interrupt Part of Device Error 0. 1486 * Set to 1 to enable interrupt Part of Device Error 1. 1487 * Set to 1 to enable interrupt Part of Device Error 0. 1488 * Set to 1 to enable interrupt Part of Device Error 1. 1489 */ 1490 typedef union { 1491 uint64_t value; 1492 struct { 1493 #if defined(_BIG_ENDIAN) 1494 uint64_t rsrvd:32; 1495 uint64_t rsrvd1:24; 1496 uint64_t rx_ctrl_fifo_sec:2; 1497 uint64_t rx_ctrl_fifo_ded:2; 1498 uint64_t rx_data_fifo_sec:2; 1499 uint64_t rx_data_fifo_ded:2; 1500 #else 1501 uint64_t rx_data_fifo_ded:2; 1502 uint64_t rx_data_fifo_sec:2; 1503 uint64_t rx_ctrl_fifo_ded:2; 1504 uint64_t rx_ctrl_fifo_sec:2; 1505 uint64_t rsrvd1:24; 1506 uint64_t rsrvd:32; 1507 #endif 1508 } bits; 1509 } rdc_fifo_err_int_dbg_t; 1510 1511 1512 /* 1513 * Register: RdcPeuTxnLog 1514 * PEU Transaction Log 1515 * Description: PEU Transaction Log register. Counts the memory read 1516 * and write requests sent to peu block. For debug only. 1517 * Fields: 1518 * Counts the memory write transactions sent to peu block. This 1519 * counter saturates. This counter increments when vnmDbg is on 1520 * Counts the memory read transactions sent to peu block. This 1521 * counter saturates. This counter increments when vnmDbg is on 1522 */ 1523 typedef union { 1524 uint64_t value; 1525 struct { 1526 #if defined(_BIG_ENDIAN) 1527 uint64_t rsrvd:32; 1528 uint64_t rsrvd1:16; 1529 uint64_t peu_mem_wr_count:8; 1530 uint64_t peu_mem_rd_count:8; 1531 #else 1532 uint64_t peu_mem_rd_count:8; 1533 uint64_t peu_mem_wr_count:8; 1534 uint64_t rsrvd1:16; 1535 uint64_t rsrvd:32; 1536 #endif 1537 } bits; 1538 } rdc_peu_txn_log_t; 1539 1540 1541 /* 1542 * Register: RdcDbgTrainingVec 1543 * Debug Training Vector 1544 * Description: Debug Training Vector register Debug Training Vector 1545 * for the coreClk domain. For the pcieClk domain, the dbgxMsb and 1546 * dbgyMsb values are flipped on the debug bus. 1547 * Fields: 1548 * Blade Number, the value read depends on the blade this block 1549 * resides 1550 * debug training vector the sub-group select value of 0 selects 1551 * this vector 1552 * Blade Number, the value read depends on the blade this block 1553 * resides 1554 * debug training vector the sub-group select value of 0 selects 1555 * this vector 1556 */ 1557 typedef union { 1558 uint64_t value; 1559 struct { 1560 #if defined(_BIG_ENDIAN) 1561 uint64_t rsrvd:32; 1562 uint64_t dbgx_msb:1; 1563 uint64_t dbgx_bld_num:3; 1564 uint64_t dbgx_training_vec:12; 1565 uint64_t dbgy_msb:1; 1566 uint64_t dbgy_bld_num:3; 1567 uint64_t dbgy_training_vec:12; 1568 #else 1569 uint64_t dbgy_training_vec:12; 1570 uint64_t dbgy_bld_num:3; 1571 uint64_t dbgy_msb:1; 1572 uint64_t dbgx_training_vec:12; 1573 uint64_t dbgx_bld_num:3; 1574 uint64_t dbgx_msb:1; 1575 uint64_t rsrvd:32; 1576 #endif 1577 } bits; 1578 } rdc_dbg_training_vec_t; 1579 1580 1581 /* 1582 * Register: RdcDbgGrpSel 1583 * Debug Group Select 1584 * Description: Debug Group Select register. Debug Group Select 1585 * register selects the group of signals brought out on the debug 1586 * port 1587 * Fields: 1588 * high 32b sub-group select 1589 * low 32b sub-group select 1590 */ 1591 typedef union { 1592 uint64_t value; 1593 struct { 1594 #if defined(_BIG_ENDIAN) 1595 uint64_t rsrvd:48; 1596 uint64_t dbg_h32_sub_sel:8; 1597 uint64_t dbg_l32_sub_sel:8; 1598 #else 1599 uint64_t dbg_l32_sub_sel:8; 1600 uint64_t dbg_h32_sub_sel:8; 1601 uint64_t rsrvd:48; 1602 #endif 1603 } bits; 1604 } rdc_dbg_grp_sel_t; 1605 1606 1607 #ifdef __cplusplus 1608 } 1609 #endif 1610 1611 #endif /* _HXGE_RDC_HW_H */ 1612